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remove remaining .bsf (schematics) files

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This commit is contained in:
Markus Fröschle
2016-07-29 06:43:24 +00:00
parent 799f41e8d5
commit e0269dc6c9
13 changed files with 0 additions and 1193 deletions
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64
FPGA_Quartus_13.1/altddio_out0.bsf
View File

@@ -1,64 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 232 120)
(text "altddio_out0" (rect 81 1 163 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 104 25 116)(font "Arial" ))
(port
(pt 0 24)
(input)
(text "datain_h" (rect 0 0 48 14)(font "Arial" (font_size 8)))
(text "datain_h" (rect 4 11 46 24)(font "Arial" (font_size 8)))
(line (pt 0 24)(pt 88 24)(line_width 1))
)
(port
(pt 0 40)
(input)
(text "datain_l" (rect 0 0 43 14)(font "Arial" (font_size 8)))
(text "datain_l" (rect 4 27 43 40)(font "Arial" (font_size 8)))
(line (pt 0 40)(pt 88 40)(line_width 1))
)
(port
(pt 0 56)
(input)
(text "outclock" (rect 0 0 47 14)(font "Arial" (font_size 8)))
(text "outclock" (rect 4 43 42 56)(font "Arial" (font_size 8)))
(line (pt 0 56)(pt 88 56)(line_width 1))
)
(port
(pt 232 24)
(output)
(text "dataout" (rect 0 0 42 14)(font "Arial" (font_size 8)))
(text "dataout" (rect 193 11 229 24)(font "Arial" (font_size 8)))
(line (pt 232 24)(pt 152 24)(line_width 1))
)
(drawing
(text "ddio" (rect 110 27 131 40)(font "Arial" (font_size 8)))
(text "output" (rect 105 42 135 55)(font "Arial" (font_size 8)))
(text "power up" (rect 92 74 129 86)(font "Arial" ))
(text "low" (rect 92 84 105 96)(font "Arial" ))
(line (pt 88 16)(pt 152 16)(line_width 1))
(line (pt 152 16)(pt 152 96)(line_width 1))
(line (pt 152 96)(pt 88 96)(line_width 1))
(line (pt 88 96)(pt 88 16)(line_width 1))
)
)

64
FPGA_Quartus_13.1/altddio_out3.bsf
View File

@@ -1,64 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 232 120)
(text "altddio_out3" (rect 81 1 163 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 104 25 116)(font "Arial" ))
(port
(pt 0 24)
(input)
(text "datain_h" (rect 0 0 48 14)(font "Arial" (font_size 8)))
(text "datain_h" (rect 4 11 46 24)(font "Arial" (font_size 8)))
(line (pt 0 24)(pt 88 24)(line_width 1))
)
(port
(pt 0 40)
(input)
(text "datain_l" (rect 0 0 43 14)(font "Arial" (font_size 8)))
(text "datain_l" (rect 4 27 43 40)(font "Arial" (font_size 8)))
(line (pt 0 40)(pt 88 40)(line_width 1))
)
(port
(pt 0 56)
(input)
(text "outclock" (rect 0 0 47 14)(font "Arial" (font_size 8)))
(text "outclock" (rect 4 43 42 56)(font "Arial" (font_size 8)))
(line (pt 0 56)(pt 88 56)(line_width 1))
)
(port
(pt 232 24)
(output)
(text "dataout" (rect 0 0 42 14)(font "Arial" (font_size 8)))
(text "dataout" (rect 193 11 229 24)(font "Arial" (font_size 8)))
(line (pt 232 24)(pt 152 24)(line_width 1))
)
(drawing
(text "ddio" (rect 110 27 131 40)(font "Arial" (font_size 8)))
(text "output" (rect 105 42 135 55)(font "Arial" (font_size 8)))
(text "power up" (rect 92 74 129 86)(font "Arial" ))
(text "low" (rect 92 84 105 96)(font "Arial" ))
(line (pt 88 16)(pt 152 16)(line_width 1))
(line (pt 152 16)(pt 152 96)(line_width 1))
(line (pt 152 96)(pt 88 96)(line_width 1))
(line (pt 88 96)(pt 88 16)(line_width 1))
)
)

117
FPGA_Quartus_13.1/altpll0.bsf
View File

@@ -1,117 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2010 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 280 248)
(text "altpll0" (rect 120 1 167 20)(font "Arial" (font_size 10)))
(text "inst" (rect 8 229 31 244)(font "Arial" ))
(port
(pt 0 72)
(input)
(text "inclk0" (rect 0 0 40 16)(font "Arial" (font_size 8)))
(text "inclk0" (rect 4 56 38 72)(font "Arial" (font_size 8)))
(line (pt 0 72)(pt 48 72)(line_width 1))
)
(port
(pt 280 72)
(output)
(text "c0" (rect 0 0 16 16)(font "Arial" (font_size 8)))
(text "c0" (rect 263 56 277 72)(font "Arial" (font_size 8)))
(line (pt 280 72)(pt 248 72)(line_width 1))
)
(port
(pt 280 96)
(output)
(text "c1" (rect 0 0 16 16)(font "Arial" (font_size 8)))
(text "c1" (rect 263 80 277 96)(font "Arial" (font_size 8)))
(line (pt 280 96)(pt 248 96)(line_width 1))
)
(port
(pt 280 120)
(output)
(text "c2" (rect 0 0 16 16)(font "Arial" (font_size 8)))
(text "c2" (rect 263 104 277 120)(font "Arial" (font_size 8)))
(line (pt 280 120)(pt 248 120)(line_width 1))
)
(port
(pt 280 144)
(output)
(text "c3" (rect 0 0 16 16)(font "Arial" (font_size 8)))
(text "c3" (rect 263 128 277 144)(font "Arial" (font_size 8)))
(line (pt 280 144)(pt 248 144)(line_width 1))
)
(port
(pt 280 168)
(output)
(text "c4" (rect 0 0 16 16)(font "Arial" (font_size 8)))
(text "c4" (rect 263 152 277 168)(font "Arial" (font_size 8)))
(line (pt 280 168)(pt 248 168)(line_width 1))
)
(drawing
(text "Cyclone III" (rect 205 230 253 244)(font "Arial" ))
(text "inclk0 frequency: 33.000 MHz" (rect 58 67 201 81)(font "Arial" ))
(text "Operation Mode: Normal" (rect 58 84 173 98)(font "Arial" ))
(text "Clk " (rect 59 111 76 125)(font "Arial" ))
(text "Ratio" (rect 90 111 114 125)(font "Arial" ))
(text "Ph (dg)" (rect 128 111 163 125)(font "Arial" ))
(text "DC (%)" (rect 173 111 208 125)(font "Arial" ))
(text "c0" (rect 63 129 75 143)(font "Arial" ))
(text "16/11" (rect 89 129 116 143)(font "Arial" ))
(text "0.00" (rect 136 129 157 143)(font "Arial" ))
(text "50.00" (rect 178 129 205 143)(font "Arial" ))
(text "c1" (rect 63 147 75 161)(font "Arial" ))
(text "50/11" (rect 89 147 116 161)(font "Arial" ))
(text "0.00" (rect 136 147 157 161)(font "Arial" ))
(text "50.00" (rect 178 147 205 161)(font "Arial" ))
(text "c2" (rect 63 165 75 179)(font "Arial" ))
(text "40/11" (rect 89 165 116 179)(font "Arial" ))
(text "0.00" (rect 136 165 157 179)(font "Arial" ))
(text "50.00" (rect 178 165 205 179)(font "Arial" ))
(text "c3" (rect 63 183 75 197)(font "Arial" ))
(text "109/33" (rect 85 183 118 197)(font "Arial" ))
(text "0.00" (rect 136 183 157 197)(font "Arial" ))
(text "50.00" (rect 178 183 205 197)(font "Arial" ))
(text "c4" (rect 63 201 75 215)(font "Arial" ))
(text "109/39" (rect 85 201 118 215)(font "Arial" ))
(text "0.00" (rect 136 201 157 215)(font "Arial" ))
(text "50.00" (rect 178 201 205 215)(font "Arial" ))
(line (pt 0 0)(pt 281 0)(line_width 1))
(line (pt 281 0)(pt 281 249)(line_width 1))
(line (pt 0 249)(pt 281 249)(line_width 1))
(line (pt 0 0)(pt 0 249)(line_width 1))
(line (pt 56 108)(pt 215 108)(line_width 1))
(line (pt 56 125)(pt 215 125)(line_width 1))
(line (pt 56 143)(pt 215 143)(line_width 1))
(line (pt 56 161)(pt 215 161)(line_width 1))
(line (pt 56 179)(pt 215 179)(line_width 1))
(line (pt 56 197)(pt 215 197)(line_width 1))
(line (pt 56 215)(pt 215 215)(line_width 1))
(line (pt 56 108)(pt 56 215)(line_width 1))
(line (pt 82 108)(pt 82 215)(line_width 3))
(line (pt 125 108)(pt 125 215)(line_width 3))
(line (pt 170 108)(pt 170 215)(line_width 3))
(line (pt 214 108)(pt 214 215)(line_width 1))
(line (pt 48 56)(pt 248 56)(line_width 1))
(line (pt 248 56)(pt 248 232)(line_width 1))
(line (pt 48 232)(pt 248 232)(line_width 1))
(line (pt 48 56)(pt 48 232)(line_width 1))
)
)

117
FPGA_Quartus_13.1/altpll2.bsf
View File

@@ -1,117 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2014 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.2"))
(symbol
(rect 0 0 256 200)
(text "altpll2" (rect 111 0 153 16)(font "Arial" (font_size 10)))
(text "inst" (rect 8 185 26 196)(font "Arial" ))
(port
(pt 0 64)
(input)
(text "inclk0" (rect 0 0 34 13)(font "Arial" (font_size 8)))
(text "inclk0" (rect 4 51 31 63)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 40 64))
)
(port
(pt 256 64)
(output)
(text "c0" (rect 0 0 15 13)(font "Arial" (font_size 8)))
(text "c0" (rect 241 51 253 63)(font "Arial" (font_size 8)))
)
(port
(pt 256 80)
(output)
(text "c1" (rect 0 0 14 13)(font "Arial" (font_size 8)))
(text "c1" (rect 241 67 251 79)(font "Arial" (font_size 8)))
)
(port
(pt 256 96)
(output)
(text "c2" (rect 0 0 15 13)(font "Arial" (font_size 8)))
(text "c2" (rect 241 83 253 95)(font "Arial" (font_size 8)))
)
(port
(pt 256 112)
(output)
(text "c3" (rect 0 0 15 13)(font "Arial" (font_size 8)))
(text "c3" (rect 241 99 253 111)(font "Arial" (font_size 8)))
)
(port
(pt 256 128)
(output)
(text "c4" (rect 0 0 15 13)(font "Arial" (font_size 8)))
(text "c4" (rect 241 115 253 127)(font "Arial" (font_size 8)))
)
(drawing
(text "Cyclone III" (rect 198 186 442 382)(font "Arial" ))
(text "inclk0 frequency: 33.000 MHz" (rect 50 60 226 130)(font "Arial" ))
(text "Operation Mode: Src Sync Comp" (rect 50 72 239 154)(font "Arial" ))
(text "Clk " (rect 51 91 117 192)(font "Arial" ))
(text "Ratio" (rect 71 91 165 192)(font "Arial" ))
(text "Ph (dg)" (rect 97 91 225 192)(font "Arial" ))
(text "DC (%)" (rect 132 91 296 192)(font "Arial" ))
(text "c0" (rect 54 104 119 218)(font "Arial" ))
(text "4/1" (rect 76 104 165 218)(font "Arial" ))
(text "240.00" (rect 98 104 225 218)(font "Arial" ))
(text "50.00" (rect 136 104 296 218)(font "Arial" ))
(text "c1" (rect 54 117 118 244)(font "Arial" ))
(text "4/1" (rect 76 117 165 244)(font "Arial" ))
(text "0.00" (rect 103 117 225 244)(font "Arial" ))
(text "50.00" (rect 136 117 296 244)(font "Arial" ))
(text "c2" (rect 54 130 119 270)(font "Arial" ))
(text "4/1" (rect 76 130 165 270)(font "Arial" ))
(text "180.00" (rect 98 130 224 270)(font "Arial" ))
(text "50.00" (rect 136 130 296 270)(font "Arial" ))
(text "c3" (rect 54 143 119 296)(font "Arial" ))
(text "4/1" (rect 76 143 165 296)(font "Arial" ))
(text "105.00" (rect 98 143 224 296)(font "Arial" ))
(text "50.00" (rect 136 143 296 296)(font "Arial" ))
(text "c4" (rect 54 156 119 322)(font "Arial" ))
(text "2/1" (rect 76 156 165 322)(font "Arial" ))
(text "270.00" (rect 98 156 225 322)(font "Arial" ))
(text "50.00" (rect 136 156 296 322)(font "Arial" ))
(line (pt 0 0)(pt 257 0))
(line (pt 257 0)(pt 257 201))
(line (pt 0 201)(pt 257 201))
(line (pt 0 0)(pt 0 201))
(line (pt 48 89)(pt 164 89))
(line (pt 48 101)(pt 164 101))
(line (pt 48 114)(pt 164 114))
(line (pt 48 127)(pt 164 127))
(line (pt 48 140)(pt 164 140))
(line (pt 48 153)(pt 164 153))
(line (pt 48 166)(pt 164 166))
(line (pt 48 89)(pt 48 166))
(line (pt 68 89)(pt 68 166)(line_width 3))
(line (pt 94 89)(pt 94 166)(line_width 3))
(line (pt 129 89)(pt 129 166)(line_width 3))
(line (pt 163 89)(pt 163 166))
(line (pt 40 48)(pt 223 48))
(line (pt 223 48)(pt 223 183))
(line (pt 40 183)(pt 223 183))
(line (pt 40 48)(pt 40 183))
(line (pt 255 64)(pt 223 64))
(line (pt 255 80)(pt 223 80))
(line (pt 255 96)(pt 223 96))
(line (pt 255 112)(pt 223 112))
(line (pt 255 128)(pt 223 128))
)
)

112
FPGA_Quartus_13.1/altpll3.bsf
View File

@@ -1,112 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2010 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 272 200)
(text "altpll3" (rect 119 0 159 16)(font "Arial" (font_size 10)))
(text "inst" (rect 8 184 25 196)(font "Arial" ))
(port
(pt 0 64)
(input)
(text "inclk0" (rect 0 0 31 14)(font "Arial" (font_size 8)))
(text "inclk0" (rect 4 51 31 64)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 40 64)(line_width 1))
)
(port
(pt 272 64)
(output)
(text "c0" (rect 0 0 14 14)(font "Arial" (font_size 8)))
(text "c0" (rect 257 51 268 64)(font "Arial" (font_size 8)))
(line (pt 272 64)(pt 224 64)(line_width 1))
)
(port
(pt 272 80)
(output)
(text "c1" (rect 0 0 14 14)(font "Arial" (font_size 8)))
(text "c1" (rect 257 67 268 80)(font "Arial" (font_size 8)))
(line (pt 272 80)(pt 224 80)(line_width 1))
)
(port
(pt 272 96)
(output)
(text "c2" (rect 0 0 14 14)(font "Arial" (font_size 8)))
(text "c2" (rect 257 83 268 96)(font "Arial" (font_size 8)))
(line (pt 272 96)(pt 224 96)(line_width 1))
)
(port
(pt 272 112)
(output)
(text "c3" (rect 0 0 14 14)(font "Arial" (font_size 8)))
(text "c3" (rect 257 99 268 112)(font "Arial" (font_size 8)))
(line (pt 272 112)(pt 224 112)(line_width 1))
)
(port
(pt 272 128)
(output)
(text "locked" (rect 0 0 36 14)(font "Arial" (font_size 8)))
(text "locked" (rect 238 115 268 128)(font "Arial" (font_size 8)))
(line (pt 272 128)(pt 224 128)(line_width 1))
)
(drawing
(text "Cyclone III" (rect 211 185 258 197)(font "Arial" ))
(text "inclk0 frequency: 33.000 MHz" (rect 50 59 175 71)(font "Arial" ))
(text "Operation Mode: Src Sync Comp" (rect 50 73 188 85)(font "Arial" ))
(text "Clk " (rect 51 96 68 108)(font "Arial" ))
(text "Ratio" (rect 81 96 103 108)(font "Arial" ))
(text "Ph (dg)" (rect 116 96 146 108)(font "Arial" ))
(text "DC (%)" (rect 151 96 182 108)(font "Arial" ))
(text "c0" (rect 54 111 64 123)(font "Arial" ))
(text "25/33" (rect 81 111 104 123)(font "Arial" ))
(text "0.00" (rect 122 111 140 123)(font "Arial" ))
(text "50.00" (rect 155 111 178 123)(font "Arial" ))
(text "c1" (rect 54 126 64 138)(font "Arial" ))
(text "2/33" (rect 83 126 101 138)(font "Arial" ))
(text "0.00" (rect 122 126 140 138)(font "Arial" ))
(text "50.00" (rect 155 126 178 138)(font "Arial" ))
(text "c2" (rect 54 141 64 153)(font "Arial" ))
(text "1/66" (rect 83 141 101 153)(font "Arial" ))
(text "0.00" (rect 122 141 140 153)(font "Arial" ))
(text "50.00" (rect 155 141 178 153)(font "Arial" ))
(text "c3" (rect 54 156 64 168)(font "Arial" ))
(text "512/6875" (rect 73 156 111 168)(font "Arial" ))
(text "0.00" (rect 122 156 140 168)(font "Arial" ))
(text "50.00" (rect 155 156 178 168)(font "Arial" ))
(line (pt 0 0)(pt 273 0)(line_width 1))
(line (pt 273 0)(pt 273 201)(line_width 1))
(line (pt 0 201)(pt 273 201)(line_width 1))
(line (pt 0 0)(pt 0 201)(line_width 1))
(line (pt 48 94)(pt 184 94)(line_width 1))
(line (pt 48 108)(pt 184 108)(line_width 1))
(line (pt 48 123)(pt 184 123)(line_width 1))
(line (pt 48 138)(pt 184 138)(line_width 1))
(line (pt 48 153)(pt 184 153)(line_width 1))
(line (pt 48 168)(pt 184 168)(line_width 1))
(line (pt 48 94)(pt 48 168)(line_width 1))
(line (pt 70 94)(pt 70 168)(line_width 3))
(line (pt 113 94)(pt 113 168)(line_width 3))
(line (pt 148 94)(pt 148 168)(line_width 3))
(line (pt 183 94)(pt 183 168)(line_width 1))
(line (pt 40 48)(pt 224 48)(line_width 1))
(line (pt 224 48)(pt 224 184)(line_width 1))
(line (pt 40 184)(pt 224 184)(line_width 1))
(line (pt 40 48)(pt 40 184)(line_width 1))
)
)

125
FPGA_Quartus_13.1/altpll4.bsf
View File

@@ -1,125 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2014 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.2"))
(symbol
(rect 0 0 312 184)
(text "altpll4" (rect 139 0 181 16)(font "Arial" (font_size 10)))
(text "inst" (rect 8 169 26 180)(font "Arial" ))
(port
(pt 0 64)
(input)
(text "inclk0" (rect 0 0 34 13)(font "Arial" (font_size 8)))
(text "inclk0" (rect 4 51 31 63)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 72 64))
)
(port
(pt 0 80)
(input)
(text "areset" (rect 0 0 36 13)(font "Arial" (font_size 8)))
(text "areset" (rect 4 67 35 79)(font "Arial" (font_size 8)))
(line (pt 0 80)(pt 72 80))
)
(port
(pt 0 96)
(input)
(text "scanclk" (rect 0 0 44 13)(font "Arial" (font_size 8)))
(text "scanclk" (rect 4 83 40 95)(font "Arial" (font_size 8)))
(line (pt 0 96)(pt 72 96))
)
(port
(pt 0 112)
(input)
(text "scandata" (rect 0 0 53 13)(font "Arial" (font_size 8)))
(text "scandata" (rect 4 99 48 111)(font "Arial" (font_size 8)))
(line (pt 0 112)(pt 72 112))
)
(port
(pt 0 128)
(input)
(text "scanclkena" (rect 0 0 64 13)(font "Arial" (font_size 8)))
(text "scanclkena" (rect 4 115 57 127)(font "Arial" (font_size 8)))
(line (pt 0 128)(pt 72 128))
)
(port
(pt 0 144)
(input)
(text "configupdate" (rect 0 0 73 13)(font "Arial" (font_size 8)))
(text "configupdate" (rect 4 131 66 143)(font "Arial" (font_size 8)))
(line (pt 0 144)(pt 72 144))
)
(port
(pt 312 64)
(output)
(text "c0" (rect 0 0 15 13)(font "Arial" (font_size 8)))
(text "c0" (rect 297 51 309 63)(font "Arial" (font_size 8)))
)
(port
(pt 312 80)
(output)
(text "scandataout" (rect 0 0 70 13)(font "Arial" (font_size 8)))
(text "scandataout" (rect 250 67 309 79)(font "Arial" (font_size 8)))
)
(port
(pt 312 96)
(output)
(text "scandone" (rect 0 0 56 13)(font "Arial" (font_size 8)))
(text "scandone" (rect 262 83 309 95)(font "Arial" (font_size 8)))
)
(port
(pt 312 112)
(output)
(text "locked" (rect 0 0 37 13)(font "Arial" (font_size 8)))
(text "locked" (rect 277 99 308 111)(font "Arial" (font_size 8)))
)
(drawing
(text "Cyclone III" (rect 254 171 554 352)(font "Arial" ))
(text "inclk0 frequency: 48.000 MHz" (rect 82 93 290 196)(font "Arial" ))
(text "Operation Mode: Normal" (rect 82 105 267 220)(font "Arial" ))
(text "Clk " (rect 83 124 181 258)(font "Arial" ))
(text "Ratio" (rect 103 124 229 258)(font "Arial" ))
(text "Ph (dg)" (rect 129 124 289 258)(font "Arial" ))
(text "DC (%)" (rect 164 124 360 258)(font "Arial" ))
(text "c0" (rect 86 137 183 284)(font "Arial" ))
(text "2/1" (rect 108 137 229 284)(font "Arial" ))
(text "0.00" (rect 135 137 289 284)(font "Arial" ))
(text "50.00" (rect 168 137 360 284)(font "Arial" ))
(line (pt 0 0)(pt 313 0))
(line (pt 313 0)(pt 313 186))
(line (pt 0 186)(pt 313 186))
(line (pt 0 0)(pt 0 186))
(line (pt 80 122)(pt 196 122))
(line (pt 80 134)(pt 196 134))
(line (pt 80 147)(pt 196 147))
(line (pt 80 122)(pt 80 147))
(line (pt 100 122)(pt 100 147)(line_width 3))
(line (pt 126 122)(pt 126 147)(line_width 3))
(line (pt 161 122)(pt 161 147)(line_width 3))
(line (pt 195 122)(pt 195 147))
(line (pt 72 48)(pt 239 48))
(line (pt 239 48)(pt 239 168))
(line (pt 72 168)(pt 239 168))
(line (pt 72 48)(pt 72 168))
(line (pt 311 64)(pt 239 64))
(line (pt 311 80)(pt 239 80))
(line (pt 311 96)(pt 239 96))
(line (pt 311 112)(pt 239 112))
)
)

162
FPGA_Quartus_13.1/altpll_reconfig0.bsf
View File

@@ -1,162 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2010 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 216 296)
(text "altpll_reconfig0" (rect 54 1 182 20)(font "Arial" (font_size 10)))
(text "inst" (rect 8 277 31 292)(font "Arial" ))
(port
(pt 0 40)
(input)
(text "reconfig" (rect 0 0 53 16)(font "Arial" (font_size 8)))
(text "reconfig" (rect 20 32 65 48)(font "Arial" (font_size 8)))
(line (pt 0 40)(pt 16 40)(line_width 1))
)
(port
(pt 0 56)
(input)
(text "read_param" (rect 0 0 80 16)(font "Arial" (font_size 8)))
(text "read_param" (rect 20 48 88 64)(font "Arial" (font_size 8)))
(line (pt 0 56)(pt 16 56)(line_width 1))
)
(port
(pt 0 72)
(input)
(text "write_param" (rect 0 0 82 16)(font "Arial" (font_size 8)))
(text "write_param" (rect 20 64 90 80)(font "Arial" (font_size 8)))
(line (pt 0 72)(pt 16 72)(line_width 1))
)
(port
(pt 0 96)
(input)
(text "data_in[8..0]" (rect 0 0 84 16)(font "Arial" (font_size 8)))
(text "data_in[8..0]" (rect 20 88 92 104)(font "Arial" (font_size 8)))
(line (pt 0 96)(pt 16 96)(line_width 3))
)
(port
(pt 0 112)
(input)
(text "counter_type[3..0]" (rect 0 0 123 16)(font "Arial" (font_size 8)))
(text "counter_type[3..0]" (rect 20 104 125 120)(font "Arial" (font_size 8)))
(line (pt 0 112)(pt 16 112)(line_width 3))
)
(port
(pt 0 128)
(input)
(text "counter_param[2..0]" (rect 0 0 136 16)(font "Arial" (font_size 8)))
(text "counter_param[2..0]" (rect 20 120 136 136)(font "Arial" (font_size 8)))
(line (pt 0 128)(pt 16 128)(line_width 3))
)
(port
(pt 0 168)
(input)
(text "pll_scandataout" (rect 0 0 107 16)(font "Arial" (font_size 8)))
(text "pll_scandataout" (rect 20 160 111 176)(font "Arial" (font_size 8)))
(line (pt 0 168)(pt 16 168)(line_width 1))
)
(port
(pt 0 184)
(input)
(text "pll_scandone" (rect 0 0 89 16)(font "Arial" (font_size 8)))
(text "pll_scandone" (rect 20 176 96 192)(font "Arial" (font_size 8)))
(line (pt 0 184)(pt 16 184)(line_width 1))
)
(port
(pt 0 208)
(input)
(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
(text "clock" (rect 20 200 51 216)(font "Arial" (font_size 8)))
(line (pt 0 208)(pt 16 208)(line_width 1))
)
(port
(pt 0 224)
(input)
(text "reset" (rect 0 0 34 16)(font "Arial" (font_size 8)))
(text "reset" (rect 20 216 49 232)(font "Arial" (font_size 8)))
(line (pt 0 224)(pt 16 224)(line_width 1))
)
(port
(pt 0 248)
(input)
(text "pll_areset_in" (rect 0 0 86 16)(font "Arial" (font_size 8)))
(text "pll_areset_in" (rect 20 240 93 256)(font "Arial" (font_size 8)))
(line (pt 0 248)(pt 16 248)(line_width 1))
)
(port
(pt 216 40)
(output)
(text "busy" (rect 0 0 33 16)(font "Arial" (font_size 8)))
(text "busy" (rect 169 32 197 48)(font "Arial" (font_size 8)))
(line (pt 216 40)(pt 200 40)(line_width 1))
)
(port
(pt 216 96)
(output)
(text "data_out[8..0]" (rect 0 0 94 16)(font "Arial" (font_size 8)))
(text "data_out[8..0]" (rect 117 88 197 104)(font "Arial" (font_size 8)))
(line (pt 216 96)(pt 200 96)(line_width 3))
)
(port
(pt 216 152)
(output)
(text "pll_scandata" (rect 0 0 86 16)(font "Arial" (font_size 8)))
(text "pll_scandata" (rect 124 144 197 160)(font "Arial" (font_size 8)))
(line (pt 216 152)(pt 200 152)(line_width 1))
)
(port
(pt 216 168)
(output)
(text "pll_scanclk" (rect 0 0 76 16)(font "Arial" (font_size 8)))
(text "pll_scanclk" (rect 132 160 197 176)(font "Arial" (font_size 8)))
(line (pt 216 168)(pt 200 168)(line_width 1))
)
(port
(pt 216 200)
(output)
(text "pll_scanclkena" (rect 0 0 101 16)(font "Arial" (font_size 8)))
(text "pll_scanclkena" (rect 111 192 197 208)(font "Arial" (font_size 8)))
(line (pt 216 200)(pt 200 200)(line_width 1))
)
(port
(pt 216 216)
(output)
(text "pll_configupdate" (rect 0 0 109 16)(font "Arial" (font_size 8)))
(text "pll_configupdate" (rect 104 208 197 224)(font "Arial" (font_size 8)))
(line (pt 216 216)(pt 200 216)(line_width 1))
)
(port
(pt 216 248)
(output)
(text "pll_areset" (rect 0 0 66 16)(font "Arial" (font_size 8)))
(text "pll_areset" (rect 141 240 197 256)(font "Arial" (font_size 8)))
(line (pt 216 248)(pt 200 248)(line_width 1))
)
(drawing
(line (pt 0 0)(pt 217 0)(line_width 1))
(line (pt 217 0)(pt 217 297)(line_width 1))
(line (pt 0 297)(pt 217 297)(line_width 1))
(line (pt 0 0)(pt 0 297)(line_width 1))
(line (pt 16 24)(pt 201 24)(line_width 1))
(line (pt 201 24)(pt 201 273)(line_width 1))
(line (pt 16 273)(pt 201 273)(line_width 1))
(line (pt 16 24)(pt 16 273)(line_width 1))
)
)

162
FPGA_Quartus_13.1/altpll_reconfig1.bsf
View File

@@ -1,162 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2010 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 216 296)
(text "altpll_reconfig1" (rect 54 1 182 20)(font "Arial" (font_size 10)))
(text "inst" (rect 8 277 31 292)(font "Arial" ))
(port
(pt 0 40)
(input)
(text "reconfig" (rect 0 0 53 16)(font "Arial" (font_size 8)))
(text "reconfig" (rect 20 32 65 48)(font "Arial" (font_size 8)))
(line (pt 0 40)(pt 16 40)(line_width 1))
)
(port
(pt 0 56)
(input)
(text "read_param" (rect 0 0 80 16)(font "Arial" (font_size 8)))
(text "read_param" (rect 20 48 88 64)(font "Arial" (font_size 8)))
(line (pt 0 56)(pt 16 56)(line_width 1))
)
(port
(pt 0 72)
(input)
(text "write_param" (rect 0 0 82 16)(font "Arial" (font_size 8)))
(text "write_param" (rect 20 64 90 80)(font "Arial" (font_size 8)))
(line (pt 0 72)(pt 16 72)(line_width 1))
)
(port
(pt 0 96)
(input)
(text "data_in[8..0]" (rect 0 0 84 16)(font "Arial" (font_size 8)))
(text "data_in[8..0]" (rect 20 88 92 104)(font "Arial" (font_size 8)))
(line (pt 0 96)(pt 16 96)(line_width 3))
)
(port
(pt 0 112)
(input)
(text "counter_type[3..0]" (rect 0 0 123 16)(font "Arial" (font_size 8)))
(text "counter_type[3..0]" (rect 20 104 125 120)(font "Arial" (font_size 8)))
(line (pt 0 112)(pt 16 112)(line_width 3))
)
(port
(pt 0 128)
(input)
(text "counter_param[2..0]" (rect 0 0 136 16)(font "Arial" (font_size 8)))
(text "counter_param[2..0]" (rect 20 120 136 136)(font "Arial" (font_size 8)))
(line (pt 0 128)(pt 16 128)(line_width 3))
)
(port
(pt 0 168)
(input)
(text "pll_scandataout" (rect 0 0 107 16)(font "Arial" (font_size 8)))
(text "pll_scandataout" (rect 20 160 111 176)(font "Arial" (font_size 8)))
(line (pt 0 168)(pt 16 168)(line_width 1))
)
(port
(pt 0 184)
(input)
(text "pll_scandone" (rect 0 0 89 16)(font "Arial" (font_size 8)))
(text "pll_scandone" (rect 20 176 96 192)(font "Arial" (font_size 8)))
(line (pt 0 184)(pt 16 184)(line_width 1))
)
(port
(pt 0 208)
(input)
(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
(text "clock" (rect 20 200 51 216)(font "Arial" (font_size 8)))
(line (pt 0 208)(pt 16 208)(line_width 1))
)
(port
(pt 0 224)
(input)
(text "reset" (rect 0 0 34 16)(font "Arial" (font_size 8)))
(text "reset" (rect 20 216 49 232)(font "Arial" (font_size 8)))
(line (pt 0 224)(pt 16 224)(line_width 1))
)
(port
(pt 0 248)
(input)
(text "pll_areset_in" (rect 0 0 86 16)(font "Arial" (font_size 8)))
(text "pll_areset_in" (rect 20 240 93 256)(font "Arial" (font_size 8)))
(line (pt 0 248)(pt 16 248)(line_width 1))
)
(port
(pt 216 40)
(output)
(text "busy" (rect 0 0 33 16)(font "Arial" (font_size 8)))
(text "busy" (rect 169 32 197 48)(font "Arial" (font_size 8)))
(line (pt 216 40)(pt 200 40)(line_width 1))
)
(port
(pt 216 96)
(output)
(text "data_out[8..0]" (rect 0 0 94 16)(font "Arial" (font_size 8)))
(text "data_out[8..0]" (rect 117 88 197 104)(font "Arial" (font_size 8)))
(line (pt 216 96)(pt 200 96)(line_width 3))
)
(port
(pt 216 152)
(output)
(text "pll_scandata" (rect 0 0 86 16)(font "Arial" (font_size 8)))
(text "pll_scandata" (rect 124 144 197 160)(font "Arial" (font_size 8)))
(line (pt 216 152)(pt 200 152)(line_width 1))
)
(port
(pt 216 168)
(output)
(text "pll_scanclk" (rect 0 0 76 16)(font "Arial" (font_size 8)))
(text "pll_scanclk" (rect 132 160 197 176)(font "Arial" (font_size 8)))
(line (pt 216 168)(pt 200 168)(line_width 1))
)
(port
(pt 216 200)
(output)
(text "pll_scanclkena" (rect 0 0 101 16)(font "Arial" (font_size 8)))
(text "pll_scanclkena" (rect 111 192 197 208)(font "Arial" (font_size 8)))
(line (pt 216 200)(pt 200 200)(line_width 1))
)
(port
(pt 216 216)
(output)
(text "pll_configupdate" (rect 0 0 109 16)(font "Arial" (font_size 8)))
(text "pll_configupdate" (rect 104 208 197 224)(font "Arial" (font_size 8)))
(line (pt 216 216)(pt 200 216)(line_width 1))
)
(port
(pt 216 248)
(output)
(text "pll_areset" (rect 0 0 66 16)(font "Arial" (font_size 8)))
(text "pll_areset" (rect 141 240 197 256)(font "Arial" (font_size 8)))
(line (pt 216 248)(pt 200 248)(line_width 1))
)
(drawing
(line (pt 0 0)(pt 217 0)(line_width 1))
(line (pt 217 0)(pt 217 297)(line_width 1))
(line (pt 0 297)(pt 217 297)(line_width 1))
(line (pt 0 0)(pt 0 297)(line_width 1))
(line (pt 16 24)(pt 201 24)(line_width 1))
(line (pt 201 24)(pt 201 273)(line_width 1))
(line (pt 16 273)(pt 201 273)(line_width 1))
(line (pt 16 24)(pt 16 273)(line_width 1))
)
)

56
FPGA_Quartus_13.1/lpm_bustri_BYT.bsf
View File

@@ -1,56 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 96 40)
(text "lpm_bustri_BYT" (rect 2 1 110 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 24 25 36)(font "Arial" ))
(port
(pt 40 40)
(input)
(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
(text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible))
(line (pt 40 40)(pt 40 28)(line_width 1))
)
(port
(pt 0 24)
(input)
(text "data[7..0]" (rect 0 0 53 14)(font "Arial" (font_size 8)))
(text "data[7..0]" (rect -3 -21 10 24)(font "Arial" (font_size 8))(invisible))
(line (pt 0 24)(pt 32 24)(line_width 3))
)
(port
(pt 96 24)
(bidir)
(text "tridata[7..0]" (rect 0 0 63 14)(font "Arial" (font_size 8)))
(text "tridata[7..0]" (rect 100 -30 113 24)(font "Arial" (font_size 8))(invisible))
(line (pt 96 24)(pt 48 24)(line_width 3))
)
(drawing
(text "8" (rect 71 25 76 37)(font "Arial" ))
(text "8" (rect 15 25 20 37)(font "Arial" ))
(line (pt 32 16)(pt 48 24)(line_width 1))
(line (pt 48 24)(pt 32 32)(line_width 1))
(line (pt 32 32)(pt 32 16)(line_width 1))
(line (pt 66 28)(pt 74 20)(line_width 1))
(line (pt 10 28)(pt 18 20)(line_width 1))
)
)

56
FPGA_Quartus_13.1/lpm_bustri_LONG.bsf
View File

@@ -1,56 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 112 40)
(text "lpm_bustri_LONG" (rect 5 1 126 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 24 25 36)(font "Arial" ))
(port
(pt 40 40)
(input)
(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
(text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible))
(line (pt 40 40)(pt 40 28)(line_width 1))
)
(port
(pt 0 24)
(input)
(text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
(text "data[31..0]" (rect -3 -27 10 24)(font "Arial" (font_size 8))(invisible))
(line (pt 0 24)(pt 32 24)(line_width 3))
)
(port
(pt 112 24)
(bidir)
(text "tridata[31..0]" (rect 0 0 70 14)(font "Arial" (font_size 8)))
(text "tridata[31..0]" (rect 116 -36 129 24)(font "Arial" (font_size 8))(invisible))
(line (pt 112 24)(pt 48 24)(line_width 3))
)
(drawing
(text "32" (rect 77 25 87 37)(font "Arial" ))
(text "32" (rect 13 25 23 37)(font "Arial" ))
(line (pt 32 16)(pt 48 24)(line_width 1))
(line (pt 48 24)(pt 32 32)(line_width 1))
(line (pt 32 32)(pt 32 16)(line_width 1))
(line (pt 72 28)(pt 80 20)(line_width 1))
(line (pt 8 28)(pt 16 20)(line_width 1))
)
)

56
FPGA_Quartus_13.1/lpm_bustri_WORD.bsf
View File

@@ -1,56 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 112 40)
(text "lpm_bustri_WORD" (rect 2 1 129 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 24 25 36)(font "Arial" ))
(port
(pt 40 40)
(input)
(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
(text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible))
(line (pt 40 40)(pt 40 28)(line_width 1))
)
(port
(pt 0 24)
(input)
(text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
(text "data[15..0]" (rect -3 -27 10 24)(font "Arial" (font_size 8))(invisible))
(line (pt 0 24)(pt 32 24)(line_width 3))
)
(port
(pt 112 24)
(bidir)
(text "tridata[15..0]" (rect 0 0 70 14)(font "Arial" (font_size 8)))
(text "tridata[15..0]" (rect 116 -36 129 24)(font "Arial" (font_size 8))(invisible))
(line (pt 112 24)(pt 48 24)(line_width 3))
)
(drawing
(text "16" (rect 77 25 87 37)(font "Arial" ))
(text "16" (rect 13 25 23 37)(font "Arial" ))
(line (pt 32 16)(pt 48 24)(line_width 1))
(line (pt 48 24)(pt 32 32)(line_width 1))
(line (pt 32 32)(pt 32 16)(line_width 1))
(line (pt 72 28)(pt 80 20)(line_width 1))
(line (pt 8 28)(pt 16 20)(line_width 1))
)
)

49
FPGA_Quartus_13.1/lpm_counter0.bsf
View File

@@ -1,49 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 144 64)
(text "lpm_counter0" (rect 33 1 125 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 48 25 60)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
(text "clock" (rect 26 26 49 39)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 16 32)(line_width 1))
)
(port
(pt 144 40)
(output)
(text "q[17..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
(text "q[17..0]" (rect 89 34 125 47)(font "Arial" (font_size 8)))
(line (pt 144 40)(pt 128 40)(line_width 3))
)
(drawing
(text "up counter" (rect 84 17 128 29)(font "Arial" ))
(line (pt 16 16)(pt 128 16)(line_width 1))
(line (pt 128 16)(pt 128 48)(line_width 1))
(line (pt 128 48)(pt 16 48)(line_width 1))
(line (pt 16 48)(pt 16 16)(line_width 1))
(line (pt 16 26)(pt 22 32)(line_width 1))
(line (pt 22 32)(pt 16 38)(line_width 1))
)
)

53
FPGA_Quartus_13.1/lpm_latch0.bsf
View File

@@ -1,53 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
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