Firebee/FPGA_Config
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This commit is contained in:
Markus Fröschle
2016-01-17 20:39:25 +00:00
parent 21a4a80fb7
commit b9c3ec9366
2 changed files with 19 additions and 19 deletions
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FPGA_Quartus_13.1/firebee1.qws
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38
FPGA_Quartus_13.1/flexbus_register.vhd
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@@ -2,25 +2,25 @@ LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY flexbus_register IS
GENERIC
(
reg_width : integer := 11;
match_address : std_logic_vector(31 DOWNTO 0) := (OTHERS => '0');
match_mask : std_logic_vector(31 DOWNTO 0) := (OTHERS => '1');
match_fbcs : integer := 0
);
PORT
(
clk : IN std_logic;
fb_addr : IN std_logic_vector(31 DOWNTO 0);
fb_data : IN std_logic_vector(31 DOWNTO 0);
fb_cs : IN std_logic_vector(5 DOWNTO 1);
fb_wr_n : IN std_logic;
data : OUT std_logic_vector(reg_width - 1 DOWNTO 0);
cs : OUT std_logic := '0'
);
END ENTITY flexbus_register;
ENTITY flexbus_register IS
GENERIC
(
reg_width : integer := 11;
match_address : std_logic_vector(31 DOWNTO 0) := (OTHERS => '0');
match_mask : std_logic_vector(31 DOWNTO 0) := (OTHERS => '1');
match_fbcs : integer := 0
);
PORT
(
clk : IN std_logic;
fb_addr : IN std_logic_vector(31 DOWNTO 0);
fb_data : IN std_logic_vector(31 DOWNTO 0);
fb_cs : IN std_logic_vector(5 DOWNTO 1);
fb_wr_n : IN std_logic;
data : OUT std_logic_vector(reg_width - 1 DOWNTO 0);
cs : OUT std_logic := '0'
);
END ENTITY flexbus_register;
ARCHITECTURE rtl OF flexbus_register IS
SIGNAL fbcs_match : std_logic;