From b9c3ec9366ab29d236b5a87eb3e5768bca745de8 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= <mfro@mubf.de>
Date: Sun, 17 Jan 2016 20:39:25 +0000
Subject: [PATCH] modify indent

---
 FPGA_Quartus_13.1/firebee1.qws         | Bin 5228 -> 7748 bytes
 FPGA_Quartus_13.1/flexbus_register.vhd |  38 ++++++++++++-------------
 2 files changed, 19 insertions(+), 19 deletions(-)

diff --git a/FPGA_Quartus_13.1/firebee1.qws b/FPGA_Quartus_13.1/firebee1.qws
index 80b4fbfd39e1e937c7752e40f53896c9ec813214..b91970ff6c6c26f4a9ba8047ac6b48c8eff1de53 100644
GIT binary patch
delta 1283
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zWg3H2XK0uvH^e|08pg>T!z6|o3Me6TVTRH=B+!B|B7`_<P|IhKHZ|1L5r;`dj7%ue
z$`d8T3=WeHW0vu5;kbTaPXtXjN&#ws(gFeN@&a5zzzXHR`>(1)u6r~{0Pfe6e<S3`
zFOYvu`jat-UbV*Tee_w@r(IRU_(Jg@3WdTi5+%6A!ZNsyjN~dKtZwRwT@3YzSg%nF
zB_4aw&Pk5ZC&dZIMb2ZamLw`*&r32E*srqJs0#p|3dVX*I!<UOzl*#ia*hnK5%p#u
z&4!XOwV;`W){|<$3DQwB#3<`ckV<f1jcB4YMjN>T8Ga12tf2swWqoGd+V9W4l3Z&R
zQ(0?#opMsEYTE4oNr4hok@OZqHzSR+FXy_0<RiT95iUT4@)XjhUz1|n6pL}5He-lw
z)2i}~8E4@&BTI_A88h!wY6R|VUc+AWQkTLFrcX1`2yuo6TbA9MmQ^@QZJLc9rbQ6v
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p@umv-y9ECEchRH1fZN^12s*#$o09^HD@|YgqMgIl`7I!vg+G3g7S{j(

delta 319
zcmX?N^G0KWHY4jqood!%h7^Y6jcfQBCqHNEnw-eg#>hT7lP!-`oPmL9+T=TIa%_yA
z3=9k@li0;2^BEWz-9a3N|Ns93X=Vlnc6*?h-(&-J1tAcVVHre<O$n?$fGcP6Irg`V
zj+6Cy#JCw{fP&wEiWrzCxAKKd4rQs>9Lv9$ak7FO$K)U})y@5UEUdD{K>7U)46L7k
z%H{#>K;dtaY-W-K$}-hMWI=|3R73caHwZ^=J}9Qdqy*9g1Rz5g??Vki;scqJ19<XT
lK@Mu3e1ykDh^ZMU2K5)qMX)f`@w`9@5CA)<X|kT27yu~UNxuL9

diff --git a/FPGA_Quartus_13.1/flexbus_register.vhd b/FPGA_Quartus_13.1/flexbus_register.vhd
index 6b54cbf..72d3dc0 100644
--- a/FPGA_Quartus_13.1/flexbus_register.vhd
+++ b/FPGA_Quartus_13.1/flexbus_register.vhd
@@ -2,25 +2,25 @@ LIBRARY ieee;
     USE ieee.std_logic_1164.all;
     USE ieee.numeric_std.all;
 
-    ENTITY flexbus_register IS
-        GENERIC
-        (
-            reg_width       : integer := 11;
-            match_address   : std_logic_vector(31 DOWNTO 0) := (OTHERS => '0');
-            match_mask      : std_logic_vector(31 DOWNTO 0) := (OTHERS => '1');
-            match_fbcs      : integer := 0
-        );
-        PORT
-        (
-            clk             : IN std_logic;
-            fb_addr         : IN std_logic_vector(31 DOWNTO 0);
-            fb_data         : IN std_logic_vector(31 DOWNTO 0);
-            fb_cs           : IN std_logic_vector(5 DOWNTO 1);
-            fb_wr_n         : IN std_logic;
-            data            : OUT std_logic_vector(reg_width - 1 DOWNTO 0);
-            cs              : OUT std_logic := '0'
-        );
-    END ENTITY flexbus_register;
+ENTITY flexbus_register IS
+    GENERIC
+    (
+        reg_width       : integer := 11;
+        match_address   : std_logic_vector(31 DOWNTO 0) := (OTHERS => '0');
+        match_mask      : std_logic_vector(31 DOWNTO 0) := (OTHERS => '1');
+        match_fbcs      : integer := 0
+    );
+    PORT
+    (
+        clk             : IN std_logic;
+        fb_addr         : IN std_logic_vector(31 DOWNTO 0);
+        fb_data         : IN std_logic_vector(31 DOWNTO 0);
+        fb_cs           : IN std_logic_vector(5 DOWNTO 1);
+        fb_wr_n         : IN std_logic;
+        data            : OUT std_logic_vector(reg_width - 1 DOWNTO 0);
+        cs              : OUT std_logic := '0'
+    );
+END ENTITY flexbus_register;
     
 ARCHITECTURE rtl OF flexbus_register IS
     SIGNAL fbcs_match       : std_logic;