modify indent

FPGA_Quartus_13.1/flexbus_register.vhd

@@ -2,7 +2,7 @@ LIBRARY ieee;
     USE ieee.std_logic_1164.all;
     USE ieee.numeric_std.all;
 
-    ENTITY flexbus_register IS
+ENTITY flexbus_register IS
     GENERIC
     (
         reg_width       : integer := 11;
@@ -20,7 +20,7 @@ LIBRARY ieee;
         data            : OUT std_logic_vector(reg_width - 1 DOWNTO 0);
         cs              : OUT std_logic := '0'
     );
-    END ENTITY flexbus_register;
+END ENTITY flexbus_register;
     
 ARCHITECTURE rtl OF flexbus_register IS
     SIGNAL fbcs_match       : std_logic;