Sync with Fredi's source tree 13/06/2015

Parallel port fix.
2018-04-09 17:19:13 +02:00
parent 3fb6e3bd8a
commit 68129dbe57
107 changed files with 12435 additions and 27384 deletions
--- a/FPGA_by_Fredi/altpll3.cmp
+++ b/FPGA_by_Fredi/altpll3.cmp
@@ -20,6 +20,7 @@ component altpll3
 		c0		: OUT STD_LOGIC ;
 		c1		: OUT STD_LOGIC ;
 		c2		: OUT STD_LOGIC ;
-		c3		: OUT STD_LOGIC 
+		c3		: OUT STD_LOGIC ;
+		locked		: OUT STD_LOGIC 
 	);
 end component;