Sync with Fredi's source tree 13/06/2015

Parallel port fix.

FPGA_by_Fredi/altiobuf_bidir0.tdf

@@ -0,0 +1,90 @@
+-- megafunction wizard: %ALTIOBUF%
+-- GENERATION: STANDARD
+-- VERSION: WM1.0
+-- MODULE: altiobuf_bidir 
+
+-- ============================================================
+-- File Name: altiobuf_bidir0.tdf
+-- Megafunction Name(s):
+-- 			altiobuf_bidir
+--
+-- Simulation Library Files(s):
+-- 			cycloneiii
+-- ============================================================
+-- ************************************************************
+-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+--
+-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
+-- ************************************************************
+
+
+--Copyright (C) 1991-2010 Altera Corporation
+--Your use of Altera Corporation's design tools, logic functions 
+--and other software and tools, and its AMPP partner logic 
+--functions, and any output files from any of the foregoing 
+--(including device programming or simulation files), and any 
+--associated documentation or information are expressly subject 
+--to the terms and conditions of the Altera Program License 
+--Subscription Agreement, Altera MegaCore Function License 
+--Agreement, or other applicable license agreement, including, 
+--without limitation, that your use is for the sole purpose of 
+--programming logic devices manufactured by Altera and sold by 
+--Altera or its authorized distributors.  Please refer to the 
+--applicable agreement for further details.
+
+-- Clearbox generated function header
+FUNCTION altiobuf_bidir0_iobuf_bidir_quo (datain[0..0], oe[0..0])
+RETURNS ( dataio[0..0], dataout[0..0]);
+
+
+
+
+SUBDESIGN altiobuf_bidir0
+(
+	datain[0..0]	 : INPUT;
+	oe[0..0]	 : INPUT;
+	dataio[0..0]	 : BIDIR;
+	dataout[0..0]	 : OUTPUT;
+)
+
+VARIABLE
+
+	altiobuf_bidir0_iobuf_bidir_quo_component : altiobuf_bidir0_iobuf_bidir_quo;
+
+BEGIN
+
+	dataout[0..0] = altiobuf_bidir0_iobuf_bidir_quo_component.dataout[0..0];
+	dataio[0..0] = altiobuf_bidir0_iobuf_bidir_quo_component.dataio[0..0];
+	altiobuf_bidir0_iobuf_bidir_quo_component.datain[0..0] = datain[0..0];
+	altiobuf_bidir0_iobuf_bidir_quo_component.oe[0..0] = oe[0..0];
+END;
+
+
+
+-- ============================================================
+-- CNX file retrieval info
+-- ============================================================
+-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
+-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
+-- Retrieval info: CONSTANT: enable_bus_hold STRING "FALSE"
+-- Retrieval info: CONSTANT: number_of_channels NUMERIC "1"
+-- Retrieval info: CONSTANT: open_drain_output STRING "FALSE"
+-- Retrieval info: CONSTANT: use_differential_mode STRING "FALSE"
+-- Retrieval info: CONSTANT: use_dynamic_termination_control STRING "FALSE"
+-- Retrieval info: CONSTANT: use_termination_control STRING "FALSE"
+-- Retrieval info: USED_PORT: datain 0 0 1 0 INPUT NODEFVAL "datain[0..0]"
+-- Retrieval info: USED_PORT: dataio 0 0 1 0 BIDIR NODEFVAL "dataio[0..0]"
+-- Retrieval info: USED_PORT: dataout 0 0 1 0 OUTPUT NODEFVAL "dataout[0..0]"
+-- Retrieval info: USED_PORT: oe 0 0 1 0 INPUT NODEFVAL "oe[0..0]"
+-- Retrieval info: CONNECT: @datain 0 0 1 0 datain 0 0 1 0
+-- Retrieval info: CONNECT: @oe 0 0 1 0 oe 0 0 1 0
+-- Retrieval info: CONNECT: dataout 0 0 1 0 @dataout 0 0 1 0
+-- Retrieval info: CONNECT: dataio 0 0 1 0 @dataio 0 0 1 0
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altiobuf_bidir0.tdf TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altiobuf_bidir0.inc TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altiobuf_bidir0.cmp TRUE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altiobuf_bidir0.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altiobuf_bidir0_inst.tdf FALSE
+-- Retrieval info: LIB_FILE: cycloneiii