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Sync with Fredi's source tree 13/06/2015

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Parallel port fix.
This commit is contained in:
David Gálvez
2018-04-09 17:19:13 +02:00
parent 3fb6e3bd8a
commit 68129dbe57
107 changed files with 12435 additions and 27384 deletions
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6
FPGA_by_Fredi/Video/DDR_CTR.tdf
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@@ -373,8 +373,8 @@ BEGIN
VA_S[10] = VA_S[10]; -- AUTO PRECHARGE WENN NICHT FIFO PAGE
BA_S[] = CPU_AC & CPU_BA[]
# BLITTER_AC & BLITTER_BA[];
SR_VDMP[7..4] = FB_B[]; -- BYTE ENABLE WRITE
SR_VDMP[3..0] = LINE & B"1111"; -- LINE ENABLE WRITE
SR_VDMP[7..4] = FB_B[] # BLITTER_AC & B"1111"; -- BYTE ENABLE WRITE, BEI BLITTER IMMER LINE
SR_VDMP[3..0] = (LINE # BLITTER_AC) & B"1111"; -- LINE ENABLE WRITE, BEI BLITTER IMMER LINE
DDR_SM = DS_T6W;
WHEN DS_T6W =>
@@ -384,7 +384,7 @@ BEGIN
VWE = VCC;
SR_DDR_WR = VCC; -- WRITE COMMAND CPU UND BLITTER IF WRITER
SR_DDRWR_D_SEL = VCC; -- 2. H<>LFTE WRITE DATEN SELEKTIEREN
SR_VDMP[] = LINE & B"11111111"; -- WENN LINE DANN ACTIV
SR_VDMP[] = (LINE # BLITTER_AC) & B"11111111"; -- WENN LINE DANN ACTIV
DDR_SM = DS_T7W;
WHEN DS_T7W =>