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delete remaininf .bsf (schematics) files

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This commit is contained in:
Markus Fröschle
2016-07-29 07:13:44 +00:00
parent e0269dc6c9
commit 386851c02b
50 changed files with 0 additions and 3718 deletions
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95
FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/dcfifo0.bsf
View File

@@ -1,95 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 160 168)
(text "dcfifo0" (rect 62 1 105 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 152 25 164)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "data[7..0]" (rect 0 0 53 14)(font "Arial" (font_size 8)))
(text "data[7..0]" (rect 20 26 65 39)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 16 32)(line_width 3))
)
(port
(pt 0 56)
(input)
(text "wrreq" (rect 0 0 35 14)(font "Arial" (font_size 8)))
(text "wrreq" (rect 20 50 45 63)(font "Arial" (font_size 8)))
(line (pt 0 56)(pt 16 56)(line_width 1))
)
(port
(pt 0 72)
(input)
(text "wrclk" (rect 0 0 31 14)(font "Arial" (font_size 8)))
(text "wrclk" (rect 26 66 48 79)(font "Arial" (font_size 8)))
(line (pt 0 72)(pt 16 72)(line_width 1))
)
(port
(pt 0 104)
(input)
(text "rdreq" (rect 0 0 30 14)(font "Arial" (font_size 8)))
(text "rdreq" (rect 20 98 44 111)(font "Arial" (font_size 8)))
(line (pt 0 104)(pt 16 104)(line_width 1))
)
(port
(pt 0 120)
(input)
(text "rdclk" (rect 0 0 27 14)(font "Arial" (font_size 8)))
(text "rdclk" (rect 26 114 47 127)(font "Arial" (font_size 8)))
(line (pt 0 120)(pt 16 120)(line_width 1))
)
(port
(pt 0 144)
(input)
(text "aclr" (rect 0 0 21 14)(font "Arial" (font_size 8)))
(text "aclr" (rect 20 138 37 151)(font "Arial" (font_size 8)))
(line (pt 0 144)(pt 16 144)(line_width 1))
)
(port
(pt 160 72)
(output)
(text "wrusedw[9..0]" (rect 0 0 84 14)(font "Arial" (font_size 8)))
(text "wrusedw[9..0]" (rect 69 66 132 79)(font "Arial" (font_size 8)))
(line (pt 160 72)(pt 144 72)(line_width 3))
)
(port
(pt 160 96)
(output)
(text "q[31..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
(text "q[31..0]" (rect 105 90 141 103)(font "Arial" (font_size 8)))
(line (pt 160 96)(pt 144 96)(line_width 3))
)
(drawing
(text "8 bits x 1024 words" (rect 63 140 144 152)(font "Arial" ))
(line (pt 16 16)(pt 144 16)(line_width 1))
(line (pt 144 16)(pt 144 152)(line_width 1))
(line (pt 144 152)(pt 16 152)(line_width 1))
(line (pt 16 152)(pt 16 16)(line_width 1))
(line (pt 16 84)(pt 144 84)(line_width 1))
(line (pt 16 132)(pt 144 132)(line_width 1))
(line (pt 16 66)(pt 22 72)(line_width 1))
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(line (pt 16 114)(pt 22 120)(line_width 1))
(line (pt 22 120)(pt 16 126)(line_width 1))
)
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95
FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/dcfifo1.bsf
View File

@@ -1,95 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 160 168)
(text "dcfifo1" (rect 62 1 105 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 152 25 164)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
(text "data[31..0]" (rect 20 26 71 39)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 16 32)(line_width 3))
)
(port
(pt 0 56)
(input)
(text "wrreq" (rect 0 0 35 14)(font "Arial" (font_size 8)))
(text "wrreq" (rect 20 50 45 63)(font "Arial" (font_size 8)))
(line (pt 0 56)(pt 16 56)(line_width 1))
)
(port
(pt 0 72)
(input)
(text "wrclk" (rect 0 0 31 14)(font "Arial" (font_size 8)))
(text "wrclk" (rect 26 66 48 79)(font "Arial" (font_size 8)))
(line (pt 0 72)(pt 16 72)(line_width 1))
)
(port
(pt 0 104)
(input)
(text "rdreq" (rect 0 0 30 14)(font "Arial" (font_size 8)))
(text "rdreq" (rect 20 98 44 111)(font "Arial" (font_size 8)))
(line (pt 0 104)(pt 16 104)(line_width 1))
)
(port
(pt 0 120)
(input)
(text "rdclk" (rect 0 0 27 14)(font "Arial" (font_size 8)))
(text "rdclk" (rect 26 114 47 127)(font "Arial" (font_size 8)))
(line (pt 0 120)(pt 16 120)(line_width 1))
)
(port
(pt 0 144)
(input)
(text "aclr" (rect 0 0 21 14)(font "Arial" (font_size 8)))
(text "aclr" (rect 20 138 37 151)(font "Arial" (font_size 8)))
(line (pt 0 144)(pt 16 144)(line_width 1))
)
(port
(pt 160 96)
(output)
(text "q[7..0]" (rect 0 0 35 14)(font "Arial" (font_size 8)))
(text "q[7..0]" (rect 111 90 141 103)(font "Arial" (font_size 8)))
(line (pt 160 96)(pt 144 96)(line_width 3))
)
(port
(pt 160 120)
(output)
(text "rdusedw[9..0]" (rect 0 0 80 14)(font "Arial" (font_size 8)))
(text "rdusedw[9..0]" (rect 73 114 135 127)(font "Arial" (font_size 8)))
(line (pt 160 120)(pt 144 120)(line_width 3))
)
(drawing
(text "32 bits x 256 words" (rect 63 140 144 152)(font "Arial" ))
(line (pt 16 16)(pt 144 16)(line_width 1))
(line (pt 144 16)(pt 144 152)(line_width 1))
(line (pt 144 152)(pt 16 152)(line_width 1))
(line (pt 16 152)(pt 16 16)(line_width 1))
(line (pt 16 84)(pt 144 84)(line_width 1))
(line (pt 16 132)(pt 144 132)(line_width 1))
(line (pt 16 66)(pt 22 72)(line_width 1))
(line (pt 22 72)(pt 16 78)(line_width 1))
(line (pt 16 114)(pt 22 120)(line_width 1))
(line (pt 22 120)(pt 16 126)(line_width 1))
)
)

99
FPGA_Quartus_13.1/video/altddio_bidir0.bsf
View File

@@ -1,99 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 240 136)
(text "altddio_bidir0" (rect 82 1 171 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 120 25 132)(font "Arial" ))
(port
(pt 0 24)
(input)
(text "datain_h[31..0]" (rect 0 0 83 14)(font "Arial" (font_size 8)))
(text "datain_h[31..0]" (rect 4 11 76 24)(font "Arial" (font_size 8)))
(line (pt 0 24)(pt 88 24)(line_width 3))
)
(port
(pt 0 40)
(input)
(text "datain_l[31..0]" (rect 0 0 79 14)(font "Arial" (font_size 8)))
(text "datain_l[31..0]" (rect 4 27 73 40)(font "Arial" (font_size 8)))
(line (pt 0 40)(pt 88 40)(line_width 3))
)
(port
(pt 0 56)
(input)
(text "oe" (rect 0 0 14 14)(font "Arial" (font_size 8)))
(text "oe" (rect 4 43 16 56)(font "Arial" (font_size 8)))
(line (pt 0 56)(pt 88 56)(line_width 1))
)
(port
(pt 0 72)
(input)
(text "inclock" (rect 0 0 38 14)(font "Arial" (font_size 8)))
(text "inclock" (rect 4 59 36 72)(font "Arial" (font_size 8)))
(line (pt 0 72)(pt 88 72)(line_width 1))
)
(port
(pt 0 88)
(input)
(text "outclock" (rect 0 0 47 14)(font "Arial" (font_size 8)))
(text "outclock" (rect 4 75 42 88)(font "Arial" (font_size 8)))
(line (pt 0 88)(pt 88 88)(line_width 1))
)
(port
(pt 240 24)
(output)
(text "dataout_h[31..0]" (rect 0 0 92 14)(font "Arial" (font_size 8)))
(text "dataout_h[31..0]" (rect 159 11 237 24)(font "Arial" (font_size 8)))
(line (pt 240 24)(pt 144 24)(line_width 3))
)
(port
(pt 240 40)
(output)
(text "dataout_l[31..0]" (rect 0 0 87 14)(font "Arial" (font_size 8)))
(text "dataout_l[31..0]" (rect 163 27 238 40)(font "Arial" (font_size 8)))
(line (pt 240 40)(pt 144 40)(line_width 3))
)
(port
(pt 240 72)
(output)
(text "combout[31..0]" (rect 0 0 83 14)(font "Arial" (font_size 8)))
(text "combout[31..0]" (rect 166 59 237 72)(font "Arial" (font_size 8)))
(line (pt 240 72)(pt 144 72)(line_width 3))
)
(port
(pt 240 56)
(bidir)
(text "padio[31..0]" (rect 0 0 66 14)(font "Arial" (font_size 8)))
(text "padio[31..0]" (rect 181 43 238 56)(font "Arial" (font_size 8)))
(line (pt 240 56)(pt 144 56)(line_width 3))
)
(drawing
(text "ddio" (rect 108 27 129 40)(font "Arial" (font_size 8)))
(text "bidir" (rect 108 42 129 55)(font "Arial" (font_size 8)))
(text "power up" (rect 92 90 129 102)(font "Arial" ))
(text "low" (rect 92 100 105 112)(font "Arial" ))
(line (pt 88 16)(pt 144 16)(line_width 1))
(line (pt 144 16)(pt 144 112)(line_width 1))
(line (pt 144 112)(pt 88 112)(line_width 1))
(line (pt 88 112)(pt 88 16)(line_width 1))
)
)

64
FPGA_Quartus_13.1/video/altddio_out0.bsf
View File

@@ -1,64 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 232 120)
(text "altddio_out0" (rect 81 1 163 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 104 25 116)(font "Arial" ))
(port
(pt 0 24)
(input)
(text "datain_h[3..0]" (rect 0 0 76 14)(font "Arial" (font_size 8)))
(text "datain_h[3..0]" (rect 4 11 70 24)(font "Arial" (font_size 8)))
(line (pt 0 24)(pt 88 24)(line_width 3))
)
(port
(pt 0 40)
(input)
(text "datain_l[3..0]" (rect 0 0 71 14)(font "Arial" (font_size 8)))
(text "datain_l[3..0]" (rect 4 27 67 40)(font "Arial" (font_size 8)))
(line (pt 0 40)(pt 88 40)(line_width 3))
)
(port
(pt 0 56)
(input)
(text "outclock" (rect 0 0 47 14)(font "Arial" (font_size 8)))
(text "outclock" (rect 4 43 42 56)(font "Arial" (font_size 8)))
(line (pt 0 56)(pt 88 56)(line_width 1))
)
(port
(pt 232 24)
(output)
(text "dataout[3..0]" (rect 0 0 70 14)(font "Arial" (font_size 8)))
(text "dataout[3..0]" (rect 169 11 229 24)(font "Arial" (font_size 8)))
(line (pt 232 24)(pt 152 24)(line_width 3))
)
(drawing
(text "ddio" (rect 110 27 131 40)(font "Arial" (font_size 8)))
(text "output" (rect 105 42 135 55)(font "Arial" (font_size 8)))
(text "power up" (rect 92 74 129 86)(font "Arial" ))
(text "high" (rect 92 84 109 96)(font "Arial" ))
(line (pt 88 16)(pt 152 16)(line_width 1))
(line (pt 152 16)(pt 152 96)(line_width 1))
(line (pt 152 96)(pt 88 96)(line_width 1))
(line (pt 88 96)(pt 88 16)(line_width 1))
)
)

64
FPGA_Quartus_13.1/video/altddio_out1.bsf
View File

@@ -1,64 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 232 120)
(text "altddio_out1" (rect 81 1 163 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 104 25 116)(font "Arial" ))
(port
(pt 0 24)
(input)
(text "datain_h" (rect 0 0 48 14)(font "Arial" (font_size 8)))
(text "datain_h" (rect 4 11 46 24)(font "Arial" (font_size 8)))
(line (pt 0 24)(pt 88 24)(line_width 1))
)
(port
(pt 0 40)
(input)
(text "datain_l" (rect 0 0 43 14)(font "Arial" (font_size 8)))
(text "datain_l" (rect 4 27 43 40)(font "Arial" (font_size 8)))
(line (pt 0 40)(pt 88 40)(line_width 1))
)
(port
(pt 0 56)
(input)
(text "outclock" (rect 0 0 47 14)(font "Arial" (font_size 8)))
(text "outclock" (rect 4 43 42 56)(font "Arial" (font_size 8)))
(line (pt 0 56)(pt 88 56)(line_width 1))
)
(port
(pt 232 24)
(output)
(text "dataout" (rect 0 0 42 14)(font "Arial" (font_size 8)))
(text "dataout" (rect 193 11 229 24)(font "Arial" (font_size 8)))
(line (pt 232 24)(pt 152 24)(line_width 1))
)
(drawing
(text "ddio" (rect 110 27 131 40)(font "Arial" (font_size 8)))
(text "output" (rect 105 42 135 55)(font "Arial" (font_size 8)))
(text "power up" (rect 92 74 129 86)(font "Arial" ))
(text "low" (rect 92 84 105 96)(font "Arial" ))
(line (pt 88 16)(pt 152 16)(line_width 1))
(line (pt 152 16)(pt 152 96)(line_width 1))
(line (pt 152 96)(pt 88 96)(line_width 1))
(line (pt 88 96)(pt 88 16)(line_width 1))
)
)

64
FPGA_Quartus_13.1/video/altddio_out2.bsf
View File

@@ -1,64 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 232 120)
(text "altddio_out2" (rect 81 1 163 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 104 25 116)(font "Arial" ))
(port
(pt 0 24)
(input)
(text "datain_h[23..0]" (rect 0 0 83 14)(font "Arial" (font_size 8)))
(text "datain_h[23..0]" (rect 4 11 76 24)(font "Arial" (font_size 8)))
(line (pt 0 24)(pt 88 24)(line_width 3))
)
(port
(pt 0 40)
(input)
(text "datain_l[23..0]" (rect 0 0 79 14)(font "Arial" (font_size 8)))
(text "datain_l[23..0]" (rect 4 27 73 40)(font "Arial" (font_size 8)))
(line (pt 0 40)(pt 88 40)(line_width 3))
)
(port
(pt 0 56)
(input)
(text "outclock" (rect 0 0 47 14)(font "Arial" (font_size 8)))
(text "outclock" (rect 4 43 42 56)(font "Arial" (font_size 8)))
(line (pt 0 56)(pt 88 56)(line_width 1))
)
(port
(pt 232 24)
(output)
(text "dataout[23..0]" (rect 0 0 77 14)(font "Arial" (font_size 8)))
(text "dataout[23..0]" (rect 163 11 229 24)(font "Arial" (font_size 8)))
(line (pt 232 24)(pt 152 24)(line_width 3))
)
(drawing
(text "ddio" (rect 110 27 131 40)(font "Arial" (font_size 8)))
(text "output" (rect 105 42 135 55)(font "Arial" (font_size 8)))
(text "power up" (rect 92 74 129 86)(font "Arial" ))
(text "low" (rect 92 84 105 96)(font "Arial" ))
(line (pt 88 16)(pt 152 16)(line_width 1))
(line (pt 152 16)(pt 152 96)(line_width 1))
(line (pt 152 96)(pt 88 96)(line_width 1))
(line (pt 88 96)(pt 88 16)(line_width 1))
)
)

173
FPGA_Quartus_13.1/video/altdpram0.bsf
View File

@@ -1,173 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 256 208)
(text "altdpram0" (rect 100 1 167 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 192 25 204)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "data_a[2..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
(text "data_a[2..0]" (rect 4 19 61 32)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 112 32)(line_width 3))
)
(port
(pt 0 48)
(input)
(text "address_a[3..0]" (rect 0 0 89 14)(font "Arial" (font_size 8)))
(text "address_a[3..0]" (rect 4 35 75 48)(font "Arial" (font_size 8)))
(line (pt 0 48)(pt 112 48)(line_width 3))
)
(port
(pt 0 64)
(input)
(text "wren_a" (rect 0 0 44 14)(font "Arial" (font_size 8)))
(text "wren_a" (rect 4 51 38 64)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 112 64)(line_width 1))
)
(port
(pt 0 96)
(input)
(text "data_b[2..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
(text "data_b[2..0]" (rect 4 83 61 96)(font "Arial" (font_size 8)))
(line (pt 0 96)(pt 112 96)(line_width 3))
)
(port
(pt 0 112)
(input)
(text "address_b[3..0]" (rect 0 0 89 14)(font "Arial" (font_size 8)))
(text "address_b[3..0]" (rect 4 99 75 112)(font "Arial" (font_size 8)))
(line (pt 0 112)(pt 112 112)(line_width 3))
)
(port
(pt 0 128)
(input)
(text "wren_b" (rect 0 0 44 14)(font "Arial" (font_size 8)))
(text "wren_b" (rect 4 115 38 128)(font "Arial" (font_size 8)))
(line (pt 0 128)(pt 112 128)(line_width 1))
)
(port
(pt 0 160)
(input)
(text "clock_a" (rect 0 0 43 14)(font "Arial" (font_size 8)))
(text "clock_a" (rect 4 147 39 160)(font "Arial" (font_size 8)))
(line (pt 0 160)(pt 176 160)(line_width 1))
)
(port
(pt 0 176)
(input)
(text "clock_b" (rect 0 0 43 14)(font "Arial" (font_size 8)))
(text "clock_b" (rect 4 163 39 176)(font "Arial" (font_size 8)))
(line (pt 0 176)(pt 181 176)(line_width 1))
)
(port
(pt 256 32)
(output)
(text "q_a[2..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
(text "q_a[2..0]" (rect 211 19 253 32)(font "Arial" (font_size 8)))
(line (pt 256 32)(pt 192 32)(line_width 3))
)
(port
(pt 256 96)
(output)
(text "q_b[2..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
(text "q_b[2..0]" (rect 211 83 253 96)(font "Arial" (font_size 8)))
(line (pt 256 96)(pt 192 96)(line_width 3))
)
(drawing
(text "16 Word(s)" (rect 136 61 148 107)(font "Arial" )(vertical))
(text "RAM" (rect 149 74 161 94)(font "Arial" )(vertical))
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173
FPGA_Quartus_13.1/video/altdpram1.bsf
View File

@@ -1,173 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
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173
FPGA_Quartus_13.1/video/altdpram2.bsf
View File

@@ -1,173 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
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56
FPGA_Quartus_13.1/video/lpm_bustri0.bsf
View File

@@ -1,56 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
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56
FPGA_Quartus_13.1/video/lpm_bustri1.bsf
View File

@@ -1,56 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
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(line (pt 32 32)(pt 32 16)(line_width 1))
(line (pt 58 28)(pt 66 20)(line_width 1))
(line (pt 10 28)(pt 18 20)(line_width 1))
)
)

56
FPGA_Quartus_13.1/video/lpm_bustri2.bsf
View File

@@ -1,56 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 80 40)
(text "lpm_bustri2" (rect 7 1 86 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 24 25 36)(font "Arial" ))
(port
(pt 40 40)
(input)
(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
(text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible))
(line (pt 40 40)(pt 40 28)(line_width 1))
)
(port
(pt 0 24)
(input)
(text "data[17..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
(text "data[17..0]" (rect -3 -27 10 24)(font "Arial" (font_size 8))(invisible))
(line (pt 0 24)(pt 32 24)(line_width 3))
)
(port
(pt 80 24)
(bidir)
(text "tridata[17..0]" (rect 0 0 70 14)(font "Arial" (font_size 8)))
(text "tridata[17..0]" (rect 84 -36 97 24)(font "Arial" (font_size 8))(invisible))
(line (pt 80 24)(pt 48 24)(line_width 3))
)
(drawing
(text "18" (rect 61 25 71 37)(font "Arial" ))
(text "18" (rect 13 25 23 37)(font "Arial" ))
(line (pt 32 16)(pt 48 24)(line_width 1))
(line (pt 48 24)(pt 32 32)(line_width 1))
(line (pt 32 32)(pt 32 16)(line_width 1))
(line (pt 56 28)(pt 64 20)(line_width 1))
(line (pt 8 28)(pt 16 20)(line_width 1))
)
)

56
FPGA_Quartus_13.1/video/lpm_bustri3.bsf
View File

@@ -1,56 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 80 40)
(text "lpm_bustri3" (rect 7 1 86 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 24 25 36)(font "Arial" ))
(port
(pt 40 40)
(input)
(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
(text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible))
(line (pt 40 40)(pt 40 28)(line_width 1))
)
(port
(pt 0 24)
(input)
(text "data[5..0]" (rect 0 0 53 14)(font "Arial" (font_size 8)))
(text "data[5..0]" (rect -3 -21 10 24)(font "Arial" (font_size 8))(invisible))
(line (pt 0 24)(pt 32 24)(line_width 3))
)
(port
(pt 80 24)
(bidir)
(text "tridata[5..0]" (rect 0 0 63 14)(font "Arial" (font_size 8)))
(text "tridata[5..0]" (rect 84 -30 97 24)(font "Arial" (font_size 8))(invisible))
(line (pt 80 24)(pt 48 24)(line_width 3))
)
(drawing
(text "6" (rect 63 25 68 37)(font "Arial" ))
(text "6" (rect 15 25 20 37)(font "Arial" ))
(line (pt 32 16)(pt 48 24)(line_width 1))
(line (pt 48 24)(pt 32 32)(line_width 1))
(line (pt 32 32)(pt 32 16)(line_width 1))
(line (pt 58 28)(pt 66 20)(line_width 1))
(line (pt 10 28)(pt 18 20)(line_width 1))
)
)

56
FPGA_Quartus_13.1/video/lpm_bustri4.bsf
View File

@@ -1,56 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 80 40)
(text "lpm_bustri4" (rect 7 1 86 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 24 25 36)(font "Arial" ))
(port
(pt 40 40)
(input)
(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
(text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible))
(line (pt 40 40)(pt 40 28)(line_width 1))
)
(port
(pt 0 24)
(input)
(text "data[4..0]" (rect 0 0 53 14)(font "Arial" (font_size 8)))
(text "data[4..0]" (rect -3 -21 10 24)(font "Arial" (font_size 8))(invisible))
(line (pt 0 24)(pt 32 24)(line_width 3))
)
(port
(pt 80 24)
(bidir)
(text "tridata[4..0]" (rect 0 0 63 14)(font "Arial" (font_size 8)))
(text "tridata[4..0]" (rect 84 -30 97 24)(font "Arial" (font_size 8))(invisible))
(line (pt 80 24)(pt 48 24)(line_width 3))
)
(drawing
(text "5" (rect 63 25 68 37)(font "Arial" ))
(text "5" (rect 15 25 20 37)(font "Arial" ))
(line (pt 32 16)(pt 48 24)(line_width 1))
(line (pt 48 24)(pt 32 32)(line_width 1))
(line (pt 32 32)(pt 32 16)(line_width 1))
(line (pt 58 28)(pt 66 20)(line_width 1))
(line (pt 10 28)(pt 18 20)(line_width 1))
)
)

56
FPGA_Quartus_13.1/video/lpm_bustri5.bsf
View File

@@ -1,56 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 80 40)
(text "lpm_bustri5" (rect 7 1 86 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 24 25 36)(font "Arial" ))
(port
(pt 40 40)
(input)
(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
(text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible))
(line (pt 40 40)(pt 40 28)(line_width 1))
)
(port
(pt 0 24)
(input)
(text "data[7..0]" (rect 0 0 53 14)(font "Arial" (font_size 8)))
(text "data[7..0]" (rect -3 -21 10 24)(font "Arial" (font_size 8))(invisible))
(line (pt 0 24)(pt 32 24)(line_width 3))
)
(port
(pt 80 24)
(bidir)
(text "tridata[7..0]" (rect 0 0 63 14)(font "Arial" (font_size 8)))
(text "tridata[7..0]" (rect 84 -30 97 24)(font "Arial" (font_size 8))(invisible))
(line (pt 80 24)(pt 48 24)(line_width 3))
)
(drawing
(text "8" (rect 63 25 68 37)(font "Arial" ))
(text "8" (rect 15 25 20 37)(font "Arial" ))
(line (pt 32 16)(pt 48 24)(line_width 1))
(line (pt 48 24)(pt 32 32)(line_width 1))
(line (pt 32 32)(pt 32 16)(line_width 1))
(line (pt 58 28)(pt 66 20)(line_width 1))
(line (pt 10 28)(pt 18 20)(line_width 1))
)
)

56
FPGA_Quartus_13.1/video/lpm_bustri6.bsf
View File

@@ -1,56 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 80 40)
(text "lpm_bustri6" (rect 7 1 86 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 24 25 36)(font "Arial" ))
(port
(pt 40 40)
(input)
(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
(text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible))
(line (pt 40 40)(pt 40 28)(line_width 1))
)
(port
(pt 0 24)
(input)
(text "data[23..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
(text "data[23..0]" (rect -3 -27 10 24)(font "Arial" (font_size 8))(invisible))
(line (pt 0 24)(pt 32 24)(line_width 3))
)
(port
(pt 80 24)
(bidir)
(text "tridata[23..0]" (rect 0 0 70 14)(font "Arial" (font_size 8)))
(text "tridata[23..0]" (rect 84 -36 97 24)(font "Arial" (font_size 8))(invisible))
(line (pt 80 24)(pt 48 24)(line_width 3))
)
(drawing
(text "24" (rect 61 25 71 37)(font "Arial" ))
(text "24" (rect 13 25 23 37)(font "Arial" ))
(line (pt 32 16)(pt 48 24)(line_width 1))
(line (pt 48 24)(pt 32 32)(line_width 1))
(line (pt 32 32)(pt 32 16)(line_width 1))
(line (pt 56 28)(pt 64 20)(line_width 1))
(line (pt 8 28)(pt 16 20)(line_width 1))
)
)

56
FPGA_Quartus_13.1/video/lpm_bustri7.bsf
View File

@@ -1,56 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 80 40)
(text "lpm_bustri7" (rect 7 1 86 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 24 25 36)(font "Arial" ))
(port
(pt 40 40)
(input)
(text "enabledt" (rect 0 0 48 14)(font "Arial" (font_size 8)))
(text "enabledt" (rect 40 -6 53 36)(font "Arial" (font_size 8))(invisible))
(line (pt 40 40)(pt 40 28)(line_width 1))
)
(port
(pt 0 24)
(input)
(text "data[3..0]" (rect 0 0 53 14)(font "Arial" (font_size 8)))
(text "data[3..0]" (rect -3 -21 10 24)(font "Arial" (font_size 8))(invisible))
(line (pt 0 24)(pt 32 24)(line_width 3))
)
(port
(pt 80 24)
(bidir)
(text "tridata[3..0]" (rect 0 0 63 14)(font "Arial" (font_size 8)))
(text "tridata[3..0]" (rect 84 -30 97 24)(font "Arial" (font_size 8))(invisible))
(line (pt 80 24)(pt 48 24)(line_width 3))
)
(drawing
(text "4" (rect 63 25 68 37)(font "Arial" ))
(text "4" (rect 15 25 20 37)(font "Arial" ))
(line (pt 32 16)(pt 48 24)(line_width 1))
(line (pt 48 24)(pt 32 32)(line_width 1))
(line (pt 32 32)(pt 32 16)(line_width 1))
(line (pt 58 28)(pt 66 20)(line_width 1))
(line (pt 10 28)(pt 18 20)(line_width 1))
)
)

54
FPGA_Quartus_13.1/video/lpm_compare1.bsf
View File

@@ -1,54 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 128 96)
(text "lpm_compare1" (rect 22 1 122 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 80 25 92)(font "Arial" ))
(port
(pt 0 48)
(input)
(text "dataa[10..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
(text "dataa[10..0]" (rect 20 42 77 55)(font "Arial" (font_size 8)))
(line (pt 0 48)(pt 16 48)(line_width 3))
)
(port
(pt 0 64)
(input)
(text "datab[10..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
(text "datab[10..0]" (rect 20 58 77 71)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 16 64)(line_width 3))
)
(port
(pt 128 56)
(output)
(text "agb" (rect 0 0 21 14)(font "Arial" (font_size 8)))
(text "agb" (rect 91 50 109 63)(font "Arial" (font_size 8)))
(line (pt 128 56)(pt 112 56)(line_width 1))
)
(drawing
(text "unsigned compare" (rect 36 17 112 29)(font "Arial" ))
(line (pt 16 16)(pt 112 16)(line_width 1))
(line (pt 112 16)(pt 112 80)(line_width 1))
(line (pt 112 80)(pt 16 80)(line_width 1))
(line (pt 16 80)(pt 16 16)(line_width 1))
)
)

42
FPGA_Quartus_13.1/video/lpm_constant0.bsf
View File

@@ -1,42 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 96 48)
(text "lpm_constant0" (rect 6 1 106 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 32 25 44)(font "Arial" ))
(port
(pt 96 24)
(output)
(text "result[4..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
(text "result[4..0]" (rect 93 -25 106 24)(font "Arial" (font_size 8))(invisible))
(line (pt 96 24)(pt 80 24)(line_width 3))
)
(drawing
(text "0" (rect 75 18 80 30)(font "Arial" ))
(text "5" (rect 87 25 92 37)(font "Arial" ))
(line (pt 16 16)(pt 80 16)(line_width 1))
(line (pt 80 16)(pt 80 32)(line_width 1))
(line (pt 80 32)(pt 16 32)(line_width 1))
(line (pt 16 32)(pt 16 16)(line_width 1))
(line (pt 82 28)(pt 90 20)(line_width 1))
)
)

42
FPGA_Quartus_13.1/video/lpm_constant1.bsf
View File

@@ -1,42 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 96 48)
(text "lpm_constant1" (rect 6 1 106 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 32 25 44)(font "Arial" ))
(port
(pt 96 24)
(output)
(text "result[1..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
(text "result[1..0]" (rect 93 -25 106 24)(font "Arial" (font_size 8))(invisible))
(line (pt 96 24)(pt 80 24)(line_width 3))
)
(drawing
(text "0" (rect 75 18 80 30)(font "Arial" ))
(text "2" (rect 87 25 92 37)(font "Arial" ))
(line (pt 16 16)(pt 80 16)(line_width 1))
(line (pt 80 16)(pt 80 32)(line_width 1))
(line (pt 80 32)(pt 16 32)(line_width 1))
(line (pt 16 32)(pt 16 16)(line_width 1))
(line (pt 82 28)(pt 90 20)(line_width 1))
)
)

42
FPGA_Quartus_13.1/video/lpm_constant2.bsf
View File

@@ -1,42 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 96 48)
(text "lpm_constant2" (rect 6 1 106 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 32 25 44)(font "Arial" ))
(port
(pt 96 24)
(output)
(text "result[7..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
(text "result[7..0]" (rect 93 -25 106 24)(font "Arial" (font_size 8))(invisible))
(line (pt 96 24)(pt 80 24)(line_width 3))
)
(drawing
(text "0" (rect 75 18 80 30)(font "Arial" ))
(text "8" (rect 87 25 92 37)(font "Arial" ))
(line (pt 16 16)(pt 80 16)(line_width 1))
(line (pt 80 16)(pt 80 32)(line_width 1))
(line (pt 80 32)(pt 16 32)(line_width 1))
(line (pt 16 32)(pt 16 16)(line_width 1))
(line (pt 82 28)(pt 90 20)(line_width 1))
)
)

42
FPGA_Quartus_13.1/video/lpm_constant3.bsf
View File

@@ -1,42 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 96 48)
(text "lpm_constant3" (rect 6 1 106 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 32 25 44)(font "Arial" ))
(port
(pt 96 24)
(output)
(text "result[6..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
(text "result[6..0]" (rect 93 -25 106 24)(font "Arial" (font_size 8))(invisible))
(line (pt 96 24)(pt 80 24)(line_width 3))
)
(drawing
(text "0" (rect 75 18 80 30)(font "Arial" ))
(text "7" (rect 87 25 92 37)(font "Arial" ))
(line (pt 16 16)(pt 80 16)(line_width 1))
(line (pt 80 16)(pt 80 32)(line_width 1))
(line (pt 80 32)(pt 16 32)(line_width 1))
(line (pt 16 32)(pt 16 16)(line_width 1))
(line (pt 82 28)(pt 90 20)(line_width 1))
)
)

42
FPGA_Quartus_13.1/video/lpm_constant4.bsf
View File

@@ -1,42 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 96 48)
(text "lpm_constant4" (rect 6 1 106 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 32 25 44)(font "Arial" ))
(port
(pt 96 24)
(output)
(text "result[10..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
(text "result[10..0]" (rect 93 -31 106 24)(font "Arial" (font_size 8))(invisible))
(line (pt 96 24)(pt 80 24)(line_width 3))
)
(drawing
(text "2040" (rect 60 18 80 30)(font "Arial" ))
(text "11" (rect 85 25 95 37)(font "Arial" ))
(line (pt 16 16)(pt 80 16)(line_width 1))
(line (pt 80 16)(pt 80 32)(line_width 1))
(line (pt 80 32)(pt 16 32)(line_width 1))
(line (pt 16 32)(pt 16 16)(line_width 1))
(line (pt 80 28)(pt 88 20)(line_width 1))
)
)

63
FPGA_Quartus_13.1/video/lpm_ff0.bsf
View File

@@ -1,63 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 144 96)
(text "lpm_ff0" (rect 52 1 100 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 80 25 92)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
(text "data[31..0]" (rect 20 26 71 39)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 16 32)(line_width 3))
)
(port
(pt 0 48)
(input)
(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
(text "clock" (rect 26 42 49 55)(font "Arial" (font_size 8)))
(line (pt 0 48)(pt 16 48)(line_width 1))
)
(port
(pt 0 64)
(input)
(text "enable" (rect 0 0 37 14)(font "Arial" (font_size 8)))
(text "enable" (rect 20 58 53 71)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 16 64)(line_width 1))
)
(port
(pt 144 56)
(output)
(text "q[31..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
(text "q[31..0]" (rect 89 50 125 63)(font "Arial" (font_size 8)))
(line (pt 144 56)(pt 128 56)(line_width 3))
)
(drawing
(text "DFF" (rect 109 17 128 29)(font "Arial" ))
(line (pt 16 16)(pt 128 16)(line_width 1))
(line (pt 128 16)(pt 128 80)(line_width 1))
(line (pt 128 80)(pt 16 80)(line_width 1))
(line (pt 16 80)(pt 16 16)(line_width 1))
(line (pt 16 42)(pt 22 48)(line_width 1))
(line (pt 22 48)(pt 16 54)(line_width 1))
)
)

56
FPGA_Quartus_13.1/video/lpm_ff1.bsf
View File

@@ -1,56 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 144 80)
(text "lpm_ff1" (rect 52 1 100 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 64 25 76)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
(text "data[31..0]" (rect 20 26 71 39)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 16 32)(line_width 3))
)
(port
(pt 0 48)
(input)
(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
(text "clock" (rect 26 42 49 55)(font "Arial" (font_size 8)))
(line (pt 0 48)(pt 16 48)(line_width 1))
)
(port
(pt 144 48)
(output)
(text "q[31..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
(text "q[31..0]" (rect 89 42 125 55)(font "Arial" (font_size 8)))
(line (pt 144 48)(pt 128 48)(line_width 3))
)
(drawing
(text "DFF" (rect 109 17 128 29)(font "Arial" ))
(line (pt 16 16)(pt 128 16)(line_width 1))
(line (pt 128 16)(pt 128 64)(line_width 1))
(line (pt 128 64)(pt 16 64)(line_width 1))
(line (pt 16 64)(pt 16 16)(line_width 1))
(line (pt 16 42)(pt 22 48)(line_width 1))
(line (pt 22 48)(pt 16 54)(line_width 1))
)
)

56
FPGA_Quartus_13.1/video/lpm_ff2.bsf
View File

@@ -1,56 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 144 80)
(text "lpm_ff2" (rect 52 1 100 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 64 25 76)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "data[127..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
(text "data[127..0]" (rect 20 26 77 39)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 16 32)(line_width 3))
)
(port
(pt 0 48)
(input)
(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
(text "clock" (rect 26 42 49 55)(font "Arial" (font_size 8)))
(line (pt 0 48)(pt 16 48)(line_width 1))
)
(port
(pt 144 48)
(output)
(text "q[127..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
(text "q[127..0]" (rect 83 42 125 55)(font "Arial" (font_size 8)))
(line (pt 144 48)(pt 128 48)(line_width 3))
)
(drawing
(text "DFF" (rect 109 17 128 29)(font "Arial" ))
(line (pt 16 16)(pt 128 16)(line_width 1))
(line (pt 128 16)(pt 128 64)(line_width 1))
(line (pt 128 64)(pt 16 64)(line_width 1))
(line (pt 16 64)(pt 16 16)(line_width 1))
(line (pt 16 42)(pt 22 48)(line_width 1))
(line (pt 22 48)(pt 16 54)(line_width 1))
)
)

56
FPGA_Quartus_13.1/video/lpm_ff3.bsf
View File

@@ -1,56 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 144 80)
(text "lpm_ff3" (rect 52 1 100 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 64 25 76)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "data[23..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
(text "data[23..0]" (rect 20 26 71 39)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 16 32)(line_width 3))
)
(port
(pt 0 48)
(input)
(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
(text "clock" (rect 26 42 49 55)(font "Arial" (font_size 8)))
(line (pt 0 48)(pt 16 48)(line_width 1))
)
(port
(pt 144 48)
(output)
(text "q[23..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
(text "q[23..0]" (rect 89 42 125 55)(font "Arial" (font_size 8)))
(line (pt 144 48)(pt 128 48)(line_width 3))
)
(drawing
(text "DFF" (rect 109 17 128 29)(font "Arial" ))
(line (pt 16 16)(pt 128 16)(line_width 1))
(line (pt 128 16)(pt 128 64)(line_width 1))
(line (pt 128 64)(pt 16 64)(line_width 1))
(line (pt 16 64)(pt 16 16)(line_width 1))
(line (pt 16 42)(pt 22 48)(line_width 1))
(line (pt 22 48)(pt 16 54)(line_width 1))
)
)

56
FPGA_Quartus_13.1/video/lpm_ff4.bsf
View File

@@ -1,56 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 144 80)
(text "lpm_ff4" (rect 52 1 100 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 64 25 76)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
(text "data[15..0]" (rect 20 26 71 39)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 16 32)(line_width 3))
)
(port
(pt 0 48)
(input)
(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
(text "clock" (rect 26 42 49 55)(font "Arial" (font_size 8)))
(line (pt 0 48)(pt 16 48)(line_width 1))
)
(port
(pt 144 48)
(output)
(text "q[15..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
(text "q[15..0]" (rect 89 42 125 55)(font "Arial" (font_size 8)))
(line (pt 144 48)(pt 128 48)(line_width 3))
)
(drawing
(text "DFF" (rect 109 17 128 29)(font "Arial" ))
(line (pt 16 16)(pt 128 16)(line_width 1))
(line (pt 128 16)(pt 128 64)(line_width 1))
(line (pt 128 64)(pt 16 64)(line_width 1))
(line (pt 16 64)(pt 16 16)(line_width 1))
(line (pt 16 42)(pt 22 48)(line_width 1))
(line (pt 22 48)(pt 16 54)(line_width 1))
)
)

56
FPGA_Quartus_13.1/video/lpm_ff5.bsf
View File

@@ -1,56 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 144 80)
(text "lpm_ff5" (rect 52 1 100 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 64 25 76)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "data[7..0]" (rect 0 0 53 14)(font "Arial" (font_size 8)))
(text "data[7..0]" (rect 20 26 65 39)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 16 32)(line_width 3))
)
(port
(pt 0 48)
(input)
(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
(text "clock" (rect 26 42 49 55)(font "Arial" (font_size 8)))
(line (pt 0 48)(pt 16 48)(line_width 1))
)
(port
(pt 144 48)
(output)
(text "q[7..0]" (rect 0 0 35 14)(font "Arial" (font_size 8)))
(text "q[7..0]" (rect 95 42 125 55)(font "Arial" (font_size 8)))
(line (pt 144 48)(pt 128 48)(line_width 3))
)
(drawing
(text "DFF" (rect 109 17 128 29)(font "Arial" ))
(line (pt 16 16)(pt 128 16)(line_width 1))
(line (pt 128 16)(pt 128 64)(line_width 1))
(line (pt 128 64)(pt 16 64)(line_width 1))
(line (pt 16 64)(pt 16 16)(line_width 1))
(line (pt 16 42)(pt 22 48)(line_width 1))
(line (pt 22 48)(pt 16 54)(line_width 1))
)
)

63
FPGA_Quartus_13.1/video/lpm_ff6.bsf
View File

@@ -1,63 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 144 96)
(text "lpm_ff6" (rect 52 1 100 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 80 25 92)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "data[127..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
(text "data[127..0]" (rect 20 26 77 39)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 16 32)(line_width 3))
)
(port
(pt 0 48)
(input)
(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
(text "clock" (rect 26 42 49 55)(font "Arial" (font_size 8)))
(line (pt 0 48)(pt 16 48)(line_width 1))
)
(port
(pt 0 64)
(input)
(text "enable" (rect 0 0 37 14)(font "Arial" (font_size 8)))
(text "enable" (rect 20 58 53 71)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 16 64)(line_width 1))
)
(port
(pt 144 56)
(output)
(text "q[127..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
(text "q[127..0]" (rect 83 50 125 63)(font "Arial" (font_size 8)))
(line (pt 144 56)(pt 128 56)(line_width 3))
)
(drawing
(text "DFF" (rect 109 17 128 29)(font "Arial" ))
(line (pt 16 16)(pt 128 16)(line_width 1))
(line (pt 128 16)(pt 128 80)(line_width 1))
(line (pt 128 80)(pt 16 80)(line_width 1))
(line (pt 16 80)(pt 16 16)(line_width 1))
(line (pt 16 42)(pt 22 48)(line_width 1))
(line (pt 22 48)(pt 16 54)(line_width 1))
)
)

79
FPGA_Quartus_13.1/video/lpm_fifoDZ.bsf
View File

@@ -1,79 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2010 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 160 144)
(text "lpm_fifoDZ" (rect 41 2 133 21)(font "Arial" (font_size 10)))
(text "inst" (rect 8 125 31 140)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "data[127..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
(text "data[127..0]" (rect 20 24 89 40)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 16 32)(line_width 3))
)
(port
(pt 0 56)
(input)
(text "wrreq" (rect 0 0 36 16)(font "Arial" (font_size 8)))
(text "wrreq" (rect 20 48 51 64)(font "Arial" (font_size 8)))
(line (pt 0 56)(pt 16 56)(line_width 1))
)
(port
(pt 0 72)
(input)
(text "rdreq" (rect 0 0 34 16)(font "Arial" (font_size 8)))
(text "rdreq" (rect 20 64 49 80)(font "Arial" (font_size 8)))
(line (pt 0 72)(pt 16 72)(line_width 1))
)
(port
(pt 0 96)
(input)
(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
(text "clock" (rect 26 88 57 104)(font "Arial" (font_size 8)))
(line (pt 0 96)(pt 16 96)(line_width 1))
)
(port
(pt 0 120)
(input)
(text "aclr" (rect 0 0 24 16)(font "Arial" (font_size 8)))
(text "aclr" (rect 20 112 41 128)(font "Arial" (font_size 8)))
(line (pt 0 120)(pt 16 120)(line_width 1))
)
(port
(pt 160 32)
(output)
(text "q[127..0]" (rect 0 0 60 16)(font "Arial" (font_size 8)))
(text "q[127..0]" (rect 90 24 141 40)(font "Arial" (font_size 8)))
(line (pt 160 32)(pt 144 32)(line_width 3))
)
(drawing
(text "(ack)" (rect 51 67 76 81)(font "Arial" ))
(text "128 bits x 128 words" (rect 31 114 134 128)(font "Arial" ))
(line (pt 16 16)(pt 144 16)(line_width 1))
(line (pt 144 16)(pt 144 128)(line_width 1))
(line (pt 144 128)(pt 16 128)(line_width 1))
(line (pt 16 128)(pt 16 16)(line_width 1))
(line (pt 16 108)(pt 144 108)(line_width 1))
(line (pt 16 90)(pt 22 96)(line_width 1))
(line (pt 22 96)(pt 16 102)(line_width 1))
)
)

102
FPGA_Quartus_13.1/video/lpm_fifo_dc0.bsf
View File

@@ -1,102 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 160 168)
(text "lpm_fifo_dc0" (rect 44 1 128 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 152 25 164)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "data[127..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
(text "data[127..0]" (rect 20 26 77 39)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 16 32)(line_width 3))
)
(port
(pt 0 56)
(input)
(text "wrreq" (rect 0 0 35 14)(font "Arial" (font_size 8)))
(text "wrreq" (rect 20 50 45 63)(font "Arial" (font_size 8)))
(line (pt 0 56)(pt 16 56)(line_width 1))
)
(port
(pt 0 72)
(input)
(text "wrclk" (rect 0 0 31 14)(font "Arial" (font_size 8)))
(text "wrclk" (rect 26 66 48 79)(font "Arial" (font_size 8)))
(line (pt 0 72)(pt 16 72)(line_width 1))
)
(port
(pt 0 104)
(input)
(text "rdreq" (rect 0 0 30 14)(font "Arial" (font_size 8)))
(text "rdreq" (rect 20 98 44 111)(font "Arial" (font_size 8)))
(line (pt 0 104)(pt 16 104)(line_width 1))
)
(port
(pt 0 120)
(input)
(text "rdclk" (rect 0 0 27 14)(font "Arial" (font_size 8)))
(text "rdclk" (rect 26 114 47 127)(font "Arial" (font_size 8)))
(line (pt 0 120)(pt 16 120)(line_width 1))
)
(port
(pt 0 144)
(input)
(text "aclr" (rect 0 0 21 14)(font "Arial" (font_size 8)))
(text "aclr" (rect 20 138 37 151)(font "Arial" (font_size 8)))
(line (pt 0 144)(pt 16 144)(line_width 1))
)
(port
(pt 160 72)
(output)
(text "wrusedw[8..0]" (rect 0 0 84 14)(font "Arial" (font_size 8)))
(text "wrusedw[8..0]" (rect 69 66 132 79)(font "Arial" (font_size 8)))
(line (pt 160 72)(pt 144 72)(line_width 3))
)
(port
(pt 160 96)
(output)
(text "q[127..0]" (rect 0 0 49 14)(font "Arial" (font_size 8)))
(text "q[127..0]" (rect 99 90 141 103)(font "Arial" (font_size 8)))
(line (pt 160 96)(pt 144 96)(line_width 3))
)
(port
(pt 160 120)
(output)
(text "rdempty" (rect 0 0 46 14)(font "Arial" (font_size 8)))
(text "rdempty" (rect 102 114 140 127)(font "Arial" (font_size 8)))
(line (pt 160 120)(pt 144 120)(line_width 1))
)
(drawing
(text "128 bits x 512 words" (rect 58 140 144 152)(font "Arial" ))
(line (pt 16 16)(pt 144 16)(line_width 1))
(line (pt 144 16)(pt 144 152)(line_width 1))
(line (pt 144 152)(pt 16 152)(line_width 1))
(line (pt 16 152)(pt 16 16)(line_width 1))
(line (pt 16 84)(pt 144 84)(line_width 1))
(line (pt 16 132)(pt 144 132)(line_width 1))
(line (pt 16 66)(pt 22 72)(line_width 1))
(line (pt 22 72)(pt 16 78)(line_width 1))
(line (pt 16 114)(pt 22 120)(line_width 1))
(line (pt 22 120)(pt 16 126)(line_width 1))
)
)

53
FPGA_Quartus_13.1/video/lpm_latch1.bsf
View File

@@ -1,53 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 160 80)
(text "lpm_latch1" (rect 49 1 123 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 64 25 76)(font "Arial" ))
(port
(pt 0 32)
(input)
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(line (pt 0 32)(pt 16 32)(line_width 3))
)
(port
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(text "gate" (rect 20 42 41 55)(font "Arial" (font_size 8)))
(line (pt 0 48)(pt 16 48)(line_width 1))
)
(port
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(text "q[31..0]" (rect 105 26 141 39)(font "Arial" (font_size 8)))
(line (pt 160 32)(pt 144 32)(line_width 3))
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83
FPGA_Quartus_13.1/video/lpm_mux0.bsf
View File

@@ -1,83 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 152 128)
(text "lpm_mux0" (rect 50 2 120 18)(font "Arial" (font_size 10)))
(text "inst" (rect 8 112 25 124)(font "Arial" ))
(port
(pt 0 40)
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(text "data3x[31..0]" (rect 4 27 66 40)(font "Arial" (font_size 8)))
(line (pt 0 40)(pt 72 40)(line_width 3))
)
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(text "clock" (rect 4 91 27 104)(font "Arial" (font_size 8)))
(line (pt 0 104)(pt 72 104)(line_width 1))
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(port
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(line (pt 80 128)(pt 80 116)(line_width 3))
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(port
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(text "result[31..0]" (rect 92 59 147 72)(font "Arial" (font_size 8)))
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111
FPGA_Quartus_13.1/video/lpm_mux1.bsf
View File

@@ -1,111 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 152 192)
(text "lpm_mux1" (rect 50 2 120 18)(font "Arial" (font_size 10)))
(text "inst" (rect 8 176 25 188)(font "Arial" ))
(port
(pt 0 40)
(input)
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(line (pt 0 120)(pt 72 120)(line_width 3))
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(line (pt 0 152)(pt 72 152)(line_width 3))
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(port
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(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
(text "clock" (rect 4 155 27 168)(font "Arial" (font_size 8)))
(line (pt 0 168)(pt 72 168)(line_width 1))
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(port
(pt 80 192)
(input)
(text "sel[2..0]" (rect 0 0 44 14)(font "Arial" (font_size 8)))
(text "sel[2..0]" (rect 84 179 121 192)(font "Arial" (font_size 8)))
(line (pt 80 192)(pt 80 180)(line_width 3))
)
(port
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(text "result[15..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
(text "result[15..0]" (rect 92 91 147 104)(font "Arial" (font_size 8)))
(line (pt 152 104)(pt 88 104)(line_width 3))
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)

167
FPGA_Quartus_13.1/video/lpm_mux2.bsf
View File

@@ -1,167 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 144 320)
(text "lpm_mux2" (rect 50 2 120 18)(font "Arial" (font_size 10)))
(text "inst" (rect 8 304 25 316)(font "Arial" ))
(port
(pt 0 40)
(input)
(text "data15x[7..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
(text "data15x[7..0]" (rect 4 27 66 40)(font "Arial" (font_size 8)))
(line (pt 0 40)(pt 72 40)(line_width 3))
)
(port
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(input)
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(text "data14x[7..0]" (rect 4 43 66 56)(font "Arial" (font_size 8)))
(line (pt 0 56)(pt 72 56)(line_width 3))
)
(port
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(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
(text "clock" (rect 4 283 27 296)(font "Arial" (font_size 8)))
(line (pt 0 296)(pt 72 296)(line_width 1))
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(text "sel[3..0]" (rect 0 0 44 14)(font "Arial" (font_size 8)))
(text "sel[3..0]" (rect 84 307 121 320)(font "Arial" (font_size 8)))
(line (pt 80 320)(pt 80 308)(line_width 3))
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(line (pt 144 168)(pt 88 168)(line_width 3))
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60
FPGA_Quartus_13.1/video/lpm_mux3.bsf
View File

@@ -1,60 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 80 80)
(text "lpm_mux3" (rect 10 2 80 18)(font "Arial" (font_size 10)))
(text "inst" (rect 8 64 25 76)(font "Arial" ))
(port
(pt 0 40)
(input)
(text "data1" (rect 0 0 31 14)(font "Arial" (font_size 8)))
(text "data1" (rect 4 27 31 40)(font "Arial" (font_size 8)))
(line (pt 0 40)(pt 32 40)(line_width 1))
)
(port
(pt 0 56)
(input)
(text "data0" (rect 0 0 31 14)(font "Arial" (font_size 8)))
(text "data0" (rect 4 43 31 56)(font "Arial" (font_size 8)))
(line (pt 0 56)(pt 32 56)(line_width 1))
)
(port
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(input)
(text "sel" (rect 0 0 16 14)(font "Arial" (font_size 8)))
(text "sel" (rect 44 67 57 80)(font "Arial" (font_size 8)))
(line (pt 40 80)(pt 40 68)(line_width 1))
)
(port
(pt 80 48)
(output)
(text "result" (rect 0 0 31 14)(font "Arial" (font_size 8)))
(text "result" (rect 50 35 75 48)(font "Arial" (font_size 8)))
(line (pt 80 48)(pt 48 48)(line_width 1))
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(line (pt 32 72)(pt 48 64)(line_width 1))
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)

60
FPGA_Quartus_13.1/video/lpm_mux4.bsf
View File

@@ -1,60 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 136 80)
(text "lpm_mux4" (rect 42 2 112 18)(font "Arial" (font_size 10)))
(text "inst" (rect 8 64 25 76)(font "Arial" ))
(port
(pt 0 40)
(input)
(text "data1x[6..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
(text "data1x[6..0]" (rect 4 27 60 40)(font "Arial" (font_size 8)))
(line (pt 0 40)(pt 64 40)(line_width 3))
)
(port
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(text "data0x[6..0]" (rect 4 43 60 56)(font "Arial" (font_size 8)))
(line (pt 0 56)(pt 64 56)(line_width 3))
)
(port
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(input)
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(line (pt 72 80)(pt 72 68)(line_width 1))
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(line (pt 136 48)(pt 80 48)(line_width 3))
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)

74
FPGA_Quartus_13.1/video/lpm_mux5.bsf
View File

@@ -1,74 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 152 112)
(text "lpm_mux5" (rect 50 2 120 18)(font "Arial" (font_size 10)))
(text "inst" (rect 8 96 25 108)(font "Arial" ))
(port
(pt 0 40)
(input)
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(line (pt 0 40)(pt 72 40)(line_width 3))
)
(port
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(text "data2x[63..0]" (rect 4 43 66 56)(font "Arial" (font_size 8)))
(line (pt 0 56)(pt 72 56)(line_width 3))
)
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(line (pt 72 104)(pt 88 96)(line_width 1))
)
)

111
FPGA_Quartus_13.1/video/lpm_mux6.bsf
View File

@@ -1,111 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 152 192)
(text "lpm_mux6" (rect 50 2 120 18)(font "Arial" (font_size 10)))
(text "inst" (rect 8 176 25 188)(font "Arial" ))
(port
(pt 0 40)
(input)
(text "data7x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
(text "data7x[23..0]" (rect 4 27 66 40)(font "Arial" (font_size 8)))
(line (pt 0 40)(pt 72 40)(line_width 3))
)
(port
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(text "data6x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
(text "data6x[23..0]" (rect 4 43 66 56)(font "Arial" (font_size 8)))
(line (pt 0 56)(pt 72 56)(line_width 3))
)
(port
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(text "data5x[23..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
(text "data5x[23..0]" (rect 4 59 66 72)(font "Arial" (font_size 8)))
(line (pt 0 72)(pt 72 72)(line_width 3))
)
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(line (pt 0 88)(pt 72 88)(line_width 3))
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(line (pt 0 104)(pt 72 104)(line_width 3))
)
(port
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(text "data2x[23..0]" (rect 4 107 66 120)(font "Arial" (font_size 8)))
(line (pt 0 120)(pt 72 120)(line_width 3))
)
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(text "data0x[23..0]" (rect 4 139 66 152)(font "Arial" (font_size 8)))
(line (pt 0 152)(pt 72 152)(line_width 3))
)
(port
(pt 0 168)
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(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
(text "clock" (rect 4 155 27 168)(font "Arial" (font_size 8)))
(line (pt 0 168)(pt 72 168)(line_width 1))
)
(port
(pt 80 192)
(input)
(text "sel[2..0]" (rect 0 0 44 14)(font "Arial" (font_size 8)))
(text "sel[2..0]" (rect 84 179 121 192)(font "Arial" (font_size 8)))
(line (pt 80 192)(pt 80 180)(line_width 3))
)
(port
(pt 152 104)
(output)
(text "result[23..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
(text "result[23..0]" (rect 92 91 147 104)(font "Arial" (font_size 8)))
(line (pt 152 104)(pt 88 104)(line_width 3))
)
(drawing
(line (pt 72 24)(pt 72 184)(line_width 1))
(line (pt 88 32)(pt 88 176)(line_width 1))
(line (pt 72 24)(pt 88 32)(line_width 1))
(line (pt 72 184)(pt 88 176)(line_width 1))
(line (pt 72 162)(pt 78 168)(line_width 1))
(line (pt 78 168)(pt 72 174)(line_width 1))
)
)

76
FPGA_Quartus_13.1/video/lpm_muxDZ.bsf
View File

@@ -1,76 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 168 112)
(text "lpm_muxDZ" (rect 54 2 135 18)(font "Arial" (font_size 10)))
(text "inst" (rect 8 96 25 108)(font "Arial" ))
(port
(pt 0 40)
(input)
(text "data1x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
(text "data1x[127..0]" (rect 4 27 72 40)(font "Arial" (font_size 8)))
(line (pt 0 40)(pt 80 40)(line_width 3))
)
(port
(pt 0 56)
(input)
(text "data0x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
(text "data0x[127..0]" (rect 4 43 72 56)(font "Arial" (font_size 8)))
(line (pt 0 56)(pt 80 56)(line_width 3))
)
(port
(pt 0 72)
(input)
(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
(text "clock" (rect 4 59 27 72)(font "Arial" (font_size 8)))
(line (pt 0 72)(pt 80 72)(line_width 1))
)
(port
(pt 0 88)
(input)
(text "clken" (rect 0 0 29 14)(font "Arial" (font_size 8)))
(text "clken" (rect 4 75 28 88)(font "Arial" (font_size 8)))
(line (pt 0 88)(pt 80 88)(line_width 1))
)
(port
(pt 88 112)
(input)
(text "sel" (rect 0 0 16 14)(font "Arial" (font_size 8)))
(text "sel" (rect 92 99 105 112)(font "Arial" (font_size 8)))
(line (pt 88 112)(pt 88 100)(line_width 1))
)
(port
(pt 168 64)
(output)
(text "result[127..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
(text "result[127..0]" (rect 102 51 163 64)(font "Arial" (font_size 8)))
(line (pt 168 64)(pt 96 64)(line_width 3))
)
(drawing
(line (pt 80 24)(pt 80 104)(line_width 1))
(line (pt 96 32)(pt 96 96)(line_width 1))
(line (pt 80 24)(pt 96 32)(line_width 1))
(line (pt 80 104)(pt 96 96)(line_width 1))
(line (pt 80 66)(pt 86 72)(line_width 1))
(line (pt 86 72)(pt 80 78)(line_width 1))
)
)

60
FPGA_Quartus_13.1/video/lpm_muxDZ2.bsf
View File

@@ -1,60 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 96 80)
(text "lpm_muxDZ2" (rect 10 2 99 18)(font "Arial" (font_size 10)))
(text "inst" (rect 8 64 25 76)(font "Arial" ))
(port
(pt 0 40)
(input)
(text "data1" (rect 0 0 31 14)(font "Arial" (font_size 8)))
(text "data1" (rect 4 27 31 40)(font "Arial" (font_size 8)))
(line (pt 0 40)(pt 40 40)(line_width 1))
)
(port
(pt 0 56)
(input)
(text "data0" (rect 0 0 31 14)(font "Arial" (font_size 8)))
(text "data0" (rect 4 43 31 56)(font "Arial" (font_size 8)))
(line (pt 0 56)(pt 40 56)(line_width 1))
)
(port
(pt 48 80)
(input)
(text "sel" (rect 0 0 16 14)(font "Arial" (font_size 8)))
(text "sel" (rect 52 67 65 80)(font "Arial" (font_size 8)))
(line (pt 48 80)(pt 48 68)(line_width 1))
)
(port
(pt 96 48)
(output)
(text "result" (rect 0 0 31 14)(font "Arial" (font_size 8)))
(text "result" (rect 66 35 91 48)(font "Arial" (font_size 8)))
(line (pt 96 48)(pt 56 48)(line_width 1))
)
(drawing
(line (pt 40 24)(pt 40 72)(line_width 1))
(line (pt 56 32)(pt 56 64)(line_width 1))
(line (pt 40 24)(pt 56 32)(line_width 1))
(line (pt 40 72)(pt 56 64)(line_width 1))
)
)

158
FPGA_Quartus_13.1/video/lpm_muxVDM.bsf
View File

@@ -1,158 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 168 304)
(text "lpm_muxVDM" (rect 47 2 143 18)(font "Arial" (font_size 10)))
(text "inst" (rect 8 288 25 300)(font "Arial" ))
(port
(pt 0 40)
(input)
(text "data15x[127..0]" (rect 0 0 88 14)(font "Arial" (font_size 8)))
(text "data15x[127..0]" (rect 4 27 78 40)(font "Arial" (font_size 8)))
(line (pt 0 40)(pt 80 40)(line_width 3))
)
(port
(pt 0 56)
(input)
(text "data14x[127..0]" (rect 0 0 88 14)(font "Arial" (font_size 8)))
(text "data14x[127..0]" (rect 4 43 78 56)(font "Arial" (font_size 8)))
(line (pt 0 56)(pt 80 56)(line_width 3))
)
(port
(pt 0 72)
(input)
(text "data13x[127..0]" (rect 0 0 88 14)(font "Arial" (font_size 8)))
(text "data13x[127..0]" (rect 4 59 78 72)(font "Arial" (font_size 8)))
(line (pt 0 72)(pt 80 72)(line_width 3))
)
(port
(pt 0 88)
(input)
(text "data12x[127..0]" (rect 0 0 88 14)(font "Arial" (font_size 8)))
(text "data12x[127..0]" (rect 4 75 78 88)(font "Arial" (font_size 8)))
(line (pt 0 88)(pt 80 88)(line_width 3))
)
(port
(pt 0 104)
(input)
(text "data11x[127..0]" (rect 0 0 88 14)(font "Arial" (font_size 8)))
(text "data11x[127..0]" (rect 4 91 78 104)(font "Arial" (font_size 8)))
(line (pt 0 104)(pt 80 104)(line_width 3))
)
(port
(pt 0 120)
(input)
(text "data10x[127..0]" (rect 0 0 88 14)(font "Arial" (font_size 8)))
(text "data10x[127..0]" (rect 4 107 78 120)(font "Arial" (font_size 8)))
(line (pt 0 120)(pt 80 120)(line_width 3))
)
(port
(pt 0 136)
(input)
(text "data9x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
(text "data9x[127..0]" (rect 4 123 72 136)(font "Arial" (font_size 8)))
(line (pt 0 136)(pt 80 136)(line_width 3))
)
(port
(pt 0 152)
(input)
(text "data8x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
(text "data8x[127..0]" (rect 4 139 72 152)(font "Arial" (font_size 8)))
(line (pt 0 152)(pt 80 152)(line_width 3))
)
(port
(pt 0 168)
(input)
(text "data7x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
(text "data7x[127..0]" (rect 4 155 72 168)(font "Arial" (font_size 8)))
(line (pt 0 168)(pt 80 168)(line_width 3))
)
(port
(pt 0 184)
(input)
(text "data6x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
(text "data6x[127..0]" (rect 4 171 72 184)(font "Arial" (font_size 8)))
(line (pt 0 184)(pt 80 184)(line_width 3))
)
(port
(pt 0 200)
(input)
(text "data5x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
(text "data5x[127..0]" (rect 4 187 72 200)(font "Arial" (font_size 8)))
(line (pt 0 200)(pt 80 200)(line_width 3))
)
(port
(pt 0 216)
(input)
(text "data4x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
(text "data4x[127..0]" (rect 4 203 72 216)(font "Arial" (font_size 8)))
(line (pt 0 216)(pt 80 216)(line_width 3))
)
(port
(pt 0 232)
(input)
(text "data3x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
(text "data3x[127..0]" (rect 4 219 72 232)(font "Arial" (font_size 8)))
(line (pt 0 232)(pt 80 232)(line_width 3))
)
(port
(pt 0 248)
(input)
(text "data2x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
(text "data2x[127..0]" (rect 4 235 72 248)(font "Arial" (font_size 8)))
(line (pt 0 248)(pt 80 248)(line_width 3))
)
(port
(pt 0 264)
(input)
(text "data1x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
(text "data1x[127..0]" (rect 4 251 72 264)(font "Arial" (font_size 8)))
(line (pt 0 264)(pt 80 264)(line_width 3))
)
(port
(pt 0 280)
(input)
(text "data0x[127..0]" (rect 0 0 81 14)(font "Arial" (font_size 8)))
(text "data0x[127..0]" (rect 4 267 72 280)(font "Arial" (font_size 8)))
(line (pt 0 280)(pt 80 280)(line_width 3))
)
(port
(pt 88 304)
(input)
(text "sel[3..0]" (rect 0 0 44 14)(font "Arial" (font_size 8)))
(text "sel[3..0]" (rect 92 291 129 304)(font "Arial" (font_size 8)))
(line (pt 88 304)(pt 88 292)(line_width 3))
)
(port
(pt 168 160)
(output)
(text "result[127..0]" (rect 0 0 74 14)(font "Arial" (font_size 8)))
(text "result[127..0]" (rect 102 147 163 160)(font "Arial" (font_size 8)))
(line (pt 168 160)(pt 96 160)(line_width 3))
)
(drawing
(line (pt 80 24)(pt 80 296)(line_width 1))
(line (pt 96 32)(pt 96 288)(line_width 1))
(line (pt 80 24)(pt 96 32)(line_width 1))
(line (pt 80 296)(pt 96 288)(line_width 1))
)
)

70
FPGA_Quartus_13.1/video/lpm_shiftreg0.bsf
View File

@@ -1,70 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 144 128)
(text "lpm_shiftreg0" (rect 34 1 124 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 112 25 124)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "load" (rect 0 0 23 14)(font "Arial" (font_size 8)))
(text "load" (rect 20 26 41 39)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 16 32)(line_width 1))
)
(port
(pt 0 48)
(input)
(text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size 8)))
(text "data[15..0]" (rect 20 42 71 55)(font "Arial" (font_size 8)))
(line (pt 0 48)(pt 16 48)(line_width 3))
)
(port
(pt 0 80)
(input)
(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
(text "clock" (rect 26 74 49 87)(font "Arial" (font_size 8)))
(line (pt 0 80)(pt 16 80)(line_width 1))
)
(port
(pt 0 96)
(input)
(text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8)))
(text "shiftin" (rect 20 90 48 103)(font "Arial" (font_size 8)))
(line (pt 0 96)(pt 16 96)(line_width 1))
)
(port
(pt 144 72)
(output)
(text "shiftout" (rect 0 0 42 14)(font "Arial" (font_size 8)))
(text "shiftout" (rect 89 66 123 79)(font "Arial" (font_size 8)))
(line (pt 144 72)(pt 128 72)(line_width 1))
)
(drawing
(text "left shift" (rect 92 17 128 29)(font "Arial" ))
(line (pt 16 16)(pt 128 16)(line_width 1))
(line (pt 128 16)(pt 128 112)(line_width 1))
(line (pt 128 112)(pt 16 112)(line_width 1))
(line (pt 16 112)(pt 16 16)(line_width 1))
(line (pt 16 74)(pt 22 80)(line_width 1))
(line (pt 22 80)(pt 16 86)(line_width 1))
)
)

56
FPGA_Quartus_13.1/video/lpm_shiftreg1.bsf
View File

@@ -1,56 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 144 80)
(text "lpm_shiftreg1" (rect 34 1 124 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 64 25 76)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
(text "clock" (rect 26 26 49 39)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 16 32)(line_width 1))
)
(port
(pt 0 48)
(input)
(text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8)))
(text "shiftin" (rect 20 42 48 55)(font "Arial" (font_size 8)))
(line (pt 0 48)(pt 16 48)(line_width 1))
)
(port
(pt 144 48)
(output)
(text "q[1..0]" (rect 0 0 35 14)(font "Arial" (font_size 8)))
(text "q[1..0]" (rect 95 42 125 55)(font "Arial" (font_size 8)))
(line (pt 144 48)(pt 128 48)(line_width 3))
)
(drawing
(text "left shift" (rect 92 17 128 29)(font "Arial" ))
(line (pt 16 16)(pt 128 16)(line_width 1))
(line (pt 128 16)(pt 128 64)(line_width 1))
(line (pt 128 64)(pt 16 64)(line_width 1))
(line (pt 16 64)(pt 16 16)(line_width 1))
(line (pt 16 26)(pt 22 32)(line_width 1))
(line (pt 22 32)(pt 16 38)(line_width 1))
)
)

56
FPGA_Quartus_13.1/video/lpm_shiftreg2.bsf
View File

@@ -1,56 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 144 80)
(text "lpm_shiftreg2" (rect 34 1 124 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 64 25 76)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
(text "clock" (rect 26 26 49 39)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 16 32)(line_width 1))
)
(port
(pt 0 48)
(input)
(text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8)))
(text "shiftin" (rect 20 42 48 55)(font "Arial" (font_size 8)))
(line (pt 0 48)(pt 16 48)(line_width 1))
)
(port
(pt 144 48)
(output)
(text "shiftout" (rect 0 0 42 14)(font "Arial" (font_size 8)))
(text "shiftout" (rect 89 42 123 55)(font "Arial" (font_size 8)))
(line (pt 144 48)(pt 128 48)(line_width 1))
)
(drawing
(text "right shift" (rect 88 17 128 29)(font "Arial" ))
(line (pt 16 16)(pt 128 16)(line_width 1))
(line (pt 128 16)(pt 128 64)(line_width 1))
(line (pt 128 64)(pt 16 64)(line_width 1))
(line (pt 16 64)(pt 16 16)(line_width 1))
(line (pt 16 26)(pt 22 32)(line_width 1))
(line (pt 22 32)(pt 16 38)(line_width 1))
)
)

56
FPGA_Quartus_13.1/video/lpm_shiftreg3.bsf
View File

@@ -1,56 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 144 80)
(text "lpm_shiftreg3" (rect 34 1 124 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 64 25 76)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
(text "clock" (rect 26 26 49 39)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 16 32)(line_width 1))
)
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(pt 0 48)
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(text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8)))
(text "shiftin" (rect 20 42 48 55)(font "Arial" (font_size 8)))
(line (pt 0 48)(pt 16 48)(line_width 1))
)
(port
(pt 144 48)
(output)
(text "shiftout" (rect 0 0 42 14)(font "Arial" (font_size 8)))
(text "shiftout" (rect 89 42 123 55)(font "Arial" (font_size 8)))
(line (pt 144 48)(pt 128 48)(line_width 1))
)
(drawing
(text "right shift" (rect 88 17 128 29)(font "Arial" ))
(line (pt 16 16)(pt 128 16)(line_width 1))
(line (pt 128 16)(pt 128 64)(line_width 1))
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)
)

56
FPGA_Quartus_13.1/video/lpm_shiftreg4.bsf
View File

@@ -1,56 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 144 80)
(text "lpm_shiftreg4" (rect 34 1 124 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 64 25 76)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
(text "clock" (rect 26 26 49 39)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 16 32)(line_width 1))
)
(port
(pt 0 48)
(input)
(text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8)))
(text "shiftin" (rect 20 42 48 55)(font "Arial" (font_size 8)))
(line (pt 0 48)(pt 16 48)(line_width 1))
)
(port
(pt 144 48)
(output)
(text "shiftout" (rect 0 0 42 14)(font "Arial" (font_size 8)))
(text "shiftout" (rect 89 42 123 55)(font "Arial" (font_size 8)))
(line (pt 144 48)(pt 128 48)(line_width 1))
)
(drawing
(text "right shift" (rect 88 17 128 29)(font "Arial" ))
(line (pt 16 16)(pt 128 16)(line_width 1))
(line (pt 128 16)(pt 128 64)(line_width 1))
(line (pt 128 64)(pt 16 64)(line_width 1))
(line (pt 16 64)(pt 16 16)(line_width 1))
(line (pt 16 26)(pt 22 32)(line_width 1))
(line (pt 22 32)(pt 16 38)(line_width 1))
)
)

56
FPGA_Quartus_13.1/video/lpm_shiftreg5.bsf
View File

@@ -1,56 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 144 80)
(text "lpm_shiftreg5" (rect 34 1 124 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 64 25 76)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
(text "clock" (rect 26 26 49 39)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 16 32)(line_width 1))
)
(port
(pt 0 48)
(input)
(text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8)))
(text "shiftin" (rect 20 42 48 55)(font "Arial" (font_size 8)))
(line (pt 0 48)(pt 16 48)(line_width 1))
)
(port
(pt 144 48)
(output)
(text "q[4..0]" (rect 0 0 35 14)(font "Arial" (font_size 8)))
(text "q[4..0]" (rect 95 42 125 55)(font "Arial" (font_size 8)))
(line (pt 144 48)(pt 128 48)(line_width 3))
)
(drawing
(text "right shift" (rect 88 17 128 29)(font "Arial" ))
(line (pt 16 16)(pt 128 16)(line_width 1))
(line (pt 128 16)(pt 128 64)(line_width 1))
(line (pt 128 64)(pt 16 64)(line_width 1))
(line (pt 16 64)(pt 16 16)(line_width 1))
(line (pt 16 26)(pt 22 32)(line_width 1))
(line (pt 22 32)(pt 16 38)(line_width 1))
)
)

56
FPGA_Quartus_13.1/video/lpm_shiftreg6.bsf
View File

@@ -1,56 +0,0 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 0 0 144 80)
(text "lpm_shiftreg6" (rect 34 1 124 17)(font "Arial" (font_size 10)))
(text "inst" (rect 8 64 25 76)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "clock" (rect 0 0 29 14)(font "Arial" (font_size 8)))
(text "clock" (rect 26 26 49 39)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 16 32)(line_width 1))
)
(port
(pt 0 48)
(input)
(text "shiftin" (rect 0 0 34 14)(font "Arial" (font_size 8)))
(text "shiftin" (rect 20 42 48 55)(font "Arial" (font_size 8)))
(line (pt 0 48)(pt 16 48)(line_width 1))
)
(port
(pt 144 48)
(output)
(text "q[4..0]" (rect 0 0 35 14)(font "Arial" (font_size 8)))
(text "q[4..0]" (rect 95 42 125 55)(font "Arial" (font_size 8)))
(line (pt 144 48)(pt 128 48)(line_width 3))
)
(drawing
(text "right shift" (rect 88 17 128 29)(font "Arial" ))
(line (pt 16 16)(pt 128 16)(line_width 1))
(line (pt 128 16)(pt 128 64)(line_width 1))
(line (pt 128 64)(pt 16 64)(line_width 1))
(line (pt 16 64)(pt 16 16)(line_width 1))
(line (pt 16 26)(pt 22 32)(line_width 1))
(line (pt 22 32)(pt 16 38)(line_width 1))
)
)