Sync with Fredi's source tree 18/04/2017
Blitter work.
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20
FPGA_by_Fredi/PLLJ_PLLSPE_INFO.txt
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20
FPGA_by_Fredi/PLLJ_PLLSPE_INFO.txt
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PLL_Name altpll1:inst|altpll:altpll_component|altpll_3vp2:auto_generated|pll1
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PLLJITTER 36
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PLLSPEmax 84
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PLLSPEmin -53
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PLL_Name altpll2:inst12|altpll:altpll_component|altpll_1r33:auto_generated|pll1
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PLLJITTER 43
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PLLSPEmax 84
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PLLSPEmin -53
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PLL_Name altpll3:inst13|altpll:altpll_component|altpll_aus2:auto_generated|pll1
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PLLJITTER NA
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PLLSPEmax 84
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PLLSPEmin -53
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PLL_Name altpll4:inst22|altpll:altpll_component|altpll_r4n2:auto_generated|pll1
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PLLJITTER 31
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PLLSPEmax 84
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PLLSPEmin -53
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