diff --git a/FPGA_by_Fredi/FPGA_DATE.bsf b/FPGA_by_Fredi/FPGA_DATE.bsf index fd5ac89..a6c809a 100644 --- a/FPGA_by_Fredi/FPGA_DATE.bsf +++ b/FPGA_by_Fredi/FPGA_DATE.bsf @@ -31,7 +31,7 @@ applicable agreement for further details. (line (pt 88 24)(pt 72 24)(line_width 3)) ) (drawing - (text "319037463" (rect 27 18 72 30)(font "Arial" )) + (text "402923543" (rect 27 18 72 30)(font "Arial" )) (text "32" (rect 77 25 87 37)(font "Arial" )) (line (pt 16 16)(pt 72 16)(line_width 1)) (line (pt 72 16)(pt 72 32)(line_width 1)) diff --git a/FPGA_by_Fredi/FPGA_DATE.tdf b/FPGA_by_Fredi/FPGA_DATE.tdf index 6769853..49f319c 100644 --- a/FPGA_by_Fredi/FPGA_DATE.tdf +++ b/FPGA_by_Fredi/FPGA_DATE.tdf @@ -33,7 +33,7 @@ --applicable agreement for further details. -- Clearbox generated function header -FUNCTION FPGA_DATE_lpm_constant_d19 () +FUNCTION FPGA_DATE_lpm_constant_i19 () RETURNS ( result[31..0]); @@ -46,11 +46,11 @@ SUBDESIGN FPGA_DATE VARIABLE - FPGA_DATE_lpm_constant_d19_component : FPGA_DATE_lpm_constant_d19; + FPGA_DATE_lpm_constant_i19_component : FPGA_DATE_lpm_constant_i19; BEGIN - result[31..0] = FPGA_DATE_lpm_constant_d19_component.result[31..0]; + result[31..0] = FPGA_DATE_lpm_constant_i19_component.result[31..0]; END; @@ -63,9 +63,9 @@ END; -- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" -- Retrieval info: PRIVATE: Radix NUMERIC "16" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" --- Retrieval info: PRIVATE: Value NUMERIC "319037463" +-- Retrieval info: PRIVATE: Value NUMERIC "402923543" -- Retrieval info: PRIVATE: nBit NUMERIC "32" --- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "319037463" +-- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "402923543" -- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO" -- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT" -- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32" diff --git a/FPGA_by_Fredi/FPGA_DATE_lpm_constant_i19.tdf b/FPGA_by_Fredi/FPGA_DATE_lpm_constant_i19.tdf new file mode 100644 index 0000000..4ae1da6 --- /dev/null +++ b/FPGA_by_Fredi/FPGA_DATE_lpm_constant_i19.tdf @@ -0,0 +1,30 @@ +--lpm_constant CBX_AUTO_BLACKBOX="ALL" ENABLE_RUNTIME_MOD="NO" LPM_CVALUE=18042017 LPM_WIDTH=32 result +--VERSION_BEGIN 9.1SP2 cbx_lpm_constant 2010:03:24:20:43:43:SJ cbx_mgl 2010:03:24:21:01:05:SJ VERSION_END + + +-- Copyright (C) 1991-2010 Altera Corporation +-- Your use of Altera Corporation's design tools, logic functions +-- and other software and tools, and its AMPP partner logic +-- functions, and any output files from any of the foregoing +-- (including device programming or simulation files), and any +-- associated documentation or information are expressly subject +-- to the terms and conditions of the Altera Program License +-- Subscription Agreement, Altera MegaCore Function License +-- Agreement, or other applicable license agreement, including, +-- without limitation, that your use is for the sole purpose of +-- programming logic devices manufactured by Altera and sold by +-- Altera or its authorized distributors. Please refer to the +-- applicable agreement for further details. + + + +--synthesis_resources = +SUBDESIGN FPGA_DATE_lpm_constant_i19 +( + result[31..0] : output; +) + +BEGIN + result[] = B"00011000000001000010000000010111"; +END; +--VALID FILE diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd.bak b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd.bak deleted file mode 100644 index 915c271..0000000 --- a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_MFP68901_IP/wf68901ip_interrupts.vhd.bak +++ /dev/null @@ -1,391 +0,0 @@ ----------------------------------------------------------------------- ----- ---- ----- ATARI MFP compatible IP Core ---- ----- ---- ----- This file is part of the SUSKA ATARI clone project. ---- ----- http://www.experiment-s.de ---- ----- ---- ----- Description: ---- ----- MC68901 compatible multi function port core. ---- ----- ---- ----- This is the SUSKA MFP IP core interrupt logic file. ---- ----- ---- ----- ---- ----- To Do: ---- ----- - ---- ----- ---- ----- Author(s): ---- ----- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2006 - 2008 Wolfgang Foerster ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.gnu.org/licenses/lgpl.html ---- ----- ---- ----------------------------------------------------------------------- --- --- Revision History --- --- Revision 2K6A 2006/06/03 WF --- Initial Release. --- Revision 2K6B 2006/11/07 WF --- Modified Source to compile with the Xilinx ISE. --- Revision 2K8A 2008/06/03 WF --- Fixed Pending register logic. --- Revision 2K9A 2009/06/20 WF --- Fixed interrupt polarity for TA_I and TB_I. --- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; - -entity WF68901IP_INTERRUPTS is - port ( -- System control: - CLK : in bit; - RESETn : in bit; - - -- Asynchronous bus control: - DSn : in bit; - CSn : in bit; - RWn : in bit; - - -- Data and Adresses: - RS : in bit_vector(5 downto 1); - DATA_IN : in bit_vector(7 downto 0); - DATA_OUT : out bit_vector(7 downto 0); - DATA_OUT_EN : out bit; - - -- Interrupt control: - IACKn : in bit; - IEIn : in bit; - IEOn : out bit; - IRQn : out bit; - - -- Interrupt sources: - GP_INT : in bit_vector(7 downto 0); - - AER_4 : in bit; - AER_3 : in bit; - TAI : in bit; - TBI : in bit; - TA_PWM : in bit; - TB_PWM : in bit; - TIMER_A_INT : in bit; - TIMER_B_INT : in bit; - TIMER_C_INT : in bit; - TIMER_D_INT : in bit; - - RCV_ERR : in bit; - TRM_ERR : in bit; - RCV_BUF_F : in bit; - TRM_BUF_E : in bit - ); -end entity WF68901IP_INTERRUPTS; - -architecture BEHAVIOR of WF68901IP_INTERRUPTS is --- Interrupt state machine: -type INT_STATES is (SCAN, REQUEST, VECTOR_OUT); -signal INT_STATE : INT_STATES; --- The registers: -signal IERA : bit_vector(7 downto 0); -signal IERB : bit_vector(7 downto 0); -signal IPRA : bit_vector(7 downto 0); -signal IPRB : bit_vector(7 downto 0); -signal ISRA : bit_vector(7 downto 0); -signal ISRB : bit_vector(7 downto 0); -signal IMRA : bit_vector(7 downto 0); -signal IMRB : bit_vector(7 downto 0); -signal VR : bit_vector(7 downto 3); --- Interconnect: -signal VECT_NUMBER : bit_vector(7 downto 0); -signal INT_SRC : bit_vector(15 downto 0); -signal INT_SRC_EDGE : bit_vector(15 downto 0); -signal INT_ENA : bit_vector(15 downto 0); -signal INT_MASK : bit_vector(15 downto 0); -signal INT_PENDING : bit_vector(15 downto 0); -signal INT_SERVICE : bit_vector(15 downto 0); -signal INT_PASS : bit_vector(15 downto 0); -signal INT_OUT : bit_vector(15 downto 0); -signal GP_INT_4 : bit; -signal GP_INT_3 : bit; -begin - -- Interrupt source for the GPI_4 and GPI_3 is normally the respective port pin. - -- But when the timers operate in their PWM modes, the GPI_4 and GPI_3 are associated - -- to timer A and timer B. - -- The xor logic provides polarity control for the interrupt transition. Be aware, - -- that the PWM signals cause an interrupt on the opposite transition like the - -- respective GPIP port pins (with the same AER settings). - --GP_INT_4 <= GP_INT(4) when TA_PWM = '0' else TAI xor AER_4; - --GP_INT_3 <= GP_INT(3) when TB_PWM = '0' else TBI xor AER_3; - GP_INT_4 <= GP_INT(4) when TA_PWM = '0' else TAI xnor AER_4; -- This should be correct. - GP_INT_3 <= GP_INT(3) when TB_PWM = '0' else TBI xnor AER_3; - - - -- Interrupt source priority sorted (15 = highest): - INT_SRC <= GP_INT(7 downto 6) & TIMER_A_INT & RCV_BUF_F & RCV_ERR & TRM_BUF_E & TRM_ERR & TIMER_B_INT & - GP_INT(5) & GP_INT_4 & TIMER_C_INT & TIMER_D_INT & GP_INT_3 & GP_INT(2 downto 0); - - INT_ENA <= IERA & IERB; - INT_MASK <= IMRA & IMRB; - INT_PENDING <= IPRA & IPRB; - INT_SERVICE <= ISRA & ISRB; - INT_OUT <= INT_PENDING and INT_MASK; -- Masking: - - -- Enable the daisy chain, if there is no pending interrupt and - -- the interrupt state machine is not in service. - IEOn <= '0' when INT_OUT = x"0000" and INT_STATE = SCAN else '1'; - - -- Interrupt request: - IRQn <= '0' when INT_OUT /= x"0000" and INT_STATE = REQUEST else '1'; - - EDGE_ENA: process(RESETn, CLK) - -- These are the 16 edge detectors of the 16 interrupt input sources. This - -- process also provides the disabling or enabling via the IERA and IERB registers. - variable LOCK : bit_vector(15 downto 0); - begin - if RESETn = '0' then - INT_SRC_EDGE <= x"0000"; - LOCK := x"0000"; - elsif CLK = '0' and CLK' event then - for i in 15 downto 0 loop - if INT_SRC(i) = '1' and INT_ENA(i) = '1' and LOCK(i) = '0' then - LOCK(i) := '1'; - INT_SRC_EDGE(i) <= '1'; - elsif INT_SRC(i) = '0' then - LOCK(i) := '0'; - INT_SRC_EDGE(i) <= '0'; - else - INT_SRC_EDGE(i) <= '0'; - end if; - end loop; - end if; - end process EDGE_ENA; - - INT_REGISTERS: process(RESETn, CLK) - begin - if RESETn = '0' then - IERA <= (others => '0'); - IERB <= (others => '0'); - IPRA <= (others => '0'); - IPRB <= (others => '0'); - ISRA <= (others => '0'); - ISRB <= (others => '0'); - IMRA <= (others => '0'); - IMRB <= (others => '0'); - elsif CLK = '1' and CLK' event then - if CSn = '0' and DSn = '0' and RWn = '0' then - case RS is - when "00011" => IERA <= DATA_IN; -- Enable A. - when "00100" => IERB <= DATA_IN; -- Enable B. - when "00101" => - -- Only a '0' can be written to the pending register. - for i in 7 downto 0 loop - if DATA_IN(i) = '0' then - IPRA(i) <= '0'; -- Pending A. - end if; - end loop; - when "00110" => - -- Only a '0' can be written to the pending register. - for i in 7 downto 0 loop - if DATA_IN(i) = '0' then - IPRB(i) <= '0'; -- Pending B. - end if; - end loop; - when "00111" => - -- Only a '0' can be written to the in service register. - for i in 7 downto 0 loop - if DATA_IN(i) = '0' then - ISRA(i) <= '0'; -- In Service A. - end if; - end loop; - when "01000" => - -- Only a '0' can be written to the in service register. - for i in 7 downto 0 loop - if DATA_IN(i) = '0' then - ISRB(i) <= '0'; -- In Service B. - end if; - end loop; - when "01001" => IMRA <= DATA_IN; -- Mask A. - when "01010" => IMRB <= DATA_IN; -- Mask B. - when "01011" => VR <= DATA_IN(7 downto 3); -- Vector register. - when others => null; - end case; - end if; - - -- Pending register: - -- set and clear bit logic. - for i in 15 downto 8 loop - if INT_SRC_EDGE(i) = '1' then - IPRA(i-8) <= '1'; - elsif INT_ENA(i) = '0' then - IPRA(i-8) <= '0'; -- Clear by disabling the channel. - elsif INT_PASS(i) = '1' then - IPRA(i-8) <= '0'; -- Clear by passing the interrupt. - end if; - end loop; - for i in 7 downto 0 loop - if INT_SRC_EDGE(i) = '1' then - IPRB(i) <= '1'; - elsif INT_ENA(i) = '0' then - IPRB(i) <= '0'; -- Clear by disabling the channel. - elsif INT_PASS(i) = '1' then - IPRB(i) <= '0'; -- Clear by passing the interrupt. - end if; - end loop; - - -- In-Service register: - -- Set bit logic, VR(3) is the service register enable. - for i in 15 downto 8 loop - if INT_OUT(i) = '1' and INT_PASS(i) = '1' and VR(3) = '1' then - ISRA(i-8) <= '1'; - end if; - end loop; - for i in 7 downto 0 loop - if INT_OUT(i) = '1' and INT_PASS(i) = '1' and VR(3) = '1' then - ISRB(i) <= '1'; - end if; - end loop; - end if; - end process INT_REGISTERS; - DATA_OUT_EN <= '1' when CSn = '0' and DSn = '0' and RWn = '1' and RS > "00010" and RS <= "01011" else '1' when INT_STATE = VECTOR_OUT else '0'; - - DATA_OUT <= IERA when CSn = '0' and DSn = '0' and RWn = '1' and RS = "00011" else - IERB when CSn = '0' and DSn = '0' and RWn = '1' and RS = "00100" else - IPRA when CSn = '0' and DSn = '0' and RWn = '1' and RS = "00101" else - IPRB when CSn = '0' and DSn = '0' and RWn = '1' and RS = "00110" else - ISRA when CSn = '0' and DSn = '0' and RWn = '1' and RS = "00111" else - ISRB when CSn = '0' and DSn = '0' and RWn = '1' and RS = "01000" else - IMRA when CSn = '0' and DSn = '0' and RWn = '1' and RS = "01001" else - IMRB when CSn = '0' and DSn = '0' and RWn = '1' and RS = "01010" else - VR & "000" when CSn = '0' and DSn = '0' and RWn = '1' and RS = "01011" else - VECT_NUMBER when INT_STATE = VECTOR_OUT else x"00"; - - P_INT_STATE : process(RESETn, CLK) - begin - if RESETn = '0' then - INT_STATE <= SCAN; - elsif CLK = '1' and CLK' event then - case INT_STATE is - when SCAN => - INT_PASS <= x"0000"; - -- Automatic End of Interrupt mode. Service register disabled. - -- The MFP does not respond for an interrupt acknowledge cycle for an uninitialized - -- vector number (VR(7 downto 4) = x"0"). - if INT_OUT /= x"0000" and VR(7 downto 4) /= x"0" and VR(3) = '0' and IEIn = '0' then - INT_STATE <= REQUEST; -- Non masked interrupt is pending. - -- The following 16 are the Software end of interrupt mode. Service register enabled. - -- The MFP does not respond for an interrupt acknowledge cycle for an uninitialized - -- vector number (VR(7 downto 4) = x"0"). The interrupts are prioritized. - elsif INT_OUT /= x"0000" and VR(7 downto 4) /= x"0" and VR(3) = '1' and IEIn = '0' then - if INT_OUT (15) = '1' and INT_SERVICE(15) = '0' then - INT_STATE <= REQUEST; - elsif INT_OUT (14) = '1' and INT_SERVICE(15 downto 14) = "00" then - INT_STATE <= REQUEST; - elsif INT_OUT (13) = '1' and INT_SERVICE(15 downto 13) = "000" then - INT_STATE <= REQUEST; - elsif INT_OUT (12) = '1' and INT_SERVICE(15 downto 12) = x"0" then - INT_STATE <= REQUEST; - elsif INT_OUT (11) = '1' and INT_SERVICE(15 downto 11) = x"0" & '0' then - INT_STATE <= REQUEST; - elsif INT_OUT (10) = '1' and INT_SERVICE(15 downto 10) = x"0" & "00" then - INT_STATE <= REQUEST; - elsif INT_OUT (9) = '1' and INT_SERVICE(15 downto 9) = x"0" & "000" then - INT_STATE <= REQUEST; - elsif INT_OUT (8) = '1' and INT_SERVICE(15 downto 8) = x"00" then - INT_STATE <= REQUEST; - elsif INT_OUT (7) = '1' and INT_SERVICE(15 downto 7) = x"00" & '0' then - INT_STATE <= REQUEST; - elsif INT_OUT (6) = '1' and INT_SERVICE(15 downto 6) = x"00" & "00" then - INT_STATE <= REQUEST; - elsif INT_OUT (5) = '1' and INT_SERVICE(15 downto 5) = x"00" & "000" then - INT_STATE <= REQUEST; - elsif INT_OUT (4) = '1' and INT_SERVICE(15 downto 4) = x"000" then - INT_STATE <= REQUEST; - elsif INT_OUT (3) = '1' and INT_SERVICE(15 downto 3) = x"000" & '0' then - INT_STATE <= REQUEST; - elsif INT_OUT (2) = '1' and INT_SERVICE(15 downto 2) = x"000" & "00" then - INT_STATE <= REQUEST; - elsif INT_OUT (1) = '1' and INT_SERVICE(15 downto 1) = x"000" & "000" then - INT_STATE <= REQUEST; - elsif INT_OUT (0) = '1' and INT_SERVICE(15 downto 0) = x"0000" then - INT_STATE <= REQUEST; - else - INT_STATE <= SCAN; -- Wait for interrupt. - end if; - else - INT_STATE <= SCAN; - end if; - when REQUEST => - if IACKn = '0' and DSn = '0' then -- Vectored interrupt mode. - INT_STATE <= VECTOR_OUT; -- Non masked interrupt is pending. - if INT_OUT(15) = '1' then - INT_PASS(15) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"F"; -- GPI 7. - elsif INT_OUT(14) = '1' then - INT_PASS(14) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"E"; -- GPI 6. - elsif INT_OUT(13) = '1' then - INT_PASS(13) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"D"; -- TIMER A. - elsif INT_OUT(12) = '1' then - INT_PASS(12) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"C"; -- Receive buffer full. - elsif INT_OUT(11) = '1' then - INT_PASS(11) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"B"; -- Receiver error. - elsif INT_OUT(10) = '1' then - INT_PASS(10) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"A"; -- Transmit buffer empty. - elsif INT_OUT(9) = '1' then - INT_PASS(9) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"9"; -- Transmit error. - elsif INT_OUT(8) = '1' then - INT_PASS(8) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"8"; -- Timer B. - elsif INT_OUT(7) = '1' then - INT_PASS(7) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"7"; -- GPI 5. - elsif INT_OUT(6) = '1' then - INT_PASS(6) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"6"; -- GPI 4. - elsif INT_OUT(5) = '1' then - INT_PASS(5) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"5"; -- Timer C. - elsif INT_OUT(4) = '1' then - INT_PASS(4) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"4"; -- Timer D. - elsif INT_OUT(3) = '1' then - INT_PASS(3) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"3"; -- GPI 3. - elsif INT_OUT(2) = '1' then - INT_PASS(2) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"2"; -- GPI 2. - elsif INT_OUT(1) = '1' then - INT_PASS(1) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"1"; -- GPI 1. - elsif INT_OUT(0) = '1' then - INT_PASS(0) <= '1'; VECT_NUMBER <= VR(7 downto 4) & x"0"; -- GPI 0. - end if; - -- Polled interrupt mode: End of interrupt by writing to the pending registers. - elsif CSn = '0' and DSn = '0' and RWn = '0' and (RS = "00101" or RS = "00110") then - INT_STATE <= SCAN; - else - INT_STATE <= REQUEST; -- Wait. - end if; - when VECTOR_OUT => - INT_PASS <= x"0000"; - if DSn = '1' or IACKn = '1' then - INT_STATE <= SCAN; -- Finished. - else - INT_STATE <= VECTOR_OUT; -- Wait for processor to read the vector. - end if; - end case; - end if; - end process P_INT_STATE; -end architecture BEHAVIOR; diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_SDC_IF/sd-card-interface_soc.vhd.bak b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_SDC_IF/sd-card-interface_soc.vhd.bak deleted file mode 100644 index 0200dea..0000000 --- a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_SDC_IF/sd-card-interface_soc.vhd.bak +++ /dev/null @@ -1,239 +0,0 @@ ----------------------------------------------------------------------- ----- ---- ----- ATARI IP Core peripheral Add-On ---- ----- ---- ----- This file is part of the FPGA-ATARI project. ---- ----- http://www.experiment-s.de ---- ----- ---- ----- Description: ---- ----- This hardware provides an interface to connect to a SD-Card. ---- ----- ---- ----- This interface is based on the project 'SatanDisk' of ---- ----- Miroslav Nohaj 'Jookie'. The code is an interpretation of ---- ----- the original code, written in VERILOG. It is provided for ---- ----- the use in a system on programmable chips (SOPC). ---- ----- ---- ----- Timing: Use a clock frequency of 16MHz for this component. ---- ----- Use the same clock frequency for the connected AVR ---- ----- microcontroller. ---- ----- ---- ----- To Do: ---- ----- - ---- ----- ---- ----- Author(s): ---- ----- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2007 - 2008 Wolfgang Foerster ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.gnu.org/licenses/lgpl.html ---- ----- ---- ----------------------------------------------------------------------- ----- This hardware works with the original ATARI ---- ----- hard dik driver. ---- ----------------------------------------------------------------------- --- --- Revision History --- --- Revision 2K7A 2007/01/05 WF --- Initial Release. --- Revision 2K8A 2008/07/14 WF --- Minor changes. --- -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; - -entity WF_SD_CARD is - port ( - -- System: - RESETn : in bit; - CLK : in bit; -- 16MHz, see above. - - -- ACSI section: - ACSI_A1 : in bit; - ACSI_CSn : in bit; - ACSI_ACKn : in bit; - ACSI_INTn : out bit; - ACSI_DRQn : out bit; - ACSI_D_IN : in std_logic_vector(7 downto 0); - ACSI_D_OUT : out std_logic_vector(7 downto 0); - ACSI_D_EN : out bit; - - -- Microcontroller interface: - MC_DO : in bit; - MC_PIO_DMAn : in bit; - MC_RWn : in bit; - MC_CLR_CMD : in bit; - MC_DONE : out bit; - MC_GOT_CMD : out bit; - MC_D_IN : in std_logic_vector(7 downto 0); - MC_D_OUT : out std_logic_vector(7 downto 0); - MC_D_EN : out bit - ); -end WF_SD_CARD; - -architecture BEHAVIOR of WF_SD_CARD is -signal DATA_REG : std_logic_vector(7 downto 0); -signal D0_REG : bit; -signal INT_REG : bit; -signal DRQ_REG : bit; -signal DONE_REG : bit; -signal GOT_CMD_REG : bit; -signal HOLD : bit; -signal PREV_CSn : bit; -signal PREV_ACKn : bit; -begin - MC_D_OUT <= DATA_REG when MC_RWn = '0' and DONE_REG = '1' else (others => '0'); - MC_D_EN <= '1' when MC_RWn = '0' and DONE_REG = '1' else '0'; - ACSI_D_OUT <= DATA_REG when MC_RWn = '1' and (ACSI_CSn = '0' or ACSI_ACKn = '0' or HOLD = '1') else (others => '0'); --- ???: ---ACSI_D_EN <= '1' when MC_RWn = '1' and (ACSI_CSn = '0' or ACSI_ACKn = '0' or HOLD = '1') else '0'; -ACSI_D_EN <= '0'; - ACSI_INTn <= INT_REG; - ACSI_DRQn <= DRQ_REG; - MC_DONE <= DONE_REG; - MC_GOT_CMD <= GOT_CMD_REG; - - P_DATA: process(RESETn, CLK) - begin - if RESETn = '0' then - DATA_REG <= (others => '0'); - elsif CLK = '1' and CLK' event then - if D0_REG = '0' and MC_DO = '1' and MC_RWn = '1' then - DATA_REG <= MC_D_IN; -- Read from AVR to ACSI. - end if; - -- - if PREV_CSn = '0' and ACSI_CSn = '0' and MC_RWn = '0' and DONE_REG = '0' then - DATA_REG <= ACSI_D_IN; -- Write from ACSI to AVR. - elsif PREV_ACKn = '0' and ACSI_ACKn = '0' and MC_RWn = '0' and DONE_REG = '0' then - DATA_REG <= ACSI_D_IN; -- Write from ACSI to AVR. - end if; - end if; - end process P_DATA; - - P_SYNC: process - begin - wait until CLK = '1' and CLK' event; - PREV_CSn <= ACSI_CSn; - PREV_ACKn <= ACSI_ACKn; - end process P_SYNC; - - P_INT_DRQ: process(RESETn, CLK) - begin - if RESETn = '0' then - INT_REG <= '1'; -- No interrupt. - DRQ_REG <= '1'; -- No data request. - elsif CLK = '1' and CLK' event then - if D0_REG = '0' and MC_DO = '1' and MC_PIO_DMAn = '1' then -- Positive MC_DO edge. - INT_REG <= '0'; -- Release an interrupt. - DRQ_REG <= '1'; - elsif D0_REG = '0' and MC_DO = '1' then - INT_REG <= '1'; - DRQ_REG <= '0'; -- Release a data request. - end if; - -- - if MC_CLR_CMD = '1' then -- Clear done. - INT_REG <= '1'; -- Restore INT_REG. - DRQ_REG <= '1'; -- Restore DRQ_REG. - end if; - -- - if (PREV_CSn = '0' and ACSI_CSn = '0') or (PREV_ACKn = '0' and ACSI_ACKn = '0') then - if ACSI_CSn = '0' then - INT_REG <= '1'; - end if; - -- - if ACSI_ACKn = '0' then - DRQ_REG <= '1'; - end if; - end if; - end if; - end process P_INT_DRQ; - - P_HOLD: process(RESETn, CLK) - begin - if RESETn = '0' then - HOLD <= '0'; - elsif CLK = '1' and CLK' event then - if (PREV_CSn = '0' and ACSI_CSn = '0') or (PREV_ACKn = '0' and ACSI_ACKn = '0') then - HOLD <= '1'; - elsif PREV_CSn = '1' and ACSI_CSn = '1' then -- If signal is high. - HOLD <= '0'; - elsif PREV_ACKn = '1' and ACSI_ACKn = '1' then -- If signal is high. - HOLD <= '0'; - elsif PREV_CSn = '0' and ACSI_CSn = '1' then -- Rising edge. - HOLD <= '1'; - elsif PREV_ACKn = '0' and ACSI_ACKn = '1' then -- Rising edge. - HOLD <= '1'; - elsif MC_CLR_CMD = '1' then -- Clear done. - HOLD <= '0'; - end if; - end if; - end process P_HOLD; - - P_DONE: process(RESETn, CLK) - begin - if RESETn = '0' then - DONE_REG <= '0'; - elsif CLK = '1' and CLK' event then - if (PREV_CSn = '0' and ACSI_CSn = '0') or (PREV_ACKn = '0' and ACSI_ACKn = '0') then - DONE_REG <= '1'; - elsif MC_CLR_CMD = '1' then -- Clear done. - DONE_REG <= '0'; - elsif D0_REG = '0' and MC_DO = '1' then -- Positive MC_DO edge. - DONE_REG <= '0'; - elsif D0_REG = '1' and MC_DO = '0' then -- Negative MC_DO edge. - DONE_REG <= '0'; - end if; - end if; - end process P_DONE; - - P_DO_REG: process(RESETn, CLK) - begin - if RESETn = '0' then - D0_REG <= '0'; - elsif CLK = '1' and CLK' event then - if D0_REG = '0' and MC_DO = '1' then -- Positive MC_DO edge. - D0_REG <= MC_DO; - elsif D0_REG = '1' and MC_DO = '0' then -- Negative MC_DO edge. - D0_REG <= MC_DO; - end if; - end if; - end process P_DO_REG; - - P_GOT_CMD: process(RESETn, CLK) - begin - if RESETn = '0' then - GOT_CMD_REG <= '0'; - elsif CLK = '1' and CLK' event then --- ?? ACSI_CSn doppelt! ---if PREV_CSn = '0' and ACSI_CSn = '0' and ACSI_CSn = '0' and ACSI_A1 = '0' then - GOT_CMD_REG <= '1'; -- If command was received. - elsif PREV_ACKn = '0' and ACSI_ACKn = '0' and ACSI_CSn = '0' and ACSI_A1 = '0' then - GOT_CMD_REG <= '1'; -- If command was received. - elsif MC_CLR_CMD = '1' then -- Clear done. - GOT_CMD_REG <= '0'; - end if; - end if; - end process P_GOT_CMD; -end architecture BEHAVIOR; \ No newline at end of file diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd.bak b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd.bak deleted file mode 100644 index 2e85cdd..0000000 --- a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_ctrl_status.vhd.bak +++ /dev/null @@ -1,214 +0,0 @@ ----------------------------------------------------------------------- ----- ---- ----- 6850 compatible IP Core ---- ----- ---- ----- This file is part of the SUSKA ATARI clone project. ---- ----- http://www.experiment-s.de ---- ----- ---- ----- Description: ---- ----- UART 6850 compatible IP core ---- ----- ---- ----- Control unit and status logic. ---- ----- ---- ----- ---- ----- To Do: ---- ----- - ---- ----- ---- ----- Author(s): ---- ----- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2006 - 2008 Wolfgang Foerster ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.gnu.org/licenses/lgpl.html ---- ----- ---- ----------------------------------------------------------------------- --- --- Revision History --- --- Revision 2K6A 2006/06/03 WF --- Initial Release. --- Revision 2K6B 2006/11/07 WF --- Modified Source to compile with the Xilinx ISE. --- Revision 2K8A 2008/07/14 WF --- Minor changes. --- Revision 2K9A 2009/06/20 WF --- CTRL_REG has now synchronous reset to meet preset requirements. --- Process P_DCD has now synchronous reset to meet preset requirements. --- IRQ_In has now synchronous reset to meet preset requirement. --- Revision 2K9B 2009/12/24 WF --- Fixed the interrupt logic. --- Introduced a minor RTSn correction. --- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; - -entity WF6850IP_CTRL_STATUS is - port ( - CLK : in std_logic; - RESETn : in bit; - - CS : in bit_vector(2 downto 0); -- Active if "011". - E : in bit; - RWn : in bit; - RS : in bit; - - DATA_IN : in bit_vector(7 downto 0); - DATA_OUT : out bit_vector(7 downto 0); - DATA_EN : out bit; - - -- Status register stuff: - RDRF : in bit; -- Receive data register full. - TDRE : in bit; -- Transmit data register empty. - DCDn : in bit; -- Data carrier detect. - CTSn : in bit; -- Clear to send. - FE : in bit; -- Framing error. - OVR : in bit; -- Overrun error. - PE : in bit; -- Parity error. - - -- Control register stuff: - MCLR : buffer bit; -- Master clear (high active). - RTSn : out bit; -- Request to send. - CDS : out bit_vector(1 downto 0); -- Clock control. - WS : out bit_vector(2 downto 0); -- Word select. - TC : out bit_vector(1 downto 0); -- Transmit control. - IRQn : buffer bit -- Interrupt request. - ); -end entity WF6850IP_CTRL_STATUS; - -architecture BEHAVIOR of WF6850IP_CTRL_STATUS is -signal CTRL_REG : bit_vector(7 downto 0); -signal STATUS_REG : bit_vector(7 downto 0); -signal RIE : bit; -signal CTS_In : bit; -signal DCD_In : bit; -signal DCD_FLAGn : bit; -begin - CTS_In <= CTSn; - DCD_In <= DCDn; -- immer 0 - - STATUS_REG(7) <= not IRQn; - STATUS_REG(6) <= PE; - STATUS_REG(5) <= OVR; - STATUS_REG(4) <= FE; - STATUS_REG(3) <= CTS_In; -- Reflexion of the input pin. - STATUS_REG(2) <= DCD_FLAGn; - STATUS_REG(1) <= TDRE and not CTS_In; -- No TDRE for CTSn = '1'. - STATUS_REG(0) <= RDRF and not DCD_In; -- DCDn = '1' indicates empty. - - DATA_OUT <= STATUS_REG when CS = "011" and RWn = '1' and RS = '0' else (others => '0'); - DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '0' else '0'; - - MCLR <= '1' when CTRL_REG(1 downto 0) = "11" else '0'; - RTSn <= '0' when CTRL_REG(6 downto 5) /= "10" else '1'; - - CDS <= CTRL_REG(1 downto 0); - WS <= CTRL_REG(4 downto 2); - TC <= CTRL_REG(6 downto 5); - RIE <= CTRL_REG(7); - - P_IRQ: process(CLK) - variable irq_v : std_logic_vector(3 downto 0); - begin - if rising_edge(CLK) then - if RESETn = '0' or MCLR = '1' then - irq_v := x"0"; - IRQn <= '1'; - else - -- Transmitter interrupt: - if TDRE = '1' and CTRL_REG(6 downto 5) = "01" then - if irq_v = x"F" then - irq_v := irq_v + 1; - end if; - -- Receiver interrupts: - elsif RDRF = '1' and RIE = '1' then - if irq_v < 15 then - irq_v := irq_v + 1; - end if; - -- Overrun - elsif OVR = '1' and RIE = '1' then - if irq_v < 15 then - irq_v := irq_v + 1; - end if; - else - if irq_v > 0 then - irq_v := irq_v - 1; - end if; - end if; - if irq_v < 8 then - IRQn <= '1'; - else - IRQn <= '0'; - end if; - -- The reset of the IRQ status flag: - -- Clear by writing to the transmit data register. - -- Clear by reading the receive data register. - end if; - end if; - end process P_IRQ; - - CONTROL: process(CLK) - begin - if rising_edge(CLK) then - if RESETn = '0' then - CTRL_REG <= "01000000"; - elsif CS = "011" and RWn = '0' and RS = '0' then - CTRL_REG <= DATA_IN; - end if; - end if; - end process CONTROL; - - P_DCD: process(CLK) - -- This process is some kind of tricky. Refer to the MC6850 data - -- sheet for more information. - variable READ_LOCK : boolean; - variable DCD_RELEASE : boolean; - begin - if rising_edge(CLK) then - if RESETn = '0' then - DCD_FLAGn <= '0'; -- This interrupt source must initialise low. - READ_LOCK := true; - DCD_RELEASE := false; - elsif MCLR = '1' then - DCD_FLAGn <= DCD_In; - READ_LOCK := true; - elsif DCD_In = '1' then - DCD_FLAGn <= '1'; - elsif CS = "011" and RWn = '1' and RS = '0' then - READ_LOCK := false; -- Un-READ_LOCK if receiver data register is read. - elsif CS = "011" and RWn = '1' and RS = '1' and READ_LOCK = false then - -- Clear if receiver status register read access. - -- After data register has ben read and READ_LOCK again. - DCD_RELEASE := true; - READ_LOCK := true; - DCD_FLAGn <= DCD_In; - elsif DCD_In = '0' and DCD_RELEASE = true then - DCD_FLAGn <= '0'; - DCD_RELEASE := false; - end if; - end if; - end process P_DCD; -end architecture BEHAVIOR; - diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive - Kopie.vhd b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive - Kopie.vhd deleted file mode 100644 index c6626df..0000000 --- a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive - Kopie.vhd +++ /dev/null @@ -1,419 +0,0 @@ ----------------------------------------------------------------------- ----- ---- ----- 6850 compatible IP Core ---- ----- ---- ----- This file is part of the SUSKA ATARI clone project. ---- ----- http://www.experiment-s.de ---- ----- ---- ----- Description: ---- ----- UART 6850 compatible IP core ---- ----- ---- ----- 6850's receiver unit. ---- ----- ---- ----- ---- ----- To Do: ---- ----- - ---- ----- ---- ----- Author(s): ---- ----- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2006 - 2008 Wolfgang Foerster ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.gnu.org/licenses/lgpl.html ---- ----- ---- ----------------------------------------------------------------------- --- --- Revision History --- --- Revision 2K6A 2006/06/03 WF --- Initial Release. --- Revision 2K6B 2006/11/07 WF --- Modified Source to compile with the Xilinx ISE. --- Revision 2K8A 2008/07/14 WF --- Minor changes. --- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; - -entity WF6850IP_RECEIVE is - port ( - CLK : in bit; - RESETn : in bit; - MCLR : in bit; - - CS : in bit_vector(2 downto 0); - E : in bit; - RWn : in bit; - RS : in bit; - - DATA_OUT : out bit_vector(7 downto 0); - DATA_EN : out bit; - - WS : in bit_vector(2 downto 0); - CDS : in bit_vector(1 downto 0); - - RXCLK : in bit; - RXDATA : in bit; - - RDRF : buffer bit; - OVR : out bit; - PE : out bit; - FE : out bit - ); -end entity WF6850IP_RECEIVE; - -architecture BEHAVIOR of WF6850IP_RECEIVE is -type RCV_STATES is (IDLE, WAIT_START, SAMPLE, PARITY, STOP1, STOP2, SYNC); -signal RCV_STATE, RCV_NEXT_STATE : RCV_STATES; -signal RXDATA_I : bit; -signal RXDATA_S : bit; -signal DATA_REG : bit_vector(7 downto 0); -signal SHIFT_REG : bit_vector(7 downto 0); -signal CLK_STRB : bit; -signal BITCNT : std_logic_vector(2 downto 0); -begin - P_SAMPLE: process - -- This filter provides a synchronisation to the system - -- clock, even for random baud rates of the received data - -- stream. - variable FLT_TMP : integer range 0 to 2; - begin - wait until CLK = '1' and CLK' event; - -- - RXDATA_I <= RXDATA; - -- - if RXDATA_I = '1' and FLT_TMP < 2 then - FLT_TMP := FLT_TMP + 1; - elsif RXDATA_I = '1' then - RXDATA_S <= '1'; - elsif RXDATA_I = '0' and FLT_TMP > 0 then - FLT_TMP := FLT_TMP - 1; - elsif RXDATA_I = '0' then - RXDATA_S <= '0'; - end if; - end process P_SAMPLE; - - CLKDIV: process - variable CLK_LOCK : boolean; - variable STRB_LOCK : boolean; - variable CLK_DIVCNT : std_logic_vector(6 downto 0); - begin - wait until CLK = '1' and CLK' event; - if CDS = "00" then -- Divider off. - if RXCLK = '1' and STRB_LOCK = false then - CLK_STRB <= '1'; - STRB_LOCK := true; - elsif RXCLK = '0' then - CLK_STRB <= '0'; - STRB_LOCK := false; - else - CLK_STRB <= '0'; - end if; - elsif RCV_STATE = IDLE then - -- Preset the CLKDIV with the start delays. - if CDS = "01" then - CLK_DIVCNT := "0001000"; -- Half of div by 16 mode. - elsif CDS = "10" then - CLK_DIVCNT := "0100000"; -- Half of div by 64 mode. - end if; - CLK_STRB <= '0'; - else - if CLK_DIVCNT > "0000000" and RXCLK = '1' and CLK_LOCK = false then - CLK_DIVCNT := CLK_DIVCNT - '1'; - CLK_STRB <= '0'; - CLK_LOCK := true; - elsif CDS = "01" and CLK_DIVCNT = "0000000" then - CLK_DIVCNT := "0010000"; -- Div by 16 mode. - -- - if STRB_LOCK = false then - STRB_LOCK := true; - CLK_STRB <= '1'; - else - CLK_STRB <= '0'; - end if; - elsif CDS = "10" and CLK_DIVCNT = "0000000" then - CLK_DIVCNT := "1000000"; -- Div by 64 mode. - if STRB_LOCK = false then - STRB_LOCK := true; - CLK_STRB <= '1'; - else - CLK_STRB <= '0'; - end if; - elsif RXCLK = '0' then - CLK_LOCK := false; - STRB_LOCK := false; - CLK_STRB <= '0'; - else - CLK_STRB <= '0'; - end if; - end if; - end process CLKDIV; - - DATAREG: process(RESETn, CLK) - begin - if RESETn = '0' then - DATA_REG <= x"00"; - elsif CLK = '1' and CLK' event then - if MCLR = '1' then - DATA_REG <= x"00"; - elsif RCV_STATE = SYNC and WS(2) = '0' and RDRF = '0' then -- 7 bit data. - -- Transfer from shift- to data register only if - -- data register is empty (RDRF = '0'). - DATA_REG <= '0' & SHIFT_REG(7 downto 1); - elsif RCV_STATE = SYNC and WS(2) = '1' and RDRF = '0' then -- 8 bit data. - -- Transfer from shift- to data register only if - -- data register is empty (RDRF = '0'). - DATA_REG <= SHIFT_REG; - end if; - end if; - end process DATAREG; - DATA_OUT <= DATA_REG when CS = "011" and RWn = '1' and RS = '1' and E = '1' else (others => '0'); - DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '1' and E = '1' else '0'; - - SHIFTREG: process(RESETn, CLK) - begin - if RESETn = '0' then - SHIFT_REG <= x"00"; - elsif CLK = '1' and CLK' event then - if MCLR = '1' then - SHIFT_REG <= x"00"; - elsif RCV_STATE = SAMPLE and CLK_STRB = '1' then - SHIFT_REG <= RXDATA_S & SHIFT_REG(7 downto 1); -- Shift right. - end if; - end if; - end process SHIFTREG; - - P_BITCNT: process - begin - wait until CLK = '1' and CLK' event; - if RCV_STATE = SAMPLE and CLK_STRB = '1' then - BITCNT <= BITCNT + '1'; - elsif RCV_STATE /= SAMPLE then - BITCNT <= (others => '0'); - end if; - end process P_BITCNT; - - FRAME_ERR: process(RESETn, CLK) - -- This module detects a framing error - -- during stop bit 1 and stop bit 2. - variable FE_I: bit; - begin - if RESETn = '0' then - FE_I := '0'; - FE <= '0'; - elsif CLK = '1' and CLK' event then - if MCLR = '1' then - FE_I := '0'; - FE <= '0'; - elsif CLK_STRB = '1' then - if RCV_STATE = STOP1 and RXDATA_S = '0' then - FE_I := '1'; - elsif RCV_STATE = STOP2 and RXDATA_S = '0' then - FE_I := '1'; - elsif RCV_STATE = STOP1 or RCV_STATE = STOP2 then - FE_I := '0'; -- Error resets when correct data appears. - end if; - end if; - if RCV_STATE = SYNC then - FE <= FE_I; -- Update the FE every SYNC time. - end if; - end if; - end process FRAME_ERR; - - OVERRUN: process(RESETn, CLK) - variable OVR_I : bit; - variable FIRST_READ : boolean; - begin - if RESETn = '0' then - OVR_I := '0'; - OVR <= '0'; - FIRST_READ := false; - elsif CLK = '1' and CLK' event then - if MCLR = '1' then - OVR_I := '0'; - OVR <= '0'; - FIRST_READ := false; - elsif CLK_STRB = '1' and RCV_STATE = STOP1 then - -- Overrun appears if RDRF is '1' in this state. - OVR_I := RDRF; - end if; - if CS = "011" and RWn = '1' and RS = '1' then - -- If an overrun was detected, the concerning flag is - -- set when the valid data word in the receiver data - -- register is read. Thereafter the RDRF flag is reset - -- and the overrun disappears (OVR_I goes low) after - -- a second read (in time) of the receiver data register. - if FIRST_READ = false then - if OVR_I = '1' then - OVR <= '1'; - OVR_I := '0'; - FIRST_READ := true; - else - OVR <= '0'; - end if; - end if; - else - FIRST_READ := false; - end if; - end if; - end process OVERRUN; - - PARITY_TEST: process(RESETn, CLK) - variable PAR_TMP : bit; - variable PE_I : bit; - begin - if RESETn = '0' then - PE <= '0'; - elsif CLK = '1' and CLK' event then - if MCLR = '1' then - PE <= '0'; - elsif CLK_STRB = '1' then -- Sample parity on clock strobe. - PE_I := '0'; -- Initialise. - if RCV_STATE = PARITY then - for i in 1 to 7 loop - if i = 1 then - PAR_TMP := SHIFT_REG(i-1) xor SHIFT_REG(i); - else - PAR_TMP := PAR_TMP xor SHIFT_REG(i); - end if; - end loop; - if WS = "000" or WS = "010" or WS = "110" then -- Even parity. - PE_I := PAR_TMP xor RXDATA_S; - elsif WS = "001" or WS = "011" or WS = "111" then -- Odd parity. - PE_I := not PAR_TMP xor RXDATA_S; - else -- No parity for WS = "100" and WS = "101". - PE_I := '0'; - end if; - end if; - end if; - -- Transmit the parity flag together with the data - -- In other words: no parity to the status register - -- when RDRF inhibits the data transfer to the - -- receiver data register. - if RCV_STATE = SYNC and RDRF = '0' then - PE <= PE_I; - elsif CS = "011" and RWn = '1' and RS = '1' then - PE <= '0'; -- Clear when reading the data register. - end if; - end if; - end process PARITY_TEST; - - P_RDRF: process(RESETn, CLK) - -- Receive data register full flag. - begin - if RESETn = '0' then - RDRF <= '0'; - elsif CLK = '1' and CLK' event then - if MCLR = '1' then - RDRF <= '0'; - elsif RCV_STATE = SYNC then - RDRF <= '1'; -- Data register is full until now! - elsif CS = "011" and RWn = '1' and RS = '1' then - RDRF <= '0'; -- After reading the data register ... - end if; - end if; - end process P_RDRF; - - RCV_STATEREG: process(RESETn, CLK) - begin - if RESETn = '0' then - RCV_STATE <= IDLE; - elsif CLK = '1' and CLK' event then - if MCLR = '1' then - RCV_STATE <= IDLE; - else - RCV_STATE <= RCV_NEXT_STATE; - end if; - end if; - end process RCV_STATEREG; - - RCV_STATEDEC: process(RCV_STATE, RXDATA_S, CDS, WS, BITCNT, CLK_STRB) - begin - case RCV_STATE is - when IDLE => - if RXDATA_S = '0' and CDS = "00" then - RCV_NEXT_STATE <= SAMPLE; -- Startbit detected in div by 1 mode. - elsif RXDATA_S = '0' and CDS = "01" then - RCV_NEXT_STATE <= WAIT_START; -- Startbit detected in div by 16 mode. - elsif RXDATA_S = '0' and CDS = "10" then - RCV_NEXT_STATE <= WAIT_START; -- Startbit detected in div by 64 mode. - else - RCV_NEXT_STATE <= IDLE; -- No startbit; sleep well :-) - end if; - when WAIT_START => - if CLK_STRB = '1' then - if RXDATA_S = '0' then - RCV_NEXT_STATE <= SAMPLE; -- Start condition in no div by 1 modes. - else - RCV_NEXT_STATE <= IDLE; -- No valid start condition, go back. - end if; - else - RCV_NEXT_STATE <= WAIT_START; -- Stay. - end if; - when SAMPLE => - if CLK_STRB = '1' then - if BITCNT < "110" and WS(2) = '0' then - RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 7 data bits. - elsif BITCNT < "111" and WS(2) = '1' then - RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 8 data bits. - elsif WS = "100" or WS = "101" then - RCV_NEXT_STATE <= STOP1; -- No parity check enabled. - else - RCV_NEXT_STATE <= PARITY; -- Parity enabled. - end if; - else - RCV_NEXT_STATE <= SAMPLE; -- Stay in sample mode. - end if; - when PARITY => - if CLK_STRB = '1' then - RCV_NEXT_STATE <= STOP1; - else - RCV_NEXT_STATE <= PARITY; - end if; - when STOP1 => - if CLK_STRB = '1' then - if RXDATA_S = '0' then - RCV_NEXT_STATE <= SYNC; -- Framing error detected. - elsif WS = "000" or WS = "001" or WS = "100" then - RCV_NEXT_STATE <= STOP2; -- Two stop bits selected. - else - RCV_NEXT_STATE <= SYNC; -- One stop bit selected. - end if; - else - RCV_NEXT_STATE <= STOP1; - end if; - when STOP2 => - if CLK_STRB = '1' then - RCV_NEXT_STATE <= SYNC; - else - RCV_NEXT_STATE <= STOP2; - end if; - when SYNC => - RCV_NEXT_STATE <= IDLE; - end case; - end process RCV_STATEDEC; -end architecture BEHAVIOR; - diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd.bak b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd.bak deleted file mode 100644 index 8877e05..0000000 --- a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_receive.vhd.bak +++ /dev/null @@ -1,425 +0,0 @@ ----------------------------------------------------------------------- ----- ---- ----- 6850 compatible IP Core ---- ----- ---- ----- This file is part of the SUSKA ATARI clone project. ---- ----- http://www.experiment-s.de ---- ----- ---- ----- Description: ---- ----- UART 6850 compatible IP core ---- ----- ---- ----- 6850's receiver unit. ---- ----- ---- ----- ---- ----- To Do: ---- ----- - ---- ----- ---- ----- Author(s): ---- ----- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2006 - 2008 Wolfgang Foerster ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.gnu.org/licenses/lgpl.html ---- ----- ---- ----------------------------------------------------------------------- --- --- Revision History --- --- Revision 2K6A 2006/06/03 WF --- Initial Release. --- Revision 2K6B 2006/11/07 WF --- Modified Source to compile with the Xilinx ISE. --- Revision 2K8A 2008/07/14 WF --- Minor changes. --- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; - -entity WF6850IP_RECEIVE is - port ( - CLK : in std_logic; - RESETn : in bit; - MCLR : in bit; - - CS : in bit_vector(2 downto 0); - E : in bit; - RWn : in bit; - RS : in bit; - - DATA_OUT : out bit_vector(7 downto 0); - DATA_EN : out bit; - - WS : in bit_vector(2 downto 0); - CDS : in bit_vector(1 downto 0); - - RXCLK : in bit; - RXDATA : in bit; - - RDRF : buffer bit; - OVR : out bit; - PE : out bit; - FE : out bit - ); -end entity WF6850IP_RECEIVE; - -architecture BEHAVIOR of WF6850IP_RECEIVE is -type RCV_STATES is (IDLE, WAIT_START, SAMPLE, PARITY, STOP1, STOP2, SYNC); -signal RCV_STATE, RCV_NEXT_STATE : RCV_STATES; -signal RXDATA_I : bit; -signal RXDATA_S : bit; -signal DATA_REG : bit_vector(7 downto 0); -signal SHIFT_REG : bit_vector(7 downto 0); -signal CLK_STRB : bit; -signal BITCNT : std_logic_vector(2 downto 0); -begin - P_SAMPLE: process(CLK) - -- This filter provides a synchronisation to the system - -- clock, even for random baud rates of the received data - -- stream. - variable FLT_TMP : integer range 0 to 2; - begin - if rising_edge(CLK) then - -- - RXDATA_I <= RXDATA; - -- - if RXDATA_I = '1' and FLT_TMP < 2 then - FLT_TMP := FLT_TMP + 1; - elsif RXDATA_I = '1' then - RXDATA_S <= '1'; - elsif RXDATA_I = '0' and FLT_TMP > 0 then - FLT_TMP := FLT_TMP - 1; - elsif RXDATA_I = '0' then - RXDATA_S <= '0'; - end if; - end if; - end process P_SAMPLE; - - CLKDIV: process(CLK) - variable CLK_LOCK : boolean; - variable STRB_LOCK : boolean; - variable CLK_DIVCNT : std_logic_vector(6 downto 0); - begin - if rising_edge(CLK) then - if CDS = "00" then -- Divider off. - if RXCLK = '1' and STRB_LOCK = false then - CLK_STRB <= '1'; - STRB_LOCK := true; - elsif RXCLK = '0' then - CLK_STRB <= '0'; - STRB_LOCK := false; - else - CLK_STRB <= '0'; - end if; - elsif RCV_STATE = IDLE then - -- Preset the CLKDIV with the start delays. - if CDS = "01" then - CLK_DIVCNT := "0001000"; -- Half of div by 16 mode. - elsif CDS = "10" then - CLK_DIVCNT := "0100000"; -- Half of div by 64 mode. - end if; - CLK_STRB <= '0'; - else - if CLK_DIVCNT > "0000000" and RXCLK = '1' and CLK_LOCK = false then - CLK_DIVCNT := CLK_DIVCNT - '1'; - CLK_STRB <= '0'; - CLK_LOCK := true; - elsif CDS = "01" and CLK_DIVCNT = "0000000" then - CLK_DIVCNT := "0010000"; -- Div by 16 mode. - -- - if STRB_LOCK = false then - STRB_LOCK := true; - CLK_STRB <= '1'; - else - CLK_STRB <= '0'; - end if; - elsif CDS = "10" and CLK_DIVCNT = "0000000" then - CLK_DIVCNT := "1000000"; -- Div by 64 mode. - if STRB_LOCK = false then - STRB_LOCK := true; - CLK_STRB <= '1'; - else - CLK_STRB <= '0'; - end if; - elsif RXCLK = '0' then - CLK_LOCK := false; - STRB_LOCK := false; - CLK_STRB <= '0'; - else - CLK_STRB <= '0'; - end if; - end if; - end if; - end process CLKDIV; - - DATAREG: process(RESETn, CLK) - begin - if RESETn = '0' or MCLR = '1' then - DATA_REG <= x"00"; - else - if rising_edge(CLK) then - if RCV_STATE = SYNC and WS(2) = '0' and RDRF = '0' then -- 7 bit data. - -- Transfer from shift- to data register only if - -- data register is empty (RDRF = '0'). - DATA_REG <= '0' & SHIFT_REG(7 downto 1); - elsif RCV_STATE = SYNC and WS(2) = '1' and RDRF = '0' then -- 8 bit data. - -- Transfer from shift- to data register only if - -- data register is empty (RDRF = '0'). - DATA_REG <= SHIFT_REG; - end if; - end if; - end if; - end process DATAREG; - DATA_OUT <= DATA_REG when CS = "011" and RWn = '1' and RS = '1' else (others => '0'); - DATA_EN <= '1' when CS = "011" and RWn = '1' and RS = '1' else '0'; - - SHIFTREG: process(RESETn, CLK) - begin - if RESETn = '0' or MCLR = '1' then - SHIFT_REG <= x"00"; - else - if rising_edge(CLK) then - if RCV_STATE = SAMPLE and CLK_STRB = '1' then - SHIFT_REG <= RXDATA_S & SHIFT_REG(7 downto 1); -- Shift right. - end if; - end if; - end if; - end process SHIFTREG; - - P_BITCNT: process(CLK) - begin - if rising_edge(CLK) then - if RCV_STATE = SAMPLE and CLK_STRB = '1' then - BITCNT <= BITCNT + '1'; - elsif RCV_STATE /= SAMPLE then - BITCNT <= (others => '0'); - end if; - end if; - end process P_BITCNT; - - FRAME_ERR: process(RESETn, CLK) - -- This module detects a framing error - -- during stop bit 1 and stop bit 2. - variable FE_I: bit; - begin - if RESETn = '0' then - FE_I := '0'; - FE <= '0'; - else - if rising_edge(CLK) then - if MCLR = '1' then - FE_I := '0'; - FE <= '0'; - elsif CLK_STRB = '1' then - if RCV_STATE = STOP1 and RXDATA_S = '0' then - FE_I := '1'; - elsif RCV_STATE = STOP2 and RXDATA_S = '0' then - FE_I := '1'; - elsif RCV_STATE = STOP1 or RCV_STATE = STOP2 then - FE_I := '0'; -- Error resets when correct data appears. - end if; - end if; - if RCV_STATE = SYNC then - FE <= FE_I; -- Update the FE every SYNC time. - end if; - end if; - end if; - end process FRAME_ERR; - - OVERRUN: process(RESETn, CLK) - variable OVR_I : bit; - variable FIRST_READ : boolean; - begin - if rising_edge(CLK) then - if RESETn = '0' or MCLR = '1' then - OVR_I := '0'; - OVR <= '0'; - FIRST_READ := false; - else - if CLK_STRB = '1' and RCV_STATE = STOP1 then - -- Overrun appears if RDRF is '1' in this state. - OVR_I := RDRF; - end if; - if CS = "011" and RWn = '1' and RS = '1' then - -- If an overrun was detected, the concerning flag is - -- set when the valid data word in the receiver data - -- register is read. Thereafter the RDRF flag is reset - -- and the overrun disappears (OVR_I goes low) after - -- a second read (in time) of the receiver data register. - if FIRST_READ = false then - if OVR_I = '1' then - OVR <= '1'; - OVR_I := '0'; - FIRST_READ := true; - else - OVR <= '0'; - end if; - end if; - else - FIRST_READ := false; - end if; - end if; - end if; - end process OVERRUN; - - PARITY_TEST: process(RESETn,MCLR,CLK) - variable PAR_TMP : bit; - variable PE_I : bit; - begin - if RESETn = '0' or MCRL = '1' then - PE <= '0'; - else - if rising_edge(CLK) then - if CLK_STRB = '1' then -- Sample parity on clock strobe. - PE_I := '0'; -- Initialise. - if RCV_STATE = PARITY then - for i in 1 to 7 loop - if i = 1 then - PAR_TMP := SHIFT_REG(i-1) xor SHIFT_REG(i); - else - PAR_TMP := PAR_TMP xor SHIFT_REG(i); - end if; - end loop; - if WS = "000" or WS = "010" or WS = "110" then -- Even parity. - PE_I := PAR_TMP xor RXDATA_S; - elsif WS = "001" or WS = "011" or WS = "111" then -- Odd parity. - PE_I := not PAR_TMP xor RXDATA_S; - else -- No parity for WS = "100" and WS = "101". - PE_I := '0'; - end if; - end if; - end if; - end if; - -- Transmit the parity flag together with the data - -- In other words: no parity to the status register - -- when RDRF inhibits the data transfer to the - -- receiver data register. - if RCV_STATE = SYNC and RDRF = '0' then - PE <= PE_I; - elsif CS = "011" and RWn = '1' and RS = '1' then - PE <= '0'; -- Clear when reading the data register. - end if; - end if; - end process PARITY_TEST; - - P_RDRF: process(RESETn, CLK) - -- Receive data register full flag. - begin - if rising_edge(CLK) then - if RESETn = '0' or MCLR = '1' then - RDRF <= '0'; - else - if RCV_STATE = SYNC then - RDRF <= '1'; -- Data register is full until now! - end if; - if CS = "011" and RWn = '1' and RS = '1' then - RDRF <= '0'; -- when reading the data register ... - end if; - end if; - end if; - end process P_RDRF; - - RCV_STATEREG: process(RESETn, CLK) - begin - if RESETn = '0' then - RCV_STATE <= IDLE; - else - if rising_edge(CLK) then - if MCLR = '1' then - RCV_STATE <= IDLE; - else - RCV_STATE <= RCV_NEXT_STATE; - end if; - end if; - end if; - end process RCV_STATEREG; - - RCV_STATEDEC: process(RCV_STATE, RXDATA_S, CDS, WS, BITCNT, CLK_STRB) - begin - case RCV_STATE is - when IDLE => - if RXDATA_S = '0' and CDS = "00" then - RCV_NEXT_STATE <= SAMPLE; -- Startbit detected in div by 1 mode. - elsif RXDATA_S = '0' and CDS = "01" then - RCV_NEXT_STATE <= WAIT_START; -- Startbit detected in div by 16 mode. - elsif RXDATA_S = '0' and CDS = "10" then - RCV_NEXT_STATE <= WAIT_START; -- Startbit detected in div by 64 mode. - else - RCV_NEXT_STATE <= IDLE; -- No startbit; sleep well :-) - end if; - when WAIT_START => - if CLK_STRB = '1' then - if RXDATA_S = '0' then - RCV_NEXT_STATE <= SAMPLE; -- Start condition in no div by 1 modes. - else - RCV_NEXT_STATE <= IDLE; -- No valid start condition, go back. - end if; - else - RCV_NEXT_STATE <= WAIT_START; -- Stay. - end if; - when SAMPLE => - if CLK_STRB = '1' then - if BITCNT < "110" and WS(2) = '0' then - RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 7 data bits. - elsif BITCNT < "111" and WS(2) = '1' then - RCV_NEXT_STATE <= SAMPLE; -- Go on sampling 8 data bits. - elsif WS = "100" or WS = "101" then - RCV_NEXT_STATE <= STOP1; -- No parity check enabled. - else - RCV_NEXT_STATE <= PARITY; -- Parity enabled. - end if; - else - RCV_NEXT_STATE <= SAMPLE; -- Stay in sample mode. - end if; - when PARITY => - if CLK_STRB = '1' then - RCV_NEXT_STATE <= STOP1; - else - RCV_NEXT_STATE <= PARITY; - end if; - when STOP1 => - if CLK_STRB = '1' then - if RXDATA_S = '0' then - RCV_NEXT_STATE <= SYNC; -- Framing error detected. - elsif WS = "000" or WS = "001" or WS = "100" then - RCV_NEXT_STATE <= STOP2; -- Two stop bits selected. - else - RCV_NEXT_STATE <= SYNC; -- One stop bit selected. - end if; - else - RCV_NEXT_STATE <= STOP1; - end if; - when STOP2 => - if CLK_STRB = '1' then - RCV_NEXT_STATE <= SYNC; - else - RCV_NEXT_STATE <= STOP2; - end if; - when SYNC => - RCV_NEXT_STATE <= IDLE; - end case; - end process RCV_STATEDEC; -end architecture BEHAVIOR; - diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd.bak b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd.bak deleted file mode 100644 index 6f80a67..0000000 --- a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_top_soc.vhd.bak +++ /dev/null @@ -1,252 +0,0 @@ ----------------------------------------------------------------------- ----- ---- ----- 6850 compatible IP Core ---- ----- ---- ----- This file is part of the SUSKA ATARI clone project. ---- ----- http://www.experiment-s.de ---- ----- ---- ----- Description: ---- ----- UART 6850 compatible IP core ---- ----- ---- ----- This is the top level file. ---- ----- Top level file for use in systems on programmable chips. ---- ----- ---- ----- ---- ----- To Do: ---- ----- - ---- ----- ---- ----- Author(s): ---- ----- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2006 - 2008 Wolfgang Foerster ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.gnu.org/licenses/lgpl.html ---- ----- ---- ----------------------------------------------------------------------- --- --- Revision History --- --- Revision 2K6A 2006/06/03 WF --- Initial Release. --- Revision 2K6B 2006/11/07 WF --- Modified Source to compile with the Xilinx ISE. --- Top level file provided for SOC (systems on programmable chips). --- Revision 2K8A 2008/07/14 WF --- Minor changes. --- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; - -entity WF6850IP_TOP_SOC is - port ( - CLK : in bit; - RESETn : in bit; - - CS2n, CS1, CS0 : in bit; - E : in bit; - RWn : in bit; - RS : in bit; - - DATA_IN : in std_logic_vector(7 downto 0); - DATA_OUT : out std_logic_vector(7 downto 0); - DATA_EN : out bit; - - TXCLK : in bit; - RXCLK : in bit; - RXDATA : in bit; - CTSn : in bit; - DCDn : in bit; - - IRQn : out bit; - TXDATA : out bit; - RTSn : out bit - ); -end entity WF6850IP_TOP_SOC; - -architecture STRUCTURE of WF6850IP_TOP_SOC is -component WF6850IP_CTRL_STATUS - port ( - CLK : in bit; - RESETn : in bit; - CS : in bit_vector(2 downto 0); - E : in bit; - RWn : in bit; - RS : in bit; - DATA_IN : in bit_vector(7 downto 0); - DATA_OUT : out bit_vector(7 downto 0); - DATA_EN : out bit; - RDRF : in bit; - TDRE : in bit; - DCDn : in bit; - CTSn : in bit; - FE : in bit; - OVR : in bit; - PE : in bit; - MCLR : out bit; - RTSn : out bit; - CDS : out bit_vector(1 downto 0); - WS : out bit_vector(2 downto 0); - TC : out bit_vector(1 downto 0); - IRQn : out bit - ); -end component; - -component WF6850IP_RECEIVE - port ( - CLK : in bit; - RESETn : in bit; - MCLR : in bit; - CS : in bit_vector(2 downto 0); - E : in bit; - RWn : in bit; - RS : in bit; - DATA_OUT : out bit_vector(7 downto 0); - DATA_EN : out bit; - WS : in bit_vector(2 downto 0); - CDS : in bit_vector(1 downto 0); - RXCLK : in bit; - RXDATA : in bit; - RDRF : out bit; - OVR : out bit; - PE : out bit; - FE : out bit - ); -end component; - -component WF6850IP_TRANSMIT - port ( - CLK : in bit; - RESETn : in bit; - MCLR : in bit; - CS : in bit_vector(2 downto 0); - E : in bit; - RWn : in bit; - RS : in bit; - DATA_IN : in bit_vector(7 downto 0); - CTSn : in bit; - TC : in bit_vector(1 downto 0); - WS : in bit_vector(2 downto 0); - CDS : in bit_vector(1 downto 0); - TXCLK : in bit; - TDRE : out bit; - TXDATA : out bit - ); -end component; -signal DATA_IN_I : bit_vector(7 downto 0); -signal DATA_RX : bit_vector(7 downto 0); -signal DATA_RX_EN : bit; -signal DATA_CTRL : bit_vector(7 downto 0); -signal DATA_CTRL_EN : bit; -signal RDRF_I : bit; -signal TDRE_I : bit; -signal FE_I : bit; -signal OVR_I : bit; -signal PE_I : bit; -signal MCLR_I : bit; -signal CDS_I : bit_vector(1 downto 0); -signal WS_I : bit_vector(2 downto 0); -signal TC_I : bit_vector(1 downto 0); -signal IRQ_In : bit; -begin - DATA_IN_I <= To_BitVector(DATA_IN); - DATA_EN <= DATA_RX_EN or DATA_CTRL_EN; - DATA_OUT <= To_StdLogicVector(DATA_RX) when DATA_RX_EN = '1' else - To_StdLogicVector(DATA_CTRL) when DATA_CTRL_EN = '1' else (others => '0'); - - IRQn <= '0' when IRQ_In = '0' else '1'; - - I_UART_CTRL_STATUS: WF6850IP_CTRL_STATUS - port map( - CLK => CLK, - RESETn => RESETn, - CS(2) => CS2n, - CS(1) => CS1, - CS(0) => CS0, - E => E, - RWn => RWn, - RS => RS, - DATA_IN => DATA_IN_I, - DATA_OUT => DATA_CTRL, - DATA_EN => DATA_CTRL_EN, - RDRF => RDRF_I, - TDRE => TDRE_I, - DCDn => DCDn, - CTSn => CTSn, - FE => FE_I, - OVR => OVR_I, - PE => PE_I, - MCLR => MCLR_I, - RTSn => RTSn, - CDS => CDS_I, - WS => WS_I, - TC => TC_I, - IRQn => IRQ_In - ); - - I_UART_RECEIVE: WF6850IP_RECEIVE - port map ( - CLK => CLK, - RESETn => RESETn, - MCLR => MCLR_I, - CS(2) => CS2n, - CS(1) => CS1, - CS(0) => CS0, - E => E, - RWn => RWn, - RS => RS, - DATA_OUT => DATA_RX, - DATA_EN => DATA_RX_EN, - WS => WS_I, - CDS => CDS_I, - RXCLK => RXCLK, - RXDATA => RXDATA, - RDRF => RDRF_I, - OVR => OVR_I, - PE => PE_I, - FE => FE_I - ); - - I_UART_TRANSMIT: WF6850IP_TRANSMIT - port map ( - CLK => CLK, - RESETn => RESETn, - MCLR => MCLR_I, - CS(2) => CS2n, - CS(1) => CS1, - CS(0) => CS0, - E => E, - RWn => RWn, - RS => RS, - DATA_IN => DATA_IN_I, - CTSn => CTSn, - TC => TC_I, - WS => WS_I, - CDS => CDS_I, - TDRE => TDRE_I, - TXCLK => TXCLK, - TXDATA => TXDATA - ); -end architecture STRUCTURE; \ No newline at end of file diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd.bak b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd.bak deleted file mode 100644 index d6953d5..0000000 --- a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/WF_UART6850_IP/wf6850ip_transmit.vhd.bak +++ /dev/null @@ -1,338 +0,0 @@ ----------------------------------------------------------------------- ----- ---- ----- 6850 compatible IP Core ---- ----- ---- ----- This file is part of the SUSKA ATARI clone project. ---- ----- http://www.experiment-s.de ---- ----- ---- ----- Description: ---- ----- UART 6850 compatible IP core ---- ----- ---- ----- 6850's transmitter unit. ---- ----- ---- ----- ---- ----- To Do: ---- ----- - ---- ----- ---- ----- Author(s): ---- ----- - Wolfgang Foerster, wf@experiment-s.de; wf@inventronik.de ---- ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2006 - 2008 Wolfgang Foerster ---- ----- ---- ----- This source file may be used and distributed without ---- ----- restriction provided that this copyright statement is not ---- ----- removed from the file and that any derivative work contains ---- ----- the original copyright notice and the associated disclaimer. ---- ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU Lesser General ---- ----- Public License as published by the Free Software Foundation; ---- ----- either version 2.1 of the License, or (at your option) any ---- ----- later version. ---- ----- ---- ----- This source is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU Lesser General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU Lesser General ---- ----- Public License along with this source; if not, download it ---- ----- from http://www.gnu.org/licenses/lgpl.html ---- ----- ---- ----------------------------------------------------------------------- --- --- Revision History --- --- Revision 2K6A 2006/06/03 WF --- Initial Release. --- Revision 2K6B 2006/11/07 WF --- Modified Source to compile with the Xilinx ISE. --- Revision 2K8A 2008/07/14 WF --- Minor changes. --- Revision 2K8B 2008/11/01 WF --- Fixed the T_DRE process concerning the TDRE <= '1' setting. --- Thanks to Lyndon Amsdon finding the bug. --- - -library ieee; -use ieee.std_logic_1164.all; -use ieee.std_logic_unsigned.all; - -entity WF6850IP_TRANSMIT is - port ( - CLK : in std_logic; - RESETn : in bit; - MCLR : in bit; - - CS : in bit_vector(2 downto 0); - E : in bit; - RWn : in bit; - RS : in bit; - - DATA_IN : in bit_vector(7 downto 0); - - CTSn : in bit; - - TC : in bit_vector(1 downto 0); - WS : in bit_vector(2 downto 0); - CDS : in bit_vector(1 downto 0); - - TXCLK : in bit; - - TDRE : buffer bit; - TXDATA : out bit - ); -end entity WF6850IP_TRANSMIT; - -architecture BEHAVIOR of WF6850IP_TRANSMIT is -type TR_STATES is (IDLE, LOAD_SHFT, START, SHIFTOUT, PARITY, STOP1, STOP2); -signal TR_STATE, TR_NEXT_STATE : TR_STATES; -signal CLK_STRB : bit; -signal DATA_REG : bit_vector(7 downto 0); -signal SHIFT_REG : bit_vector(7 downto 0); -signal BITCNT : std_logic_vector(2 downto 0); -signal PARITY_I : bit; -begin - -- The default condition in this statement is to ensure - -- to cover all possibilities for example if there is a - -- one hot decoding of the state machine with wrong states - -- (e.g. not one of the given here). - TXDATA <= '1' when TR_STATE = IDLE else - '1' when TR_STATE = LOAD_SHFT else - '0' when TR_STATE = START else - SHIFT_REG(0) when TR_STATE = SHIFTOUT else - PARITY_I when TR_STATE = PARITY else - '1' when TR_STATE = STOP1 else - '1' when TR_STATE = STOP2 else '1'; - - CLKDIV: process - variable CLK_LOCK : boolean; - variable STRB_LOCK : boolean; - variable CLK_DIVCNT : std_logic_vector(6 downto 0); - begin - if rising_edge(CLK) then - if CDS = "00" then -- divider off - if TXCLK = '0' and STRB_LOCK = false then -- Works on negative TXCLK edge. - CLK_STRB <= '1'; - STRB_LOCK := true; - elsif TXCLK = '1' then - CLK_STRB <= '0'; - STRB_LOCK := false; - else - CLK_STRB <= '0'; - end if; - elsif TR_STATE = IDLE then - -- preset the CLKDIV with the start delays - if CDS = "01" then - CLK_DIVCNT := "0010000"; -- div by 16 mode - elsif CDS = "10" then - CLK_DIVCNT := "1000000"; -- div by 64 mode - end if; - CLK_STRB <= '0'; - else - -- Works on negative TXCLK edge: - if CLK_DIVCNT > "0000000" and TXCLK = '0' and CLK_LOCK = false then - CLK_DIVCNT := CLK_DIVCNT - '1'; - CLK_STRB <= '0'; - CLK_LOCK := true; - elsif CDS = "01" and CLK_DIVCNT = "0000000" then - CLK_DIVCNT := "0010000"; -- Div by 16 mode. - if STRB_LOCK = false then - STRB_LOCK := true; - CLK_STRB <= '1'; - else - CLK_STRB <= '0'; - end if; - elsif CDS = "10" and CLK_DIVCNT = "0000000" then - CLK_DIVCNT := "1000000"; -- Div by 64 mode. - if STRB_LOCK = false then - STRB_LOCK := true; - CLK_STRB <= '1'; - else - CLK_STRB <= '0'; - end if; - elsif TXCLK = '1' then - CLK_LOCK := false; - STRB_LOCK := false; - CLK_STRB <= '0'; - else - CLK_STRB <= '0'; - end if; - end if; - end if; - end process CLKDIV; - - DATAREG: process(RESETn, CLK) - begin - if RESETn = '0' then - DATA_REG <= x"00"; - elsif rising_edge(CLK) then - if MCLR = '1' then - DATA_REG <= x"00"; - elsif WS(2) = '0' and CS = "011" and RWn = '0' and RS = '1' and E = '1' then - DATA_REG <= '0' & DATA_IN(6 downto 0); -- 7 bit data mode. - elsif WS(2) = '1' and CS = "011" and RWn = '0' and RS = '1' and E = '1' then - DATA_REG <= DATA_IN; -- 8 bit data mode. - end if; - end if; - end process DATAREG; - - SHIFTREG: process(RESETn, CLK) - begin - if RESETn = '0' then - SHIFT_REG <= x"00"; - elsif rising_edge(CLK) then - if MCLR = '1' then - SHIFT_REG <= x"00"; - elsif TR_STATE = LOAD_SHFT and TDRE = '0' then - -- If during LOAD_SHIFT the transmitter data register - -- is empty (TDRE = '1') the shift register will not - -- be loaded. When additionally TC = "11", the break - -- character (zero data and no stop bits) is sent. - SHIFT_REG <= DATA_REG; - elsif TR_STATE = SHIFTOUT and CLK_STRB = '1' then - SHIFT_REG <= '0' & SHIFT_REG(7 downto 1); -- Shift right. - end if; - end if; - end process SHIFTREG; - - P_BITCNT: process(CLK) - -- Counter for the data bits transmitted. - begin - if rising_edge(CLK) then - if TR_STATE = SHIFTOUT and CLK_STRB = '1' then - BITCNT <= BITCNT + '1'; - elsif TR_STATE /= SHIFTOUT then - BITCNT <= "000"; - end if; - end if; - end process P_BITCNT; - - P_TDRE: process(RESETn, CLK) - -- Transmit data register empty flag. - begin - if rising_edge(CLK) then - if RESETn = '0' or MCLR = '1' then - TDRE <= '1'; - else - if TR_NEXT_STATE = START and TR_STATE /= START then - -- Data has been loaded to shift register, thus data register is free again. - -- Thanks to Lyndon Amsdon for finding a bug here. The TDRE is set to one once - -- entering the state now. - TDRE <= '1'; - end if; - if CS = "011" and RWn = '0' and RS = '1' then - TDRE <= '0'; - end if; - end if; - end if; - end process P_TDRE; - - PARITY_GEN: process(CLK) - variable PAR_TMP : bit; - begin - if rising_edge(CLK) then - if TR_STATE = START then -- Calculate the parity during the start phase. - for i in 1 to 7 loop - if i = 1 then - PAR_TMP := SHIFT_REG(i-1) xor SHIFT_REG(i); - else - PAR_TMP := PAR_TMP xor SHIFT_REG(i); - end if; - end loop; - if WS = "000" or WS = "010" or WS = "110" then -- Even parity. - PARITY_I <= PAR_TMP; - elsif WS = "001" or WS = "011" or WS = "111" then -- Odd parity. - PARITY_I <= not PAR_TMP; - else -- No parity for WS = "100" and WS = "101". - PARITY_I <= '0'; - end if; - end if; - end if; - end process PARITY_GEN; - - TR_STATEREG: process(RESETn, CLK) - begin - if RESETn = '0' then - TR_STATE <= IDLE; - else - if rising_edge(CLK) then - if MCLR = '1' then - TR_STATE <= IDLE; - else - TR_STATE <= TR_NEXT_STATE; - end if; - end if; - end if; - end process TR_STATEREG; - - TR_STATEDEC: process(TR_STATE, CLK_STRB, TC, BITCNT, WS, TDRE, CTSn) - begin - case TR_STATE is - when IDLE => - if TDRE = '1' and TC = "11" then - TR_NEXT_STATE <= LOAD_SHFT; - elsif TDRE = '0' and CTSn = '0' then -- Start if data register is not empty. - TR_NEXT_STATE <= LOAD_SHFT; - else - TR_NEXT_STATE <= IDLE; - end if; - when LOAD_SHFT => - TR_NEXT_STATE <= START; - when START => - if CLK_STRB = '1' then - TR_NEXT_STATE <= SHIFTOUT; - else - TR_NEXT_STATE <= START; - end if; - when SHIFTOUT => - if CLK_STRB = '1' then - if BITCNT < "110" and WS(2) = '0' then - TR_NEXT_STATE <= SHIFTOUT; -- Transmit 7 data bits. - elsif BITCNT < "111" and WS(2) = '1' then - TR_NEXT_STATE <= SHIFTOUT; -- Transmit 8 data bits. - elsif WS = "100" or WS = "101" then - if TDRE = '1' and TC = "11" then - -- Break condition, do not send a stop bit. - TR_NEXT_STATE <= IDLE; - else - TR_NEXT_STATE <= STOP1; -- No parity check enabled. - end if; - else - TR_NEXT_STATE <= PARITY; -- Parity enabled. - end if; - else - TR_NEXT_STATE <= SHIFTOUT; - end if; - when PARITY => - if CLK_STRB = '1' then - if TDRE = '1' and TC = "11" then - -- Break condition, do not send a stop bit. - TR_NEXT_STATE <= IDLE; - else - TR_NEXT_STATE <= STOP1; -- No parity check enabled. - end if; - else - TR_NEXT_STATE <= PARITY; - end if; - when STOP1 => - if CLK_STRB = '1' and (WS = "000" or WS = "001" or WS = "100") then - TR_NEXT_STATE <= STOP2; -- Two stop bits selected. - elsif CLK_STRB = '1' then - TR_NEXT_STATE <= IDLE; -- One stop bits selected. - else - TR_NEXT_STATE <= STOP1; - end if; - when STOP2 => - if CLK_STRB = '1' then - TR_NEXT_STATE <= IDLE; - else - TR_NEXT_STATE <= STOP2; - end if; - end case; - end process TR_STATEDEC; -end architecture BEHAVIOR; - diff --git a/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/dcfifo1.vhd.bak b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/dcfifo1.vhd.bak new file mode 100644 index 0000000..e7c6ae6 --- /dev/null +++ b/FPGA_by_Fredi/FalconIO_SDCard_IDE_CF/dcfifo1.vhd.bak @@ -0,0 +1,202 @@ +-- megafunction wizard: %LPM_FIFO+% +-- GENERATION: STANDARD +-- VERSION: WM1.0 +-- MODULE: dcfifo_mixed_widths + +-- ============================================================ +-- File Name: dcfifo1.vhd +-- Megafunction Name(s): +-- dcfifo_mixed_widths +-- +-- Simulation Library Files(s): +-- altera_mf +-- ============================================================ +-- ************************************************************ +-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! +-- +-- 9.1 Build 222 10/21/2009 SJ Web Edition +-- ************************************************************ + + +--Copyright (C) 1991-2009 Altera Corporation +--Your use of Altera Corporation's design tools, logic functions +--and other software and tools, and its AMPP partner logic +--functions, and any output files from any of the foregoing +--(including device programming or simulation files), and any +--associated documentation or information are expressly subject +--to the terms and conditions of the Altera Program License +--Subscription Agreement, Altera MegaCore Function License +--Agreement, or other applicable license agreement, including, +--without limitation, that your use is for the sole purpose of +--programming logic devices manufactured by Altera and sold by +--Altera or its authorized distributors. Please refer to the +--applicable agreement for further details. + + +LIBRARY ieee; +USE ieee.std_logic_1164.all; + +LIBRARY altera_mf; +USE altera_mf.all; + +ENTITY dcfifo1 IS + PORT + ( + aclr : IN STD_LOGIC := '0'; + data : IN STD_LOGIC_VECTOR (15 DOWNTO 0); + rdclk : IN STD_LOGIC ; + rdreq : IN STD_LOGIC ; + wrclk : IN STD_LOGIC ; + wrreq : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + wrusedw : OUT STD_LOGIC_VECTOR (3 DOWNTO 0) + ); +END dcfifo1; + + +ARCHITECTURE SYN OF dcfifo1 IS + + SIGNAL sub_wire0 : STD_LOGIC_VECTOR (3 DOWNTO 0); + SIGNAL sub_wire1 : STD_LOGIC_VECTOR (7 DOWNTO 0); + + + + COMPONENT dcfifo_mixed_widths + GENERIC ( + intended_device_family : STRING; + lpm_numwords : NATURAL; + lpm_showahead : STRING; + lpm_type : STRING; + lpm_width : NATURAL; + lpm_widthu : NATURAL; + lpm_widthu_r : NATURAL; + lpm_width_r : NATURAL; + overflow_checking : STRING; + rdsync_delaypipe : NATURAL; + underflow_checking : STRING; + use_eab : STRING; + write_aclr_synch : STRING; + wrsync_delaypipe : NATURAL + ); + PORT ( + wrclk : IN STD_LOGIC ; + rdreq : IN STD_LOGIC ; + wrusedw : OUT STD_LOGIC_VECTOR (3 DOWNTO 0); + aclr : IN STD_LOGIC ; + rdclk : IN STD_LOGIC ; + q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); + wrreq : IN STD_LOGIC ; + data : IN STD_LOGIC_VECTOR (15 DOWNTO 0) + ); + END COMPONENT; + +BEGIN + wrusedw <= sub_wire0(3 DOWNTO 0); + q <= sub_wire1(7 DOWNTO 0); + + dcfifo_mixed_widths_component : dcfifo_mixed_widths + GENERIC MAP ( + intended_device_family => "Cyclone III", + lpm_numwords => 16, + lpm_showahead => "OFF", + lpm_type => "dcfifo", + lpm_width => 16, + lpm_widthu => 4, + lpm_widthu_r => 5, + lpm_width_r => 8, + overflow_checking => "ON", + rdsync_delaypipe => 5, + underflow_checking => "ON", + use_eab => "ON", + write_aclr_synch => "OFF", + wrsync_delaypipe => 5 + ) + PORT MAP ( + wrclk => wrclk, + rdreq => rdreq, + aclr => aclr, + rdclk => rdclk, + wrreq => wrreq, + data => data, + wrusedw => sub_wire0, + q => sub_wire1 + ); + + + +END SYN; + +-- ============================================================ +-- CNX file retrieval info +-- ============================================================ +-- Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0" +-- Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1" +-- Retrieval info: PRIVATE: AlmostFull NUMERIC "0" +-- Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1" +-- Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0" +-- Retrieval info: PRIVATE: Clock NUMERIC "4" +-- Retrieval info: PRIVATE: Depth NUMERIC "16" +-- Retrieval info: PRIVATE: Empty NUMERIC "1" +-- Retrieval info: PRIVATE: Full NUMERIC "1" +-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0" +-- Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1" +-- Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0" +-- Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0" +-- Retrieval info: PRIVATE: Optimize NUMERIC "1" +-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" +-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" +-- Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0" +-- Retrieval info: PRIVATE: UsedW NUMERIC "1" +-- Retrieval info: PRIVATE: Width NUMERIC "16" +-- Retrieval info: PRIVATE: dc_aclr NUMERIC "1" +-- Retrieval info: PRIVATE: diff_widths NUMERIC "1" +-- Retrieval info: PRIVATE: msb_usedw NUMERIC "0" +-- Retrieval info: PRIVATE: output_width NUMERIC "8" +-- Retrieval info: PRIVATE: rsEmpty NUMERIC "0" +-- Retrieval info: PRIVATE: rsFull NUMERIC "0" +-- Retrieval info: PRIVATE: rsUsedW NUMERIC "0" +-- Retrieval info: PRIVATE: sc_aclr NUMERIC "0" +-- Retrieval info: PRIVATE: sc_sclr NUMERIC "0" +-- Retrieval info: PRIVATE: wsEmpty NUMERIC "0" +-- Retrieval info: PRIVATE: wsFull NUMERIC "0" +-- Retrieval info: PRIVATE: wsUsedW NUMERIC "1" +-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" +-- Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "16" +-- Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF" +-- Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo" +-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16" +-- Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "4" +-- Retrieval info: CONSTANT: LPM_WIDTHU_R NUMERIC "5" +-- Retrieval info: CONSTANT: LPM_WIDTH_R NUMERIC "8" +-- Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON" +-- Retrieval info: CONSTANT: RDSYNC_DELAYPIPE NUMERIC "5" +-- Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON" +-- Retrieval info: CONSTANT: USE_EAB STRING "ON" +-- Retrieval info: CONSTANT: WRITE_ACLR_SYNCH STRING "OFF" +-- Retrieval info: CONSTANT: WRSYNC_DELAYPIPE NUMERIC "5" +-- Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr +-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0] +-- Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL q[7..0] +-- Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk +-- Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq +-- Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk +-- Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq +-- Retrieval info: USED_PORT: wrusedw 0 0 4 0 OUTPUT NODEFVAL wrusedw[3..0] +-- Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0 +-- Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0 +-- Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0 +-- Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0 +-- Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0 +-- Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0 +-- Retrieval info: CONNECT: wrusedw 0 0 4 0 @wrusedw 0 0 4 0 +-- Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0 +-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all +-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.vhd TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.inc FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.cmp TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1.bsf TRUE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1_inst.vhd FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1_waveforms.html FALSE +-- Retrieval info: GEN_FILE: TYPE_NORMAL dcfifo1_wave*.jpg FALSE +-- Retrieval info: LIB_FILE: altera_mf diff --git a/FPGA_by_Fredi/Interrupt_Handler/interrupt_handler.tdf.bak b/FPGA_by_Fredi/Interrupt_Handler/interrupt_handler.tdf.bak new file mode 100644 index 0000000..7e4aa32 --- /dev/null +++ b/FPGA_by_Fredi/Interrupt_Handler/interrupt_handler.tdf.bak @@ -0,0 +1,391 @@ +TITLE "INTERRUPT HANDLER UND C1287"; + +-- CREATED BY FREDI ASCHWANDEN + +INCLUDE "lpm_bustri_LONG.inc"; +INCLUDE "lpm_bustri_BYT.inc"; + + +-- Parameters Statement (optional) + +-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE! +-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE! + + +-- Subdesign Section + +SUBDESIGN interrupt_handler +( + -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! + MAIN_CLK : INPUT; + nFB_WR : INPUT; + nFB_CS1 : INPUT; + nFB_CS2 : INPUT; + FB_SIZE0 : INPUT; + FB_SIZE1 : INPUT; + FB_ADR[31..0] : INPUT; + FPGA_DATE[31..0] : INPUT; + PIC_INT : INPUT; + E0_INT : INPUT; + DVI_INT : INPUT; + nPCI_INTA : INPUT; + nPCI_INTB : INPUT; + nPCI_INTC : INPUT; + nPCI_INTD : INPUT; + nMFP_INT : INPUT; + nFB_OE : INPUT; + DSP_INT : INPUT; + VSYNC : INPUT; + HSYNC : INPUT; + DMA_DRQ : INPUT; + nRSTO : INPUT; + nIRQ[7..2] : OUTPUT; + INT_HANDLER_TA : OUTPUT; + ACP_CONF[31..0] : OUTPUT; + TIN0 : OUTPUT; + FB_AD[31..0] : BIDIR; + -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! +) + +VARIABLE + FB_B[3..0] :NODE; + INT_CTR[31..0] :DFFE; + INT_CTR_CS :NODE; + INT_LATCH[31..0] :DFF; + INT_LATCH_CS :NODE; + INT_CLEAR[31..0] :DFF; + INT_CLEAR_CS :NODE; + INT_IN[31..0] :NODE; + INT_ENA[31..0] :DFFE; + INT_ENA_CS :NODE; + INT_L[9..0] :DFF; + INT_LA[9..0][3..0] :DFF; + ACP_CONF[31..0] :DFFE; + ACP_CONF_CS :NODE; + FPGA_DATE_CS :NODE; + PSEUDO_BUS_ERROR :NODE; + UHR_AS :NODE; + UHR_DS :NODE; + RTC_ADR[5..0] :DFFE; + ACHTELSEKUNDEN[2..0] :DFFE; + WERTE[7..0][63..0] :DFFE; -- WERTE REGISTER 0-63 + PIC_INT_SYNC[2..0] :DFF; + INC_SEC :NODE; + INC_MIN :NODE; + INC_STD :NODE; + INC_TAG :NODE; + ANZAHL_TAGE_DES_MONATS[7..0]:NODE; + WINTERZEIT :NODE; + SOMMERZEIT :NODE; + INC_MONAT :NODE; + INC_JAHR :NODE; + UPDATE_ON :NODE; + +BEGIN +-- BYT SELECT + FB_B0 = FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HWORD + # !FB_SIZE1 & FB_SIZE0 & !FB_ADR1 & !FB_ADR0 -- HHBYT + # !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0; -- LONG UND LINE + FB_B1 = FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HWORD + # !FB_SIZE1 & FB_SIZE0 & !FB_ADR1 & FB_ADR0 -- HLBYT + # !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0; -- LONG UND LINE + FB_B2 = FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LWORD + # !FB_SIZE1 & FB_SIZE0 & FB_ADR1 & !FB_ADR0 -- LHBYT + # !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0; -- LONG UND LINE + FB_B3 = FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LWORD + # !FB_SIZE1 & FB_SIZE0 & FB_ADR1 & FB_ADR0 -- LLBYT + # !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0; -- LONG UND LINE + +-- INTERRUPT CONTROL REGISTER: BIT0=INT5 AUSLÖSEN, 1=INT7 AUSLÖSEN + INT_CTR[].CLK = MAIN_CLK; + INT_CTR_CS = !nFB_CS2 & FB_ADR[27..2]==H"4000"; -- $10000/4 + INT_CTR[] = FB_AD[]; + INT_CTR[31..24].ENA = INT_CTR_CS & FB_B0 & !nFB_WR; + INT_CTR[23..16].ENA = INT_CTR_CS & FB_B1 & !nFB_WR; + INT_CTR[15..8].ENA = INT_CTR_CS & FB_B2 & !nFB_WR; + INT_CTR[7..0].ENA = INT_CTR_CS & FB_B3 & !nFB_WR; +-- INTERRUPT ENABLE REGISTER BIT31=INT7,30=INT6,29=INT5,28=INT4,27=INT3,26=INT2 + INT_ENA[].CLK = MAIN_CLK; + INT_ENA[].CLRN = nRSTO; + INT_ENA_CS = !nFB_CS2 & FB_ADR[27..2]==H"4001"; -- $10004/4 + INT_ENA[] = FB_AD[]; + INT_ENA[31..24].ENA = INT_ENA_CS & FB_B0 & !nFB_WR; + INT_ENA[23..16].ENA = INT_ENA_CS & FB_B1 & !nFB_WR; + INT_ENA[15..8].ENA = INT_ENA_CS & FB_B2 & !nFB_WR; + INT_ENA[7..0].ENA = INT_ENA_CS & FB_B3 & !nFB_WR; +-- INTERRUPT CLEAR REGISTER WRITE ONLY 1=INTERRUPT CLEAR + INT_CLEAR[].CLK = MAIN_CLK; + INT_CLEAR_CS = !nFB_CS2 & FB_ADR[27..2]==H"4002"; -- $10008/4 + INT_CLEAR[31..24] = FB_AD[31..24] & INT_CLEAR_CS & FB_B0 & !nFB_WR; + INT_CLEAR[23..16] = FB_AD[23..16] & INT_CLEAR_CS & FB_B1 & !nFB_WR; + INT_CLEAR[15..8] = FB_AD[15..8] & INT_CLEAR_CS & FB_B2 & !nFB_WR; + INT_CLEAR[7..0] = FB_AD[7..0] & INT_CLEAR_CS & FB_B3 & !nFB_WR; +-- INTERRUPT LATCH REGISTER READ ONLY + INT_LATCH_CS = !nFB_CS2 & FB_ADR[27..2]==H"4003"; -- $1000C/4 +-- INTERRUPT + !nIRQ2 = HSYNC & INT_ENA[26]; + !nIRQ3 = INT_CTR0 & INT_ENA[27]; + !nIRQ4 = VSYNC & INT_ENA[28]; + !nIRQ5 = INT_LATCH[]!=H"00000000" & INT_ENA[29]; + !nIRQ6 = !nMFP_INT & INT_ENA[30]; + !nIRQ7 = PSEUDO_BUS_ERROR & INT_ENA[31]; + +PSEUDO_BUS_ERROR = !nFB_CS1 & (FB_ADR[19..4]==H"F8C8" -- SCC + # FB_ADR[19..4]==H"F8E0" -- VME +-- # FB_ADR[19..4]==H"F920" -- PADDLE +-- # FB_ADR[19..4]==H"F921" -- PADDLE +-- # FB_ADR[19..4]==H"F922" -- PADDLE + # FB_ADR[19..4]==H"FFA8" -- MFP2 + # FB_ADR[19..4]==H"FFA9" -- MFP2 + # FB_ADR[19..4]==H"FFAA" -- MFP2 + # FB_ADR[19..4]==H"FFA8" -- MFP2 + # FB_ADR[19..8]==H"F87" -- TT SCSI + # FB_ADR[19..4]==H"FFC2" -- ST UHR + # FB_ADR[19..4]==H"FFC3" -- ST UHR +-- # FB_ADR[19..4]==H"F890" -- DMA SOUND +-- # FB_ADR[19..4]==H"F891" -- DMA SOUND +-- # FB_ADR[19..4]==H"F892" -- DMA SOUND + ); +-- IF VIDEO ADR CHANGE +TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR; -- WRITE VIDEO BASE ADR HIGH 0xFFFF8201/2 + +-- INTERRUPT LATCH + INT_L[].CLK = MAIN_CLK; + INT_L[].CLRN = nRSTO; + INT_L0 = PIC_INT & INT_ENA[0]; + INT_L1 = E0_INT & INT_ENA[1]; + INT_L2 = DVI_INT & INT_ENA[2]; + INT_L3 = !nPCI_INTA & INT_ENA[3]; + INT_L4 = !nPCI_INTB & INT_ENA[4]; + INT_L5 = !nPCI_INTC & INT_ENA[5]; + INT_L6 = !nPCI_INTD & INT_ENA[6]; + INT_L7 = DSP_INT & INT_ENA[7]; + INT_L8 = VSYNC & INT_ENA[8]; + INT_L9 = HSYNC & INT_ENA[9]; + + INT_LA[][].CLK = MAIN_CLK; + INT_LATCH[] = H"FFFFFFFF"; + INT_LATCH[].CLRN = !INT_CLEAR[] & nRSTO; + FOR I IN 0 TO 9 GENERATE + INT_LA[I][].CLRN = INT_ENA[I] & nRSTO; + INT_LA[I][] = INT_LA[I][]+1 & INT_L[I] & INT_LA[I][]<7 + # INT_LA[I][]-1 & !INT_L[I] & INT_LA[I][]>8 + # 15 & INT_L[I] & INT_LA[I][]>6 + # 0 & !INT_L[I] & INT_LA[I][]<9; + INT_LATCH[I].CLK = INT_LA[I][3]; + END GENERATE; + +-- INT_IN + INT_IN0 = PIC_INT; + INT_IN1 = E0_INT; + INT_IN2 = DVI_INT; + INT_IN3 = !nPCI_INTA; + INT_IN4 = !nPCI_INTB; + INT_IN5 = !nPCI_INTC; + INT_IN6 = !nPCI_INTD; + INT_IN7 = DSP_INT; + INT_IN8 = VSYNC; + INT_IN9 = HSYNC; + INT_IN[25..10] = H"0"; + INT_IN26 = HSYNC; + INT_IN27 = INT_CTR0; + INT_IN28 = VSYNC; + INT_IN29 = INT_LATCH[]!=H"00000000"; + INT_IN30 = !nMFP_INT; + INT_IN31 = DMA_DRQ; +--*************************************************************************************** +-- ACP CONFIG REGISTER: BIT 31-> 0=CF 1=IDE + ACP_CONF[].CLK = MAIN_CLK; + ACP_CONF_CS = !nFB_CS2 & FB_ADR[27..2]==H"10000"; -- $4'0000/4 + ACP_CONF[] = FB_AD[]; + ACP_CONF[31..24].ENA = ACP_CONF_CS & FB_B0 & !nFB_WR; + ACP_CONF[23..16].ENA = ACP_CONF_CS & FB_B1 & !nFB_WR; + ACP_CONF[15..8].ENA = ACP_CONF_CS & FB_B2 & !nFB_WR; + ACP_CONF[7..0].ENA = ACP_CONF_CS & FB_B3 & !nFB_WR; +--*************************************************************************************** +-- FPGA DATE HEX (ddmmyyyy) + FPGA_DATE_CS = !nFB_CS2 & FB_ADR[27..2]==H"10040"; -- $4'0000/4 +--*************************************************************************************** + +-------------------------------------------------------------- +-- C1287 0=SEK 2=MIN 4=STD 6=WOCHENTAG 7=TAG 8=MONAT 9=JAHR +---------------------------------------------------------- + RTC_ADR[].CLK = MAIN_CLK; + RTC_ADR[] = FB_AD[21..16]; + UHR_AS = !nFB_CS1 & FB_ADR[19..1]==H"7C4B0" & FB_B1; -- FFFF8961 + UHR_DS = !nFB_CS1 & FB_ADR[19..1]==H"7C4B1" & FB_B3; -- FFFF8963 + RTC_ADR[].ENA = UHR_AS & !nFB_WR; + WERTE[][].CLK = MAIN_CLK; + WERTE[7..0][0] = FB_AD[23..16] & RTC_ADR[]==0 & UHR_DS & !nFB_WR; + WERTE[7..0][1] = FB_AD[23..16]; + WERTE[7..0][2] = FB_AD[23..16] & RTC_ADR[]==2 & UHR_DS & !nFB_WR; + WERTE[7..0][3] = FB_AD[23..16]; + WERTE[7..0][4] = FB_AD[23..16] & RTC_ADR[]==4 & UHR_DS & !nFB_WR; + WERTE[7..0][5] = FB_AD[23..16]; + WERTE[7..0][6] = FB_AD[23..16] & RTC_ADR[]==6 & UHR_DS & !nFB_WR; + WERTE[7..0][7] = FB_AD[23..16] & RTC_ADR[]==7 & UHR_DS & !nFB_WR; + WERTE[7..0][8] = FB_AD[23..16] & RTC_ADR[]==8 & UHR_DS & !nFB_WR; + WERTE[7..0][9] = FB_AD[23..16] & RTC_ADR[]==9 & UHR_DS & !nFB_WR; + FOR I IN 10 TO 63 GENERATE + WERTE[7..0][I] = FB_AD[23..16]; + END GENERATE; + FOR I IN 0 TO 63 GENERATE + WERTE[][I].ENA = RTC_ADR[]==I & UHR_DS & !nFB_WR; + END GENERATE; + PIC_INT_SYNC[].CLK = MAIN_CLK; + PIC_INT_SYNC[0] = PIC_INT; + PIC_INT_SYNC[1] = PIC_INT_SYNC[0]; + PIC_INT_SYNC[2] = !PIC_INT_SYNC[1] & PIC_INT_SYNC[0]; + UPDATE_ON = !WERTE[7][11]; + WERTE[6][10].CLRN = GND; -- KEIN UIP + UPDATE_ON = !WERTE[7][11]; -- UPDATE ON OFF + WERTE[2][11] = VCC; -- IMMER BINARY + WERTE[1][11] = VCC; -- IMMER 24H FORMAT + WERTE[0][11] = VCC; -- IMMER SOMMERZEITKORREKTUR + WERTE[7][13] = VCC; -- IMMER RICHTIG +-- SOMMER WINTERZEIT: BIT 0 IM REGISTER D IST DIE INFORMATION OB SOMMERZEIT IST (BRAUCHT MAN FÜR RÜCKSCHALTUNG) + SOMMERZEIT = WERTE[][6]==1 & WERTE[][4]==1 & WERTE[][8]==4 & WERTE[][7]>23; --LETZTER SONNTAG IM APRIL + WERTE[0][13] = SOMMERZEIT; + WERTE[0][13].ENA = INC_STD & (SOMMERZEIT # WINTERZEIT); + WINTERZEIT = WERTE[][6]==1 & WERTE[][4]==1 & WERTE[][8]==10 & WERTE[][7]>24 & WERTE[0][13]; --LETZTER SONNTAG IM OKTOBER +-- ACHTELSEKUNDEN + ACHTELSEKUNDEN[].CLK = MAIN_CLK; + ACHTELSEKUNDEN[] = ACHTELSEKUNDEN[]+1; + ACHTELSEKUNDEN[].ENA = PIC_INT_SYNC[2] & UPDATE_ON; +-- SEKUNDEN + INC_SEC = ACHTELSEKUNDEN[]==7 & PIC_INT_SYNC[2] & UPDATE_ON; + WERTE[][0] = (WERTE[][0]+1) & WERTE[][0]!=59 & !(RTC_ADR[]==0 & UHR_DS & !nFB_WR); -- SEKUNDEN ZÄHLEN BIS 59 + WERTE[][0].ENA = INC_SEC & !(RTC_ADR[]==0 & UHR_DS & !nFB_WR); +-- MINUTEN + INC_MIN = INC_SEC & WERTE[][0]==59; -- + WERTE[][2] = (WERTE[][2]+1) & WERTE[][2]!=59 & !(RTC_ADR[]==2 & UHR_DS & !nFB_WR); -- MINUTEN ZÄHLEN BIS 59 + WERTE[][2].ENA = INC_MIN & !(RTC_ADR[]==2 & UHR_DS & !nFB_WR); -- +-- STUNDEN + INC_STD = INC_MIN & WERTE[][2]==59; + WERTE[][4] = (WERTE[][4]+1+(1 & SOMMERZEIT)) & WERTE[][4]!=23 & !(RTC_ADR[]==4 & UHR_DS & !nFB_WR); -- STUNDEN ZÄHLEN BIS 23 + WERTE[][4].ENA = INC_STD & !(WINTERZEIT & WERTE[0][12]) & !(RTC_ADR[]==4 & UHR_DS & !nFB_WR); -- EINE STUNDE AUSLASSEN WENN WINTERZEITUMSCHALTUNG UND NOCH SOMMERZEIT +-- WOCHENTAG UND TAG + INC_TAG = INC_STD & WERTE[][2]==23; + WERTE[][6] = (WERTE[][6]+1) & WERTE[][6]!=7 & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR) -- WOCHENTAG ZÄHLEN BIS 7 + # 1 & WERTE[][6]==7 & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR); -- DANN BEI 1 WEITER + WERTE[][6].ENA = INC_TAG & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR); + ANZAHL_TAGE_DES_MONATS[] = 31 & (WERTE[][8]==1 # WERTE[][8]==3 # WERTE[][8]==5 # WERTE[][8]==7 # WERTE[][8]==8 # WERTE[][8]==10 # WERTE[][8]==12) + # 30 & (WERTE[][8]==4 # WERTE[][8]==6 # WERTE[][8]==9 # WERTE[][8]==11) + # 29 & WERTE[][8]==2 & WERTE[1..0][9]==0 + # 28 & WERTE[][8]==2 & WERTE[1..0][9]!=0; + WERTE[][7] = (WERTE[][7]+1) & WERTE[][7]!=ANZAHL_TAGE_DES_MONATS[] & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR) -- TAG ZÄHLEN BIS MONATSENDE + # 1 & WERTE[][7]==ANZAHL_TAGE_DES_MONATS[] & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR); -- DANN BEI 1 WEITER + WERTE[][7].ENA = INC_TAG & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR); -- +-- MONATE + INC_MONAT = INC_TAG & WERTE[][7]==ANZAHL_TAGE_DES_MONATS[]; -- + WERTE[][8] = (WERTE[][8]+1) & WERTE[][8]!=12 & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR) -- MONATE ZÄHLEN BIS 12 + # 1 & WERTE[][8]==12 & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR); -- DANN BEI 1 WEITER + WERTE[][8].ENA = INC_MONAT & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR); +-- JAHR + INC_JAHR = INC_MONAT & WERTE[][8]==12; -- + WERTE[][9] = (WERTE[][9]+1) & WERTE[][9]!=99 & !(RTC_ADR[]==9 & UHR_DS & !nFB_WR); -- JAHRE ZÄHLEN BIS 99 + WERTE[][9].ENA = INC_JAHR & !(RTC_ADR[]==9 & UHR_DS & !nFB_WR); +-- TRISTATE OUTPUT + + FB_AD[31..24] = lpm_bustri_BYT( + INT_CTR_CS & INT_CTR[31..24] + # INT_ENA_CS & INT_ENA[31..24] + # INT_LATCH_CS & INT_LATCH[31..24] + # INT_CLEAR_CS & INT_IN[31..24] + # ACP_CONF_CS & ACP_CONF[31..24] + # FPGA_DATE_CS & FPGA_DATE[31..24] + ,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE); + FB_AD[23..16] = lpm_bustri_BYT( + WERTE[][0] & RTC_ADR[]==0 & UHR_DS + # WERTE[][1] & RTC_ADR[]==1 & UHR_DS + # WERTE[][2] & RTC_ADR[]==2 & UHR_DS + # WERTE[][3] & RTC_ADR[]==3 & UHR_DS + # WERTE[][4] & RTC_ADR[]==4 & UHR_DS + # WERTE[][5] & RTC_ADR[]==5 & UHR_DS + # WERTE[][6] & RTC_ADR[]==6 & UHR_DS + # WERTE[][7] & RTC_ADR[]==7 & UHR_DS + # WERTE[][8] & RTC_ADR[]==8 & UHR_DS + # WERTE[][9] & RTC_ADR[]==9 & UHR_DS + # WERTE[][10] & RTC_ADR[]==10 & UHR_DS + # WERTE[][11] & RTC_ADR[]==11 & UHR_DS + # WERTE[][12] & RTC_ADR[]==12 & UHR_DS + # WERTE[][13] & RTC_ADR[]==13 & UHR_DS + # WERTE[][14] & RTC_ADR[]==14 & UHR_DS + # WERTE[][15] & RTC_ADR[]==15 & UHR_DS + # WERTE[][16] & RTC_ADR[]==16 & UHR_DS + # WERTE[][17] & RTC_ADR[]==17 & UHR_DS + # WERTE[][18] & RTC_ADR[]==18 & UHR_DS + # WERTE[][19] & RTC_ADR[]==19 & UHR_DS + # WERTE[][20] & RTC_ADR[]==20 & UHR_DS + # WERTE[][21] & RTC_ADR[]==21 & UHR_DS + # WERTE[][22] & RTC_ADR[]==22 & UHR_DS + # WERTE[][23] & RTC_ADR[]==23 & UHR_DS + # WERTE[][24] & RTC_ADR[]==24 & UHR_DS + # WERTE[][25] & RTC_ADR[]==25 & UHR_DS + # WERTE[][26] & RTC_ADR[]==26 & UHR_DS + # WERTE[][27] & RTC_ADR[]==27 & UHR_DS + # WERTE[][28] & RTC_ADR[]==28 & UHR_DS + # WERTE[][29] & RTC_ADR[]==29 & UHR_DS + # WERTE[][30] & RTC_ADR[]==30 & UHR_DS + # WERTE[][31] & RTC_ADR[]==31 & UHR_DS + # WERTE[][32] & RTC_ADR[]==32 & UHR_DS + # WERTE[][33] & RTC_ADR[]==33 & UHR_DS + # WERTE[][34] & RTC_ADR[]==34 & UHR_DS + # WERTE[][35] & RTC_ADR[]==35 & UHR_DS + # WERTE[][36] & RTC_ADR[]==36 & UHR_DS + # WERTE[][37] & RTC_ADR[]==37 & UHR_DS + # WERTE[][38] & RTC_ADR[]==38 & UHR_DS + # WERTE[][39] & RTC_ADR[]==39 & UHR_DS + # WERTE[][40] & RTC_ADR[]==40 & UHR_DS + # WERTE[][41] & RTC_ADR[]==41 & UHR_DS + # WERTE[][42] & RTC_ADR[]==42 & UHR_DS + # WERTE[][43] & RTC_ADR[]==43 & UHR_DS + # WERTE[][44] & RTC_ADR[]==44 & UHR_DS + # WERTE[][45] & RTC_ADR[]==45 & UHR_DS + # WERTE[][46] & RTC_ADR[]==46 & UHR_DS + # WERTE[][47] & RTC_ADR[]==47 & UHR_DS + # WERTE[][48] & RTC_ADR[]==48 & UHR_DS + # WERTE[][49] & RTC_ADR[]==49 & UHR_DS + # WERTE[][50] & RTC_ADR[]==50 & UHR_DS + # WERTE[][51] & RTC_ADR[]==51 & UHR_DS + # WERTE[][52] & RTC_ADR[]==52 & UHR_DS + # WERTE[][53] & RTC_ADR[]==53 & UHR_DS + # WERTE[][54] & RTC_ADR[]==54 & UHR_DS + # WERTE[][55] & RTC_ADR[]==55 & UHR_DS + # WERTE[][56] & RTC_ADR[]==56 & UHR_DS + # WERTE[][57] & RTC_ADR[]==57 & UHR_DS + # WERTE[][58] & RTC_ADR[]==58 & UHR_DS + # WERTE[][59] & RTC_ADR[]==59 & UHR_DS + # WERTE[][60] & RTC_ADR[]==60 & UHR_DS + # WERTE[][61] & RTC_ADR[]==61 & UHR_DS + # WERTE[][62] & RTC_ADR[]==62 & UHR_DS + # WERTE[][63] & RTC_ADR[]==63 & UHR_DS + # (0,RTC_ADR[]) & UHR_AS + # INT_CTR_CS & INT_CTR[23..16] + # INT_ENA_CS & INT_ENA[23..16] + # INT_LATCH_CS & INT_LATCH[23..16] + # INT_CLEAR_CS & INT_IN[23..16] + # ACP_CONF_CS & ACP_CONF[23..16] + # FPGA_DATE_CS & FPGA_DATE[23..16] + ,(UHR_DS # UHR_AS # INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE); + FB_AD[15..8] = lpm_bustri_BYT( + INT_CTR_CS & INT_CTR[15..8] + # INT_ENA_CS & INT_ENA[15..8] + # INT_LATCH_CS & INT_LATCH[15..8] + # INT_CLEAR_CS & INT_IN[15..8] + # ACP_CONF_CS & ACP_CONF[15..8] + # FPGA_DATE_CS & FPGA_DATE[15..8] + ,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE); + FB_AD[7..0] = lpm_bustri_BYT( + INT_CTR_CS & INT_CTR[7..0] + # INT_ENA_CS & INT_ENA[7..0] + # INT_LATCH_CS & INT_LATCH[7..0] + # INT_CLEAR_CS & INT_IN[7..0] + # ACP_CONF_CS & ACP_CONF[7..0] + # FPGA_DATE_CS & FPGA_DATE[7..0] + ,(INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS # ACP_CONF_CS) & !nFB_OE); + + INT_HANDLER_TA = INT_CTR_CS # INT_ENA_CS # INT_LATCH_CS # INT_CLEAR_CS; +END; + + diff --git a/FPGA_by_Fredi/PLLJ_PLLSPE_INFO.txt b/FPGA_by_Fredi/PLLJ_PLLSPE_INFO.txt new file mode 100644 index 0000000..797d4f8 --- /dev/null +++ b/FPGA_by_Fredi/PLLJ_PLLSPE_INFO.txt @@ -0,0 +1,20 @@ +PLL_Name altpll1:inst|altpll:altpll_component|altpll_3vp2:auto_generated|pll1 +PLLJITTER 36 +PLLSPEmax 84 +PLLSPEmin -53 + +PLL_Name altpll2:inst12|altpll:altpll_component|altpll_1r33:auto_generated|pll1 +PLLJITTER 43 +PLLSPEmax 84 +PLLSPEmin -53 + +PLL_Name altpll3:inst13|altpll:altpll_component|altpll_aus2:auto_generated|pll1 +PLLJITTER NA +PLLSPEmax 84 +PLLSPEmin -53 + +PLL_Name altpll4:inst22|altpll:altpll_component|altpll_r4n2:auto_generated|pll1 +PLLJITTER 31 +PLLSPEmax 84 +PLLSPEmin -53 + diff --git a/FPGA_by_Fredi/UNUSED b/FPGA_by_Fredi/UNUSED new file mode 100644 index 0000000..3a7d9e6 --- /dev/null +++ b/FPGA_by_Fredi/UNUSED @@ -0,0 +1,27 @@ + +-- Clearbox generated Memory Initialization File (.mif) + +WIDTH=3; +DEPTH=16; + +ADDRESS_RADIX=HEX; +DATA_RADIX=HEX; + +CONTENT BEGIN + 00 : 7; + 01 : 6; + 02 : 5; + 03 : 4; + 04 : 3; + 05 : 2; + 06 : 1; + 07 : 0; + 08 : 7; + 09 : 6; + 0a : 5; + 0b : 4; + 0c : 3; + 0d : 2; + 0e : 1; + 0f : 0; +END; diff --git a/FPGA_by_Fredi/Video/DDR_CTR.tdf.bak b/FPGA_by_Fredi/Video/DDR_CTR.tdf.bak new file mode 100644 index 0000000..c688f97 --- /dev/null +++ b/FPGA_by_Fredi/Video/DDR_CTR.tdf.bak @@ -0,0 +1,659 @@ +TITLE "DDR_CTR"; + +-- CREATED BY FREDI ASCHWANDEN + +INCLUDE "lpm_bustri_BYT.inc"; + +-- FIFO WATER MARK +CONSTANT FIFO_LWM = 0; +CONSTANT FIFO_MWM = 1000; +CONSTANT FIFO_HWM = 2000; + +-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE! +-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE! + +SUBDESIGN DDR_CTR +( + -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! + FB_ADR[31..0] : INPUT; + nFB_CS1 : INPUT; + nFB_CS2 : INPUT; + nFB_CS3 : INPUT; + nFB_OE : INPUT; + FB_SIZE0 : INPUT; + FB_SIZE1 : INPUT; + nRSTO : INPUT; + MAIN_CLK : INPUT; + FB_ALE : INPUT; + nFB_WR : INPUT; + DDR_SYNC_66M : INPUT; + CLR_FIFO : INPUT; + VIDEO_RAM_CTR[15..0] : INPUT; + BLITTER_ADR[31..0] : INPUT; + BLITTER_SIG : INPUT; + BLITTER_WR : INPUT; + DDRCLK0 : INPUT; + CLK33M : INPUT; + FIFO_MW[10..0] : INPUT; + VA[12..0] : OUTPUT; + nVWE : OUTPUT; + nVRAS : OUTPUT; + nVCS : OUTPUT; + VCKE : OUTPUT; + nVCAS : OUTPUT; + FB_LE[3..0] : OUTPUT; + FB_VDOE[3..0] : OUTPUT; + SR_FIFO_WRE : OUTPUT; + SR_DDR_FB : OUTPUT; + SR_DDR_WR : OUTPUT; + SR_DDRWR_D_SEL : OUTPUT; + SR_VDMP[7..0] : OUTPUT; + VIDEO_DDR_TA : OUTPUT; + SR_BLITTER_DACK : OUTPUT; + BA[1..0] : OUTPUT; + DDRWR_D_SEL1 : OUTPUT; + VDM_SEL[3..0] : OUTPUT; + FB_AD[31..0] : BIDIR; + -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! +) + +VARIABLE + FB_REGDDR :MACHINE WITH STATES(FR_WAIT,FR_S0,FR_S1,FR_S2,FR_S3); + DDR_SM :MACHINE WITH STATES(DS_T1,DS_T2A,DS_T2B,DS_T3,DS_N5,DS_N6, DS_N7, DS_N8, -- START (NORMAL 8 CYCLES TOTAL = 60ns) + DS_C2,DS_C3,DS_C4, DS_C5, DS_C6, DS_C7, -- CONFIG + DS_T4R,DS_T5R, -- READ CPU UND BLITTER, + DS_T4W,DS_T5W,DS_T6W,DS_T7W,DS_T8W,DS_T9W, -- WRITE CPU UND BLITTER + DS_T4F,DS_T5F,DS_T6F,DS_T7F,DS_T8F,DS_T9F,DS_T10F, -- READ FIFO + DS_CB6, DS_CB8, -- CLOSE FIFO BANK + DS_R2,DS_R3,DS_R4, DS_R5, DS_R6); -- REFRESH 10X7.5NS=75NS + LINE :NODE; + FB_B[3..0] :NODE; + VCAS :NODE; + VRAS :NODE; + VWE :NODE; + VA_P[12..0] :DFF; + BA_P[1..0] :DFF; + VA_S[12..0] :DFF; + BA_S[1..0] :DFF; + MCS[1..0] :DFF; + CPU_DDR_SYNC :DFF; + DDR_SEL :NODE; + DDR_CS :DFFE; + DDR_CONFIG :NODE; + SR_DDR_WR :DFF; + SR_DDRWR_D_SEL :DFF; + SR_VDMP[7..0] :DFF; + CPU_ROW_ADR[12..0] :NODE; + CPU_BA[1..0] :NODE; + CPU_COL_ADR[9..0] :NODE; + CPU_SIG :NODE; + CPU_REQ :DFF; + CPU_AC :DFF; + BUS_CYC :DFF; + BUS_CYC_END :NODE; + BLITTER_REQ :DFF; + BLITTER_AC :DFF; + BLITTER_ROW_ADR[12..0] :NODE; + BLITTER_BA[1..0] :NODE; + BLITTER_COL_ADR[9..0] :NODE; + FIFO_REQ :DFF; + FIFO_AC :DFF; + FIFO_ROW_ADR[12..0] :NODE; + FIFO_BA[1..0] :NODE; + FIFO_COL_ADR[9..0] :NODE; + FIFO_ACTIVE :NODE; + CLR_FIFO_SYNC :DFF; + CLEAR_FIFO_CNT :DFF; + STOP :DFF; + SR_FIFO_WRE :DFF; + FIFO_BANK_OK :DFF; + FIFO_BANK_NOT_OK :NODE; + DDR_REFRESH_ON :NODE; + DDR_REFRESH_CNT[10..0] :DFF; + DDR_REFRESH_REQ :DFF; + DDR_REFRESH_SIG[3..0] :DFFE; + REFRESH_TIME :DFF; + VIDEO_BASE_L_D[7..0] :DFFE; + VIDEO_BASE_L :NODE; + VIDEO_BASE_M_D[7..0] :DFFE; + VIDEO_BASE_M :NODE; + VIDEO_BASE_H_D[7..0] :DFFE; + VIDEO_BASE_H :NODE; + VIDEO_BASE_X_D[2..0] :DFFE; + VIDEO_ADR_CNT[22..0] :DFFE; + VIDEO_CNT_L :NODE; + VIDEO_CNT_M :NODE; + VIDEO_CNT_H :NODE; + VIDEO_BASE_ADR[22..0] :NODE; + VIDEO_ACT_ADR[26..0] :NODE; + +BEGIN + LINE = FB_SIZE0 & FB_SIZE1; +-- BYT SELECT + FB_B0 = FB_ADR[1..0]==0 -- ADR==0 + # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE + FB_B1 = FB_ADR[1..0]==1 -- ADR==1 + # FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HIGH WORD + # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE + FB_B2 = FB_ADR[1..0]==2 -- ADR==2 + # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE + FB_B3 = FB_ADR[1..0]==3 -- ADR==3 + # FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LOW WORD + # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE +-- CPU READ (REG DDR => CPU) AND WRITE (CPU => REG DDR) -------------------------------------------------- + FB_REGDDR.CLK = MAIN_CLK; + CASE FB_REGDDR IS + WHEN FR_WAIT => + FB_LE0 = !nFB_WR; + IF BUS_CYC # DDR_SEL & LINE & !nFB_WR THEN -- LOS WENN BEREIT ODER IMMER BEI LINE WRITE + FB_REGDDR = FR_S0; + ELSE + FB_REGDDR = FR_WAIT; + END IF; + WHEN FR_S0 => + IF DDR_CS THEN + FB_LE0 = !nFB_WR; + VIDEO_DDR_TA = VCC; + IF LINE THEN + FB_VDOE0 = !nFB_OE & !DDR_CONFIG; + FB_REGDDR = FR_S1; + ELSE + BUS_CYC_END = VCC; + FB_VDOE0 = !nFB_OE & !MAIN_CLK & !DDR_CONFIG; + FB_REGDDR = FR_WAIT; + END IF; + ELSE + FB_REGDDR = FR_WAIT; + END IF; + WHEN FR_S1 => + IF DDR_CS THEN + FB_VDOE1 = !nFB_OE & !DDR_CONFIG; + FB_LE1 = !nFB_WR; + VIDEO_DDR_TA = VCC; + FB_REGDDR = FR_S2; + ELSE + FB_REGDDR = FR_WAIT; + END IF; + WHEN FR_S2 => + IF DDR_CS THEN + FB_VDOE2 = !nFB_OE & !DDR_CONFIG; + FB_LE2 = !nFB_WR; + IF !BUS_CYC & LINE & !nFB_WR THEN -- BEI LINE WRITE EVT. WARTEN + FB_REGDDR = FR_S2; + ELSE + VIDEO_DDR_TA = VCC; + FB_REGDDR = FR_S3; + END IF; + ELSE + FB_REGDDR = FR_WAIT; + END IF; + WHEN FR_S3 => + IF DDR_CS THEN + FB_VDOE3 = !nFB_OE & !MAIN_CLK & !DDR_CONFIG; + FB_LE3 = !nFB_WR; + VIDEO_DDR_TA = VCC; + BUS_CYC_END = VCC; + FB_REGDDR = FR_WAIT; + ELSE + FB_REGDDR = FR_WAIT; + END IF; + END CASE; +-- DDR STEUERUNG ----------------------------------------------------- +-- VIDEO RAM CONTROL REGISTER (IST IN VIDEO_MUX_CTR) $F0000400: BIT 0: VCKE; 1: !nVCS ;2:REFRESH ON , (0=FIFO UND CNT CLEAR); 3: CONFIG; 8: FIFO_ACTIVE; + VCKE = VIDEO_RAM_CTR0; + nVCS = !VIDEO_RAM_CTR1; + DDR_REFRESH_ON = VIDEO_RAM_CTR2; + DDR_CONFIG = VIDEO_RAM_CTR3; + FIFO_ACTIVE = VIDEO_RAM_CTR8; +-------------------------------- + CPU_ROW_ADR[] = FB_ADR[26..14]; + CPU_BA[] = FB_ADR[13..12]; + CPU_COL_ADR[] = FB_ADR[11..2]; + nVRAS = !VRAS; + nVCAS = !VCAS; + nVWE = !VWE; + SR_DDR_WR.CLK = DDRCLK0; + SR_DDRWR_D_SEL.CLK = DDRCLK0; + SR_VDMP[7..0].CLK = DDRCLK0; + SR_FIFO_WRE.CLK = DDRCLK0; + CPU_AC.CLK = DDRCLK0; + FIFO_AC.CLK = DDRCLK0; + BLITTER_AC.CLK = DDRCLK0; + DDRWR_D_SEL1 = BLITTER_AC; +-- SELECT LOGIC + DDR_SEL = FB_ALE & FB_AD[31..30]==B"01"; + DDR_CS.CLK = MAIN_CLK; + DDR_CS.ENA = FB_ALE; + DDR_CS = DDR_SEL; +-- WENN READ ODER WRITE B,W,L DDR SOFORT ANFORDERN, BEI WRITE LINE SPÄTER + CPU_SIG = DDR_SEL & (nFB_WR # !LINE) & !DDR_CONFIG -- NICHT LINE ODER READ SOFORT LOS WENN NICHT CONFIG + # DDR_SEL & DDR_CONFIG -- CONFIG SOFORT LOS + # FB_REGDDR==FR_S1 & !nFB_WR; -- LINE WRITE SPÄTER + CPU_REQ.CLK = DDR_SYNC_66M; + CPU_REQ = CPU_SIG + # CPU_REQ & FB_REGDDR!=FR_S1 & FB_REGDDR!=FR_S3 & !BUS_CYC_END & !BUS_CYC; -- HALTEN BUS CYC BEGONNEN ODER FERTIG + BUS_CYC.CLK = DDRCLK0; + BUS_CYC = BUS_CYC & !BUS_CYC_END; + -- STATE MACHINE SYNCHRONISIEREN ----------------- + MCS[].CLK = DDRCLK0; + MCS0 = MAIN_CLK; + MCS1 = MCS0; + CPU_DDR_SYNC.CLK = DDRCLK0; + CPU_DDR_SYNC = MCS[]==2 & VCKE & !nVCS; -- NUR 1 WENN EIN + --------------------------------------------------- + VA_S[].CLK = DDRCLK0; + BA_S[].CLK = DDRCLK0; + VA[] = VA_S[]; + BA[] = BA_S[]; + VA_P[].CLK = DDRCLK0; + BA_P[].CLK = DDRCLK0; +-- DDR STATE MACHINE ----------------------------------------------- + DDR_SM.CLK = DDRCLK0; + CASE DDR_SM IS + WHEN DS_T1 => + IF DDR_REFRESH_REQ THEN + DDR_SM = DS_R2; + ELSE + IF CPU_DDR_SYNC THEN -- SYNCHRON UND EIN? + IF DDR_CONFIG THEN -- JA + DDR_SM = DS_C2; + ELSE + IF CPU_REQ THEN -- BEI WAIT UND LINE WRITE + VA_S[] = CPU_ROW_ADR[]; + BA_S[] = CPU_BA[]; + CPU_AC = VCC; + BUS_CYC = VCC; + DDR_SM = DS_T2B; + ELSE + IF FIFO_REQ # !BLITTER_REQ THEN -- FIFO IST DEFAULT + VA_P[] = FIFO_ROW_ADR[]; + BA_P[] = FIFO_BA[]; + FIFO_AC = VCC; -- VORBESETZEN + ELSE + VA_P[] = BLITTER_ROW_ADR[]; + BA_P[] = BLITTER_BA[]; + BLITTER_AC = VCC; -- VORBESETZEN + END IF; + DDR_SM = DS_T2A; + END IF; + END IF; + ELSE + DDR_SM = DS_T1; -- NEIN ->SYNCHRONISIEREN + END IF; + END IF; + + WHEN DS_T2A => -- SCHNELLZUGRIFF *** HIER IST PAGE IMMER NOT OK *** + IF DDR_SEL & (nFB_WR # !LINE) THEN + VRAS = VCC; + VA[] = FB_AD[26..14]; + BA[] = FB_AD[13..12]; + VA_S[10] = VCC; -- AUTO PRECHARGE DA NICHT FIFO PAGE + CPU_AC = VCC; + BUS_CYC = VCC; -- BUS CYCLUS LOSTRETEN + ELSE + VRAS = FIFO_AC & FIFO_REQ # BLITTER_AC & BLITTER_REQ; + VA[] = VA_P[]; + BA[] = BA_P[]; + VA_S[10] = !(FIFO_AC & FIFO_REQ); + FIFO_BANK_OK = FIFO_AC & FIFO_REQ; + FIFO_AC = FIFO_AC & FIFO_REQ; + BLITTER_AC = BLITTER_AC & BLITTER_REQ; + END IF; + DDR_SM = DS_T3; + + WHEN DS_T2B => + VRAS = VCC; + FIFO_BANK_NOT_OK = VCC; + CPU_AC = VCC; + BUS_CYC = VCC; -- BUS CYCLUS LOSTRETEN + DDR_SM = DS_T3; + + WHEN DS_T3 => + CPU_AC = CPU_AC; + FIFO_AC = FIFO_AC; + BLITTER_AC = BLITTER_AC; + VA_S[10] = VA_S[10]; -- AUTO PRECHARGE WENN NICHT FIFO PAGE + IF !nFB_WR & CPU_AC # BLITTER_WR & BLITTER_AC THEN + DDR_SM = DS_T4W; + ELSE + IF CPU_AC THEN -- CPU? + VA_S[9..0] = CPU_COL_ADR[]; + BA_S[] = CPU_BA[]; + DDR_SM = DS_T4R; + ELSE + IF FIFO_AC THEN -- FIFO? + VA_S[9..0] = FIFO_COL_ADR[]; + BA_S[] = FIFO_BA[]; + DDR_SM = DS_T4F; + ELSE + IF BLITTER_AC THEN + VA_S[9..0] = BLITTER_COL_ADR[]; + BA_S[] = BLITTER_BA[]; + DDR_SM = DS_T4R; + ELSE + DDR_SM = DS_N8; + END IF; + END IF; + END IF; + END IF; +-- READ + WHEN DS_T4R => + CPU_AC = CPU_AC; + BLITTER_AC = BLITTER_AC; + VCAS = VCC; + SR_DDR_FB = CPU_AC; -- READ DATEN FÜR CPU + SR_BLITTER_DACK = BLITTER_AC; -- BLITTER DACK AND BLITTER LATCH DATEN + DDR_SM = DS_T5R; + + WHEN DS_T5R => + CPU_AC = CPU_AC; + BLITTER_AC = BLITTER_AC; + IF FIFO_REQ & FIFO_BANK_OK THEN -- FIFO READ EINSCHIEBEN WENN BANK OK + VA_S[9..0] = FIFO_COL_ADR[]; + VA_S[10] = GND; -- MANUEL PRECHARGE + BA_S[] = FIFO_BA[]; + DDR_SM = DS_T6F; + ELSE + VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN + DDR_SM = DS_CB6; + END IF; +-- WRITE + WHEN DS_T4W => + CPU_AC = CPU_AC; + BLITTER_AC = BLITTER_AC; + SR_BLITTER_DACK = BLITTER_AC; -- BLITTER ACK AND BLITTER LATCH DATEN + VA_S[10] = VA_S[10]; -- AUTO PRECHARGE WENN NICHT FIFO PAGE + DDR_SM = DS_T5W; + + WHEN DS_T5W => + CPU_AC = CPU_AC; + BLITTER_AC = BLITTER_AC; + VA_S[9..0] = CPU_AC & CPU_COL_ADR[] + # BLITTER_AC & BLITTER_COL_ADR[]; + VA_S[10] = VA_S[10]; -- AUTO PRECHARGE WENN NICHT FIFO PAGE + BA_S[] = CPU_AC & CPU_BA[] + # BLITTER_AC & BLITTER_BA[]; + SR_VDMP[7..4] = FB_B[] # BLITTER_AC & B"1111"; -- BYTE ENABLE WRITE, BEI BLITTER IMMER LINE + SR_VDMP[3..0] = (LINE # BLITTER_AC) & B"1111"; -- LINE ENABLE WRITE, BEI BLITTER IMMER LINE + DDR_SM = DS_T6W; + + WHEN DS_T6W => + CPU_AC = CPU_AC; + BLITTER_AC = BLITTER_AC; + VCAS = VCC; + VWE = VCC; + SR_DDR_WR = VCC; -- WRITE COMMAND CPU UND BLITTER IF WRITER + SR_DDRWR_D_SEL = VCC; -- 2. HÄLFTE WRITE DATEN SELEKTIEREN + SR_VDMP[] = (LINE # BLITTER_AC) & B"11111111"; -- WENN LINE DANN ACTIV + DDR_SM = DS_T7W; + + WHEN DS_T7W => + CPU_AC = CPU_AC; + BLITTER_AC = BLITTER_AC; + SR_DDR_WR = VCC; -- WRITE COMMAND CPU UND BLITTER IF WRITE + SR_DDRWR_D_SEL = VCC; -- 2. HÄLFTE WRITE DATEN SELEKTIEREN + DDR_SM = DS_T8W; + + WHEN DS_T8W => + DDR_SM = DS_T9W; + + WHEN DS_T9W => + IF FIFO_REQ & FIFO_BANK_OK THEN + VA_S[9..0] = FIFO_COL_ADR[]; + VA_S[10] = GND; -- NON AUTO PRECHARGE + BA_S[] = FIFO_BA[]; + DDR_SM = DS_T6F; + ELSE + VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN + DDR_SM = DS_CB6; + END IF; +-- FIFO READ + WHEN DS_T4F => + VCAS = VCC; + SR_FIFO_WRE = VCC; -- DATEN WRITE FIFO + DDR_SM = DS_T5F; + + WHEN DS_T5F => + IF FIFO_REQ THEN + IF VIDEO_ADR_CNT[7..0]==H"FF" THEN -- NEUE PAGE? + VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN + DDR_SM = DS_CB6; -- BANK SCHLIESSEN + ELSE + VA_S[9..0] = FIFO_COL_ADR[]+4; + VA_S[10] = GND; -- NON AUTO PRECHARGE + BA_S[] = FIFO_BA[]; + DDR_SM = DS_T6F; + END IF; + ELSE + VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN + DDR_SM = DS_CB6; -- NOCH OFFEN LASSEN + END IF; + + WHEN DS_T6F => + VCAS = VCC; + SR_FIFO_WRE = VCC; -- DATEN WRITE FIFO + DDR_SM = DS_T7F; + + WHEN DS_T7F => + IF CPU_REQ & FIFO_MW[]>FIFO_LWM THEN + VA_S[10] = VCC; -- ALLE PAGES SCHLIESEN + DDR_SM = DS_CB8; -- BANK SCHLIESSEN + ELSE + IF FIFO_REQ THEN + IF VIDEO_ADR_CNT[7..0]==H"FF" THEN -- NEUE PAGE? + VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN + DDR_SM = DS_CB8; -- BANK SCHLIESSEN + ELSE + VA_S[9..0] = FIFO_COL_ADR[]+4; + VA_S[10] = GND; -- NON AUTO PRECHARGE + BA_S[] = FIFO_BA[]; + DDR_SM = DS_T8F; + END IF; + ELSE + VA_S[10] = VCC; -- ALLE PAGES SCHLIESEN + DDR_SM = DS_CB8; -- BANK SCHLIESSEN + END IF; + END IF; + + WHEN DS_T8F => + VCAS = VCC; + SR_FIFO_WRE = VCC; -- DATEN WRITE FIFO + IF FIFO_MW[] + ELSE + DDR_SM = DS_T9F; + END IF; + + WHEN DS_T9F => + IF FIFO_REQ THEN + IF VIDEO_ADR_CNT[7..0]==H"FF" THEN -- NEUE PAGE? + VA_S[10] = VCC; -- ALLE BANKS SCHLIESEN + DDR_SM = DS_CB6; -- BANK SCHLIESSEN + ELSE + VA_P[9..0] = FIFO_COL_ADR[]+4; + VA_P[10] = GND; -- NON AUTO PRECHARGE + BA_P[] = FIFO_BA[]; + DDR_SM = DS_T10F; + END IF; + ELSE + VA_S[10] = VCC; -- ALLE BANKS SCHLIESEN + DDR_SM = DS_CB6; -- BANK SCHLIESSEN + END IF; + + WHEN DS_T10F => + IF DDR_SEL & (nFB_WR # !LINE) & FB_AD[13..12]!=FIFO_BA[] THEN + VRAS = VCC; + VA[] = FB_AD[26..14]; + BA[] = FB_AD[13..12]; + CPU_AC = VCC; + BUS_CYC = VCC; -- BUS CYCLUS LOSTRETEN + VA_S[10] = VCC; -- AUTO PRECHARGE DA NICHT FIFO BANK + DDR_SM = DS_T3; + ELSE + VCAS = VCC; + VA[] = VA_P[]; + BA[] = BA_P[]; + SR_FIFO_WRE = VCC; -- DATEN WRITE FIFO + DDR_SM = DS_T7F; + END IF; + +-- CONFIG CYCLUS + WHEN DS_C2 => + DDR_SM = DS_C3; + WHEN DS_C3 => + BUS_CYC = CPU_REQ; + DDR_SM = DS_C4; + WHEN DS_C4 => + IF CPU_REQ THEN + DDR_SM = DS_C5; + ELSE + DDR_SM = DS_T1; + END IF; + WHEN DS_C5 => + DDR_SM = DS_C6; + WHEN DS_C6 => + VA_S[] = FB_AD[12..0]; + BA_S[] = FB_AD[14..13]; + DDR_SM = DS_C7; + WHEN DS_C7 => + VRAS = FB_AD18 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1; -- NUR BEI LONG WRITE + VCAS = FB_AD17 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1; -- NUR BEI LONG WRITE + VWE = FB_AD16 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1; -- NUR BEI LONG WRITE + DDR_SM = DS_N8; +-- CLOSE FIFO BANK + WHEN DS_CB6 => + FIFO_BANK_NOT_OK = VCC; -- AUF NOT OK + VRAS = VCC; -- BÄNKE SCHLIESSEN + VWE = VCC; + DDR_SM = DS_N7; + WHEN DS_CB8 => + FIFO_BANK_NOT_OK = VCC; -- AUF NOT OK + VRAS = VCC; -- BÄNKE SCHLIESSEN + VWE = VCC; + DDR_SM = DS_T1; +-- REFRESH 70NS = 10 ZYCLEN + WHEN DS_R2 => + IF DDR_REFRESH_SIG[]==9 THEN -- EIN CYCLUS VORLAUF UM BANKS ZU SCHLIESSEN + VRAS = VCC; -- ALLE BANKS SCHLIESSEN + VWE = VCC; + VA[10] = VCC; + FIFO_BANK_NOT_OK = VCC; + DDR_SM = DS_R4; + ELSE + VCAS = VCC; + VRAS = VCC; + DDR_SM = DS_R3; + END IF; + WHEN DS_R3 => + DDR_SM = DS_R4; + WHEN DS_R4 => + DDR_SM = DS_R5; + WHEN DS_R5 => + DDR_SM = DS_R6; + WHEN DS_R6 => + DDR_SM = DS_N5; +-- LEERSCHLAUFE + WHEN DS_N5 => + DDR_SM = DS_N6; + WHEN DS_N6 => + DDR_SM = DS_N7; + WHEN DS_N7 => + DDR_SM = DS_N8; + WHEN DS_N8 => + DDR_SM = DS_T1; + END CASE; + +--------------------------------------------------------------- +-- BLITTER ---------------------- +----------------------------------------- + BLITTER_REQ.CLK = DDRCLK0; + BLITTER_REQ = BLITTER_SIG & !DDR_CONFIG & VCKE & !nVCS; + BLITTER_ROW_ADR[] = BLITTER_ADR[26..14]; + BLITTER_BA1 = BLITTER_ADR13; + BLITTER_BA0 = BLITTER_ADR12; + BLITTER_COL_ADR[] = BLITTER_ADR[11..2]; +------------------------------------------------------------------------------ +-- FIFO --------------------------------- +-------------------------------------------------------- + FIFO_REQ.CLK = DDRCLK0; + FIFO_REQ = (FIFO_MW[]2048 33MHz CLOCKS +----------------------------------------------------------------------------------------- + DDR_REFRESH_CNT[].CLK = CLK33M; + DDR_REFRESH_CNT[] = DDR_REFRESH_CNT[]+1; -- ZÄHLEN 0-2047 + REFRESH_TIME.CLK = DDRCLK0; + REFRESH_TIME = DDR_REFRESH_CNT[]==0 & !MAIN_CLK; -- SYNC + DDR_REFRESH_SIG[].CLK = DDRCLK0; + DDR_REFRESH_SIG[].ENA = REFRESH_TIME # DDR_SM==DS_R6; + DDR_REFRESH_SIG[] = REFRESH_TIME & 9 & DDR_REFRESH_ON & !DDR_CONFIG -- 9 STÜCK (8 REFRESH UND 1 ALS VORLAUF) + # !REFRESH_TIME & (DDR_REFRESH_SIG[]-1) & DDR_REFRESH_ON & !DDR_CONFIG; -- MINUS 1 WENN GEMACHT + DDR_REFRESH_REQ.CLK = DDRCLK0; + DDR_REFRESH_REQ = DDR_REFRESH_SIG[]!=0 & DDR_REFRESH_ON & !REFRESH_TIME & !DDR_CONFIG; +----------------------------------------------------------- +-- VIDEO REGISTER ----------------------- +--------------------------------------------------------------------------------------------------------------------- + VIDEO_BASE_L_D[].CLK = MAIN_CLK; + VIDEO_BASE_L = !nFB_CS1 & FB_ADR[19..1]==H"7C106"; -- 820D/2 + VIDEO_BASE_L_D[] = FB_AD[23..16]; -- SORRY, NUR 16 BYT GRENZEN + VIDEO_BASE_L_D[].ENA = !nFB_WR & VIDEO_BASE_L & FB_B1; + + VIDEO_BASE_M_D[].CLK = MAIN_CLK; + VIDEO_BASE_M = !nFB_CS1 & FB_ADR[19..1]==H"7C101"; -- 8203/2 + VIDEO_BASE_M_D[] = FB_AD[23..16]; + VIDEO_BASE_M_D[].ENA = !nFB_WR & VIDEO_BASE_M & FB_B3; + + VIDEO_BASE_H_D[].CLK = MAIN_CLK; + VIDEO_BASE_H = !nFB_CS1 & FB_ADR[19..1]==H"7C100"; -- 8200-1/2 + VIDEO_BASE_H_D[] = FB_AD[23..16]; + VIDEO_BASE_H_D[].ENA = !nFB_WR & VIDEO_BASE_H & FB_B1; + VIDEO_BASE_X_D[].CLK = MAIN_CLK; + VIDEO_BASE_X_D[] = FB_AD[26..24]; + VIDEO_BASE_X_D[].ENA = !nFB_WR & VIDEO_BASE_H & FB_B0; + + VIDEO_CNT_L = !nFB_CS1 & FB_ADR[19..1]==H"7C104"; -- 8209/2 + VIDEO_CNT_M = !nFB_CS1 & FB_ADR[19..1]==H"7C103"; -- 8207/2 + VIDEO_CNT_H = !nFB_CS1 & FB_ADR[19..1]==H"7C102"; -- 8204,5/2 + + FB_AD[31..24] = lpm_bustri_BYT( + VIDEO_BASE_H & (0,VIDEO_BASE_X_D[]) + # VIDEO_CNT_H & (0,VIDEO_ACT_ADR[26..24]) + ,(VIDEO_BASE_H # VIDEO_CNT_H) & !nFB_OE); + + FB_AD[23..16] = lpm_bustri_BYT( + VIDEO_BASE_L & VIDEO_BASE_L_D[] + # VIDEO_BASE_M & VIDEO_BASE_M_D[] + # VIDEO_BASE_H & VIDEO_BASE_H_D[] + # VIDEO_CNT_L & VIDEO_ACT_ADR[7..0] + # VIDEO_CNT_M & VIDEO_ACT_ADR[15..8] + # VIDEO_CNT_H & VIDEO_ACT_ADR[23..16] + ,(VIDEO_BASE_L # VIDEO_BASE_M # VIDEO_BASE_H # VIDEO_CNT_L # VIDEO_CNT_M # VIDEO_CNT_H) & !nFB_OE); +END; + diff --git a/FPGA_by_Fredi/Video/UNUSED b/FPGA_by_Fredi/Video/UNUSED new file mode 100644 index 0000000..12f424b --- /dev/null +++ b/FPGA_by_Fredi/Video/UNUSED @@ -0,0 +1,267 @@ + +-- Clearbox generated Memory Initialization File (.mif) + +WIDTH=6; +DEPTH=256; + +ADDRESS_RADIX=HEX; +DATA_RADIX=HEX; + +CONTENT BEGIN + 000 : 0F; + 001 : 0E; + 002 : 0D; + 003 : 0C; + 004 : 0B; + 005 : 0A; + 006 : 09; + 007 : 08; + 008 : 07; + 009 : 06; + 00a : 05; + 00b : 04; + 00c : 03; + 00d : 02; + 00e : 01; + 00f : 00; + 010 : 0F; + 011 : 0E; + 012 : 0D; + 013 : 0C; + 014 : 0B; + 015 : 0A; + 016 : 09; + 017 : 08; + 018 : 07; + 019 : 06; + 01a : 05; + 01b : 04; + 01c : 03; + 01d : 02; + 01e : 01; + 01f : 00; + 020 : 0F; + 021 : 0E; + 022 : 0D; + 023 : 0C; + 024 : 0B; + 025 : 0A; + 026 : 09; + 027 : 08; + 028 : 07; + 029 : 06; + 02a : 05; + 02b : 04; + 02c : 03; + 02d : 02; + 02e : 01; + 02f : 00; + 030 : 0F; + 031 : 0E; + 032 : 0D; + 033 : 0C; + 034 : 0B; + 035 : 0A; + 036 : 09; + 037 : 08; + 038 : 07; + 039 : 06; + 03a : 05; + 03b : 04; + 03c : 03; + 03d : 02; + 03e : 01; + 03f : 00; + 040 : 0F; + 041 : 0E; + 042 : 0D; + 043 : 0C; + 044 : 0B; + 045 : 0A; + 046 : 09; + 047 : 08; + 048 : 07; + 049 : 06; + 04a : 05; + 04b : 04; + 04c : 03; + 04d : 02; + 04e : 01; + 04f : 00; + 050 : 0F; + 051 : 0E; + 052 : 0D; + 053 : 0C; + 054 : 0B; + 055 : 0A; + 056 : 09; + 057 : 08; + 058 : 07; + 059 : 06; + 05a : 05; + 05b : 04; + 05c : 03; + 05d : 02; + 05e : 01; + 05f : 00; + 060 : 0F; + 061 : 0E; + 062 : 0D; + 063 : 0C; + 064 : 0B; + 065 : 0A; + 066 : 09; + 067 : 08; + 068 : 07; + 069 : 06; + 06a : 05; + 06b : 04; + 06c : 03; + 06d : 02; + 06e : 01; + 06f : 00; + 070 : 0F; + 071 : 0E; + 072 : 0D; + 073 : 0C; + 074 : 0B; + 075 : 0A; + 076 : 09; + 077 : 08; + 078 : 07; + 079 : 06; + 07a : 05; + 07b : 04; + 07c : 03; + 07d : 02; + 07e : 01; + 07f : 00; + 080 : 0F; + 081 : 0E; + 082 : 0D; + 083 : 0C; + 084 : 0B; + 085 : 0A; + 086 : 09; + 087 : 08; + 088 : 07; + 089 : 06; + 08a : 05; + 08b : 04; + 08c : 03; + 08d : 02; + 08e : 01; + 08f : 00; + 090 : 0F; + 091 : 0E; + 092 : 0D; + 093 : 0C; + 094 : 0B; + 095 : 0A; + 096 : 09; + 097 : 08; + 098 : 07; + 099 : 06; + 09a : 05; + 09b : 04; + 09c : 03; + 09d : 02; + 09e : 01; + 09f : 00; + 0a0 : 0F; + 0a1 : 0E; + 0a2 : 0D; + 0a3 : 0C; + 0a4 : 0B; + 0a5 : 0A; + 0a6 : 09; + 0a7 : 08; + 0a8 : 07; + 0a9 : 06; + 0aa : 05; + 0ab : 04; + 0ac : 03; + 0ad : 02; + 0ae : 01; + 0af : 00; + 0b0 : 0F; + 0b1 : 0E; + 0b2 : 0D; + 0b3 : 0C; + 0b4 : 0B; + 0b5 : 0A; + 0b6 : 09; + 0b7 : 08; + 0b8 : 07; + 0b9 : 06; + 0ba : 05; + 0bb : 04; + 0bc : 03; + 0bd : 02; + 0be : 01; + 0bf : 00; + 0c0 : 0F; + 0c1 : 0E; + 0c2 : 0D; + 0c3 : 0C; + 0c4 : 0B; + 0c5 : 0A; + 0c6 : 09; + 0c7 : 08; + 0c8 : 07; + 0c9 : 06; + 0ca : 05; + 0cb : 04; + 0cc : 03; + 0cd : 02; + 0ce : 01; + 0cf : 00; + 0d0 : 0F; + 0d1 : 0E; + 0d2 : 0D; + 0d3 : 0C; + 0d4 : 0B; + 0d5 : 0A; + 0d6 : 09; + 0d7 : 08; + 0d8 : 07; + 0d9 : 06; + 0da : 05; + 0db : 04; + 0dc : 03; + 0dd : 02; + 0de : 01; + 0df : 00; + 0e0 : 0F; + 0e1 : 0E; + 0e2 : 0D; + 0e3 : 0C; + 0e4 : 0B; + 0e5 : 0A; + 0e6 : 09; + 0e7 : 08; + 0e8 : 07; + 0e9 : 06; + 0ea : 05; + 0eb : 04; + 0ec : 03; + 0ed : 02; + 0ee : 01; + 0ef : 00; + 0f0 : 0F; + 0f1 : 0E; + 0f2 : 0D; + 0f3 : 0C; + 0f4 : 0B; + 0f5 : 0A; + 0f6 : 09; + 0f7 : 08; + 0f8 : 07; + 0f9 : 06; + 0fa : 05; + 0fb : 04; + 0fc : 03; + 0fd : 02; + 0fe : 01; + 0ff : 00; +END; diff --git a/FPGA_by_Fredi/Video/VIDEO_MOD_MUX_CLUTCTR.tdf.bak b/FPGA_by_Fredi/Video/VIDEO_MOD_MUX_CLUTCTR.tdf.bak new file mode 100644 index 0000000..2a594ff --- /dev/null +++ b/FPGA_by_Fredi/Video/VIDEO_MOD_MUX_CLUTCTR.tdf.bak @@ -0,0 +1,675 @@ +TITLE "VIDEO MODUSE UND CLUT CONTROL"; + +-- CREATED BY FREDI ASCHWANDEN + +INCLUDE "lpm_bustri_WORD.inc"; +INCLUDE "lpm_bustri_BYT.inc"; + +-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE! +-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE! + +SUBDESIGN VIDEO_MOD_MUX_CLUTCTR +( + -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! + nRSTO : INPUT; + MAIN_CLK : INPUT; + nFB_CS1 : INPUT; + nFB_CS2 : INPUT; + nFB_CS3 : INPUT; + nFB_WR : INPUT; + nFB_OE : INPUT; + FB_SIZE0 : INPUT; + FB_SIZE1 : INPUT; + nFB_BURST : INPUT; + FB_ADR[31..0] : INPUT; + CLK33M : INPUT; + CLK25M : INPUT; + BLITTER_RUN : INPUT; + CLK_VIDEO : INPUT; + VR_D[8..0] : INPUT; + VR_BUSY : INPUT; + COLOR8 : OUTPUT; + ACP_CLUT_RD : OUTPUT; + COLOR1 : OUTPUT; + FALCON_CLUT_RDH : OUTPUT; + FALCON_CLUT_RDL : OUTPUT; + FALCON_CLUT_WR[3..0] : OUTPUT; + ST_CLUT_RD : OUTPUT; + ST_CLUT_WR[1..0] : OUTPUT; + CLUT_MUX_ADR[3..0] : OUTPUT; + HSYNC : OUTPUT; + VSYNC : OUTPUT; + nBLANK : OUTPUT; + nSYNC : OUTPUT; + nPD_VGA : OUTPUT; + FIFO_RDE : OUTPUT; + COLOR2 : OUTPUT; + COLOR4 : OUTPUT; + PIXEL_CLK : OUTPUT; + CLUT_OFF[3..0] : OUTPUT; + BLITTER_ON : OUTPUT; + VIDEO_RAM_CTR[15..0] : OUTPUT; + VIDEO_MOD_TA : OUTPUT; + CCR[23..0] : OUTPUT; + CCSEL[2..0] : OUTPUT; + ACP_CLUT_WR[3..0] : OUTPUT; + INTER_ZEI : OUTPUT; + DOP_FIFO_CLR : OUTPUT; + VIDEO_RECONFIG : OUTPUT; + VR_WR : OUTPUT; + VR_RD : OUTPUT; + CLR_FIFO : OUTPUT; + FB_AD[31..0] : BIDIR; + -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! +) + +VARIABLE + CLK17M :DFF; + CLK13M :DFF; + ACP_CLUT_CS :NODE; + ACP_CLUT :NODE; + VIDEO_PLL_CONFIG_CS :NODE; + VR_WR :DFF; + VR_DOUT[8..0] :DFFE; + VR_FRQ[7..0] :DFFE; + VIDEO_PLL_RECONFIG_CS :NODE; + VIDEO_RECONFIG :DFF; + FALCON_CLUT_CS :NODE; + FALCON_CLUT :NODE; + ST_CLUT_CS :NODE; + ST_CLUT :NODE; + FB_B[3..0] :NODE; + FB_16B[1..0] :NODE; + ST_SHIFT_MODE[1..0] :DFFE; + ST_SHIFT_MODE_CS :NODE; + FALCON_SHIFT_MODE[10..0] :DFFE; + FALCON_SHIFT_MODE_CS :NODE; + CLUT_MUX_ADR[3..0] :DFF; + CLUT_MUX_AV[1..0][3..0] :DFF; + ACP_VCTR_CS :NODE; + ACP_VCTR[31..0] :DFFE; + CCR_CS :NODE; + CCR[23..0] :DFFE; + ACP_VIDEO_ON :NODE; + SYS_CTR[6..0] :DFFE; + SYS_CTR_CS :NODE; + VDL_LOF[15..0] :DFFE; + VDL_LOF_CS :NODE; + VDL_LWD[15..0] :DFFE; + VDL_LWD_CS :NODE; +-- DIV. CONTROL REGISTER + CLUT_TA :DFF; -- BRAUCHT EIN WAITSTAT + HSYNC :DFF; + HSYNC_I[7..0] :DFF; + HSY_LEN[7..0] :DFF; -- LÄNGE HSYNC PULS IN PIXEL_CLK + HSYNC_START :DFF; + LAST :DFF; -- LETZTES PIXEL EINER ZEILE ERREICHT + VSYNC :DFF; + VSYNC_START :DFFE; + VSYNC_I[2..0] :DFFE; + nBLANK :DFF; + DISP_ON :DFF; + DPO_ZL :DFFE; + DPO_ON :DFF; + DPO_OFF :DFF; + VDTRON :DFF; + VDO_ZL :DFFE; + VDO_ON :DFF; + VDO_OFF :DFF; + VHCNT[11..0] :DFF; + SUB_PIXEL_CNT[6..0] :DFFE; + VVCNT[10..0] :DFFE; + VERZ[2..0][9..0] :DFF; + RAND[6..0] :DFF; + RAND_ON :NODE; + FIFO_RDE :DFF; + CLR_FIFO :DFFE; + START_ZEILE :DFFE; + SYNC_PIX :DFF; + SYNC_PIX1 :DFF; + SYNC_PIX2 :DFF; + CCSEL[2..0] :DFF; + COLOR16 :NODE; + COLOR24 :NODE; +-- ATARI RESOLUTION + ATARI_SYNC :NODE; + ATARI_HH[31..0] :DFFE; -- HORIZONTAL TIMING 640x480 + ATARI_HH_CS :NODE; + ATARI_VH[31..0] :DFFE; -- VERTIKAL TIMING 640x480 + ATARI_VH_CS :NODE; + ATARI_HL[31..0] :DFFE; -- HORIZONTAL TIMING 320x240 + ATARI_HL_CS :NODE; + ATARI_VL[31..0] :DFFE; -- VERTIKAL TIMING 320x240 + ATARI_VL_CS :NODE; +-- HORIZONTAL + RAND_LINKS[11..0] :NODE; + HDIS_START[11..0] :NODE; + HDIS_END[11..0] :NODE; + RAND_RECHTS[11..0] :NODE; + HS_START[11..0] :NODE; + H_TOTAL[11..0] :NODE; + HDIS_LEN[11..0] :NODE; + MULF[5..0] :NODE; + VDL_HHT[11..0] :DFFE; + VDL_HHT_CS :NODE; + VDL_HBE[11..0] :DFFE; + VDL_HBE_CS :NODE; + VDL_HDB[11..0] :DFFE; + VDL_HDB_CS :NODE; + VDL_HDE[11..0] :DFFE; + VDL_HDE_CS :NODE; + VDL_HBB[11..0] :DFFE; + VDL_HBB_CS :NODE; + VDL_HSS[11..0] :DFFE; + VDL_HSS_CS :NODE; +-- VERTIKAL + RAND_OBEN[10..0] :NODE; + VDIS_START[10..0] :NODE; + VDIS_END[10..0] :NODE; + RAND_UNTEN[10..0] :NODE; + VS_START[10..0] :NODE; + V_TOTAL[10..0] :NODE; + FALCON_VIDEO :NODE; + ST_VIDEO :NODE; + INTER_ZEI :DFF; + DOP_ZEI :DFF; + DOP_FIFO_CLR :DFF; + + VDL_VBE[10..0] :DFFE; + VDL_VBE_CS :NODE; + VDL_VDB[10..0] :DFFE; + VDL_VDB_CS :NODE; + VDL_VDE[10..0] :DFFE; + VDL_VDE_CS :NODE; + VDL_VBB[10..0] :DFFE; + VDL_VBB_CS :NODE; + VDL_VSS[10..0] :DFFE; + VDL_VSS_CS :NODE; + VDL_VFT[10..0] :DFFE; + VDL_VFT_CS :NODE; + VDL_VCT[8..0] :DFFE; + VDL_VCT_CS :NODE; + VDL_VMD[3..0] :DFFE; + VDL_VMD_CS :NODE; + +BEGIN +-- BYT SELECT 32 BIT + FB_B0 = FB_ADR[1..0]==0; -- ADR==0 + FB_B1 = FB_ADR[1..0]==1 -- ADR==1 + # FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HIGH WORD + # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE + FB_B2 = FB_ADR[1..0]==2 -- ADR==2 + # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE + FB_B3 = FB_ADR[1..0]==3 -- ADR==3 + # FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LOW WORD + # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE +-- BYT SELECT 16 BIT + FB_16B0 = FB_ADR[0]==0; -- ADR==0 + FB_16B1 = FB_ADR[0]==1 -- ADR==1 + # !(!FB_SIZE1 & FB_SIZE0); -- NOT BYT +-- ACP CLUT -- + ACP_CLUT_CS = !nFB_CS2 & FB_ADR[27..10]==H"0"; -- 0-3FF/1024 + ACP_CLUT_RD = ACP_CLUT_CS & !nFB_OE; + ACP_CLUT_WR[] = FB_B[] & ACP_CLUT_CS & !nFB_WR; + CLUT_TA.CLK = MAIN_CLK; + CLUT_TA = (ACP_CLUT_CS # FALCON_CLUT_CS # ST_CLUT_CS) & !VIDEO_MOD_TA; +--FALCON CLUT -- + FALCON_CLUT_CS = !nFB_CS1 & FB_ADR[19..10]==H"3E6"; -- $F9800/$400 + FALCON_CLUT_RDH = FALCON_CLUT_CS & !nFB_OE & !FB_ADR1; -- HIGH WORD + FALCON_CLUT_RDL = FALCON_CLUT_CS & !nFB_OE & FB_ADR1; -- LOW WORD + FALCON_CLUT_WR[1..0] = FB_16B[] & !FB_ADR1 & FALCON_CLUT_CS & !nFB_WR; + FALCON_CLUT_WR[3..2] = FB_16B[] & FB_ADR1 & FALCON_CLUT_CS & !nFB_WR; +-- ST CLUT -- + ST_CLUT_CS = !nFB_CS1 & FB_ADR[19..5]==H"7C12"; -- $F8240/$20 + ST_CLUT_RD = ST_CLUT_CS & !nFB_OE; + ST_CLUT_WR[] = FB_16B[] & ST_CLUT_CS & !nFB_WR; +-- ST SHIFT MODE + ST_SHIFT_MODE[].CLK = MAIN_CLK; + ST_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C130"; -- $F8260/2 + ST_SHIFT_MODE[] = FB_AD[25..24]; + ST_SHIFT_MODE[].ENA = ST_SHIFT_MODE_CS & !nFB_WR & FB_B0; + COLOR1 = ST_SHIFT_MODE[]==B"10" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- MONO + COLOR2 = ST_SHIFT_MODE[]==B"01" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- 4 FARBEN + COLOR4 = ST_SHIFT_MODE[]==B"00" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- 16 FARBEN +-- FALCON SHIFT MODE + FALCON_SHIFT_MODE[].CLK = MAIN_CLK; + FALCON_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C133"; -- $F8266/2 + FALCON_SHIFT_MODE[] = FB_AD[26..16]; + FALCON_SHIFT_MODE[10..8].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B2; + FALCON_SHIFT_MODE[7..0].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B3; + CLUT_OFF[3..0] = FALCON_SHIFT_MODE[3..0] & COLOR4; + COLOR1 = FALCON_SHIFT_MODE10 & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON; + COLOR8 = FALCON_SHIFT_MODE4 & !COLOR16 & FALCON_VIDEO & !ACP_VIDEO_ON; + COLOR16 = FALCON_SHIFT_MODE8 & FALCON_VIDEO & !ACP_VIDEO_ON; + COLOR4 = !COLOR1 & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON; +-- ACP VIDEO CONTROL BIT 0=ACP VIDEO ON, 1=POWER ON VIDEO DAC, 2=ACP 24BIT,3=ACP 16BIT,4=ACP 8BIT,5=ACP 1BIT, 6=FALCON SHIFT MODE;7=ST SHIFT MODE;9..8= VCLK FREQUENZ;15=-SYNC ALLOWED; 31..16=VIDEO_RAM_CTR,25=RANDFARBE EINSCHALTEN, 26=STANDARD ATARI SYNCS + ACP_VCTR[].CLK = MAIN_CLK; + ACP_VCTR_CS = !nFB_CS2 & FB_ADR[27..2]==H"100"; -- $400/4 + ACP_VCTR[31..8] = FB_AD[31..8]; + ACP_VCTR[5..0] = FB_AD[5..0]; + ACP_VCTR[31..24].ENA = ACP_VCTR_CS & FB_B0 & !nFB_WR; + ACP_VCTR[23..16].ENA = ACP_VCTR_CS & FB_B1 & !nFB_WR; + ACP_VCTR[15..8].ENA = ACP_VCTR_CS & FB_B2 & !nFB_WR; + ACP_VCTR[5..0].ENA = ACP_VCTR_CS & FB_B3 & !nFB_WR; + ACP_VIDEO_ON = ACP_VCTR0; + nPD_VGA = ACP_VCTR1; + -- ATARI MODUS + ATARI_SYNC = ACP_VCTR26; -- WENN 1 AUTOMATISCHE AUFLÖSUNG + -- HORIZONTAL TIMING 640x480 + ATARI_HH[].CLK = MAIN_CLK; + ATARI_HH_CS = !nFB_CS2 & FB_ADR[27..2]==H"104"; -- $410/4 + ATARI_HH[] = FB_AD[]; + ATARI_HH[31..24].ENA = ATARI_HH_CS & FB_B0 & !nFB_WR; + ATARI_HH[23..16].ENA = ATARI_HH_CS & FB_B1 & !nFB_WR; + ATARI_HH[15..8].ENA = ATARI_HH_CS & FB_B2 & !nFB_WR; + ATARI_HH[7..0].ENA = ATARI_HH_CS & FB_B3 & !nFB_WR; + -- VERTIKAL TIMING 640x480 + ATARI_VH[].CLK = MAIN_CLK; + ATARI_VH_CS = !nFB_CS2 & FB_ADR[27..2]==H"105"; -- $414/4 + ATARI_VH[] = FB_AD[]; + ATARI_VH[31..24].ENA = ATARI_VH_CS & FB_B0 & !nFB_WR; + ATARI_VH[23..16].ENA = ATARI_VH_CS & FB_B1 & !nFB_WR; + ATARI_VH[15..8].ENA = ATARI_VH_CS & FB_B2 & !nFB_WR; + ATARI_VH[7..0].ENA = ATARI_VH_CS & FB_B3 & !nFB_WR; + -- HORIZONTAL TIMING 320x240 + ATARI_HL[].CLK = MAIN_CLK; + ATARI_HL_CS = !nFB_CS2 & FB_ADR[27..2]==H"106"; -- $418/4 + ATARI_HL[] = FB_AD[]; + ATARI_HL[31..24].ENA = ATARI_HL_CS & FB_B0 & !nFB_WR; + ATARI_HL[23..16].ENA = ATARI_HL_CS & FB_B1 & !nFB_WR; + ATARI_HL[15..8].ENA = ATARI_HL_CS & FB_B2 & !nFB_WR; + ATARI_HL[7..0].ENA = ATARI_HL_CS & FB_B3 & !nFB_WR; + -- VERTIKAL TIMING 320x240 + ATARI_VL[].CLK = MAIN_CLK; + ATARI_VL_CS = !nFB_CS2 & FB_ADR[27..2]==H"107"; -- $41C/4 + ATARI_VL[] = FB_AD[]; + ATARI_VL[31..24].ENA = ATARI_VL_CS & FB_B0 & !nFB_WR; + ATARI_VL[23..16].ENA = ATARI_VL_CS & FB_B1 & !nFB_WR; + ATARI_VL[15..8].ENA = ATARI_VL_CS & FB_B2 & !nFB_WR; + ATARI_VL[7..0].ENA = ATARI_VL_CS & FB_B3 & !nFB_WR; +-- VIDEO PLL CONFIG + VIDEO_PLL_CONFIG_CS = !nFB_CS2 & FB_ADR[27..9]==H"3" & FB_B0 & FB_B1; -- $(F)000'0600-7FF ->6/2 WORD RESP LONG ONLY + VR_WR.CLK = MAIN_CLK; + VR_WR = VIDEO_PLL_CONFIG_CS & !nFB_WR & !VR_BUSY & !VR_WR; + VR_RD = VIDEO_PLL_CONFIG_CS & nFB_WR & !VR_BUSY; + VR_DOUT[].CLK = MAIN_CLK; + VR_DOUT[].ENA = !VR_BUSY; + VR_DOUT[] = VR_D[]; + VR_FRQ[].CLK = MAIN_CLK; + VR_FRQ[].ENA = VR_WR & FB_ADR[8..0]==H"04"; + VR_FRQ[] = FB_AD[23..16]; +-- VIDEO PLL RECONFIG + VIDEO_PLL_RECONFIG_CS = !nFB_CS2 & FB_ADR[27..0]==H"800" & FB_B0; -- $(F)000'0800 + VIDEO_RECONFIG.CLK = MAIN_CLK; + VIDEO_RECONFIG = VIDEO_PLL_RECONFIG_CS & !nFB_WR & !VR_BUSY & !VIDEO_RECONFIG; +------------------------------------------------------------------------------------------------------------------------ + VIDEO_RAM_CTR[] = ACP_VCTR[31..16]; +-------------- COLOR MODE IM ACP SETZEN + COLOR1 = ACP_VCTR5 & !ACP_VCTR4 & !ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON; + COLOR8 = ACP_VCTR4 & !ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON; + COLOR16 = ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON; + COLOR24 = ACP_VCTR2 & ACP_VIDEO_ON; + ACP_CLUT = ACP_VIDEO_ON & (COLOR1 # COLOR8) # ST_VIDEO & COLOR1; +-- ST ODER FALCON SHIFT MODE SETZEN WENN WRITE X..SHIFT REGISTER + ACP_VCTR7 = FALCON_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON; + ACP_VCTR6 = ST_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON; + ACP_VCTR[7..6].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR # ST_SHIFT_MODE_CS & !nFB_WR # ACP_VCTR_CS & FB_B3 & !nFB_WR & FB_AD0; + FALCON_VIDEO = ACP_VCTR7; + FALCON_CLUT = FALCON_VIDEO & !ACP_VIDEO_ON & !COLOR16; + ST_VIDEO = ACP_VCTR6; + ST_CLUT = ST_VIDEO & !ACP_VIDEO_ON & !FALCON_CLUT & !COLOR1; + CCSEL[].CLK = PIXEL_CLK; + CCSEL[] = B"000" & ST_CLUT -- ONLY FOR INFORMATION + # B"001" & FALCON_CLUT + # B"100" & ACP_CLUT + # B"101" & COLOR16 + # B"110" & COLOR24 + # B"111" & RAND_ON; +-- DIVERSE (VIDEO)-REGISTER ---------------------------- +-- RANDFARBE + CCR[].CLK = MAIN_CLK; + CCR_CS = !nFB_CS2 & FB_ADR[27..2]==H"101"; -- $404/4 + CCR[] = FB_AD[23..0]; + CCR[23..16].ENA = CCR_CS & FB_B1 & !nFB_WR; + CCR[15..8].ENA = CCR_CS & FB_B2 & !nFB_WR; + CCR[7..0].ENA = CCR_CS & FB_B3 & !nFB_WR; +--SYS CTR + SYS_CTR_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C003"; -- $8006/2 + SYS_CTR[].CLK = MAIN_CLK; + SYS_CTR[6..0] = FB_AD[22..16]; + SYS_CTR[6..0].ENA = SYS_CTR_CS & !nFB_WR & FB_B3; + BLITTER_ON = !SYS_CTR3; +--VDL_LOF + VDL_LOF_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C107"; -- $820E/2 + VDL_LOF[].CLK = MAIN_CLK; + VDL_LOF[] = FB_AD[31..16]; + VDL_LOF[15..8].ENA = VDL_LOF_CS & !nFB_WR & FB_B2; + VDL_LOF[7..0].ENA = VDL_LOF_CS & !nFB_WR & FB_B3; +--VDL_LWD + VDL_LWD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C108"; -- $8210/2 + VDL_LWD[].CLK = MAIN_CLK; + VDL_LWD[] = FB_AD[31..16]; + VDL_LWD[15..8].ENA = VDL_LWD_CS & !nFB_WR & FB_B0; + VDL_LWD[7..0].ENA = VDL_LWD_CS & !nFB_WR & FB_B1; +-- HORIZONTAL +-- VDL_HHT + VDL_HHT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C141"; -- $8282/2 + VDL_HHT[].CLK = MAIN_CLK; + VDL_HHT[] = FB_AD[27..16]; + VDL_HHT[11..8].ENA = VDL_HHT_CS & !nFB_WR & FB_B2; + VDL_HHT[7..0].ENA = VDL_HHT_CS & !nFB_WR & FB_B3; +-- VDL_HBE + VDL_HBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C143"; -- $8286/2 + VDL_HBE[].CLK = MAIN_CLK; + VDL_HBE[] = FB_AD[27..16]; + VDL_HBE[11..8].ENA = VDL_HBE_CS & !nFB_WR & FB_B2; + VDL_HBE[7..0].ENA = VDL_HBE_CS & !nFB_WR & FB_B3; +-- VDL_HDB + VDL_HDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C144"; -- $8288/2 + VDL_HDB[].CLK = MAIN_CLK; + VDL_HDB[] = FB_AD[27..16]; + VDL_HDB[11..8].ENA = VDL_HDB_CS & !nFB_WR & FB_B0; + VDL_HDB[7..0].ENA = VDL_HDB_CS & !nFB_WR & FB_B1; +-- VDL_HDE + VDL_HDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C145"; -- $828A/2 + VDL_HDE[].CLK = MAIN_CLK; + VDL_HDE[] = FB_AD[27..16]; + VDL_HDE[11..8].ENA = VDL_HDE_CS & !nFB_WR & FB_B2; + VDL_HDE[7..0].ENA = VDL_HDE_CS & !nFB_WR & FB_B3; +-- VDL_HBB + VDL_HBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C142"; -- $8284/2 + VDL_HBB[].CLK = MAIN_CLK; + VDL_HBB[] = FB_AD[27..16]; + VDL_HBB[11..8].ENA = VDL_HBB_CS & !nFB_WR & FB_B0; + VDL_HBB[7..0].ENA = VDL_HBB_CS & !nFB_WR & FB_B1; +-- VDL_HSS + VDL_HSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C146"; -- $828C/2 + VDL_HSS[].CLK = MAIN_CLK; + VDL_HSS[] = FB_AD[27..16]; + VDL_HSS[11..8].ENA = VDL_HSS_CS & !nFB_WR & FB_B0; + VDL_HSS[7..0].ENA = VDL_HSS_CS & !nFB_WR & FB_B1; +-- VERTIKAL +-- VDL_VBE + VDL_VBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C153"; -- $82A6/2 + VDL_VBE[].CLK = MAIN_CLK; + VDL_VBE[] = FB_AD[26..16]; + VDL_VBE[10..8].ENA = VDL_VBE_CS & !nFB_WR & FB_B2; + VDL_VBE[7..0].ENA = VDL_VBE_CS & !nFB_WR & FB_B3; +-- VDL_VDB + VDL_VDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C154"; -- $82A8/2 + VDL_VDB[].CLK = MAIN_CLK; + VDL_VDB[] = FB_AD[26..16]; + VDL_VDB[10..8].ENA = VDL_VDB_CS & !nFB_WR & FB_B0; + VDL_VDB[7..0].ENA = VDL_VDB_CS & !nFB_WR & FB_B1; +-- VDL_VDE + VDL_VDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C155"; -- $82AA/2 + VDL_VDE[].CLK = MAIN_CLK; + VDL_VDE[] = FB_AD[26..16]; + VDL_VDE[10..8].ENA = VDL_VDE_CS & !nFB_WR & FB_B2; + VDL_VDE[7..0].ENA = VDL_VDE_CS & !nFB_WR & FB_B3; +-- VDL_VBB + VDL_VBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C152"; -- $82A4/2 + VDL_VBB[].CLK = MAIN_CLK; + VDL_VBB[] = FB_AD[26..16]; + VDL_VBB[10..8].ENA = VDL_VBB_CS & !nFB_WR & FB_B0; + VDL_VBB[7..0].ENA = VDL_VBB_CS & !nFB_WR & FB_B1; +-- VDL_VSS + VDL_VSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C156"; -- $82AC/2 + VDL_VSS[].CLK = MAIN_CLK; + VDL_VSS[] = FB_AD[26..16]; + VDL_VSS[10..8].ENA = VDL_VSS_CS & !nFB_WR & FB_B0; + VDL_VSS[7..0].ENA = VDL_VSS_CS & !nFB_WR & FB_B1; +-- VDL_VFT + VDL_VFT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C151"; -- $82A2/2 + VDL_VFT[].CLK = MAIN_CLK; + VDL_VFT[] = FB_AD[26..16]; + VDL_VFT[10..8].ENA = VDL_VFT_CS & !nFB_WR & FB_B2; + VDL_VFT[7..0].ENA = VDL_VFT_CS & !nFB_WR & FB_B3; +-- VDL_VCT + VDL_VCT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C160"; -- $82C0/2 + VDL_VCT[].CLK = MAIN_CLK; + VDL_VCT[] = FB_AD[24..16]; + VDL_VCT[8].ENA = VDL_VCT_CS & !nFB_WR & FB_B0; + VDL_VCT[7..0].ENA = VDL_VCT_CS & !nFB_WR & FB_B1; +-- VDL_VMD + VDL_VMD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C161"; -- $82C2/2 + VDL_VMD[].CLK = MAIN_CLK; + VDL_VMD[] = FB_AD[19..16]; + VDL_VMD[3..0].ENA = VDL_VMD_CS & !nFB_WR & FB_B3; +--- REGISTER OUT + FB_AD[31..16] = lpm_bustri_WORD( + ST_SHIFT_MODE_CS & (0,ST_SHIFT_MODE[],B"00000000") + # FALCON_SHIFT_MODE_CS & (0,FALCON_SHIFT_MODE[]) + # SYS_CTR_CS & (B"100000000",SYS_CTR[6..4],BLITTER_RUN,SYS_CTR[2..0]) + # VDL_LOF_CS & VDL_LOF[] + # VDL_LWD_CS & VDL_LWD[] + # VDL_HBE_CS & (0,VDL_HBE[]) + # VDL_HDB_CS & (0,VDL_HDB[]) + # VDL_HDE_CS & (0,VDL_HDE[]) + # VDL_HBB_CS & (0,VDL_HBB[]) + # VDL_HSS_CS & (0,VDL_HSS[]) + # VDL_HHT_CS & (0,VDL_HHT[]) + # VDL_VBE_CS & (0,VDL_VBE[]) + # VDL_VDB_CS & (0,VDL_VDB[]) + # VDL_VDE_CS & (0,VDL_VDE[]) + # VDL_VBB_CS & (0,VDL_VBB[]) + # VDL_VSS_CS & (0,VDL_VSS[]) + # VDL_VFT_CS & (0,VDL_VFT[]) + # VDL_VCT_CS & (0,VDL_VCT[]) + # VDL_VMD_CS & (0,VDL_VMD[]) + # ACP_VCTR_CS & ACP_VCTR[31..16] + # ATARI_HH_CS & ATARI_HH[31..16] + # ATARI_VH_CS & ATARI_VH[31..16] + # ATARI_HL_CS & ATARI_HL[31..16] + # ATARI_VL_CS & ATARI_VL[31..16] + # CCR_CS & (0,CCR[23..16]) + # VIDEO_PLL_CONFIG_CS & (0,VR_DOUT[]) + # VIDEO_PLL_RECONFIG_CS & (VR_BUSY,B"0000",VR_WR,VR_RD,VIDEO_RECONFIG,H"FA") + ,(ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # CCR_CS # SYS_CTR_CS # VDL_LOF_CS # VDL_LWD_CS + # VDL_HBE_CS # VDL_HDB_CS # VDL_HDE_CS # VDL_HBB_CS # VDL_HSS_CS # VDL_HHT_CS + # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS # VIDEO_PLL_CONFIG_CS # VIDEO_PLL_RECONFIG_CS + # VDL_VBE_CS # VDL_VDB_CS # VDL_VDE_CS # VDL_VBB_CS # VDL_VSS_CS # VDL_VFT_CS # VDL_VCT_CS # VDL_VMD_CS) & !nFB_OE); + + FB_AD[15..0] = lpm_bustri_WORD( + ACP_VCTR_CS & ACP_VCTR[15..0] + # ATARI_HH_CS & ATARI_HH[15..0] + # ATARI_VH_CS & ATARI_VH[15..0] + # ATARI_HL_CS & ATARI_HL[15..0] + # ATARI_VL_CS & ATARI_VL[15..0] + # CCR_CS & CCR[15..0] + ,(ACP_VCTR_CS # CCR_CS # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS ) & !nFB_OE); + + VIDEO_MOD_TA = CLUT_TA # ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # SYS_CTR_CS # VDL_LOF_CS # VDL_LWD_CS + # VDL_HBE_CS # VDL_HDB_CS # VDL_HDE_CS # VDL_HBB_CS # VDL_HSS_CS # VDL_HHT_CS + # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS + # VDL_VBE_CS # VDL_VDB_CS # VDL_VDE_CS # VDL_VBB_CS # VDL_VSS_CS # VDL_VFT_CS # VDL_VCT_CS # VDL_VMD_CS; + +-- VIDEO AUSGABE SETZEN + CLK17M.CLK = CLK33M; + CLK17M = !CLK17M; + CLK13M.CLK = CLK25M; + CLK13M = !CLK13M; + PIXEL_CLK = CLK13M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & VDL_VCT2 # VDL_VCT0) + # CLK17M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & !VDL_VCT2 # VDL_VCT0) + # CLK25M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VMD2 & VDL_VCT2 & !VDL_VCT0 + # CLK33M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VMD2 & !VDL_VCT2 & !VDL_VCT0 + # CLK25M & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00" + # CLK33M & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01" + # CLK_VIDEO & ACP_VIDEO_ON & ACP_VCTR[9]; +-------------------------------------------------------------- +-- HORIZONTALE SYNC LÄNGE in PIXEL_CLK +---------------------------------------------------------------- + HSY_LEN[].CLK = MAIN_CLK; + HSY_LEN[] = 14 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & VDL_VCT2 # VDL_VCT0) + # 16 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & !VDL_VCT2 # VDL_VCT0) + # 28 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VMD2 & VDL_VCT2 & !VDL_VCT0 + # 32 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VMD2 & !VDL_VCT2 & !VDL_VCT0 + # 28 & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00" + # 32 & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01" + # 16 + (0,VR_FRQ[7..1]) & ACP_VIDEO_ON & ACP_VCTR[9]; -- hsync puls length in pixeln=frequenz/ = 500ns + + MULF[] = 2 & !ST_VIDEO & VDL_VMD2 -- MULTIPLIKATIONS FAKTOR + # 4 & !ST_VIDEO & !VDL_VMD2 + # 16 & ST_VIDEO & VDL_VMD2 + # 32 & ST_VIDEO & !VDL_VMD2; + + + HDIS_LEN[] = 320 & VDL_VMD2 -- BREITE IN PIXELN + # 640 & !VDL_VMD2; + +-- DOPPELZEILENMODUS + DOP_ZEI.CLK = MAIN_CLK; + DOP_ZEI = VDL_VMD0 & ST_VIDEO; -- ZEILENVERDOPPELUNG EIN AUS + INTER_ZEI.CLK = PIXEL_CLK; + INTER_ZEI = DOP_ZEI & VVCNT0!=VDIS_START0 & VVCNT[]!=0 & VHCNT[]<(HDIS_END[]-1) -- EINSCHIEBEZEILE AUF "DOPPEL" ZEILEN UND ZEILE NULL WEGEN SYNC + # DOP_ZEI & VVCNT0==VDIS_START0 & VVCNT[]!=0 & VHCNT[]>(HDIS_END[]-2); -- EINSCHIEBEZEILE AUF "NORMAL" ZEILEN UND ZEILE NULL WEGEN SYNC + DOP_FIFO_CLR.CLK = PIXEL_CLK; + DOP_FIFO_CLR = INTER_ZEI & HSYNC_START # SYNC_PIX; -- DOPPELZEILENFIFO LÖSCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START + + RAND_LINKS[] = VDL_HBE[] & ACP_VIDEO_ON + # 21 & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2 + # 42 & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2 + # VDL_HBE[] * (0,MULF[5..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; -- + HDIS_START[] = VDL_HDB[] & ACP_VIDEO_ON + # RAND_LINKS[]+1 & !ACP_VIDEO_ON; -- + HDIS_END[] = VDL_HDE[] & ACP_VIDEO_ON + # RAND_LINKS[]+HDIS_LEN[] & !ACP_VIDEO_ON; -- + RAND_RECHTS[] = VDL_HBB[] & ACP_VIDEO_ON + # HDIS_END[]+1 & !ACP_VIDEO_ON; -- + HS_START[] = VDL_HSS[] & ACP_VIDEO_ON + # ATARI_HL[11..0] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2 + # ATARI_HH[11..0] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2 + # (VDL_HHT[]+1+VDL_HSS[]) * (0,MULF[5..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; -- + H_TOTAL[] = VDL_HHT[] & ACP_VIDEO_ON + # ATARI_HL[27..16] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2 + # ATARI_HH[27..16] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2 + # (VDL_HHT[]+2) * (0,MULF[]) & !ACP_VIDEO_ON & !ATARI_SYNC; -- + + RAND_OBEN[] = VDL_VBE[] & ACP_VIDEO_ON + # 31 & !ACP_VIDEO_ON & ATARI_SYNC + # (0,VDL_VBE[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; + VDIS_START[] = VDL_VDB[] & ACP_VIDEO_ON + # 32 & !ACP_VIDEO_ON & ATARI_SYNC + # (0,VDL_VDB[10..1])+1 & !ACP_VIDEO_ON & !ATARI_SYNC; + VDIS_END[] = VDL_VDE[] & ACP_VIDEO_ON + # 431 & !ACP_VIDEO_ON & ATARI_SYNC & ST_VIDEO + # 511 & !ACP_VIDEO_ON & ATARI_SYNC & !ST_VIDEO + # (0,VDL_VDE[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; + RAND_UNTEN[] = VDL_VBB[] & ACP_VIDEO_ON + # VDIS_END[]+1 & !ACP_VIDEO_ON & ATARI_SYNC + # (0,VDL_VBB[10..1])+1 & !ACP_VIDEO_ON & !ATARI_SYNC; + VS_START[] = VDL_VSS[] & ACP_VIDEO_ON + # ATARI_VL[10..0] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2 + # ATARI_VH[10..0] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2 + # (0,VDL_VSS[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; + V_TOTAL[] = VDL_VFT[] & ACP_VIDEO_ON + # ATARI_VL[26..16] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2 + # ATARI_VH[26..16] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2 + # (0,VDL_VFT[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; +-- ZÄHLER + LAST.CLK = PIXEL_CLK; + LAST = VHCNT[]==(H_TOTAL[]-2); + VHCNT[].CLK = PIXEL_CLK; + VHCNT[] = (VHCNT[] + 1) & !LAST; + VVCNT[].CLK = PIXEL_CLK; + VVCNT[].ENA = LAST; + VVCNT[] = (VVCNT[] + 1) & (VVCNT[]!=V_TOTAL[]-1); +-- DISPLAY ON OFF + DPO_ZL.CLK = PIXEL_CLK; + DPO_ZL = (VVCNT[]>RAND_OBEN[]-1) & (VVCNT[]=(VDIS_START[]-1)) & (VVCNT[] + +Sample Waveforms for altdpram0.vhd + + +

Sample behavioral waveforms for design file altdpram0.vhd

+

The following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design altdpram0.vhd. For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( 7, 6, 5, 4, ...). The design altdpram0.vhd has two read/write ports. Read/write port A has 16 words of 3 bits each and Read/write port B has 16 words of 3 bits each. The output of the read/write port A is registered by clock_a. The output of the read/write port B is registered by clock_b.

+
+

Fig. 1 : Wave showing read operation.

+

The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until after the first rising edge of the read clock. The clock enable on the read side input registers are disabled. The clock enable on the output registers are disabled.

+
+

Fig. 2 : Waveform showing write operation

+

The above waveform shows the behavior of the design under normal write conditions. The write cycle is assumed to be from the rising edge of the enabled clock in which wren is high till the rising edge of the next clock cycle. In BIDIR_DUAL_PORT mode, when the write happens at the same address as the one being read in the other port, the read output is unknown. Actual write into the RAM happens at the rising edge of the write clock. The clock enable on the write side input registers are disabled. The clock enable on the output registers are disabled. For the A port, When a write happens, the output of the port is the old data at the address. For the B port, When a write happens, the output of the port is the old data at the address.

+

+ + diff --git a/FPGA_by_Fredi/Video/altdpram1_wave0.jpg b/FPGA_by_Fredi/Video/altdpram1_wave0.jpg new file mode 100644 index 0000000..3ab5c5f Binary files /dev/null and b/FPGA_by_Fredi/Video/altdpram1_wave0.jpg differ diff --git a/FPGA_by_Fredi/Video/altdpram1_wave1.jpg b/FPGA_by_Fredi/Video/altdpram1_wave1.jpg new file mode 100644 index 0000000..f2f606b Binary files /dev/null and b/FPGA_by_Fredi/Video/altdpram1_wave1.jpg differ diff --git a/FPGA_by_Fredi/Video/altdpram1_waveforms.html b/FPGA_by_Fredi/Video/altdpram1_waveforms.html new file mode 100644 index 0000000..85b4369 --- /dev/null +++ b/FPGA_by_Fredi/Video/altdpram1_waveforms.html @@ -0,0 +1,16 @@ + + +Sample Waveforms for altdpram1.vhd + + +

Sample behavioral waveforms for design file altdpram1.vhd

+

The following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design altdpram1.vhd. For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( 0F, 0E, 0D, 0C, ...). The design altdpram1.vhd has two read/write ports. Read/write port A has 256 words of 6 bits each and Read/write port B has 256 words of 6 bits each. The output of the read/write port A is registered by clock_a. The output of the read/write port B is registered by clock_b.

+
+

Fig. 1 : Wave showing read operation.

+

The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until after the first rising edge of the read clock. The clock enable on the read side input registers are disabled. The clock enable on the output registers are disabled.

+
+

Fig. 2 : Waveform showing write operation

+

The above waveform shows the behavior of the design under normal write conditions. The write cycle is assumed to be from the rising edge of the enabled clock in which wren is high till the rising edge of the next clock cycle. In BIDIR_DUAL_PORT mode, when the write happens at the same address as the one being read in the other port, the read output is unknown. Actual write into the RAM happens at the rising edge of the write clock. The clock enable on the write side input registers are disabled. The clock enable on the output registers are disabled. For the A port, When a write happens, the output of the port is the old data at the address. For the B port, When a write happens, the output of the port is the old data at the address.

+

+ + diff --git a/FPGA_by_Fredi/Video/altdpram2_wave0.jpg b/FPGA_by_Fredi/Video/altdpram2_wave0.jpg new file mode 100644 index 0000000..2da3c66 Binary files /dev/null and b/FPGA_by_Fredi/Video/altdpram2_wave0.jpg differ diff --git a/FPGA_by_Fredi/Video/altdpram2_wave1.jpg b/FPGA_by_Fredi/Video/altdpram2_wave1.jpg new file mode 100644 index 0000000..829d237 Binary files /dev/null and b/FPGA_by_Fredi/Video/altdpram2_wave1.jpg differ diff --git a/FPGA_by_Fredi/Video/altdpram2_waveforms.html b/FPGA_by_Fredi/Video/altdpram2_waveforms.html new file mode 100644 index 0000000..a856bf6 --- /dev/null +++ b/FPGA_by_Fredi/Video/altdpram2_waveforms.html @@ -0,0 +1,16 @@ + + +Sample Waveforms for altdpram2.vhd + + +

Sample behavioral waveforms for design file altdpram2.vhd

+

The following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design altdpram2.vhd. For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( F0, F1, F2, F3, ...). The design altdpram2.vhd has two read/write ports. Read/write port A has 256 words of 8 bits each and Read/write port B has 256 words of 8 bits each. The output of the read/write port A is registered by clock_a. The output of the read/write port B is registered by clock_b.

+
+

Fig. 1 : Wave showing read operation.

+

The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until after the first rising edge of the read clock. The clock enable on the read side input registers are disabled. The clock enable on the output registers are disabled.

+
+

Fig. 2 : Waveform showing write operation

+

The above waveform shows the behavior of the design under normal write conditions. The write cycle is assumed to be from the rising edge of the enabled clock in which wren is high till the rising edge of the next clock cycle. In BIDIR_DUAL_PORT mode, when the write happens at the same address as the one being read in the other port, the read output is unknown. Actual write into the RAM happens at the rising edge of the write clock. The clock enable on the write side input registers are disabled. The clock enable on the output registers are disabled. For the A port, When a write happens, the output of the port is the old data at the address. For the B port, When a write happens, the output of the port is the old data at the address.

+

+ + diff --git a/FPGA_by_Fredi/Video/lpm_compare1_wave0.jpg b/FPGA_by_Fredi/Video/lpm_compare1_wave0.jpg new file mode 100644 index 0000000..0fbc252 Binary files /dev/null and b/FPGA_by_Fredi/Video/lpm_compare1_wave0.jpg differ diff --git a/FPGA_by_Fredi/Video/lpm_compare1_waveforms.html b/FPGA_by_Fredi/Video/lpm_compare1_waveforms.html new file mode 100644 index 0000000..e8242d9 --- /dev/null +++ b/FPGA_by_Fredi/Video/lpm_compare1_waveforms.html @@ -0,0 +1,13 @@ + + +Sample Waveforms for lpm_compare1.vhd + + +

Sample behavioral waveforms for design file lpm_compare1.vhd

+

The following waveforms show the behavior of lpm_comparator megafunction for the chosen set of parameters in design lpm_compare1.vhd. The design lpm_compare1.vhd is 11 bit UNSIGNED comparator.

+
+

Fig. 1 : Wave showing comparator operation.

+

+

+ + diff --git a/FPGA_by_Fredi/Video/lpm_fifoDZ_wave0.jpg b/FPGA_by_Fredi/Video/lpm_fifoDZ_wave0.jpg new file mode 100644 index 0000000..6bb604e Binary files /dev/null and b/FPGA_by_Fredi/Video/lpm_fifoDZ_wave0.jpg differ diff --git a/FPGA_by_Fredi/Video/lpm_fifoDZ_waveforms.html b/FPGA_by_Fredi/Video/lpm_fifoDZ_waveforms.html new file mode 100644 index 0000000..956161a --- /dev/null +++ b/FPGA_by_Fredi/Video/lpm_fifoDZ_waveforms.html @@ -0,0 +1,13 @@ + + +Sample Waveforms for "lpm_fifoDZ.vhd" + + +

Sample behavioral waveforms for design file "lpm_fifoDZ.vhd"

+

The following waveforms show the behavior of scfifo megafunction for the chosen set of parameters in design "lpm_fifoDZ.vhd". The design "lpm_fifoDZ.vhd" has a depth of 512 words of 128 bits each. The fifo is in show-ahead synchronous mode. The data becomes available before 'rdreq' is asserted; 'rdreq' acts as a read acknowledge.

+
+

Fig. 1 : Wave showing read and write operation.

+

The above waveform shows the behavior of the design under normal read and write conditions with aclr .

+

+ + diff --git a/FPGA_by_Fredi/Video/lpm_fifo_dc0_wave0.jpg b/FPGA_by_Fredi/Video/lpm_fifo_dc0_wave0.jpg new file mode 100644 index 0000000..c26a8bd Binary files /dev/null and b/FPGA_by_Fredi/Video/lpm_fifo_dc0_wave0.jpg differ diff --git a/FPGA_by_Fredi/Video/lpm_fifo_dc0_waveforms.html b/FPGA_by_Fredi/Video/lpm_fifo_dc0_waveforms.html new file mode 100644 index 0000000..20c4da2 --- /dev/null +++ b/FPGA_by_Fredi/Video/lpm_fifo_dc0_waveforms.html @@ -0,0 +1,13 @@ + + +Sample Waveforms for "lpm_fifo_dc0.vhd" + + +

Sample behavioral waveforms for design file "lpm_fifo_dc0.vhd"

+

The following waveforms show the behavior of dcfifo megafunction for the chosen set of parameters in design "lpm_fifo_dc0.vhd". The design "lpm_fifo_dc0.vhd" has a depth of 2048 words of 128 bits each. The fifo is in legacy synchronous mode. The data becomes available after 'rdreq' is asserted; 'rdreq' acts as a read request.

+
+

Fig. 1 : Wave showing read and write operation.

+

The above waveform shows the behavior of the design under normal read and write conditions with aclr .

+

+ + diff --git a/FPGA_by_Fredi/altpll0_waveforms.html b/FPGA_by_Fredi/altpll0_waveforms.html deleted file mode 100644 index 80e236a..0000000 --- a/FPGA_by_Fredi/altpll0_waveforms.html +++ /dev/null @@ -1,10 +0,0 @@ - - -Sample Waveforms for "altpll0.vhd" - - -

Sample behavioral waveforms for design file "altpll0.vhd"

-

-

- - diff --git a/FPGA_by_Fredi/altpll1_waveforms.html b/FPGA_by_Fredi/altpll1_waveforms.html deleted file mode 100644 index 1382a12..0000000 --- a/FPGA_by_Fredi/altpll1_waveforms.html +++ /dev/null @@ -1,10 +0,0 @@ - - -Sample Waveforms for "altpll1.vhd" - - -

Sample behavioral waveforms for design file "altpll1.vhd"

-

-

- - diff --git a/FPGA_by_Fredi/altpll2_waveforms.html b/FPGA_by_Fredi/altpll2_waveforms.html deleted file mode 100644 index 1932527..0000000 --- a/FPGA_by_Fredi/altpll2_waveforms.html +++ /dev/null @@ -1,10 +0,0 @@ - - -Sample Waveforms for "altpll2.vhd" - - -

Sample behavioral waveforms for design file "altpll2.vhd"

-

-

- - diff --git a/FPGA_by_Fredi/altpll3_waveforms.html b/FPGA_by_Fredi/altpll3_waveforms.html deleted file mode 100644 index 3f6367c..0000000 --- a/FPGA_by_Fredi/altpll3_waveforms.html +++ /dev/null @@ -1,10 +0,0 @@ - - -Sample Waveforms for "altpll3.vhd" - - -

Sample behavioral waveforms for design file "altpll3.vhd"

-

-

- - diff --git a/FPGA_by_Fredi/blitter.tdf b/FPGA_by_Fredi/blitter.tdf index c92f2a8..740423e 100644 --- a/FPGA_by_Fredi/blitter.tdf +++ b/FPGA_by_Fredi/blitter.tdf @@ -70,8 +70,11 @@ SUBDESIGN BLITTER ) VARIABLE - FB_B[3..0] :NODE; + BYT :NODE; + LONGLINE :NODE; + W_ADR[18..0] :NODE; FB_16B[1..0] :NODE; + W_A1 :DFFE; BLITTER_CS :NODE; BL_HRAM_CS :NODE; BL_HRAM_BE[1..0] :NODE; @@ -160,30 +163,27 @@ VARIABLE ENDMASK23_IN[143..0] :NODE; ENDMASK23_OUT[143..0] :NODE; ENDMASK123[127..0] :NODE; - DDR_RAM_FREE :NODE; + ENDMASKEND[15..0] :NODE; SRC_DDR_ADR[31..0] :NODE; DST_DDR_ADR[31..0] :NODE; + BLITTER_REQ :DFF; -- MAIN STATE MACHINE - BL_SM :MACHINE WITH STATES(START,NEW_LINE,NEW_LINEW,RDSRC1,RDSRC2,RDDST,WRDST,TESTZEILENENDE,TESTFERTIG,FERTIG); + BL_SM :MACHINE WITH STATES(START,NEW_LINE,NEW_LINEW,RDSRC0,RDSRC1,RDSRC2,RDDST,WRDSTW1,WRDST,TESTZEILENENDE,TESTFERTIG,FERTIG); BEGIN --- BYT SELECT 32 BIT - FB_B0 = FB_ADR[1..0]==0; -- ADR==0 - FB_B1 = FB_ADR[1..0]==1 -- ADR==1 - # FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HIGH WORD - # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE - FB_B2 = FB_ADR[1..0]==2 -- ADR==2 - # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE - FB_B3 = FB_ADR[1..0]==3 -- ADR==3 - # FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LOW WORD - # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE --- BYT SELECT 16 BIT - FB_16B0 = FB_ADR[0]==0; -- ADR==0 - FB_16B1 = FB_ADR[0]==1 -- wenn ADR==1 - # !(!FB_SIZE1 & FB_SIZE0); -- or NOT BYT +-- BYT UND WORD SELECT 16 BIT + BYT = !FB_SIZE1 & FB_SIZE0; + LONGLINE = !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0; -- LONG OR LINE + W_A1.CLK = MAIN_CLK; + W_A1.ENA = FB_ALE # BLITTER_TA & LONGLINE; + W_A1 = FB_ADR[1] & FB_ALE # BLITTER_TA & LONGLINE; -- A1 HOCHZÄHLEN BEI LONG UND LINE WEGEN BURST + W_ADR[18..1] = FB_ADR[19..2]; + W_ADR0 = W_A1; + FB_16B0 = FB_ADR[0]==0; -- wenn ADR==0 + FB_16B1 = FB_ADR[0]==1 # !BYT; -- wenn ADR==1 or NOT BYT -- BLITTER CS - BLITTER_CS = !nFB_CS1 & FB_ADR[19..7]==H"1F14"; -- FFFF8A00-7F + BLITTER_CS = !nFB_CS1 & FB_ADR[19..7]==H"1F14"; -- FFFF8A00-7F BLITTER_TA = BLITTER_CS; -- REGISTER -- HALFTON RAM @@ -192,114 +192,114 @@ BEGIN BL_HRAM_BE0 = BL_HRAM_CS & FB_16B1; WREN_B = B"0"; LINE_NR[] = ((Y_INDEX[3..0] & !BL_DST_Y_INC15) # (!Y_INDEX[3..0] & BL_DST_Y_INC15)); - (BL_DPRAM_OUT[],BL_HRAM_OUT[]) = altsyncram0(FB_ADR[4..1],LINE_NR[],BL_HRAM_BE[],MAIN_CLK,DDRCLK0,FB_AD[31..16],FB_AD[31..16],BL_HRAM_CS & !nFB_WR,WREN_B); + (BL_DPRAM_OUT[],BL_HRAM_OUT[]) = altsyncram0(W_ADR[3..0],LINE_NR[],BL_HRAM_BE[],MAIN_CLK,DDRCLK0,FB_AD[31..16],FB_AD[31..16],BL_HRAM_CS & !nFB_WR,WREN_B); -- SRC X INC BL_SRC_X_INC[].CLK = MAIN_CLK; BL_SRC_X_INC[] = FB_AD[31..16]; - BL_SRC_X_INC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C510"; -- $F8A20.w + BL_SRC_X_INC_CS = !nFB_CS1 & W_ADR[]==H"7C510"; -- $F8A20.w BL_SRC_X_INC[15..8].ENA = BL_SRC_X_INC_CS & !nFB_WR & FB_16B0; BL_SRC_X_INC[7..0].ENA = BL_SRC_X_INC_CS & !nFB_WR & FB_16B1; SRC_XINC_NODE[] = (H"FFFF0000" & BL_SRC_X_INC15) # (H"0000",BL_SRC_X_INC[]); -- ERWEITERN AUF 32 BIT -- SRC Y INC BL_SRC_Y_INC[].CLK = MAIN_CLK; BL_SRC_Y_INC[] = FB_AD[31..16]; - BL_SRC_Y_INC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C511"; -- $F8A22.w + BL_SRC_Y_INC_CS = !nFB_CS1 & W_ADR[]==H"7C511"; -- $F8A22.w BL_SRC_Y_INC[15..8].ENA = BL_SRC_Y_INC_CS & !nFB_WR & FB_16B0; BL_SRC_Y_INC[7..0].ENA = BL_SRC_Y_INC_CS & !nFB_WR & FB_16B1; SRC_YINC_NODE[] = (H"FFFF0000" & BL_SRC_Y_INC15) # (H"0000",BL_SRC_Y_INC[]); -- ERWEITERN AUF 32 BIT -- SRC ADR HIGH BL_SRC_ADR[].CLK = MAIN_CLK; BL_SRC_ADR[31..16] = FB_AD[31..16]; - BL_SRC_ADRH_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C512"; -- $F8A24.w + BL_SRC_ADRH_CS = !nFB_CS1 & W_ADR[]==H"7C512"; -- $F8A24.w BL_SRC_ADR[31..24].ENA = BL_SRC_ADRH_CS & !nFB_WR & FB_16B0; BL_SRC_ADR[23..16].ENA = BL_SRC_ADRH_CS & !nFB_WR & FB_16B1; -- SRC ADR LOW BL_SRC_ADR[].CLK = MAIN_CLK; BL_SRC_ADR[15..0] = FB_AD[31..16]; - BL_SRC_ADRL_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C513"; -- $F8A26.w + BL_SRC_ADRL_CS = !nFB_CS1 & W_ADR[]==H"7C513"; -- $F8A26.w BL_SRC_ADR[15..8].ENA = BL_SRC_ADRL_CS & !nFB_WR & FB_16B0; BL_SRC_ADR[7..0].ENA = BL_SRC_ADRL_CS & !nFB_WR & FB_16B1; SRC_IADR[].CLK = DDRCLK0; - SRC_IADRH_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C520"; -- $F8A40.w - SRC_IADRL_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C521"; -- $F8A42.w - SRC_IADR_CLR = (BL_SRC_ADRL_CS # BL_SRC_ADRH_CS) & !nFB_WR; -- LÖSCHEN BEI WRITE + SRC_IADRH_CS = !nFB_CS1 & W_ADR[]==H"7C520"; -- $F8A40.w + SRC_IADRL_CS = !nFB_CS1 & W_ADR[]==H"7C521"; -- $F8A42.w + SRC_IADR_CLR = (BL_SRC_ADRL_CS # BL_SRC_ADRH_CS) & !nFB_WR; -- LÖSCHEN BEI WRITE SRC_IADR[] = (SRC_IADR[] + (((8 * SRC_XINC_NODE[]) & SIINC) + (SRC_YINC_NODE[] & ZYINC) + ((((0,BL_X_CNT[]) - (0,X_INDEX[]) - 8) * SRC_XINC_NODE[]) & ZIINC)) & SRC_READ) & !SRC_IADR_CLR; SRC_ADR_NODE[] = BL_SRC_ADR[] + SRC_IADR[]; -- ZUGRIFFSADRESSE THEORETISCH -- ENDMASK 1 BL_ENDMASK1[].CLK = MAIN_CLK; BL_ENDMASK1[] = FB_AD[31..16]; - BL_ENDMASK1_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C514"; -- $F8A28.w + BL_ENDMASK1_CS = !nFB_CS1 & W_ADR[]==H"7C514"; -- $F8A28.w BL_ENDMASK1[15..8].ENA = BL_ENDMASK1_CS & !nFB_WR & FB_16B0; BL_ENDMASK1[7..0].ENA = BL_ENDMASK1_CS & !nFB_WR & FB_16B1; -- ENDMASK 2 BL_ENDMASK2[].CLK = MAIN_CLK; BL_ENDMASK2[] = FB_AD[31..16]; - BL_ENDMASK2_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C515"; -- $F8A2A.w + BL_ENDMASK2_CS = !nFB_CS1 & W_ADR[]==H"7C515"; -- $F8A2A.w BL_ENDMASK2[15..8].ENA = BL_ENDMASK2_CS & !nFB_WR & FB_16B0; BL_ENDMASK2[7..0].ENA = BL_ENDMASK2_CS & !nFB_WR & FB_16B1; -- ENDMASK 3 BL_ENDMASK3[].CLK = MAIN_CLK; BL_ENDMASK3[] = FB_AD[31..16]; - BL_ENDMASK3_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C516"; -- $F8A2C.w + BL_ENDMASK3_CS = !nFB_CS1 & W_ADR[]==H"7C516"; -- $F8A2C.w BL_ENDMASK3[15..8].ENA = BL_ENDMASK3_CS & !nFB_WR & FB_16B0; BL_ENDMASK3[7..0].ENA = BL_ENDMASK3_CS & !nFB_WR & FB_16B1; -- DST X INC BL_DST_X_INC[].CLK = MAIN_CLK; BL_DST_X_INC[] = FB_AD[31..16]; - BL_DST_X_INC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C517"; -- $F8A2E.w + BL_DST_X_INC_CS = !nFB_CS1 & W_ADR[]==H"7C517"; -- $F8A2E.w BL_DST_X_INC[15..8].ENA = BL_DST_X_INC_CS & !nFB_WR & FB_16B0; BL_DST_X_INC[7..0].ENA = BL_DST_X_INC_CS & !nFB_WR & FB_16B1; DST_XINC_NODE[] = (H"FFFF0000" & BL_DST_X_INC15) # (H"0000",BL_DST_X_INC[]); -- ERWEITERN AUF 32 BIT -- DST Y INC BL_DST_Y_INC[].CLK = MAIN_CLK; BL_DST_Y_INC[] = FB_AD[31..16]; - BL_DST_Y_INC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C518"; -- $F8A30.w + BL_DST_Y_INC_CS = !nFB_CS1 & W_ADR[]==H"7C518"; -- $F8A30.w BL_DST_Y_INC[15..8].ENA = BL_DST_Y_INC_CS & !nFB_WR & FB_16B0; BL_DST_Y_INC[7..0].ENA = BL_DST_Y_INC_CS & !nFB_WR & FB_16B1; DST_YINC_NODE[] = (H"FFFF0000" & BL_DST_Y_INC15) # (H"0000",BL_DST_Y_INC[]); -- ERWEITERN AUF 32 BIT -- DST ADR HIGH BL_DST_ADR[].CLK = MAIN_CLK; BL_DST_ADR[31..16] = FB_AD[31..16]; - BL_DST_ADRH_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C519"; -- $F8A32.w + BL_DST_ADRH_CS = !nFB_CS1 & W_ADR[]==H"7C519"; -- $F8A32.w BL_DST_ADR[31..24].ENA = BL_DST_ADRH_CS & !nFB_WR & FB_16B0; BL_DST_ADR[23..16].ENA = BL_DST_ADRH_CS & !nFB_WR & FB_16B1; -- DST ADR LOW BL_DST_ADR[].CLK = MAIN_CLK; BL_DST_ADR[15..0] = FB_AD[31..16]; - BL_DST_ADRL_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51A"; -- $F8A34.w + BL_DST_ADRL_CS = !nFB_CS1 & W_ADR[]==H"7C51A"; -- $F8A34.w BL_DST_ADR[15..8].ENA = BL_DST_ADRL_CS & !nFB_WR & FB_16B0; BL_DST_ADR[7..0].ENA = BL_DST_ADRL_CS & !nFB_WR & FB_16B1; DST_IADR[].CLK = DDRCLK0; - DST_IADRH_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C522"; -- $F8A44.w - DST_IADRL_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C523"; -- $F8A46.w + DST_IADRH_CS = !nFB_CS1 & W_ADR[]==H"7C522"; -- $F8A44.w + DST_IADRL_CS = !nFB_CS1 & W_ADR[]==H"7C523"; -- $F8A46.w DST_IADR_CLR = (BL_DST_ADRL_CS # BL_DST_ADRH_CS) & !nFB_WR; -- LÖSCHEN BEI WRITE DST_IADR[] = (DST_IADR[] + ((8 * DST_XINC_NODE[]) & DIINC) + (DST_YINC_NODE[] & ZYINC) + ((((0,BL_X_CNT[]) - (0,X_INDEX[])) * DST_XINC_NODE[]) & ZIINC)) & !DST_IADR_CLR; DST_ADR_NODE[] = BL_DST_ADR[] + DST_IADR[]; -- ZUGRIFFSADRESSE THEORETISCH -- X COUNT BL_X_CNT[].CLK = MAIN_CLK; BL_X_CNT[] = FB_AD[31..16]; - BL_X_CNT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51B"; -- $F8A36.w + BL_X_CNT_CS = !nFB_CS1 & W_ADR[]==H"7C51B"; -- $F8A36.w BL_X_CNT[15..8].ENA = BL_X_CNT_CS & !nFB_WR & FB_16B0; BL_X_CNT[7..0].ENA = BL_X_CNT_CS & !nFB_WR & FB_16B1; X_INDEX[].CLK = DDRCLK0; - X_INDEX_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C524"; -- $F8A48.w + X_INDEX_CS = !nFB_CS1 & W_ADR[]==H"7C524"; -- $F8A48.w X_INDEX_CLR = BL_X_CNT_CS & !nFB_WR; -- LÖSCHEN BEI WRITE X_INDEX[] = (X_INDEX[] + (8 & XIINC) + ((BL_X_CNT[] - X_INDEX[]) & ZIINC)) & !X_INDEX_CLR; X_CNT_NODE[] = X_INDEX[] - ((0,DST_ADR_NODE[3..1]) & (X_INDEX[]!=0));-- EFFEKTIV GELESENE -- Y COUNT BL_Y_CNT[].CLK = MAIN_CLK; BL_Y_CNT[] = FB_AD[31..16]; - BL_Y_CNT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51C"; -- $F8A38.w + BL_Y_CNT_CS = !nFB_CS1 & W_ADR[]==H"7C51C"; -- $F8A38.w BL_Y_CNT[15..8].ENA = BL_Y_CNT_CS & !nFB_WR & FB_16B0; BL_Y_CNT[7..0].ENA = BL_Y_CNT_CS & !nFB_WR & FB_16B1; Y_INDEX[].CLK = DDRCLK0; - Y_INDEX_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C525"; -- $F8A4A.w + Y_INDEX_CS = !nFB_CS1 & W_ADR[]==H"7C525"; -- $F8A4A.w Y_INDEX_CLR = BL_Y_CNT_CS & !nFB_WR; -- LÖSCHEN BEI WRITE Y_INDEX[] = (Y_INDEX[] + (1 & YIINC)) & !Y_INDEX_CLR; -- HOP LOGIC BL_HOP[].CLK = MAIN_CLK; BL_HOP[] = FB_AD[31..24]; - BL_HOP_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51D"; -- $F8A3A.w + BL_HOP_CS = !nFB_CS1 & W_ADR[]==H"7C51D"; -- $F8A3A.w BL_HOP[7..0].ENA = BL_HOP_CS & !nFB_WR & FB_16B0; -- $F8A3A -- OP LOGIC BL_OP[].CLK = MAIN_CLK; @@ -309,7 +309,7 @@ BEGIN BL_LN[].CLK = MAIN_CLK; BL_LN[6..0] = FB_AD[30..24]; BL_LN7 = FB_AD31 & !LN7CLR; -- BUSY HOG UND SMUDGE - BL_LN_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51E"; -- $F8A3C.w + BL_LN_CS = !nFB_CS1 & W_ADR[]==H"7C51E"; -- $F8A3C.w BL_LN[].ENA = BL_LN_CS & !nFB_WR & FB_16B0; -- $F8A3C BL_LN7.ENA = LN7CLR; -- SKEW BYT @@ -340,8 +340,8 @@ BEGIN # DST_IADRL_CS & DST_IADR[15..0] # X_INDEX_CS & X_INDEX[] # Y_INDEX_CS & Y_INDEX[] - ,BLITTER_CS & !nFB_OE); -- FFFF8A00-7F ------------------------------------------ + ,BLITTER_CS & !nFB_OE); -- FFFF8A00-7F +-------------------------------------------------------------------------------------- -- SRC BUFFER LADEN BL_SRC_BUF1[].CLK = DDRCLK0; BL_SRC_BUF1[127..64].ENA = BLITTER_DACK1 & BL_READ_SRC; @@ -400,7 +400,7 @@ BEGIN BL_BS_SKEW[] = DIST_RIGHT[7..0]; -- LPM SHIFT RIGHT SHIFT_DIR = VCC; -- DIR = RIGHT else - BL_BS_SKEW[] = !DIST_RIGHT[3..0] + 1; -- LPM SHIFT LEFT + BL_BS_SKEW[] = !DIST_RIGHT[7..0] + 1; -- LPM SHIFT LEFT SHIFT_DIR = GND; -- DIR = LEFT end if; -- barell shifter: direction 0=links 1=rechts IN BEZUG AUF ausgabewert! @@ -471,15 +471,16 @@ BEGIN END CASE; ------------ ENDMASKEN SETZEN ****************************************************************************** ENDMASK1_SHIFT[3..0] = 0; - ENDMASK2_SHIFT[3..0] = 0; + ENDMASK2_SHIFT[3..0] = 0; IF BL_DST_X_INC15 THEN ---------------------------- RÜCKWÄRTS X_INC NEGATIV IF X_INDEX[]==0 THEN -- ENDE? - ENDMASK2_SHIFT[7..4] = 1 + (0,(DST_ADR_NODE[3..1])); -- JA ENDMASK 3 SETZEN + ENDMASK2_SHIFT[7..4] = 9 - (0,(DST_ADR_NODE[3..1])) + (8 & (DST_ADR_NODE[3..1]==0)); -- JA ENDMASK 3 SETZEN ELSE ENDMASK2_SHIFT[7..4] = 0; -- NEIN -> ENDMASK 3 AUF ENDMASK2 SETZEN END IF; IF BL_X_CNT[]<=(X_CNT_NODE[] + 8) THEN -- SCHON ZEILENANFANG? - ENDMASK1_SHIFT[7..4] = 1 + (0,(DST_ADR_NODE[3..1])); -- JA ENDMASK 3 SETZEN + ENDMASKEND[] = X_INDEX[] - BL_X_CNT[] + (0,(DST_ADR_NODE[3..1])); + ENDMASK2_SHIFT[7..4] = 1 + (0,(ENDMASKEND[3..1])); -- JA: ENDMASK 3 SETZEN ELSE ENDMASK1_SHIFT[7..4] = 0; -- NEIN -> ENDMASK 3 AUF ENDMASK2 SETZEN END IF; @@ -490,7 +491,8 @@ BEGIN ENDMASK1_SHIFT[7..4] = 0; -- NEIN->ENDMASK1 AUF ENDMASK2 SETZEN END IF; IF BL_X_CNT[]<=(X_CNT_NODE[] + 8) THEN -- SCHON ZEILENENDE? - ENDMASK2_SHIFT[7..4] = 1 + (0,(DST_ADR_NODE[3..1])); -- JA ENDMASK 3 SETZEN + ENDMASKEND[] = X_CNT_NODE[] + 8 - BL_X_CNT[]; + ENDMASK2_SHIFT[7..4] = 1 + ENDMASKEND[3..0]; -- JA: ENDMASK 3 SETZEN ELSE ENDMASK2_SHIFT[7..4] = 0; -- NOCH NICHT AKTIV->ENDMASK 3 AUF ENDMASK2 SETZEN END IF; @@ -503,13 +505,14 @@ BEGIN ENDMASK23_OUT[] = lpm_clshift144(ENDMASK23_IN[],0,ENDMASK2_SHIFT[]); -- IMMER LINKS SCHIEBEN ENDMASK123[] = ENDMASK12_OUT[127..0] & ENDMASK23_OUT[143..16]; BLITTER_DOUT[] = ((ENDMASK123[] & OP_OUT[]) # (!ENDMASK123[] & BL_DST_BUFRD[])); - NOT_DST_READ = BL_OP[3..0]==(H"0" # H"3" # H"C" # H"F") & (ENDMASK123[]==-1); --- STATE MACHINE **************************************************************************************************** + NOT_DST_READ = ((BL_OP[3..0]==H"0") # (BL_OP[3..0]==H"3") # (BL_OP[3..0]==H"C") # (BL_OP[3..0]==H"F")) & (ENDMASK123[]==H"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"); +-- STATE MACHINE **********************************************************************************---------------------------12345678901234567890123456789012 BLITTER_RUN = BLITTER_ON; -- BLITTER IST DA! - DDR_RAM_FREE = BLITTER_DACK[]==H"0"; -- 0 WENN FREI BLITTER_ADR[3..0] = H"0"; -- IMMER LINE SRC_DDR_ADR[] = (SRC_ADR_NODE[] - (0,(16 & BL_SRC_X_INC15))); -- WENN RÜCKWÄRTS NEXT ADRESS SRC DST_DDR_ADR[] = (DST_ADR_NODE[] - (0,(16 & BL_DST_X_INC15))); -- WENN RÜCKWÄRTS NEXT ADRESS DST + BLITTER_REQ.CLK = DDRCLK0; + BLITTER_SIG = BLITTER_REQ & BLITTER_DACK[]==H"0"; -- BLITTER MAIN STATE MACHINE ----------------------------------------------- BL_SM.CLK = DDRCLK0; CASE BL_SM IS @@ -521,11 +524,24 @@ BEGIN END IF; WHEN NEW_LINE => ----------------------- NEU LINIE X_INDEX_CLR = VCC; -- LÖSCHEN - BL_SM = RDSRC1; + BL_SM = RDSRC0; + WHEN RDSRC0 => ------------------------ READ SRC1 + IF SRC_READ THEN + BLITTER_ADR[31..4] = SRC_DDR_ADR[31..4] - 1; + BLITTER_REQ = VCC; + BL_READ_SRC = VCC; -- LATCH UND SB1->SB2 + IF BLITTER_DACK0 THEN + BL_SM = RDSRC2; + ELSE + BL_SM = RDSRC1; + END IF; + ELSE + BL_SM = RDDST; + END IF; WHEN RDSRC1 => ------------------------ READ SRC1 IF SRC_READ THEN BLITTER_ADR[31..4] = SRC_DDR_ADR[31..4]; - BLITTER_SIG = DDR_RAM_FREE; + BLITTER_REQ = VCC; BL_READ_SRC = VCC; -- LATCH UND SB1->SB2 IF BLITTER_DACK0 THEN SIINC = VCC; -- INC SRC ADR @@ -539,7 +555,7 @@ BEGIN WHEN RDSRC2 => ------------------------ READ SRC2 IF SRC_READ THEN BLITTER_ADR[31..4] = SRC_DDR_ADR[31..4]; - BLITTER_SIG = DDR_RAM_FREE; + BLITTER_REQ = VCC; BL_READ_SRC = VCC; -- LATCH UND SB1->SB2 IF BLITTER_DACK0 THEN SIINC = VCC; -- INC SRC ADR @@ -552,21 +568,23 @@ BEGIN END IF; WHEN RDDST => ----------------------- READ DEST IF NOT_DST_READ THEN - BL_SM = WRDST; + BL_SM = WRDSTW1; ELSE BLITTER_ADR[31..4] = DST_DDR_ADR[31..4]; - BLITTER_SIG = DDR_RAM_FREE; + BLITTER_REQ = VCC; BL_READ_DST = VCC; IF BLITTER_DACK0 THEN - BL_SM = WRDST; + BL_SM = WRDSTW1; ELSE BL_SM = RDDST; END IF; END IF; + WHEN WRDSTW1 => ------------------- WRITE DEST WAIT AUF ERGEBNIS + BL_SM = WRDST; WHEN WRDST => ------------------- WRITE DEST BLITTER_ADR[31..4] = DST_DDR_ADR[31..4]; - BLITTER_WR = DDR_RAM_FREE; - BLITTER_SIG = DDR_RAM_FREE; + BLITTER_WR = VCC; + BLITTER_REQ = VCC; IF BLITTER_DACK0 THEN XIINC = VCC; -- INC X_INDEX DIINC = VCC; -- INC DEST ADR @@ -575,7 +593,7 @@ BEGIN BL_SM = WRDST; END IF; WHEN TESTZEILENENDE => ----------------- ZEILENDE? - IF BL_X_CNT[]<=(X_CNT_NODE[]) THEN -- SCHON ZEILENENDE? + IF X_CNT_NODE[] >= BL_X_CNT[] THEN -- SCHON ZEILENENDE? YIINC = VCC; -- JA -> INC Y-INDEX UND ZEILE SRC UND DEST BL_SM = TESTFERTIG; -- -> ELSE @@ -583,7 +601,7 @@ BEGIN END IF; WHEN TESTFERTIG => --------------------- TEST AUF FERTIG ZIINC = VCC; -- INC ADRESSEN ZEILENUMBRUCH - IF Y_INDEX[]>=BL_Y_CNT[] THEN -- LETZTE ZEILE? + IF Y_INDEX[] >= BL_Y_CNT[] THEN -- LETZTE ZEILE? BL_SM = FERTIG; -- JA --> ELSE ZYINC = VCC; -- YINC ADDIEREN ZEILENENDE diff --git a/FPGA_by_Fredi/blitter.tdf.bak b/FPGA_by_Fredi/blitter.tdf.bak index f06d03b..8669470 100644 --- a/FPGA_by_Fredi/blitter.tdf.bak +++ b/FPGA_by_Fredi/blitter.tdf.bak @@ -70,8 +70,11 @@ SUBDESIGN BLITTER ) VARIABLE - FB_B[3..0] :NODE; + BYT :NODE; + LONGLINE :NODE; + W_ADR[18..0] :NODE; FB_16B[1..0] :NODE; + W_A1 :DFFE; BLITTER_CS :NODE; BL_HRAM_CS :NODE; BL_HRAM_BE[1..0] :NODE; @@ -160,30 +163,27 @@ VARIABLE ENDMASK23_IN[143..0] :NODE; ENDMASK23_OUT[143..0] :NODE; ENDMASK123[127..0] :NODE; - DDR_RAM_FREE :NODE; + ENDMASKEND[15..0] :NODE; SRC_DDR_ADR[31..0] :NODE; DST_DDR_ADR[31..0] :NODE; + BLITTER_REQ :DFF; -- MAIN STATE MACHINE - BL_SM :MACHINE WITH STATES(START,NEW_LINE,NEW_LINEW,RDSRC1,RDSRC2,RDDST,WRDST,TESTZEILENENDE,TESTFERTIG,FERTIG); + BL_SM :MACHINE WITH STATES(START,NEW_LINE,NEW_LINEW,RDSRC0,RDSRC1,RDSRC2,RDDST,WRDSTW1,WRDSTW2,WRDST,TESTZEILENENDE,TESTFERTIG,FERTIG); BEGIN --- BYT SELECT 32 BIT - FB_B0 = FB_ADR[1..0]==0; -- ADR==0 - FB_B1 = FB_ADR[1..0]==1 -- ADR==1 - # FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HIGH WORD - # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE - FB_B2 = FB_ADR[1..0]==2 -- ADR==2 - # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE - FB_B3 = FB_ADR[1..0]==3 -- ADR==3 - # FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LOW WORD - # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE --- BYT SELECT 16 BIT - FB_16B0 = FB_ADR[0]==0; -- ADR==0 - FB_16B1 = FB_ADR[0]==1 -- wenn ADR==1 - # !(!FB_SIZE1 & FB_SIZE0); -- or NOT BYT +-- BYT UND WORD SELECT 16 BIT + BYT = !FB_SIZE1 & FB_SIZE0; + LONGLINE = !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0; -- LONG OR LINE + W_A1.CLK = MAIN_CLK; + W_A1.ENA = FB_ALE # BLITTER_TA & LONGLINE; + W_A1 = FB_ADR[1] & FB_ALE # BLITTER_TA & LONGLINE; -- A1 HOCHZÄHLEN BEI LONG UND LINE WEGEN BURST + W_ADR[18..1] = FB_ADR[19..2]; + W_ADR0 = W_A1; + FB_16B0 = FB_ADR[0]==0; -- wenn ADR==0 + FB_16B1 = FB_ADR[0]==1 # !BYT; -- wenn ADR==1 or NOT BYT -- BLITTER CS - BLITTER_CS = !nFB_CS1 & FB_ADR[19..7]==H"1F14"; -- FFFF8A00-7F + BLITTER_CS = !nFB_CS1 & FB_ADR[19..7]==H"1F14"; -- FFFF8A00-7F BLITTER_TA = BLITTER_CS; -- REGISTER -- HALFTON RAM @@ -192,114 +192,114 @@ BEGIN BL_HRAM_BE0 = BL_HRAM_CS & FB_16B1; WREN_B = B"0"; LINE_NR[] = ((Y_INDEX[3..0] & !BL_DST_Y_INC15) # (!Y_INDEX[3..0] & BL_DST_Y_INC15)); - (BL_DPRAM_OUT[],BL_HRAM_OUT[]) = altsyncram0(FB_ADR[4..1],LINE_NR[],BL_HRAM_BE[],MAIN_CLK,DDRCLK0,FB_AD[31..16],FB_AD[31..16],BL_HRAM_CS & !nFB_WR,WREN_B); + (BL_DPRAM_OUT[],BL_HRAM_OUT[]) = altsyncram0(W_ADR[3..0],LINE_NR[],BL_HRAM_BE[],MAIN_CLK,DDRCLK0,FB_AD[31..16],FB_AD[31..16],BL_HRAM_CS & !nFB_WR,WREN_B); -- SRC X INC BL_SRC_X_INC[].CLK = MAIN_CLK; BL_SRC_X_INC[] = FB_AD[31..16]; - BL_SRC_X_INC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C510"; -- $F8A20.w + BL_SRC_X_INC_CS = !nFB_CS1 & W_ADR[]==H"7C510"; -- $F8A20.w BL_SRC_X_INC[15..8].ENA = BL_SRC_X_INC_CS & !nFB_WR & FB_16B0; BL_SRC_X_INC[7..0].ENA = BL_SRC_X_INC_CS & !nFB_WR & FB_16B1; SRC_XINC_NODE[] = (H"FFFF0000" & BL_SRC_X_INC15) # (H"0000",BL_SRC_X_INC[]); -- ERWEITERN AUF 32 BIT -- SRC Y INC BL_SRC_Y_INC[].CLK = MAIN_CLK; BL_SRC_Y_INC[] = FB_AD[31..16]; - BL_SRC_Y_INC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C511"; -- $F8A22.w + BL_SRC_Y_INC_CS = !nFB_CS1 & W_ADR[]==H"7C511"; -- $F8A22.w BL_SRC_Y_INC[15..8].ENA = BL_SRC_Y_INC_CS & !nFB_WR & FB_16B0; BL_SRC_Y_INC[7..0].ENA = BL_SRC_Y_INC_CS & !nFB_WR & FB_16B1; SRC_YINC_NODE[] = (H"FFFF0000" & BL_SRC_Y_INC15) # (H"0000",BL_SRC_Y_INC[]); -- ERWEITERN AUF 32 BIT -- SRC ADR HIGH BL_SRC_ADR[].CLK = MAIN_CLK; BL_SRC_ADR[31..16] = FB_AD[31..16]; - BL_SRC_ADRH_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C512"; -- $F8A24.w + BL_SRC_ADRH_CS = !nFB_CS1 & W_ADR[]==H"7C512"; -- $F8A24.w BL_SRC_ADR[31..24].ENA = BL_SRC_ADRH_CS & !nFB_WR & FB_16B0; BL_SRC_ADR[23..16].ENA = BL_SRC_ADRH_CS & !nFB_WR & FB_16B1; -- SRC ADR LOW BL_SRC_ADR[].CLK = MAIN_CLK; BL_SRC_ADR[15..0] = FB_AD[31..16]; - BL_SRC_ADRL_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C513"; -- $F8A26.w + BL_SRC_ADRL_CS = !nFB_CS1 & W_ADR[]==H"7C513"; -- $F8A26.w BL_SRC_ADR[15..8].ENA = BL_SRC_ADRL_CS & !nFB_WR & FB_16B0; BL_SRC_ADR[7..0].ENA = BL_SRC_ADRL_CS & !nFB_WR & FB_16B1; SRC_IADR[].CLK = DDRCLK0; - SRC_IADRH_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C520"; -- $F8A40.w - SRC_IADRL_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C521"; -- $F8A42.w - SRC_IADR_CLR = (BL_SRC_ADRL_CS # BL_SRC_ADRH_CS) & !nFB_WR; -- LÖSCHEN BEI WRITE + SRC_IADRH_CS = !nFB_CS1 & W_ADR[]==H"7C520"; -- $F8A40.w + SRC_IADRL_CS = !nFB_CS1 & W_ADR[]==H"7C521"; -- $F8A42.w + SRC_IADR_CLR = (BL_SRC_ADRL_CS # BL_SRC_ADRH_CS) & !nFB_WR; -- LÖSCHEN BEI WRITE SRC_IADR[] = (SRC_IADR[] + (((8 * SRC_XINC_NODE[]) & SIINC) + (SRC_YINC_NODE[] & ZYINC) + ((((0,BL_X_CNT[]) - (0,X_INDEX[]) - 8) * SRC_XINC_NODE[]) & ZIINC)) & SRC_READ) & !SRC_IADR_CLR; SRC_ADR_NODE[] = BL_SRC_ADR[] + SRC_IADR[]; -- ZUGRIFFSADRESSE THEORETISCH -- ENDMASK 1 BL_ENDMASK1[].CLK = MAIN_CLK; BL_ENDMASK1[] = FB_AD[31..16]; - BL_ENDMASK1_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C514"; -- $F8A28.w + BL_ENDMASK1_CS = !nFB_CS1 & W_ADR[]==H"7C514"; -- $F8A28.w BL_ENDMASK1[15..8].ENA = BL_ENDMASK1_CS & !nFB_WR & FB_16B0; BL_ENDMASK1[7..0].ENA = BL_ENDMASK1_CS & !nFB_WR & FB_16B1; -- ENDMASK 2 BL_ENDMASK2[].CLK = MAIN_CLK; BL_ENDMASK2[] = FB_AD[31..16]; - BL_ENDMASK2_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C515"; -- $F8A2A.w + BL_ENDMASK2_CS = !nFB_CS1 & W_ADR[]==H"7C515"; -- $F8A2A.w BL_ENDMASK2[15..8].ENA = BL_ENDMASK2_CS & !nFB_WR & FB_16B0; BL_ENDMASK2[7..0].ENA = BL_ENDMASK2_CS & !nFB_WR & FB_16B1; -- ENDMASK 3 BL_ENDMASK3[].CLK = MAIN_CLK; BL_ENDMASK3[] = FB_AD[31..16]; - BL_ENDMASK3_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C516"; -- $F8A2C.w + BL_ENDMASK3_CS = !nFB_CS1 & W_ADR[]==H"7C516"; -- $F8A2C.w BL_ENDMASK3[15..8].ENA = BL_ENDMASK3_CS & !nFB_WR & FB_16B0; BL_ENDMASK3[7..0].ENA = BL_ENDMASK3_CS & !nFB_WR & FB_16B1; -- DST X INC BL_DST_X_INC[].CLK = MAIN_CLK; BL_DST_X_INC[] = FB_AD[31..16]; - BL_DST_X_INC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C517"; -- $F8A2E.w + BL_DST_X_INC_CS = !nFB_CS1 & W_ADR[]==H"7C517"; -- $F8A2E.w BL_DST_X_INC[15..8].ENA = BL_DST_X_INC_CS & !nFB_WR & FB_16B0; BL_DST_X_INC[7..0].ENA = BL_DST_X_INC_CS & !nFB_WR & FB_16B1; DST_XINC_NODE[] = (H"FFFF0000" & BL_DST_X_INC15) # (H"0000",BL_DST_X_INC[]); -- ERWEITERN AUF 32 BIT -- DST Y INC BL_DST_Y_INC[].CLK = MAIN_CLK; BL_DST_Y_INC[] = FB_AD[31..16]; - BL_DST_Y_INC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C518"; -- $F8A30.w + BL_DST_Y_INC_CS = !nFB_CS1 & W_ADR[]==H"7C518"; -- $F8A30.w BL_DST_Y_INC[15..8].ENA = BL_DST_Y_INC_CS & !nFB_WR & FB_16B0; BL_DST_Y_INC[7..0].ENA = BL_DST_Y_INC_CS & !nFB_WR & FB_16B1; DST_YINC_NODE[] = (H"FFFF0000" & BL_DST_Y_INC15) # (H"0000",BL_DST_Y_INC[]); -- ERWEITERN AUF 32 BIT -- DST ADR HIGH BL_DST_ADR[].CLK = MAIN_CLK; BL_DST_ADR[31..16] = FB_AD[31..16]; - BL_DST_ADRH_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C519"; -- $F8A32.w + BL_DST_ADRH_CS = !nFB_CS1 & W_ADR[]==H"7C519"; -- $F8A32.w BL_DST_ADR[31..24].ENA = BL_DST_ADRH_CS & !nFB_WR & FB_16B0; BL_DST_ADR[23..16].ENA = BL_DST_ADRH_CS & !nFB_WR & FB_16B1; -- DST ADR LOW BL_DST_ADR[].CLK = MAIN_CLK; BL_DST_ADR[15..0] = FB_AD[31..16]; - BL_DST_ADRL_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51A"; -- $F8A34.w + BL_DST_ADRL_CS = !nFB_CS1 & W_ADR[]==H"7C51A"; -- $F8A34.w BL_DST_ADR[15..8].ENA = BL_DST_ADRL_CS & !nFB_WR & FB_16B0; BL_DST_ADR[7..0].ENA = BL_DST_ADRL_CS & !nFB_WR & FB_16B1; DST_IADR[].CLK = DDRCLK0; - DST_IADRH_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C522"; -- $F8A44.w - DST_IADRL_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C523"; -- $F8A46.w + DST_IADRH_CS = !nFB_CS1 & W_ADR[]==H"7C522"; -- $F8A44.w + DST_IADRL_CS = !nFB_CS1 & W_ADR[]==H"7C523"; -- $F8A46.w DST_IADR_CLR = (BL_DST_ADRL_CS # BL_DST_ADRH_CS) & !nFB_WR; -- LÖSCHEN BEI WRITE DST_IADR[] = (DST_IADR[] + ((8 * DST_XINC_NODE[]) & DIINC) + (DST_YINC_NODE[] & ZYINC) + ((((0,BL_X_CNT[]) - (0,X_INDEX[])) * DST_XINC_NODE[]) & ZIINC)) & !DST_IADR_CLR; DST_ADR_NODE[] = BL_DST_ADR[] + DST_IADR[]; -- ZUGRIFFSADRESSE THEORETISCH -- X COUNT BL_X_CNT[].CLK = MAIN_CLK; BL_X_CNT[] = FB_AD[31..16]; - BL_X_CNT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51B"; -- $F8A36.w + BL_X_CNT_CS = !nFB_CS1 & W_ADR[]==H"7C51B"; -- $F8A36.w BL_X_CNT[15..8].ENA = BL_X_CNT_CS & !nFB_WR & FB_16B0; BL_X_CNT[7..0].ENA = BL_X_CNT_CS & !nFB_WR & FB_16B1; X_INDEX[].CLK = DDRCLK0; - X_INDEX_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C524"; -- $F8A48.w + X_INDEX_CS = !nFB_CS1 & W_ADR[]==H"7C524"; -- $F8A48.w X_INDEX_CLR = BL_X_CNT_CS & !nFB_WR; -- LÖSCHEN BEI WRITE X_INDEX[] = (X_INDEX[] + (8 & XIINC) + ((BL_X_CNT[] - X_INDEX[]) & ZIINC)) & !X_INDEX_CLR; X_CNT_NODE[] = X_INDEX[] - ((0,DST_ADR_NODE[3..1]) & (X_INDEX[]!=0));-- EFFEKTIV GELESENE -- Y COUNT BL_Y_CNT[].CLK = MAIN_CLK; BL_Y_CNT[] = FB_AD[31..16]; - BL_Y_CNT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51C"; -- $F8A38.w + BL_Y_CNT_CS = !nFB_CS1 & W_ADR[]==H"7C51C"; -- $F8A38.w BL_Y_CNT[15..8].ENA = BL_Y_CNT_CS & !nFB_WR & FB_16B0; BL_Y_CNT[7..0].ENA = BL_Y_CNT_CS & !nFB_WR & FB_16B1; Y_INDEX[].CLK = DDRCLK0; - Y_INDEX_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C525"; -- $F8A4A.w + Y_INDEX_CS = !nFB_CS1 & W_ADR[]==H"7C525"; -- $F8A4A.w Y_INDEX_CLR = BL_Y_CNT_CS & !nFB_WR; -- LÖSCHEN BEI WRITE Y_INDEX[] = (Y_INDEX[] + (1 & YIINC)) & !Y_INDEX_CLR; -- HOP LOGIC BL_HOP[].CLK = MAIN_CLK; BL_HOP[] = FB_AD[31..24]; - BL_HOP_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51D"; -- $F8A3A.w + BL_HOP_CS = !nFB_CS1 & W_ADR[]==H"7C51D"; -- $F8A3A.w BL_HOP[7..0].ENA = BL_HOP_CS & !nFB_WR & FB_16B0; -- $F8A3A -- OP LOGIC BL_OP[].CLK = MAIN_CLK; @@ -309,7 +309,7 @@ BEGIN BL_LN[].CLK = MAIN_CLK; BL_LN[6..0] = FB_AD[30..24]; BL_LN7 = FB_AD31 & !LN7CLR; -- BUSY HOG UND SMUDGE - BL_LN_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51E"; -- $F8A3C.w + BL_LN_CS = !nFB_CS1 & W_ADR[]==H"7C51E"; -- $F8A3C.w BL_LN[].ENA = BL_LN_CS & !nFB_WR & FB_16B0; -- $F8A3C BL_LN7.ENA = LN7CLR; -- SKEW BYT @@ -340,8 +340,8 @@ BEGIN # DST_IADRL_CS & DST_IADR[15..0] # X_INDEX_CS & X_INDEX[] # Y_INDEX_CS & Y_INDEX[] - ,BLITTER_CS & !nFB_OE); -- FFFF8A00-7F ------------------------------------------ + ,BLITTER_CS & !nFB_OE); -- FFFF8A00-7F +-------------------------------------------------------------------------------------- -- SRC BUFFER LADEN BL_SRC_BUF1[].CLK = DDRCLK0; BL_SRC_BUF1[127..64].ENA = BLITTER_DACK1 & BL_READ_SRC; @@ -400,7 +400,7 @@ BEGIN BL_BS_SKEW[] = DIST_RIGHT[7..0]; -- LPM SHIFT RIGHT SHIFT_DIR = VCC; -- DIR = RIGHT else - BL_BS_SKEW[] = !DIST_RIGHT[3..0] + 1; -- LPM SHIFT LEFT + BL_BS_SKEW[] = !DIST_RIGHT[7..0] + 1; -- LPM SHIFT LEFT SHIFT_DIR = GND; -- DIR = LEFT end if; -- barell shifter: direction 0=links 1=rechts IN BEZUG AUF ausgabewert! @@ -471,15 +471,16 @@ BEGIN END CASE; ------------ ENDMASKEN SETZEN ****************************************************************************** ENDMASK1_SHIFT[3..0] = 0; - ENDMASK2_SHIFT[3..0] = 0; + ENDMASK2_SHIFT[3..0] = 0; IF BL_DST_X_INC15 THEN ---------------------------- RÜCKWÄRTS X_INC NEGATIV IF X_INDEX[]==0 THEN -- ENDE? - ENDMASK2_SHIFT[7..4] = 1 + (0,(DST_ADR_NODE[3..1])); -- JA ENDMASK 3 SETZEN + ENDMASK2_SHIFT[7..4] = 9 - (0,(DST_ADR_NODE[3..1])) + (8 & (DST_ADR_NODE[3..1]==0)); -- JA ENDMASK 3 SETZEN ELSE ENDMASK2_SHIFT[7..4] = 0; -- NEIN -> ENDMASK 3 AUF ENDMASK2 SETZEN END IF; IF BL_X_CNT[]<=(X_CNT_NODE[] + 8) THEN -- SCHON ZEILENANFANG? - ENDMASK1_SHIFT[7..4] = 1 + (0,(DST_ADR_NODE[3..1])); -- JA ENDMASK 3 SETZEN + ENDMASKEND[] = X_INDEX[] - BL_X_CNT[] + (0,(DST_ADR_NODE[3..1])); + ENDMASK2_SHIFT[7..4] = 1 + (0,(ENDMASKEND[3..1])); -- JA: ENDMASK 3 SETZEN ELSE ENDMASK1_SHIFT[7..4] = 0; -- NEIN -> ENDMASK 3 AUF ENDMASK2 SETZEN END IF; @@ -490,7 +491,8 @@ BEGIN ENDMASK1_SHIFT[7..4] = 0; -- NEIN->ENDMASK1 AUF ENDMASK2 SETZEN END IF; IF BL_X_CNT[]<=(X_CNT_NODE[] + 8) THEN -- SCHON ZEILENENDE? - ENDMASK2_SHIFT[7..4] = 1 + (0,(DST_ADR_NODE[3..1])); -- JA ENDMASK 3 SETZEN + ENDMASKEND[] = X_CNT_NODE[] + 8 - BL_X_CNT[]; + ENDMASK2_SHIFT[7..4] = 1 + ENDMASKEND[3..0]; -- JA: ENDMASK 3 SETZEN ELSE ENDMASK2_SHIFT[7..4] = 0; -- NOCH NICHT AKTIV->ENDMASK 3 AUF ENDMASK2 SETZEN END IF; @@ -503,13 +505,14 @@ BEGIN ENDMASK23_OUT[] = lpm_clshift144(ENDMASK23_IN[],0,ENDMASK2_SHIFT[]); -- IMMER LINKS SCHIEBEN ENDMASK123[] = ENDMASK12_OUT[127..0] & ENDMASK23_OUT[143..16]; BLITTER_DOUT[] = ((ENDMASK123[] & OP_OUT[]) # (!ENDMASK123[] & BL_DST_BUFRD[])); - NOT_DST_READ = BL_OP[3..0]==(H"0" # H"3" # H"C" # H"F") & (ENDMASK123[]==-1); --- STATE MACHINE **************************************************************************************************** + NOT_DST_READ = ((BL_OP[3..0]==H"0") # (BL_OP[3..0]==H"3") # (BL_OP[3..0]==H"C") # (BL_OP[3..0]==H"F")) & (ENDMASK123[]==H"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"); +-- STATE MACHINE **********************************************************************************---------------------------12345678901234567890123456789012 BLITTER_RUN = BLITTER_ON; -- BLITTER IST DA! - DDR_RAM_FREE = BLITTER_DACK[]==H"0"; -- 0 WENN FREI BLITTER_ADR[3..0] = H"0"; -- IMMER LINE SRC_DDR_ADR[] = (SRC_ADR_NODE[] - (0,(16 & BL_SRC_X_INC15))); -- WENN RÜCKWÄRTS NEXT ADRESS SRC DST_DDR_ADR[] = (DST_ADR_NODE[] - (0,(16 & BL_DST_X_INC15))); -- WENN RÜCKWÄRTS NEXT ADRESS DST + BLITTER_REQ.CLK = DDRCLK0; + BLITTER_SIG = BLITTER_REQ & BLITTER_DACK[]==H"0"; -- BLITTER MAIN STATE MACHINE ----------------------------------------------- BL_SM.CLK = DDRCLK0; CASE BL_SM IS @@ -521,11 +524,24 @@ BEGIN END IF; WHEN NEW_LINE => ----------------------- NEU LINIE X_INDEX_CLR = VCC; -- LÖSCHEN - BL_SM = RDSRC1; + BL_SM = RDSRC0; + WHEN RDSRC0 => ------------------------ READ SRC1 + IF SRC_READ THEN + BLITTER_ADR[31..4] = SRC_DDR_ADR[31..4] - 1; + BLITTER_REQ = VCC; + BL_READ_SRC = VCC; -- LATCH UND SB1->SB2 + IF BLITTER_DACK0 THEN + BL_SM = RDSRC2; + ELSE + BL_SM = RDSRC1; + END IF; + ELSE + BL_SM = RDDST; + END IF; WHEN RDSRC1 => ------------------------ READ SRC1 IF SRC_READ THEN BLITTER_ADR[31..4] = SRC_DDR_ADR[31..4]; - BLITTER_SIG = DDR_RAM_FREE; + BLITTER_REQ = VCC; BL_READ_SRC = VCC; -- LATCH UND SB1->SB2 IF BLITTER_DACK0 THEN SIINC = VCC; -- INC SRC ADR @@ -539,7 +555,7 @@ BEGIN WHEN RDSRC2 => ------------------------ READ SRC2 IF SRC_READ THEN BLITTER_ADR[31..4] = SRC_DDR_ADR[31..4]; - BLITTER_SIG = DDR_RAM_FREE; + BLITTER_REQ = VCC; BL_READ_SRC = VCC; -- LATCH UND SB1->SB2 IF BLITTER_DACK0 THEN SIINC = VCC; -- INC SRC ADR @@ -551,22 +567,26 @@ BEGIN BL_SM = RDDST; END IF; WHEN RDDST => ----------------------- READ DEST - IF NOT_READ_DST THEN - BL_SM = WRDST; + IF NOT_DST_READ THEN + BL_SM = WRDSTW1; ELSE BLITTER_ADR[31..4] = DST_DDR_ADR[31..4]; - BLITTER_SIG = DDR_RAM_FREE; + BLITTER_REQ = VCC; BL_READ_DST = VCC; IF BLITTER_DACK0 THEN - BL_SM = WRDST; + BL_SM = WRDSTW1; ELSE BL_SM = RDDST; END IF; END IF; + WHEN WRDSTW1 => ------------------- WRITE DEST WAIT AUF ERGEBNIS + BL_SM = WRDSTW2; + WHEN WRDSTW2 => ------------------- WRITE DEST WAIT AUF ERGEBNIS + BL_SM = WRDST; WHEN WRDST => ------------------- WRITE DEST BLITTER_ADR[31..4] = DST_DDR_ADR[31..4]; - BLITTER_WR = DDR_RAM_FREE; - BLITTER_SIG = DDR_RAM_FREE; + BLITTER_WR = VCC; + BLITTER_REQ = VCC; IF BLITTER_DACK0 THEN XIINC = VCC; -- INC X_INDEX DIINC = VCC; -- INC DEST ADR @@ -575,7 +595,7 @@ BEGIN BL_SM = WRDST; END IF; WHEN TESTZEILENENDE => ----------------- ZEILENDE? - IF BL_X_CNT[]<=(X_CNT_NODE[]) THEN -- SCHON ZEILENENDE? + IF X_CNT_NODE[] >= BL_X_CNT[] THEN -- SCHON ZEILENENDE? YIINC = VCC; -- JA -> INC Y-INDEX UND ZEILE SRC UND DEST BL_SM = TESTFERTIG; -- -> ELSE @@ -583,7 +603,7 @@ BEGIN END IF; WHEN TESTFERTIG => --------------------- TEST AUF FERTIG ZIINC = VCC; -- INC ADRESSEN ZEILENUMBRUCH - IF Y_INDEX[]>=BL_Y_CNT[] THEN -- LETZTE ZEILE? + IF Y_INDEX[] >= BL_Y_CNT[] THEN -- LETZTE ZEILE? BL_SM = FERTIG; -- JA --> ELSE ZYINC = VCC; -- YINC ADDIEREN ZEILENENDE diff --git a/FPGA_by_Fredi/firebee1.asm.rpt b/FPGA_by_Fredi/firebee1.asm.rpt deleted file mode 100644 index 0641298..0000000 --- a/FPGA_by_Fredi/firebee1.asm.rpt +++ /dev/null @@ -1,128 +0,0 @@ -Assembler report for firebee1 -Thu Apr 13 11:08:24 2017 -Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Assembler Summary - 3. Assembler Settings - 4. Assembler Generated Files - 5. Assembler Device Options: C:/FireBee/FPGA/firebee1.sof - 6. Assembler Device Options: C:/FireBee/FPGA/firebee1.rbf - 7. Assembler Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 1991-2010 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. - - - -+---------------------------------------------------------------+ -; Assembler Summary ; -+-----------------------+---------------------------------------+ -; Assembler Status ; Successful - Thu Apr 13 11:08:24 2017 ; -; Revision Name ; firebee1 ; -; Top-level Entity Name ; firebee1 ; -; Family ; Cyclone III ; -; Device ; EP3C40F484C6 ; -+-----------------------+---------------------------------------+ - - -+----------------------------------------------------------------------------------------------------------+ -; Assembler Settings ; -+-----------------------------------------------------------------------------+------------+---------------+ -; Option ; Setting ; Default Value ; -+-----------------------------------------------------------------------------+------------+---------------+ -; Generate Raw Binary File (.rbf) For Target Device ; On ; Off ; -; Hexadecimal Output File start address ; 0XE0700000 ; 0 ; -; Use smart compilation ; Off ; Off ; -; Enable parallel Assembler and TimeQuest Timing Analyzer during compilation ; On ; On ; -; Enable compact report table ; Off ; Off ; -; Generate compressed bitstreams ; On ; On ; -; Compression mode ; Off ; Off ; -; Clock source for configuration device ; Internal ; Internal ; -; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ; -; Divide clock frequency by ; 1 ; 1 ; -; Auto user code ; Off ; Off ; -; Use configuration device ; Off ; Off ; -; Configuration device ; Auto ; Auto ; -; Configuration device auto user code ; Off ; Off ; -; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ; -; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ; -; Hexadecimal Output File count direction ; Up ; Up ; -; Release clears before tri-states ; Off ; Off ; -; Auto-restart configuration after error ; On ; On ; -; Enable OCT_DONE ; Off ; Off ; -; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ; -; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ; -; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ; -; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ; -+-----------------------------------------------------------------------------+------------+---------------+ - - -+------------------------------+ -; Assembler Generated Files ; -+------------------------------+ -; File Name ; -+------------------------------+ -; C:/FireBee/FPGA/firebee1.sof ; -; C:/FireBee/FPGA/firebee1.rbf ; -+------------------------------+ - - -+--------------------------------------------------------+ -; Assembler Device Options: C:/FireBee/FPGA/firebee1.sof ; -+----------------+---------------------------------------+ -; Option ; Setting ; -+----------------+---------------------------------------+ -; Device ; EP3C40F484C6 ; -; JTAG usercode ; 0xFFFFFFFF ; -; Checksum ; 0x01072C3E ; -+----------------+---------------------------------------+ - - -+--------------------------------------------------------+ -; Assembler Device Options: C:/FireBee/FPGA/firebee1.rbf ; -+---------------------+----------------------------------+ -; Option ; Setting ; -+---------------------+----------------------------------+ -; Raw Binary File ; ; -; Compression Ratio ; 2 ; -+---------------------+----------------------------------+ - - -+--------------------+ -; Assembler Messages ; -+--------------------+ -Info: ******************************************************************* -Info: Running Quartus II Assembler - Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition - Info: Processing started: Thu Apr 13 11:08:20 2017 -Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off firebeei1 -c firebee1 -Info: Writing out detailed assembly data for power analysis -Info: Assembler is generating device programming files -Info: Quartus II Assembler was successful. 0 errors, 0 warnings - Info: Peak virtual memory: 310 megabytes - Info: Processing ended: Thu Apr 13 11:08:24 2017 - Info: Elapsed time: 00:00:04 - Info: Total CPU time (on all processors): 00:00:05 - - diff --git a/FPGA_by_Fredi/firebee1.bdf b/FPGA_by_Fredi/firebee1.bdf index dc29aec..beb9946 100644 --- a/FPGA_by_Fredi/firebee1.bdf +++ b/FPGA_by_Fredi/firebee1.bdf @@ -3506,7 +3506,7 @@ applicable agreement for further details. (line (pt 88 24)(pt 72 24)(line_width 3)) ) (drawing - (text "319037463" (rect 27 18 80 30)(font "Arial" )) + (text "402923543" (rect 27 18 80 30)(font "Arial" )) (text "32" (rect 77 25 88 37)(font "Arial" )) (line (pt 16 16)(pt 72 16)(line_width 1)) (line (pt 72 16)(pt 72 32)(line_width 1)) diff --git a/FPGA_by_Fredi/firebee1.done b/FPGA_by_Fredi/firebee1.done index 1c56ddf..2f3cd55 100644 --- a/FPGA_by_Fredi/firebee1.done +++ b/FPGA_by_Fredi/firebee1.done @@ -1 +1 @@ -Thu Apr 13 11:08:39 2017 +Tue Apr 18 20:21:44 2017 diff --git a/FPGA_by_Fredi/firebee1.fit.summary b/FPGA_by_Fredi/firebee1.fit.summary deleted file mode 100644 index 33aa7d2..0000000 --- a/FPGA_by_Fredi/firebee1.fit.summary +++ /dev/null @@ -1,16 +0,0 @@ -Fitter Status : Successful - Thu Apr 13 11:08:12 2017 -Quartus II Version : 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition -Revision Name : firebee1 -Top-level Entity Name : firebee1 -Family : Cyclone III -Device : EP3C40F484C6 -Timing Models : Final -Total logic elements : 20,945 / 39,600 ( 53 % ) - Total combinational functions : 19,059 / 39,600 ( 48 % ) - Dedicated logic registers : 5,696 / 39,600 ( 14 % ) -Total registers : 5845 -Total pins : 296 / 332 ( 89 % ) -Total virtual pins : 0 -Total memory bits : 355,360 / 1,161,216 ( 31 % ) -Embedded Multiplier 9-bit elements : 12 / 252 ( 5 % ) -Total PLLs : 4 / 4 ( 100 % ) diff --git a/FPGA_by_Fredi/firebee1.flow.rpt b/FPGA_by_Fredi/firebee1.flow.rpt deleted file mode 100644 index 1bad0f9..0000000 --- a/FPGA_by_Fredi/firebee1.flow.rpt +++ /dev/null @@ -1,428 +0,0 @@ -Flow report for firebee1 -Sat Apr 15 23:46:36 2017 -Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Flow Summary - 3. Flow Settings - 4. Flow Non-Default Global Settings - 5. Flow Elapsed Time - 6. Flow OS Summary - 7. Flow Log - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 1991-2010 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. - - - -+-----------------------------------------------------------------------------------+ -; Flow Summary ; -+------------------------------------+----------------------------------------------+ -; Flow Status ; Successful - Sat Apr 15 23:46:35 2017 ; -; Quartus II Version ; 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition ; -; Revision Name ; firebee1 ; -; Top-level Entity Name ; firebee1 ; -; Family ; Cyclone III ; -; Device ; EP3C40F484C6 ; -; Timing Models ; Final ; -; Met timing requirements ; N/A ; -; Total logic elements ; 22,593 ; -; Total combinational functions ; 19,050 ; -; Dedicated logic registers ; 5,711 ; -; Total registers ; 5839 ; -; Total pins ; 296 ; -; Total virtual pins ; 0 ; -; Total memory bits ; 355,360 ; -; Embedded Multiplier 9-bit elements ; 12 ; -; Total PLLs ; 4 ; -+------------------------------------+----------------------------------------------+ - - -+-----------------------------------------+ -; Flow Settings ; -+-------------------+---------------------+ -; Option ; Setting ; -+-------------------+---------------------+ -; Start date & time ; 04/15/2017 23:43:13 ; -; Main task ; Compilation ; -; Revision Name ; firebee1 ; -+-------------------+---------------------+ - - -+-----------------------------------------------------------------------------------------------------------------------------+ -; Flow Non-Default Global Settings ; -+-----------------------------------------+------------------------------------+---------------+-------------+----------------+ -; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ; -+-----------------------------------------+------------------------------------+---------------+-------------+----------------+ -; COMPILER_SIGNATURE_ID ; 1098263457634.149229259302120 ; -- ; -- ; -- ; -; CYCLONEII_OPTIMIZATION_TECHNIQUE ; Speed ; Balanced ; -- ; -- ; -; FMAX_REQUIREMENT ; 30 ns ; -- ; -- ; -- ; -; IP_TOOL_NAME ; ALTPLL ; -- ; -- ; -- ; -; IP_TOOL_NAME ; ALTPLL ; -- ; -- ; -- ; -; IP_TOOL_NAME ; ALTPLL ; -- ; -- ; -- ; -; IP_TOOL_NAME ; ALTPLL ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_COUNTER ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_SHIFTREG ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_RAM_DP+ ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_BUSTRI ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_RAM_DP+ ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_BUSTRI ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_BUSTRI ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_CONSTANT ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_CONSTANT ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_MUX ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_MUX ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_MUX ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_CONSTANT ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_RAM_DP+ ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_BUSTRI ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_MUX ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_MUX ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_CONSTANT ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_SHIFTREG ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_LATCH ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_CONSTANT ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_SHIFTREG ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_COMPARE ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_BUSTRI ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_BUSTRI ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_BUSTRI ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_FF ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_FF ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_FF ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_SHIFTREG ; -- ; -- ; -- ; -; IP_TOOL_NAME ; ALTDDIO_BIDIR ; -- ; -- ; -- ; -; IP_TOOL_NAME ; ALTDDIO_OUT ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_MUX ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_SHIFTREG ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_SHIFTREG ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_SHIFTREG ; -- ; -- ; -- ; -; IP_TOOL_NAME ; ALTDDIO_OUT ; -- ; -- ; -- ; -; IP_TOOL_NAME ; ALTDDIO_OUT ; -- ; -- ; -- ; -; IP_TOOL_NAME ; ALTDDIO_OUT ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_MUX ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_FIFO+ ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_FIFO+ ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_MUX ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_MUX ; -- ; -- ; -- ; -; IP_TOOL_NAME ; ALTPLL_RECONFIG ; -- ; -- ; -- ; -; IP_TOOL_NAME ; ALTPLL ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_MUX ; -- ; -- ; -- ; -; IP_TOOL_NAME ; ALTSYNCRAM ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_SHIFTREG ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_COUNTER ; -- ; -- ; -- ; -; IP_TOOL_NAME ; ALTIOBUF ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_MUX ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_FF ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_CLSHIFT ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_CLSHIFT ; -- ; -- ; -- ; -; IP_TOOL_NAME ; LPM_CONSTANT ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 8.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ; -; IP_TOOL_VERSION ; 9.1 ; -- ; -- ; -- ; -; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ; -; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ; -; MISC_FILE ; C:/firebee/FPGA/firebee1.dpf ; -- ; -- ; -- ; -; MISC_FILE ; C:/FireBee/FPGA/firebee1.dpf ; -- ; -- ; -- ; -; MISC_FILE ; altpll1.bsf ; -- ; -- ; -- ; -; MISC_FILE ; altpll1.inc ; -- ; -- ; -- ; -; MISC_FILE ; altpll1.cmp ; -- ; -- ; -- ; -; MISC_FILE ; altpll1.ppf ; -- ; -- ; -- ; -; MISC_FILE ; altpll2.bsf ; -- ; -- ; -- ; -; MISC_FILE ; altpll2.inc ; -- ; -- ; -- ; -; MISC_FILE ; altpll2.cmp ; -- ; -- ; -- ; -; MISC_FILE ; altpll2.ppf ; -- ; -- ; -- ; -; MISC_FILE ; altpll3.bsf ; -- ; -- ; -- ; -; MISC_FILE ; altpll3.inc ; -- ; -- ; -- ; -; MISC_FILE ; altpll3.cmp ; -- ; -- ; -- ; -; MISC_FILE ; altpll3.ppf ; -- ; -- ; -- ; -; MISC_FILE ; altpll0.bsf ; -- ; -- ; -- ; -; MISC_FILE ; altpll0.inc ; -- ; -- ; -- ; -; MISC_FILE ; altpll0.cmp ; -- ; -- ; -- ; -; MISC_FILE ; altpll0.ppf ; -- ; -- ; -- ; -; MISC_FILE ; lpm_counter0.bsf ; -- ; -- ; -- ; -; MISC_FILE ; lpm_counter0.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_shiftreg0.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_shiftreg0.inc ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_shiftreg0.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/altdpram0.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/altdpram0.inc ; -- ; -- ; -- ; -; MISC_FILE ; Video/altdpram0.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_bustri1.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_bustri1.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/altdpram1.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/altdpram1.inc ; -- ; -- ; -- ; -; MISC_FILE ; Video/altdpram1.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_bustri2.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_bustri2.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_bustri4.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_bustri4.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_constant0.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_constant0.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_constant1.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_constant1.inc ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_constant1.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_mux0.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_mux0.inc ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_mux0.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_mux1.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_mux1.inc ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_mux1.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_mux2.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_mux2.inc ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_mux2.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_constant2.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_constant2.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/altdpram2.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/altdpram2.inc ; -- ; -- ; -- ; -; MISC_FILE ; Video/altdpram2.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_bustri6.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_bustri6.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_mux3.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_mux3.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_mux4.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_mux4.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_constant3.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_constant3.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_shiftreg1.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_shiftreg1.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_latch1.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_latch1.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_constant4.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_constant4.inc ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_constant4.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_shiftreg2.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_shiftreg2.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_compare1.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_compare1.inc ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_compare1.cmp ; -- ; -- ; -- ; -; MISC_FILE ; lpm_bustri_LONG.bsf ; -- ; -- ; -- ; -; MISC_FILE ; lpm_bustri_LONG.inc ; -- ; -- ; -- ; -; MISC_FILE ; lpm_bustri_LONG.cmp ; -- ; -- ; -- ; -; MISC_FILE ; lpm_bustri_BYT.bsf ; -- ; -- ; -- ; -; MISC_FILE ; lpm_bustri_BYT.inc ; -- ; -- ; -- ; -; MISC_FILE ; lpm_bustri_BYT.cmp ; -- ; -- ; -- ; -; MISC_FILE ; lpm_bustri_WORD.bsf ; -- ; -- ; -- ; -; MISC_FILE ; lpm_bustri_WORD.inc ; -- ; -- ; -- ; -; MISC_FILE ; lpm_bustri_WORD.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_ff4.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_ff4.inc ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_ff4.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_ff5.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_ff5.inc ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_ff5.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_ff6.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_ff6.inc ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_ff6.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_shiftreg3.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_shiftreg3.inc ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_shiftreg3.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/altddio_bidir0.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/altddio_bidir0.inc ; -- ; -- ; -- ; -; MISC_FILE ; Video/altddio_bidir0.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/altddio_bidir0.ppf ; -- ; -- ; -- ; -; MISC_FILE ; Video/altddio_out0.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/altddio_out0.inc ; -- ; -- ; -- ; -; MISC_FILE ; Video/altddio_out0.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/altddio_out0.ppf ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_mux5.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_mux5.inc ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_mux5.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_shiftreg5.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_shiftreg5.inc ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_shiftreg5.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_shiftreg6.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_shiftreg6.inc ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_shiftreg6.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_shiftreg4.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_shiftreg4.inc ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_shiftreg4.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/altddio_out1.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/altddio_out1.inc ; -- ; -- ; -- ; -; MISC_FILE ; Video/altddio_out1.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/altddio_out1.ppf ; -- ; -- ; -- ; -; MISC_FILE ; Video/altddio_out2.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/altddio_out2.inc ; -- ; -- ; -- ; -; MISC_FILE ; Video/altddio_out2.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/altddio_out2.ppf ; -- ; -- ; -- ; -; MISC_FILE ; altddio_out3.bsf ; -- ; -- ; -- ; -; MISC_FILE ; altddio_out3.inc ; -- ; -- ; -- ; -; MISC_FILE ; altddio_out3.cmp ; -- ; -- ; -- ; -; MISC_FILE ; altddio_out3.ppf ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_mux6.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_mux6.inc ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_mux6.cmp ; -- ; -- ; -- ; -; MISC_FILE ; FalconIO_SDCard_IDE_CF/dcfifo0.bsf ; -- ; -- ; -- ; -; MISC_FILE ; FalconIO_SDCard_IDE_CF/dcfifo0.cmp ; -- ; -- ; -- ; -; MISC_FILE ; FalconIO_SDCard_IDE_CF/dcfifo1.bsf ; -- ; -- ; -- ; -; MISC_FILE ; FalconIO_SDCard_IDE_CF/dcfifo1.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_muxDZ.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_muxDZ.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_muxVDM.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_muxVDM.cmp ; -- ; -- ; -- ; -; MISC_FILE ; altpll_reconfig1.tdf ; -- ; -- ; -- ; -; MISC_FILE ; altpll_reconfig1.bsf ; -- ; -- ; -- ; -; MISC_FILE ; altpll_reconfig1.inc ; -- ; -- ; -- ; -; MISC_FILE ; altpll_reconfig1.cmp ; -- ; -- ; -- ; -; MISC_FILE ; altpll4.tdf ; -- ; -- ; -- ; -; MISC_FILE ; altpll4.bsf ; -- ; -- ; -- ; -; MISC_FILE ; altpll4.inc ; -- ; -- ; -- ; -; MISC_FILE ; altpll4.cmp ; -- ; -- ; -- ; -; MISC_FILE ; altpll4.ppf ; -- ; -- ; -- ; -; MISC_FILE ; lpm_mux0.tdf ; -- ; -- ; -- ; -; MISC_FILE ; lpm_mux0.bsf ; -- ; -- ; -- ; -; MISC_FILE ; lpm_mux0.inc ; -- ; -- ; -- ; -; MISC_FILE ; lpm_mux0.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/BLITTER/altsyncram0.tdf ; -- ; -- ; -- ; -; MISC_FILE ; Video/BLITTER/altsyncram0.inc ; -- ; -- ; -- ; -; MISC_FILE ; lpm_shiftreg0.tdf ; -- ; -- ; -- ; -; MISC_FILE ; lpm_shiftreg0.bsf ; -- ; -- ; -- ; -; MISC_FILE ; lpm_shiftreg0.inc ; -- ; -- ; -- ; -; MISC_FILE ; lpm_shiftreg0.cmp ; -- ; -- ; -- ; -; MISC_FILE ; lpm_counter1.tdf ; -- ; -- ; -- ; -; MISC_FILE ; lpm_counter1.bsf ; -- ; -- ; -- ; -; MISC_FILE ; lpm_counter1.inc ; -- ; -- ; -- ; -; MISC_FILE ; lpm_counter1.cmp ; -- ; -- ; -- ; -; MISC_FILE ; altiobuf_bidir0.tdf ; -- ; -- ; -- ; -; MISC_FILE ; altiobuf_bidir0.bsf ; -- ; -- ; -- ; -; MISC_FILE ; altiobuf_bidir0.inc ; -- ; -- ; -- ; -; MISC_FILE ; altiobuf_bidir0.cmp ; -- ; -- ; -- ; -; MISC_FILE ; lpm_mux1.tdf ; -- ; -- ; -- ; -; MISC_FILE ; lpm_mux1.bsf ; -- ; -- ; -- ; -; MISC_FILE ; lpm_mux1.inc ; -- ; -- ; -- ; -; MISC_FILE ; lpm_mux1.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_blitter.bsf ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_blitter.inc ; -- ; -- ; -- ; -; MISC_FILE ; Video/lpm_blitter.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/BLITTER/lpm_clshift384.tdf ; -- ; -- ; -- ; -; MISC_FILE ; Video/BLITTER/lpm_clshift384.inc ; -- ; -- ; -- ; -; MISC_FILE ; Video/BLITTER/lpm_clshift384.cmp ; -- ; -- ; -- ; -; MISC_FILE ; Video/BLITTER/lpm_clshift144.tdf ; -- ; -- ; -- ; -; MISC_FILE ; Video/BLITTER/lpm_clshift144.inc ; -- ; -- ; -- ; -; MISC_FILE ; FPGA_DATE.tdf ; -- ; -- ; -- ; -; MISC_FILE ; FPGA_DATE.bsf ; -- ; -- ; -- ; -; MISC_FILE ; FPGA_DATE.inc ; -- ; -- ; -- ; -; NOMINAL_CORE_SUPPLY_VOLTAGE ; 1.2V ; -- ; -- ; -- ; -; PARTITION_COLOR ; 16764057 ; -- ; -- ; Top ; -; PARTITION_FITTER_PRESERVATION_LEVEL ; PLACEMENT_AND_ROUTING ; -- ; -- ; Top ; -; PARTITION_NETLIST_TYPE ; SOURCE ; -- ; -- ; Top ; -; PHYSICAL_SYNTHESIS_COMBO_LOGIC ; On ; Off ; -- ; -- ; -; PHYSICAL_SYNTHESIS_COMBO_LOGIC_FOR_AREA ; On ; Off ; -- ; -- ; -; PHYSICAL_SYNTHESIS_EFFORT ; Fast ; Normal ; -- ; -- ; -; PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ; On ; Off ; -- ; -- ; -; POWER_BOARD_THERMAL_MODEL ; None (CONSERVATIVE) ; -- ; -- ; -- ; -; POWER_PRESET_COOLING_SOLUTION ; No Heat Sink With Still Air ; -- ; -- ; -- ; -; POWER_USE_TA_VALUE ; 35 ; 25 ; -- ; -- ; -; STATE_MACHINE_PROCESSING ; One-Hot ; Auto ; -- ; -- ; -; TCO_REQUIREMENT ; 1 ns ; -- ; -- ; -- ; -; TH_REQUIREMENT ; 1 ns ; -- ; -- ; -- ; -; TPD_REQUIREMENT ; 1 ns ; -- ; -- ; -- ; -; TSU_REQUIREMENT ; 1 ns ; -- ; -- ; -- ; -; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off ; -- ; -- ; eda_blast_fpga ; -; USE_TIMEQUEST_TIMING_ANALYZER ; Off ; On ; -- ; -- ; -+-----------------------------------------+------------------------------------+---------------+-------------+----------------+ - - -+--------------------------------------------------------------------------------------------------------------------------+ -; Flow Elapsed Time ; -+----------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ; -+----------------------+--------------+-------------------------+---------------------+------------------------------------+ -; Analysis & Synthesis ; 00:03:20 ; 1.0 ; 355 MB ; 00:03:21 ; -; Total ; 00:03:20 ; -- ; -- ; 00:03:21 ; -+----------------------+--------------+-------------------------+---------------------+------------------------------------+ - - -+---------------------------------------------------------------------------------------+ -; Flow OS Summary ; -+----------------------+------------------+---------------+------------+----------------+ -; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ; -+----------------------+------------------+---------------+------------+----------------+ -; Analysis & Synthesis ; Vaio ; Windows Vista ; 6.1 ; x86_64 ; -+----------------------+------------------+---------------+------------+----------------+ - - ------------- -; Flow Log ; ------------- -quartus_map --read_settings_files=on --write_settings_files=off firebeei1 -c firebee1 - - - diff --git a/FPGA_by_Fredi/firebee1.map.summary b/FPGA_by_Fredi/firebee1.map.summary deleted file mode 100644 index aa8c768..0000000 --- a/FPGA_by_Fredi/firebee1.map.summary +++ /dev/null @@ -1,14 +0,0 @@ -Analysis & Synthesis Status : Successful - Sat Apr 15 23:46:35 2017 -Quartus II Version : 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition -Revision Name : firebee1 -Top-level Entity Name : firebee1 -Family : Cyclone III -Total logic elements : 22,593 - Total combinational functions : 19,050 - Dedicated logic registers : 5,711 -Total registers : 5839 -Total pins : 296 -Total virtual pins : 0 -Total memory bits : 355,360 -Embedded Multiplier 9-bit elements : 12 -Total PLLs : 4 diff --git a/FPGA_by_Fredi/firebee1.rbf b/FPGA_by_Fredi/firebee1.rbf new file mode 100644 index 0000000..57fa441 Binary files /dev/null and b/FPGA_by_Fredi/firebee1.rbf differ diff --git a/FPGA_by_Fredi/firebee1.sim.rpt b/FPGA_by_Fredi/firebee1.sim.rpt deleted file mode 100644 index 6bfa8c3..0000000 --- a/FPGA_by_Fredi/firebee1.sim.rpt +++ /dev/null @@ -1,247 +0,0 @@ -Simulator report for firebee1 -Fri Mar 10 13:17:46 2017 -Quartus II Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition - - ---------------------- -; Table of Contents ; ---------------------- - 1. Legal Notice - 2. Simulator Summary - 3. Simulator Settings - 4. Simulation Waveforms - 5. |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ALTSYNCRAM - 6. |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ALTSYNCRAM - 7. |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ALTSYNCRAM - 8. |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ALTSYNCRAM - 9. |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|ALTSYNCRAM - 10. |firebee1|Video:Fredi_Aschwanden|BLITTER:BLITTER|altsyncram0:$00000|altsyncram:altsyncram_component|altsyncram_3on1:auto_generated|ALTSYNCRAM - 11. |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ALTSYNCRAM - 12. |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ALTSYNCRAM - 13. |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ALTSYNCRAM - 14. |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ALTSYNCRAM - 15. |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ALTSYNCRAM - 16. |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ALTSYNCRAM - 17. |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4|altsyncram_46r:auto_generated|ALTSYNCRAM - 18. |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ALTSYNCRAM - 19. |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ALTSYNCRAM - 20. Coverage Summary - 21. Complete 1/0-Value Coverage - 22. Missing 1-Value Coverage - 23. Missing 0-Value Coverage - 24. Simulator INI Usage - 25. Simulator Messages - - - ----------------- -; Legal Notice ; ----------------- -Copyright (C) 1991-2010 Altera Corporation -Your use of Altera Corporation's design tools, logic functions -and other software and tools, and its AMPP partner logic -functions, and any output files from any of the foregoing -(including device programming or simulation files), and any -associated documentation or information are expressly subject -to the terms and conditions of the Altera Program License -Subscription Agreement, Altera MegaCore Function License -Agreement, or other applicable license agreement, including, -without limitation, that your use is for the sole purpose of -programming logic devices manufactured by Altera and sold by -Altera or its authorized distributors. Please refer to the -applicable agreement for further details. - - - -+-------------------+ -; Simulator Summary ; -+------+------------+ -; Type ; Value ; -+------+------------+ - - -+---------------------------------------------------------------------------------------------------------------------------+ -; Simulator Settings ; -+--------------------------------------------------------------------------------------------+--------------+---------------+ -; Option ; Setting ; Default Value ; -+--------------------------------------------------------------------------------------------+--------------+---------------+ -; Simulation mode ; Timing ; Timing ; -; Start time ; 0 ns ; 0 ns ; -; End time ; 2 us ; ; -; Simulation results format ; CVWF ; ; -; Vector input source ; firebee1.vwf ; ; -; Add pins automatically to simulation output waveforms ; Off ; On ; -; Check outputs ; Off ; Off ; -; Report simulation coverage ; On ; On ; -; Display complete 1/0 value coverage report ; On ; On ; -; Display missing 1-value coverage report ; On ; On ; -; Display missing 0-value coverage report ; On ; On ; -; Detect setup and hold time violations ; Off ; Off ; -; Detect glitches ; Off ; Off ; -; Disable timing delays in Timing Simulation ; Off ; Off ; -; Generate Signal Activity File ; Off ; Off ; -; Generate VCD File for PowerPlay Power Analyzer ; Off ; Off ; -; Group bus channels in simulation results ; Off ; Off ; -; Preserve fewer signal transitions to reduce memory requirements ; On ; On ; -; Trigger vector comparison with the specified mode ; INPUT_EDGE ; INPUT_EDGE ; -; Disable setup and hold time violations detection in input registers of bi-directional pins ; Off ; Off ; -; Overwrite Waveform Inputs With Simulation Outputs ; Off ; ; -; Perform Glitch Filtering in Timing Simulation ; Auto ; Auto ; -; Interconnect Delay Model Type ; Transport ; Transport ; -; Cell Delay Model Type ; Transport ; Transport ; -+--------------------------------------------------------------------------------------------+--------------+---------------+ - - -+----------------------+ -; Simulation Waveforms ; -+----------------------+ -Waveform report data cannot be output to ASCII. -Please use Quartus II to view the waveform report data. - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ALTSYNCRAM ; -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Please refer to fitter text-based report (*.fit.rpt) to view logical memory report content in ASCII. - - -+-----------------------------------------------------------------------------------------------------------------------------------+ -; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ALTSYNCRAM ; -+-----------------------------------------------------------------------------------------------------------------------------------+ -Please refer to fitter text-based report (*.fit.rpt) to view logical memory report content in ASCII. - - -+------------------------------------------------------------------------------------------------------------------------------------+ -; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ALTSYNCRAM ; -+------------------------------------------------------------------------------------------------------------------------------------+ -Please refer to fitter text-based report (*.fit.rpt) to view logical memory report content in ASCII. - - -+-------------------------------------------------------------------------------------------------------------------------------------+ -; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM55|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ALTSYNCRAM ; -+-------------------------------------------------------------------------------------------------------------------------------------+ -Please refer to fitter text-based report (*.fit.rpt) to view logical memory report content in ASCII. - - -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; |firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|ALTSYNCRAM ; -+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Please refer to fitter text-based report (*.fit.rpt) to view logical memory report content in ASCII. - - -+-----------------------------------------------------------------------------------------------------------------------------------------------+ -; |firebee1|Video:Fredi_Aschwanden|BLITTER:BLITTER|altsyncram0:$00000|altsyncram:altsyncram_component|altsyncram_3on1:auto_generated|ALTSYNCRAM ; -+-----------------------------------------------------------------------------------------------------------------------------------------------+ -Please refer to fitter text-based report (*.fit.rpt) to view logical memory report content in ASCII. - - -+----------------------------------------------------------------------------------------------------------------------------------------+ -; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_GREEN|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ALTSYNCRAM ; -+----------------------------------------------------------------------------------------------------------------------------------------+ -Please refer to fitter text-based report (*.fit.rpt) to view logical memory report content in ASCII. - - -+---------------------------------------------------------------------------------------------------------------------------------------+ -; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_BLUE|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ALTSYNCRAM ; -+---------------------------------------------------------------------------------------------------------------------------------------+ -Please refer to fitter text-based report (*.fit.rpt) to view logical memory report content in ASCII. - - -+--------------------------------------------------------------------------------------------------------------------------------------+ -; |firebee1|Video:Fredi_Aschwanden|altdpram1:FALCON_CLUT_RED|altsyncram:altsyncram_component|altsyncram_lf92:auto_generated|ALTSYNCRAM ; -+--------------------------------------------------------------------------------------------------------------------------------------+ -Please refer to fitter text-based report (*.fit.rpt) to view logical memory report content in ASCII. - - -+----------------------------------------------------------------------------------------------------------------------------------+ -; |firebee1|Video:Fredi_Aschwanden|altdpram0:ST_CLUT_RED|altsyncram:altsyncram_component|altsyncram_rb92:auto_generated|ALTSYNCRAM ; -+----------------------------------------------------------------------------------------------------------------------------------+ -Please refer to fitter text-based report (*.fit.rpt) to view logical memory report content in ASCII. - - -+-------------------------------------------------------------------------------------------------------------------------------------+ -; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM54|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ALTSYNCRAM ; -+-------------------------------------------------------------------------------------------------------------------------------------+ -Please refer to fitter text-based report (*.fit.rpt) to view logical memory report content in ASCII. - - -+-----------------------------------------------------------------------------------------------------------------------------------+ -; |firebee1|Video:Fredi_Aschwanden|altdpram2:ACP_CLUT_RAM|altsyncram:altsyncram_component|altsyncram_pf92:auto_generated|ALTSYNCRAM ; -+-----------------------------------------------------------------------------------------------------------------------------------+ -Please refer to fitter text-based report (*.fit.rpt) to view logical memory report content in ASCII. - - -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; |firebee1|altpll_reconfig1:inst7|altpll_reconfig1_pllrcfg_t4q:altpll_reconfig1_pllrcfg_t4q_component|altsyncram:altsyncram4|altsyncram_46r:auto_generated|ALTSYNCRAM ; -+----------------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Please refer to fitter text-based report (*.fit.rpt) to view logical memory report content in ASCII. - - -+-------------------------------------------------------------------------------------------------------------------------------------------+ -; |firebee1|Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_8fi1:auto_generated|altsyncram_tl31:fifo_ram|ALTSYNCRAM ; -+-------------------------------------------------------------------------------------------------------------------------------------------+ -Please refer to fitter text-based report (*.fit.rpt) to view logical memory report content in ASCII. - - -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -; |firebee1|Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_lk21:auto_generated|a_dpfifo_oq21:dpfifo|altsyncram_gj81:FIFOram|ALTSYNCRAM ; -+---------------------------------------------------------------------------------------------------------------------------------------------------------------+ -Please refer to fitter text-based report (*.fit.rpt) to view logical memory report content in ASCII. - - -+------------------+ -; Coverage Summary ; -+------+-----------+ -; Type ; Value ; -+------+-----------+ - - -The following table displays output ports that toggle between 1 and 0 during simulation. -+-------------------------------------------------+ -; Complete 1/0-Value Coverage ; -+-----------+------------------+------------------+ -; Node Name ; Output Port Name ; Output Port Type ; -+-----------+------------------+------------------+ - - -The following table displays output ports that do not toggle to 1 during simulation. -+-------------------------------------------------+ -; Missing 1-Value Coverage ; -+-----------+------------------+------------------+ -; Node Name ; Output Port Name ; Output Port Type ; -+-----------+------------------+------------------+ - - -The following table displays output ports that do not toggle to 0 during simulation. -+-------------------------------------------------+ -; Missing 0-Value Coverage ; -+-----------+------------------+------------------+ -; Node Name ; Output Port Name ; Output Port Type ; -+-----------+------------------+------------------+ - - -+---------------------+ -; Simulator INI Usage ; -+--------+------------+ -; Option ; Usage ; -+--------+------------+ - - -+--------------------+ -; Simulator Messages ; -+--------------------+ -Info: ******************************************************************* -Info: Running Quartus II Simulator - Info: Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition - Info: Processing started: Fri Mar 10 13:17:43 2017 -Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off firebeei1 -c firebee1 -Info: Can't find specified vector source file "C:/FireBee/FPGA/firebee1.vwf" -Warning: Can't display state machine states -- register holding state machine bit "|firebee1|FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF1772IP_TOP_SOC:I_FDC|WF1772IP_TRANSCEIVER:I_TRANSCEIVER|MFM_STATE.A_00" was synthesized away -Error: No valid vector source file specified and default file "C:/FireBee/FPGA/firebee1.cvwf" does not exist -Error: Quartus II Simulator was unsuccessful. 1 error, 1 warning - Error: Peak virtual memory: 241 megabytes - Error: Processing ended: Fri Mar 10 13:17:46 2017 - Error: Elapsed time: 00:00:03 - Error: Total CPU time (on all processors): 00:00:03 - - diff --git a/FPGA_by_Fredi/firebee1.sta.summary b/FPGA_by_Fredi/firebee1.sta.summary deleted file mode 100644 index 08274d1..0000000 --- a/FPGA_by_Fredi/firebee1.sta.summary +++ /dev/null @@ -1,857 +0,0 @@ ------------------------------------------------------------- -TimeQuest Timing Analyzer Summary ------------------------------------------------------------- - -Type : Slow 1200mV 85C Model Setup 'inst22|altpll_component|auto_generated|pll1|clk[0]' -Slack : -17.450 -TNS : -16147.437 - -Type : Slow 1200mV 85C Model Setup 'inst13|altpll_component|auto_generated|pll1|clk[2]' -Slack : -7.331 -TNS : -4287.365 - -Type : Slow 1200mV 85C Model Setup 'inst12|altpll_component|auto_generated|pll1|clk[0]' -Slack : -4.994 -TNS : -47.649 - -Type : Slow 1200mV 85C Model Setup 'inst13|altpll_component|auto_generated|pll1|clk[1]' -Slack : -4.588 -TNS : -478.150 - -Type : Slow 1200mV 85C Model Setup 'MAIN_CLK' -Slack : -4.230 -TNS : -5479.268 - -Type : Slow 1200mV 85C Model Setup 'inst12|altpll_component|auto_generated|pll1|clk[3]' -Slack : 2.377 -TNS : 0.000 - -Type : Slow 1200mV 85C Model Setup 'inst12|altpll_component|auto_generated|pll1|clk[1]' -Slack : 2.892 -TNS : 0.000 - -Type : Slow 1200mV 85C Model Setup 'inst12|altpll_component|auto_generated|pll1|clk[4]' -Slack : 3.750 -TNS : 0.000 - -Type : Slow 1200mV 85C Model Setup 'inst12|altpll_component|auto_generated|pll1|clk[2]' -Slack : 5.312 -TNS : 0.000 - -Type : Slow 1200mV 85C Model Setup 'inst13|altpll_component|auto_generated|pll1|clk[0]' -Slack : 497.531 -TNS : 0.000 - -Type : Slow 1200mV 85C Model Setup 'inst13|altpll_component|auto_generated|pll1|clk[3]' -Slack : 1997.881 -TNS : 0.000 - -Type : Slow 1200mV 85C Model Hold 'inst13|altpll_component|auto_generated|pll1|clk[2]' -Slack : -11.047 -TNS : -9871.573 - -Type : Slow 1200mV 85C Model Hold 'MAIN_CLK' -Slack : -10.882 -TNS : -9731.628 - -Type : Slow 1200mV 85C Model Hold 'inst12|altpll_component|auto_generated|pll1|clk[0]' -Slack : -5.940 -TNS : -5.940 - -Type : Slow 1200mV 85C Model Hold 'inst13|altpll_component|auto_generated|pll1|clk[1]' -Slack : 0.283 -TNS : 0.000 - -Type : Slow 1200mV 85C Model Hold 'inst22|altpll_component|auto_generated|pll1|clk[0]' -Slack : 0.342 -TNS : 0.000 - -Type : Slow 1200mV 85C Model Hold 'inst13|altpll_component|auto_generated|pll1|clk[0]' -Slack : 0.376 -TNS : 0.000 - -Type : Slow 1200mV 85C Model Hold 'inst13|altpll_component|auto_generated|pll1|clk[3]' -Slack : 0.389 -TNS : 0.000 - -Type : Slow 1200mV 85C Model Hold 'inst12|altpll_component|auto_generated|pll1|clk[2]' -Slack : 1.541 -TNS : 0.000 - -Type : Slow 1200mV 85C Model Hold 'inst12|altpll_component|auto_generated|pll1|clk[3]' -Slack : 2.366 -TNS : 0.000 - -Type : Slow 1200mV 85C Model Hold 'inst12|altpll_component|auto_generated|pll1|clk[4]' -Slack : 3.005 -TNS : 0.000 - -Type : Slow 1200mV 85C Model Hold 'inst12|altpll_component|auto_generated|pll1|clk[1]' -Slack : 4.128 -TNS : 0.000 - -Type : Slow 1200mV 85C Model Recovery 'inst22|altpll_component|auto_generated|pll1|clk[0]' -Slack : -15.674 -TNS : -2798.000 - -Type : Slow 1200mV 85C Model Recovery 'inst12|altpll_component|auto_generated|pll1|clk[0]' -Slack : -8.406 -TNS : -16.812 - -Type : Slow 1200mV 85C Model Recovery 'inst13|altpll_component|auto_generated|pll1|clk[2]' -Slack : -4.536 -TNS : -782.022 - -Type : Slow 1200mV 85C Model Recovery 'inst13|altpll_component|auto_generated|pll1|clk[1]' -Slack : -4.460 -TNS : -652.825 - -Type : Slow 1200mV 85C Model Recovery 'MAIN_CLK' -Slack : -3.788 -TNS : -646.634 - -Type : Slow 1200mV 85C Model Recovery 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC' -Slack : -2.802 -TNS : -2.802 - -Type : Slow 1200mV 85C Model Recovery 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC' -Slack : -1.533 -TNS : -1.533 - -Type : Slow 1200mV 85C Model Recovery 'DVI_INT' -Slack : -0.826 -TNS : -0.826 - -Type : Slow 1200mV 85C Model Recovery 'E0_INT' -Slack : -0.766 -TNS : -0.766 - -Type : Slow 1200mV 85C Model Recovery 'nPCI_INTA' -Slack : -0.281 -TNS : -0.281 - -Type : Slow 1200mV 85C Model Recovery 'nPCI_INTD' -Slack : -0.267 -TNS : -0.267 - -Type : Slow 1200mV 85C Model Recovery 'nPCI_INTC' -Slack : -0.249 -TNS : -0.249 - -Type : Slow 1200mV 85C Model Recovery 'nPCI_INTB' -Slack : -0.188 -TNS : -0.188 - -Type : Slow 1200mV 85C Model Recovery 'PIC_INT' -Slack : -0.038 -TNS : -0.038 - -Type : Slow 1200mV 85C Model Removal 'inst13|altpll_component|auto_generated|pll1|clk[2]' -Slack : -10.353 -TNS : -1430.734 - -Type : Slow 1200mV 85C Model Removal 'MAIN_CLK' -Slack : -10.188 -TNS : -1400.869 - -Type : Slow 1200mV 85C Model Removal 'inst12|altpll_component|auto_generated|pll1|clk[0]' -Slack : -2.755 -TNS : -5.510 - -Type : Slow 1200mV 85C Model Removal 'PIC_INT' -Slack : -0.526 -TNS : -0.526 - -Type : Slow 1200mV 85C Model Removal 'nPCI_INTB' -Slack : -0.361 -TNS : -0.361 - -Type : Slow 1200mV 85C Model Removal 'nPCI_INTC' -Slack : -0.295 -TNS : -0.295 - -Type : Slow 1200mV 85C Model Removal 'nPCI_INTD' -Slack : -0.274 -TNS : -0.274 - -Type : Slow 1200mV 85C Model Removal 'nPCI_INTA' -Slack : -0.256 -TNS : -0.256 - -Type : Slow 1200mV 85C Model Removal 'E0_INT' -Slack : 0.237 -TNS : 0.000 - -Type : Slow 1200mV 85C Model Removal 'DVI_INT' -Slack : 0.299 -TNS : 0.000 - -Type : Slow 1200mV 85C Model Removal 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC' -Slack : 1.026 -TNS : 0.000 - -Type : Slow 1200mV 85C Model Removal 'inst22|altpll_component|auto_generated|pll1|clk[0]' -Slack : 1.036 -TNS : 0.000 - -Type : Slow 1200mV 85C Model Removal 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC' -Slack : 2.350 -TNS : 0.000 - -Type : Slow 1200mV 85C Model Removal 'inst13|altpll_component|auto_generated|pll1|clk[1]' -Slack : 3.015 -TNS : 0.000 - -Type : Slow 1200mV 85C Model Minimum Pulse Width 'PIC_INT' -Slack : -3.000 -TNS : -4.134 - -Type : Slow 1200mV 85C Model Minimum Pulse Width 'nPCI_INTB' -Slack : -3.000 -TNS : -4.079 - -Type : Slow 1200mV 85C Model Minimum Pulse Width 'nPCI_INTD' -Slack : -3.000 -TNS : -4.070 - -Type : Slow 1200mV 85C Model Minimum Pulse Width 'nPCI_INTC' -Slack : -3.000 -TNS : -4.050 - -Type : Slow 1200mV 85C Model Minimum Pulse Width 'nPCI_INTA' -Slack : -3.000 -TNS : -4.038 - -Type : Slow 1200mV 85C Model Minimum Pulse Width 'DVI_INT' -Slack : -3.000 -TNS : -4.000 - -Type : Slow 1200mV 85C Model Minimum Pulse Width 'E0_INT' -Slack : -3.000 -TNS : -4.000 - -Type : Slow 1200mV 85C Model Minimum Pulse Width 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC' -Slack : -1.000 -TNS : -1.000 - -Type : Slow 1200mV 85C Model Minimum Pulse Width 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC' -Slack : -1.000 -TNS : -1.000 - -Type : Slow 1200mV 85C Model Minimum Pulse Width 'inst12|altpll_component|auto_generated|pll1|clk[0]' -Slack : 3.527 -TNS : 0.000 - -Type : Slow 1200mV 85C Model Minimum Pulse Width 'inst12|altpll_component|auto_generated|pll1|clk[1]' -Slack : 3.533 -TNS : 0.000 - -Type : Slow 1200mV 85C Model Minimum Pulse Width 'inst12|altpll_component|auto_generated|pll1|clk[2]' -Slack : 3.533 -TNS : 0.000 - -Type : Slow 1200mV 85C Model Minimum Pulse Width 'inst12|altpll_component|auto_generated|pll1|clk[3]' -Slack : 3.533 -TNS : 0.000 - -Type : Slow 1200mV 85C Model Minimum Pulse Width 'inst22|altpll_component|auto_generated|pll1|clk[0]' -Slack : 4.811 -TNS : 0.000 - -Type : Slow 1200mV 85C Model Minimum Pulse Width 'inst12|altpll_component|auto_generated|pll1|clk[4]' -Slack : 7.320 -TNS : 0.000 - -Type : Slow 1200mV 85C Model Minimum Pulse Width 'inst|altpll_component|auto_generated|pll1|clk[3]' -Slack : 10.398 -TNS : 0.000 - -Type : Slow 1200mV 85C Model Minimum Pulse Width 'MAIN_CLK' -Slack : 13.528 -TNS : 0.000 - -Type : Slow 1200mV 85C Model Minimum Pulse Width 'inst13|altpll_component|auto_generated|pll1|clk[2]' -Slack : 18.585 -TNS : 0.000 - -Type : Slow 1200mV 85C Model Minimum Pulse Width 'inst13|altpll_component|auto_generated|pll1|clk[1]' -Slack : 30.973 -TNS : 0.000 - -Type : Slow 1200mV 85C Model Minimum Pulse Width 'inst13|altpll_component|auto_generated|pll1|clk[0]' -Slack : 249.617 -TNS : 0.000 - -Type : Slow 1200mV 85C Model Minimum Pulse Width 'inst13|altpll_component|auto_generated|pll1|clk[3]' -Slack : 999.882 -TNS : 0.000 - -Type : Slow 1200mV 0C Model Setup 'inst22|altpll_component|auto_generated|pll1|clk[0]' -Slack : -15.403 -TNS : -14377.209 - -Type : Slow 1200mV 0C Model Setup 'inst13|altpll_component|auto_generated|pll1|clk[2]' -Slack : -6.421 -TNS : -3676.693 - -Type : Slow 1200mV 0C Model Setup 'inst12|altpll_component|auto_generated|pll1|clk[0]' -Slack : -4.520 -TNS : -37.132 - -Type : Slow 1200mV 0C Model Setup 'inst13|altpll_component|auto_generated|pll1|clk[1]' -Slack : -4.094 -TNS : -426.105 - -Type : Slow 1200mV 0C Model Setup 'MAIN_CLK' -Slack : -3.696 -TNS : -4132.088 - -Type : Slow 1200mV 0C Model Setup 'inst12|altpll_component|auto_generated|pll1|clk[3]' -Slack : 2.718 -TNS : 0.000 - -Type : Slow 1200mV 0C Model Setup 'inst12|altpll_component|auto_generated|pll1|clk[1]' -Slack : 2.995 -TNS : 0.000 - -Type : Slow 1200mV 0C Model Setup 'inst12|altpll_component|auto_generated|pll1|clk[4]' -Slack : 3.994 -TNS : 0.000 - -Type : Slow 1200mV 0C Model Setup 'inst12|altpll_component|auto_generated|pll1|clk[2]' -Slack : 5.426 -TNS : 0.000 - -Type : Slow 1200mV 0C Model Setup 'inst13|altpll_component|auto_generated|pll1|clk[0]' -Slack : 497.772 -TNS : 0.000 - -Type : Slow 1200mV 0C Model Setup 'inst13|altpll_component|auto_generated|pll1|clk[3]' -Slack : 1998.168 -TNS : 0.000 - -Type : Slow 1200mV 0C Model Hold 'inst13|altpll_component|auto_generated|pll1|clk[2]' -Slack : -9.832 -TNS : -8727.393 - -Type : Slow 1200mV 0C Model Hold 'MAIN_CLK' -Slack : -9.617 -TNS : -8529.400 - -Type : Slow 1200mV 0C Model Hold 'inst12|altpll_component|auto_generated|pll1|clk[0]' -Slack : -5.065 -TNS : -5.065 - -Type : Slow 1200mV 0C Model Hold 'inst13|altpll_component|auto_generated|pll1|clk[1]' -Slack : 0.254 -TNS : 0.000 - -Type : Slow 1200mV 0C Model Hold 'inst22|altpll_component|auto_generated|pll1|clk[0]' -Slack : 0.297 -TNS : 0.000 - -Type : Slow 1200mV 0C Model Hold 'inst13|altpll_component|auto_generated|pll1|clk[0]' -Slack : 0.335 -TNS : 0.000 - -Type : Slow 1200mV 0C Model Hold 'inst13|altpll_component|auto_generated|pll1|clk[3]' -Slack : 0.346 -TNS : 0.000 - -Type : Slow 1200mV 0C Model Hold 'inst12|altpll_component|auto_generated|pll1|clk[2]' -Slack : 1.517 -TNS : 0.000 - -Type : Slow 1200mV 0C Model Hold 'inst12|altpll_component|auto_generated|pll1|clk[3]' -Slack : 2.163 -TNS : 0.000 - -Type : Slow 1200mV 0C Model Hold 'inst12|altpll_component|auto_generated|pll1|clk[4]' -Slack : 2.766 -TNS : 0.000 - -Type : Slow 1200mV 0C Model Hold 'inst12|altpll_component|auto_generated|pll1|clk[1]' -Slack : 4.082 -TNS : 0.000 - -Type : Slow 1200mV 0C Model Recovery 'inst22|altpll_component|auto_generated|pll1|clk[0]' -Slack : -13.902 -TNS : -2482.848 - -Type : Slow 1200mV 0C Model Recovery 'inst12|altpll_component|auto_generated|pll1|clk[0]' -Slack : -7.532 -TNS : -15.064 - -Type : Slow 1200mV 0C Model Recovery 'inst13|altpll_component|auto_generated|pll1|clk[1]' -Slack : -3.927 -TNS : -573.408 - -Type : Slow 1200mV 0C Model Recovery 'inst13|altpll_component|auto_generated|pll1|clk[2]' -Slack : -3.851 -TNS : -663.617 - -Type : Slow 1200mV 0C Model Recovery 'MAIN_CLK' -Slack : -3.223 -TNS : -549.949 - -Type : Slow 1200mV 0C Model Recovery 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC' -Slack : -2.555 -TNS : -2.555 - -Type : Slow 1200mV 0C Model Recovery 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC' -Slack : -1.377 -TNS : -1.377 - -Type : Slow 1200mV 0C Model Recovery 'DVI_INT' -Slack : -0.706 -TNS : -0.706 - -Type : Slow 1200mV 0C Model Recovery 'E0_INT' -Slack : -0.653 -TNS : -0.653 - -Type : Slow 1200mV 0C Model Recovery 'nPCI_INTA' -Slack : -0.192 -TNS : -0.192 - -Type : Slow 1200mV 0C Model Recovery 'nPCI_INTD' -Slack : -0.190 -TNS : -0.190 - -Type : Slow 1200mV 0C Model Recovery 'nPCI_INTC' -Slack : -0.180 -TNS : -0.180 - -Type : Slow 1200mV 0C Model Recovery 'nPCI_INTB' -Slack : -0.104 -TNS : -0.104 - -Type : Slow 1200mV 0C Model Recovery 'PIC_INT' -Slack : 0.013 -TNS : 0.000 - -Type : Slow 1200mV 0C Model Removal 'inst13|altpll_component|auto_generated|pll1|clk[2]' -Slack : -9.193 -TNS : -1262.369 - -Type : Slow 1200mV 0C Model Removal 'MAIN_CLK' -Slack : -8.978 -TNS : -1223.454 - -Type : Slow 1200mV 0C Model Removal 'inst12|altpll_component|auto_generated|pll1|clk[0]' -Slack : -2.195 -TNS : -4.390 - -Type : Slow 1200mV 0C Model Removal 'PIC_INT' -Slack : -0.527 -TNS : -0.527 - -Type : Slow 1200mV 0C Model Removal 'nPCI_INTB' -Slack : -0.384 -TNS : -0.384 - -Type : Slow 1200mV 0C Model Removal 'nPCI_INTC' -Slack : -0.316 -TNS : -0.316 - -Type : Slow 1200mV 0C Model Removal 'nPCI_INTD' -Slack : -0.288 -TNS : -0.288 - -Type : Slow 1200mV 0C Model Removal 'nPCI_INTA' -Slack : -0.283 -TNS : -0.283 - -Type : Slow 1200mV 0C Model Removal 'E0_INT' -Slack : 0.170 -TNS : 0.000 - -Type : Slow 1200mV 0C Model Removal 'DVI_INT' -Slack : 0.223 -TNS : 0.000 - -Type : Slow 1200mV 0C Model Removal 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC' -Slack : 0.914 -TNS : 0.000 - -Type : Slow 1200mV 0C Model Removal 'inst22|altpll_component|auto_generated|pll1|clk[0]' -Slack : 0.936 -TNS : 0.000 - -Type : Slow 1200mV 0C Model Removal 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC' -Slack : 2.150 -TNS : 0.000 - -Type : Slow 1200mV 0C Model Removal 'inst13|altpll_component|auto_generated|pll1|clk[1]' -Slack : 2.663 -TNS : 0.000 - -Type : Slow 1200mV 0C Model Minimum Pulse Width 'PIC_INT' -Slack : -3.000 -TNS : -4.036 - -Type : Slow 1200mV 0C Model Minimum Pulse Width 'nPCI_INTB' -Slack : -3.000 -TNS : -4.036 - -Type : Slow 1200mV 0C Model Minimum Pulse Width 'nPCI_INTD' -Slack : -3.000 -TNS : -4.012 - -Type : Slow 1200mV 0C Model Minimum Pulse Width 'nPCI_INTA' -Slack : -3.000 -TNS : -4.002 - -Type : Slow 1200mV 0C Model Minimum Pulse Width 'DVI_INT' -Slack : -3.000 -TNS : -4.000 - -Type : Slow 1200mV 0C Model Minimum Pulse Width 'E0_INT' -Slack : -3.000 -TNS : -4.000 - -Type : Slow 1200mV 0C Model Minimum Pulse Width 'nPCI_INTC' -Slack : -3.000 -TNS : -4.000 - -Type : Slow 1200mV 0C Model Minimum Pulse Width 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC' -Slack : -1.000 -TNS : -1.000 - -Type : Slow 1200mV 0C Model Minimum Pulse Width 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC' -Slack : -1.000 -TNS : -1.000 - -Type : Slow 1200mV 0C Model Minimum Pulse Width 'inst12|altpll_component|auto_generated|pll1|clk[0]' -Slack : 3.517 -TNS : 0.000 - -Type : Slow 1200mV 0C Model Minimum Pulse Width 'inst12|altpll_component|auto_generated|pll1|clk[2]' -Slack : 3.528 -TNS : 0.000 - -Type : Slow 1200mV 0C Model Minimum Pulse Width 'inst12|altpll_component|auto_generated|pll1|clk[1]' -Slack : 3.529 -TNS : 0.000 - -Type : Slow 1200mV 0C Model Minimum Pulse Width 'inst12|altpll_component|auto_generated|pll1|clk[3]' -Slack : 3.529 -TNS : 0.000 - -Type : Slow 1200mV 0C Model Minimum Pulse Width 'inst22|altpll_component|auto_generated|pll1|clk[0]' -Slack : 4.909 -TNS : 0.000 - -Type : Slow 1200mV 0C Model Minimum Pulse Width 'inst12|altpll_component|auto_generated|pll1|clk[4]' -Slack : 7.316 -TNS : 0.000 - -Type : Slow 1200mV 0C Model Minimum Pulse Width 'inst|altpll_component|auto_generated|pll1|clk[3]' -Slack : 10.392 -TNS : 0.000 - -Type : Slow 1200mV 0C Model Minimum Pulse Width 'MAIN_CLK' -Slack : 13.634 -TNS : 0.000 - -Type : Slow 1200mV 0C Model Minimum Pulse Width 'inst13|altpll_component|auto_generated|pll1|clk[2]' -Slack : 18.774 -TNS : 0.000 - -Type : Slow 1200mV 0C Model Minimum Pulse Width 'inst13|altpll_component|auto_generated|pll1|clk[1]' -Slack : 30.967 -TNS : 0.000 - -Type : Slow 1200mV 0C Model Minimum Pulse Width 'inst13|altpll_component|auto_generated|pll1|clk[0]' -Slack : 249.612 -TNS : 0.000 - -Type : Slow 1200mV 0C Model Minimum Pulse Width 'inst13|altpll_component|auto_generated|pll1|clk[3]' -Slack : 999.877 -TNS : 0.000 - -Type : Fast 1200mV 0C Model Setup 'inst22|altpll_component|auto_generated|pll1|clk[0]' -Slack : -9.748 -TNS : -9757.013 - -Type : Fast 1200mV 0C Model Setup 'inst13|altpll_component|auto_generated|pll1|clk[2]' -Slack : -3.484 -TNS : -1911.267 - -Type : Fast 1200mV 0C Model Setup 'inst12|altpll_component|auto_generated|pll1|clk[0]' -Slack : -2.773 -TNS : -9.357 - -Type : Fast 1200mV 0C Model Setup 'inst13|altpll_component|auto_generated|pll1|clk[1]' -Slack : -2.483 -TNS : -260.497 - -Type : Fast 1200mV 0C Model Setup 'MAIN_CLK' -Slack : -1.767 -TNS : -1399.694 - -Type : Fast 1200mV 0C Model Setup 'inst12|altpll_component|auto_generated|pll1|clk[1]' -Slack : 3.283 -TNS : 0.000 - -Type : Fast 1200mV 0C Model Setup 'inst12|altpll_component|auto_generated|pll1|clk[3]' -Slack : 3.689 -TNS : 0.000 - -Type : Fast 1200mV 0C Model Setup 'inst12|altpll_component|auto_generated|pll1|clk[4]' -Slack : 4.868 -TNS : 0.000 - -Type : Fast 1200mV 0C Model Setup 'inst12|altpll_component|auto_generated|pll1|clk[2]' -Slack : 5.744 -TNS : 0.000 - -Type : Fast 1200mV 0C Model Setup 'inst13|altpll_component|auto_generated|pll1|clk[0]' -Slack : 498.517 -TNS : 0.000 - -Type : Fast 1200mV 0C Model Setup 'inst13|altpll_component|auto_generated|pll1|clk[3]' -Slack : 1998.908 -TNS : 0.000 - -Type : Fast 1200mV 0C Model Hold 'inst13|altpll_component|auto_generated|pll1|clk[2]' -Slack : -6.775 -TNS : -6188.069 - -Type : Fast 1200mV 0C Model Hold 'MAIN_CLK' -Slack : -6.521 -TNS : -5940.597 - -Type : Fast 1200mV 0C Model Hold 'inst12|altpll_component|auto_generated|pll1|clk[0]' -Slack : -3.440 -TNS : -3.440 - -Type : Fast 1200mV 0C Model Hold 'inst13|altpll_component|auto_generated|pll1|clk[1]' -Slack : 0.136 -TNS : 0.000 - -Type : Fast 1200mV 0C Model Hold 'inst22|altpll_component|auto_generated|pll1|clk[0]' -Slack : 0.178 -TNS : 0.000 - -Type : Fast 1200mV 0C Model Hold 'inst13|altpll_component|auto_generated|pll1|clk[0]' -Slack : 0.197 -TNS : 0.000 - -Type : Fast 1200mV 0C Model Hold 'inst13|altpll_component|auto_generated|pll1|clk[3]' -Slack : 0.204 -TNS : 0.000 - -Type : Fast 1200mV 0C Model Hold 'inst12|altpll_component|auto_generated|pll1|clk[3]' -Slack : 1.296 -TNS : 0.000 - -Type : Fast 1200mV 0C Model Hold 'inst12|altpll_component|auto_generated|pll1|clk[2]' -Slack : 1.392 -TNS : 0.000 - -Type : Fast 1200mV 0C Model Hold 'inst12|altpll_component|auto_generated|pll1|clk[4]' -Slack : 1.655 -TNS : 0.000 - -Type : Fast 1200mV 0C Model Hold 'inst12|altpll_component|auto_generated|pll1|clk[1]' -Slack : 3.971 -TNS : 0.000 - -Type : Fast 1200mV 0C Model Recovery 'inst22|altpll_component|auto_generated|pll1|clk[0]' -Slack : -9.449 -TNS : -1688.035 - -Type : Fast 1200mV 0C Model Recovery 'inst12|altpll_component|auto_generated|pll1|clk[0]' -Slack : -4.842 -TNS : -9.684 - -Type : Fast 1200mV 0C Model Recovery 'inst13|altpll_component|auto_generated|pll1|clk[1]' -Slack : -2.521 -TNS : -370.829 - -Type : Fast 1200mV 0C Model Recovery 'inst13|altpll_component|auto_generated|pll1|clk[2]' -Slack : -2.077 -TNS : -353.703 - -Type : Fast 1200mV 0C Model Recovery 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC' -Slack : -1.593 -TNS : -1.593 - -Type : Fast 1200mV 0C Model Recovery 'MAIN_CLK' -Slack : -1.560 -TNS : -261.778 - -Type : Fast 1200mV 0C Model Recovery 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC' -Slack : -0.866 -TNS : -0.866 - -Type : Fast 1200mV 0C Model Recovery 'DVI_INT' -Slack : -0.475 -TNS : -0.475 - -Type : Fast 1200mV 0C Model Recovery 'E0_INT' -Slack : -0.438 -TNS : -0.438 - -Type : Fast 1200mV 0C Model Recovery 'PIC_INT' -Slack : -0.086 -TNS : -0.086 - -Type : Fast 1200mV 0C Model Recovery 'nPCI_INTA' -Slack : 0.253 -TNS : 0.000 - -Type : Fast 1200mV 0C Model Recovery 'nPCI_INTC' -Slack : 0.262 -TNS : 0.000 - -Type : Fast 1200mV 0C Model Recovery 'nPCI_INTD' -Slack : 0.263 -TNS : 0.000 - -Type : Fast 1200mV 0C Model Recovery 'nPCI_INTB' -Slack : 0.294 -TNS : 0.000 - -Type : Fast 1200mV 0C Model Removal 'inst13|altpll_component|auto_generated|pll1|clk[2]' -Slack : -6.385 -TNS : -890.317 - -Type : Fast 1200mV 0C Model Removal 'MAIN_CLK' -Slack : -6.131 -TNS : -844.343 - -Type : Fast 1200mV 0C Model Removal 'inst12|altpll_component|auto_generated|pll1|clk[0]' -Slack : -1.544 -TNS : -3.088 - -Type : Fast 1200mV 0C Model Removal 'nPCI_INTB' -Slack : -0.648 -TNS : -0.648 - -Type : Fast 1200mV 0C Model Removal 'nPCI_INTD' -Slack : -0.607 -TNS : -0.607 - -Type : Fast 1200mV 0C Model Removal 'nPCI_INTA' -Slack : -0.603 -TNS : -0.603 - -Type : Fast 1200mV 0C Model Removal 'nPCI_INTC' -Slack : -0.601 -TNS : -0.601 - -Type : Fast 1200mV 0C Model Removal 'PIC_INT' -Slack : -0.261 -TNS : -0.261 - -Type : Fast 1200mV 0C Model Removal 'E0_INT' -Slack : 0.109 -TNS : 0.000 - -Type : Fast 1200mV 0C Model Removal 'DVI_INT' -Slack : 0.148 -TNS : 0.000 - -Type : Fast 1200mV 0C Model Removal 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC' -Slack : 0.560 -TNS : 0.000 - -Type : Fast 1200mV 0C Model Removal 'inst22|altpll_component|auto_generated|pll1|clk[0]' -Slack : 0.568 -TNS : 0.000 - -Type : Fast 1200mV 0C Model Removal 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC' -Slack : 1.306 -TNS : 0.000 - -Type : Fast 1200mV 0C Model Removal 'inst13|altpll_component|auto_generated|pll1|clk[1]' -Slack : 1.739 -TNS : 0.000 - -Type : Fast 1200mV 0C Model Minimum Pulse Width 'PIC_INT' -Slack : -3.000 -TNS : -5.254 - -Type : Fast 1200mV 0C Model Minimum Pulse Width 'nPCI_INTD' -Slack : -3.000 -TNS : -5.059 - -Type : Fast 1200mV 0C Model Minimum Pulse Width 'nPCI_INTB' -Slack : -3.000 -TNS : -5.025 - -Type : Fast 1200mV 0C Model Minimum Pulse Width 'nPCI_INTC' -Slack : -3.000 -TNS : -5.003 - -Type : Fast 1200mV 0C Model Minimum Pulse Width 'nPCI_INTA' -Slack : -3.000 -TNS : -4.993 - -Type : Fast 1200mV 0C Model Minimum Pulse Width 'E0_INT' -Slack : -3.000 -TNS : -4.216 - -Type : Fast 1200mV 0C Model Minimum Pulse Width 'DVI_INT' -Slack : -3.000 -TNS : -4.207 - -Type : Fast 1200mV 0C Model Minimum Pulse Width 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC' -Slack : -1.000 -TNS : -1.000 - -Type : Fast 1200mV 0C Model Minimum Pulse Width 'Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC' -Slack : -1.000 -TNS : -1.000 - -Type : Fast 1200mV 0C Model Minimum Pulse Width 'inst12|altpll_component|auto_generated|pll1|clk[0]' -Slack : 3.538 -TNS : 0.000 - -Type : Fast 1200mV 0C Model Minimum Pulse Width 'inst12|altpll_component|auto_generated|pll1|clk[1]' -Slack : 3.563 -TNS : 0.000 - -Type : Fast 1200mV 0C Model Minimum Pulse Width 'inst12|altpll_component|auto_generated|pll1|clk[2]' -Slack : 3.567 -TNS : 0.000 - -Type : Fast 1200mV 0C Model Minimum Pulse Width 'inst12|altpll_component|auto_generated|pll1|clk[3]' -Slack : 3.568 -TNS : 0.000 - -Type : Fast 1200mV 0C Model Minimum Pulse Width 'inst22|altpll_component|auto_generated|pll1|clk[0]' -Slack : 4.773 -TNS : 0.000 - -Type : Fast 1200mV 0C Model Minimum Pulse Width 'inst12|altpll_component|auto_generated|pll1|clk[4]' -Slack : 7.355 -TNS : 0.000 - -Type : Fast 1200mV 0C Model Minimum Pulse Width 'inst|altpll_component|auto_generated|pll1|clk[3]' -Slack : 10.398 -TNS : 0.000 - -Type : Fast 1200mV 0C Model Minimum Pulse Width 'MAIN_CLK' -Slack : 13.572 -TNS : 0.000 - -Type : Fast 1200mV 0C Model Minimum Pulse Width 'inst13|altpll_component|auto_generated|pll1|clk[2]' -Slack : 18.964 -TNS : 0.000 - -Type : Fast 1200mV 0C Model Minimum Pulse Width 'inst13|altpll_component|auto_generated|pll1|clk[1]' -Slack : 30.983 -TNS : 0.000 - -Type : Fast 1200mV 0C Model Minimum Pulse Width 'inst13|altpll_component|auto_generated|pll1|clk[0]' -Slack : 249.649 -TNS : 0.000 - -Type : Fast 1200mV 0C Model Minimum Pulse Width 'inst13|altpll_component|auto_generated|pll1|clk[3]' -Slack : 999.914 -TNS : 0.000 - ------------------------------------------------------------- diff --git a/FPGA_by_Fredi/firebee1.tan.summary b/FPGA_by_Fredi/firebee1.tan.summary deleted file mode 100644 index 4f5907a..0000000 --- a/FPGA_by_Fredi/firebee1.tan.summary +++ /dev/null @@ -1,256 +0,0 @@ --------------------------------------------------------------------------------------- -Timing Analyzer Summary --------------------------------------------------------------------------------------- - -Type : Worst-case tsu -Slack : -10.689 ns -Required Time : 1.000 ns -Actual Time : 11.689 ns -From : nFB_CS1 -To : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|SER[2] -From Clock : -- -To Clock : MAIN_CLK -Failed Paths : 9930 - -Type : Worst-case tco -Slack : -14.089 ns -Required Time : 1.000 ns -Actual Time : 15.089 ns -From : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF2149IP_TOP_SOC:I_SOUND|ADR_I[1] -To : FB_AD[27] -From Clock : MAIN_CLK -To Clock : -- -Failed Paths : 7401 - -Type : Worst-case tpd -Slack : -14.015 ns -Required Time : 1.000 ns -Actual Time : 15.015 ns -From : nFB_CS1 -To : FB_AD[27] -From Clock : -- -To Clock : -- -Failed Paths : 546 - -Type : Worst-case th -Slack : -0.258 ns -Required Time : 1.000 ns -Actual Time : 1.258 ns -From : FB_AD[20] -To : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo1:WRF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_3fh1:auto_generated|altsyncram_ci31:fifo_ram|ram_block11a0~porta_datain_reg0 -From Clock : -- -To Clock : MAIN_CLK -Failed Paths : 16 - -Type : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]' -Slack : -17.845 ns -Required Time : 132.01 MHz ( period = 7.575 ns ) -Actual Time : N/A -From : Video:Fredi_Aschwanden|BLITTER:BLITTER|BL_DST_ADR[0] -To : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[21]~DFFLO -From Clock : MAIN_CLK -To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] -Failed Paths : 29183 - -Type : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]' -Slack : -11.412 ns -Required Time : 132.01 MHz ( period = 7.575 ns ) -Actual Time : N/A -From : Video:Fredi_Aschwanden|BLITTER:BLITTER|BL_DST_ADR[0] -To : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|VA_P[4] -From Clock : MAIN_CLK -To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] -Failed Paths : 25165 - -Type : Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0]' -Slack : -6.848 ns -Required Time : 25.00 MHz ( period = 39.999 ns ) -Actual Time : N/A -From : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[6] -To : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI -From Clock : MAIN_CLK -To Clock : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0] -Failed Paths : 5329 - -Type : Clock Setup: 'MAIN_CLK' -Slack : -6.482 ns -Required Time : 33.00 MHz ( period = 30.303 ns ) -Actual Time : N/A -From : FB_ALE -To : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|CMD_STATE.T8 -From Clock : altpll1:inst|altpll:altpll_component|altpll_d4m2:auto_generated|clk[0] -To Clock : MAIN_CLK -Failed Paths : 43303 - -Type : Clock Setup: 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]' -Slack : -6.153 ns -Required Time : 96.01 MHz ( period = 10.416 ns ) -Actual Time : N/A -From : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|ACP_VCTR[6] -To : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|INTER_ZEI -From Clock : MAIN_CLK -To Clock : altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] -Failed Paths : 5302 - -Type : Clock Setup: 'altpll1:inst|altpll:altpll_component|altpll_d4m2:auto_generated|clk[1]' -Slack : -4.613 ns -Required Time : 16.00 MHz ( period = 62.499 ns ) -Actual Time : N/A -From : lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[16] -To : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF5380_TOP_SOC:I_SCSI|WF5380_REGISTERS:I_REGISTERS|SER[2] -From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] -To Clock : altpll1:inst|altpll:altpll_component|altpll_d4m2:auto_generated|clk[1] -Failed Paths : 2876 - -Type : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]' -Slack : -3.386 ns -Required Time : 66.00 MHz ( period = 15.151 ns ) -Actual Time : N/A -From : FB_ALE -To : lpm_ff0:inst1|lpm_ff:lpm_ff_component|dffs[14] -From Clock : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0] -To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] -Failed Paths : 33 - -Type : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]' -Slack : 2.966 ns -Required Time : 132.01 MHz ( period = 7.575 ns ) -Actual Time : Restricted to 500.00 MHz ( period = 2.000 ns ) -From : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[8] -To : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[8] -From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] -To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] -Failed Paths : 0 - -Type : Clock Setup: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]' -Slack : 5.489 ns -Required Time : 132.01 MHz ( period = 7.575 ns ) -Actual Time : N/A -From : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[6] -To : Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[6] -From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] -To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] -Failed Paths : 0 - -Type : Clock Setup: 'altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[2]' -Slack : 27.221 ns -Required Time : 0.50 MHz ( period = 1999.998 ns ) -Actual Time : N/A -From : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|WF6850IP_TOP_SOC:I_ACIA_KEYBOARD|WF6850IP_TRANSMIT:I_UART_TRANSMIT|TR_STATE.PARITY -To : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_TX -From Clock : MAIN_CLK -To Clock : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[2] -Failed Paths : 0 - -Type : Clock Hold: 'MAIN_CLK' -Slack : -4.871 ns -Required Time : 33.00 MHz ( period = 30.303 ns ) -Actual Time : N/A -From : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSY_LEN[4] -To : Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC_I[4] -From Clock : MAIN_CLK -To Clock : MAIN_CLK -Failed Paths : 764 - -Type : Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0]' -Slack : -0.116 ns -Required Time : 25.00 MHz ( period = 39.999 ns ) -Actual Time : N/A -From : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_kk21:auto_generated|a_dpfifo_nq21:dpfifo|low_addressa[8] -To : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_kk21:auto_generated|a_dpfifo_nq21:dpfifo|low_addressa[8] -From Clock : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0] -To Clock : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[0] -Failed Paths : 136 - -Type : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0]' -Slack : 0.491 ns -Required Time : 132.01 MHz ( period = 7.575 ns ) -Actual Time : N/A -From : Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_bqh1:auto_generated|a_graycounter_pjc:wrptr_gp|counter11a[0] -To : Video:Fredi_Aschwanden|lpm_fifo_dc0:inst|dcfifo:dcfifo_component|dcfifo_bqh1:auto_generated|altsyncram_fo31:fifo_ram|ram_block12a79~porta_address_reg0 -From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] -To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] -Failed Paths : 0 - -Type : Clock Hold: 'altpll1:inst|altpll:altpll_component|altpll_d4m2:auto_generated|clk[1]' -Slack : 0.500 ns -Required Time : 16.00 MHz ( period = 62.499 ns ) -Actual Time : N/A -From : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|wrptr_g[8] -To : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|dcfifo0:RDF|dcfifo_mixed_widths:dcfifo_mixed_widths_component|dcfifo_0hh1:auto_generated|altsyncram_bi31:fifo_ram|ram_block11a0~porta_address_reg0 -From Clock : altpll1:inst|altpll:altpll_component|altpll_d4m2:auto_generated|clk[1] -To Clock : altpll1:inst|altpll:altpll_component|altpll_d4m2:auto_generated|clk[1] -Failed Paths : 0 - -Type : Clock Hold: 'altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[2]' -Slack : 0.502 ns -Required Time : 0.50 MHz ( period = 1999.998 ns ) -Actual Time : N/A -From : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] -To : FalconIO_SDCard_IDE_CF:Wolfgang_Foerster_and_Fredi_Aschwanden|AMKB_REG[0] -From Clock : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[2] -To Clock : altpll3:inst13|altpll:altpll_component|altpll_qks2:auto_generated|clk[2] -Failed Paths : 0 - -Type : Clock Hold: 'altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0]' -Slack : 0.502 ns -Required Time : 96.01 MHz ( period = 10.416 ns ) -Actual Time : N/A -From : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_kk21:auto_generated|a_dpfifo_nq21:dpfifo|low_addressa[8] -To : Video:Fredi_Aschwanden|lpm_fifoDZ:inst63|scfifo:scfifo_component|scfifo_kk21:auto_generated|a_dpfifo_nq21:dpfifo|low_addressa[8] -From Clock : altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] -To Clock : altpll4:inst22|altpll:altpll_component|altpll_c6j2:auto_generated|clk[0] -Failed Paths : 0 - -Type : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2]' -Slack : 1.812 ns -Required Time : 132.01 MHz ( period = 7.575 ns ) -Actual Time : N/A -From : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|SR_VDMP[4] -To : Video:Fredi_Aschwanden|lpm_ff5:inst97|lpm_ff:lpm_ff_component|dffs[4] -From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[0] -To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[2] -Failed Paths : 0 - -Type : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4]' -Slack : 2.489 ns -Required Time : 66.00 MHz ( period = 15.151 ns ) -Actual Time : N/A -From : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ -To : Video:Fredi_Aschwanden|DDR_CTR:DDR_CTR|CPU_REQ -From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] -To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[4] -Failed Paths : 0 - -Type : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3]' -Slack : 3.193 ns -Required Time : 132.01 MHz ( period = 7.575 ns ) -Actual Time : N/A -From : Video:Fredi_Aschwanden|inst90~_Duplicate_4 -To : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|ddio_outa[31]~DFFHI -From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] -To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[3] -Failed Paths : 0 - -Type : Clock Hold: 'altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1]' -Slack : 4.335 ns -Required Time : 132.01 MHz ( period = 7.575 ns ) -Actual Time : N/A -From : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_cell_l[16] -To : Video:Fredi_Aschwanden|altddio_bidir0:inst1|altddio_bidir:altddio_bidir_component|ddio_bidir_3jl:auto_generated|input_latch_l[16] -From Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] -To Clock : altpll2:inst12|altpll:altpll_component|altpll_isv2:auto_generated|clk[1] -Failed Paths : 0 - -Type : Total number of failed paths -Slack : -Required Time : -Actual Time : -From : -To : -From Clock : -To Clock : -Failed Paths : 129984 - --------------------------------------------------------------------------------------- - diff --git a/FPGA_by_Fredi/firebeei1.qws b/FPGA_by_Fredi/firebeei1.qws index 7f27155..9c279dd 100644 --- a/FPGA_by_Fredi/firebeei1.qws +++ b/FPGA_by_Fredi/firebeei1.qws @@ -4,13 +4,13 @@ ptn_Child1=Frames ptn_Child1=ChildFrames [ProjectWorkspace.Frames.ChildFrames] ptn_Child1=Document-0 -ptn_Child2=Document-1 -ptn_Child3=Document-2 [ProjectWorkspace.Frames.ChildFrames.Document-0] ptn_Child1=ViewFrame-0 [ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0] -DocPathName=firebee1.bdf -DocumentCLSID={7b19e8f2-2bbe-11d1-a082-0020affa5bde} +DocPathName=blitter.tdf +DocumentCLSID={5d384c4f-893c-11d1-a087-0020affa43f2} IsChildFrameDetached=False -IsActiveChildFrame=False +IsActiveChildFrame=True ptn_Child1=StateMap +[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0.StateMap] +AFC_IN_REPORT=False diff --git a/FPGA_by_Fredi/lpm_counter1_wave0.jpg b/FPGA_by_Fredi/lpm_counter1_wave0.jpg deleted file mode 100644 index 8298f97..0000000 Binary files a/FPGA_by_Fredi/lpm_counter1_wave0.jpg and /dev/null differ diff --git a/FPGA_by_Fredi/lpm_counter1_waveforms.html b/FPGA_by_Fredi/lpm_counter1_waveforms.html deleted file mode 100644 index a353967..0000000 --- a/FPGA_by_Fredi/lpm_counter1_waveforms.html +++ /dev/null @@ -1,13 +0,0 @@ - - -Sample Waveforms for "lpm_counter1.tdf" - - -

Sample behavioral waveforms for design file "lpm_counter1.tdf"

-

The following waveforms show the behavior of lpm_counter megafunction for the chosen set of parameters in design "lpm_counter1.tdf". The design "lpm_counter1.tdf" is a 12 bit up counter.

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-

Fig. 1 : Wave showing counter operation.

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The output port cout will be asserted at the completion of count sequence. The ports cin and cout are used to chain multiple counters together.

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- - diff --git a/FPGA_by_Fredi/lpm_fifo_dc0_waveforms.html b/FPGA_by_Fredi/lpm_fifo_dc0_waveforms.html deleted file mode 100644 index 12ad5c2..0000000 --- a/FPGA_by_Fredi/lpm_fifo_dc0_waveforms.html +++ /dev/null @@ -1,16 +0,0 @@ - - -Sample Waveforms for "lpm_fifo_dc0.vhd" - - -

Sample behavioral waveforms for design file "lpm_fifo_dc0.vhd"

-

The following waveforms show the behavior of dcfifo_mixed_widths megafunction for the chosen set of parameters in design "lpm_fifo_dc0.vhd". The design "lpm_fifo_dc0.vhd" has a write-side depth of 32 words of 8 bits each. a read-side width of 32. The fifo is in legacy synchronous mode. The data becomes available after 'rdreq' is asserted; 'rdreq' acts as a read request.

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-

Fig. 1 : Wave showing read and write operation.

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The above waveform shows the behavior of the design under normal read and write conditions .

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-

Fig. 2 : Wave showing FIFO full operation.

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The above waveform shows the behavior of the FIFO under wrfull condition. In the example above, data is written into the FIFO till it is full, then data is read back.

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- - diff --git a/FPGA_by_Fredi/serv_req_info.txt b/FPGA_by_Fredi/serv_req_info.txt new file mode 100644 index 0000000..51a4176 --- /dev/null +++ b/FPGA_by_Fredi/serv_req_info.txt @@ -0,0 +1,115 @@ + + quartus.exe + VDB + /quartus/db/vdb/vdb_value_bus.cpp + 4101 + + 0x0382cb44: db_vdb + 0x5cb44 (?get_element@VDB_VALUE_BUS@@QBIPAVVDB_VALUE@@I@Z + 0x54) + + loc < m_value->size() + Tue Oct 13 17:01:46 2009 + Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition + loc < m_value->size() +Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition + + + + quartus.exe + VDB + /quartus/db/vdb/vdb_value_bus.cpp + 4101 + + 0x0382cb44: db_vdb + 0x5cb44 (?get_element@VDB_VALUE_BUS@@QBIPAVVDB_VALUE@@I@Z + 0x54) + + loc < m_value->size() + Tue Oct 13 17:11:00 2009 + Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition + loc < m_value->size() +Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition + + + + quartus.exe + unknown + unknown + 0 + Current editor: GED + Wed Oct 14 23:17:06 2009 + Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition + Access Violation at 00000000 +Current editor: GED +Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition + + + + quartus.exe + unknown + unknown + 0 + Current editor: SFW, STED + Thu Oct 15 19:23:19 2009 + Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition + Access Violation at 00000000 +Current editor: SFW, STED +Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition + + + + quartus.exe + unknown + unknown + 0 + + 0x1002d196: GCL_AFC + 0x2d196 (?open_document_file@AFC_TEMPLATE_MANAGER@@UAIPAVCDocument@@PBDPBVAFC_DOC_INFO@@PAVAFC_PROJECT_STATE_MAP@@_N33@Z + 0x7b6) + + Current editor: RPW, SFW +Current dockable window: PJN + Fri Oct 16 00:14:03 2009 + Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition + Access Violation at 0X1002D196 +Current editor: RPW, SFW +Current dockable window: PJN +Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition + + + + quartus.exe + unknown + unknown + 0 + Current editor: SFW + Sat Oct 17 19:01:54 2009 + Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition + Access Violation at 00000000 +Current editor: SFW +Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition + + + + quartus.exe + AFC + /quartus/gcl/afc/afc_child_frame.cpp + 1940 + + 0x100084fa: GCL_AFC + 0x84fa (?enable_docking@AFC_CHILD_FRAME@@QAIXK@Z + 0x7a) + + (bar != NULL) && bar->Create(this, WS_CLIPSIBLINGS | WS_CLIPCHILDREN | WS_CHILD | WS_VISIBLE | m_s_dock_bar_map[i][1], 0, m_s_dock_bar_map[i][0]) + Mon Oct 19 21:58:36 2009 + Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition + (bar != NULL) && bar->Create(this, WS_CLIPSIBLINGS | WS_CLIPCHILDREN | WS_CHILD | WS_VISIBLE | m_s_dock_bar_map[i][1], 0, m_s_dock_bar_map[i][0]) +Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition + + + + quartus.exe + unknown + unknown + 0 + Current editor: RPW, GED + Tue Oct 20 00:53:11 2009 + Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition + Access Violation at 00000000 +Current editor: RPW, GED +Quartus II Version 8.1 Build 163 10/28/2008 SJ Web Edition + + diff --git a/FPGA_by_Fredi/sopc_builder_log.txt b/FPGA_by_Fredi/sopc_builder_log.txt new file mode 100644 index 0000000..e69de29 diff --git a/FPGA_by_Fredi/undo_redo.txt b/FPGA_by_Fredi/undo_redo.txt new file mode 100644 index 0000000..5c139c4 --- /dev/null +++ b/FPGA_by_Fredi/undo_redo.txt @@ -0,0 +1,12 @@ +GED + + Undo Commands + 1. Properties + 2. Move + 3. Paste + 4. Properties + 5. Properties + 6. Move + 7. Paste + +