151 lines
7.6 KiB
C
151 lines
7.6 KiB
C
/* Coldfire C Header File
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* Copyright Freescale Semiconductor Inc
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* All rights reserved.
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*
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* 2008/05/23 Revision: 0.81
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*
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* (c) Copyright UNIS, a.s. 1997-2008
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* UNIS, a.s.
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* Jundrovska 33
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* 624 00 Brno
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* Czech Republic
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* http : www.processorexpert.com
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* mail : info@processorexpert.com
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*/
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#ifndef __MCF5475_DSPI_H__
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#define __MCF5475_DSPI_H__
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/*********************************************************************
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*
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* DMA Serial Peripheral Interface (DSPI)
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*
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*********************************************************************/
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/* Register read/write macros */
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#define MCF_DSPI_DMCR (*(volatile uint32_t*)(&_MBAR[0x8A00]))
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#define MCF_DSPI_DTCR (*(volatile uint32_t*)(&_MBAR[0x8A08]))
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#define MCF_DSPI_DCTAR0 (*(volatile uint32_t*)(&_MBAR[0x8A0C]))
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#define MCF_DSPI_DCTAR1 (*(volatile uint32_t*)(&_MBAR[0x8A10]))
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#define MCF_DSPI_DCTAR2 (*(volatile uint32_t*)(&_MBAR[0x8A14]))
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#define MCF_DSPI_DCTAR3 (*(volatile uint32_t*)(&_MBAR[0x8A18]))
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#define MCF_DSPI_DCTAR4 (*(volatile uint32_t*)(&_MBAR[0x8A1C]))
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#define MCF_DSPI_DCTAR5 (*(volatile uint32_t*)(&_MBAR[0x8A20]))
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#define MCF_DSPI_DCTAR6 (*(volatile uint32_t*)(&_MBAR[0x8A24]))
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#define MCF_DSPI_DCTAR7 (*(volatile uint32_t*)(&_MBAR[0x8A28]))
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#define MCF_DSPI_DSR (*(volatile uint32_t*)(&_MBAR[0x8A2C]))
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#define MCF_DSPI_DIRSR (*(volatile uint32_t*)(&_MBAR[0x8A30]))
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#define MCF_DSPI_DTFR (*(volatile uint32_t*)(&_MBAR[0x8A34]))
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#define MCF_DSPI_DRFR (*(volatile uint32_t*)(&_MBAR[0x8A38]))
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#define MCF_DSPI_DTFDR0 (*(volatile uint32_t*)(&_MBAR[0x8A3C]))
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#define MCF_DSPI_DTFDR1 (*(volatile uint32_t*)(&_MBAR[0x8A40]))
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#define MCF_DSPI_DTFDR2 (*(volatile uint32_t*)(&_MBAR[0x8A44]))
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#define MCF_DSPI_DTFDR3 (*(volatile uint32_t*)(&_MBAR[0x8A48]))
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#define MCF_DSPI_DRFDR0 (*(volatile uint32_t*)(&_MBAR[0x8A7C]))
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#define MCF_DSPI_DRFDR1 (*(volatile uint32_t*)(&_MBAR[0x8A80]))
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#define MCF_DSPI_DRFDR2 (*(volatile uint32_t*)(&_MBAR[0x8A84]))
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#define MCF_DSPI_DRFDR3 (*(volatile uint32_t*)(&_MBAR[0x8A88]))
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#define MCF_DSPI_DCTAR(x) (*(volatile uint32_t*)(&_MBAR[0x8A0C + ((x)*0x4)]))
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#define MCF_DSPI_DTFDR(x) (*(volatile uint32_t*)(&_MBAR[0x8A3C + ((x)*0x4)]))
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#define MCF_DSPI_DRFDR(x) (*(volatile uint32_t*)(&_MBAR[0x8A7C + ((x)*0x4)]))
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/* Bit definitions and macros for MCF_DSPI_DMCR */
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#define MCF_DSPI_DMCR_HALT (0x1)
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#define MCF_DSPI_DMCR_SMPL_PT(x) (((x)&0x3)<<0x8)
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#define MCF_DSPI_DMCR_SMPL_PT_0CLK (0)
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#define MCF_DSPI_DMCR_SMPL_PT_1CLK (0x100)
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#define MCF_DSPI_DMCR_SMPL_PT_2CLK (0x200)
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#define MCF_DSPI_DMCR_CRXF (0x400)
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#define MCF_DSPI_DMCR_CTXF (0x800)
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#define MCF_DSPI_DMCR_DRXF (0x1000)
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#define MCF_DSPI_DMCR_DTXF (0x2000)
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#define MCF_DSPI_DMCR_CSIS0 (0x10000)
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#define MCF_DSPI_DMCR_CSIS2 (0x40000)
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#define MCF_DSPI_DMCR_CSIS3 (0x80000)
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#define MCF_DSPI_DMCR_CSIS5 (0x200000)
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#define MCF_DSPI_DMCR_ROOE (0x1000000)
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#define MCF_DSPI_DMCR_PCSSE (0x2000000)
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#define MCF_DSPI_DMCR_MTFE (0x4000000)
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#define MCF_DSPI_DMCR_FRZ (0x8000000)
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#define MCF_DSPI_DMCR_DCONF(x) (((x)&0x3)<<0x1C)
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#define MCF_DSPI_DMCR_CSCK (0x40000000)
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#define MCF_DSPI_DMCR_MSTR (0x80000000)
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/* Bit definitions and macros for MCF_DSPI_DTCR */
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#define MCF_DSPI_DTCR_SPI_TCNT(x) (((x)&0xFFFF)<<0x10)
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/* Bit definitions and macros for MCF_DSPI_DCTAR */
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#define MCF_DSPI_DCTAR_BR(x) (((x)&0xF)<<0)
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#define MCF_DSPI_DCTAR_DT(x) (((x)&0xF)<<0x4)
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#define MCF_DSPI_DCTAR_ASC(x) (((x)&0xF)<<0x8)
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#define MCF_DSPI_DCTAR_CSSCK(x) (((x)&0xF)<<0xC)
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#define MCF_DSPI_DCTAR_PBR(x) (((x)&0x3)<<0x10)
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#define MCF_DSPI_DCTAR_PBR_1CLK (0)
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#define MCF_DSPI_DCTAR_PBR_3CLK (0x10000)
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#define MCF_DSPI_DCTAR_PBR_5CLK (0x20000)
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#define MCF_DSPI_DCTAR_PBR_7CLK (0x30000)
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#define MCF_DSPI_DCTAR_PDT(x) (((x)&0x3)<<0x12)
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#define MCF_DSPI_DCTAR_PDT_1CLK (0)
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#define MCF_DSPI_DCTAR_PDT_3CLK (0x40000)
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#define MCF_DSPI_DCTAR_PDT_5CLK (0x80000)
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#define MCF_DSPI_DCTAR_PDT_7CLK (0xC0000)
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#define MCF_DSPI_DCTAR_PASC(x) (((x)&0x3)<<0x14)
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#define MCF_DSPI_DCTAR_PASC_1CLK (0)
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#define MCF_DSPI_DCTAR_PASC_3CLK (0x100000)
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#define MCF_DSPI_DCTAR_PASC_5CLK (0x200000)
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#define MCF_DSPI_DCTAR_PASC_7CLK (0x300000)
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#define MCF_DSPI_DCTAR_PCSSCK(x) (((x)&0x3)<<0x16)
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#define MCF_DSPI_DCTAR_LSBFE (0x1000000)
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#define MCF_DSPI_DCTAR_CPHA (0x2000000)
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#define MCF_DSPI_DCTAR_CPOL (0x4000000)
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#define MCF_DSPI_DCTAR_TRSZ(x) (((x)&0xF)<<0x1B)
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/* Bit definitions and macros for MCF_DSPI_DSR */
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#define MCF_DSPI_DSR_RXPTR(x) (((x)&0xF)<<0)
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#define MCF_DSPI_DSR_RXCTR(x) (((x)&0xF)<<0x4)
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#define MCF_DSPI_DSR_TXPTR(x) (((x)&0xF)<<0x8)
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#define MCF_DSPI_DSR_TXCTR(x) (((x)&0xF)<<0xC)
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#define MCF_DSPI_DSR_RFDF (0x20000)
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#define MCF_DSPI_DSR_RFOF (0x80000)
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#define MCF_DSPI_DSR_TFFF (0x2000000)
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#define MCF_DSPI_DSR_TFUF (0x8000000)
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#define MCF_DSPI_DSR_EOQF (0x10000000)
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#define MCF_DSPI_DSR_TXRXS (0x40000000)
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#define MCF_DSPI_DSR_TCF (0x80000000)
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/* Bit definitions and macros for MCF_DSPI_DIRSR */
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#define MCF_DSPI_DIRSR_RFDFS (0x10000)
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#define MCF_DSPI_DIRSR_RFDFE (0x20000)
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#define MCF_DSPI_DIRSR_RFOFE (0x80000)
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#define MCF_DSPI_DIRSR_TFFFS (0x1000000)
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#define MCF_DSPI_DIRSR_TFFFE (0x2000000)
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#define MCF_DSPI_DIRSR_TFUFE (0x8000000)
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#define MCF_DSPI_DIRSR_EOQFE (0x10000000)
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#define MCF_DSPI_DIRSR_TCFE (0x80000000)
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/* Bit definitions and macros for MCF_DSPI_DTFR */
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#define MCF_DSPI_DTFR_TXDATA(x) (((x)&0xFFFF)<<0)
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#define MCF_DSPI_DTFR_CS0 (0x10000)
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#define MCF_DSPI_DTFR_CS2 (0x40000)
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#define MCF_DSPI_DTFR_CS3 (0x80000)
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#define MCF_DSPI_DTFR_CS5 (0x200000)
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#define MCF_DSPI_DTFR_CTCNT (0x4000000)
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#define MCF_DSPI_DTFR_EOQ (0x8000000)
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#define MCF_DSPI_DTFR_CTAS(x) (((x)&0x7)<<0x1C)
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#define MCF_DSPI_DTFR_CONT (0x80000000)
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/* Bit definitions and macros for MCF_DSPI_DRFR */
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#define MCF_DSPI_DRFR_RXDATA(x) (((x)&0xFFFF)<<0)
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/* Bit definitions and macros for MCF_DSPI_DTFDR */
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#define MCF_DSPI_DTFDR_TXDATA(x) (((x)&0xFFFF)<<0)
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#define MCF_DSPI_DTFDR_TXCMD(x) (((x)&0xFFFF)<<0x10)
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/* Bit definitions and macros for MCF_DSPI_DRFDR */
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#define MCF_DSPI_DRFDR_RXDATA(x) (((x)&0xFFFF)<<0)
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#endif /* __MCF5475_DSPI_H__ */
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