remove debug output

release 0.91. Fixes FireTOS cold boot problem
make FireTOS always cold boot (clear sys vars)
2016-09-27 04:37:42 +00:00 · 2016-08-14 10:00:25 +00:00 · 2016-08-14 09:55:28 +00:00 · 2016-08-14 09:09:12 +00:00 · 2016-08-14 08:16:20 +00:00 · 2016-08-02 08:45:26 +00:00
71 changed files with 7327 additions and 325 deletions
--- a/BaS_gcc.files
+++ b/BaS_gcc.files
@@ -185,10 +185,6 @@ usb/usb_kbd.c
 tos/jtagwait/sources/bas_printf.c
 tos/jtagwait/sources/bas_string.c
 tos/vmem_test/Makefile
-tos/vmem_test/sources/bas_printf.c
-tos/vmem_test/sources/bas_string.c
-tos/vmem_test/sources/printf_helper.S
-tos/vmem_test/sources/vmem_test.c
 sys/startcf.S
 sys/exceptions.S
 util/bas_printf.c
@@ -525,11 +521,6 @@ tos/vmem_test/include/MCF5475_USB.h
 tos/vmem_test/include/MCF5475_XLB.h
 tos/vmem_test/m5475/mshort/vmem_test.prg
 tos/vmem_test/m5475/vmem_test.prg
-tos/vmem_test/sources/bas_printf.c
-tos/vmem_test/sources/bas_string.c
-tos/vmem_test/sources/printf_helper.S
-tos/vmem_test/sources/vmem_test.c
-tos/vmem_test/depend
 tos/vmem_test/Makefile
 tos/vmem_test/mapfile
 tos/vmem_test/vmem_test.config
@@ -610,3 +601,134 @@ tos/pci_test/include/MCF5475_XLB.h
 tos/pci_test/include/MCF5475.h
 tos/pci_test/include/pci.h
 memory_map.txt
+pci/pci_errata.c
+include/pci_errata.h
+tos/bascook/sources/bascook.c
+tos/bascook/Makefile
+tos/fpga_test/include/bas_printf.h
+tos/fpga_test/include/bas_string.h
+tos/fpga_test/include/driver_vec.h
+tos/fpga_test/include/MCF5475.h
+tos/fpga_test/include/MCF5475_CLOCK.h
+tos/fpga_test/include/MCF5475_CTM.h
+tos/fpga_test/include/MCF5475_DMA.h
+tos/fpga_test/include/MCF5475_DSPI.h
+tos/fpga_test/include/MCF5475_EPORT.h
+tos/fpga_test/include/MCF5475_FBCS.h
+tos/fpga_test/include/MCF5475_FEC.h
+tos/fpga_test/include/MCF5475_GPIO.h
+tos/fpga_test/include/MCF5475_GPT.h
+tos/fpga_test/include/MCF5475_I2C.h
+tos/fpga_test/include/MCF5475_INTC.h
+tos/fpga_test/include/MCF5475_MMU.h
+tos/fpga_test/include/MCF5475_PAD.h
+tos/fpga_test/include/MCF5475_PCI.h
+tos/fpga_test/include/MCF5475_PCIARB.h
+tos/fpga_test/include/MCF5475_PSC.h
+tos/fpga_test/include/MCF5475_SDRAMC.h
+tos/fpga_test/include/MCF5475_SEC.h
+tos/fpga_test/include/MCF5475_SIU.h
+tos/fpga_test/include/MCF5475_SLT.h
+tos/fpga_test/include/MCF5475_SRAM.h
+tos/fpga_test/include/MCF5475_USB.h
+tos/fpga_test/include/MCF5475_XLB.h
+tos/fpga_test/sources/bas_printf.c
+tos/fpga_test/sources/bas_string.c
+tos/fpga_test/sources/printf_helper.S
+tos/fpga_test/Makefile
+tos/jtagwait/include/bas_printf.h
+tos/jtagwait/include/bas_string.h
+tos/jtagwait/include/driver_vec.h
+tos/jtagwait/include/MCF5475.h
+tos/jtagwait/include/MCF5475_CLOCK.h
+tos/jtagwait/include/MCF5475_CTM.h
+tos/jtagwait/include/MCF5475_DMA.h
+tos/jtagwait/include/MCF5475_DSPI.h
+tos/jtagwait/include/MCF5475_EPORT.h
+tos/jtagwait/include/MCF5475_FBCS.h
+tos/jtagwait/include/MCF5475_FEC.h
+tos/jtagwait/include/MCF5475_GPIO.h
+tos/jtagwait/include/MCF5475_GPT.h
+tos/jtagwait/include/MCF5475_I2C.h
+tos/jtagwait/include/MCF5475_INTC.h
+tos/jtagwait/include/MCF5475_MMU.h
+tos/jtagwait/include/MCF5475_PAD.h
+tos/jtagwait/include/MCF5475_PCI.h
+tos/jtagwait/include/MCF5475_PCIARB.h
+tos/jtagwait/include/MCF5475_PSC.h
+tos/jtagwait/include/MCF5475_SDRAMC.h
+tos/jtagwait/include/MCF5475_SEC.h
+tos/jtagwait/include/MCF5475_SIU.h
+tos/jtagwait/include/MCF5475_SLT.h
+tos/jtagwait/include/MCF5475_SRAM.h
+tos/jtagwait/include/MCF5475_USB.h
+tos/jtagwait/include/MCF5475_XLB.h
+tos/jtagwait/sources/bas_printf.c
+tos/jtagwait/sources/bas_string.c
+tos/jtagwait/sources/jtagwait.c
+tos/jtagwait/sources/printf_helper.S
+tos/jtagwait/Makefile
+tos/pci_test/include/bas_printf.h
+tos/pci_test/include/bas_string.h
+tos/pci_test/include/driver_vec.h
+tos/pci_test/include/MCF5475.h
+tos/pci_test/include/MCF5475_CLOCK.h
+tos/pci_test/include/MCF5475_CTM.h
+tos/pci_test/include/MCF5475_DMA.h
+tos/pci_test/include/MCF5475_DSPI.h
+tos/pci_test/include/MCF5475_EPORT.h
+tos/pci_test/include/MCF5475_FBCS.h
+tos/pci_test/include/MCF5475_FEC.h
+tos/pci_test/include/MCF5475_GPIO.h
+tos/pci_test/include/MCF5475_GPT.h
+tos/pci_test/include/MCF5475_I2C.h
+tos/pci_test/include/MCF5475_INTC.h
+tos/pci_test/include/MCF5475_MMU.h
+tos/pci_test/include/MCF5475_PAD.h
+tos/pci_test/include/MCF5475_PCI.h
+tos/pci_test/include/MCF5475_PCIARB.h
+tos/pci_test/include/MCF5475_PSC.h
+tos/pci_test/include/MCF5475_SDRAMC.h
+tos/pci_test/include/MCF5475_SEC.h
+tos/pci_test/include/MCF5475_SIU.h
+tos/pci_test/include/MCF5475_SLT.h
+tos/pci_test/include/MCF5475_SRAM.h
+tos/pci_test/include/MCF5475_USB.h
+tos/pci_test/include/MCF5475_XLB.h
+tos/pci_test/include/pci.h
+tos/pci_test/sources/bas_printf.c
+tos/pci_test/sources/bas_string.c
+tos/pci_test/sources/pci_test.c
+tos/pci_test/sources/printf_helper.S
+tos/pci_test/Makefile
+tos/vmem_test/include/bas_printf.h
+tos/vmem_test/include/bas_string.h
+tos/vmem_test/include/driver_vec.h
+tos/vmem_test/include/MCF5475.h
+tos/vmem_test/include/MCF5475_CLOCK.h
+tos/vmem_test/include/MCF5475_CTM.h
+tos/vmem_test/include/MCF5475_DMA.h
+tos/vmem_test/include/MCF5475_DSPI.h
+tos/vmem_test/include/MCF5475_EPORT.h
+tos/vmem_test/include/MCF5475_FBCS.h
+tos/vmem_test/include/MCF5475_FEC.h
+tos/vmem_test/include/MCF5475_GPIO.h
+tos/vmem_test/include/MCF5475_GPT.h
+tos/vmem_test/include/MCF5475_I2C.h
+tos/vmem_test/include/MCF5475_INTC.h
+tos/vmem_test/include/MCF5475_MMU.h
+tos/vmem_test/include/MCF5475_PAD.h
+tos/vmem_test/include/MCF5475_PCI.h
+tos/vmem_test/include/MCF5475_PCIARB.h
+tos/vmem_test/include/MCF5475_PSC.h
+tos/vmem_test/include/MCF5475_SDRAMC.h
+tos/vmem_test/include/MCF5475_SEC.h
+tos/vmem_test/include/MCF5475_SIU.h
+tos/vmem_test/include/MCF5475_SLT.h
+tos/vmem_test/include/MCF5475_SRAM.h
+tos/vmem_test/include/MCF5475_USB.h
+tos/vmem_test/include/MCF5475_XLB.h
+tos/vmem_test/sources/fpga_test.c
+tos/vmem_test/Makefile
+tos/Makefile
+tos/fpga_test/sources/fpga_test.c
--- a/BaS_gcc.includes
+++ b/BaS_gcc.includes
@@ -2,6 +2,8 @@ include
 tos/jtagwait/include
 tos/pci_test/include
 /usr/m68k-atari-mint/include
+/opt/cross-mint/m68k-atari-mint/include
+/opt/gygwin/opt/cross-mint/m68k-atari-mint/include
 dma
 m54455
 sys
@@ -42,3 +44,6 @@ tos/vmem_test
 tos/pci_test/sources
 firebee
 tos/jtagwait
+tos/fpga_test/include
+tos/fpga_test
+tos/fpga_test/sources
--- a/13
+++ b/13
@@ -38,10 +38,14 @@ endif

 INCLUDE=-Iinclude
 CFLAGS=	-Wall \
+	-O2 \
 	-fomit-frame-pointer \
 	-ffreestanding \
 	-fleading-underscore \
-	-Wa,--register-prefix-optional
+	-Winline \
+	-Wshadow \
+	-Wa,--register-prefix-optional \
+	-g2
 CFLAGS_OPTIMIZED = -mcpu=5474 \
 		-Wall \
 		-O2 \
@@ -51,7 +55,7 @@ CFLAGS_OPTIMIZED = -mcpu=5474 \
 		-Wa,--register-prefix-optional
 LDFLAGS=

-TRGTDIRS= ./firebee ./m5484lite
+TRGTDIRS= ./firebee ./m54455 ./m5484lite
 OBJDIRS=$(patsubst %, %/objs,$(TRGTDIRS))
 TOOLDIR=util

@@ -92,6 +96,7 @@ CSRCS= \
 	xhdi_sd.c \
 	xhdi_interface.c \
 	pci.c \
+	pci_errata.c \
 	dspi.c \
 	driver_vec.c \
 	driver_mem.c \
@@ -185,6 +190,8 @@ clean:
 		do rm -f $$d/*.map $$d/*.s19 $$d/*.elf $$d/*.lk $$d/*.a $$d/objs/* $$d/depend;\
 	done
 	rm -f tags
+	(cd tos; make clean)
+


 # flags for targets
@@ -278,7 +285,7 @@ $(1)_MAPFILE_RAM=$(1)/$$(basename $$(RAM_EXEC)).map
 $(1)/$$(RAM_EXEC): $(1)/$(LIBBAS) $(LDCSRC)
 	$(CPP) $(INCLUDE) -DCOMPILE_RAM -DOBJDIR=$(1)/objs -P -DFORMAT_ELF=$(FORMAT_ELF) -D$$(MACHINE) $(LDCSRC) -o $(1)/$$(LDRFILE)
 	#$(LD) $(LDFLAGS) --oformat $$(FORMAT) -Map $$($(1)_MAPFILE_RAM) --cref -T $(1)/$$(LDRFILE) $(LDLIBS) -o $$@
-	$(CC) $$(CFLAGS) -nostdlib -Wl,--oformat -Wl,$$(FORMAT) -Wl,-Map -Wl,$$($(1)_MAPFILE) -Wl,--cref -Wl,-T -Wl,$(1)/$$(LDRFILE) $(LDLIBS) -o $$@
+	$(CC) $$(CFLAGS) -nostdlib -Wl,--oformat -Wl,$$(FORMAT) -Wl,-Map -Wl,$$($(1)_MAPFILE_RAM) -Wl,--cref -Wl,-T -Wl,$(1)/$$(LDRFILE) $(LDLIBS) -o $$@
 ifeq ($(COMPILE_ELF),Y)
 	$(OBJCOPY) -O srec $$@ $$(basename $$@).s19
 else
--- a/bas.lk.in
+++ b/bas.lk.in
@@ -1,7 +1,7 @@
 #if defined(MACHINE_FIREBEE)
 #include "firebee.h"
 #elif defined(MACHINE_M5484LITE)
-#include "m5484l.h"
+#    include "m5484l.h"
 #elif defined(MACHINE_M54455)
 #include "m54455.h"
 #else
@@ -49,6 +49,8 @@ SECTIONS

                OBJDIR/BaS.o(.text)
                OBJDIR/pci.o(.text)
+                . = ALIGN(16);
+                OBJDIR/pci_errata.o(.text)
                OBJDIR/pci_wrappers.o(.text)
                OBJDIR/usb.o(.text)
                OBJDIR/driver_mem.o(.text)
--- a/dma/dma.c
+++ b/dma/dma.c
@@ -39,7 +39,7 @@
 #error "unknown machine!"
 #endif /* MACHINE_FIREBEE */

-// #define DBG_DMA
+//#define DBG_DMA
 #ifdef DBG_DMA
 #define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
 #else
--- a/flash_scripts/flash_firebee_bas.bdm
+++ b/flash_scripts/flash_firebee_bas.bdm
@@ -11,7 +11,7 @@ wait
 # use system sdram as flashlib scratch area.
 # TODO: plugin flashing seems to work o.k. now for smaller binaries, while it doesn't for larger ones (EmuTOS) yet.
 # This seems to be related to large flash buffers and PC-relative adressing of the plugin
-#flash-plugin 0x1000 0xf000 flash29-5475.plugin
+flash-plugin 0x1000 0xf000 flash29.plugin
 # notify flashlib that we have flash at address 0xE0000000, length 0x7FFFFF, plugin is flash29
 flash 0xe0000000

--- a/include/bas_utils.h
+++ b/include/bas_utils.h
@@ -26,4 +26,7 @@
 #define CLEAR_BIT(p,bit)        p &= ~(bit)
 #define CLEAR_BIT_NO(p,nr)      CLEAR_BIT(p, (1 << (nr)))

+extern void write_pic_byte(uint8_t value);
+extern uint8_t read_pic_byte(void);
+
 #endif /* _BAS_UTILS_H_ */
--- a/include/driver_vec.h
+++ b/include/driver_vec.h
@@ -265,9 +265,9 @@ struct pci_bios_interface

 struct mmu_driver_interface
 {
-    int32_t (*map_page_locked)(uint32_t address, uint32_t length, int asid);
-    int32_t (*unlock_page)(uint32_t address, uint32_t length, int asid);
-    int32_t (*report_locked_pages)(uint32_t *num_itlb, uint32_t *num_dtlb);
+    uint32_t (*map_page_locked)(uint32_t address, uint32_t length, int asid);
+    uint32_t (*unlock_page)(uint32_t address, uint32_t length, int asid);
+    uint32_t (*report_locked_pages)(uint32_t *num_itlb, uint32_t *num_dtlb);
    uint32_t (*report_pagesize)(void);
 };

--- a/include/exceptions.h
+++ b/include/exceptions.h
@@ -3,26 +3,6 @@

 #include <bas_types.h>

-static inline uint32_t set_ipl(uint32_t ipl)
-{
-	uint32_t ret;
-
-	__asm__ __volatile__(
-		"		move.w	sr,%[ret]\r\n"			/* retrieve status register */
-		"		andi.l	#0x07,%[ipl]\n\t"		/* mask out ipl bits on new value */
-		"		lsl.l	#8,%[ipl]\n\t"			/* shift them to position */
-		"		move.l	%[ret],d0\n\t"			/* retrieve original value */
-		"		andi.l	#0x0000f8ff,d0\n\t"		/* clear ipl part */
-		"		or.l	%[ipl],d0\n\t"			/* or in new value */
-		"		move.w	d0,sr\n\t"				/* put it in place */
-		"		andi.l	#0x0700,%[ret]\r\n"		/* mask out ipl bits */
-		"		lsr.l	#8,%[ret]\r\n"			/* shift them to position */
-		: [ret] "=&d" (ret)		/* output */
-		: [ipl] "d" (ipl)		/* input */
-		: "cc", "d0"	/* clobber */
-	);
-
-	return ret;
-}
+extern uint32_t set_ipl(uint32_t ipl);

 #endif /* _EXCEPTIONS_H_ */
--- a/include/mmu.h
+++ b/include/mmu.h
@@ -64,13 +64,14 @@ enum mmu_page_size
    MMU_PAGE_SIZE_1K	= 3
 };

+#define MMU_PAGE_SIZE_DEFAULT   MMU_PAGE_SIZE_1M    /* note: if this changes, SIZE_DEFAULT below _must_ also change */
+
 #define SIZE_1M             0x100000        /* 1 Megabyte */
 #define SIZE_4K             0x1000          /* 4 KB */
 #define SIZE_8K             0x2000          /* 8 KB */
 #define SIZE_1K             0x400           /* 1 KB */

-#define DEFAULT_PAGE_SIZE   0x00100000      /* 1M pagesize */
-
+#define SIZE_DEFAULT        SIZE_1M
 /*
 * cache modes
 */
@@ -97,16 +98,25 @@ enum mmu_page_size
 extern long video_tlb;
 extern long video_sbt;

-struct mmu_page_descriptor;
+struct mmu_page_descriptor
+{
+    uint8_t cache_mode          : 2;
+    uint8_t supervisor_protect  : 1;
+    uint8_t read                : 1;
+    uint8_t write               : 1;
+    uint8_t execute             : 1;
+    uint8_t global              : 1;
+    uint8_t locked              : 1;
+};

 extern void mmu_init(void);
-extern int mmu_map_page(int32_t virt, int32_t phys, enum mmu_page_size sz, uint8_t page_id, const struct mmu_page_descriptor *flags);
+extern uint32_t mmu_map_page(uint32_t virt, uint32_t phys, enum mmu_page_size sz, uint8_t page_id, const struct mmu_page_descriptor *flags);

 /*
 * API functions for the BaS driver interface
 */
-extern int32_t mmu_map_data_page_locked(uint32_t address, uint32_t length, int asid);
-extern int32_t mmu_unlock_data_page(uint32_t address, uint32_t length, int asid);
-extern int32_t mmu_report_locked_pages(uint32_t *num_itlb, uint32_t *num_dtlb);
+extern uint32_t mmu_map_data_page_locked(uint32_t address, uint32_t length, int asid);
+extern uint32_t mmu_unlock_data_page(uint32_t address, uint32_t length, int asid);
+extern uint32_t mmu_report_locked_pages(uint32_t *num_itlb, uint32_t *num_dtlb);
 extern uint32_t mmu_report_pagesize(void);
 #endif /* _MMU_H_ */
--- a/include/pci.h
+++ b/include/pci.h
@@ -195,7 +195,7 @@ typedef struct                       /* structure of address conversion     */

 /* register 0x08 macros */
 #define PCI_CLASS_CODE(i)   ((swpl((i)) & 0xff000000) >> 24)
-#define PCI_SUBCLASS(i)     ((swpl((i)) & 0xffff0000) >> 16)
+#define PCI_SUBCLASS(i)     ((swpl((i)) & 0x00ff0000) >> 16)
 #define PCI_PROG_IF(i)      ((swpl((i)) & 0x0000ff00) >> 8)
 #define PCI_REVISION_ID(i)  ((swpl((i)) & 0x000000ff))

--- a/include/pci_errata.h
+++ b/include/pci_errata.h
@@ -0,0 +1,11 @@
+#ifndef PCI_ERRATA_H
+#define PCI_ERRATA_H
+
+#include <stdint.h>
+
+
+extern void chip_errata_135(void);
+extern void chip_errata_055(int32_t handle);
+
+#endif // PCI_ERRATA_H
+
--- a/include/util.h
+++ b/include/util.h
@@ -61,13 +61,13 @@ static inline uint32_t swpl(uint32_t l)
 	__asm__ __volatile__
 	(
 		"lea		%[input],a0\n\t"				\
-		"mvz.b	3(a0),%[output]\n\t"			\
-		"lsl.l	#8,%[output]\n\t"				\
-		"move.b	2(a0),%[output]\n\t"			\
-		"lsl.l	#8,%[output]\n\t"				\
-		"move.b	1(a0),%[output]\n\t"			\
-		"lsl.l	#8,%[output]\n\t"				\
-		"move.b	(a0),%[output]\n\t"			\
+        "mvz.b      3(a0),%[output]\n\t"			\
+        "lsl.l      #8,%[output]\n\t"				\
+        "move.b     2(a0),%[output]\n\t"			\
+        "lsl.l      #8,%[output]\n\t"				\
+        "move.b     1(a0),%[output]\n\t"			\
+        "lsl.l      #8,%[output]\n\t"				\
+        "move.b     (a0),%[output]\n\t"			\
 		:	[output] "=d" (result)	/* output */
 		:	[input] "o" (l)			/* input */
 		: "cc", "a0", "memory"	/* clobbered */
--- a/include/version.h
+++ b/include/version.h
@@ -28,8 +28,8 @@
 * increment version number for release
 */

-#define MAJOR_VERSION	0
-#define MINOR_VERSION	88
+#define MAJOR_VERSION   0
+#define MINOR_VERSION   91


 #endif /* VERSION_H_ */
--- a/pci/pci.c
+++ b/pci/pci.c
@@ -26,6 +26,7 @@

 #include <MCF5475.h>
 #include "pci.h"
+#include "pci_errata.h"
 #include "bas_types.h"
 #include "bas_printf.h"
 #include "bas_string.h"
@@ -33,7 +34,7 @@
 #include "interrupts.h"
 #include "wait.h"

-//#define DEBUG_PCI
+// #define DEBUG_PCI
 #ifdef DEBUG_PCI
 #define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
 #else
@@ -98,65 +99,6 @@ struct pci_interrupt
 #define MAX_INTERRUPTS  (NUM_CARDS * 3)
 static struct pci_interrupt interrupts[MAX_INTERRUPTS];

-static inline __attribute__((aligned(16))) void chip_errata_135(void)
-{
-    /*
-     * Errata type: Silicon
-     * Affected component: PCI
-     * Description: When core PCI transactions that involve writes to configuration or I/O space
-     * are followed by a core line access to line addresses 0x4 and 0xC, core access
-     * to the XL bus can hang.
-     * Workaround: Prevent PCI configuration and I/O writes from being followed by the described
-     * line access by the core by generating a known good XL bus transaction after
-     * the PCI transaction.
-     * Create a dummy function which is called immediately after each of the affected
-     * transactions. There are three requirements for this dummy function.
-     * 1. The function must be aligned to a 16-byte boundary.
-     * 2. The function must contain a dummy write to a location on the XL bus,
-     * preferably one with no side effects.
-     * 3. The function must be longer than 32 bytes. If it is not, the function should
-     * be padded with 16- or 48-bit TPF instructions placed after the end of
-     * the function (after the RTS instruction) such that the length is longer
-     * than 32 bytes.
-     */
-
-     __asm__ __volatile(
-        "       .extern __MBAR          \n\t"
-        "       clr.l   d0              \n\t"
-        "       move.l  d0,__MBAR+0xF0C \n\t"       /* Must use direct addressing. write to EPORT module */
-                                                    /* xlbus -> slavebus -> eport, writing '0' to register */
-                                                    /* has no effect */
-        "       rts                     \n\t"
-        "       tpf.l   #0x0            \n\t"
-        "       tpf.l   #0x0            \n\t"
-        "       tpf.l   #0x0            \n\t"
-        "       tpf.l   #0x0            \n\t"
-        "       tpf.l   #0x0            \n\t"
-        ::: "d0", "memory");
-}
-
-static inline void chip_errata_055(int32_t handle)
-{
-    uint32_t dummy;
-
-    return;     /* test */
-
-    /* initiate PCI configuration access to device */
-    MCF_PCI_PCICAR = MCF_PCI_PCICAR_E |         /* enable configuration access special cycle */
-            MCF_PCI_PCICAR_BUSNUM(3) |          /* note: invalid bus number */
-            MCF_PCI_PCICAR_DEVNUM(PCI_DEVICE_FROM_HANDLE(handle)) | /* device number, devices 0 - 9 are reserved */
-            MCF_PCI_PCICAR_FUNCNUM(PCI_FUNCTION_FROM_HANDLE(handle)) |  /* function number */
-            MCF_PCI_PCICAR_DWORD(0);
-
-    /* issue a dummy read to an unsupported bus number (will fail) */
-    dummy =  * (volatile uint32_t *) PCI_IO_OFFSET; /* access device */
-
-    /* silently clear the PCI errors we produced just now */
-    MCF_PCI_PCIISR = 0xffffffff;     /* clear all errors */
-    MCF_PCI_PCIGSCR = MCF_PCI_PCIGSCR_PE | MCF_PCI_PCIGSCR_SE;
-
-    (void) dummy;
-}

 /*
 * Although this pragma stuff should work according to the GCC docs, it doesn't seem to
@@ -472,6 +414,7 @@ int32_t pci_write_config_byte(int32_t handle, int offset, uint8_t value)

    return PCI_SUCCESSFUL;
 }
+
 /*
 * pci_get_resource
 *
@@ -598,9 +541,9 @@ int32_t pci_find_classcode(uint32_t classcode, int index)
                value = pci_read_config_longword(handle, PCICCR);

                dbg("classcode to search for=%x\r\n", classcode);
-                dbg("PCI_CLASSCODE found=%x\r\n", PCI_CLASS_CODE(value));
-                dbg("PCI_SUBCLASS found=%x\r\n", PCI_SUBCLASS(value));
-                dbg("PCI_PROG_IF found=%x\r\n", PCI_PROG_IF(value));
+                dbg("PCI_CLASSCODE found=%02x\r\n", PCI_CLASS_CODE(value));
+                dbg("PCI_SUBCLASS found=%02x\r\n", PCI_SUBCLASS(value));
+                dbg("PCI_PROG_IF found=%02x\r\n", PCI_PROG_IF(value));

                if ((classcode & (1 << 26) ? ((PCI_CLASS_CODE(value) == (classcode & 0xff))) : true) &&
                    (classcode & (1 << 25) ? ((PCI_SUBCLASS(value) == ((classcode & 0xff00) >> 8))) : true) &&
@@ -608,6 +551,7 @@ int32_t pci_find_classcode(uint32_t classcode, int index)
                {
                    if (n == index)
                    {
+                        dbg("found device at handle %d\r\n", handle);
                        return handle;
                    }
                    n++;
@@ -631,12 +575,13 @@ int32_t pci_find_classcode(uint32_t classcode, int index)
                        {
                            value = pci_read_config_longword(handle, PCICCR);

-                            if ((classcode & (1 << 26) ? ((PCI_CLASS_CODE(value) == (classcode & 0xff))) : true) &&
-                                (classcode & (1 << 25) ? ((PCI_SUBCLASS(value) == ((classcode & 0xff00) >> 8))) : true) &&
-                                (classcode & (1 << 24) ? ((PCI_PROG_IF(value) == ((classcode & 0xff0000) >> 16))) : true))
+                            if ((classcode & PCI_FIND_BASE_CLASS ? ((PCI_CLASS_CODE(value) == (classcode & 0xff))) : true) &&
+                                (classcode & PCI_FIND_SUB_CLASS ? ((PCI_SUBCLASS(value) == ((classcode & 0xff00) >> 8))) : true) &&
+                                (classcode & PCI_FIND_PROG_IF ? ((PCI_PROG_IF(value) == ((classcode & 0xff0000) >> 16))) : true))
                            {
                                if (n == index)
                                {
+                                    dbg("found device with handle %d\n", handle);
                                    return handle;
                                }
                                n++;
@@ -1056,7 +1001,7 @@ static void pci_bridge_config(uint16_t bus, uint16_t device, uint16_t function)
    handle = PCI_HANDLE(bus, device, function);
    dbg("handle=%d\r\n", handle);

-    pci_write_config_longword(handle, PCIBAR0, 0x40000000);
+    pci_write_config_longword(handle, PCIBAR0, swpl(0x40000000));
    pci_write_config_longword(handle, PCIBAR1, 0x0);
    pci_write_config_longword(handle, PCICSR, 0x146);
 }
@@ -1080,14 +1025,15 @@ void pci_scan(void)

        value = pci_read_config_longword(handle, PCIIDR);

-        xprintf(" %02x | %02x | %02x |%04x|%04x|%04x| %s (0x%02x)\r\n",
+        xprintf(" %02x | %02x | %02x |%04x|%04x|%04x| %s (0x%02x, 0x%04x)\r\n",
                PCI_BUS_FROM_HANDLE(handle),
                PCI_DEVICE_FROM_HANDLE(handle),
                PCI_FUNCTION_FROM_HANDLE(handle),
                PCI_VENDOR_ID(value), PCI_DEVICE_ID(value),
                handle,
                device_class(pci_read_config_byte(handle, PCICCR)),
-                pci_read_config_byte(handle, PCICCR));
+                pci_read_config_byte(handle, PCICCR),
+                pci_read_config_word(handle, PCICCR));

        /* save handle to index value so that we'll be able to later find our resources */
        handles[index] = handle;
--- a/pci/pci_errata.c
+++ b/pci/pci_errata.c
@@ -0,0 +1,64 @@
+#include "pci_errata.h"
+#include "pci.h"
+#include <MCF5475.h>
+
+__attribute__((aligned(16))) void chip_errata_135(void)
+{
+    /*
+     * Errata type: Silicon
+     * Affected component: PCI
+     * Description: When core PCI transactions that involve writes to configuration or I/O space
+     * are followed by a core line access to line addresses 0x4 and 0xC, core access
+     * to the XL bus can hang.
+     * Workaround: Prevent PCI configuration and I/O writes from being followed by the described
+     * line access by the core by generating a known good XL bus transaction after
+     * the PCI transaction.
+     * Create a dummy function which is called immediately after each of the affected
+     * transactions. There are three requirements for this dummy function.
+     * 1. The function must be aligned to a 16-byte boundary.
+     * 2. The function must contain a dummy write to a location on the XL bus,
+     * preferably one with no side effects.
+     * 3. The function must be longer than 32 bytes. If it is not, the function should
+     * be padded with 16- or 48-bit TPF instructions placed after the end of
+     * the function (after the RTS instruction) such that the length is longer
+     * than 32 bytes.
+     */
+
+     __asm__ __volatile(
+        "       .extern __MBAR          \n\t"
+        "       clr.l   d0              \n\t"
+        "       move.l  d0,__MBAR+0xF0C \n\t"       /* Must use direct addressing. write to EPORT module */
+                                                    /* xlbus -> slavebus -> eport, writing '0' to register */
+                                                    /* has no effect */
+        "       rts                     \n\t"
+        "       tpf.l   #0x0            \n\t"
+        "       tpf.l   #0x0            \n\t"
+        "       tpf.l   #0x0            \n\t"
+        "       tpf.l   #0x0            \n\t"
+        "       tpf.l   #0x0            \n\t"
+        ::: "d0", "memory");
+}
+
+void chip_errata_055(int32_t handle)
+{
+    uint32_t dummy;
+
+    return;     /* test */
+
+    /* initiate PCI configuration access to device */
+    MCF_PCI_PCICAR = MCF_PCI_PCICAR_E |         /* enable configuration access special cycle */
+            MCF_PCI_PCICAR_BUSNUM(3) |          /* note: invalid bus number */
+            MCF_PCI_PCICAR_DEVNUM(PCI_DEVICE_FROM_HANDLE(handle)) | /* device number, devices 0 - 9 are reserved */
+            MCF_PCI_PCICAR_FUNCNUM(PCI_FUNCTION_FROM_HANDLE(handle)) |  /* function number */
+            MCF_PCI_PCICAR_DWORD(0);
+
+    /* issue a dummy read to an unsupported bus number (will fail) */
+    dummy =  * (volatile uint32_t *) PCI_IO_OFFSET; /* access device */
+
+    /* silently clear the PCI errors we produced just now */
+    MCF_PCI_PCIISR = 0xffffffff;     /* clear all errors */
+    MCF_PCI_PCIGSCR = MCF_PCI_PCIGSCR_PE | MCF_PCI_PCIGSCR_SE;
+
+    (void) dummy;
+}
+
--- a/radeon/radeon_base.c
+++ b/radeon/radeon_base.c
@@ -2185,14 +2185,6 @@ int32_t radeonfb_pci_register(int32_t handle, const struct pci_device_id *ent)
                        rinfo->big_endian = 1; /* radeon make swapping intel -> motorola */
                        dbg("host bridge is little endian\r\n");
                    }
-
-                    xprintf("framebuffer dump:\r\n");
-                    hexdump((uint8_t *) rinfo->fb_base_phys, 0x10);
-                    xprintf("change framebuffer contents\r\n");
-                    * (uint32_t *) rinfo->fb_base_phys = 0x01234567;
-                    * (uint32_t *) (rinfo->fb_base_phys + 8) = 0x89abcdef;
-                    hexdump((uint8_t *) rinfo->fb_base_phys, 0x10);
-
                }
                else if ((pci_rsc_desc->length >= RADEON_REGSIZE) && (pci_rsc_desc->length < 0x100000))
                {
@@ -2213,8 +2205,6 @@ int32_t radeonfb_pci_register(int32_t handle, const struct pci_device_id *ent)
                            {
                                dbg("rinfo->bios_seg[0] (%p) was %x (expected 0xaa55)\r\n",
                                    rinfo->bios_seg_phys, * (uint16_t *) rinfo->bios_seg_phys);
-                                xprintf("bios_seg_phys dump:\r\n");
-                                hexdump((uint8_t *) rinfo->bios_seg_phys, 0x100);

                                rinfo->bios_seg_phys = 0;
                            }
@@ -2227,8 +2217,6 @@ int32_t radeonfb_pci_register(int32_t handle, const struct pci_device_id *ent)
                            rinfo->mmio_base = (void *)(pci_rsc_desc->offset + pci_rsc_desc->start);
                            rinfo->mmio_base_phys = pci_rsc_desc->start;

-                            xprintf("mmio_base dump:\r\n");
-                            hexdump((uint8_t *) rinfo->mmio_base_phys, 0x100);
                        }
                    }
                }
@@ -2240,8 +2228,6 @@ int32_t radeonfb_pci_register(int32_t handle, const struct pci_device_id *ent)
                    rinfo->io_base = (void *)(pci_rsc_desc->offset + pci_rsc_desc->start);
                    rinfo->io_base_phys = pci_rsc_desc->start;

-                    xprintf("io_base dump:\r\n");
-                    hexdump((uint8_t *) rinfo->io_base_phys, 0x100);
                }
            }
            flags = pci_rsc_desc->flags;
--- a/sys/BaS.c
+++ b/sys/BaS.c
@@ -31,6 +31,7 @@
 #include "bas_printf.h"
 #include "bas_string.h"
 #include "bas_types.h"
+#include "bas_utils.h"
 #include "sd_card.h"
 #include "wait.h"

@@ -222,6 +223,7 @@ void enable_coldfire_interrupts()

    MCF_EPORT_EPPAR = 0xaaa8;               /* all interrupts on falling edge */

+#ifdef _NOT_USED_
 #if defined(MACHINE_FIREBEE)
    /*
     * TIN0 on the Coldfire is connected to the FPGA. TIN0 triggers every write
@@ -234,7 +236,7 @@ void enable_coldfire_interrupts()
                     MCF_INTC_ICR_IP(6);    /* interrupt level 7, interrupt priority 7 */
    MCF_INTC_IMRH = 0xbffffffe;             /* psc3 and timer 0 int on */
 #endif
-
+#endif
    xprintf("finished\r\n");
 }

@@ -366,7 +368,7 @@ void init_isr(void)
                       MCF_XLB_XARB_IMR_TTME |          /* TBST/TSIZ mismatch interrupt */
                       MCF_XLB_XARB_IMR_BAE;            /* bus activity tenure timeout interrupt */

-    if (!isr_register_handler(64 + INT_SOURCE_PCIARB, 5, 1, pciarb_interrupt_handler, NULL, NULL))
+    if (!isr_register_handler(64 + INT_SOURCE_PCIARB, 5, 0, pciarb_interrupt_handler, NULL, NULL))
    {
        dbg("Error: unable to register isr for PCIARB interrupts\r\n");

@@ -443,7 +445,7 @@ void BaS(void)
    /*
     * memory setup
     */
-    memset((void *) 0x200, 0, 0x400);
+    // memset((void *) 0x200, 0, 0x400);

 #if defined(MACHINE_FIREBEE)
    /* set Falcon bus control register */
@@ -509,6 +511,12 @@ void BaS(void)
        MCF_MMU_MMUCR = 0;  /* MMU off */
        NOP();              /* force pipeline sync */

+
+        /*
+         * FireTOS wants to have the TOS system variables cleared
+         */
+        memset((void *) 0x400, 0, 0x400);
+
        /* ST RAM */

        * (uint32_t *) 0x42e = STRAM_END;   /* phystop TOS system variable */
@@ -528,6 +536,16 @@ void BaS(void)
        FireTOS();  // Should never return
    }

+    /*
+     * fix initial pc/sp in ST RAM for FreeMiNT. It expects valid values there
+     * like on original STs (where these values reside in ROM) and uses them on
+     * CTRL-ALT-DELETE reboots.
+     */
+    struct rom_header *bas_header = (struct rom_header *) TARGET_ADDRESS;
+    struct rom_header *stram_header = (struct rom_header *) 0x0;
+
+    *stram_header = *bas_header;
+
    xprintf("call EmuTOS\r\n");
    struct rom_header *os_header = (struct rom_header *) TOS;
    os_header->initial_pc();
--- a/sys/exceptions.S
+++ b/sys/exceptions.S
@@ -247,7 +247,7 @@ init_vec_loop:
 #ifdef MACHINE_FIREBEE

 // timer vectors (triggers when vbashi gets changed, used for video page copy)
-        move.l  a1,(INT_SOURCE_GPT0 + 64) * 4(a0)
+        // move.l  a1,(INT_SOURCE_GPT0 + 64) * 4(a0)
 #endif /* MACHINE_FIREBEE */

        move.l  (sp)+,a2                        // Restore registers
@@ -326,8 +326,9 @@ access:
        move.l  4(a6),-(sp)                     // push format_status
        move.l  8(a6),-(sp)                     // pc at exception
        move.l  MCF_MMU_MMUAR,-(sp)             // MMU fault address
-        move.l  MCF_MMU_MMUSR,-(sp)             // MMU status regisrter
-        move.w  #0x2300,sr                      // can lower interrupt mask now that MMU status is safe
+        move.l  MCF_MMU_MMUSR,-(sp)             // MMU status register
+        // probably doesn't make sense since we still have a potential unmapped MMU page
+        // move.w  #0x2300,sr                      // can lower interrupt mask now that MMU status is safe
        jsr     _mmutr_miss                     // call C routine
        lea     4 * 4(sp),sp                    // adjust stack

@@ -341,7 +342,9 @@ access:
 bus_error:
        movem.l (sp),d0-d1/a0-a1                // restore registers
        unlk    a6
-        bra     std_exc_vec                     // FIXME: this seems to be bogous...
+        move.l  0x08,-(sp)
+        rts
+        // bra     std_exc_vec                     // FIXME: this seems to be bogous...

 zero_divide:
        move.w  #0x2700,sr                      // disable interrupt
@@ -581,7 +584,7 @@ _lowlevel_isr_handler:
        jsr     _isr_execute_handler            // call the C handler
        addq.l	#4,sp                           // adjust stack
        tst.b	d0                              // handled?
-        beq	lowlevel_forward                    // no, forward it to TOS
+        beq     lowlevel_forward                // no, forward it to TOS

        movem.l	(sp),d0-d1/a0-a1                // restore registers
        unlk	a6
--- a/sys/init_fpga.c
+++ b/sys/init_fpga.c
@@ -95,13 +95,15 @@ bool init_fpga(void)
    int i;

    xprintf("FPGA load config...\r\n");
+    xprintf("_FPGA_JTAG_LOADED = 0x%x\r\n", _FPGA_JTAG_LOADED);
+    xprintf("_FPGA_JTAG_VALID = 0x%x\r\n", _FPGA_JTAG_VALID);
    if (_FPGA_JTAG_LOADED == 1 && _FPGA_JTAG_VALID == VALID_JTAG)
    {
        xprintf("detected _FPGA_JTAG_LOADED flag. FPGA config skipped.\r\n");

        /* reset the flag so that next boot will load config again from flash */
-        _FPGA_JTAG_LOADED = 0;
-        _FPGA_JTAG_VALID = 0;
+        // _FPGA_JTAG_LOADED = 0;
+        // _FPGA_JTAG_VALID = 0;

        return true;
    }
@@ -180,6 +182,16 @@ bool init_fpga(void)

        xprintf("finished (took %f seconds).\r\n", time / 1000.0);
        config_gpio_for_jtag_config();
+
+        /*
+         * assure skipping fpga load on warm boot
+         */
+
+        _FPGA_JTAG_LOADED = 1;
+        _FPGA_JTAG_VALID = VALID_JTAG;
+
+        xprintf("SRAM now set to FPGA load skip\r\n");
+
        return true;
    }
    xprintf("FAILED!\r\n");
--- a/sys/interrupts.c
+++ b/sys/interrupts.c
@@ -37,7 +37,7 @@
 #include "dma.h"
 #include "pci.h"

-//#define IRQ_DEBUG
+// #define IRQ_DEBUG
 #if defined(IRQ_DEBUG)
 #define dbg(format, arg...) do { xprintf("DEBUG %s(): " format, __FUNCTION__, ##arg); } while (0)
 #else
@@ -61,6 +61,7 @@ struct isrentry

 static struct isrentry isrtab[MAX_ISR_ENTRY];      /* list of interrupt service routines */

+
 /*
 * clear the table of interrupt service handlers
 */
@@ -235,6 +236,7 @@ bool isr_execute_handler(int vector)
    return true;
 }

+#if defined(MACHINE_FIREBEE)
 /*
 * PIC interrupt handler for Firebee
 *
@@ -247,24 +249,25 @@ bool pic_interrupt_handler(void *arg1, void *arg2)

    dbg("PIC interrupt\r\n");

-    rcv_byte = MCF_PSC3_PSCRB_8BIT;
+    rcv_byte = read_pic_byte();
    if (rcv_byte == 2)                  /* PIC requests RTC data */
    {
-        uint8_t *rtc_reg = (uint8_t *) 0xffff8961;
-        uint8_t *rtc_data = (uint8_t *) 0xffff8963;
+        volatile uint8_t *rtc_reg = (uint8_t *) 0xffff8961;
+        volatile uint8_t *rtc_data = (uint8_t *) 0xffff8963;
        int index = 0;

        err("PIC interrupt: requesting RTC data\r\n");

-        MCF_PSC3_PSCTB_8BIT = 0x82;     // header byte to PIC
+        write_pic_byte(0x82);     // header byte to PIC
        do
        {
-            *rtc_reg = 0;
-            MCF_PSC3_PSCTB_8BIT = *rtc_data;
-        } while (index++ < 64);
+            *rtc_reg = index;
+            write_pic_byte(*rtc_data);
+        } while (++index < 64);
    }
    return true;
 }
+#endif /* MACHINE_FIREBEE */

 bool xlbpci_interrupt_handler(void *arg1, void *arg2)
 {
@@ -476,7 +479,7 @@ bool irq7_handler(void)
 */
 bool gpt0_interrupt_handler(void *arg0, void *arg1)
 {
-    dbg("handler called\n\r");
+    dbg("gpt0 handler called\n\r");

    MCF_GPT0_GMS &= ~1;     /* rearm trigger */
    NOP();
@@ -485,3 +488,26 @@ bool gpt0_interrupt_handler(void *arg0, void *arg1)
    return true;
 }
 #endif /* MACHINE_FIREBEE */
+
+
+uint32_t set_ipl(uint32_t ipl)
+{
+    uint32_t ret;
+
+    __asm__ __volatile__(
+        "		move.w	sr,%[ret]\r\n"			/* retrieve status register */
+        "		andi.l	#0x07,%[ipl]\n\t"		/* mask out ipl bits on new value */
+        "		lsl.l	#8,%[ipl]\n\t"			/* shift them to position */
+        "		move.l	%[ret],d0\n\t"			/* retrieve original value */
+        "		andi.l	#0x0000f8ff,d0\n\t"		/* clear ipl part */
+        "		or.l	%[ipl],d0\n\t"			/* or in new value */
+        "		move.w	d0,sr\n\t"				/* put it in place */
+        "		andi.l	#0x0700,%[ret]\r\n"		/* mask out ipl bits */
+        "		lsr.l	#8,%[ret]\r\n"			/* shift them to position */
+        : [ret] "=&d" (ret)		/* output */
+        : [ipl] "d" (ipl)		/* input */
+        : "cc"	/* clobber */
+    );
+
+    return ret;
+}
--- a/sys/mmu.c
+++ b/sys/mmu.c
@@ -247,7 +247,7 @@ static struct virt_to_phys translation[] =

 static int num_translations = sizeof(translation) / sizeof(struct virt_to_phys);

-static inline int32_t lookup_phys(int32_t virt)
+static inline uint32_t lookup_phys(int32_t virt)
 {
    int i;

@@ -263,36 +263,27 @@ static inline int32_t lookup_phys(int32_t virt)
    return -1;
 }

-struct mmu_page_descriptor
-{
-    uint8_t cache_mode          : 2;
-    uint8_t supervisor_protect  : 1;
-    uint8_t read                : 1;
-    uint8_t write               : 1;
-    uint8_t execute             : 1;
-    uint8_t global              : 1;
-    uint8_t locked              : 1;
-};

 /*
 * page descriptors. Size depending on DEFAULT_PAGE_SIZE, either 1M (resulting in 512
 * bytes size) or 8k pages (64k descriptor array size)
 */
-static struct mmu_page_descriptor pages[SDRAM_SIZE / DEFAULT_PAGE_SIZE];
+#define NUM_PAGES    (SDRAM_SIZE / SIZE_DEFAULT)
+static struct mmu_page_descriptor pages[NUM_PAGES];


-int mmu_map_instruction_page(int32_t virt, uint8_t asid)
+int mmu_map_instruction_page(uint32_t virt, uint8_t asid)
 {
-    const uint32_t size_mask = ~ (DEFAULT_PAGE_SIZE - 1);       /* pagesize */
-    int page_index = (virt & size_mask) / DEFAULT_PAGE_SIZE;    /* index into page_descriptor array */
-    struct mmu_page_descriptor *page = &pages[page_index];      /* attributes of page to map */
+    const uint32_t size_mask = ~ (SIZE_DEFAULT - 1);                /* pagesize */
+    int page_index = (virt & size_mask) / SIZE_DEFAULT;             /* index into page_descriptor array */
+    struct mmu_page_descriptor *page = &pages[page_index];          /* attributes of page to map */
    int ipl;
-    int32_t phys = lookup_phys(virt);                           /* virtual to physical translation of page */
+    uint32_t phys = lookup_phys(virt);                               /* virtual to physical translation of page */

-    if (phys == -1)
+    if (phys == (uint32_t) -1)
    {
        /* no valid mapping found, caller will issue a bus error in return */
-
+        dbg("no mapping found\r\n");
        return 0;
    }

@@ -315,7 +306,7 @@ int mmu_map_instruction_page(int32_t virt, uint8_t asid)
        MCF_MMU_MMUTR_V;                                            /* valid */

    MCF_MMU_MMUDR = (phys & size_mask) |                            /* physical address */
-        MCF_MMU_MMUDR_SZ(DEFAULT_PAGE_SIZE) |                       /* page size */
+        MCF_MMU_MMUDR_SZ(MMU_PAGE_SIZE_DEFAULT) |                   /* page size */
        MCF_MMU_MMUDR_CM(page->cache_mode) |                        /* cache mode */
        (page->supervisor_protect ? MCF_MMU_MMUDR_SP : 0) |         /* supervisor protect */
        (page->read ? MCF_MMU_MMUDR_R : 0) |                        /* read access enable */
@@ -336,19 +327,19 @@ int mmu_map_instruction_page(int32_t virt, uint8_t asid)
    return 1;
 }

-int mmu_map_data_page(int32_t virt, uint8_t asid)
+int mmu_map_data_page(uint32_t virt, uint8_t asid)
 {
    uint16_t ipl;
-    const uint32_t size_mask = ~ (DEFAULT_PAGE_SIZE - 1);       /* pagesize */
-    int page_index = (virt & size_mask) / DEFAULT_PAGE_SIZE;    /* index into page_descriptor array */
+    const uint32_t size_mask = ~ (SIZE_DEFAULT - 1);            /* pagesize */
+    int page_index = (virt & size_mask) / SIZE_DEFAULT;         /* index into page_descriptor array */
    struct mmu_page_descriptor *page = &pages[page_index];      /* attributes of page to map */

-    int32_t phys = lookup_phys(virt);                           /* virtual to physical translation of page */
+    uint32_t phys = lookup_phys(virt);                           /* virtual to physical translation of page */

-    if (phys == -1)
+    if (phys == (uint32_t) -1)
    {
        /* no valid mapping found, caller will issue a bus error in return */
-
+        dbg("no mapping found\r\n");
        return 0;
    }

@@ -369,7 +360,7 @@ int mmu_map_data_page(int32_t virt, uint8_t asid)
        MCF_MMU_MMUTR_V;                                            /* valid */

    MCF_MMU_MMUDR = (phys & size_mask) |                            /* physical address */
-        MCF_MMU_MMUDR_SZ(DEFAULT_PAGE_SIZE) |                       /* page size */
+        MCF_MMU_MMUDR_SZ(MMU_PAGE_SIZE_DEFAULT) |                   /* page size */
        MCF_MMU_MMUDR_CM(page->cache_mode) |                        /* cache mode */
        (page->supervisor_protect ? MCF_MMU_MMUDR_SP : 0) |         /* supervisor protect */
        (page->read ? MCF_MMU_MMUDR_R : 0) |                        /* read access enable */
@@ -398,7 +389,7 @@ int mmu_map_data_page(int32_t virt, uint8_t asid)
 * per instruction as a minimum, more for performance. Thus locked pages (that can't be touched by the
 * LRU algorithm) should be used sparsingly.
 */
-int mmu_map_page(int32_t virt, int32_t phys, enum mmu_page_size sz, uint8_t page_id, const struct mmu_page_descriptor *flags)
+uint32_t mmu_map_page(uint32_t virt, uint32_t phys, enum mmu_page_size sz, uint8_t page_id, const struct mmu_page_descriptor *flags)
 {
    int size_mask;
    int ipl;
@@ -432,17 +423,18 @@ int mmu_map_page(int32_t virt, int32_t phys, enum mmu_page_size sz, uint8_t page

    ipl = set_ipl(7);       /* do not disturb */

-    MCF_MMU_MMUTR = ((int) virt & size_mask) |                      /* virtual address */
+    MCF_MMU_MMUTR = (virt & size_mask) |                            /* virtual address */
        MCF_MMU_MMUTR_ID(page_id) |                                 /* address space id (ASID) */
        (flags->global ? MCF_MMU_MMUTR_SG : 0) |                    /* shared global */
        MCF_MMU_MMUTR_V;                                            /* valid */

-    MCF_MMU_MMUDR = ((int) phys & size_mask) |                      /* physical address */
+    MCF_MMU_MMUDR = (phys & size_mask) |                            /* physical address */
        MCF_MMU_MMUDR_SZ(sz) |                                      /* page size */
        MCF_MMU_MMUDR_CM(flags->cache_mode) |
        (flags->read ? MCF_MMU_MMUDR_R : 0) |                       /* read access enable */
        (flags->write ? MCF_MMU_MMUDR_W : 0) |                      /* write access enable */
        (flags->execute ? MCF_MMU_MMUDR_X : 0) |                    /* execute access enable */
+        (flags->supervisor_protect ? MCF_MMU_MMUDR_SP : 0) |        /* supervisor protect */
        (flags->locked ? MCF_MMU_MMUDR_LK : 0);

    MCF_MMU_MMUOR = MCF_MMU_MMUOR_ACC |     /* access TLB, data */
@@ -455,7 +447,7 @@ int mmu_map_page(int32_t virt, int32_t phys, enum mmu_page_size sz, uint8_t page

    set_ipl(ipl);

-    dbg("mapped virt=0x%08x to phys=0x%08x\r\n", virt, phys);
+    dbg("mapped virt=0x%08x to phys=0x%08x size mask 0x%lx\r\n", virt, phys, size_mask);

    return 1;
 }
@@ -476,26 +468,24 @@ void mmu_init(void)
    /*
     * prelaminary initialization of page descriptor 0 (root) table
     */
-    for (i = 0; i < sizeof(pages) / sizeof(struct mmu_page_descriptor); i++)
+    for (i = 0; i < NUM_PAGES; i++)
    {
-        uint32_t addr = i * DEFAULT_PAGE_SIZE;
+        uint32_t addr = i * SIZE_DEFAULT;

 #if defined(MACHINE_FIREBEE)
        if (addr >= 0x00f00000UL && addr < 0x00ffffffUL)        /* Falcon I/O area on the Firebee */
        {
            pages[i].cache_mode = CACHE_NOCACHE_PRECISE;
-            pages[i].execute = 0;
+            pages[i].supervisor_protect = 1;
            pages[i].read = 1;
            pages[i].write = 1;
            pages[i].execute = 0;
            pages[i].global = 1;
-            pages[i].supervisor_protect = 1;
        }
        else if (addr >= 0x0UL && addr < 0x00e00000UL)          /* ST-RAM, potential video memory */
        {
            pages[i].cache_mode = CACHE_WRITETHROUGH;
-            pages[i].execute = 1;
-            pages[i].supervisor_protect = 0;
+            pages[i].supervisor_protect = 0; // (addr == 0x0L ? 1 : 0);
            pages[i].read = 1;
            pages[i].write = 1;
            pages[i].execute = 1;
@@ -504,24 +494,31 @@ void mmu_init(void)
        else if (addr >= 0x00e00000UL && addr < 0x00f00000UL)   /* EmuTOS */
        {
            pages[i].cache_mode = CACHE_COPYBACK;
-            pages[i].execute = 1;
-            pages[i].supervisor_protect = 1;
+            pages[i].supervisor_protect = 0;
            pages[i].read = 1;
            pages[i].write = 0;
            pages[i].execute = 1;
            pages[i].global = 1;
        }
+        else if (addr >= 0x00000000 && addr <= 0x00010000)      /* first Megabyte of ST RAM */
+        {
+            pages[i].cache_mode = CACHE_COPYBACK;
+            pages[i].supervisor_protect = 0;
+            pages[i].read = 1;
+            pages[i].write = 1;
+            pages[i].execute = 1;
+            pages[i].global = 1;
+        }
        else
        {
            pages[i].cache_mode = CACHE_COPYBACK;
-            pages[i].execute = 1;
+            pages[i].supervisor_protect = 0;
            pages[i].read = 1;
            pages[i].write = 1;
-            pages[i].supervisor_protect = 0;
+            pages[i].execute = 1;
            pages[i].global = 1;
        }
        pages[i].locked = 0;                /* not locked */
-        pages[0].supervisor_protect = 0;    /* protect system vectors */

 #elif defined(MACHINE_M5484LITE)
        if (addr >= 0x60000000UL && addr < 0x70000000UL)        /* Compact Flash on the m5484lite */
@@ -562,7 +559,6 @@ void mmu_init(void)
            pages[i].global = 1;
        }
        pages[i].locked = 0;                /* not locked */
-        pages[0].supervisor_protect = 0;    /* protect system vectors */

 #elif defined(MACHINE_M54455)
        if (addr >= 0x60000000UL && addr < 0x70000000UL)        /* Compact Flash on the m5484lite */
@@ -605,26 +601,27 @@ void mmu_init(void)
            pages[i].global = 1;
        }
        pages[i].locked = 0;                /* not locked */
-        pages[0].supervisor_protect = 0;    /* protect system vectors */
 #else
 #error Unknown machine!
 #endif /* MACHINE_FIREBEE */
    }

-    set_asid(0);            /* do not use address extension (ASID provides virtual 48 bit addresses */
+    set_asid(0);                        /* do not use address extension (ASID provides virtual 48 bit addresses */
+
+    // pages[0].supervisor_protect = 1;    /* protect system vectors */

    /* set data access attributes in ACR0 and ACR1 */

    /* map PCI address space */
    set_acr0(ACR_W(0) |                             /* read and write accesses permitted */
-            ACR_SP(1) |                             /* supervisor and user mode access permitted */
+            //ACR_SP(1) |                             /* supervisor only access permitted */
            ACR_CM(ACR_CM_CACHE_INH_PRECISE) |      /* cache inhibit, precise */
            ACR_AMM(0) |                            /* control region > 16 MB */
            ACR_S(ACR_S_SUPERVISOR_MODE) |          /* match addresses in supervisor mode only */
            ACR_E(1) |                              /* enable ACR */
 #if defined(MACHINE_FIREBEE)
            ACR_ADMSK(0x7f) |                       /* cover 2GB area from 0x80000000 to 0xffffffff */
-            ACR_BA(0x80000000));                    /* (equals area from 3 to 4 GB */
+            ACR_BA(PCI_MEMORY_OFFSET));             /* (equals area from 3 to 4 GB */
 #elif defined(MACHINE_M5484LITE)
            ACR_ADMSK(0x7f) |                       /* cover 2 GB area from 0x80000000 to 0xffffffff */
            ACR_BA(PCI_MEMORY_OFFSET));
@@ -671,30 +668,18 @@ void mmu_init(void)
            ACR_ADMSK(0x7) |
            ACR_BA(0xe0000000));

-    /* disable ACR1 - 3, essentially disabling all of the above */

+    /* disable ACR3 */
    set_acr3(0x0);

    set_mmubar(MMUBAR + 1);     /* set and enable MMUBAR */

-    /* create locked TLB entries */
-
-    flags.cache_mode = CACHE_COPYBACK;
-    flags.supervisor_protect = 0;
-    flags.read = 1;
-    flags.write = 1;
-    flags.execute = 1;
-    flags.locked = true;
-
-    /* 0x00000000 - 0x00100000 (first MB of physical memory) locked virt = phys */
-    mmu_map_page(0x0, 0x0, MMU_PAGE_SIZE_1M, 0, &flags);
-
    /*
     * Make the TOS (in SDRAM) read-only
     * This maps virtual 0x00e0'0000 - 0x00ef'ffff to the same virtual address
     */
    flags.cache_mode = CACHE_COPYBACK;
-    flags.supervisor_protect = 0;
+    flags.supervisor_protect = 0;  // needs to stay like this or cf_flasher will choke */
    flags.read = 1;
    flags.write = 0;
    flags.execute = 1;
@@ -731,7 +716,7 @@ void mmu_init(void)
     * virtual address. This is also used (completely) when BaS is in RAM
     */
    flags.cache_mode = CACHE_COPYBACK;
-    flags.supervisor_protect = 1;
+    flags.supervisor_protect = 0;
    flags.read = 1;
    flags.write = 1;
    flags.execute = 1;
@@ -743,7 +728,7 @@ void mmu_init(void)
     * virtual address. Used uncached for drivers.
     */
    flags.cache_mode = CACHE_NOCACHE_PRECISE;
-    flags.supervisor_protect = 1;
+    flags.supervisor_protect = 0;
    flags.read = 1;
    flags.write = 1;
    flags.execute = 0;
@@ -774,22 +759,24 @@ uint32_t mmutr_miss(uint32_t mmu_sr, uint32_t fault_address, uint32_t pc, uint32

            if (!mmu_map_instruction_page(pc, 0))
            {
-                dbg("bus error\r\n");
+                dbg("ITLB miss bus error\r\n");
                return 1;   /* bus error */
            }

+#ifdef _NOT_USED_
            /* due to prefetch, it makes sense to map the next adjacent page also for ITLBs */
-            if (pc + DEFAULT_PAGE_SIZE < TARGET_ADDRESS)
+            if (pc + SIZE_DEFAULT < TARGET_ADDRESS)
            {
                /*
                 * only do this if the next page is still valid RAM
                 */
-                if (!mmu_map_instruction_page(pc + DEFAULT_PAGE_SIZE, 0))
+                if (!mmu_map_instruction_page(pc + MMU_DEFAULT_PAGE_SIZE, 0))
                {
-                    dbg("bus error\r\n");
+                    dbg("ITLB next page bus error\r\n");
                    return 1;   /* bus error */
                }
            }
+#endif /* _NOT_USED_ */
            break;

        case 0x08020000:    /* TLB miss on data write */
@@ -803,14 +790,58 @@ uint32_t mmutr_miss(uint32_t mmu_sr, uint32_t fault_address, uint32_t pc, uint32

            if (!mmu_map_data_page(fault_address, 0))
            {
-                dbg("bus error\r\n");
+                dbg("DTLB miss bus error\r\n");
                return 1;   /* bus error */
            }
            break;

+        case 0x0c010000:
+        case 0x08010000:
+            dbg("privilege violation accessing 0x%08x\r\n"
+                "FS = 0x%08x\r\n"
+                "MMUSR = 0x%08x\r\n"
+                "PC = 0x%08x\r\n",
+                fault_address, format_status, mmu_sr, pc);
+            dbg("fault = 0x%08x\r\n", fault);
+#ifdef _DOES_NOT_WORK_
+            /*
+             * check if its one of our "special cases" and map a user page on top of it if user
+             * mode access should be allowed
+             */
+            if (fault_address >= 1024 && fault_address < 0x00100000) /* ST-RAM */
+            {
+                struct mmu_page_descriptor flags =
+                {
+                    .cache_mode = CACHE_COPYBACK,
+                    .supervisor_protect = 0,
+                    .read = 1,
+                    .write = 1,
+                    .execute = 1,
+                    .global = 1,
+                    .locked = 0
+                };
+
+                uint32_t virt = fault_address & ~(SIZE_1K - 1);
+                uint32_t phys = (fault_address & (~(SIZE_1K - 1))) + 0x60000000;
+                dbg("mapping helper page virt=0x%08x to phys=0x%08x\r\n", virt, phys);
+                if (!mmu_map_page(virt, phys, MMU_PAGE_SIZE_1K, 0, &flags))
+                {
+                    dbg("privilege violation (bus error)\r\n");
+                    return 1;
+                }
+            }
+#endif
+            return 1;
+            break;
+
        /* else issue a bus error */
        default:
-            dbg("bus error\r\n");
+            dbg("bus error accessing 0x%08x\r\n"
+                "FS = 0x%08x\r\n"
+                "MMUSR = 0x%08x\r\n"
+                "PC = 0x%08x\r\n",
+                fault_address, format_status, mmu_sr, pc);
+            dbg("fault = 0x%08x\r\n", fault);
            return 1;       /* signal bus error to caller */
    }
 #ifdef DBG_MMU
@@ -846,14 +877,14 @@ uint32_t mmutr_miss(uint32_t mmu_sr, uint32_t fault_address, uint32_t pc, uint32
 *
 * return: 0 if failed (page not in translation table), 1 otherwise
 */
-int32_t mmu_map_data_page_locked(uint32_t virt, uint32_t size, int asid)
+uint32_t mmu_map_data_page_locked(uint32_t virt, uint32_t size, int asid)
 {
-    const uint32_t size_mask = ~ (DEFAULT_PAGE_SIZE - 1);       /* pagesize */
-    int page_index = (virt & size_mask) / DEFAULT_PAGE_SIZE;    /* index into page_descriptor array */
+    const uint32_t size_mask = ~ (SIZE_DEFAULT - 1);       /* pagesize */
+    int page_index = (virt & size_mask) / SIZE_DEFAULT;    /* index into page_descriptor array */
    struct mmu_page_descriptor *page = &pages[page_index];          /* attributes of page to map */
    int i = 0;

-    while (page_index * DEFAULT_PAGE_SIZE < virt + size)
+    while (page_index * SIZE_DEFAULT < virt + size)
    {
        if (page->locked)
        {
@@ -865,7 +896,7 @@ int32_t mmu_map_data_page_locked(uint32_t virt, uint32_t size, int asid)
            mmu_map_data_page(virt, 0);
            i++;
        }
-        virt += DEFAULT_PAGE_SIZE;
+        virt += SIZE_DEFAULT;
    }

    dbg("%d pages locked\r\n", i);
@@ -878,18 +909,18 @@ int32_t mmu_map_data_page_locked(uint32_t virt, uint32_t size, int asid)
 *
 * return: 0 if failed (page not found), 1 otherwise
 */
-int32_t mmu_unlock_data_page(uint32_t address, uint32_t size, int asid)
+uint32_t mmu_unlock_data_page(uint32_t address, uint32_t size, int asid)
 {
    int curr_asid;
-    const uint32_t size_mask = ~ (DEFAULT_PAGE_SIZE - 1);
-    int page_index = (address & size_mask) / DEFAULT_PAGE_SIZE;     /* index into page descriptor array */
+    const uint32_t size_mask = ~ (SIZE_DEFAULT - 1);
+    int page_index = (address & size_mask) / SIZE_DEFAULT;     /* index into page descriptor array */
    struct mmu_page_descriptor *page = &pages[page_index];

    curr_asid = set_asid(asid);         /* set asid to the one to search for */

    /* TODO: check for pages[] array bounds */

-    while (page_index * DEFAULT_PAGE_SIZE < address + size)
+    while (page_index * SIZE_DEFAULT < address + size)
    {
        MCF_MMU_MMUAR = address + page->supervisor_protect;
        MCF_MMU_MMUOR = MCF_MMU_MMUOR_STLB |        /* search TLB */
@@ -918,7 +949,7 @@ int32_t mmu_unlock_data_page(uint32_t address, uint32_t size, int asid)
    return 1;   /* success */
 }

-int32_t mmu_report_locked_pages(uint32_t *num_itlb, uint32_t *num_dtlb)
+uint32_t mmu_report_locked_pages(uint32_t *num_itlb, uint32_t *num_dtlb)
 {
    int i;
    int li = 0;
@@ -967,5 +998,5 @@ int32_t mmu_report_locked_pages(uint32_t *num_itlb, uint32_t *num_dtlb)

 uint32_t mmu_report_pagesize(void)
 {
-    return DEFAULT_PAGE_SIZE;
+    return SIZE_DEFAULT;
 }
--- a/sys/startcf.S
+++ b/sys/startcf.S
@@ -4,73 +4,74 @@
 * so it will be placed at the very beginning of the ROM.
 */

-		.equ	MCF_MMU_MMUCR, __MMUBAR + 0
+        .equ	MCF_MMU_MMUCR, __MMUBAR + 0

-		.globl	_rom_header
-		.globl	_rom_entry
+        .globl	_rom_header
+        .globl	_rom_entry

-		.extern	_initialize_hardware
-		.extern	_rt_mbar
+        .extern	_initialize_hardware
+        .extern	_rt_mbar

 /* ROM header */
 _rom_header:
-		/* The first long is supposed to be the initial SP.
-		 * We replace it by bra.s to allow running the ROM from the first byte.
-		 * Then we add a fake jmp instruction for pretty disassembly.
-		 */
-		bra.s	_rom_entry		// Short jump to the real entry point
-		.short	0x4ef9			// Fake jmp instruction
-		/* The second long is the initial PC */
-		.long	_rom_entry		// Real entry point
+        /* The first long is supposed to be the initial SP.
+         * We replace it by bra.s to allow running the ROM from the first byte.
+         * Then we add a fake jmp instruction for pretty disassembly.
+         */
+        bra.s	_rom_entry		// Short jump to the real entry point
+        .short	0x4ef9			// Fake jmp instruction
+        /* The second long is the initial PC */
+        .long	_rom_entry		// Real entry point

 /* ROM entry point */
 _rom_entry:
-		/* disable interrupts */
-		move.w #0x2700,sr
+        /* disable interrupts */
+        move.w #0x2700,sr

 #if !defined(MACHINE_M54455)			// MCF54455 does not have the MBAR register
-		/* Initialize MBAR */
-		move.l	#__MBAR,d0
-		movec	d0,MBAR
-		move.l	d0,_rt_mbar
+        /* Initialize MBAR */
+        move.l	#__MBAR,d0
+        movec	d0,MBAR
+        move.l	d0,_rt_mbar
 #endif

-		/* mmu off */
-		move.l	#__MMUBAR+1,d0
-		movec	d0,MMUBAR
+        /* mmu off */
+        move.l	#__MMUBAR+1,d0
+        movec	d0,MMUBAR

-		clr.l	d0
-		move.l	d0,MCF_MMU_MMUCR
+        clr.l	d0
+        move.l	d0,MCF_MMU_MMUCR
+        nop

 #if !defined(MACHINE_M54455)			// MCF54455 does not have RAMBAR0 and RAMBAR1 registers */

-		/* Initialize RAMBARs: locate SRAM and validate it */
-		move.l	#__RAMBAR0 + 0x7,d0 	// supervisor only
-		movec	d0,RAMBAR0
-		move.l	#__RAMBAR1 + 0x1,d0
-		movec	d0,RAMBAR1
+        /* Initialize RAMBARs: locate SRAM and validate it */
+        move.l	#__RAMBAR0 + 0x7,d0 	// supervisor only
+        movec	d0,RAMBAR0
+        move.l	#__RAMBAR1 + 0x1,d0
+        movec	d0,RAMBAR1
 #else
-		move.l	#__RAMBAR0 + 0x7,d0
-		movec	d0,RAMBAR
+        move.l	#__RAMBAR0 + 0x7,d0
+        movec	d0,RAMBAR
 #endif

-		/* set stack pointer to end of SRAM */
-		lea 	__SUP_SP,a7
-		move.l	#0,(sp)
+        /* set stack pointer to end of SRAM */
+        lea 	__SUP_SP,a7
+        move.l	#0,(sp)

-		/*
-		 * Initialize the processor caches.
-		 * The instruction cache is fully enabled.
-		 * The data cache is enabled, but cache-inhibited by default.
-		 * Later, the MMU will fully activate the data cache for specific areas.
-		 * It is important to enable both caches now, otherwise cpushl would hang.
-		 */
+        /*
+         * Initialize the processor caches.
+         * The instruction cache is fully enabled.
+         * The data cache is enabled, but cache-inhibited by default.
+         * Later, the MMU will fully activate the data cache for specific areas.
+         * It is important to enable both caches now, otherwise cpushl would hang.
+         */

-		move.l	#0xa50c8120,d0
-		movec	d0,cacr
-		andi.l	#0xfefbfeff,d0			// Clear invalidate bits
-		move.l	d0,_rt_cacr
+        move.l	#0xa50c8120,d0
+        movec	d0,cacr
+        andi.l	#0xfefbfeff,d0			// Clear invalidate bits
+        move.l	d0,_rt_cacr

-		/* initialize any hardware specific issues */
-		bra    _initialize_hardware
+        /* initialize any hardware specific issues */
+        bra    _initialize_hardware

--- a/sys/sysinit.c
+++ b/sys/sysinit.c
@@ -265,9 +265,6 @@ static void init_serial(void)
    MCF_PSC3_PSCCR = 0x05;
 #endif /* MACHINE_FIREBEE */

-    MCF_INTC_ICR32 = MCF_INTC_ICR_IL(7) |
-                     MCF_INTC_ICR_IL(4);      /* PSC3 interrupt vector. Do we need it? */
-
    xprintf("\r\nserial interfaces initialization: finished\r\n");
 }

@@ -428,13 +425,19 @@ static void init_fbcs()
    MCF_FBCS2_CSMR = (MCF_FBCS_CSMR_BAM_128M            /* F000'0000-F7FF'FFFF */
              | MCF_FBCS_CSMR_V);

-    MCF_FBCS3_CSAR = MCF_FBCS_CSAR_BA(0xF8000000);      /* Firebee new I/O address range */
+    MCF_FBCS3_CSAR = MCF_FBCS_CSAR_BA(0xF8000000);      /* Firebee SRAM */
    MCF_FBCS3_CSCR = MCF_FBCS_CSCR_PS_16                /* 16 bit port */
        | MCF_FBCS_CSCR_WS(32)                          /* 0 wait states */
        | MCF_FBCS_CSCR_AA;                             /* auto /TA acknowledge */
    MCF_FBCS3_CSMR = (MCF_FBCS_CSMR_BAM_64M             /* F800'0000-FBFF'FFFF */
              | MCF_FBCS_CSMR_V);

+    /*
+     * Note: burst read/write settings of the following FBCS are purely "cosmetical".
+     * The Coldfire FlexBus only "bursts" on a smaller port size than 32 bit up to 32 bit,
+     * i.e. it can burst on an 8 bit port up to 4 burst cycles or two on a 16 bit port.
+     * Enabling burst on a 32 bit port has no effect (unfortunately).
+     */
    MCF_FBCS4_CSAR = MCF_FBCS_CSAR_BA(0x40000000);      /* video ram area, FB_CS3 not used, decoded on FPGA */
    MCF_FBCS4_CSCR = MCF_FBCS_CSCR_PS_32                /* 32 bit port */
        | MCF_FBCS_CSCR_WS(32)                          /* 0 wait states */
@@ -583,11 +586,11 @@ void init_usb(void)

    do
    {
-        handle = pci_find_classcode(PCI_CLASS_SERIAL_USB | (1 << 25) | (1 << 26), index++);
+        handle = pci_find_classcode(PCI_CLASS_SERIAL_USB | PCI_FIND_BASE_CLASS | PCI_FIND_SUB_CLASS, index++);
        if (handle > 0)
        {
            long id;
-            long class;
+            long pci_class;

            xprintf("serial USB found at bus=0x%x, dev=0x%x, fnc=0x%x (0x%x)\r\n",
                    PCI_BUS_FROM_HANDLE(handle),
@@ -595,9 +598,9 @@ void init_usb(void)
                    PCI_FUNCTION_FROM_HANDLE(handle),
                    handle);
            id = pci_read_config_longword(handle, PCIIDR);
-            class = pci_read_config_longword(handle, PCIREV);
+            pci_class = pci_read_config_longword(handle, PCIREV);

-            if (PCI_SUBCLASS(class) == PCI_CLASS_SERIAL_USB_EHCI)
+            if (PCI_SUBCLASS(pci_class) == PCI_CLASS_SERIAL_USB_EHCI)
            {
                board = ehci_usb_pci_table;
                while (board->vendor)
@@ -612,7 +615,7 @@ void init_usb(void)
                    board++;
                }
            }
-            if (PCI_SUBCLASS(class) == PCI_CLASS_SERIAL_USB_OHCI)
+            if (PCI_SUBCLASS(pci_class) == PCI_CLASS_SERIAL_USB_OHCI)
            {
                board = ohci_usb_pci_table;
                while (board->vendor)
--- a/tos/Makefile
+++ b/tos/Makefile
@@ -3,7 +3,8 @@
 .PHONY: bascook
 .PHONY: vmem_test
 .PHONY: pci_test
-tos: jtagwait bascook vmem_test pci_test
+.PHONY: fpga_test
+tos: jtagwait bascook vmem_test pci_test fpga_test

 jtagwait:
 	$(MAKE) -C $@
@@ -17,3 +18,15 @@ vmem_test:
 pci_test:
 	$(MAKE) -C $@

+fpga_test:
+	$(MAKE) -C $@
+
+.PHONY: clean
+clean:
+	(cd jtagwait; make clean)
+	(cd bascook; make clean)
+	(cd vmem_test; make clean)
+	(cd pci_test; make clean)
+	(cd fpga_test; make clean)
+
+
--- a/tos/bascook/Makefile
+++ b/tos/bascook/Makefile
@@ -23,7 +23,9 @@ TOPDIR= ../..

 BAS_INCLUDE=-I$(TOPDIR)/../BaS_gcc/include

-INCLUDE=-I$(TOPDIR)/../libcmini/include $(BAS_INCLUDE) -nostdlib
+LIBCMINI=$(TOPDIR)/../libcmini/libcmini
+
+INCLUDE=-I$(LIBCMINI)/include $(BAS_INCLUDE) -nostdlib
 LIBS=-lcmini -nostdlib -lgcc
 CC=$(PREFIX)/bin/gcc

@@ -72,7 +74,7 @@ $(1)/objs/%.o:$(SRCDIR)/%.S

 $(1)_OBJS=$(patsubst %,$(1)/objs/%,$(OBJS))
 $(1)/$(APP): $$($(1)_OBJS)
-	$(CC) $$(CFLAGS) -o $$@ $(TOPDIR)/../libcmini/m5475/startup.o $$($(1)_OBJS) -L$(TOPDIR)/../libcmini/m5475 $(LIBS)
+	$(CC) $$(CFLAGS) -o $$@ $(LIBCMINI)/m5475/startup.o $$($(1)_OBJS) -L$(LIBCMINI)/m5475 $(LIBS)
 	$(STRIP) $$@
 endef
 $(foreach DIR,$(TRGTDIRS),$(eval $(call CC_TEMPLATE,$(DIR))))
@@ -90,8 +92,7 @@ clean:

 .PHONY: printvars
 printvars:
-	@$(foreach V,$(.VARIABLES), $(if $(filter-out environment% default automatic, $(origin $V)),$(warning $V=$($V))))
-
+	@$(foreach V,$(.VARIABLES), $(if $(filter-out environment% default automatic, $(origin $V)),$(warning $V=$($V)))) 
 ifneq (clean,$(MAKECMDGOALS))
 -include $(DEPEND)
 endif
--- a/tos/fpga_test/Makefile
+++ b/tos/fpga_test/Makefile
@@ -0,0 +1,106 @@
+CROSS=Y
+
+CROSSBINDIR_IS_Y=m68k-atari-mint-
+CROSSBINDIR_IS_N=
+
+CROSSBINDIR=$(CROSSBINDIR_IS_$(CROSS))
+
+UNAME := $(shell uname)
+ifeq ($(CROSS), Y)
+ifeq ($(UNAME),Linux)
+PREFIX=m68k-atari-mint
+HATARI=hatari
+else
+PREFIX=m68k-atari-mint
+HATARI=/usr/local/bin/hatari
+endif
+else
+PREFIX=/usr
+endif
+
+DEPEND=depend
+TOPDIR = ../..
+
+LIBCMINI=$(TOPDIR)/../libcmini/libcmini
+
+INCLUDE=-I$(LIBCMINI)/include -nostdlib
+LIBS=-lcmini -nostdlib -lgcc
+CC=$(PREFIX)/bin/gcc
+
+CC=$(CROSSBINDIR)gcc
+STRIP=$(CROSSBINDIR)strip
+STACK=$(CROSSBINDIR)stack
+
+APP=fpga_test.prg
+TEST_APP=$(APP)
+
+CFLAGS=\
+	-O0\
+	-g\
+	-Wl,-Map,mapfile\
+	-Wl,--defsym -Wl,__MBAR=0xff000000\
+	-Wl,--defsym -Wl,__MMUBAR=0xff040000\
+	-Wl,--defsym -Wl,__FPGA_JTAG_LOADED=0xff101000\
+	-Wl,--defsym -Wl,__FPGA_JTAG_VALID=0xff101004\
+	-Wl,--defsym -Wl,__VRAM=0x60000000\
+	-Wall
+
+SRCDIR=sources
+INCDIR=include
+INCLUDE+=-I$(INCDIR)
+
+CSRCS=\
+	$(SRCDIR)/fpga_test.c \
+	$(SRCDIR)/bas_printf.c
+
+ASRCS=$(SRCDIR)/printf_helper.S
+
+COBJS=$(patsubst $(SRCDIR)/%.o,%.o,$(patsubst %.c,%.o,$(CSRCS)))
+AOBJS=$(patsubst $(SRCDIR)/%.o,%.o,$(patsubst %.S,%.o,$(ASRCS)))
+OBJS=$(COBJS) $(AOBJS)
+
+TRGTDIRS=./m5475 ./m5475/mshort
+OBJDIRS=$(patsubst %,%/objs,$(TRGTDIRS))
+
+#
+# multilib flags. These must match m68k-atari-mint-gcc -print-multi-lib output
+#
+m5475/$(APP):CFLAGS += -mcpu=5475
+m5475/mshort/$(APP): CFLAGS += -mcpu=5475 -mshort
+
+all:$(patsubst %,%/$(APP),$(TRGTDIRS))
+#
+# generate pattern rules for multilib object files.
+#
+define CC_TEMPLATE
+$(1)/objs/%.o:$(SRCDIR)/%.c
+	$(CC) $$(CFLAGS) $(INCLUDE) -c $$< -o $$@
+
+$(1)/objs/%.o:$(SRCDIR)/%.S
+	$(CC) $$(CFLAGS) $(INCLUDE) -c $$< -o $$@
+
+$(1)_OBJS=$(patsubst %,$(1)/objs/%,$(OBJS))
+$(1)/$(APP): $$($(1)_OBJS)
+	$(CC) $$(CFLAGS) -o $$@ $(LIBCMINI)/$(1)/startup.o $$($(1)_OBJS) -L$(LIBCMINI)/$(1) $(LIBS)
+	#$(STRIP) $$@
+endef
+$(foreach DIR,$(TRGTDIRS),$(eval $(call CC_TEMPLATE,$(DIR))))
+
+$(DEPEND): $(ASRCS) $(CSRCS)
+	-rm -f $(DEPEND)
+	for d in $(TRGTDIRS);\
+		do $(CC) $(CFLAGS) $(INCLUDE) -M $(ASRCS) $(CSRCS) | sed -e "s#^\(.*\).o:#$$d/objs/\1.o:#" >> $(DEPEND); \
+    done
+
+
+clean:
+	@rm -f $(patsubst %,%/objs/*.o,$(TRGTDIRS)) $(patsubst %,%/$(APP),$(TRGTDIRS))
+	@rm -f $(DEPEND) mapfile
+
+.PHONY: printvars
+printvars:
+	@$(foreach V,$(.VARIABLES), $(if $(filter-out environment% default automatic, $(origin $V)),$(warning $V=$($V))))
+
+ifneq (clean,$(MAKECMDGOALS))
+-include $(DEPEND)
+endif
--- a/tos/fpga_test/include/MCF5475.h
+++ b/tos/fpga_test/include/MCF5475.h
@@ -0,0 +1,67 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_H__
+#define __MCF5475_H__
+
+#include <stdint.h>
+/***
+ * MCF5475 Derivative Memory map definitions from linker command files:
+ * __MBAR, __MMUBAR, __RAMBAR0, __RAMBAR0_SIZE, __RAMBAR1, __RAMBAR1_SIZE
+ * linker symbols must be defined in the linker command file.
+ */
+
+typedef uint32_t __attribute__((__may_alias__)) uint32_t_a;	/* a type to avoid gcc's complaints about pointer aliasing */
+
+extern uint8_t _MBAR[];
+extern uint8_t _MMUBAR[];
+extern uint8_t _RAMBAR0[];
+extern uint8_t _RAMBAR0_SIZE[];
+extern uint8_t _RAMBAR1[];
+extern uint8_t _RAMBAR1_SIZE[];
+
+#define MBAR_ADDRESS    (uint32_t)_MBAR
+#define MMUBAR_ADDRESS  (uint32_t)_MMUBAR
+#define RAMBAR0_ADDRESS (uint32_t)_RAMBAR0
+#define RAMBAR0_SIZE    (uint32_t)_RAMBAR0_SIZE
+#define RAMBAR1_ADDRESS (uint32_t)_RAMBAR1
+#define RAMBAR1_SIZE    (uint32_t)_RAMBAR1_SIZE
+
+
+#include "MCF5475_SIU.h"
+#include "MCF5475_MMU.h"
+#include "MCF5475_SDRAMC.h"
+#include "MCF5475_XLB.h"
+#include "MCF5475_CLOCK.h"
+#include "MCF5475_FBCS.h"
+#include "MCF5475_INTC.h"
+#include "MCF5475_GPT.h"
+#include "MCF5475_SLT.h"
+#include "MCF5475_GPIO.h"
+#include "MCF5475_PAD.h"
+#include "MCF5475_PCI.h"
+#include "MCF5475_PCIARB.h"
+#include "MCF5475_EPORT.h"
+#include "MCF5475_CTM.h"
+#include "MCF5475_DMA.h"
+#include "MCF5475_PSC.h"
+#include "MCF5475_DSPI.h"
+#include "MCF5475_I2C.h"
+#include "MCF5475_FEC.h"
+#include "MCF5475_USB.h"
+#include "MCF5475_SRAM.h"
+#include "MCF5475_SEC.h"
+
+#endif /* __MCF5475_H__ */
--- a/tos/fpga_test/include/MCF5475_CLOCK.h
+++ b/tos/fpga_test/include/MCF5475_CLOCK.h
@@ -0,0 +1,47 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_CLOCK_H__
+#define __MCF5475_CLOCK_H__
+
+
+/*********************************************************************
+*
+* Clock Module (CLOCK)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_CLOCK_SPCR                       (*(volatile uint32_t*)(&_MBAR[0x300]))
+
+
+/* Bit definitions and macros for MCF_CLOCK_SPCR */
+#define MCF_CLOCK_SPCR_MEMEN                 (0x1)
+#define MCF_CLOCK_SPCR_PCIEN                 (0x2)
+#define MCF_CLOCK_SPCR_FBEN                  (0x4)
+#define MCF_CLOCK_SPCR_CAN0EN                (0x8)
+#define MCF_CLOCK_SPCR_DMAEN                 (0x10)
+#define MCF_CLOCK_SPCR_FEC0EN                (0x20)
+#define MCF_CLOCK_SPCR_FEC1EN                (0x40)
+#define MCF_CLOCK_SPCR_USBEN                 (0x80)
+#define MCF_CLOCK_SPCR_PSCEN                 (0x200)
+#define MCF_CLOCK_SPCR_CAN1EN                (0x800)
+#define MCF_CLOCK_SPCR_CRYENA                (0x1000)
+#define MCF_CLOCK_SPCR_CRYENB                (0x2000)
+#define MCF_CLOCK_SPCR_COREN                 (0x4000)
+#define MCF_CLOCK_SPCR_PLLK                  (0x80000000)
+
+
+#endif /* __MCF5475_CLOCK_H__ */
--- a/tos/fpga_test/include/MCF5475_CTM.h
+++ b/tos/fpga_test/include/MCF5475_CTM.h
@@ -0,0 +1,76 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_CTM_H__
+#define __MCF5475_CTM_H__
+
+
+/*********************************************************************
+*
+* Comm Timer Module (CTM)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_CTM_CTCR0                        (*(volatile uint32_t*)(&_MBAR[0x7F00]))
+#define MCF_CTM_CTCR1                        (*(volatile uint32_t*)(&_MBAR[0x7F04]))
+#define MCF_CTM_CTCR2                        (*(volatile uint32_t*)(&_MBAR[0x7F08]))
+#define MCF_CTM_CTCR3                        (*(volatile uint32_t*)(&_MBAR[0x7F0C]))
+#define MCF_CTM_CTCR4                        (*(volatile uint32_t*)(&_MBAR[0x7F10]))
+#define MCF_CTM_CTCR5                        (*(volatile uint32_t*)(&_MBAR[0x7F14]))
+#define MCF_CTM_CTCR6                        (*(volatile uint32_t*)(&_MBAR[0x7F18]))
+#define MCF_CTM_CTCR7                        (*(volatile uint32_t*)(&_MBAR[0x7F1C]))
+#define MCF_CTM_CTCRF(x)                     (*(volatile uint32_t*)(&_MBAR[0x7F00 + ((x)*0x4)]))
+#define MCF_CTM_CTCRV(x)                     (*(volatile uint32_t*)(&_MBAR[0x7F10 + ((x-4)*0x4)]))
+
+
+/* Bit definitions and macros for MCF_CTM_CTCRF */
+#define MCF_CTM_CTCRF_CRV(x)                 (((x)&0xFFFF)<<0)
+#define MCF_CTM_CTCRF_S(x)                   (((x)&0xF)<<0x10)
+#define MCF_CTM_CTCRF_S_CLK_1                (0)
+#define MCF_CTM_CTCRF_S_CLK_2                (0x10000)
+#define MCF_CTM_CTCRF_S_CLK_4                (0x20000)
+#define MCF_CTM_CTCRF_S_CLK_8                (0x30000)
+#define MCF_CTM_CTCRF_S_CLK_16               (0x40000)
+#define MCF_CTM_CTCRF_S_CLK_32               (0x50000)
+#define MCF_CTM_CTCRF_S_CLK_64               (0x60000)
+#define MCF_CTM_CTCRF_S_CLK_128              (0x70000)
+#define MCF_CTM_CTCRF_S_CLK_256              (0x80000)
+#define MCF_CTM_CTCRF_S_CLK_EXT              (0x90000)
+#define MCF_CTM_CTCRF_PCT(x)                 (((x)&0x7)<<0x14)
+#define MCF_CTM_CTCRF_PCT_100                (0)
+#define MCF_CTM_CTCRF_PCT_50                 (0x100000)
+#define MCF_CTM_CTCRF_PCT_25                 (0x200000)
+#define MCF_CTM_CTCRF_PCT_12p5               (0x300000)
+#define MCF_CTM_CTCRF_PCT_6p25               (0x400000)
+#define MCF_CTM_CTCRF_PCT_OFF                (0x500000)
+#define MCF_CTM_CTCRF_M                      (0x800000)
+#define MCF_CTM_CTCRF_IM                     (0x1000000)
+#define MCF_CTM_CTCRF_I                      (0x80000000)
+
+/* Bit definitions and macros for MCF_CTM_CTCRV */
+#define MCF_CTM_CTCRV_CRV(x)                 (((x)&0xFFFFFF)<<0)
+#define MCF_CTM_CTCRV_PCT(x)                 (((x)&0x7)<<0x18)
+#define MCF_CTM_CTCRV_PCT_100                (0)
+#define MCF_CTM_CTCRV_PCT_50                 (0x1000000)
+#define MCF_CTM_CTCRV_PCT_25                 (0x2000000)
+#define MCF_CTM_CTCRV_PCT_12p5               (0x3000000)
+#define MCF_CTM_CTCRV_PCT_6p25               (0x4000000)
+#define MCF_CTM_CTCRV_PCT_OFF                (0x5000000)
+#define MCF_CTM_CTCRV_M                      (0x8000000)
+#define MCF_CTM_CTCRV_S                      (0x10000000)
+
+
+#endif /* __MCF5475_CTM_H__ */
--- a/tos/fpga_test/include/MCF5475_DMA.h
+++ b/tos/fpga_test/include/MCF5475_DMA.h
@@ -0,0 +1,234 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_DMA_H__
+#define __MCF5475_DMA_H__
+
+
+/*********************************************************************
+*
+* Multichannel DMA (DMA)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_DMA_TASKBAR                      (*(volatile uint32_t*)(&_MBAR[0x8000]))
+#define MCF_DMA_CP                           (*(volatile uint32_t*)(&_MBAR[0x8004]))
+#define MCF_DMA_EP                           (*(volatile uint32_t*)(&_MBAR[0x8008]))
+#define MCF_DMA_VP                           (*(volatile uint32_t*)(&_MBAR[0x800C]))
+#define MCF_DMA_PTD                          (*(volatile uint32_t*)(&_MBAR[0x8010]))
+#define MCF_DMA_DIPR                         (*(volatile uint32_t*)(&_MBAR[0x8014]))
+#define MCF_DMA_DIMR                         (*(volatile uint32_t*)(&_MBAR[0x8018]))
+#define MCF_DMA_TCR0                         (*(volatile uint16_t*)(&_MBAR[0x801C]))
+#define MCF_DMA_TCR1                         (*(volatile uint16_t*)(&_MBAR[0x801E]))
+#define MCF_DMA_TCR2                         (*(volatile uint16_t*)(&_MBAR[0x8020]))
+#define MCF_DMA_TCR3                         (*(volatile uint16_t*)(&_MBAR[0x8022]))
+#define MCF_DMA_TCR4                         (*(volatile uint16_t*)(&_MBAR[0x8024]))
+#define MCF_DMA_TCR5                         (*(volatile uint16_t*)(&_MBAR[0x8026]))
+#define MCF_DMA_TCR6                         (*(volatile uint16_t*)(&_MBAR[0x8028]))
+#define MCF_DMA_TCR7                         (*(volatile uint16_t*)(&_MBAR[0x802A]))
+#define MCF_DMA_TCR8                         (*(volatile uint16_t*)(&_MBAR[0x802C]))
+#define MCF_DMA_TCR9                         (*(volatile uint16_t*)(&_MBAR[0x802E]))
+#define MCF_DMA_TCR10                        (*(volatile uint16_t*)(&_MBAR[0x8030]))
+#define MCF_DMA_TCR11                        (*(volatile uint16_t*)(&_MBAR[0x8032]))
+#define MCF_DMA_TCR12                        (*(volatile uint16_t*)(&_MBAR[0x8034]))
+#define MCF_DMA_TCR13                        (*(volatile uint16_t*)(&_MBAR[0x8036]))
+#define MCF_DMA_TCR14                        (*(volatile uint16_t*)(&_MBAR[0x8038]))
+#define MCF_DMA_TCR15                        (*(volatile uint16_t*)(&_MBAR[0x803A]))
+#define MCF_DMA_PRIOR0                       (*(volatile uint8_t *)(&_MBAR[0x803C]))
+#define MCF_DMA_PRIOR1                       (*(volatile uint8_t *)(&_MBAR[0x803D]))
+#define MCF_DMA_PRIOR2                       (*(volatile uint8_t *)(&_MBAR[0x803E]))
+#define MCF_DMA_PRIOR3                       (*(volatile uint8_t *)(&_MBAR[0x803F]))
+#define MCF_DMA_PRIOR4                       (*(volatile uint8_t *)(&_MBAR[0x8040]))
+#define MCF_DMA_PRIOR5                       (*(volatile uint8_t *)(&_MBAR[0x8041]))
+#define MCF_DMA_PRIOR6                       (*(volatile uint8_t *)(&_MBAR[0x8042]))
+#define MCF_DMA_PRIOR7                       (*(volatile uint8_t *)(&_MBAR[0x8043]))
+#define MCF_DMA_PRIOR8                       (*(volatile uint8_t *)(&_MBAR[0x8044]))
+#define MCF_DMA_PRIOR9                       (*(volatile uint8_t *)(&_MBAR[0x8045]))
+#define MCF_DMA_PRIOR10                      (*(volatile uint8_t *)(&_MBAR[0x8046]))
+#define MCF_DMA_PRIOR11                      (*(volatile uint8_t *)(&_MBAR[0x8047]))
+#define MCF_DMA_PRIOR12                      (*(volatile uint8_t *)(&_MBAR[0x8048]))
+#define MCF_DMA_PRIOR13                      (*(volatile uint8_t *)(&_MBAR[0x8049]))
+#define MCF_DMA_PRIOR14                      (*(volatile uint8_t *)(&_MBAR[0x804A]))
+#define MCF_DMA_PRIOR15                      (*(volatile uint8_t *)(&_MBAR[0x804B]))
+#define MCF_DMA_PRIOR16                      (*(volatile uint8_t *)(&_MBAR[0x804C]))
+#define MCF_DMA_PRIOR17                      (*(volatile uint8_t *)(&_MBAR[0x804D]))
+#define MCF_DMA_PRIOR18                      (*(volatile uint8_t *)(&_MBAR[0x804E]))
+#define MCF_DMA_PRIOR19                      (*(volatile uint8_t *)(&_MBAR[0x804F]))
+#define MCF_DMA_PRIOR20                      (*(volatile uint8_t *)(&_MBAR[0x8050]))
+#define MCF_DMA_PRIOR21                      (*(volatile uint8_t *)(&_MBAR[0x8051]))
+#define MCF_DMA_PRIOR22                      (*(volatile uint8_t *)(&_MBAR[0x8052]))
+#define MCF_DMA_PRIOR23                      (*(volatile uint8_t *)(&_MBAR[0x8053]))
+#define MCF_DMA_PRIOR24                      (*(volatile uint8_t *)(&_MBAR[0x8054]))
+#define MCF_DMA_PRIOR25                      (*(volatile uint8_t *)(&_MBAR[0x8055]))
+#define MCF_DMA_PRIOR26                      (*(volatile uint8_t *)(&_MBAR[0x8056]))
+#define MCF_DMA_PRIOR27                      (*(volatile uint8_t *)(&_MBAR[0x8057]))
+#define MCF_DMA_PRIOR28                      (*(volatile uint8_t *)(&_MBAR[0x8058]))
+#define MCF_DMA_PRIOR29                      (*(volatile uint8_t *)(&_MBAR[0x8059]))
+#define MCF_DMA_PRIOR30                      (*(volatile uint8_t *)(&_MBAR[0x805A]))
+#define MCF_DMA_PRIOR31                      (*(volatile uint8_t *)(&_MBAR[0x805B]))
+#define MCF_DMA_IMCR                         (*(volatile uint32_t*)(&_MBAR[0x805C]))
+#define MCF_DMA_TSKSZ0                       (*(volatile uint32_t*)(&_MBAR[0x8060]))
+#define MCF_DMA_TSKSZ1                       (*(volatile uint32_t*)(&_MBAR[0x8064]))
+#define MCF_DMA_DBGCOMP0                     (*(volatile uint32_t*)(&_MBAR[0x8070]))
+#define MCF_DMA_DBGCOMP2                     (*(volatile uint32_t*)(&_MBAR[0x8074]))
+#define MCF_DMA_DBGCTL                       (*(volatile uint32_t*)(&_MBAR[0x8078]))
+#define MCF_DMA_TCR(x)                       (*(volatile uint16_t*)(&_MBAR[0x801C + ((x)*0x2)]))
+#define MCF_DMA_PRIOR(x)                     (*(volatile uint8_t *)(&_MBAR[0x803C + ((x)*0x1)]))
+
+
+/* Bit definitions and macros for MCF_DMA_TASKBAR */
+#define MCF_DMA_TASKBAR_TASK_BASE_ADDRESS(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DMA_CP */
+#define MCF_DMA_CP_DESCRIPTOR_POINTER(x)     (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DMA_EP */
+#define MCF_DMA_EP_DESCRIPTOR_POINTER(x)     (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DMA_VP */
+#define MCF_DMA_VP_VARIABLE_POINTER(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DMA_PTD */
+#define MCF_DMA_PTD_PCTL0                    (0x1)
+#define MCF_DMA_PTD_PCTL1                    (0x2)
+#define MCF_DMA_PTD_PCTL13                   (0x2000)
+#define MCF_DMA_PTD_PCTL14                   (0x4000)
+#define MCF_DMA_PTD_PCTL15                   (0x8000)
+
+/* Bit definitions and macros for MCF_DMA_DIPR */
+#define MCF_DMA_DIPR_TASK(x)                 (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DMA_DIMR */
+#define MCF_DMA_DIMR_TASK(x)                 (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DMA_TCR */
+#define MCF_DMA_TCR_ASTSKNUM(x)              (((x)&0xF)<<0)
+#define MCF_DMA_TCR_HLDINITNUM               (0x20)
+#define MCF_DMA_TCR_HIPRITSKEN               (0x40)
+#define MCF_DMA_TCR_ASTRT                    (0x80)
+#define MCF_DMA_TCR_INITNUM(x)               (((x)&0x1F)<<0x8)
+#define MCF_DMA_TCR_ALWINIT                  (0x2000)
+#define MCF_DMA_TCR_V                        (0x4000)
+#define MCF_DMA_TCR_EN                       (0x8000)
+
+/* Bit definitions and macros for MCF_DMA_PRIOR */
+#define MCF_DMA_PRIOR_PRI(x)                 (((x)&0x7)<<0)
+#define MCF_DMA_PRIOR_HLD                    (0x80)
+
+/* Bit definitions and macros for MCF_DMA_IMCR */
+#define MCF_DMA_IMCR_IMC16(x)	(((x)&0x3)<<0)
+#define MCF_DMA_IMCR_IMC17(x)	(((x)&0x3)<<0x2)
+#define MCF_DMA_IMCR_IMC18(x)	(((x)&0x3)<<0x4)
+#define MCF_DMA_IMCR_IMC19(x)	(((x)&0x3)<<0x6)
+#define MCF_DMA_IMCR_IMC20(x)	(((x)&0x3)<<0x8)
+#define MCF_DMA_IMCR_IMC21(x)	(((x)&0x3)<<0xA)
+#define MCF_DMA_IMCR_IMC22(x)	(((x)&0x3)<<0xC)
+#define MCF_DMA_IMCR_IMC23(x)	(((x)&0x3)<<0xE)
+#define MCF_DMA_IMCR_IMC24(x)	(((x)&0x3)<<0x10)
+#define MCF_DMA_IMCR_IMC25(x)	(((x)&0x3)<<0x12)
+#define MCF_DMA_IMCR_IMC26(x)	(((x)&0x3)<<0x14)
+#define MCF_DMA_IMCR_IMC27(x)	(((x)&0x3)<<0x16)
+#define MCF_DMA_IMCR_IMC28(x)	(((x)&0x3)<<0x18)
+#define MCF_DMA_IMCR_IMC29(x)	(((x)&0x3)<<0x1A)
+#define MCF_DMA_IMCR_IMC30(x)	(((x)&0x3)<<0x1C)
+#define MCF_DMA_IMCR_IMC31(x)	(((x)&0x3)<<0x1E)
+
+
+#define MCF_DMA_IMCR_IMC16_FEC0RX    (0x00000000)
+#define MCF_DMA_IMCR_IMC17_FEC0TX    (0x00000000)
+#define MCF_DMA_IMCR_IMC18_FEC0RX    (0x00000020)
+#define MCF_DMA_IMCR_IMC19_FEC0TX    (0x00000080)
+#define MCF_DMA_IMCR_IMC20_FEC1RX    (0x00000100)
+#define MCF_DMA_IMCR_IMC21_DREQ1     (0x00000000)
+#define MCF_DMA_IMCR_IMC21_FEC1TX    (0x00000400)
+#define MCF_DMA_IMCR_IMC22_FEC0RX    (0x00001000)
+#define MCF_DMA_IMCR_IMC23_FEC0TX    (0x00004000)
+#define MCF_DMA_IMCR_IMC24_CTM0      (0x00010000)
+#define MCF_DMA_IMCR_IMC24_FEC1RX    (0x00020000)
+#define MCF_DMA_IMCR_IMC25_CTM1      (0x00040000)
+#define MCF_DMA_IMCR_IMC25_FEC1TX    (0x00080000)
+#define MCF_DMA_IMCR_IMC26_USBEP4    (0x00000000)
+#define MCF_DMA_IMCR_IMC26_CTM2      (0x00200000)
+#define MCF_DMA_IMCR_IMC27_USBEP5    (0x00000000)
+#define MCF_DMA_IMCR_IMC27_CTM3      (0x00800000)
+#define MCF_DMA_IMCR_IMC28_USBEP6    (0x00000000)
+#define MCF_DMA_IMCR_IMC28_CTM4      (0x01000000)
+#define MCF_DMA_IMCR_IMC28_DREQ1     (0x02000000)
+#define MCF_DMA_IMCR_IMC28_PSC2RX    (0x03000000)
+#define MCF_DMA_IMCR_IMC29_DREQ1     (0x04000000)
+#define MCF_DMA_IMCR_IMC29_CTM5      (0x08000000)
+#define MCF_DMA_IMCR_IMC29_PSC2TX    (0x0C000000)
+#define MCF_DMA_IMCR_IMC30_FEC1RX    (0x00000000)
+#define MCF_DMA_IMCR_IMC30_CTM6      (0x10000000)
+#define MCF_DMA_IMCR_IMC30_PSC3RX    (0x30000000)
+#define MCF_DMA_IMCR_IMC31_FEC1TX    (0x00000000)
+#define MCF_DMA_IMCR_IMC31_CTM7      (0x80000000)
+#define MCF_DMA_IMCR_IMC31_PSC3TX    (0xC0000000)
+
+/* Bit definitions and macros for MCF_DMA_TSKSZ0 */
+#define MCF_DMA_TSKSZ0_DSTSZ7(x)             (((x)&0x3)<<0)
+#define MCF_DMA_TSKSZ0_SRCSZ7(x)             (((x)&0x3)<<0x2)
+#define MCF_DMA_TSKSZ0_DSTSZ6(x)             (((x)&0x3)<<0x4)
+#define MCF_DMA_TSKSZ0_SRCSZ6(x)             (((x)&0x3)<<0x6)
+#define MCF_DMA_TSKSZ0_DSTSZ5(x)             (((x)&0x3)<<0x8)
+#define MCF_DMA_TSKSZ0_SRCSZ5(x)             (((x)&0x3)<<0xA)
+#define MCF_DMA_TSKSZ0_DSTSZ4(x)             (((x)&0x3)<<0xC)
+#define MCF_DMA_TSKSZ0_SRCSZ4(x)             (((x)&0x3)<<0xE)
+#define MCF_DMA_TSKSZ0_DSTSZ3(x)             (((x)&0x3)<<0x10)
+#define MCF_DMA_TSKSZ0_SRCSZ3(x)             (((x)&0x3)<<0x12)
+#define MCF_DMA_TSKSZ0_DSTSZ2(x)             (((x)&0x3)<<0x14)
+#define MCF_DMA_TSKSZ0_SRCSZ2(x)             (((x)&0x3)<<0x16)
+#define MCF_DMA_TSKSZ0_DSTSZ1(x)             (((x)&0x3)<<0x18)
+#define MCF_DMA_TSKSZ0_SRCSZ1(x)             (((x)&0x3)<<0x1A)
+#define MCF_DMA_TSKSZ0_DSTSZ0(x)             (((x)&0x3)<<0x1C)
+#define MCF_DMA_TSKSZ0_SRCSZ0(x)             (((x)&0x3)<<0x1E)
+
+/* Bit definitions and macros for MCF_DMA_TSKSZ1 */
+#define MCF_DMA_TSKSZ1_DSTSZ15(x)            (((x)&0x3)<<0)
+#define MCF_DMA_TSKSZ1_SRCSZ15(x)            (((x)&0x3)<<0x2)
+#define MCF_DMA_TSKSZ1_DSTSZ14(x)            (((x)&0x3)<<0x4)
+#define MCF_DMA_TSKSZ1_SRCSZ14(x)            (((x)&0x3)<<0x6)
+#define MCF_DMA_TSKSZ1_DSTSZ13(x)            (((x)&0x3)<<0x8)
+#define MCF_DMA_TSKSZ1_SRCSZ13(x)            (((x)&0x3)<<0xA)
+#define MCF_DMA_TSKSZ1_DSTSZ12(x)            (((x)&0x3)<<0xC)
+#define MCF_DMA_TSKSZ1_SRCSZ12(x)            (((x)&0x3)<<0xE)
+#define MCF_DMA_TSKSZ1_DSTSZ11(x)            (((x)&0x3)<<0x10)
+#define MCF_DMA_TSKSZ1_SRCSZ11(x)            (((x)&0x3)<<0x12)
+#define MCF_DMA_TSKSZ1_DSTSZ10(x)            (((x)&0x3)<<0x14)
+#define MCF_DMA_TSKSZ1_SRCSZ10(x)            (((x)&0x3)<<0x16)
+#define MCF_DMA_TSKSZ1_DSTSZ9(x)             (((x)&0x3)<<0x18)
+#define MCF_DMA_TSKSZ1_SRCSZ9(x)             (((x)&0x3)<<0x1A)
+#define MCF_DMA_TSKSZ1_DSTSZ8(x)             (((x)&0x3)<<0x1C)
+#define MCF_DMA_TSKSZ1_SRCSZ8(x)             (((x)&0x3)<<0x1E)
+
+/* Bit definitions and macros for MCF_DMA_DBGCOMP0 */
+#define MCF_DMA_DBGCOMP0_COMPARATOR_VALUE(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DMA_DBGCOMP2 */
+#define MCF_DMA_DBGCOMP2_COMPARATOR_VALUE(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DMA_DBGCTL */
+#define MCF_DMA_DBGCTL_I                     (0x2)
+#define MCF_DMA_DBGCTL_E                     (0x4)
+#define MCF_DMA_DBGCTL_AND_OR                (0x80)
+#define MCF_DMA_DBGCTL_COMPARATOR_TYPE_2(x)  (((x)&0x7)<<0x8)
+#define MCF_DMA_DBGCTL_COMPARATOR_TYPE_1(x)  (((x)&0x7)<<0xB)
+#define MCF_DMA_DBGCTL_B                     (0x4000)
+#define MCF_DMA_DBGCTL_AA                    (0x8000)
+#define MCF_DMA_DBGCTL_BLOCK_TASKS(x)        (((x)&0xFFFF)<<0x10)
+
+
+#endif /* __MCF5475_DMA_H__ */
--- a/tos/fpga_test/include/MCF5475_DSPI.h
+++ b/tos/fpga_test/include/MCF5475_DSPI.h
@@ -0,0 +1,150 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_DSPI_H__
+#define __MCF5475_DSPI_H__
+
+
+/*********************************************************************
+*
+* DMA Serial Peripheral Interface (DSPI)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_DSPI_DMCR                        (*(volatile uint32_t*)(&_MBAR[0x8A00]))
+#define MCF_DSPI_DTCR                        (*(volatile uint32_t*)(&_MBAR[0x8A08]))
+#define MCF_DSPI_DCTAR0                      (*(volatile uint32_t*)(&_MBAR[0x8A0C]))
+#define MCF_DSPI_DCTAR1                      (*(volatile uint32_t*)(&_MBAR[0x8A10]))
+#define MCF_DSPI_DCTAR2                      (*(volatile uint32_t*)(&_MBAR[0x8A14]))
+#define MCF_DSPI_DCTAR3                      (*(volatile uint32_t*)(&_MBAR[0x8A18]))
+#define MCF_DSPI_DCTAR4                      (*(volatile uint32_t*)(&_MBAR[0x8A1C]))
+#define MCF_DSPI_DCTAR5                      (*(volatile uint32_t*)(&_MBAR[0x8A20]))
+#define MCF_DSPI_DCTAR6                      (*(volatile uint32_t*)(&_MBAR[0x8A24]))
+#define MCF_DSPI_DCTAR7                      (*(volatile uint32_t*)(&_MBAR[0x8A28]))
+#define MCF_DSPI_DSR                         (*(volatile uint32_t*)(&_MBAR[0x8A2C]))
+#define MCF_DSPI_DIRSR                       (*(volatile uint32_t*)(&_MBAR[0x8A30]))
+#define MCF_DSPI_DTFR                        (*(volatile uint32_t*)(&_MBAR[0x8A34]))
+#define MCF_DSPI_DRFR                        (*(volatile uint32_t*)(&_MBAR[0x8A38]))
+#define MCF_DSPI_DTFDR0                      (*(volatile uint32_t*)(&_MBAR[0x8A3C]))
+#define MCF_DSPI_DTFDR1                      (*(volatile uint32_t*)(&_MBAR[0x8A40]))
+#define MCF_DSPI_DTFDR2                      (*(volatile uint32_t*)(&_MBAR[0x8A44]))
+#define MCF_DSPI_DTFDR3                      (*(volatile uint32_t*)(&_MBAR[0x8A48]))
+#define MCF_DSPI_DRFDR0                      (*(volatile uint32_t*)(&_MBAR[0x8A7C]))
+#define MCF_DSPI_DRFDR1                      (*(volatile uint32_t*)(&_MBAR[0x8A80]))
+#define MCF_DSPI_DRFDR2                      (*(volatile uint32_t*)(&_MBAR[0x8A84]))
+#define MCF_DSPI_DRFDR3                      (*(volatile uint32_t*)(&_MBAR[0x8A88]))
+#define MCF_DSPI_DCTAR(x)                    (*(volatile uint32_t*)(&_MBAR[0x8A0C + ((x)*0x4)]))
+#define MCF_DSPI_DTFDR(x)                    (*(volatile uint32_t*)(&_MBAR[0x8A3C + ((x)*0x4)]))
+#define MCF_DSPI_DRFDR(x)                    (*(volatile uint32_t*)(&_MBAR[0x8A7C + ((x)*0x4)]))
+
+
+/* Bit definitions and macros for MCF_DSPI_DMCR */
+#define MCF_DSPI_DMCR_HALT                   (0x1)
+#define MCF_DSPI_DMCR_SMPL_PT(x)             (((x)&0x3)<<0x8)
+#define MCF_DSPI_DMCR_SMPL_PT_0CLK           (0)
+#define MCF_DSPI_DMCR_SMPL_PT_1CLK           (0x100)
+#define MCF_DSPI_DMCR_SMPL_PT_2CLK           (0x200)
+#define MCF_DSPI_DMCR_CRXF                   (0x400)
+#define MCF_DSPI_DMCR_CTXF                   (0x800)
+#define MCF_DSPI_DMCR_DRXF                   (0x1000)
+#define MCF_DSPI_DMCR_DTXF                   (0x2000)
+#define MCF_DSPI_DMCR_CSIS0                  (0x10000)
+#define MCF_DSPI_DMCR_CSIS2                  (0x40000)
+#define MCF_DSPI_DMCR_CSIS3                  (0x80000)
+#define MCF_DSPI_DMCR_CSIS5                  (0x200000)
+#define MCF_DSPI_DMCR_ROOE                   (0x1000000)
+#define MCF_DSPI_DMCR_PCSSE                  (0x2000000)
+#define MCF_DSPI_DMCR_MTFE                   (0x4000000)
+#define MCF_DSPI_DMCR_FRZ                    (0x8000000)
+#define MCF_DSPI_DMCR_DCONF(x)               (((x)&0x3)<<0x1C)
+#define MCF_DSPI_DMCR_CSCK                   (0x40000000)
+#define MCF_DSPI_DMCR_MSTR                   (0x80000000)
+
+/* Bit definitions and macros for MCF_DSPI_DTCR */
+#define MCF_DSPI_DTCR_SPI_TCNT(x)            (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_DSPI_DCTAR */
+#define MCF_DSPI_DCTAR_BR(x)                 (((x)&0xF)<<0)
+#define MCF_DSPI_DCTAR_DT(x)                 (((x)&0xF)<<0x4)
+#define MCF_DSPI_DCTAR_ASC(x)                (((x)&0xF)<<0x8)
+#define MCF_DSPI_DCTAR_CSSCK(x)              (((x)&0xF)<<0xC)
+#define MCF_DSPI_DCTAR_PBR(x)                (((x)&0x3)<<0x10)
+#define MCF_DSPI_DCTAR_PBR_1CLK              (0)
+#define MCF_DSPI_DCTAR_PBR_3CLK              (0x10000)
+#define MCF_DSPI_DCTAR_PBR_5CLK              (0x20000)
+#define MCF_DSPI_DCTAR_PBR_7CLK              (0x30000)
+#define MCF_DSPI_DCTAR_PDT(x)                (((x)&0x3)<<0x12)
+#define MCF_DSPI_DCTAR_PDT_1CLK              (0)
+#define MCF_DSPI_DCTAR_PDT_3CLK              (0x40000)
+#define MCF_DSPI_DCTAR_PDT_5CLK              (0x80000)
+#define MCF_DSPI_DCTAR_PDT_7CLK              (0xC0000)
+#define MCF_DSPI_DCTAR_PASC(x)               (((x)&0x3)<<0x14)
+#define MCF_DSPI_DCTAR_PASC_1CLK             (0)
+#define MCF_DSPI_DCTAR_PASC_3CLK             (0x100000)
+#define MCF_DSPI_DCTAR_PASC_5CLK             (0x200000)
+#define MCF_DSPI_DCTAR_PASC_7CLK             (0x300000)
+#define MCF_DSPI_DCTAR_PCSSCK(x)             (((x)&0x3)<<0x16)
+#define MCF_DSPI_DCTAR_LSBFE                 (0x1000000)
+#define MCF_DSPI_DCTAR_CPHA                  (0x2000000)
+#define MCF_DSPI_DCTAR_CPOL                  (0x4000000)
+#define MCF_DSPI_DCTAR_TRSZ(x)               (((x)&0xF)<<0x1B)
+
+/* Bit definitions and macros for MCF_DSPI_DSR */
+#define MCF_DSPI_DSR_RXPTR(x)                (((x)&0xF)<<0)
+#define MCF_DSPI_DSR_RXCTR(x)                (((x)&0xF)<<0x4)
+#define MCF_DSPI_DSR_TXPTR(x)                (((x)&0xF)<<0x8)
+#define MCF_DSPI_DSR_TXCTR(x)                (((x)&0xF)<<0xC)
+#define MCF_DSPI_DSR_RFDF                    (0x20000)
+#define MCF_DSPI_DSR_RFOF                    (0x80000)
+#define MCF_DSPI_DSR_TFFF                    (0x2000000)
+#define MCF_DSPI_DSR_TFUF                    (0x8000000)
+#define MCF_DSPI_DSR_EOQF                    (0x10000000)
+#define MCF_DSPI_DSR_TXRXS                   (0x40000000)
+#define MCF_DSPI_DSR_TCF                     (0x80000000)
+
+/* Bit definitions and macros for MCF_DSPI_DIRSR */
+#define MCF_DSPI_DIRSR_RFDFS                 (0x10000)
+#define MCF_DSPI_DIRSR_RFDFE                 (0x20000)
+#define MCF_DSPI_DIRSR_RFOFE                 (0x80000)
+#define MCF_DSPI_DIRSR_TFFFS                 (0x1000000)
+#define MCF_DSPI_DIRSR_TFFFE                 (0x2000000)
+#define MCF_DSPI_DIRSR_TFUFE                 (0x8000000)
+#define MCF_DSPI_DIRSR_EOQFE                 (0x10000000)
+#define MCF_DSPI_DIRSR_TCFE                  (0x80000000)
+
+/* Bit definitions and macros for MCF_DSPI_DTFR */
+#define MCF_DSPI_DTFR_TXDATA(x)              (((x)&0xFFFF)<<0)
+#define MCF_DSPI_DTFR_CS0                    (0x10000)
+#define MCF_DSPI_DTFR_CS2                    (0x40000)
+#define MCF_DSPI_DTFR_CS3                    (0x80000)
+#define MCF_DSPI_DTFR_CS5                    (0x200000)
+#define MCF_DSPI_DTFR_CTCNT                  (0x4000000)
+#define MCF_DSPI_DTFR_EOQ                    (0x8000000)
+#define MCF_DSPI_DTFR_CTAS(x)                (((x)&0x7)<<0x1C)
+#define MCF_DSPI_DTFR_CONT                   (0x80000000)
+
+/* Bit definitions and macros for MCF_DSPI_DRFR */
+#define MCF_DSPI_DRFR_RXDATA(x)              (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DSPI_DTFDR */
+#define MCF_DSPI_DTFDR_TXDATA(x)             (((x)&0xFFFF)<<0)
+#define MCF_DSPI_DTFDR_TXCMD(x)              (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_DSPI_DRFDR */
+#define MCF_DSPI_DRFDR_RXDATA(x)             (((x)&0xFFFF)<<0)
+
+
+#endif /* __MCF5475_DSPI_H__ */
--- a/tos/fpga_test/include/MCF5475_EPORT.h
+++ b/tos/fpga_test/include/MCF5475_EPORT.h
@@ -0,0 +1,123 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_EPORT_H__
+#define __MCF5475_EPORT_H__
+
+
+/*********************************************************************
+*
+* Edge Port Module (EPORT)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_EPORT_EPPAR                      (*(volatile uint16_t*)(&_MBAR[0xF00]))
+#define MCF_EPORT_EPDDR                      (*(volatile uint8_t *)(&_MBAR[0xF04]))
+#define MCF_EPORT_EPIER                      (*(volatile uint8_t *)(&_MBAR[0xF05]))
+#define MCF_EPORT_EPDR                       (*(volatile uint8_t *)(&_MBAR[0xF08]))
+#define MCF_EPORT_EPPDR                      (*(volatile uint8_t *)(&_MBAR[0xF09]))
+#define MCF_EPORT_EPFR                       (*(volatile uint8_t *)(&_MBAR[0xF0C]))
+
+
+
+/* Bit definitions and macros for MCF_EPORT_EPPAR */
+#define MCF_EPORT_EPPAR_EPPA1(x)             (((x)&0x3)<<0x2)
+#define MCF_EPORT_EPPAR_EPPA1_LEVEL          (0)
+#define MCF_EPORT_EPPAR_EPPA1_RISING         (0x4)
+#define MCF_EPORT_EPPAR_EPPA1_FALLING        (0x8)
+#define MCF_EPORT_EPPAR_EPPA1_BOTH           (0xC)
+#define MCF_EPORT_EPPAR_EPPA2(x)             (((x)&0x3)<<0x4)
+#define MCF_EPORT_EPPAR_EPPA2_LEVEL          (0)
+#define MCF_EPORT_EPPAR_EPPA2_RISING         (0x10)
+#define MCF_EPORT_EPPAR_EPPA2_FALLING        (0x20)
+#define MCF_EPORT_EPPAR_EPPA2_BOTH           (0x30)
+#define MCF_EPORT_EPPAR_EPPA3(x)             (((x)&0x3)<<0x6)
+#define MCF_EPORT_EPPAR_EPPA3_LEVEL          (0)
+#define MCF_EPORT_EPPAR_EPPA3_RISING         (0x40)
+#define MCF_EPORT_EPPAR_EPPA3_FALLING        (0x80)
+#define MCF_EPORT_EPPAR_EPPA3_BOTH           (0xC0)
+#define MCF_EPORT_EPPAR_EPPA4(x)             (((x)&0x3)<<0x8)
+#define MCF_EPORT_EPPAR_EPPA4_LEVEL          (0)
+#define MCF_EPORT_EPPAR_EPPA4_RISING         (0x100)
+#define MCF_EPORT_EPPAR_EPPA4_FALLING        (0x200)
+#define MCF_EPORT_EPPAR_EPPA4_BOTH           (0x300)
+#define MCF_EPORT_EPPAR_EPPA5(x)             (((x)&0x3)<<0xA)
+#define MCF_EPORT_EPPAR_EPPA5_LEVEL          (0)
+#define MCF_EPORT_EPPAR_EPPA5_RISING         (0x400)
+#define MCF_EPORT_EPPAR_EPPA5_FALLING        (0x800)
+#define MCF_EPORT_EPPAR_EPPA5_BOTH           (0xC00)
+#define MCF_EPORT_EPPAR_EPPA6(x)             (((x)&0x3)<<0xC)
+#define MCF_EPORT_EPPAR_EPPA6_LEVEL          (0)
+#define MCF_EPORT_EPPAR_EPPA6_RISING         (0x1000)
+#define MCF_EPORT_EPPAR_EPPA6_FALLING        (0x2000)
+#define MCF_EPORT_EPPAR_EPPA6_BOTH           (0x3000)
+#define MCF_EPORT_EPPAR_EPPA7(x)             (((x)&0x3)<<0xE)
+#define MCF_EPORT_EPPAR_EPPA7_LEVEL          (0)
+#define MCF_EPORT_EPPAR_EPPA7_RISING         (0x4000)
+#define MCF_EPORT_EPPAR_EPPA7_FALLING        (0x8000)
+#define MCF_EPORT_EPPAR_EPPA7_BOTH           (0xC000)
+#define MCF_EPORT_EPPAR_LEVEL                (0)
+#define MCF_EPORT_EPPAR_RISING               (0x1)
+#define MCF_EPORT_EPPAR_FALLING              (0x2)
+#define MCF_EPORT_EPPAR_BOTH                 (0x3)
+
+/* Bit definitions and macros for MCF_EPORT_EPDDR */
+#define MCF_EPORT_EPDDR_EPDD1                (0x2)
+#define MCF_EPORT_EPDDR_EPDD2                (0x4)
+#define MCF_EPORT_EPDDR_EPDD3                (0x8)
+#define MCF_EPORT_EPDDR_EPDD4                (0x10)
+#define MCF_EPORT_EPDDR_EPDD5                (0x20)
+#define MCF_EPORT_EPDDR_EPDD6                (0x40)
+#define MCF_EPORT_EPDDR_EPDD7                (0x80)
+
+/* Bit definitions and macros for MCF_EPORT_EPIER */
+#define MCF_EPORT_EPIER_EPIE1                (0x2)
+#define MCF_EPORT_EPIER_EPIE2                (0x4)
+#define MCF_EPORT_EPIER_EPIE3                (0x8)
+#define MCF_EPORT_EPIER_EPIE4                (0x10)
+#define MCF_EPORT_EPIER_EPIE5                (0x20)
+#define MCF_EPORT_EPIER_EPIE6                (0x40)
+#define MCF_EPORT_EPIER_EPIE7                (0x80)
+
+/* Bit definitions and macros for MCF_EPORT_EPDR */
+#define MCF_EPORT_EPDR_EPD1                  (0x2)
+#define MCF_EPORT_EPDR_EPD2                  (0x4)
+#define MCF_EPORT_EPDR_EPD3                  (0x8)
+#define MCF_EPORT_EPDR_EPD4                  (0x10)
+#define MCF_EPORT_EPDR_EPD5                  (0x20)
+#define MCF_EPORT_EPDR_EPD6                  (0x40)
+#define MCF_EPORT_EPDR_EPD7                  (0x80)
+
+/* Bit definitions and macros for MCF_EPORT_EPPDR */
+#define MCF_EPORT_EPPDR_EPPD1                (0x2)
+#define MCF_EPORT_EPPDR_EPPD2                (0x4)
+#define MCF_EPORT_EPPDR_EPPD3                (0x8)
+#define MCF_EPORT_EPPDR_EPPD4                (0x10)
+#define MCF_EPORT_EPPDR_EPPD5                (0x20)
+#define MCF_EPORT_EPPDR_EPPD6                (0x40)
+#define MCF_EPORT_EPPDR_EPPD7                (0x80)
+
+/* Bit definitions and macros for MCF_EPORT_EPFR */
+#define MCF_EPORT_EPFR_EPF1                  (0x2)
+#define MCF_EPORT_EPFR_EPF2                  (0x4)
+#define MCF_EPORT_EPFR_EPF3                  (0x8)
+#define MCF_EPORT_EPFR_EPF4                  (0x10)
+#define MCF_EPORT_EPFR_EPF5                  (0x20)
+#define MCF_EPORT_EPFR_EPF6                  (0x40)
+#define MCF_EPORT_EPFR_EPF7                  (0x80)
+
+
+#endif /* __MCF5475_EPORT_H__ */
--- a/tos/fpga_test/include/MCF5475_FBCS.h
+++ b/tos/fpga_test/include/MCF5475_FBCS.h
@@ -0,0 +1,100 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_FBCS_H__
+#define __MCF5475_FBCS_H__
+
+
+/*********************************************************************
+*
+* FlexBus Chip Select Module (FBCS)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_FBCS0_CSAR                       (*(volatile uint32_t*)(&_MBAR[0x500]))
+#define MCF_FBCS0_CSMR                       (*(volatile uint32_t*)(&_MBAR[0x504]))
+#define MCF_FBCS0_CSCR                       (*(volatile uint32_t*)(&_MBAR[0x508]))
+
+#define MCF_FBCS1_CSAR                       (*(volatile uint32_t*)(&_MBAR[0x50C]))
+#define MCF_FBCS1_CSMR                       (*(volatile uint32_t*)(&_MBAR[0x510]))
+#define MCF_FBCS1_CSCR                       (*(volatile uint32_t*)(&_MBAR[0x514]))
+
+#define MCF_FBCS2_CSAR                       (*(volatile uint32_t*)(&_MBAR[0x518]))
+#define MCF_FBCS2_CSMR                       (*(volatile uint32_t*)(&_MBAR[0x51C]))
+#define MCF_FBCS2_CSCR                       (*(volatile uint32_t*)(&_MBAR[0x520]))
+
+#define MCF_FBCS3_CSAR                       (*(volatile uint32_t*)(&_MBAR[0x524]))
+#define MCF_FBCS3_CSMR                       (*(volatile uint32_t*)(&_MBAR[0x528]))
+#define MCF_FBCS3_CSCR                       (*(volatile uint32_t*)(&_MBAR[0x52C]))
+
+#define MCF_FBCS4_CSAR                       (*(volatile uint32_t*)(&_MBAR[0x530]))
+#define MCF_FBCS4_CSMR                       (*(volatile uint32_t*)(&_MBAR[0x534]))
+#define MCF_FBCS4_CSCR                       (*(volatile uint32_t*)(&_MBAR[0x538]))
+
+#define MCF_FBCS5_CSAR                       (*(volatile uint32_t*)(&_MBAR[0x53C]))
+#define MCF_FBCS5_CSMR                       (*(volatile uint32_t*)(&_MBAR[0x540]))
+#define MCF_FBCS5_CSCR                       (*(volatile uint32_t*)(&_MBAR[0x544]))
+
+#define MCF_FBCS_CSAR(x)                     (*(volatile uint32_t*)(&_MBAR[0x500 + ((x)*0xC)]))
+#define MCF_FBCS_CSMR(x)                     (*(volatile uint32_t*)(&_MBAR[0x504 + ((x)*0xC)]))
+#define MCF_FBCS_CSCR(x)                     (*(volatile uint32_t*)(&_MBAR[0x508 + ((x)*0xC)]))
+
+
+/* Bit definitions and macros for MCF_FBCS_CSAR */
+#define MCF_FBCS_CSAR_BA(x)                  ((x)&0xFFFF0000)
+
+/* Bit definitions and macros for MCF_FBCS_CSMR */
+#define MCF_FBCS_CSMR_V                      (0x1)
+#define MCF_FBCS_CSMR_WP                     (0x100)
+#define MCF_FBCS_CSMR_BAM(x)                 (((x)&0xFFFF)<<0x10)
+#define MCF_FBCS_CSMR_BAM_4G                 (0xFFFF0000)
+#define MCF_FBCS_CSMR_BAM_2G                 (0x7FFF0000)
+#define MCF_FBCS_CSMR_BAM_1G                 (0x3FFF0000)
+#define MCF_FBCS_CSMR_BAM_1024M              (0x3FFF0000)
+#define MCF_FBCS_CSMR_BAM_512M               (0x1FFF0000)
+#define MCF_FBCS_CSMR_BAM_256M               (0xFFF0000)
+#define MCF_FBCS_CSMR_BAM_128M               (0x7FF0000)
+#define MCF_FBCS_CSMR_BAM_64M                (0x3FF0000)
+#define MCF_FBCS_CSMR_BAM_32M                (0x1FF0000)
+#define MCF_FBCS_CSMR_BAM_16M                (0xFF0000)
+#define MCF_FBCS_CSMR_BAM_8M                 (0x7F0000)
+#define MCF_FBCS_CSMR_BAM_4M                 (0x3F0000)
+#define MCF_FBCS_CSMR_BAM_2M                 (0x1F0000)
+#define MCF_FBCS_CSMR_BAM_1M                 (0xF0000)
+#define MCF_FBCS_CSMR_BAM_1024K              (0xF0000)
+#define MCF_FBCS_CSMR_BAM_512K               (0x70000)
+#define MCF_FBCS_CSMR_BAM_256K               (0x30000)
+#define MCF_FBCS_CSMR_BAM_128K               (0x10000)
+#define MCF_FBCS_CSMR_BAM_64K                (0)
+
+/* Bit definitions and macros for MCF_FBCS_CSCR */
+#define MCF_FBCS_CSCR_BSTW                   (0x8)
+#define MCF_FBCS_CSCR_BSTR                   (0x10)
+#define MCF_FBCS_CSCR_BEM                    (0x20)
+#define MCF_FBCS_CSCR_PS(x)                  (((x)&0x3)<<0x6)
+#define MCF_FBCS_CSCR_PS_32                  (0)
+#define MCF_FBCS_CSCR_PS_8                   (0x40)
+#define MCF_FBCS_CSCR_PS_16                  (0x80)
+#define MCF_FBCS_CSCR_AA                     (0x100)
+#define MCF_FBCS_CSCR_WS(x)                  (((x)&0x3F)<<0xA)
+#define MCF_FBCS_CSCR_WRAH(x)                (((x)&0x3)<<0x10)
+#define MCF_FBCS_CSCR_RDAH(x)                (((x)&0x3)<<0x12)
+#define MCF_FBCS_CSCR_ASET(x)                (((x)&0x3)<<0x14)
+#define MCF_FBCS_CSCR_SWSEN                  (0x800000)
+#define MCF_FBCS_CSCR_SWS(x)                 (((x)&0x3F)<<0x1A)
+
+
+#endif /* __MCF5475_FBCS_H__ */
--- a/tos/fpga_test/include/MCF5475_FEC.h
+++ b/tos/fpga_test/include/MCF5475_FEC.h
@@ -0,0 +1,680 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_FEC_H__
+#define __MCF5475_FEC_H__
+
+
+/*********************************************************************
+*
+* Fast Ethernet Controller(FEC)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_FEC0_EIR                         (*(volatile uint32_t*)(&_MBAR[0x9004]))
+#define MCF_FEC0_EIMR                        (*(volatile uint32_t*)(&_MBAR[0x9008]))
+#define MCF_FEC0_ECR                         (*(volatile uint32_t*)(&_MBAR[0x9024]))
+#define MCF_FEC0_MMFR                        (*(volatile uint32_t*)(&_MBAR[0x9040]))
+#define MCF_FEC0_MSCR                        (*(volatile uint32_t*)(&_MBAR[0x9044]))
+#define MCF_FEC0_MIBC                        (*(volatile uint32_t*)(&_MBAR[0x9064]))
+#define MCF_FEC0_RCR                         (*(volatile uint32_t*)(&_MBAR[0x9084]))
+#define MCF_FEC0_RHR                         (*(volatile uint32_t*)(&_MBAR[0x9088]))
+#define MCF_FEC0_TCR                         (*(volatile uint32_t*)(&_MBAR[0x90C4]))
+#define MCF_FEC0_PALR                        (*(volatile uint32_t*)(&_MBAR[0x90E4]))
+#define MCF_FEC0_PAHR                        (*(volatile uint32_t*)(&_MBAR[0x90E8]))
+#define MCF_FEC0_OPD                         (*(volatile uint32_t*)(&_MBAR[0x90EC]))
+#define MCF_FEC0_IAUR                        (*(volatile uint32_t*)(&_MBAR[0x9118]))
+#define MCF_FEC0_IALR                        (*(volatile uint32_t*)(&_MBAR[0x911C]))
+#define MCF_FEC0_GAUR                        (*(volatile uint32_t*)(&_MBAR[0x9120]))
+#define MCF_FEC0_GALR                        (*(volatile uint32_t*)(&_MBAR[0x9124]))
+#define MCF_FEC0_FECTFWR                     (*(volatile uint32_t*)(&_MBAR[0x9144]))
+#define MCF_FEC0_FECRFDR                     (*(volatile uint32_t*)(&_MBAR[0x9184]))
+#define MCF_FEC0_FECRFSR                     (*(volatile uint32_t*)(&_MBAR[0x9188]))
+#define MCF_FEC0_FECRFCR                     (*(volatile uint32_t*)(&_MBAR[0x918C]))
+#define MCF_FEC0_FECRLRFP                    (*(volatile uint32_t*)(&_MBAR[0x9190]))
+#define MCF_FEC0_FECRLWFP                    (*(volatile uint32_t*)(&_MBAR[0x9194]))
+#define MCF_FEC0_FECRFAR                     (*(volatile uint32_t*)(&_MBAR[0x9198]))
+#define MCF_FEC0_FECRFRP                     (*(volatile uint32_t*)(&_MBAR[0x919C]))
+#define MCF_FEC0_FECRFWP                     (*(volatile uint32_t*)(&_MBAR[0x91A0]))
+#define MCF_FEC0_FECTFDR                     (*(volatile uint32_t*)(&_MBAR[0x91A4]))
+#define MCF_FEC0_FECTFSR                     (*(volatile uint32_t*)(&_MBAR[0x91A8]))
+#define MCF_FEC0_FECTFCR                     (*(volatile uint32_t*)(&_MBAR[0x91AC]))
+#define MCF_FEC0_FECTLRFP                    (*(volatile uint32_t*)(&_MBAR[0x91B0]))
+#define MCF_FEC0_FECTLWFP                    (*(volatile uint32_t*)(&_MBAR[0x91B4]))
+#define MCF_FEC0_FECTFAR                     (*(volatile uint32_t*)(&_MBAR[0x91B8]))
+#define MCF_FEC0_FECTFRP                     (*(volatile uint32_t*)(&_MBAR[0x91BC]))
+#define MCF_FEC0_FECTFWP                     (*(volatile uint32_t*)(&_MBAR[0x91C0]))
+#define MCF_FEC0_FECFRST                     (*(volatile uint32_t*)(&_MBAR[0x91C4]))
+#define MCF_FEC0_FECCTCWR                    (*(volatile uint32_t*)(&_MBAR[0x91C8]))
+#define MCF_FEC0_RMON_T_DROP                 (*(volatile uint32_t*)(&_MBAR[0x9200]))
+#define MCF_FEC0_RMON_T_PACKETS              (*(volatile uint32_t*)(&_MBAR[0x9204]))
+#define MCF_FEC0_RMON_T_BC_PKT               (*(volatile uint32_t*)(&_MBAR[0x9208]))
+#define MCF_FEC0_RMON_T_MC_PKT               (*(volatile uint32_t*)(&_MBAR[0x920C]))
+#define MCF_FEC0_RMON_T_CRC_ALIGN            (*(volatile uint32_t*)(&_MBAR[0x9210]))
+#define MCF_FEC0_RMON_T_UNDERSIZE            (*(volatile uint32_t*)(&_MBAR[0x9214]))
+#define MCF_FEC0_RMON_T_OVERSIZE             (*(volatile uint32_t*)(&_MBAR[0x9218]))
+#define MCF_FEC0_RMON_T_FRAG                 (*(volatile uint32_t*)(&_MBAR[0x921C]))
+#define MCF_FEC0_RMON_T_JAB                  (*(volatile uint32_t*)(&_MBAR[0x9220]))
+#define MCF_FEC0_RMON_T_COL                  (*(volatile uint32_t*)(&_MBAR[0x9224]))
+#define MCF_FEC0_RMON_T_P64                  (*(volatile uint32_t*)(&_MBAR[0x9228]))
+#define MCF_FEC0_RMON_T_P65TO127             (*(volatile uint32_t*)(&_MBAR[0x922C]))
+#define MCF_FEC0_RMON_T_P128TO255            (*(volatile uint32_t*)(&_MBAR[0x9230]))
+#define MCF_FEC0_RMON_T_P256TO511            (*(volatile uint32_t*)(&_MBAR[0x9234]))
+#define MCF_FEC0_RMON_T_P512TO1023           (*(volatile uint32_t*)(&_MBAR[0x9238]))
+#define MCF_FEC0_RMON_T_P1024TO2047          (*(volatile uint32_t*)(&_MBAR[0x923C]))
+#define MCF_FEC0_RMON_T_P_GTE2048            (*(volatile uint32_t*)(&_MBAR[0x9240]))
+#define MCF_FEC0_RMON_T_OCTETS               (*(volatile uint32_t*)(&_MBAR[0x9244]))
+#define MCF_FEC0_IEEE_T_DROP                 (*(volatile uint32_t*)(&_MBAR[0x9248]))
+#define MCF_FEC0_IEEE_T_FRAME_OK             (*(volatile uint32_t*)(&_MBAR[0x924C]))
+#define MCF_FEC0_IEEE_T_1COL                 (*(volatile uint32_t*)(&_MBAR[0x9250]))
+#define MCF_FEC0_IEEE_T_MCOL                 (*(volatile uint32_t*)(&_MBAR[0x9254]))
+#define MCF_FEC0_IEEE_T_DEF                  (*(volatile uint32_t*)(&_MBAR[0x9258]))
+#define MCF_FEC0_IEEE_T_LCOL                 (*(volatile uint32_t*)(&_MBAR[0x925C]))
+#define MCF_FEC0_IEEE_T_EXCOL                (*(volatile uint32_t*)(&_MBAR[0x9260]))
+#define MCF_FEC0_IEEE_T_MACERR               (*(volatile uint32_t*)(&_MBAR[0x9264]))
+#define MCF_FEC0_IEEE_T_CSERR                (*(volatile uint32_t*)(&_MBAR[0x9268]))
+#define MCF_FEC0_IEEE_T_SQE                  (*(volatile uint32_t*)(&_MBAR[0x926C]))
+#define MCF_FEC0_IEEE_T_FDXFC                (*(volatile uint32_t*)(&_MBAR[0x9270]))
+#define MCF_FEC0_IEEE_T_OCTETS_OK            (*(volatile uint32_t*)(&_MBAR[0x9274]))
+#define MCF_FEC0_RMON_R_DROP                 (*(volatile uint32_t*)(&_MBAR[0x9280]))
+#define MCF_FEC0_RMON_R_PACKETS              (*(volatile uint32_t*)(&_MBAR[0x9284]))
+#define MCF_FEC0_RMON_R_BC_PKT               (*(volatile uint32_t*)(&_MBAR[0x9288]))
+#define MCF_FEC0_RMON_R_MC_PKT               (*(volatile uint32_t*)(&_MBAR[0x928C]))
+#define MCF_FEC0_RMON_R_CRC_ALIGN            (*(volatile uint32_t*)(&_MBAR[0x9290]))
+#define MCF_FEC0_RMON_R_UNDERSIZE            (*(volatile uint32_t*)(&_MBAR[0x9294]))
+#define MCF_FEC0_RMON_R_OVERSIZE             (*(volatile uint32_t*)(&_MBAR[0x9298]))
+#define MCF_FEC0_RMON_R_FRAG                 (*(volatile uint32_t*)(&_MBAR[0x929C]))
+#define MCF_FEC0_RMON_R_JAB                  (*(volatile uint32_t*)(&_MBAR[0x92A0]))
+#define MCF_FEC0_RMON_R_RESVD_0              (*(volatile uint32_t*)(&_MBAR[0x92A4]))
+#define MCF_FEC0_RMON_R_P64                  (*(volatile uint32_t*)(&_MBAR[0x92A8]))
+#define MCF_FEC0_RMON_R_P65TO127             (*(volatile uint32_t*)(&_MBAR[0x92AC]))
+#define MCF_FEC0_RMON_R_P128TO255            (*(volatile uint32_t*)(&_MBAR[0x92B0]))
+#define MCF_FEC0_RMON_R_P256TO511            (*(volatile uint32_t*)(&_MBAR[0x92B4]))
+#define MCF_FEC0_RMON_R_P512TO1023           (*(volatile uint32_t*)(&_MBAR[0x92B8]))
+#define MCF_FEC0_RMON_R_P1024TO2047          (*(volatile uint32_t*)(&_MBAR[0x92BC]))
+#define MCF_FEC0_RMON_R_P_GTE2048            (*(volatile uint32_t*)(&_MBAR[0x92C0]))
+#define MCF_FEC0_RMON_R_OCTETS               (*(volatile uint32_t*)(&_MBAR[0x92C4]))
+#define MCF_FEC0_IEEE_R_DROP                 (*(volatile uint32_t*)(&_MBAR[0x92C8]))
+#define MCF_FEC0_IEEE_R_FRAME_OK             (*(volatile uint32_t*)(&_MBAR[0x92CC]))
+#define MCF_FEC0_IEEE_R_CRC                  (*(volatile uint32_t*)(&_MBAR[0x92D0]))
+#define MCF_FEC0_IEEE_R_ALIGN                (*(volatile uint32_t*)(&_MBAR[0x92D4]))
+#define MCF_FEC0_IEEE_R_MACERR               (*(volatile uint32_t*)(&_MBAR[0x92D8]))
+#define MCF_FEC0_IEEE_R_FDXFC                (*(volatile uint32_t*)(&_MBAR[0x92DC]))
+#define MCF_FEC0_IEEE_R_OCTETS_OK            (*(volatile uint32_t*)(&_MBAR[0x92E0]))
+
+#define MCF_FEC1_EIR                         (*(volatile uint32_t*)(&_MBAR[0x9804]))
+#define MCF_FEC1_EIMR                        (*(volatile uint32_t*)(&_MBAR[0x9808]))
+#define MCF_FEC1_ECR                         (*(volatile uint32_t*)(&_MBAR[0x9824]))
+#define MCF_FEC1_MMFR                        (*(volatile uint32_t*)(&_MBAR[0x9840]))
+#define MCF_FEC1_MSCR                        (*(volatile uint32_t*)(&_MBAR[0x9844]))
+#define MCF_FEC1_MIBC                        (*(volatile uint32_t*)(&_MBAR[0x9864]))
+#define MCF_FEC1_RCR                         (*(volatile uint32_t*)(&_MBAR[0x9884]))
+#define MCF_FEC1_RHR                         (*(volatile uint32_t*)(&_MBAR[0x9888]))
+#define MCF_FEC1_TCR                         (*(volatile uint32_t*)(&_MBAR[0x98C4]))
+#define MCF_FEC1_PALR                        (*(volatile uint32_t*)(&_MBAR[0x98E4]))
+#define MCF_FEC1_PAHR                        (*(volatile uint32_t*)(&_MBAR[0x98E8]))
+#define MCF_FEC1_OPD                         (*(volatile uint32_t*)(&_MBAR[0x98EC]))
+#define MCF_FEC1_IAUR                        (*(volatile uint32_t*)(&_MBAR[0x9918]))
+#define MCF_FEC1_IALR                        (*(volatile uint32_t*)(&_MBAR[0x991C]))
+#define MCF_FEC1_GAUR                        (*(volatile uint32_t*)(&_MBAR[0x9920]))
+#define MCF_FEC1_GALR                        (*(volatile uint32_t*)(&_MBAR[0x9924]))
+#define MCF_FEC1_FECTFWR                     (*(volatile uint32_t*)(&_MBAR[0x9944]))
+#define MCF_FEC1_FECRFDR                     (*(volatile uint32_t*)(&_MBAR[0x9984]))
+#define MCF_FEC1_FECRFSR                     (*(volatile uint32_t*)(&_MBAR[0x9988]))
+#define MCF_FEC1_FECRFCR                     (*(volatile uint32_t*)(&_MBAR[0x998C]))
+#define MCF_FEC1_FECRLRFP                    (*(volatile uint32_t*)(&_MBAR[0x9990]))
+#define MCF_FEC1_FECRLWFP                    (*(volatile uint32_t*)(&_MBAR[0x9994]))
+#define MCF_FEC1_FECRFAR                     (*(volatile uint32_t*)(&_MBAR[0x9998]))
+#define MCF_FEC1_FECRFRP                     (*(volatile uint32_t*)(&_MBAR[0x999C]))
+#define MCF_FEC1_FECRFWP                     (*(volatile uint32_t*)(&_MBAR[0x99A0]))
+#define MCF_FEC1_FECTFDR                     (*(volatile uint32_t*)(&_MBAR[0x99A4]))
+#define MCF_FEC1_FECTFSR                     (*(volatile uint32_t*)(&_MBAR[0x99A8]))
+#define MCF_FEC1_FECTFCR                     (*(volatile uint32_t*)(&_MBAR[0x99AC]))
+#define MCF_FEC1_FECTLRFP                    (*(volatile uint32_t*)(&_MBAR[0x99B0]))
+#define MCF_FEC1_FECTLWFP                    (*(volatile uint32_t*)(&_MBAR[0x99B4]))
+#define MCF_FEC1_FECTFAR                     (*(volatile uint32_t*)(&_MBAR[0x99B8]))
+#define MCF_FEC1_FECTFRP                     (*(volatile uint32_t*)(&_MBAR[0x99BC]))
+#define MCF_FEC1_FECTFWP                     (*(volatile uint32_t*)(&_MBAR[0x99C0]))
+#define MCF_FEC1_FECFRST                     (*(volatile uint32_t*)(&_MBAR[0x99C4]))
+#define MCF_FEC1_FECCTCWR                    (*(volatile uint32_t*)(&_MBAR[0x99C8]))
+#define MCF_FEC1_RMON_T_DROP                 (*(volatile uint32_t*)(&_MBAR[0x9A00]))
+#define MCF_FEC1_RMON_T_PACKETS              (*(volatile uint32_t*)(&_MBAR[0x9A04]))
+#define MCF_FEC1_RMON_T_BC_PKT               (*(volatile uint32_t*)(&_MBAR[0x9A08]))
+#define MCF_FEC1_RMON_T_MC_PKT               (*(volatile uint32_t*)(&_MBAR[0x9A0C]))
+#define MCF_FEC1_RMON_T_CRC_ALIGN            (*(volatile uint32_t*)(&_MBAR[0x9A10]))
+#define MCF_FEC1_RMON_T_UNDERSIZE            (*(volatile uint32_t*)(&_MBAR[0x9A14]))
+#define MCF_FEC1_RMON_T_OVERSIZE             (*(volatile uint32_t*)(&_MBAR[0x9A18]))
+#define MCF_FEC1_RMON_T_FRAG                 (*(volatile uint32_t*)(&_MBAR[0x9A1C]))
+#define MCF_FEC1_RMON_T_JAB                  (*(volatile uint32_t*)(&_MBAR[0x9A20]))
+#define MCF_FEC1_RMON_T_COL                  (*(volatile uint32_t*)(&_MBAR[0x9A24]))
+#define MCF_FEC1_RMON_T_P64                  (*(volatile uint32_t*)(&_MBAR[0x9A28]))
+#define MCF_FEC1_RMON_T_P65TO127             (*(volatile uint32_t*)(&_MBAR[0x9A2C]))
+#define MCF_FEC1_RMON_T_P128TO255            (*(volatile uint32_t*)(&_MBAR[0x9A30]))
+#define MCF_FEC1_RMON_T_P256TO511            (*(volatile uint32_t*)(&_MBAR[0x9A34]))
+#define MCF_FEC1_RMON_T_P512TO1023           (*(volatile uint32_t*)(&_MBAR[0x9A38]))
+#define MCF_FEC1_RMON_T_P1024TO2047          (*(volatile uint32_t*)(&_MBAR[0x9A3C]))
+#define MCF_FEC1_RMON_T_P_GTE2048            (*(volatile uint32_t*)(&_MBAR[0x9A40]))
+#define MCF_FEC1_RMON_T_OCTETS               (*(volatile uint32_t*)(&_MBAR[0x9A44]))
+#define MCF_FEC1_IEEE_T_DROP                 (*(volatile uint32_t*)(&_MBAR[0x9A48]))
+#define MCF_FEC1_IEEE_T_FRAME_OK             (*(volatile uint32_t*)(&_MBAR[0x9A4C]))
+#define MCF_FEC1_IEEE_T_1COL                 (*(volatile uint32_t*)(&_MBAR[0x9A50]))
+#define MCF_FEC1_IEEE_T_MCOL                 (*(volatile uint32_t*)(&_MBAR[0x9A54]))
+#define MCF_FEC1_IEEE_T_DEF                  (*(volatile uint32_t*)(&_MBAR[0x9A58]))
+#define MCF_FEC1_IEEE_T_LCOL                 (*(volatile uint32_t*)(&_MBAR[0x9A5C]))
+#define MCF_FEC1_IEEE_T_EXCOL                (*(volatile uint32_t*)(&_MBAR[0x9A60]))
+#define MCF_FEC1_IEEE_T_MACERR               (*(volatile uint32_t*)(&_MBAR[0x9A64]))
+#define MCF_FEC1_IEEE_T_CSERR                (*(volatile uint32_t*)(&_MBAR[0x9A68]))
+#define MCF_FEC1_IEEE_T_SQE                  (*(volatile uint32_t*)(&_MBAR[0x9A6C]))
+#define MCF_FEC1_IEEE_T_FDXFC                (*(volatile uint32_t*)(&_MBAR[0x9A70]))
+#define MCF_FEC1_IEEE_T_OCTETS_OK            (*(volatile uint32_t*)(&_MBAR[0x9A74]))
+#define MCF_FEC1_RMON_R_DROP                 (*(volatile uint32_t*)(&_MBAR[0x9A80]))
+#define MCF_FEC1_RMON_R_PACKETS              (*(volatile uint32_t*)(&_MBAR[0x9A84]))
+#define MCF_FEC1_RMON_R_BC_PKT               (*(volatile uint32_t*)(&_MBAR[0x9A88]))
+#define MCF_FEC1_RMON_R_MC_PKT               (*(volatile uint32_t*)(&_MBAR[0x9A8C]))
+#define MCF_FEC1_RMON_R_CRC_ALIGN            (*(volatile uint32_t*)(&_MBAR[0x9A90]))
+#define MCF_FEC1_RMON_R_UNDERSIZE            (*(volatile uint32_t*)(&_MBAR[0x9A94]))
+#define MCF_FEC1_RMON_R_OVERSIZE             (*(volatile uint32_t*)(&_MBAR[0x9A98]))
+#define MCF_FEC1_RMON_R_FRAG                 (*(volatile uint32_t*)(&_MBAR[0x9A9C]))
+#define MCF_FEC1_RMON_R_JAB                  (*(volatile uint32_t*)(&_MBAR[0x9AA0]))
+#define MCF_FEC1_RMON_R_RESVD_0              (*(volatile uint32_t*)(&_MBAR[0x9AA4]))
+#define MCF_FEC1_RMON_R_P64                  (*(volatile uint32_t*)(&_MBAR[0x9AA8]))
+#define MCF_FEC1_RMON_R_P65TO127             (*(volatile uint32_t*)(&_MBAR[0x9AAC]))
+#define MCF_FEC1_RMON_R_P128TO255            (*(volatile uint32_t*)(&_MBAR[0x9AB0]))
+#define MCF_FEC1_RMON_R_P256TO511            (*(volatile uint32_t*)(&_MBAR[0x9AB4]))
+#define MCF_FEC1_RMON_R_P512TO1023           (*(volatile uint32_t*)(&_MBAR[0x9AB8]))
+#define MCF_FEC1_RMON_R_P1024TO2047          (*(volatile uint32_t*)(&_MBAR[0x9ABC]))
+#define MCF_FEC1_RMON_R_P_GTE2048            (*(volatile uint32_t*)(&_MBAR[0x9AC0]))
+#define MCF_FEC1_RMON_R_OCTETS               (*(volatile uint32_t*)(&_MBAR[0x9AC4]))
+#define MCF_FEC1_IEEE_R_DROP                 (*(volatile uint32_t*)(&_MBAR[0x9AC8]))
+#define MCF_FEC1_IEEE_R_FRAME_OK             (*(volatile uint32_t*)(&_MBAR[0x9ACC]))
+#define MCF_FEC1_IEEE_R_CRC                  (*(volatile uint32_t*)(&_MBAR[0x9AD0]))
+#define MCF_FEC1_IEEE_R_ALIGN                (*(volatile uint32_t*)(&_MBAR[0x9AD4]))
+#define MCF_FEC1_IEEE_R_MACERR               (*(volatile uint32_t*)(&_MBAR[0x9AD8]))
+#define MCF_FEC1_IEEE_R_FDXFC                (*(volatile uint32_t*)(&_MBAR[0x9ADC]))
+#define MCF_FEC1_IEEE_R_OCTETS_OK            (*(volatile uint32_t*)(&_MBAR[0x9AE0]))
+
+#define MCF_FEC_EIR(x)                       (*(volatile uint32_t*)(&_MBAR[0x9004 + ((x)*0x800)]))
+#define MCF_FEC_EIMR(x)                      (*(volatile uint32_t*)(&_MBAR[0x9008 + ((x)*0x800)]))
+#define MCF_FEC_ECR(x)                       (*(volatile uint32_t*)(&_MBAR[0x9024 + ((x)*0x800)]))
+#define MCF_FEC_MMFR(x)                      (*(volatile uint32_t*)(&_MBAR[0x9040 + ((x)*0x800)]))
+#define MCF_FEC_MSCR(x)                      (*(volatile uint32_t*)(&_MBAR[0x9044 + ((x)*0x800)]))
+#define MCF_FEC_MIBC(x)                      (*(volatile uint32_t*)(&_MBAR[0x9064 + ((x)*0x800)]))
+#define MCF_FEC_RCR(x)                       (*(volatile uint32_t*)(&_MBAR[0x9084 + ((x)*0x800)]))
+#define MCF_FEC_RHR(x)                       (*(volatile uint32_t*)(&_MBAR[0x9088 + ((x)*0x800)]))
+#define MCF_FEC_TCR(x)                       (*(volatile uint32_t*)(&_MBAR[0x90C4 + ((x)*0x800)]))
+#define MCF_FEC_PALR(x)                      (*(volatile uint32_t*)(&_MBAR[0x90E4 + ((x)*0x800)]))
+#define MCF_FEC_PAHR(x)                      (*(volatile uint32_t*)(&_MBAR[0x90E8 + ((x)*0x800)]))
+#define MCF_FEC_OPD(x)                       (*(volatile uint32_t*)(&_MBAR[0x90EC + ((x)*0x800)]))
+#define MCF_FEC_IAUR(x)                      (*(volatile uint32_t*)(&_MBAR[0x9118 + ((x)*0x800)]))
+#define MCF_FEC_IALR(x)                      (*(volatile uint32_t*)(&_MBAR[0x911C + ((x)*0x800)]))
+#define MCF_FEC_GAUR(x)                      (*(volatile uint32_t*)(&_MBAR[0x9120 + ((x)*0x800)]))
+#define MCF_FEC_GALR(x)                      (*(volatile uint32_t*)(&_MBAR[0x9124 + ((x)*0x800)]))
+#define MCF_FEC_FECTFWR(x)                   (*(volatile uint32_t*)(&_MBAR[0x9144 + ((x)*0x800)]))
+#define MCF_FEC_FECRFDR(x)                   (*(volatile uint32_t*)(&_MBAR[0x9184 + ((x)*0x800)]))
+#define MCF_FEC_FECRFSR(x)                   (*(volatile uint32_t*)(&_MBAR[0x9188 + ((x)*0x800)]))
+#define MCF_FEC_FECRFCR(x)                   (*(volatile uint32_t*)(&_MBAR[0x918C + ((x)*0x800)]))
+#define MCF_FEC_FECRLRFP(x)                  (*(volatile uint32_t*)(&_MBAR[0x9190 + ((x)*0x800)]))
+#define MCF_FEC_FECRLWFP(x)                  (*(volatile uint32_t*)(&_MBAR[0x9194 + ((x)*0x800)]))
+#define MCF_FEC_FECRFAR(x)                   (*(volatile uint32_t*)(&_MBAR[0x9198 + ((x)*0x800)]))
+#define MCF_FEC_FECRFRP(x)                   (*(volatile uint32_t*)(&_MBAR[0x919C + ((x)*0x800)]))
+#define MCF_FEC_FECRFWP(x)                   (*(volatile uint32_t*)(&_MBAR[0x91A0 + ((x)*0x800)]))
+#define MCF_FEC_FECTFDR(x)                   (*(volatile uint32_t*)(&_MBAR[0x91A4 + ((x)*0x800)]))
+#define MCF_FEC_FECTFSR(x)                   (*(volatile uint32_t*)(&_MBAR[0x91A8 + ((x)*0x800)]))
+#define MCF_FEC_FECTFCR(x)                   (*(volatile uint32_t*)(&_MBAR[0x91AC + ((x)*0x800)]))
+#define MCF_FEC_FECTLRFP(x)                  (*(volatile uint32_t*)(&_MBAR[0x91B0 + ((x)*0x800)]))
+#define MCF_FEC_FECTLWFP(x)                  (*(volatile uint32_t*)(&_MBAR[0x91B4 + ((x)*0x800)]))
+#define MCF_FEC_FECTFAR(x)                   (*(volatile uint32_t*)(&_MBAR[0x91B8 + ((x)*0x800)]))
+#define MCF_FEC_FECTFRP(x)                   (*(volatile uint32_t*)(&_MBAR[0x91BC + ((x)*0x800)]))
+#define MCF_FEC_FECTFWP(x)                   (*(volatile uint32_t*)(&_MBAR[0x91C0 + ((x)*0x800)]))
+#define MCF_FEC_FECFRST(x)                   (*(volatile uint32_t*)(&_MBAR[0x91C4 + ((x)*0x800)]))
+#define MCF_FEC_FECCTCWR(x)                  (*(volatile uint32_t*)(&_MBAR[0x91C8 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_DROP(x)               (*(volatile uint32_t*)(&_MBAR[0x9200 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_PACKETS(x)            (*(volatile uint32_t*)(&_MBAR[0x9204 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_BC_PKT(x)             (*(volatile uint32_t*)(&_MBAR[0x9208 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_MC_PKT(x)             (*(volatile uint32_t*)(&_MBAR[0x920C + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_CRC_ALIGN(x)          (*(volatile uint32_t*)(&_MBAR[0x9210 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_UNDERSIZE(x)          (*(volatile uint32_t*)(&_MBAR[0x9214 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_OVERSIZE(x)           (*(volatile uint32_t*)(&_MBAR[0x9218 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_FRAG(x)               (*(volatile uint32_t*)(&_MBAR[0x921C + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_JAB(x)                (*(volatile uint32_t*)(&_MBAR[0x9220 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_COL(x)                (*(volatile uint32_t*)(&_MBAR[0x9224 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_P64(x)                (*(volatile uint32_t*)(&_MBAR[0x9228 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_P65TO127(x)           (*(volatile uint32_t*)(&_MBAR[0x922C + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_P128TO255(x)          (*(volatile uint32_t*)(&_MBAR[0x9230 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_P256TO511(x)          (*(volatile uint32_t*)(&_MBAR[0x9234 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_P512TO1023(x)         (*(volatile uint32_t*)(&_MBAR[0x9238 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_P1024TO2047(x)        (*(volatile uint32_t*)(&_MBAR[0x923C + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_P_GTE2048(x)          (*(volatile uint32_t*)(&_MBAR[0x9240 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_OCTETS(x)             (*(volatile uint32_t*)(&_MBAR[0x9244 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_DROP(x)               (*(volatile uint32_t*)(&_MBAR[0x9248 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_FRAME_OK(x)           (*(volatile uint32_t*)(&_MBAR[0x924C + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_1COL(x)               (*(volatile uint32_t*)(&_MBAR[0x9250 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_MCOL(x)               (*(volatile uint32_t*)(&_MBAR[0x9254 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_DEF(x)                (*(volatile uint32_t*)(&_MBAR[0x9258 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_LCOL(x)               (*(volatile uint32_t*)(&_MBAR[0x925C + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_EXCOL(x)              (*(volatile uint32_t*)(&_MBAR[0x9260 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_MACERR(x)             (*(volatile uint32_t*)(&_MBAR[0x9264 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_CSERR(x)              (*(volatile uint32_t*)(&_MBAR[0x9268 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_SQE(x)                (*(volatile uint32_t*)(&_MBAR[0x926C + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_FDXFC(x)              (*(volatile uint32_t*)(&_MBAR[0x9270 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_OCTETS_OK(x)          (*(volatile uint32_t*)(&_MBAR[0x9274 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_DROP(x)               (*(volatile uint32_t*)(&_MBAR[0x9280 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_PACKETS(x)            (*(volatile uint32_t*)(&_MBAR[0x9284 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_BC_PKT(x)             (*(volatile uint32_t*)(&_MBAR[0x9288 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_MC_PKT(x)             (*(volatile uint32_t*)(&_MBAR[0x928C + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_CRC_ALIGN(x)          (*(volatile uint32_t*)(&_MBAR[0x9290 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_UNDERSIZE(x)          (*(volatile uint32_t*)(&_MBAR[0x9294 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_OVERSIZE(x)           (*(volatile uint32_t*)(&_MBAR[0x9298 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_FRAG(x)               (*(volatile uint32_t*)(&_MBAR[0x929C + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_JAB(x)                (*(volatile uint32_t*)(&_MBAR[0x92A0 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_RESVD_0(x)            (*(volatile uint32_t*)(&_MBAR[0x92A4 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_P64(x)                (*(volatile uint32_t*)(&_MBAR[0x92A8 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_P65TO127(x)           (*(volatile uint32_t*)(&_MBAR[0x92AC + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_P128TO255(x)          (*(volatile uint32_t*)(&_MBAR[0x92B0 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_P256TO511(x)          (*(volatile uint32_t*)(&_MBAR[0x92B4 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_P512TO1023(x)         (*(volatile uint32_t*)(&_MBAR[0x92B8 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_P1024TO2047(x)        (*(volatile uint32_t*)(&_MBAR[0x92BC + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_P_GTE2048(x)          (*(volatile uint32_t*)(&_MBAR[0x92C0 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_OCTETS(x)             (*(volatile uint32_t*)(&_MBAR[0x92C4 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_R_DROP(x)               (*(volatile uint32_t*)(&_MBAR[0x92C8 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_R_FRAME_OK(x)           (*(volatile uint32_t*)(&_MBAR[0x92CC + ((x)*0x800)]))
+#define MCF_FEC_IEEE_R_CRC(x)                (*(volatile uint32_t*)(&_MBAR[0x92D0 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_R_ALIGN(x)              (*(volatile uint32_t*)(&_MBAR[0x92D4 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_R_MACERR(x)             (*(volatile uint32_t*)(&_MBAR[0x92D8 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_R_FDXFC(x)              (*(volatile uint32_t*)(&_MBAR[0x92DC + ((x)*0x800)]))
+#define MCF_FEC_IEEE_R_OCTETS_OK(x)          (*(volatile uint32_t*)(&_MBAR[0x92E0 + ((x)*0x800)]))
+
+
+/* Bit definitions and macros for MCF_FEC_EIR */
+#define MCF_FEC_EIR_RFERR                    (0x20000)
+#define MCF_FEC_EIR_XFERR                    (0x40000)
+#define MCF_FEC_EIR_XFUN                     (0x80000)
+#define MCF_FEC_EIR_RL                       (0x100000)
+#define MCF_FEC_EIR_LC                       (0x200000)
+#define MCF_FEC_EIR_MII                      (0x800000)
+#define MCF_FEC_EIR_TXF                      (0x8000000)
+#define MCF_FEC_EIR_GRA                      (0x10000000)
+#define MCF_FEC_EIR_BABT                     (0x20000000)
+#define MCF_FEC_EIR_BABR                     (0x40000000)
+#define MCF_FEC_EIR_HBERR                    (0x80000000)
+#define MCF_FEC_EIR_CLEAR_ALL                (0xFFFFFFFF)
+
+/* Bit definitions and macros for MCF_FEC_EIMR */
+#define MCF_FEC_EIMR_RFERR                   (0x20000)
+#define MCF_FEC_EIMR_XFERR                   (0x40000)
+#define MCF_FEC_EIMR_XFUN                    (0x80000)
+#define MCF_FEC_EIMR_RL                      (0x100000)
+#define MCF_FEC_EIMR_LC                      (0x200000)
+#define MCF_FEC_EIMR_MII                     (0x800000)
+#define MCF_FEC_EIMR_TXF                     (0x8000000)
+#define MCF_FEC_EIMR_GRA                     (0x10000000)
+#define MCF_FEC_EIMR_BABT                    (0x20000000)
+#define MCF_FEC_EIMR_BABR                    (0x40000000)
+#define MCF_FEC_EIMR_HBERR                   (0x80000000)
+#define MCF_FEC_EIMR_MASK_ALL                (0)
+#define MCF_FEC_EIMR_UNMASK_ALL              (0xFFFFFFFF)
+
+/* Bit definitions and macros for MCF_FEC_ECR */
+#define MCF_FEC_ECR_RESET                    (0x1)
+#define MCF_FEC_ECR_ETHER_EN                 (0x2)
+
+/* Bit definitions and macros for MCF_FEC_MMFR */
+#define MCF_FEC_MMFR_DATA(x)                 (((x)&0xFFFF)<<0)
+#define MCF_FEC_MMFR_TA(x)                   (((x)&0x3)<<0x10)
+#define MCF_FEC_MMFR_TA_10                   (0x20000)
+#define MCF_FEC_MMFR_RA(x)                   (((x)&0x1F)<<0x12)
+#define MCF_FEC_MMFR_PA(x)                   (((x)&0x1F)<<0x17)
+#define MCF_FEC_MMFR_OP(x)                   (((x)&0x3)<<0x1C)
+#define MCF_FEC_MMFR_OP_READ                 (0x20000000)
+#define MCF_FEC_MMFR_OP_WRITE                (0x10000000)
+#define MCF_FEC_MMFR_ST(x)                   (((x)&0x3)<<0x1E)
+#define MCF_FEC_MMFR_ST_01                   (0x40000000)
+
+/* Bit definitions and macros for MCF_FEC_MSCR */
+#define MCF_FEC_MSCR_MII_SPEED(x)            (((x)&0x3F)<<0x1)
+#define MCF_FEC_MSCR_DIS_PREAMBLE            (0x80)
+#define MCF_FEC_MSCR_MII_SPEED_133           (0x1B<<0x1)
+#define MCF_FEC_MSCR_MII_SPEED_120           (0x18<<0x1)
+#define MCF_FEC_MSCR_MII_SPEED_66            (0xE<<0x1)
+#define MCF_FEC_MSCR_MII_SPEED_60            (0xC<<0x1)
+
+/* Bit definitions and macros for MCF_FEC_MIBC */
+#define MCF_FEC_MIBC_MIB_IDLE                (0x40000000)
+#define MCF_FEC_MIBC_MIB_DISABLE             (0x80000000)
+
+/* Bit definitions and macros for MCF_FEC_RCR */
+#define MCF_FEC_RCR_LOOP                     (0x1)
+#define MCF_FEC_RCR_DRT                      (0x2)
+#define MCF_FEC_RCR_MII_MODE                 (0x4)
+#define MCF_FEC_RCR_PROM                     (0x8)
+#define MCF_FEC_RCR_BC_REJ                   (0x10)
+#define MCF_FEC_RCR_FCE                      (0x20)
+#define MCF_FEC_RCR_MAX_FL(x)                (((x)&0x7FF)<<0x10)
+
+/* Bit definitions and macros for MCF_FEC_RHR */
+#define MCF_FEC_RHR_HASH(x)                  (((x)&0x3F)<<0x18)
+#define MCF_FEC_RHR_MULTCAST                 (0x40000000)
+#define MCF_FEC_RHR_FCE                      (0x80000000)
+
+/* Bit definitions and macros for MCF_FEC_TCR */
+#define MCF_FEC_TCR_GTS                      (0x1)
+#define MCF_FEC_TCR_HBC                      (0x2)
+#define MCF_FEC_TCR_FDEN                     (0x4)
+#define MCF_FEC_TCR_TFC_PAUSE                (0x8)
+#define MCF_FEC_TCR_RFC_PAUSE                (0x10)
+
+/* Bit definitions and macros for MCF_FEC_PALR */
+#define MCF_FEC_PALR_PADDR1(x)               (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_PAHR */
+#define MCF_FEC_PAHR_TYPE(x)                 (((x)&0xFFFF)<<0)
+#define MCF_FEC_PAHR_PADDR2(x)               (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_FEC_OPD */
+#define MCF_FEC_OPD_PAUSE_DUR(x)             (((x)&0xFFFF)<<0)
+#define MCF_FEC_OPD_OPCODE(x)                (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_FEC_IAUR */
+#define MCF_FEC_IAUR_IADDR1(x)               (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IALR */
+#define MCF_FEC_IALR_IADDR2(x)               (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_GAUR */
+#define MCF_FEC_GAUR_GADDR1(x)               (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_GALR */
+#define MCF_FEC_GALR_GADDR2(x)               (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECTFWR */
+#define MCF_FEC_FECTFWR_X_WMRK(x)            (((x)&0xF)<<0)
+#define MCF_FEC_FECTFWR_X_WMRK_64            (0)
+#define MCF_FEC_FECTFWR_X_WMRK_128           (0x1)
+#define MCF_FEC_FECTFWR_X_WMRK_192           (0x2)
+#define MCF_FEC_FECTFWR_X_WMRK_256           (0x3)
+#define MCF_FEC_FECTFWR_X_WMRK_320           (0x4)
+#define MCF_FEC_FECTFWR_X_WMRK_384           (0x5)
+#define MCF_FEC_FECTFWR_X_WMRK_448           (0x6)
+#define MCF_FEC_FECTFWR_X_WMRK_512           (0x7)
+#define MCF_FEC_FECTFWR_X_WMRK_576           (0x8)
+#define MCF_FEC_FECTFWR_X_WMRK_640           (0x9)
+#define MCF_FEC_FECTFWR_X_WMRK_704           (0xA)
+#define MCF_FEC_FECTFWR_X_WMRK_768           (0xB)
+#define MCF_FEC_FECTFWR_X_WMRK_832           (0xC)
+#define MCF_FEC_FECTFWR_X_WMRK_896           (0xD)
+#define MCF_FEC_FECTFWR_X_WMRK_960           (0xE)
+#define MCF_FEC_FECTFWR_X_WMRK_1024          (0xF)
+
+/* Bit definitions and macros for MCF_FEC_FECRFDR */
+#define MCF_FEC_FECRFDR_FIFO_DATA(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECRFSR */
+#define MCF_FEC_FECRFSR_EMT                  (0x10000)
+#define MCF_FEC_FECRFSR_ALARM                (0x20000)
+#define MCF_FEC_FECRFSR_FU                   (0x40000)
+#define MCF_FEC_FECRFSR_FRMRDY               (0x80000)
+#define MCF_FEC_FECRFSR_OF                   (0x100000)
+#define MCF_FEC_FECRFSR_UF                   (0x200000)
+#define MCF_FEC_FECRFSR_RXW                  (0x400000)
+#define MCF_FEC_FECRFSR_FAE                  (0x800000)
+#define MCF_FEC_FECRFSR_FRM(x)               (((x)&0xF)<<0x18)
+#define MCF_FEC_FECRFSR_IP                   (0x80000000)
+
+/* Bit definitions and macros for MCF_FEC_FECRFCR */
+#define MCF_FEC_FECRFCR_COUNTER(x)           (((x)&0xFFFF)<<0)
+#define MCF_FEC_FECRFCR_OF_MSK               (0x80000)
+#define MCF_FEC_FECRFCR_UF_MSK               (0x100000)
+#define MCF_FEC_FECRFCR_RXW_MSK              (0x200000)
+#define MCF_FEC_FECRFCR_FAE_MSK              (0x400000)
+#define MCF_FEC_FECRFCR_IP_MSK               (0x800000)
+#define MCF_FEC_FECRFCR_GR(x)                (((x)&0x7)<<0x18)
+#define MCF_FEC_FECRFCR_FRMEN                (0x8000000)
+#define MCF_FEC_FECRFCR_TIMER                (0x10000000)
+
+/* Bit definitions and macros for MCF_FEC_FECRLRFP */
+#define MCF_FEC_FECRLRFP_LRFP(x)             (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECRLWFP */
+#define MCF_FEC_FECRLWFP_LWFP(x)             (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECRFAR */
+#define MCF_FEC_FECRFAR_ALARM(x)             (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECRFRP */
+#define MCF_FEC_FECRFRP_READ(x)              (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECRFWP */
+#define MCF_FEC_FECRFWP_WRITE(x)             (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECTFDR */
+#define MCF_FEC_FECTFDR_FIFO_DATA(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECTFSR */
+#define MCF_FEC_FECTFSR_EMT                  (0x10000)
+#define MCF_FEC_FECTFSR_ALARM                (0x20000)
+#define MCF_FEC_FECTFSR_FU                   (0x40000)
+#define MCF_FEC_FECTFSR_FRMRDY               (0x80000)
+#define MCF_FEC_FECTFSR_OF                   (0x100000)
+#define MCF_FEC_FECTFSR_UF                   (0x200000)
+#define MCF_FEC_FECTFSR_FAE                  (0x800000)
+#define MCF_FEC_FECTFSR_FRM(x)               (((x)&0xF)<<0x18)
+#define MCF_FEC_FECTFSR_TXW                  (0x40000000)
+#define MCF_FEC_FECTFSR_IP                   (0x80000000)
+
+/* Bit definitions and macros for MCF_FEC_FECTFCR */
+#define MCF_FEC_FECTFCR_RESERVED             (0x200000)
+#define MCF_FEC_FECTFCR_COUNTER(x)           (((x)&0xFFFF)<<0|0x200000)
+#define MCF_FEC_FECTFCR_TXW_MASK             (0x240000)
+#define MCF_FEC_FECTFCR_OF_MSK               (0x280000)
+#define MCF_FEC_FECTFCR_UF_MSK               (0x300000)
+#define MCF_FEC_FECTFCR_FAE_MSK              (0x600000)
+#define MCF_FEC_FECTFCR_IP_MSK               (0xA00000)
+#define MCF_FEC_FECTFCR_GR(x)                (((x)&0x7)<<0x18|0x200000)
+#define MCF_FEC_FECTFCR_FRMEN                (0x8200000)
+#define MCF_FEC_FECTFCR_TIMER                (0x10200000)
+#define MCF_FEC_FECTFCR_WFR                  (0x20200000)
+#define MCF_FEC_FECTFCR_WCTL                 (0x40200000)
+
+/* Bit definitions and macros for MCF_FEC_FECTLRFP */
+#define MCF_FEC_FECTLRFP_LRFP(x)             (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECTLWFP */
+#define MCF_FEC_FECTLWFP_LWFP(x)             (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECTFAR */
+#define MCF_FEC_FECTFAR_ALARM(x)             (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECTFRP */
+#define MCF_FEC_FECTFRP_READ(x)              (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECTFWP */
+#define MCF_FEC_FECTFWP_WRITE(x)             (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECFRST */
+#define MCF_FEC_FECFRST_RST_CTL              (0x1000000)
+#define MCF_FEC_FECFRST_SW_RST               (0x2000000)
+
+/* Bit definitions and macros for MCF_FEC_FECCTCWR */
+#define MCF_FEC_FECCTCWR_TFCW                (0x1000000)
+#define MCF_FEC_FECCTCWR_CRC                 (0x2000000)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_DROP */
+#define MCF_FEC_RMON_T_DROP_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_PACKETS */
+#define MCF_FEC_RMON_T_PACKETS_Value(x)      (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_BC_PKT */
+#define MCF_FEC_RMON_T_BC_PKT_Value(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_MC_PKT */
+#define MCF_FEC_RMON_T_MC_PKT_Value(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_CRC_ALIGN */
+#define MCF_FEC_RMON_T_CRC_ALIGN_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_UNDERSIZE */
+#define MCF_FEC_RMON_T_UNDERSIZE_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_OVERSIZE */
+#define MCF_FEC_RMON_T_OVERSIZE_Value(x)     (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_FRAG */
+#define MCF_FEC_RMON_T_FRAG_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_JAB */
+#define MCF_FEC_RMON_T_JAB_Value(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_COL */
+#define MCF_FEC_RMON_T_COL_Value(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_P64 */
+#define MCF_FEC_RMON_T_P64_Value(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_P65TO127 */
+#define MCF_FEC_RMON_T_P65TO127_Value(x)     (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_P128TO255 */
+#define MCF_FEC_RMON_T_P128TO255_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_P256TO511 */
+#define MCF_FEC_RMON_T_P256TO511_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_P512TO1023 */
+#define MCF_FEC_RMON_T_P512TO1023_Value(x)   (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_P1024TO2047 */
+#define MCF_FEC_RMON_T_P1024TO2047_Value(x)  (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_P_GTE2048 */
+#define MCF_FEC_RMON_T_P_GTE2048_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_OCTETS */
+#define MCF_FEC_RMON_T_OCTETS_Value(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_DROP */
+#define MCF_FEC_IEEE_T_DROP_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_FRAME_OK */
+#define MCF_FEC_IEEE_T_FRAME_OK_Value(x)     (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_1COL */
+#define MCF_FEC_IEEE_T_1COL_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_MCOL */
+#define MCF_FEC_IEEE_T_MCOL_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_DEF */
+#define MCF_FEC_IEEE_T_DEF_Value(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_LCOL */
+#define MCF_FEC_IEEE_T_LCOL_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_EXCOL */
+#define MCF_FEC_IEEE_T_EXCOL_Value(x)        (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_MACERR */
+#define MCF_FEC_IEEE_T_MACERR_Value(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_CSERR */
+#define MCF_FEC_IEEE_T_CSERR_Value(x)        (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_SQE */
+#define MCF_FEC_IEEE_T_SQE_Value(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_FDXFC */
+#define MCF_FEC_IEEE_T_FDXFC_Value(x)        (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_OCTETS_OK */
+#define MCF_FEC_IEEE_T_OCTETS_OK_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_DROP */
+#define MCF_FEC_RMON_R_DROP_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_PACKETS */
+#define MCF_FEC_RMON_R_PACKETS_Value(x)      (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_BC_PKT */
+#define MCF_FEC_RMON_R_BC_PKT_Value(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_MC_PKT */
+#define MCF_FEC_RMON_R_MC_PKT_Value(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_CRC_ALIGN */
+#define MCF_FEC_RMON_R_CRC_ALIGN_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_UNDERSIZE */
+#define MCF_FEC_RMON_R_UNDERSIZE_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_OVERSIZE */
+#define MCF_FEC_RMON_R_OVERSIZE_Value(x)     (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_FRAG */
+#define MCF_FEC_RMON_R_FRAG_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_JAB */
+#define MCF_FEC_RMON_R_JAB_Value(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_RESVD_0 */
+#define MCF_FEC_RMON_R_RESVD_0_Value(x)      (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_P64 */
+#define MCF_FEC_RMON_R_P64_Value(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_P65TO127 */
+#define MCF_FEC_RMON_R_P65TO127_Value(x)     (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_P128TO255 */
+#define MCF_FEC_RMON_R_P128TO255_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_P256TO511 */
+#define MCF_FEC_RMON_R_P256TO511_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_P512TO1023 */
+#define MCF_FEC_RMON_R_P512TO1023_Value(x)   (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_P1024TO2047 */
+#define MCF_FEC_RMON_R_P1024TO2047_Value(x)  (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_P_GTE2048 */
+#define MCF_FEC_RMON_R_P_GTE2048_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_OCTETS */
+#define MCF_FEC_RMON_R_OCTETS_Value(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_R_DROP */
+#define MCF_FEC_IEEE_R_DROP_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_R_FRAME_OK */
+#define MCF_FEC_IEEE_R_FRAME_OK_Value(x)     (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_R_CRC */
+#define MCF_FEC_IEEE_R_CRC_Value(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_R_ALIGN */
+#define MCF_FEC_IEEE_R_ALIGN_Value(x)        (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_R_MACERR */
+#define MCF_FEC_IEEE_R_MACERR_Value(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_R_FDXFC */
+#define MCF_FEC_IEEE_R_FDXFC_Value(x)        (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_R_OCTETS_OK */
+#define MCF_FEC_IEEE_R_OCTETS_OK_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+
+#endif /* __MCF5475_FEC_H__ */
--- a/tos/fpga_test/include/MCF5475_GPIO.h
+++ b/tos/fpga_test/include/MCF5475_GPIO.h
@@ -0,0 +1,543 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_GPIO_H__
+#define __MCF5475_GPIO_H__
+
+
+/*********************************************************************
+*
+* General Purpose I/O (GPIO)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_GPIO_PODR_FBCTL                  (*(volatile uint8_t *)(&_MBAR[0xA00]))
+#define MCF_GPIO_PDDR_FBCTL                  (*(volatile uint8_t *)(&_MBAR[0xA10]))
+#define MCF_GPIO_PPDSDR_FBCTL                (*(volatile uint8_t *)(&_MBAR[0xA20]))
+#define MCF_GPIO_PCLRR_FBCTL                 (*(volatile uint8_t *)(&_MBAR[0xA30]))
+
+#define MCF_GPIO_PODR_FBCS                   (*(volatile uint8_t *)(&_MBAR[0xA01]))
+#define MCF_GPIO_PDDR_FBCS                   (*(volatile uint8_t *)(&_MBAR[0xA11]))
+#define MCF_GPIO_PPDSDR_FBCS                 (*(volatile uint8_t *)(&_MBAR[0xA21]))
+#define MCF_GPIO_PCLRR_FBCS                  (*(volatile uint8_t *)(&_MBAR[0xA31]))
+
+#define MCF_GPIO_PODR_DMA                    (*(volatile uint8_t *)(&_MBAR[0xA02]))
+#define MCF_GPIO_PDDR_DMA                    (*(volatile uint8_t *)(&_MBAR[0xA12]))
+#define MCF_GPIO_PPDSDR_DMA                  (*(volatile uint8_t *)(&_MBAR[0xA22]))
+#define MCF_GPIO_PCLRR_DMA                   (*(volatile uint8_t *)(&_MBAR[0xA32]))
+
+#define MCF_GPIO_PODR_FEC0H                  (*(volatile uint8_t *)(&_MBAR[0xA04]))
+#define MCF_GPIO_PDDR_FEC0H                  (*(volatile uint8_t *)(&_MBAR[0xA14]))
+#define MCF_GPIO_PPDSDR_FEC0H                (*(volatile uint8_t *)(&_MBAR[0xA24]))
+#define MCF_GPIO_PCLRR_FEC0H                 (*(volatile uint8_t *)(&_MBAR[0xA34]))
+
+#define MCF_GPIO_PODR_FEC0L                  (*(volatile uint8_t *)(&_MBAR[0xA05]))
+#define MCF_GPIO_PDDR_FEC0L                  (*(volatile uint8_t *)(&_MBAR[0xA15]))
+#define MCF_GPIO_PPDSDR_FEC0L                (*(volatile uint8_t *)(&_MBAR[0xA25]))
+#define MCF_GPIO_PCLRR_FEC0L                 (*(volatile uint8_t *)(&_MBAR[0xA35]))
+
+#define MCF_GPIO_PODR_FEC1H                  (*(volatile uint8_t *)(&_MBAR[0xA06]))
+#define MCF_GPIO_PDDR_FEC1H                  (*(volatile uint8_t *)(&_MBAR[0xA16]))
+#define MCF_GPIO_PPDSDR_FEC1H                (*(volatile uint8_t *)(&_MBAR[0xA26]))
+#define MCF_GPIO_PCLRR_FEC1H                 (*(volatile uint8_t *)(&_MBAR[0xA36]))
+
+#define MCF_GPIO_PODR_FEC1L                  (*(volatile uint8_t *)(&_MBAR[0xA07]))
+#define MCF_GPIO_PDDR_FEC1L                  (*(volatile uint8_t *)(&_MBAR[0xA17]))
+#define MCF_GPIO_PPDSDR_FEC1L                (*(volatile uint8_t *)(&_MBAR[0xA27]))
+#define MCF_GPIO_PCLRR_FEC1L                 (*(volatile uint8_t *)(&_MBAR[0xA37]))
+
+#define MCF_GPIO_PODR_FECI2C                 (*(volatile uint8_t *)(&_MBAR[0xA08]))
+#define MCF_GPIO_PDDR_FECI2C                 (*(volatile uint8_t *)(&_MBAR[0xA18]))
+#define MCF_GPIO_PPDSDR_FECI2C               (*(volatile uint8_t *)(&_MBAR[0xA28]))
+#define MCF_GPIO_PCLRR_FECI2C                (*(volatile uint8_t *)(&_MBAR[0xA38]))
+
+#define MCF_GPIO_PODR_PCIBG                  (*(volatile uint8_t *)(&_MBAR[0xA09]))
+#define MCF_GPIO_PDDR_PCIBG                  (*(volatile uint8_t *)(&_MBAR[0xA19]))
+#define MCF_GPIO_PPDSDR_PCIBG                (*(volatile uint8_t *)(&_MBAR[0xA29]))
+#define MCF_GPIO_PCLRR_PCIBG                 (*(volatile uint8_t *)(&_MBAR[0xA39]))
+
+#define MCF_GPIO_PODR_PCIBR                  (*(volatile uint8_t *)(&_MBAR[0xA0A]))
+#define MCF_GPIO_PDDR_PCIBR                  (*(volatile uint8_t *)(&_MBAR[0xA1A]))
+#define MCF_GPIO_PPDSDR_PCIBR                (*(volatile uint8_t *)(&_MBAR[0xA2A]))
+#define MCF_GPIO_PCLRR_PCIBR                 (*(volatile uint8_t *)(&_MBAR[0xA3A]))
+
+#define MCF_GPIO2_PODR_PSC3PSC               (*(volatile uint8_t *)(&_MBAR[0xA0C]))
+#define MCF_GPIO2_PDDR_PSC3PSC               (*(volatile uint8_t *)(&_MBAR[0xA1C]))
+#define MCF_GPIO2_PPDSDR_PSC3PSC             (*(volatile uint8_t *)(&_MBAR[0xA2C]))
+#define MCF_GPIO2_PCLRR_PSC3PSC              (*(volatile uint8_t *)(&_MBAR[0xA3C]))
+
+#define MCF_GPIO0_PODR_PSC1PSC               (*(volatile uint8_t *)(&_MBAR[0xA0D]))
+#define MCF_GPIO0_PDDR_PSC1PSC               (*(volatile uint8_t *)(&_MBAR[0xA1D]))
+#define MCF_GPIO0_PPDSDR_PSC1PSC             (*(volatile uint8_t *)(&_MBAR[0xA2D]))
+#define MCF_GPIO0_PCLRR_PSC1PSC              (*(volatile uint8_t *)(&_MBAR[0xA3D]))
+
+#define MCF_GPIO_PODR_DSPI                   (*(volatile uint8_t *)(&_MBAR[0xA0E]))
+#define MCF_GPIO_PDDR_DSPI                   (*(volatile uint8_t *)(&_MBAR[0xA1E]))
+#define MCF_GPIO_PPDSDR_DSPI                 (*(volatile uint8_t *)(&_MBAR[0xA2E]))
+#define MCF_GPIO_PCLRR_DSPI                  (*(volatile uint8_t *)(&_MBAR[0xA3E]))
+
+
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FBCTL */
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL0      (0x1)
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL1      (0x2)
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL2      (0x4)
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL3      (0x8)
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL4      (0x10)
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL5      (0x20)
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL6      (0x40)
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FBCTL */
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL0      (0x1)
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL1      (0x2)
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL2      (0x4)
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL3      (0x8)
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL4      (0x10)
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL5      (0x20)
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL6      (0x40)
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCTL */
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL0  (0x1)
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL1  (0x2)
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL2  (0x4)
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL3  (0x8)
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL4  (0x10)
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL5  (0x20)
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL6  (0x40)
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL7  (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCTL */
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL0    (0x1)
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL1    (0x2)
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL2    (0x4)
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL3    (0x8)
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL4    (0x10)
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL5    (0x20)
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL6    (0x40)
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL7    (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FBCS */
+#define MCF_GPIO_PODR_FBCS_PODR_FBCS1        (0x2)
+#define MCF_GPIO_PODR_FBCS_PODR_FBCS2        (0x4)
+#define MCF_GPIO_PODR_FBCS_PODR_FBCS3        (0x8)
+#define MCF_GPIO_PODR_FBCS_PODR_FBCS4        (0x10)
+#define MCF_GPIO_PODR_FBCS_PODR_FBCS5        (0x20)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FBCS */
+#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS1        (0x2)
+#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS2        (0x4)
+#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS3        (0x8)
+#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS4        (0x10)
+#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS5        (0x20)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCS */
+#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS1    (0x2)
+#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS2    (0x4)
+#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS3    (0x8)
+#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS4    (0x10)
+#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS5    (0x20)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCS */
+#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS1      (0x2)
+#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS2      (0x4)
+#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS3      (0x8)
+#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS4      (0x10)
+#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS5      (0x20)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_DMA */
+#define MCF_GPIO_PODR_DMA_PODR_DMA0          (0x1)
+#define MCF_GPIO_PODR_DMA_PODR_DMA1          (0x2)
+#define MCF_GPIO_PODR_DMA_PODR_DMA2          (0x4)
+#define MCF_GPIO_PODR_DMA_PODR_DMA3          (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_DMA */
+#define MCF_GPIO_PDDR_DMA_PDDR_DMA0          (0x1)
+#define MCF_GPIO_PDDR_DMA_PDDR_DMA1          (0x2)
+#define MCF_GPIO_PDDR_DMA_PDDR_DMA2          (0x4)
+#define MCF_GPIO_PDDR_DMA_PDDR_DMA3          (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_DMA */
+#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA0      (0x1)
+#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA1      (0x2)
+#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA2      (0x4)
+#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA3      (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_DMA */
+#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA0        (0x1)
+#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA1        (0x2)
+#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA2        (0x4)
+#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA3        (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FEC0H */
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H0      (0x1)
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H1      (0x2)
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H2      (0x4)
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H3      (0x8)
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H4      (0x10)
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H5      (0x20)
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H6      (0x40)
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0H */
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H0      (0x1)
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H1      (0x2)
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H2      (0x4)
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H3      (0x8)
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H4      (0x10)
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H5      (0x20)
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H6      (0x40)
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0H */
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H0  (0x1)
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H1  (0x2)
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H2  (0x4)
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H3  (0x8)
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H4  (0x10)
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H5  (0x20)
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H6  (0x40)
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H7  (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0H */
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H0    (0x1)
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H1    (0x2)
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H2    (0x4)
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H3    (0x8)
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H4    (0x10)
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H5    (0x20)
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H6    (0x40)
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H7    (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FEC0L */
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L0      (0x1)
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L1      (0x2)
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L2      (0x4)
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L3      (0x8)
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L4      (0x10)
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L5      (0x20)
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L6      (0x40)
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0L */
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L0      (0x1)
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L1      (0x2)
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L2      (0x4)
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L3      (0x8)
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L4      (0x10)
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L5      (0x20)
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L6      (0x40)
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0L */
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L0  (0x1)
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L1  (0x2)
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L2  (0x4)
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L3  (0x8)
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L4  (0x10)
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L5  (0x20)
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L6  (0x40)
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L7  (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0L */
+#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L0    (0x1)
+#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L1    (0x2)
+#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L2    (0x4)
+#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L3    (0x8)
+#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L4    (0x10)
+#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L5    (0x20)
+#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L6    (0x40)
+#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L7    (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FEC1H */
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H0      (0x1)
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H1      (0x2)
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H2      (0x4)
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H3      (0x8)
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H4      (0x10)
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H5      (0x20)
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H6      (0x40)
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1H */
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H0      (0x1)
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H1      (0x2)
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H2      (0x4)
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H3      (0x8)
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H4      (0x10)
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H5      (0x20)
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H6      (0x40)
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1H */
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H0  (0x1)
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H1  (0x2)
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H2  (0x4)
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H3  (0x8)
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H4  (0x10)
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H5  (0x20)
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H6  (0x40)
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H7  (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1H */
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H0    (0x1)
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H1    (0x2)
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H2    (0x4)
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H3    (0x8)
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H4    (0x10)
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H5    (0x20)
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H6    (0x40)
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H7    (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FEC1L */
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L0      (0x1)
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L1      (0x2)
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L2      (0x4)
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L3      (0x8)
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L4      (0x10)
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L5      (0x20)
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L6      (0x40)
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1L */
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L0      (0x1)
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L1      (0x2)
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L2      (0x4)
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L3      (0x8)
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4      (0x10)
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L5      (0x20)
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L6      (0x40)
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1L */
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L0  (0x1)
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L1  (0x2)
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L2  (0x4)
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L3  (0x8)
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L4  (0x10)
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L5  (0x20)
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L6  (0x40)
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L7  (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1L */
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L0    (0x1)
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L1    (0x2)
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L2    (0x4)
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L3    (0x8)
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L4    (0x10)
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L5    (0x20)
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L6    (0x40)
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L7    (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FECI2C */
+#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C0    (0x1)
+#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C1    (0x2)
+#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C2    (0x4)
+#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C3    (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FECI2C */
+#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0    (0x1)
+#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1    (0x2)
+#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C2    (0x4)
+#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C3    (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECI2C */
+#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C0 (0x1)
+#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C1 (0x2)
+#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C2 (0x4)
+#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C3 (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FECI2C */
+#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C0  (0x1)
+#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C1  (0x2)
+#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C2  (0x4)
+#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C3  (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_PCIBG */
+#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG0      (0x1)
+#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG1      (0x2)
+#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG2      (0x4)
+#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG3      (0x8)
+#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG4      (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBG */
+#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG0      (0x1)
+#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG1      (0x2)
+#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG2      (0x4)
+#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG3      (0x8)
+#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG4      (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBG */
+#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG0  (0x1)
+#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG1  (0x2)
+#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG2  (0x4)
+#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG3  (0x8)
+#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG4  (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBG */
+#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG0    (0x1)
+#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG1    (0x2)
+#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG2    (0x4)
+#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG3    (0x8)
+#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG4    (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_PCIBR */
+#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR0      (0x1)
+#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR1      (0x2)
+#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR2      (0x4)
+#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR3      (0x8)
+#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR4      (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBR */
+#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR0      (0x1)
+#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR1      (0x2)
+#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR2      (0x4)
+#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR3      (0x8)
+#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR4      (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBR */
+#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR0  (0x1)
+#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR1  (0x2)
+#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR2  (0x4)
+#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR3  (0x8)
+#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR4  (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBR */
+#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR0    (0x1)
+#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR1    (0x2)
+#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR2    (0x4)
+#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR3    (0x8)
+#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR4    (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_PSC3PSC */
+#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC20 (0x1)
+#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC21 (0x2)
+#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC22 (0x4)
+#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC23 (0x8)
+#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC24 (0x10)
+#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC25 (0x20)
+#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC26 (0x40)
+#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC27 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_PSC3PSC */
+#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC20 (0x1)
+#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC21 (0x2)
+#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC22 (0x4)
+#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC23 (0x8)
+#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC24 (0x10)
+#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC25 (0x20)
+#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC26 (0x40)
+#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC27 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC3PSC */
+#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC20 (0x1)
+#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC21 (0x2)
+#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC22 (0x4)
+#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC23 (0x8)
+#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC24 (0x10)
+#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC25 (0x20)
+#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC26 (0x40)
+#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC27 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC3PSC */
+#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC20 (0x1)
+#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC21 (0x2)
+#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC22 (0x4)
+#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC23 (0x8)
+#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC24 (0x10)
+#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC25 (0x20)
+#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC26 (0x40)
+#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC27 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_PSC1PSC */
+#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC00 (0x1)
+#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC01 (0x2)
+#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC02 (0x4)
+#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC03 (0x8)
+#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC04 (0x10)
+#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC05 (0x20)
+#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC06 (0x40)
+#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC07 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_PSC1PSC */
+#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC00 (0x1)
+#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC01 (0x2)
+#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC02 (0x4)
+#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC03 (0x8)
+#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC04 (0x10)
+#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC05 (0x20)
+#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC06 (0x40)
+#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC07 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC1PSC */
+#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC00 (0x1)
+#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC01 (0x2)
+#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC02 (0x4)
+#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC03 (0x8)
+#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC04 (0x10)
+#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC05 (0x20)
+#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC06 (0x40)
+#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC07 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC1PSC */
+#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC00 (0x1)
+#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC01 (0x2)
+#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC02 (0x4)
+#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC03 (0x8)
+#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC04 (0x10)
+#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC05 (0x20)
+#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC06 (0x40)
+#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC07 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_DSPI */
+#define MCF_GPIO_PODR_DSPI_PODR_DSPI0        (0x1)
+#define MCF_GPIO_PODR_DSPI_PODR_DSPI1        (0x2)
+#define MCF_GPIO_PODR_DSPI_PODR_DSPI2        (0x4)
+#define MCF_GPIO_PODR_DSPI_PODR_DSPI3        (0x8)
+#define MCF_GPIO_PODR_DSPI_PODR_DSPI4        (0x10)
+#define MCF_GPIO_PODR_DSPI_PODR_DSPI5        (0x20)
+#define MCF_GPIO_PODR_DSPI_PODR_DSPI6        (0x40)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_DSPI */
+#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI0        (0x1)
+#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI1        (0x2)
+#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI2        (0x4)
+#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI3        (0x8)
+#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI4        (0x10)
+#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI5        (0x20)
+#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI6        (0x40)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_DSPI */
+#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI0    (0x1)
+#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI1    (0x2)
+#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI2    (0x4)
+#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI3    (0x8)
+#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI4    (0x10)
+#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI5    (0x20)
+#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI6    (0x40)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_DSPI */
+#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI0      (0x1)
+#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI1      (0x2)
+#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI2      (0x4)
+#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI3      (0x8)
+#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI4      (0x10)
+#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI5      (0x20)
+#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI6      (0x40)
+
+
+#endif /* __MCF5475_GPIO_H__ */
--- a/tos/fpga_test/include/MCF5475_GPT.h
+++ b/tos/fpga_test/include/MCF5475_GPT.h
@@ -0,0 +1,100 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_GPT_H__
+#define __MCF5475_GPT_H__
+
+
+/*********************************************************************
+*
+* General Purpose Timers (GPT)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_GPT0_GMS                         (*(volatile uint32_t*)(&_MBAR[0x800]))
+#define MCF_GPT0_GCIR                        (*(volatile uint32_t*)(&_MBAR[0x804]))
+#define MCF_GPT0_GPWM                        (*(volatile uint32_t*)(&_MBAR[0x808]))
+#define MCF_GPT0_GSR                         (*(volatile uint32_t*)(&_MBAR[0x80C]))
+
+#define MCF_GPT1_GMS                         (*(volatile uint32_t*)(&_MBAR[0x810]))
+#define MCF_GPT1_GCIR                        (*(volatile uint32_t*)(&_MBAR[0x814]))
+#define MCF_GPT1_GPWM                        (*(volatile uint32_t*)(&_MBAR[0x818]))
+#define MCF_GPT1_GSR                         (*(volatile uint32_t*)(&_MBAR[0x81C]))
+
+#define MCF_GPT2_GMS                         (*(volatile uint32_t*)(&_MBAR[0x820]))
+#define MCF_GPT2_GCIR                        (*(volatile uint32_t*)(&_MBAR[0x824]))
+#define MCF_GPT2_GPWM                        (*(volatile uint32_t*)(&_MBAR[0x828]))
+#define MCF_GPT2_GSR                         (*(volatile uint32_t*)(&_MBAR[0x82C]))
+
+#define MCF_GPT3_GMS                         (*(volatile uint32_t*)(&_MBAR[0x830]))
+#define MCF_GPT3_GCIR                        (*(volatile uint32_t*)(&_MBAR[0x834]))
+#define MCF_GPT3_GPWM                        (*(volatile uint32_t*)(&_MBAR[0x838]))
+#define MCF_GPT3_GSR                         (*(volatile uint32_t*)(&_MBAR[0x83C]))
+
+#define MCF_GPT_GMS(x)                       (*(volatile uint32_t*)(&_MBAR[0x800 + ((x)*0x10)]))
+#define MCF_GPT_GCIR(x)                      (*(volatile uint32_t*)(&_MBAR[0x804 + ((x)*0x10)]))
+#define MCF_GPT_GPWM(x)                      (*(volatile uint32_t*)(&_MBAR[0x808 + ((x)*0x10)]))
+#define MCF_GPT_GSR(x)                       (*(volatile uint32_t*)(&_MBAR[0x80C + ((x)*0x10)]))
+
+
+/* Bit definitions and macros for MCF_GPT_GMS */
+#define MCF_GPT_GMS_TMS(x)                   (((x)&0x7)<<0)
+#define MCF_GPT_GMS_TMS_DISABLE              (0)
+#define MCF_GPT_GMS_TMS_INCAPT               (0x1)
+#define MCF_GPT_GMS_TMS_OUTCAPT              (0x2)
+#define MCF_GPT_GMS_TMS_PWM                  (0x3)
+#define MCF_GPT_GMS_TMS_GPIO                 (0x4)
+#define MCF_GPT_GMS_GPIO(x)                  (((x)&0x3)<<0x4)
+#define MCF_GPT_GMS_GPIO_INPUT               (0)
+#define MCF_GPT_GMS_GPIO_OUTLO               (0x20)
+#define MCF_GPT_GMS_GPIO_OUTHI               (0x30)
+#define MCF_GPT_GMS_IEN                      (0x100)
+#define MCF_GPT_GMS_OD                       (0x200)
+#define MCF_GPT_GMS_SC                       (0x400)
+#define MCF_GPT_GMS_CE                       (0x1000)
+#define MCF_GPT_GMS_WDEN                     (0x8000)
+#define MCF_GPT_GMS_ICT(x)                   (((x)&0x3)<<0x10)
+#define MCF_GPT_GMS_ICT_ANY                  (0)
+#define MCF_GPT_GMS_ICT_RISE                 (0x10000)
+#define MCF_GPT_GMS_ICT_FALL                 (0x20000)
+#define MCF_GPT_GMS_ICT_PULSE                (0x30000)
+#define MCF_GPT_GMS_OCT(x)                   (((x)&0x3)<<0x14)
+#define MCF_GPT_GMS_OCT_FRCLOW               (0)
+#define MCF_GPT_GMS_OCT_PULSEHI              (0x100000)
+#define MCF_GPT_GMS_OCT_PULSELO              (0x200000)
+#define MCF_GPT_GMS_OCT_TOGGLE               (0x300000)
+#define MCF_GPT_GMS_OCPW(x)                  (((x)&0xFF)<<0x18)
+
+/* Bit definitions and macros for MCF_GPT_GCIR */
+#define MCF_GPT_GCIR_CNT(x)                  (((x)&0xFFFF)<<0)
+#define MCF_GPT_GCIR_PRE(x)                  (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_GPT_GPWM */
+#define MCF_GPT_GPWM_LOAD                    (0x1)
+#define MCF_GPT_GPWM_PWMOP                   (0x100)
+#define MCF_GPT_GPWM_WIDTH(x)                (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_GPT_GSR */
+#define MCF_GPT_GSR_CAPT                     (0x1)
+#define MCF_GPT_GSR_COMP                     (0x2)
+#define MCF_GPT_GSR_PWMP                     (0x4)
+#define MCF_GPT_GSR_TEXP                     (0x8)
+#define MCF_GPT_GSR_PIN                      (0x100)
+#define MCF_GPT_GSR_OVF(x)                   (((x)&0x7)<<0xC)
+#define MCF_GPT_GSR_CAPTURE(x)               (((x)&0xFFFF)<<0x10)
+
+
+#endif /* __MCF5475_GPT_H__ */
--- a/tos/fpga_test/include/MCF5475_I2C.h
+++ b/tos/fpga_test/include/MCF5475_I2C.h
@@ -0,0 +1,69 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_I2C_H__
+#define __MCF5475_I2C_H__
+
+
+/*********************************************************************
+*
+* I2C Module (I2C)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_I2C_I2ADR                        (*(volatile uint8_t *)(&_MBAR[0x8F00]))
+#define MCF_I2C_I2FDR                        (*(volatile uint8_t *)(&_MBAR[0x8F04]))
+#define MCF_I2C_I2CR                         (*(volatile uint8_t *)(&_MBAR[0x8F08]))
+#define MCF_I2C_I2SR                         (*(volatile uint8_t *)(&_MBAR[0x8F0C]))
+#define MCF_I2C_I2DR                         (*(volatile uint8_t *)(&_MBAR[0x8F10]))
+#define MCF_I2C_I2ICR                        (*(volatile uint8_t *)(&_MBAR[0x8F20]))
+
+
+
+/* Bit definitions and macros for MCF_I2C_I2ADR */
+#define MCF_I2C_I2ADR_ADR(x)                 (((x)&0x7F)<<0x1)
+
+/* Bit definitions and macros for MCF_I2C_I2FDR */
+#define MCF_I2C_I2FDR_IC(x)                  (((x)&0x3F)<<0)
+
+/* Bit definitions and macros for MCF_I2C_I2CR */
+#define MCF_I2C_I2CR_RSTA                    (0x4)
+#define MCF_I2C_I2CR_TXAK                    (0x8)
+#define MCF_I2C_I2CR_MTX                     (0x10)
+#define MCF_I2C_I2CR_MSTA                    (0x20)
+#define MCF_I2C_I2CR_IIEN                    (0x40)
+#define MCF_I2C_I2CR_IEN                     (0x80)
+
+/* Bit definitions and macros for MCF_I2C_I2SR */
+#define MCF_I2C_I2SR_RXAK                    (0x1)
+#define MCF_I2C_I2SR_IIF                     (0x2)
+#define MCF_I2C_I2SR_SRW                     (0x4)
+#define MCF_I2C_I2SR_IAL                     (0x10)
+#define MCF_I2C_I2SR_IBB                     (0x20)
+#define MCF_I2C_I2SR_IAAS                    (0x40)
+#define MCF_I2C_I2SR_ICF                     (0x80)
+
+/* Bit definitions and macros for MCF_I2C_I2DR */
+#define MCF_I2C_I2DR_DATA(x)                 (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_I2C_I2ICR */
+#define MCF_I2C_I2ICR_IE                     (0x1)
+#define MCF_I2C_I2ICR_RE                     (0x2)
+#define MCF_I2C_I2ICR_TE                     (0x4)
+#define MCF_I2C_I2ICR_BNBE                   (0x8)
+
+
+#endif /* __MCF5475_I2C_H__ */
--- a/tos/fpga_test/include/MCF5475_INTC.h
+++ b/tos/fpga_test/include/MCF5475_INTC.h
@@ -0,0 +1,331 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_INTC_H__
+#define __MCF5475_INTC_H__
+
+
+/*********************************************************************
+*
+* Interrupt Controller (INTC)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_INTC_IPRH                        (*(volatile uint32_t*)(&_MBAR[0x700]))
+#define MCF_INTC_IPRL                        (*(volatile uint32_t*)(&_MBAR[0x704]))
+#define MCF_INTC_IMRH                        (*(volatile uint32_t*)(&_MBAR[0x708]))
+#define MCF_INTC_IMRL                        (*(volatile uint32_t*)(&_MBAR[0x70C]))
+#define MCF_INTC_INTFRCH                     (*(volatile uint32_t*)(&_MBAR[0x710]))
+#define MCF_INTC_INTFRCL                     (*(volatile uint32_t*)(&_MBAR[0x714]))
+#define MCF_INTC_IRLR                        (*(volatile uint8_t *)(&_MBAR[0x718]))
+#define MCF_INTC_IACKLPR                     (*(volatile uint8_t *)(&_MBAR[0x719]))
+#define MCF_INTC_ICR01                       (*(volatile uint8_t *)(&_MBAR[0x741]))
+#define MCF_INTC_ICR02                       (*(volatile uint8_t *)(&_MBAR[0x742]))
+#define MCF_INTC_ICR03                       (*(volatile uint8_t *)(&_MBAR[0x743]))
+#define MCF_INTC_ICR04                       (*(volatile uint8_t *)(&_MBAR[0x744]))
+#define MCF_INTC_ICR05                       (*(volatile uint8_t *)(&_MBAR[0x745]))
+#define MCF_INTC_ICR06                       (*(volatile uint8_t *)(&_MBAR[0x746]))
+#define MCF_INTC_ICR07                       (*(volatile uint8_t *)(&_MBAR[0x747]))
+#define MCF_INTC_ICR08                       (*(volatile uint8_t *)(&_MBAR[0x748]))
+#define MCF_INTC_ICR09                       (*(volatile uint8_t *)(&_MBAR[0x749]))
+#define MCF_INTC_ICR10                       (*(volatile uint8_t *)(&_MBAR[0x74A]))
+#define MCF_INTC_ICR11                       (*(volatile uint8_t *)(&_MBAR[0x74B]))
+#define MCF_INTC_ICR12                       (*(volatile uint8_t *)(&_MBAR[0x74C]))
+#define MCF_INTC_ICR13                       (*(volatile uint8_t *)(&_MBAR[0x74D]))
+#define MCF_INTC_ICR14                       (*(volatile uint8_t *)(&_MBAR[0x74E]))
+#define MCF_INTC_ICR15                       (*(volatile uint8_t *)(&_MBAR[0x74F]))
+#define MCF_INTC_ICR16                       (*(volatile uint8_t *)(&_MBAR[0x750]))
+#define MCF_INTC_ICR17                       (*(volatile uint8_t *)(&_MBAR[0x751]))
+#define MCF_INTC_ICR18                       (*(volatile uint8_t *)(&_MBAR[0x752]))
+#define MCF_INTC_ICR19                       (*(volatile uint8_t *)(&_MBAR[0x753]))
+#define MCF_INTC_ICR20                       (*(volatile uint8_t *)(&_MBAR[0x754]))
+#define MCF_INTC_ICR21                       (*(volatile uint8_t *)(&_MBAR[0x755]))
+#define MCF_INTC_ICR22                       (*(volatile uint8_t *)(&_MBAR[0x756]))
+#define MCF_INTC_ICR23                       (*(volatile uint8_t *)(&_MBAR[0x757]))
+#define MCF_INTC_ICR24                       (*(volatile uint8_t *)(&_MBAR[0x758]))
+#define MCF_INTC_ICR25                       (*(volatile uint8_t *)(&_MBAR[0x759]))
+#define MCF_INTC_ICR26                       (*(volatile uint8_t *)(&_MBAR[0x75A]))
+#define MCF_INTC_ICR27                       (*(volatile uint8_t *)(&_MBAR[0x75B]))
+#define MCF_INTC_ICR28                       (*(volatile uint8_t *)(&_MBAR[0x75C]))
+#define MCF_INTC_ICR29                       (*(volatile uint8_t *)(&_MBAR[0x75D]))
+#define MCF_INTC_ICR30                       (*(volatile uint8_t *)(&_MBAR[0x75E]))
+#define MCF_INTC_ICR31                       (*(volatile uint8_t *)(&_MBAR[0x75F]))
+#define MCF_INTC_ICR32                       (*(volatile uint8_t *)(&_MBAR[0x760]))
+#define MCF_INTC_ICR33                       (*(volatile uint8_t *)(&_MBAR[0x761]))
+#define MCF_INTC_ICR34                       (*(volatile uint8_t *)(&_MBAR[0x762]))
+#define MCF_INTC_ICR35                       (*(volatile uint8_t *)(&_MBAR[0x763]))
+#define MCF_INTC_ICR36                       (*(volatile uint8_t *)(&_MBAR[0x764]))
+#define MCF_INTC_ICR37                       (*(volatile uint8_t *)(&_MBAR[0x765]))
+#define MCF_INTC_ICR38                       (*(volatile uint8_t *)(&_MBAR[0x766]))
+#define MCF_INTC_ICR39                       (*(volatile uint8_t *)(&_MBAR[0x767]))
+#define MCF_INTC_ICR40                       (*(volatile uint8_t *)(&_MBAR[0x768]))
+#define MCF_INTC_ICR41                       (*(volatile uint8_t *)(&_MBAR[0x769]))
+#define MCF_INTC_ICR42                       (*(volatile uint8_t *)(&_MBAR[0x76A]))
+#define MCF_INTC_ICR43                       (*(volatile uint8_t *)(&_MBAR[0x76B]))
+#define MCF_INTC_ICR44                       (*(volatile uint8_t *)(&_MBAR[0x76C]))
+#define MCF_INTC_ICR45                       (*(volatile uint8_t *)(&_MBAR[0x76D]))
+#define MCF_INTC_ICR46                       (*(volatile uint8_t *)(&_MBAR[0x76E]))
+#define MCF_INTC_ICR47                       (*(volatile uint8_t *)(&_MBAR[0x76F]))
+#define MCF_INTC_ICR48                       (*(volatile uint8_t *)(&_MBAR[0x770]))
+#define MCF_INTC_ICR49                       (*(volatile uint8_t *)(&_MBAR[0x771]))
+#define MCF_INTC_ICR50                       (*(volatile uint8_t *)(&_MBAR[0x772]))
+#define MCF_INTC_ICR51                       (*(volatile uint8_t *)(&_MBAR[0x773]))
+#define MCF_INTC_ICR52                       (*(volatile uint8_t *)(&_MBAR[0x774]))
+#define MCF_INTC_ICR53                       (*(volatile uint8_t *)(&_MBAR[0x775]))
+#define MCF_INTC_ICR54                       (*(volatile uint8_t *)(&_MBAR[0x776]))
+#define MCF_INTC_ICR55                       (*(volatile uint8_t *)(&_MBAR[0x777]))
+#define MCF_INTC_ICR56                       (*(volatile uint8_t *)(&_MBAR[0x778]))
+#define MCF_INTC_ICR57                       (*(volatile uint8_t *)(&_MBAR[0x779]))
+#define MCF_INTC_ICR58                       (*(volatile uint8_t *)(&_MBAR[0x77A]))
+#define MCF_INTC_ICR59                       (*(volatile uint8_t *)(&_MBAR[0x77B]))
+#define MCF_INTC_ICR60                       (*(volatile uint8_t *)(&_MBAR[0x77C]))
+#define MCF_INTC_ICR61                       (*(volatile uint8_t *)(&_MBAR[0x77D]))
+#define MCF_INTC_ICR62                       (*(volatile uint8_t *)(&_MBAR[0x77E]))
+#define MCF_INTC_ICR63                       (*(volatile uint8_t *)(&_MBAR[0x77F]))
+#define MCF_INTC_SWIACK                      (*(volatile uint8_t *)(&_MBAR[0x7E0]))
+#define MCF_INTC_L1IACK                      (*(volatile uint8_t *)(&_MBAR[0x7E4]))
+#define MCF_INTC_L2IACK                      (*(volatile uint8_t *)(&_MBAR[0x7E8]))
+#define MCF_INTC_L3IACK                      (*(volatile uint8_t *)(&_MBAR[0x7EC]))
+#define MCF_INTC_L4IACK                      (*(volatile uint8_t *)(&_MBAR[0x7F0]))
+#define MCF_INTC_L5IACK                      (*(volatile uint8_t *)(&_MBAR[0x7F4]))
+#define MCF_INTC_L6IACK                      (*(volatile uint8_t *)(&_MBAR[0x7F8]))
+#define MCF_INTC_L7IACK                      (*(volatile uint8_t *)(&_MBAR[0x7FC]))
+#define MCF_INTC_ICR(x)                      (*(volatile uint8_t *)(&_MBAR[0x741 + ((x-1)*0x1)]))
+#define MCF_INTC_LIACK(x)                    (*(volatile uint8_t *)(&_MBAR[0x7E4 + ((x-1)*0x4)]))
+
+
+
+/* Bit definitions and macros for MCF_INTC_IPRH */
+#define MCF_INTC_IPRH_INT32                  (0x1)
+#define MCF_INTC_IPRH_INT33                  (0x2)
+#define MCF_INTC_IPRH_INT34                  (0x4)
+#define MCF_INTC_IPRH_INT35                  (0x8)
+#define MCF_INTC_IPRH_INT36                  (0x10)
+#define MCF_INTC_IPRH_INT37                  (0x20)
+#define MCF_INTC_IPRH_INT38                  (0x40)
+#define MCF_INTC_IPRH_INT39                  (0x80)
+#define MCF_INTC_IPRH_INT40                  (0x100)
+#define MCF_INTC_IPRH_INT41                  (0x200)
+#define MCF_INTC_IPRH_INT42                  (0x400)
+#define MCF_INTC_IPRH_INT43                  (0x800)
+#define MCF_INTC_IPRH_INT44                  (0x1000)
+#define MCF_INTC_IPRH_INT45                  (0x2000)
+#define MCF_INTC_IPRH_INT46                  (0x4000)
+#define MCF_INTC_IPRH_INT47                  (0x8000)
+#define MCF_INTC_IPRH_INT48                  (0x10000)
+#define MCF_INTC_IPRH_INT49                  (0x20000)
+#define MCF_INTC_IPRH_INT50                  (0x40000)
+#define MCF_INTC_IPRH_INT51                  (0x80000)
+#define MCF_INTC_IPRH_INT52                  (0x100000)
+#define MCF_INTC_IPRH_INT53                  (0x200000)
+#define MCF_INTC_IPRH_INT54                  (0x400000)
+#define MCF_INTC_IPRH_INT55                  (0x800000)
+#define MCF_INTC_IPRH_INT56                  (0x1000000)
+#define MCF_INTC_IPRH_INT57                  (0x2000000)
+#define MCF_INTC_IPRH_INT58                  (0x4000000)
+#define MCF_INTC_IPRH_INT59                  (0x8000000)
+#define MCF_INTC_IPRH_INT60                  (0x10000000)
+#define MCF_INTC_IPRH_INT61                  (0x20000000)
+#define MCF_INTC_IPRH_INT62                  (0x40000000)
+#define MCF_INTC_IPRH_INT63                  (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC_IPRL */
+#define MCF_INTC_IPRL_INT1                   (0x2)
+#define MCF_INTC_IPRL_INT2                   (0x4)
+#define MCF_INTC_IPRL_INT3                   (0x8)
+#define MCF_INTC_IPRL_INT4                   (0x10)
+#define MCF_INTC_IPRL_INT5                   (0x20)
+#define MCF_INTC_IPRL_INT6                   (0x40)
+#define MCF_INTC_IPRL_INT7                   (0x80)
+#define MCF_INTC_IPRL_INT8                   (0x100)
+#define MCF_INTC_IPRL_INT9                   (0x200)
+#define MCF_INTC_IPRL_INT10                  (0x400)
+#define MCF_INTC_IPRL_INT11                  (0x800)
+#define MCF_INTC_IPRL_INT12                  (0x1000)
+#define MCF_INTC_IPRL_INT13                  (0x2000)
+#define MCF_INTC_IPRL_INT14                  (0x4000)
+#define MCF_INTC_IPRL_INT15                  (0x8000)
+#define MCF_INTC_IPRL_INT16                  (0x10000)
+#define MCF_INTC_IPRL_INT17                  (0x20000)
+#define MCF_INTC_IPRL_INT18                  (0x40000)
+#define MCF_INTC_IPRL_INT19                  (0x80000)
+#define MCF_INTC_IPRL_INT20                  (0x100000)
+#define MCF_INTC_IPRL_INT21                  (0x200000)
+#define MCF_INTC_IPRL_INT22                  (0x400000)
+#define MCF_INTC_IPRL_INT23                  (0x800000)
+#define MCF_INTC_IPRL_INT24                  (0x1000000)
+#define MCF_INTC_IPRL_INT25                  (0x2000000)
+#define MCF_INTC_IPRL_INT26                  (0x4000000)
+#define MCF_INTC_IPRL_INT27                  (0x8000000)
+#define MCF_INTC_IPRL_INT28                  (0x10000000)
+#define MCF_INTC_IPRL_INT29                  (0x20000000)
+#define MCF_INTC_IPRL_INT30                  (0x40000000)
+#define MCF_INTC_IPRL_INT31                  (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC_IMRH */
+#define MCF_INTC_IMRH_INT_MASK32             (0x1)
+#define MCF_INTC_IMRH_INT_MASK33             (0x2)
+#define MCF_INTC_IMRH_INT_MASK34             (0x4)
+#define MCF_INTC_IMRH_INT_MASK35             (0x8)
+#define MCF_INTC_IMRH_INT_MASK36             (0x10)
+#define MCF_INTC_IMRH_INT_MASK37             (0x20)
+#define MCF_INTC_IMRH_INT_MASK38             (0x40)
+#define MCF_INTC_IMRH_INT_MASK39             (0x80)
+#define MCF_INTC_IMRH_INT_MASK40             (0x100)
+#define MCF_INTC_IMRH_INT_MASK41             (0x200)
+#define MCF_INTC_IMRH_INT_MASK42             (0x400)
+#define MCF_INTC_IMRH_INT_MASK43             (0x800)
+#define MCF_INTC_IMRH_INT_MASK44             (0x1000)
+#define MCF_INTC_IMRH_INT_MASK45             (0x2000)
+#define MCF_INTC_IMRH_INT_MASK46             (0x4000)
+#define MCF_INTC_IMRH_INT_MASK47             (0x8000)
+#define MCF_INTC_IMRH_INT_MASK48             (0x10000)
+#define MCF_INTC_IMRH_INT_MASK49             (0x20000)
+#define MCF_INTC_IMRH_INT_MASK50             (0x40000)
+#define MCF_INTC_IMRH_INT_MASK51             (0x80000)
+#define MCF_INTC_IMRH_INT_MASK52             (0x100000)
+#define MCF_INTC_IMRH_INT_MASK53             (0x200000)
+#define MCF_INTC_IMRH_INT_MASK54             (0x400000)
+#define MCF_INTC_IMRH_INT_MASK55             (0x800000)
+#define MCF_INTC_IMRH_INT_MASK56             (0x1000000)
+#define MCF_INTC_IMRH_INT_MASK57             (0x2000000)
+#define MCF_INTC_IMRH_INT_MASK58             (0x4000000)
+#define MCF_INTC_IMRH_INT_MASK59             (0x8000000)
+#define MCF_INTC_IMRH_INT_MASK60             (0x10000000)
+#define MCF_INTC_IMRH_INT_MASK61             (0x20000000)
+#define MCF_INTC_IMRH_INT_MASK62             (0x40000000)
+#define MCF_INTC_IMRH_INT_MASK63             (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC_IMRL */
+#define MCF_INTC_IMRL_MASKALL                (0x1)
+#define MCF_INTC_IMRL_INT_MASK1              (0x2)
+#define MCF_INTC_IMRL_INT_MASK2              (0x4)
+#define MCF_INTC_IMRL_INT_MASK3              (0x8)
+#define MCF_INTC_IMRL_INT_MASK4              (0x10)
+#define MCF_INTC_IMRL_INT_MASK5              (0x20)
+#define MCF_INTC_IMRL_INT_MASK6              (0x40)
+#define MCF_INTC_IMRL_INT_MASK7              (0x80)
+#define MCF_INTC_IMRL_INT_MASK8              (0x100)
+#define MCF_INTC_IMRL_INT_MASK9              (0x200)
+#define MCF_INTC_IMRL_INT_MASK10             (0x400)
+#define MCF_INTC_IMRL_INT_MASK11             (0x800)
+#define MCF_INTC_IMRL_INT_MASK12             (0x1000)
+#define MCF_INTC_IMRL_INT_MASK13             (0x2000)
+#define MCF_INTC_IMRL_INT_MASK14             (0x4000)
+#define MCF_INTC_IMRL_INT_MASK15             (0x8000)
+#define MCF_INTC_IMRL_INT_MASK16             (0x10000)
+#define MCF_INTC_IMRL_INT_MASK17             (0x20000)
+#define MCF_INTC_IMRL_INT_MASK18             (0x40000)
+#define MCF_INTC_IMRL_INT_MASK19             (0x80000)
+#define MCF_INTC_IMRL_INT_MASK20             (0x100000)
+#define MCF_INTC_IMRL_INT_MASK21             (0x200000)
+#define MCF_INTC_IMRL_INT_MASK22             (0x400000)
+#define MCF_INTC_IMRL_INT_MASK23             (0x800000)
+#define MCF_INTC_IMRL_INT_MASK24             (0x1000000)
+#define MCF_INTC_IMRL_INT_MASK25             (0x2000000)
+#define MCF_INTC_IMRL_INT_MASK26             (0x4000000)
+#define MCF_INTC_IMRL_INT_MASK27             (0x8000000)
+#define MCF_INTC_IMRL_INT_MASK28             (0x10000000)
+#define MCF_INTC_IMRL_INT_MASK29             (0x20000000)
+#define MCF_INTC_IMRL_INT_MASK30             (0x40000000)
+#define MCF_INTC_IMRL_INT_MASK31             (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC_INTFRCH */
+#define MCF_INTC_INTFRCH_INTFRC32            (0x1)
+#define MCF_INTC_INTFRCH_INTFRC33            (0x2)
+#define MCF_INTC_INTFRCH_INTFRC34            (0x4)
+#define MCF_INTC_INTFRCH_INTFRC35            (0x8)
+#define MCF_INTC_INTFRCH_INTFRC36            (0x10)
+#define MCF_INTC_INTFRCH_INTFRC37            (0x20)
+#define MCF_INTC_INTFRCH_INTFRC38            (0x40)
+#define MCF_INTC_INTFRCH_INTFRC39            (0x80)
+#define MCF_INTC_INTFRCH_INTFRC40            (0x100)
+#define MCF_INTC_INTFRCH_INTFRC41            (0x200)
+#define MCF_INTC_INTFRCH_INTFRC42            (0x400)
+#define MCF_INTC_INTFRCH_INTFRC43            (0x800)
+#define MCF_INTC_INTFRCH_INTFRC44            (0x1000)
+#define MCF_INTC_INTFRCH_INTFRC45            (0x2000)
+#define MCF_INTC_INTFRCH_INTFRC46            (0x4000)
+#define MCF_INTC_INTFRCH_INTFRC47            (0x8000)
+#define MCF_INTC_INTFRCH_INTFRC48            (0x10000)
+#define MCF_INTC_INTFRCH_INTFRC49            (0x20000)
+#define MCF_INTC_INTFRCH_INTFRC50            (0x40000)
+#define MCF_INTC_INTFRCH_INTFRC51            (0x80000)
+#define MCF_INTC_INTFRCH_INTFRC52            (0x100000)
+#define MCF_INTC_INTFRCH_INTFRC53            (0x200000)
+#define MCF_INTC_INTFRCH_INTFRC54            (0x400000)
+#define MCF_INTC_INTFRCH_INTFRC55            (0x800000)
+#define MCF_INTC_INTFRCH_INTFRC56            (0x1000000)
+#define MCF_INTC_INTFRCH_INTFRC57            (0x2000000)
+#define MCF_INTC_INTFRCH_INTFRC58            (0x4000000)
+#define MCF_INTC_INTFRCH_INTFRC59            (0x8000000)
+#define MCF_INTC_INTFRCH_INTFRC60            (0x10000000)
+#define MCF_INTC_INTFRCH_INTFRC61            (0x20000000)
+#define MCF_INTC_INTFRCH_INTFRC62            (0x40000000)
+#define MCF_INTC_INTFRCH_INTFRC63            (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC_INTFRCL */
+#define MCF_INTC_INTFRCL_INTFRC1             (0x2)
+#define MCF_INTC_INTFRCL_INTFRC2             (0x4)
+#define MCF_INTC_INTFRCL_INTFRC3             (0x8)
+#define MCF_INTC_INTFRCL_INTFRC4             (0x10)
+#define MCF_INTC_INTFRCL_INTFRC5             (0x20)
+#define MCF_INTC_INTFRCL_INTFRC6             (0x40)
+#define MCF_INTC_INTFRCL_INTFRC7             (0x80)
+#define MCF_INTC_INTFRCL_INTFRC8             (0x100)
+#define MCF_INTC_INTFRCL_INTFRC9             (0x200)
+#define MCF_INTC_INTFRCL_INTFRC10            (0x400)
+#define MCF_INTC_INTFRCL_INTFRC11            (0x800)
+#define MCF_INTC_INTFRCL_INTFRC12            (0x1000)
+#define MCF_INTC_INTFRCL_INTFRC13            (0x2000)
+#define MCF_INTC_INTFRCL_INTFRC14            (0x4000)
+#define MCF_INTC_INTFRCL_INTFRC15            (0x8000)
+#define MCF_INTC_INTFRCL_INTFRC16            (0x10000)
+#define MCF_INTC_INTFRCL_INTFRC17            (0x20000)
+#define MCF_INTC_INTFRCL_INTFRC18            (0x40000)
+#define MCF_INTC_INTFRCL_INTFRC19            (0x80000)
+#define MCF_INTC_INTFRCL_INTFRC20            (0x100000)
+#define MCF_INTC_INTFRCL_INTFRC21            (0x200000)
+#define MCF_INTC_INTFRCL_INTFRC22            (0x400000)
+#define MCF_INTC_INTFRCL_INTFRC23            (0x800000)
+#define MCF_INTC_INTFRCL_INTFRC24            (0x1000000)
+#define MCF_INTC_INTFRCL_INTFRC25            (0x2000000)
+#define MCF_INTC_INTFRCL_INTFRC26            (0x4000000)
+#define MCF_INTC_INTFRCL_INTFRC27            (0x8000000)
+#define MCF_INTC_INTFRCL_INTFRC28            (0x10000000)
+#define MCF_INTC_INTFRCL_INTFRC29            (0x20000000)
+#define MCF_INTC_INTFRCL_INTFRC30            (0x40000000)
+#define MCF_INTC_INTFRCL_INTFRC31            (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC_IRLR */
+#define MCF_INTC_IRLR_IRQ(x)                 (((x)&0x7F)<<0x1)
+
+/* Bit definitions and macros for MCF_INTC_IACKLPR */
+#define MCF_INTC_IACKLPR_PRI(x)              (((x)&0xF)<<0)
+#define MCF_INTC_IACKLPR_LEVEL(x)            (((x)&0x7)<<0x4)
+
+/* Bit definitions and macros for MCF_INTC_ICR */
+#define MCF_INTC_ICR_IP(x)                   (((x)&0x7)<<0)
+#define MCF_INTC_ICR_IL(x)                   (((x)&0x7)<<0x3)
+
+/* Bit definitions and macros for MCF_INTC_SWIACK */
+#define MCF_INTC_SWIACK_VECTOR(x)            (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_INTC_LIACK */
+#define MCF_INTC_LIACK_VECTOR(x)             (((x)&0xFF)<<0)
+
+
+#endif /* __MCF5475_INTC_H__ */
--- a/tos/fpga_test/include/MCF5475_MMU.h
+++ b/tos/fpga_test/include/MCF5475_MMU.h
@@ -0,0 +1,79 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_MMU_H__
+#define __MCF5475_MMU_H__
+
+
+/*********************************************************************
+*
+* Memory Management Unit (MMU)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+
+/* note the uint32_t_a - this is to avoid gcc warnings about pointer aliasing */
+#define MCF_MMU_MMUCR                        (*(volatile uint32_t_a*)(&_MMUBAR[0]))
+#define MCF_MMU_MMUOR                        (*(volatile uint32_t_a*)(&_MMUBAR[0x4]))
+#define MCF_MMU_MMUSR                        (*(volatile uint32_t_a*)(&_MMUBAR[0x8]))
+#define MCF_MMU_MMUAR                        (*(volatile uint32_t_a*)(&_MMUBAR[0x10]))
+#define MCF_MMU_MMUTR                        (*(volatile uint32_t_a*)(&_MMUBAR[0x14]))
+#define MCF_MMU_MMUDR                        (*(volatile uint32_t_a*)(&_MMUBAR[0x18]))
+
+
+/* Bit definitions and macros for MCF_MMU_MMUCR */
+#define MCF_MMU_MMUCR_EN                     (0x1)
+#define MCF_MMU_MMUCR_ASM                    (0x2)
+
+/* Bit definitions and macros for MCF_MMU_MMUOR */
+#define MCF_MMU_MMUOR_UAA                    (0x1)
+#define MCF_MMU_MMUOR_ACC                    (0x2)
+#define MCF_MMU_MMUOR_RW                     (0x4)
+#define MCF_MMU_MMUOR_ADR                    (0x8)
+#define MCF_MMU_MMUOR_ITLB                   (0x10)
+#define MCF_MMU_MMUOR_CAS                    (0x20)
+#define MCF_MMU_MMUOR_CNL                    (0x40)
+#define MCF_MMU_MMUOR_CA                     (0x80)
+#define MCF_MMU_MMUOR_STLB                   (0x100)
+#define MCF_MMU_MMUOR_AA(x)                  (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_MMU_MMUSR */
+#define MCF_MMU_MMUSR_HIT                    (0x2)
+#define MCF_MMU_MMUSR_WF                     (0x8)
+#define MCF_MMU_MMUSR_RF                     (0x10)
+#define MCF_MMU_MMUSR_SPF                    (0x20)
+
+/* Bit definitions and macros for MCF_MMU_MMUAR */
+#define MCF_MMU_MMUAR_FA(x)                  (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_MMU_MMUTR */
+#define MCF_MMU_MMUTR_V                      (0x1)
+#define MCF_MMU_MMUTR_SG                     (0x2)
+#define MCF_MMU_MMUTR_ID(x)                  (((x)&0xFF)<<0x2)
+#define MCF_MMU_MMUTR_VA(x)                  (((x)&0x3FFFFF)<<0xA)
+
+/* Bit definitions and macros for MCF_MMU_MMUDR */
+#define MCF_MMU_MMUDR_LK                     (0x2)
+#define MCF_MMU_MMUDR_X                      (0x4)
+#define MCF_MMU_MMUDR_W                      (0x8)
+#define MCF_MMU_MMUDR_R                      (0x10)
+#define MCF_MMU_MMUDR_SP                     (0x20)
+#define MCF_MMU_MMUDR_CM(x)                  (((x)&0x3)<<0x6)
+#define MCF_MMU_MMUDR_SZ(x)                  (((x)&0x3)<<0x8)
+#define MCF_MMU_MMUDR_PA(x)                  (((x)&0x3FFFFF)<<0xA)
+
+
+#endif /* __MCF5475_MMU_H__ */
--- a/tos/fpga_test/include/MCF5475_PAD.h
+++ b/tos/fpga_test/include/MCF5475_PAD.h
@@ -0,0 +1,233 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_PAD_H__
+#define __MCF5475_PAD_H__
+
+
+/*********************************************************************
+*
+* Common GPIO
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_PAD_PAR_FBCTL                    (*(volatile uint16_t*)(&_MBAR[0xA40]))
+#define MCF_PAD_PAR_FBCS                     (*(volatile uint8_t *)(&_MBAR[0xA42]))
+#define MCF_PAD_PAR_DMA                      (*(volatile uint8_t *)(&_MBAR[0xA43]))
+#define MCF_PAD_PAR_FECI2CIRQ                (*(volatile uint16_t*)(&_MBAR[0xA44]))
+#define MCF_PAD_PAR_PCIBG                    (*(volatile uint16_t*)(&_MBAR[0xA48]))
+#define MCF_PAD_PAR_PCIBR                    (*(volatile uint16_t*)(&_MBAR[0xA4A]))
+#define MCF_PAD_PAR_PSC3                     (*(volatile uint8_t *)(&_MBAR[0xA4C]))
+#define MCF_PAD_PAR_PSC2                     (*(volatile uint8_t *)(&_MBAR[0xA4D]))
+#define MCF_PAD_PAR_PSC1                     (*(volatile uint8_t *)(&_MBAR[0xA4E]))
+#define MCF_PAD_PAR_PSC0                     (*(volatile uint8_t *)(&_MBAR[0xA4F]))
+#define MCF_PAD_PAR_DSPI                     (*(volatile uint16_t*)(&_MBAR[0xA50]))
+#define MCF_PAD_PAR_TIMER                    (*(volatile uint8_t *)(&_MBAR[0xA52]))
+
+
+/* Bit definitions and macros for MCF_PAD_PAR_FBCTL */
+#define MCF_PAD_PAR_FBCTL_PAR_ALE(x)         (((x)&0x3)<<0)
+#define MCF_PAD_PAR_FBCTL_PAR_ALE_GPIO       (0)
+#define MCF_PAD_PAR_FBCTL_PAR_ALE_TBST       (0x2)
+#define MCF_PAD_PAR_FBCTL_PAR_ALE_ALE        (0x3)
+#define MCF_PAD_PAR_FBCTL_PAR_TA             (0x4)
+#define MCF_PAD_PAR_FBCTL_PAR_RWB(x)         (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_FBCTL_PAR_RWB_GPIO       (0)
+#define MCF_PAD_PAR_FBCTL_PAR_RWB_TBST       (0x20)
+#define MCF_PAD_PAR_FBCTL_PAR_RWB_RW         (0x30)
+#define MCF_PAD_PAR_FBCTL_PAR_OE             (0x40)
+#define MCF_PAD_PAR_FBCTL_PAR_BWE0           (0x100)
+#define MCF_PAD_PAR_FBCTL_PAR_BWE1           (0x400)
+#define MCF_PAD_PAR_FBCTL_PAR_BWE2           (0x1000)
+#define MCF_PAD_PAR_FBCTL_PAR_BWE3           (0x4000)
+
+/* Bit definitions and macros for MCF_PAD_PAR_FBCS */
+#define MCF_PAD_PAR_FBCS_PAR_CS1             (0x2)
+#define MCF_PAD_PAR_FBCS_PAR_CS2             (0x4)
+#define MCF_PAD_PAR_FBCS_PAR_CS3             (0x8)
+#define MCF_PAD_PAR_FBCS_PAR_CS4             (0x10)
+#define MCF_PAD_PAR_FBCS_PAR_CS5             (0x20)
+
+/* Bit definitions and macros for MCF_PAD_PAR_DMA */
+#define MCF_PAD_PAR_DMA_PAR_DREQ0(x)         (((x)&0x3)<<0)
+#define MCF_PAD_PAR_DMA_PAR_DREQ0_GPIO       (0)
+#define MCF_PAD_PAR_DMA_PAR_DREQ0_TIN0       (0x2)
+#define MCF_PAD_PAR_DMA_PAR_DREQ0_DREQ0      (0x3)
+#define MCF_PAD_PAR_DMA_PAR_DREQ1(x)         (((x)&0x3)<<0x2)
+#define MCF_PAD_PAR_DMA_PAR_DREQ1_GPIO       (0)
+#define MCF_PAD_PAR_DMA_PAR_DREQ1_IRQ1       (0x4)
+#define MCF_PAD_PAR_DMA_PAR_DREQ1_TIN1       (0x8)
+#define MCF_PAD_PAR_DMA_PAR_DREQ1_DREQ1      (0xC)
+#define MCF_PAD_PAR_DMA_PAR_DACK0(x)         (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_DMA_PAR_DACK0_GPIO       (0)
+#define MCF_PAD_PAR_DMA_PAR_DACK0_TOUT0      (0x20)
+#define MCF_PAD_PAR_DMA_PAR_DACK0_DACK0      (0x30)
+#define MCF_PAD_PAR_DMA_PAR_DACK1(x)         (((x)&0x3)<<0x6)
+#define MCF_PAD_PAR_DMA_PAR_DACK1_GPIO       (0)
+#define MCF_PAD_PAR_DMA_PAR_DACK1_TOUT1      (0x80)
+#define MCF_PAD_PAR_DMA_PAR_DACK1_DACK1      (0xC0)
+
+/* Bit definitions and macros for MCF_PAD_PAR_FECI2CIRQ */
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_IRQ5       (0x1)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_IRQ6       (0x2)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_SCL        (0x4)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_SDA        (0x8)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDC(x)   (((x)&0x3)<<0x6)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDC_SCL  (0x80)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDC_E1MDC (0xC0)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDIO(x)  (((x)&0x3)<<0x8)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDIO_SDA (0x200)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDIO_E1MDIO (0x300)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MII      (0x400)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E17        (0x800)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E0MDC      (0x1000)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E0MDIO     (0x2000)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E0MII      (0x4000)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E07        (0x8000)
+
+/* Bit definitions and macros for MCF_PAD_PAR_PCIBG */
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0(x)      (((x)&0x3)<<0)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0_GPIO    (0)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0_TOUT0   (0x2)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0_PCIBG0  (0x3)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1(x)      (((x)&0x3)<<0x2)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1_GPIO    (0)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1_TOUT1   (0x8)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1_PCIBG1  (0xC)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2(x)      (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2_GPIO    (0)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2_TOUT2   (0x20)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2_PCIBG2  (0x30)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3(x)      (((x)&0x3)<<0x6)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3_GPIO    (0)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3_TOUT3   (0x80)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3_PCIBG3  (0xC0)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4(x)      (((x)&0x3)<<0x8)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4_GPIO    (0)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4_TBST    (0x200)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4_PCIBG4  (0x300)
+
+/* Bit definitions and macros for MCF_PAD_PAR_PCIBR */
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0(x)      (((x)&0x3)<<0)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0_GPIO    (0)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0_TIN0    (0x2)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0_PCIBR0  (0x3)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1(x)      (((x)&0x3)<<0x2)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1_GPIO    (0)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1_TIN1    (0x8)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1_PCIBR1  (0xC)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2(x)      (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2_GPIO    (0)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2_TIN2    (0x20)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2_PCIBR2  (0x30)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3(x)      (((x)&0x3)<<0x6)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3_GPIO    (0)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3_TIN3    (0x80)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3_PCIBR3  (0xC0)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4(x)      (((x)&0x3)<<0x8)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4_GPIO    (0)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4_IRQ4    (0x200)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4_PCIBR4  (0x300)
+
+/* Bit definitions and macros for MCF_PAD_PAR_PSC3 */
+#define MCF_PAD_PAR_PSC3_PAR_TXD3            (0x4)
+#define MCF_PAD_PAR_PSC3_PAR_RXD3            (0x8)
+#define MCF_PAD_PAR_PSC3_PAR_RTS3(x)         (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_PSC3_PAR_RTS3_GPIO       (0)
+#define MCF_PAD_PAR_PSC3_PAR_RTS3_FSYNC      (0x20)
+#define MCF_PAD_PAR_PSC3_PAR_RTS3_RTS        (0x30)
+#define MCF_PAD_PAR_PSC3_PAR_CTS3(x)         (((x)&0x3)<<0x6)
+#define MCF_PAD_PAR_PSC3_PAR_CTS3_GPIO       (0)
+#define MCF_PAD_PAR_PSC3_PAR_CTS3_BCLK       (0x80)
+#define MCF_PAD_PAR_PSC3_PAR_CTS3_CTS        (0xC0)
+
+/* Bit definitions and macros for MCF_PAD_PAR_PSC2 */
+#define MCF_PAD_PAR_PSC2_PAR_TXD2            (0x4)
+#define MCF_PAD_PAR_PSC2_PAR_RXD2            (0x8)
+#define MCF_PAD_PAR_PSC2_PAR_RTS2(x)         (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_PSC2_PAR_RTS2_GPIO       (0)
+#define MCF_PAD_PAR_PSC2_PAR_RTS2_FSYNC      (0x20)
+#define MCF_PAD_PAR_PSC2_PAR_RTS2_RTS        (0x30)
+#define MCF_PAD_PAR_PSC2_PAR_CTS2(x)         (((x)&0x3)<<0x6)
+#define MCF_PAD_PAR_PSC2_PAR_CTS2_GPIO       (0)
+#define MCF_PAD_PAR_PSC2_PAR_CTS2_BCLK       (0x80)
+#define MCF_PAD_PAR_PSC2_PAR_CTS2_CTS        (0xC0)
+
+/* Bit definitions and macros for MCF_PAD_PAR_PSC1 */
+#define MCF_PAD_PAR_PSC1_PAR_TXD1            (0x4)
+#define MCF_PAD_PAR_PSC1_PAR_RXD1            (0x8)
+#define MCF_PAD_PAR_PSC1_PAR_RTS1(x)         (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_PSC1_PAR_RTS1_GPIO       (0)
+#define MCF_PAD_PAR_PSC1_PAR_RTS1_FSYNC      (0x20)
+#define MCF_PAD_PAR_PSC1_PAR_RTS1_RTS        (0x30)
+#define MCF_PAD_PAR_PSC1_PAR_CTS1(x)         (((x)&0x3)<<0x6)
+#define MCF_PAD_PAR_PSC1_PAR_CTS1_GPIO       (0)
+#define MCF_PAD_PAR_PSC1_PAR_CTS1_BCLK       (0x80)
+#define MCF_PAD_PAR_PSC1_PAR_CTS1_CTS        (0xC0)
+
+/* Bit definitions and macros for MCF_PAD_PAR_PSC0 */
+#define MCF_PAD_PAR_PSC0_PAR_TXD0            (0x4)
+#define MCF_PAD_PAR_PSC0_PAR_RXD0            (0x8)
+#define MCF_PAD_PAR_PSC0_PAR_RTS0(x)         (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_PSC0_PAR_RTS0_GPIO       (0)
+#define MCF_PAD_PAR_PSC0_PAR_RTS0_FSYNC      (0x20)
+#define MCF_PAD_PAR_PSC0_PAR_RTS0_RTS        (0x30)
+#define MCF_PAD_PAR_PSC0_PAR_CTS0(x)         (((x)&0x3)<<0x6)
+#define MCF_PAD_PAR_PSC0_PAR_CTS0_GPIO       (0)
+#define MCF_PAD_PAR_PSC0_PAR_CTS0_BCLK       (0x80)
+#define MCF_PAD_PAR_PSC0_PAR_CTS0_CTS        (0xC0)
+
+/* Bit definitions and macros for MCF_PAD_PAR_DSPI */
+#define MCF_PAD_PAR_DSPI_PAR_SOUT(x)         (((x)&0x3)<<0)
+#define MCF_PAD_PAR_DSPI_PAR_SOUT_GPIO       (0)
+#define MCF_PAD_PAR_DSPI_PAR_SOUT_TXD        (0x2)
+#define MCF_PAD_PAR_DSPI_PAR_SOUT_SOUT       (0x3)
+#define MCF_PAD_PAR_DSPI_PAR_SIN(x)          (((x)&0x3)<<0x2)
+#define MCF_PAD_PAR_DSPI_PAR_SIN_GPIO        (0)
+#define MCF_PAD_PAR_DSPI_PAR_SIN_RXD         (0x8)
+#define MCF_PAD_PAR_DSPI_PAR_SIN_SIN         (0xC)
+#define MCF_PAD_PAR_DSPI_PAR_SCK(x)          (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_DSPI_PAR_SCK_GPIO        (0)
+#define MCF_PAD_PAR_DSPI_PAR_SCK_BCLK        (0x10)
+#define MCF_PAD_PAR_DSPI_PAR_SCK_CTS         (0x20)
+#define MCF_PAD_PAR_DSPI_PAR_SCK_SCK         (0x30)
+#define MCF_PAD_PAR_DSPI_PAR_CS0(x)          (((x)&0x3)<<0x6)
+#define MCF_PAD_PAR_DSPI_PAR_CS0_GPIO        (0)
+#define MCF_PAD_PAR_DSPI_PAR_CS0_FSYNC       (0x40)
+#define MCF_PAD_PAR_DSPI_PAR_CS0_RTS         (0x80)
+#define MCF_PAD_PAR_DSPI_PAR_CS0_DSPICS0     (0xC0)
+#define MCF_PAD_PAR_DSPI_PAR_CS2(x)          (((x)&0x3)<<0x8)
+#define MCF_PAD_PAR_DSPI_PAR_CS2_GPIO        (0)
+#define MCF_PAD_PAR_DSPI_PAR_CS2_TOUT2       (0x200)
+#define MCF_PAD_PAR_DSPI_PAR_CS2_DSPICS2     (0x300)
+#define MCF_PAD_PAR_DSPI_PAR_CS3(x)          (((x)&0x3)<<0xA)
+#define MCF_PAD_PAR_DSPI_PAR_CS3_GPIO        (0)
+#define MCF_PAD_PAR_DSPI_PAR_CS3_TOUT3       (0x800)
+#define MCF_PAD_PAR_DSPI_PAR_CS3_DSPICS3     (0xC00)
+#define MCF_PAD_PAR_DSPI_PAR_CS5             (0x1000)
+
+/* Bit definitions and macros for MCF_PAD_PAR_TIMER */
+#define MCF_PAD_PAR_TIMER_PAR_TOUT2          (0x1)
+#define MCF_PAD_PAR_TIMER_PAR_TIN2(x)        (((x)&0x3)<<0x1)
+#define MCF_PAD_PAR_TIMER_PAR_TIN2_IRQ2      (0x4)
+#define MCF_PAD_PAR_TIMER_PAR_TIN2_TIN2      (0x6)
+#define MCF_PAD_PAR_TIMER_PAR_TOUT3          (0x8)
+#define MCF_PAD_PAR_TIMER_PAR_TIN3(x)        (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_TIMER_PAR_TIN3_IRQ3      (0x20)
+#define MCF_PAD_PAR_TIMER_PAR_TIN3_TIN3      (0x30)
+
+
+#endif /* __MCF5475_PAD_H__ */
--- a/tos/fpga_test/include/MCF5475_PCI.h
+++ b/tos/fpga_test/include/MCF5475_PCI.h
@@ -0,0 +1,376 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_PCI_H__
+#define __MCF5475_PCI_H__
+
+
+/*********************************************************************
+*
+* PCI Bus Controller (PCI)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_PCI_PCIIDR                       (*(volatile uint32_t*)(&_MBAR[0xB00]))
+#define MCF_PCI_PCISCR                       (*(volatile uint32_t*)(&_MBAR[0xB04]))
+#define MCF_PCI_PCICCRIR                     (*(volatile uint32_t*)(&_MBAR[0xB08]))
+#define MCF_PCI_PCICR1                       (*(volatile uint32_t*)(&_MBAR[0xB0C]))
+#define MCF_PCI_PCIBAR0                      (*(volatile uint32_t*)(&_MBAR[0xB10]))
+#define MCF_PCI_PCIBAR1                      (*(volatile uint32_t*)(&_MBAR[0xB14]))
+#define MCF_PCI_PCICCPR                      (*(volatile uint32_t*)(&_MBAR[0xB28]))
+#define MCF_PCI_PCISID                       (*(volatile uint32_t*)(&_MBAR[0xB2C]))
+#define MCF_PCI_PCICR2                       (*(volatile uint32_t*)(&_MBAR[0xB3C]))
+#define MCF_PCI_PCIGSCR                      (*(volatile uint32_t*)(&_MBAR[0xB60]))
+#define MCF_PCI_PCITBATR0                    (*(volatile uint32_t*)(&_MBAR[0xB64]))
+#define MCF_PCI_PCITBATR1                    (*(volatile uint32_t*)(&_MBAR[0xB68]))
+#define MCF_PCI_PCITCR                       (*(volatile uint32_t*)(&_MBAR[0xB6C]))
+#define MCF_PCI_PCIIW0BTAR                   (*(volatile uint32_t*)(&_MBAR[0xB70]))
+#define MCF_PCI_PCIIW1BTAR                   (*(volatile uint32_t*)(&_MBAR[0xB74]))
+#define MCF_PCI_PCIIW2BTAR                   (*(volatile uint32_t*)(&_MBAR[0xB78]))
+#define MCF_PCI_PCIIWCR                      (*(volatile uint32_t*)(&_MBAR[0xB80]))
+#define MCF_PCI_PCIICR                       (*(volatile uint32_t*)(&_MBAR[0xB84]))
+#define MCF_PCI_PCIISR                       (*(volatile uint32_t*)(&_MBAR[0xB88]))
+#define MCF_PCI_PCICAR                       (*(volatile uint32_t*)(&_MBAR[0xBF8]))
+#define MCF_PCI_PCITPSR                      (*(volatile uint32_t*)(&_MBAR[0x8400]))
+#define MCF_PCI_PCITSAR                      (*(volatile uint32_t*)(&_MBAR[0x8404]))
+#define MCF_PCI_PCITTCR                      (*(volatile uint32_t*)(&_MBAR[0x8408]))
+#define MCF_PCI_PCITER                       (*(volatile uint32_t*)(&_MBAR[0x840C]))
+#define MCF_PCI_PCITNAR                      (*(volatile uint32_t*)(&_MBAR[0x8410]))
+#define MCF_PCI_PCITLWR                      (*(volatile uint32_t*)(&_MBAR[0x8414]))
+#define MCF_PCI_PCITDCR                      (*(volatile uint32_t*)(&_MBAR[0x8418]))
+#define MCF_PCI_PCITSR                       (*(volatile uint32_t*)(&_MBAR[0x841C]))
+#define MCF_PCI_PCITFDR                      (*(volatile uint32_t*)(&_MBAR[0x8440]))
+#define MCF_PCI_PCITFSR                      (*(volatile uint32_t*)(&_MBAR[0x8444]))
+#define MCF_PCI_PCITFCR                      (*(volatile uint32_t*)(&_MBAR[0x8448]))
+#define MCF_PCI_PCITFAR                      (*(volatile uint32_t*)(&_MBAR[0x844C]))
+#define MCF_PCI_PCITFRPR                     (*(volatile uint32_t*)(&_MBAR[0x8450]))
+#define MCF_PCI_PCITFWPR                     (*(volatile uint32_t*)(&_MBAR[0x8454]))
+#define MCF_PCI_PCIRPSR                      (*(volatile uint32_t*)(&_MBAR[0x8480]))
+#define MCF_PCI_PCIRSAR                      (*(volatile uint32_t*)(&_MBAR[0x8484]))
+#define MCF_PCI_PCIRTCR                      (*(volatile uint32_t*)(&_MBAR[0x8488]))
+#define MCF_PCI_PCIRER                       (*(volatile uint32_t*)(&_MBAR[0x848C]))
+#define MCF_PCI_PCIRNAR                      (*(volatile uint32_t*)(&_MBAR[0x8490]))
+#define MCF_PCI_PCIRDCR                      (*(volatile uint32_t*)(&_MBAR[0x8498]))
+#define MCF_PCI_PCIRSR                       (*(volatile uint32_t*)(&_MBAR[0x849C]))
+#define MCF_PCI_PCIRFDR                      (*(volatile uint32_t*)(&_MBAR[0x84C0]))
+#define MCF_PCI_PCIRFSR                      (*(volatile uint32_t*)(&_MBAR[0x84C4]))
+#define MCF_PCI_PCIRFCR                      (*(volatile uint32_t*)(&_MBAR[0x84C8]))
+#define MCF_PCI_PCIRFAR                      (*(volatile uint32_t*)(&_MBAR[0x84CC]))
+#define MCF_PCI_PCIRFRPR                     (*(volatile uint32_t*)(&_MBAR[0x84D0]))
+#define MCF_PCI_PCIRFWPR                     (*(volatile uint32_t*)(&_MBAR[0x84D4]))
+
+
+/* Bit definitions and macros for MCF_PCI_PCIIDR */
+#define MCF_PCI_PCIIDR_VENDORID(x)           (((x)&0xFFFF)<<0)
+#define MCF_PCI_PCIIDR_DEVICEID(x)           (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_PCI_PCISCR */
+#define MCF_PCI_PCISCR_IO                    (0x1)
+#define MCF_PCI_PCISCR_M                     (0x2)
+#define MCF_PCI_PCISCR_B                     (0x4)
+#define MCF_PCI_PCISCR_SP                    (0x8)
+#define MCF_PCI_PCISCR_MW                    (0x10)
+#define MCF_PCI_PCISCR_V                     (0x20)
+#define MCF_PCI_PCISCR_PER                   (0x40)
+#define MCF_PCI_PCISCR_ST                    (0x80)
+#define MCF_PCI_PCISCR_S                     (0x100)
+#define MCF_PCI_PCISCR_F                     (0x200)
+#define MCF_PCI_PCISCR_C                     (0x100000)
+#define MCF_PCI_PCISCR_66M                   (0x200000)
+#define MCF_PCI_PCISCR_R                     (0x400000)
+#define MCF_PCI_PCISCR_FC                    (0x800000)
+#define MCF_PCI_PCISCR_DP                    (0x1000000)
+#define MCF_PCI_PCISCR_DT(x)                 (((x)&0x3)<<0x19)
+#define MCF_PCI_PCISCR_TS                    (0x8000000)
+#define MCF_PCI_PCISCR_TR                    (0x10000000)
+#define MCF_PCI_PCISCR_MA                    (0x20000000)
+#define MCF_PCI_PCISCR_SE                    (0x40000000)
+#define MCF_PCI_PCISCR_PE                    (0x80000000)
+
+/* Bit definitions and macros for MCF_PCI_PCICCRIR */
+#define MCF_PCI_PCICCRIR_REVISIONID(x)       (((x)&0xFF)<<0)
+#define MCF_PCI_PCICCRIR_CLASSCODE(x)        (((x)&0xFFFFFF)<<0x8)
+
+/* Bit definitions and macros for MCF_PCI_PCICR1 */
+#define MCF_PCI_PCICR1_CACHELINESIZE(x)      (((x)&0xFF)<<0)
+#define MCF_PCI_PCICR1_LATTIMER(x)           (((x)&0xFF)<<0x8)
+#define MCF_PCI_PCICR1_HEADERTYPE(x)         (((x)&0xFF)<<0x10)
+#define MCF_PCI_PCICR1_BIST(x)               (((x)&0xFF)<<0x18)
+
+/* Bit definitions and macros for MCF_PCI_PCIBAR0 */
+#define MCF_PCI_PCIBAR0_IOM                  (0x1)
+#define MCF_PCI_PCIBAR0_RANGE(x)             (((x)&0x3)<<0x1)
+#define MCF_PCI_PCIBAR0_PREF                 (0x8)
+#define MCF_PCI_PCIBAR0_BAR0(x)              (((x)&0x3FFF)<<0x12)
+
+/* Bit definitions and macros for MCF_PCI_PCIBAR1 */
+#define MCF_PCI_PCIBAR1_IOM                  (0x1)
+#define MCF_PCI_PCIBAR1_RANGE(x)             (((x)&0x3)<<0x1)
+#define MCF_PCI_PCIBAR1_PREF                 (0x8)
+#define MCF_PCI_PCIBAR1_BAR1(x)              (((x)&0x3)<<0x1E)
+
+/* Bit definitions and macros for MCF_PCI_PCICCPR */
+#define MCF_PCI_PCICCPR_PCICCP(x)            (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCISID */
+#define MCF_PCI_PCISID_VENDORID(x)           (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCICR2 */
+#define MCF_PCI_PCICR2_INTLINE(x)            (((x)&0xFF)<<0)
+#define MCF_PCI_PCICR2_INTPIN(x)             (((x)&0xFF)<<0x8)
+#define MCF_PCI_PCICR2_MINGNT(x)             (((x)&0xFF)<<0x10)
+#define MCF_PCI_PCICR2_MAXLAT(x)             (((x)&0xFF)<<0x18)
+
+/* Bit definitions and macros for MCF_PCI_PCIGSCR */
+#define MCF_PCI_PCIGSCR_PR                   (0x1)
+#define MCF_PCI_PCIGSCR_SEE                  (0x1000)
+#define MCF_PCI_PCIGSCR_PEE                  (0x2000)
+#define MCF_PCI_PCIGSCR_CLKINRESERVED(x)     (((x)&0x7)<<0x10)
+#define MCF_PCI_PCIGSCR_XLB2CLKIN(x)         (((x)&0x7)<<0x18)
+#define MCF_PCI_PCIGSCR_SE                   (0x10000000)
+#define MCF_PCI_PCIGSCR_PE                   (0x20000000)
+
+/* Bit definitions and macros for MCF_PCI_PCITBATR0 */
+#define MCF_PCI_PCITBATR0_EN                 (0x1)
+#define MCF_PCI_PCITBATR0_BAT0(x)            (((x)&0x3FFF)<<0x12)
+
+/* Bit definitions and macros for MCF_PCI_PCITBATR1 */
+#define MCF_PCI_PCITBATR1_EN                 (0x1)
+#define MCF_PCI_PCITBATR1_BAT1(x)            (((x)&0x3)<<0x1E)
+
+/* Bit definitions and macros for MCF_PCI_PCITCR */
+#define MCF_PCI_PCITCR_P                     (0x10000)
+#define MCF_PCI_PCITCR_LD                    (0x1000000)
+
+/* Bit definitions and macros for MCF_PCI_PCIIW0BTAR */
+#define MCF_PCI_PCIIW0BTAR_WTA0(x)           (((x)&0xFF)<<0x8)
+#define MCF_PCI_PCIIW0BTAR_WAM0(x)           (((x)&0xFF)<<0x10)
+#define MCF_PCI_PCIIW0BTAR_WBA0(x)           (((x)&0xFF)<<0x18)
+
+/* Bit definitions and macros for MCF_PCI_PCIIW1BTAR */
+#define MCF_PCI_PCIIW1BTAR_WTA1(x)           (((x)&0xFF)<<0x8)
+#define MCF_PCI_PCIIW1BTAR_WAM1(x)           (((x)&0xFF)<<0x10)
+#define MCF_PCI_PCIIW1BTAR_WBA1(x)           (((x)&0xFF)<<0x18)
+
+/* Bit definitions and macros for MCF_PCI_PCIIW2BTAR */
+#define MCF_PCI_PCIIW2BTAR_WTA2(x)           (((x)&0xFF)<<0x8)
+#define MCF_PCI_PCIIW2BTAR_WAM2(x)           (((x)&0xFF)<<0x10)
+#define MCF_PCI_PCIIW2BTAR_WBA2(x)           (((x)&0xFF)<<0x18)
+
+/* Bit definitions and macros for MCF_PCI_PCIIWCR */
+#define MCF_PCI_PCIIWCR_WINCTRL2_E           (0x100)
+#define MCF_PCI_PCIIWCR_WINCTRL2_PRC(x)      (((x)&0x3)<<0x9)
+#define MCF_PCI_PCIIWCR_WINCTRL2_IOM         (0x800)
+#define MCF_PCI_PCIIWCR_WINCTRL1_E           (0x10000)
+#define MCF_PCI_PCIIWCR_WINCTRL1_PRC(x)      (((x)&0x3)<<0x11)
+#define MCF_PCI_PCIIWCR_WINCTRL1_IOM         (0x80000)
+#define MCF_PCI_PCIIWCR_WINCTRL0_E           (0x1000000)
+#define MCF_PCI_PCIIWCR_WINCTRL0_PRC(x)      (((x)&0x3)<<0x19)
+#define MCF_PCI_PCIIWCR_WINCTRL0_IOM         (0x8000000)
+#define MCF_PCI_PCIIWCR_WINCTRL2_MEMREAD     (0x100)
+#define MCF_PCI_PCIIWCR_WINCTRL2_MEMRDLINE   (0x300)
+#define MCF_PCI_PCIIWCR_WINCTRL2_MEMRDMUL    (0x500)
+#define MCF_PCI_PCIIWCR_WINCTRL2_IO          (0x900)
+#define MCF_PCI_PCIIWCR_WINCTRL1_MEMREAD     (0x10000)
+#define MCF_PCI_PCIIWCR_WINCTRL1_MEMRDLINE   (0x30000)
+#define MCF_PCI_PCIIWCR_WINCTRL1_MEMRDMUL    (0x50000)
+#define MCF_PCI_PCIIWCR_WINCTRL1_IO          (0x90000)
+#define MCF_PCI_PCIIWCR_WINCTRL0_MEMREAD     (0x1000000)
+#define MCF_PCI_PCIIWCR_WINCTRL0_MEMRDLINE   (0x3000000)
+#define MCF_PCI_PCIIWCR_WINCTRL0_MEMRDMUL    (0x5000000)
+#define MCF_PCI_PCIIWCR_WINCTRL0_IO          (0x9000000)
+
+/* Bit definitions and macros for MCF_PCI_PCIICR */
+#define MCF_PCI_PCIICR_MAXRETRY(x)           (((x)&0xFF)<<0)
+#define MCF_PCI_PCIICR_TAE                   (0x1000000)
+#define MCF_PCI_PCIICR_IAE                   (0x2000000)
+#define MCF_PCI_PCIICR_REE                   (0x4000000)
+
+/* Bit definitions and macros for MCF_PCI_PCIISR */
+#define MCF_PCI_PCIISR_TA                    (0x1000000)
+#define MCF_PCI_PCIISR_IA                    (0x2000000)
+#define MCF_PCI_PCIISR_RE                    (0x4000000)
+
+/* Bit definitions and macros for MCF_PCI_PCICAR */
+#define MCF_PCI_PCICAR_DWORD(x)              (((x)&0x3F)<<0x2)
+#define MCF_PCI_PCICAR_FUNCNUM(x)            (((x)&0x7)<<0x8)
+#define MCF_PCI_PCICAR_DEVNUM(x)             (((x)&0x1F)<<0xB)
+#define MCF_PCI_PCICAR_BUSNUM(x)             (((x)&0xFF)<<0x10)
+#define MCF_PCI_PCICAR_E                     (0x80000000)
+
+/* Bit definitions and macros for MCF_PCI_PCITPSR */
+#define MCF_PCI_PCITPSR_PKTSIZE(x)           (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_PCI_PCITSAR */
+#define MCF_PCI_PCITSAR_STARTADD(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCITTCR */
+#define MCF_PCI_PCITTCR_DI                   (0x1)
+#define MCF_PCI_PCITTCR_W                    (0x10)
+#define MCF_PCI_PCITTCR_MAXBEATS(x)          (((x)&0x7)<<0x8)
+#define MCF_PCI_PCITTCR_MAXRETRY(x)          (((x)&0xFF)<<0x10)
+#define MCF_PCI_PCITTCR_PCICMD(x)            (((x)&0xF)<<0x18)
+
+/* Bit definitions and macros for MCF_PCI_PCITER */
+#define MCF_PCI_PCITER_NE                    (0x10000)
+#define MCF_PCI_PCITER_IAE                   (0x20000)
+#define MCF_PCI_PCITER_TAE                   (0x40000)
+#define MCF_PCI_PCITER_RE                    (0x80000)
+#define MCF_PCI_PCITER_SE                    (0x100000)
+#define MCF_PCI_PCITER_FEE                   (0x200000)
+#define MCF_PCI_PCITER_ME                    (0x1000000)
+#define MCF_PCI_PCITER_BE                    (0x8000000)
+#define MCF_PCI_PCITER_CM                    (0x10000000)
+#define MCF_PCI_PCITER_RF                    (0x40000000)
+#define MCF_PCI_PCITER_RC                    (0x80000000)
+
+/* Bit definitions and macros for MCF_PCI_PCITNAR */
+#define MCF_PCI_PCITNAR_NEXTADDRESS(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCITLWR */
+#define MCF_PCI_PCITLWR_LASTWORD(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCITDCR */
+#define MCF_PCI_PCITDCR_PKTSDONE(x)          (((x)&0xFFFF)<<0)
+#define MCF_PCI_PCITDCR_BYTESDONE(x)         (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_PCI_PCITSR */
+#define MCF_PCI_PCITSR_IA                    (0x10000)
+#define MCF_PCI_PCITSR_TA                    (0x20000)
+#define MCF_PCI_PCITSR_RE                    (0x40000)
+#define MCF_PCI_PCITSR_SE                    (0x80000)
+#define MCF_PCI_PCITSR_FE                    (0x100000)
+#define MCF_PCI_PCITSR_BE1                   (0x200000)
+#define MCF_PCI_PCITSR_BE2                   (0x400000)
+#define MCF_PCI_PCITSR_BE3                   (0x800000)
+#define MCF_PCI_PCITSR_NT                    (0x1000000)
+
+/* Bit definitions and macros for MCF_PCI_PCITFDR */
+#define MCF_PCI_PCITFDR_FIFODATAWORD(x)      (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCITFSR */
+#define MCF_PCI_PCITFSR_EMPTY                (0x10000)
+#define MCF_PCI_PCITFSR_ALARM                (0x20000)
+#define MCF_PCI_PCITFSR_FULL                 (0x40000)
+#define MCF_PCI_PCITFSR_FR                   (0x80000)
+#define MCF_PCI_PCITFSR_OF                   (0x100000)
+#define MCF_PCI_PCITFSR_UF                   (0x200000)
+#define MCF_PCI_PCITFSR_RXW                  (0x400000)
+#define MCF_PCI_PCITFSR_FAE                  (0x800000)
+#define MCF_PCI_PCITFSR_TXW                  (0x40000000)
+#define MCF_PCI_PCITFSR_IP                   (0x80000000)
+
+/* Bit definitions and macros for MCF_PCI_PCITFCR */
+#define MCF_PCI_PCITFCR_TXW_MASK             (0x40000)
+#define MCF_PCI_PCITFCR_OF_MASK              (0x80000)
+#define MCF_PCI_PCITFCR_UF_MASK              (0x100000)
+#define MCF_PCI_PCITFCR_RXW_MASK             (0x200000)
+#define MCF_PCI_PCITFCR_FAE_MASK             (0x400000)
+#define MCF_PCI_PCITFCR_IP_MASK              (0x800000)
+#define MCF_PCI_PCITFCR_GR(x)                (((x)&0x7)<<0x18)
+#define MCF_PCI_PCITFCR_WFR                  (0x20000000)
+
+/* Bit definitions and macros for MCF_PCI_PCITFAR */
+#define MCF_PCI_PCITFAR_ALARM(x)             (((x)&0xFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCITFRPR */
+#define MCF_PCI_PCITFRPR_READPTR(x)          (((x)&0x7F)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCITFWPR */
+#define MCF_PCI_PCITFWPR_WRITEPTR(x)         (((x)&0x7F)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCIRPSR */
+#define MCF_PCI_PCIRPSR_PKTSIZE(x)           (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_PCI_PCIRSAR */
+#define MCF_PCI_PCIRSAR_STARTADD(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCIRTCR */
+#define MCF_PCI_PCIRTCR_DI                   (0x1)
+#define MCF_PCI_PCIRTCR_W                    (0x10)
+#define MCF_PCI_PCIRTCR_MAXBEATS(x)          (((x)&0x7)<<0x8)
+#define MCF_PCI_PCIRTCR_FB                   (0x1000)
+#define MCF_PCI_PCIRTCR_MAXRETRY(x)          (((x)&0xFF)<<0x10)
+#define MCF_PCI_PCIRTCR_PCICMD(x)            (((x)&0xF)<<0x18)
+
+/* Bit definitions and macros for MCF_PCI_PCIRER */
+#define MCF_PCI_PCIRER_NE                    (0x10000)
+#define MCF_PCI_PCIRER_IAE                   (0x20000)
+#define MCF_PCI_PCIRER_TAE                   (0x40000)
+#define MCF_PCI_PCIRER_RE                    (0x80000)
+#define MCF_PCI_PCIRER_SE                    (0x100000)
+#define MCF_PCI_PCIRER_FEE                   (0x200000)
+#define MCF_PCI_PCIRER_ME                    (0x1000000)
+#define MCF_PCI_PCIRER_BE                    (0x8000000)
+#define MCF_PCI_PCIRER_CM                    (0x10000000)
+#define MCF_PCI_PCIRER_FE                    (0x20000000)
+#define MCF_PCI_PCIRER_RF                    (0x40000000)
+#define MCF_PCI_PCIRER_RC                    (0x80000000)
+
+/* Bit definitions and macros for MCF_PCI_PCIRNAR */
+#define MCF_PCI_PCIRNAR_NEXTADDRESS(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCIRDCR */
+#define MCF_PCI_PCIRDCR_PKTSDONE(x)          (((x)&0xFFFF)<<0)
+#define MCF_PCI_PCIRDCR_BYTESDONE(x)         (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_PCI_PCIRSR */
+#define MCF_PCI_PCIRSR_IA                    (0x10000)
+#define MCF_PCI_PCIRSR_TA                    (0x20000)
+#define MCF_PCI_PCIRSR_RE                    (0x40000)
+#define MCF_PCI_PCIRSR_SE                    (0x80000)
+#define MCF_PCI_PCIRSR_FE                    (0x100000)
+#define MCF_PCI_PCIRSR_BE1                   (0x200000)
+#define MCF_PCI_PCIRSR_BE2                   (0x400000)
+#define MCF_PCI_PCIRSR_BE3                   (0x800000)
+#define MCF_PCI_PCIRSR_NT                    (0x1000000)
+
+/* Bit definitions and macros for MCF_PCI_PCIRFDR */
+#define MCF_PCI_PCIRFDR_FIFODATAWORD(x)      (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCIRFSR */
+#define MCF_PCI_PCIRFSR_EMPTY                (0x10000)
+#define MCF_PCI_PCIRFSR_ALARM                (0x20000)
+#define MCF_PCI_PCIRFSR_FULL                 (0x40000)
+#define MCF_PCI_PCIRFSR_FR                   (0x80000)
+#define MCF_PCI_PCIRFSR_OF                   (0x100000)
+#define MCF_PCI_PCIRFSR_UF                   (0x200000)
+#define MCF_PCI_PCIRFSR_RXW                  (0x400000)
+#define MCF_PCI_PCIRFSR_FAE                  (0x800000)
+#define MCF_PCI_PCIRFSR_TXW                  (0x40000000)
+#define MCF_PCI_PCIRFSR_IP                   (0x80000000)
+
+/* Bit definitions and macros for MCF_PCI_PCIRFCR */
+#define MCF_PCI_PCIRFCR_TXW_MASK             (0x40000)
+#define MCF_PCI_PCIRFCR_OF_MASK              (0x80000)
+#define MCF_PCI_PCIRFCR_UF_MASK              (0x100000)
+#define MCF_PCI_PCIRFCR_RXW_MASK             (0x200000)
+#define MCF_PCI_PCIRFCR_FAE_MASK             (0x400000)
+#define MCF_PCI_PCIRFCR_IP_MASK              (0x800000)
+#define MCF_PCI_PCIRFCR_GR(x)                (((x)&0x7)<<0x18)
+#define MCF_PCI_PCIRFCR_WFR                  (0x20000000)
+
+/* Bit definitions and macros for MCF_PCI_PCIRFAR */
+#define MCF_PCI_PCIRFAR_ALARM(x)             (((x)&0x7F)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCIRFRPR */
+#define MCF_PCI_PCIRFRPR_READPTR(x)          (((x)&0x7F)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCIRFWPR */
+#define MCF_PCI_PCIRFWPR_WRITEPTR(x)         (((x)&0x7F)<<0)
+
+
+#endif /* __MCF5475_PCI_H__ */
--- a/tos/fpga_test/include/MCF5475_PCIARB.h
+++ b/tos/fpga_test/include/MCF5475_PCIARB.h
@@ -0,0 +1,43 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_PCIARB_H__
+#define __MCF5475_PCIARB_H__
+
+
+/*********************************************************************
+*
+* PCI Bus Arbiter Module (PCIARB)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_PCIARB_PACR                      (*(volatile uint32_t*)(&_MBAR[0xC00]))
+#define MCF_PCIARB_PASR                      (*(volatile uint32_t*)(&_MBAR[0xC04]))
+
+
+/* Bit definitions and macros for MCF_PCIARB_PACR */
+#define MCF_PCIARB_PACR_INTMPRI              (0x1)
+#define MCF_PCIARB_PACR_EXTMPRI(x)           (((x)&0x1F)<<0x1)
+#define MCF_PCIARB_PACR_INTMINTEN            (0x10000)
+#define MCF_PCIARB_PACR_EXTMINTEN(x)         (((x)&0x1F)<<0x11)
+#define MCF_PCIARB_PACR_DS                   (0x80000000)
+
+/* Bit definitions and macros for MCF_PCIARB_PASR */
+#define MCF_PCIARB_PASR_ITLMBK               (0x10000)
+#define MCF_PCIARB_PASR_EXTMBK(x)            (((x)&0x1F)<<0x11)
+
+
+#endif /* __MCF5475_PCIARB_H__ */
--- a/tos/fpga_test/include/MCF5475_PSC.h
+++ b/tos/fpga_test/include/MCF5475_PSC.h
@@ -0,0 +1,527 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_PSC_H__
+#define __MCF5475_PSC_H__
+
+
+/*********************************************************************
+*
+* Programmable Serial Controller (PSC)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_PSC0_PSCMR2                      (*(volatile uint8_t *)(&_MBAR[0x8600]))
+#define MCF_PSC0_PSCMR1                      (*(volatile uint8_t *)(&_MBAR[0x8600]))
+#define MCF_PSC0_PSCCSR                      (*(volatile uint8_t *)(&_MBAR[0x8604]))
+#define MCF_PSC0_PSCSR                       (*(volatile uint16_t*)(&_MBAR[0x8604]))
+#define MCF_PSC0_PSCCR                       (*(volatile uint8_t *)(&_MBAR[0x8608]))
+#define MCF_PSC0_PSCRB_8BIT                  (*(volatile uint32_t*)(&_MBAR[0x860C]))
+#define MCF_PSC0_PSCTB_8BIT                  (*(volatile uint32_t*)(&_MBAR[0x860C]))
+#define MCF_PSC0_PSCRB_16BIT                 (*(volatile uint32_t*)(&_MBAR[0x860C]))
+#define MCF_PSC0_PSCTB_16BIT                 (*(volatile uint32_t*)(&_MBAR[0x860C]))
+#define MCF_PSC0_PSCRB_AC97                  (*(volatile uint32_t*)(&_MBAR[0x860C]))
+#define MCF_PSC0_PSCTB_AC97                  (*(volatile uint32_t*)(&_MBAR[0x860C]))
+#define MCF_PSC0_PSCIPCR                     (*(volatile uint8_t *)(&_MBAR[0x8610]))
+#define MCF_PSC0_PSCACR                      (*(volatile uint8_t *)(&_MBAR[0x8610]))
+#define MCF_PSC0_PSCIMR                      (*(volatile uint16_t*)(&_MBAR[0x8614]))
+#define MCF_PSC0_PSCISR                      (*(volatile uint16_t*)(&_MBAR[0x8614]))
+#define MCF_PSC0_PSCCTUR                     (*(volatile uint8_t *)(&_MBAR[0x8618]))
+#define MCF_PSC0_PSCCTLR                     (*(volatile uint8_t *)(&_MBAR[0x861C]))
+#define MCF_PSC0_PSCIP                       (*(volatile uint8_t *)(&_MBAR[0x8634]))
+#define MCF_PSC0_PSCOPSET                    (*(volatile uint8_t *)(&_MBAR[0x8638]))
+#define MCF_PSC0_PSCOPRESET                  (*(volatile uint8_t *)(&_MBAR[0x863C]))
+#define MCF_PSC0_PSCSICR                     (*(volatile uint8_t *)(&_MBAR[0x8640]))
+#define MCF_PSC0_PSCIRCR1                    (*(volatile uint8_t *)(&_MBAR[0x8644]))
+#define MCF_PSC0_PSCIRCR2                    (*(volatile uint8_t *)(&_MBAR[0x8648]))
+#define MCF_PSC0_PSCIRSDR                    (*(volatile uint8_t *)(&_MBAR[0x864C]))
+#define MCF_PSC0_PSCIRMDR                    (*(volatile uint8_t *)(&_MBAR[0x8650]))
+#define MCF_PSC0_PSCIRFDR                    (*(volatile uint8_t *)(&_MBAR[0x8654]))
+#define MCF_PSC0_PSCRFCNT                    (*(volatile uint16_t*)(&_MBAR[0x8658]))
+#define MCF_PSC0_PSCTFCNT                    (*(volatile uint16_t*)(&_MBAR[0x865C]))
+#define MCF_PSC0_PSCRFDR                     (*(volatile uint32_t*)(&_MBAR[0x8660]))
+#define MCF_PSC0_PSCRFSR                     (*(volatile uint16_t*)(&_MBAR[0x8664]))
+#define MCF_PSC0_PSCRFCR                     (*(volatile uint32_t*)(&_MBAR[0x8668]))
+#define MCF_PSC0_PSCRFAR                     (*(volatile uint16_t*)(&_MBAR[0x866E]))
+#define MCF_PSC0_PSCRFRP                     (*(volatile uint16_t*)(&_MBAR[0x8672]))
+#define MCF_PSC0_PSCRFWP                     (*(volatile uint16_t*)(&_MBAR[0x8676]))
+#define MCF_PSC0_PSCRLRFP                    (*(volatile uint16_t*)(&_MBAR[0x867A]))
+#define MCF_PSC0_PSCRLWFP                    (*(volatile uint16_t*)(&_MBAR[0x867E]))
+#define MCF_PSC0_PSCTFDR                     (*(volatile uint32_t*)(&_MBAR[0x8680]))
+#define MCF_PSC0_PSCTFSR                     (*(volatile uint16_t*)(&_MBAR[0x8684]))
+#define MCF_PSC0_PSCTFCR                     (*(volatile uint32_t*)(&_MBAR[0x8688]))
+#define MCF_PSC0_PSCTFAR                     (*(volatile uint16_t*)(&_MBAR[0x868E]))
+#define MCF_PSC0_PSCTFRP                     (*(volatile uint16_t*)(&_MBAR[0x8692]))
+#define MCF_PSC0_PSCTFWP                     (*(volatile uint16_t*)(&_MBAR[0x8696]))
+#define MCF_PSC0_PSCTLRFP                    (*(volatile uint16_t*)(&_MBAR[0x869A]))
+#define MCF_PSC0_PSCTLWFP                    (*(volatile uint16_t*)(&_MBAR[0x869E]))
+
+#define MCF_PSC1_PSCMR2                      (*(volatile uint8_t *)(&_MBAR[0x8700]))
+#define MCF_PSC1_PSCMR1                      (*(volatile uint8_t *)(&_MBAR[0x8700]))
+#define MCF_PSC1_PSCCSR                      (*(volatile uint8_t *)(&_MBAR[0x8704]))
+#define MCF_PSC1_PSCSR                       (*(volatile uint16_t*)(&_MBAR[0x8704]))
+#define MCF_PSC1_PSCCR                       (*(volatile uint8_t *)(&_MBAR[0x8708]))
+#define MCF_PSC1_PSCRB_8BIT                  (*(volatile uint32_t*)(&_MBAR[0x870C]))
+#define MCF_PSC1_PSCTB_8BIT                  (*(volatile uint32_t*)(&_MBAR[0x870C]))
+#define MCF_PSC1_PSCRB_16BIT                 (*(volatile uint32_t*)(&_MBAR[0x870C]))
+#define MCF_PSC1_PSCTB_16BIT                 (*(volatile uint32_t*)(&_MBAR[0x870C]))
+#define MCF_PSC1_PSCRB_AC97                  (*(volatile uint32_t*)(&_MBAR[0x870C]))
+#define MCF_PSC1_PSCTB_AC97                  (*(volatile uint32_t*)(&_MBAR[0x870C]))
+#define MCF_PSC1_PSCIPCR                     (*(volatile uint8_t *)(&_MBAR[0x8710]))
+#define MCF_PSC1_PSCACR                      (*(volatile uint8_t *)(&_MBAR[0x8710]))
+#define MCF_PSC1_PSCIMR                      (*(volatile uint16_t*)(&_MBAR[0x8714]))
+#define MCF_PSC1_PSCISR                      (*(volatile uint16_t*)(&_MBAR[0x8714]))
+#define MCF_PSC1_PSCCTUR                     (*(volatile uint8_t *)(&_MBAR[0x8718]))
+#define MCF_PSC1_PSCCTLR                     (*(volatile uint8_t *)(&_MBAR[0x871C]))
+#define MCF_PSC1_PSCIP                       (*(volatile uint8_t *)(&_MBAR[0x8734]))
+#define MCF_PSC1_PSCOPSET                    (*(volatile uint8_t *)(&_MBAR[0x8738]))
+#define MCF_PSC1_PSCOPRESET                  (*(volatile uint8_t *)(&_MBAR[0x873C]))
+#define MCF_PSC1_PSCSICR                     (*(volatile uint8_t *)(&_MBAR[0x8740]))
+#define MCF_PSC1_PSCIRCR1                    (*(volatile uint8_t *)(&_MBAR[0x8744]))
+#define MCF_PSC1_PSCIRCR2                    (*(volatile uint8_t *)(&_MBAR[0x8748]))
+#define MCF_PSC1_PSCIRSDR                    (*(volatile uint8_t *)(&_MBAR[0x874C]))
+#define MCF_PSC1_PSCIRMDR                    (*(volatile uint8_t *)(&_MBAR[0x8750]))
+#define MCF_PSC1_PSCIRFDR                    (*(volatile uint8_t *)(&_MBAR[0x8754]))
+#define MCF_PSC1_PSCRFCNT                    (*(volatile uint16_t*)(&_MBAR[0x8758]))
+#define MCF_PSC1_PSCTFCNT                    (*(volatile uint16_t*)(&_MBAR[0x875C]))
+#define MCF_PSC1_PSCRFDR                     (*(volatile uint32_t*)(&_MBAR[0x8760]))
+#define MCF_PSC1_PSCRFSR                     (*(volatile uint16_t*)(&_MBAR[0x8764]))
+#define MCF_PSC1_PSCRFCR                     (*(volatile uint32_t*)(&_MBAR[0x8768]))
+#define MCF_PSC1_PSCRFAR                     (*(volatile uint16_t*)(&_MBAR[0x876E]))
+#define MCF_PSC1_PSCRFRP                     (*(volatile uint16_t*)(&_MBAR[0x8772]))
+#define MCF_PSC1_PSCRFWP                     (*(volatile uint16_t*)(&_MBAR[0x8776]))
+#define MCF_PSC1_PSCRLRFP                    (*(volatile uint16_t*)(&_MBAR[0x877A]))
+#define MCF_PSC1_PSCRLWFP                    (*(volatile uint16_t*)(&_MBAR[0x877E]))
+#define MCF_PSC1_PSCTFDR                     (*(volatile uint32_t*)(&_MBAR[0x8780]))
+#define MCF_PSC1_PSCTFSR                     (*(volatile uint16_t*)(&_MBAR[0x8784]))
+#define MCF_PSC1_PSCTFCR                     (*(volatile uint32_t*)(&_MBAR[0x8788]))
+#define MCF_PSC1_PSCTFAR                     (*(volatile uint16_t*)(&_MBAR[0x878E]))
+#define MCF_PSC1_PSCTFRP                     (*(volatile uint16_t*)(&_MBAR[0x8792]))
+#define MCF_PSC1_PSCTFWP                     (*(volatile uint16_t*)(&_MBAR[0x8796]))
+#define MCF_PSC1_PSCTLRFP                    (*(volatile uint16_t*)(&_MBAR[0x879A]))
+#define MCF_PSC1_PSCTLWFP                    (*(volatile uint16_t*)(&_MBAR[0x879E]))
+
+#define MCF_PSC2_PSCMR2                      (*(volatile uint8_t *)(&_MBAR[0x8800]))
+#define MCF_PSC2_PSCMR1                      (*(volatile uint8_t *)(&_MBAR[0x8800]))
+#define MCF_PSC2_PSCCSR                      (*(volatile uint8_t *)(&_MBAR[0x8804]))
+#define MCF_PSC2_PSCSR                       (*(volatile uint16_t*)(&_MBAR[0x8804]))
+#define MCF_PSC2_PSCCR                       (*(volatile uint8_t *)(&_MBAR[0x8808]))
+#define MCF_PSC2_PSCRB_8BIT                  (*(volatile uint32_t*)(&_MBAR[0x880C]))
+#define MCF_PSC2_PSCTB_8BIT                  (*(volatile uint32_t*)(&_MBAR[0x880C]))
+#define MCF_PSC2_PSCRB_16BIT                 (*(volatile uint32_t*)(&_MBAR[0x880C]))
+#define MCF_PSC2_PSCTB_16BIT                 (*(volatile uint32_t*)(&_MBAR[0x880C]))
+#define MCF_PSC2_PSCRB_AC97                  (*(volatile uint32_t*)(&_MBAR[0x880C]))
+#define MCF_PSC2_PSCTB_AC97                  (*(volatile uint32_t*)(&_MBAR[0x880C]))
+#define MCF_PSC2_PSCIPCR                     (*(volatile uint8_t *)(&_MBAR[0x8810]))
+#define MCF_PSC2_PSCACR                      (*(volatile uint8_t *)(&_MBAR[0x8810]))
+#define MCF_PSC2_PSCIMR                      (*(volatile uint16_t*)(&_MBAR[0x8814]))
+#define MCF_PSC2_PSCISR                      (*(volatile uint16_t*)(&_MBAR[0x8814]))
+#define MCF_PSC2_PSCCTUR                     (*(volatile uint8_t *)(&_MBAR[0x8818]))
+#define MCF_PSC2_PSCCTLR                     (*(volatile uint8_t *)(&_MBAR[0x881C]))
+#define MCF_PSC2_PSCIP                       (*(volatile uint8_t *)(&_MBAR[0x8834]))
+#define MCF_PSC2_PSCOPSET                    (*(volatile uint8_t *)(&_MBAR[0x8838]))
+#define MCF_PSC2_PSCOPRESET                  (*(volatile uint8_t *)(&_MBAR[0x883C]))
+#define MCF_PSC2_PSCSICR                     (*(volatile uint8_t *)(&_MBAR[0x8840]))
+#define MCF_PSC2_PSCIRCR1                    (*(volatile uint8_t *)(&_MBAR[0x8844]))
+#define MCF_PSC2_PSCIRCR2                    (*(volatile uint8_t *)(&_MBAR[0x8848]))
+#define MCF_PSC2_PSCIRSDR                    (*(volatile uint8_t *)(&_MBAR[0x884C]))
+#define MCF_PSC2_PSCIRMDR                    (*(volatile uint8_t *)(&_MBAR[0x8850]))
+#define MCF_PSC2_PSCIRFDR                    (*(volatile uint8_t *)(&_MBAR[0x8854]))
+#define MCF_PSC2_PSCRFCNT                    (*(volatile uint16_t*)(&_MBAR[0x8858]))
+#define MCF_PSC2_PSCTFCNT                    (*(volatile uint16_t*)(&_MBAR[0x885C]))
+#define MCF_PSC2_PSCRFDR                     (*(volatile uint32_t*)(&_MBAR[0x8860]))
+#define MCF_PSC2_PSCRFSR                     (*(volatile uint16_t*)(&_MBAR[0x8864]))
+#define MCF_PSC2_PSCRFCR                     (*(volatile uint32_t*)(&_MBAR[0x8868]))
+#define MCF_PSC2_PSCRFAR                     (*(volatile uint16_t*)(&_MBAR[0x886E]))
+#define MCF_PSC2_PSCRFRP                     (*(volatile uint16_t*)(&_MBAR[0x8872]))
+#define MCF_PSC2_PSCRFWP                     (*(volatile uint16_t*)(&_MBAR[0x8876]))
+#define MCF_PSC2_PSCRLRFP                    (*(volatile uint16_t*)(&_MBAR[0x887A]))
+#define MCF_PSC2_PSCRLWFP                    (*(volatile uint16_t*)(&_MBAR[0x887E]))
+#define MCF_PSC2_PSCTFDR                     (*(volatile uint32_t*)(&_MBAR[0x8880]))
+#define MCF_PSC2_PSCTFSR                     (*(volatile uint16_t*)(&_MBAR[0x8884]))
+#define MCF_PSC2_PSCTFCR                     (*(volatile uint32_t*)(&_MBAR[0x8888]))
+#define MCF_PSC2_PSCTFAR                     (*(volatile uint16_t*)(&_MBAR[0x888E]))
+#define MCF_PSC2_PSCTFRP                     (*(volatile uint16_t*)(&_MBAR[0x8892]))
+#define MCF_PSC2_PSCTFWP                     (*(volatile uint16_t*)(&_MBAR[0x8896]))
+#define MCF_PSC2_PSCTLRFP                    (*(volatile uint16_t*)(&_MBAR[0x889A]))
+#define MCF_PSC2_PSCTLWFP                    (*(volatile uint16_t*)(&_MBAR[0x889E]))
+
+#define MCF_PSC3_PSCMR2                      (*(volatile uint8_t *)(&_MBAR[0x8900]))
+#define MCF_PSC3_PSCMR1                      (*(volatile uint8_t *)(&_MBAR[0x8900]))
+#define MCF_PSC3_PSCCSR                      (*(volatile uint8_t *)(&_MBAR[0x8904]))
+#define MCF_PSC3_PSCSR                       (*(volatile uint16_t*)(&_MBAR[0x8904]))
+#define MCF_PSC3_PSCCR                       (*(volatile uint8_t *)(&_MBAR[0x8908]))
+#define MCF_PSC3_PSCRB_8BIT                  (*(volatile uint32_t*)(&_MBAR[0x890C]))
+#define MCF_PSC3_PSCTB_8BIT                  (*(volatile uint32_t*)(&_MBAR[0x890C]))
+#define MCF_PSC3_PSCRB_16BIT                 (*(volatile uint32_t*)(&_MBAR[0x890C]))
+#define MCF_PSC3_PSCTB_16BIT                 (*(volatile uint32_t*)(&_MBAR[0x890C]))
+#define MCF_PSC3_PSCRB_AC97                  (*(volatile uint32_t*)(&_MBAR[0x890C]))
+#define MCF_PSC3_PSCTB_AC97                  (*(volatile uint32_t*)(&_MBAR[0x890C]))
+#define MCF_PSC3_PSCIPCR                     (*(volatile uint8_t *)(&_MBAR[0x8910]))
+#define MCF_PSC3_PSCACR                      (*(volatile uint8_t *)(&_MBAR[0x8910]))
+#define MCF_PSC3_PSCIMR                      (*(volatile uint16_t*)(&_MBAR[0x8914]))
+#define MCF_PSC3_PSCISR                      (*(volatile uint16_t*)(&_MBAR[0x8914]))
+#define MCF_PSC3_PSCCTUR                     (*(volatile uint8_t *)(&_MBAR[0x8918]))
+#define MCF_PSC3_PSCCTLR                     (*(volatile uint8_t *)(&_MBAR[0x891C]))
+#define MCF_PSC3_PSCIP                       (*(volatile uint8_t *)(&_MBAR[0x8934]))
+#define MCF_PSC3_PSCOPSET                    (*(volatile uint8_t *)(&_MBAR[0x8938]))
+#define MCF_PSC3_PSCOPRESET                  (*(volatile uint8_t *)(&_MBAR[0x893C]))
+#define MCF_PSC3_PSCSICR                     (*(volatile uint8_t *)(&_MBAR[0x8940]))
+#define MCF_PSC3_PSCIRCR1                    (*(volatile uint8_t *)(&_MBAR[0x8944]))
+#define MCF_PSC3_PSCIRCR2                    (*(volatile uint8_t *)(&_MBAR[0x8948]))
+#define MCF_PSC3_PSCIRSDR                    (*(volatile uint8_t *)(&_MBAR[0x894C]))
+#define MCF_PSC3_PSCIRMDR                    (*(volatile uint8_t *)(&_MBAR[0x8950]))
+#define MCF_PSC3_PSCIRFDR                    (*(volatile uint8_t *)(&_MBAR[0x8954]))
+#define MCF_PSC3_PSCRFCNT                    (*(volatile uint16_t*)(&_MBAR[0x8958]))
+#define MCF_PSC3_PSCTFCNT                    (*(volatile uint16_t*)(&_MBAR[0x895C]))
+#define MCF_PSC3_PSCRFDR                     (*(volatile uint32_t*)(&_MBAR[0x8960]))
+#define MCF_PSC3_PSCRFSR                     (*(volatile uint16_t*)(&_MBAR[0x8964]))
+#define MCF_PSC3_PSCRFCR                     (*(volatile uint32_t*)(&_MBAR[0x8968]))
+#define MCF_PSC3_PSCRFAR                     (*(volatile uint16_t*)(&_MBAR[0x896E]))
+#define MCF_PSC3_PSCRFRP                     (*(volatile uint16_t*)(&_MBAR[0x8972]))
+#define MCF_PSC3_PSCRFWP                     (*(volatile uint16_t*)(&_MBAR[0x8976]))
+#define MCF_PSC3_PSCRLRFP                    (*(volatile uint16_t*)(&_MBAR[0x897A]))
+#define MCF_PSC3_PSCRLWFP                    (*(volatile uint16_t*)(&_MBAR[0x897E]))
+#define MCF_PSC3_PSCTFDR                     (*(volatile uint32_t*)(&_MBAR[0x8980]))
+#define MCF_PSC3_PSCTFSR                     (*(volatile uint16_t*)(&_MBAR[0x8984]))
+#define MCF_PSC3_PSCTFCR                     (*(volatile uint32_t*)(&_MBAR[0x8988]))
+#define MCF_PSC3_PSCTFAR                     (*(volatile uint16_t*)(&_MBAR[0x898E]))
+#define MCF_PSC3_PSCTFRP                     (*(volatile uint16_t*)(&_MBAR[0x8992]))
+#define MCF_PSC3_PSCTFWP                     (*(volatile uint16_t*)(&_MBAR[0x8996]))
+#define MCF_PSC3_PSCTLRFP                    (*(volatile uint16_t*)(&_MBAR[0x899A]))
+#define MCF_PSC3_PSCTLWFP                    (*(volatile uint16_t*)(&_MBAR[0x899E]))
+
+#define MCF_PSC_PSCMR(x)                     (*(volatile uint8_t *)(&_MBAR[0x8600 + ((x)*0x100)]))
+#define MCF_PSC_PSCCSR(x)                    (*(volatile uint8_t *)(&_MBAR[0x8604 + ((x)*0x100)]))
+#define MCF_PSC_PSCSR(x)                     (*(volatile uint16_t*)(&_MBAR[0x8604 + ((x)*0x100)]))
+#define MCF_PSC_PSCCR(x)                     (*(volatile uint8_t *)(&_MBAR[0x8608 + ((x)*0x100)]))
+#define MCF_PSC_PSCRB_8BIT(x)                (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)]))
+#define MCF_PSC_PSCTB_8BIT(x)                (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)]))
+#define MCF_PSC_PSCRB_16BIT(x)               (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)]))
+#define MCF_PSC_PSCTB_16BIT(x)               (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)]))
+#define MCF_PSC_PSCRB_AC97(x)                (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)]))
+#define MCF_PSC_PSCTB_AC97(x)                (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)]))
+#define MCF_PSC_PSCIPCR(x)                   (*(volatile uint8_t *)(&_MBAR[0x8610 + ((x)*0x100)]))
+#define MCF_PSC_PSCACR(x)                    (*(volatile uint8_t *)(&_MBAR[0x8610 + ((x)*0x100)]))
+#define MCF_PSC_PSCIMR(x)                    (*(volatile uint16_t*)(&_MBAR[0x8614 + ((x)*0x100)]))
+#define MCF_PSC_PSCISR(x)                    (*(volatile uint16_t*)(&_MBAR[0x8614 + ((x)*0x100)]))
+#define MCF_PSC_PSCCTUR(x)                   (*(volatile uint8_t *)(&_MBAR[0x8618 + ((x)*0x100)]))
+#define MCF_PSC_PSCCTLR(x)                   (*(volatile uint8_t *)(&_MBAR[0x861C + ((x)*0x100)]))
+#define MCF_PSC_PSCIP(x)                     (*(volatile uint8_t *)(&_MBAR[0x8634 + ((x)*0x100)]))
+#define MCF_PSC_PSCOPSET(x)                  (*(volatile uint8_t *)(&_MBAR[0x8638 + ((x)*0x100)]))
+#define MCF_PSC_PSCOPRESET(x)                (*(volatile uint8_t *)(&_MBAR[0x863C + ((x)*0x100)]))
+#define MCF_PSC_PSCSICR(x)                   (*(volatile uint8_t *)(&_MBAR[0x8640 + ((x)*0x100)]))
+#define MCF_PSC_PSCIRCR1(x)                  (*(volatile uint8_t *)(&_MBAR[0x8644 + ((x)*0x100)]))
+#define MCF_PSC_PSCIRCR2(x)                  (*(volatile uint8_t *)(&_MBAR[0x8648 + ((x)*0x100)]))
+#define MCF_PSC_PSCIRSDR(x)                  (*(volatile uint8_t *)(&_MBAR[0x864C + ((x)*0x100)]))
+#define MCF_PSC_PSCIRMDR(x)                  (*(volatile uint8_t *)(&_MBAR[0x8650 + ((x)*0x100)]))
+#define MCF_PSC_PSCIRFDR(x)                  (*(volatile uint8_t *)(&_MBAR[0x8654 + ((x)*0x100)]))
+#define MCF_PSC_PSCRFCNT(x)                  (*(volatile uint16_t*)(&_MBAR[0x8658 + ((x)*0x100)]))
+#define MCF_PSC_PSCTFCNT(x)                  (*(volatile uint16_t*)(&_MBAR[0x865C + ((x)*0x100)]))
+#define MCF_PSC_PSCRFDR(x)                   (*(volatile uint32_t*)(&_MBAR[0x8660 + ((x)*0x100)]))
+#define MCF_PSC_PSCRFSR(x)                   (*(volatile uint16_t*)(&_MBAR[0x8664 + ((x)*0x100)]))
+#define MCF_PSC_PSCRFCR(x)                   (*(volatile uint32_t*)(&_MBAR[0x8668 + ((x)*0x100)]))
+#define MCF_PSC_PSCRFAR(x)                   (*(volatile uint16_t*)(&_MBAR[0x866E + ((x)*0x100)]))
+#define MCF_PSC_PSCRFRP(x)                   (*(volatile uint16_t*)(&_MBAR[0x8672 + ((x)*0x100)]))
+#define MCF_PSC_PSCRFWP(x)                   (*(volatile uint16_t*)(&_MBAR[0x8676 + ((x)*0x100)]))
+#define MCF_PSC_PSCRLRFP(x)                  (*(volatile uint16_t*)(&_MBAR[0x867A + ((x)*0x100)]))
+#define MCF_PSC_PSCRLWFP(x)                  (*(volatile uint16_t*)(&_MBAR[0x867E + ((x)*0x100)]))
+#define MCF_PSC_PSCTFDR(x)                   (*(volatile uint32_t*)(&_MBAR[0x8680 + ((x)*0x100)]))
+#define MCF_PSC_PSCTFSR(x)                   (*(volatile uint16_t*)(&_MBAR[0x8684 + ((x)*0x100)]))
+#define MCF_PSC_PSCTFCR(x)                   (*(volatile uint32_t*)(&_MBAR[0x8688 + ((x)*0x100)]))
+#define MCF_PSC_PSCTFAR(x)                   (*(volatile uint16_t*)(&_MBAR[0x868E + ((x)*0x100)]))
+#define MCF_PSC_PSCTFRP(x)                   (*(volatile uint16_t*)(&_MBAR[0x8692 + ((x)*0x100)]))
+#define MCF_PSC_PSCTFWP(x)                   (*(volatile uint16_t*)(&_MBAR[0x8696 + ((x)*0x100)]))
+#define MCF_PSC_PSCTLRFP(x)                  (*(volatile uint16_t*)(&_MBAR[0x869A + ((x)*0x100)]))
+#define MCF_PSC_PSCTLWFP(x)                  (*(volatile uint16_t*)(&_MBAR[0x869E + ((x)*0x100)]))
+
+/* Bit definitions and macros for MCF_PSC_PSCMR */
+#define MCF_PSC_PSCMR_SB(x)                  (((x)&0xF)<<0)
+#define MCF_PSC_PSCMR_TXCTS                  (0x10)
+#define MCF_PSC_PSCMR_TXRTS                  (0x20)
+#define MCF_PSC_PSCMR_CM(x)                  (((x)&0x3)<<0x6)
+#define MCF_PSC_PSCMR_CM_NORMAL              (0)
+#define MCF_PSC_PSCMR_CM_ECHO                (0x40)
+#define MCF_PSC_PSCMR_CM_LOCAL_LOOP          (0x80)
+#define MCF_PSC_PSCMR_CM_REMOTE_LOOP         (0xC0)
+#define MCF_PSC_PSCMR_SB_STOP_BITS_1         (0x7)
+#define MCF_PSC_PSCMR_SB_STOP_BITS_15        (0x8)
+#define MCF_PSC_PSCMR_SB_STOP_BITS_2         (0xF)
+#define MCF_PSC_PSCMR_PM_MULTI_ADDR          (0x1C)
+#define MCF_PSC_PSCMR_PM_MULTI_DATA          (0x18)
+#define MCF_PSC_PSCMR_PM_NONE                (0x10)
+#define MCF_PSC_PSCMR_PM_FORCE_HI            (0xC)
+#define MCF_PSC_PSCMR_PM_FORCE_LO            (0x8)
+#define MCF_PSC_PSCMR_PM_ODD                 (0x4)
+#define MCF_PSC_PSCMR_PM_EVEN                (0)
+#define MCF_PSC_PSCMR_BC(x)                  (((x)&0x3)<<0)
+#define MCF_PSC_PSCMR_BC_5                   (0)
+#define MCF_PSC_PSCMR_BC_6                   (0x1)
+#define MCF_PSC_PSCMR_BC_7                   (0x2)
+#define MCF_PSC_PSCMR_BC_8                   (0x3)
+#define MCF_PSC_PSCMR_PT                     (0x4)
+#define MCF_PSC_PSCMR_PM(x)                  (((x)&0x3)<<0x3)
+#define MCF_PSC_PSCMR_ERR                    (0x20)
+#define MCF_PSC_PSCMR_RXIRQ_FU               (0x40)
+#define MCF_PSC_PSCMR_RXRTS                  (0x80)
+
+/* Bit definitions and macros for MCF_PSC_PSCCSR */
+#define MCF_PSC_PSCCSR_TCSEL(x)              (((x)&0xF)<<0)
+#define MCF_PSC_PSCCSR_RCSEL(x)              (((x)&0xF)<<0x4)
+#define MCF_PSC_PSCCSR_TCSEL_SYS_CLK         (0x0D)
+#define MCF_PSC_PSCCSR_TCSEL_CTM16           (0x0E)
+#define MCF_PSC_PSCCSR_TCSEL_CTM             (0x0F)
+#define MCF_PSC_PSCCSR_RCSEL_SYS_CLK         (0xD0)
+#define MCF_PSC_PSCCSR_RCSEL_CTM16           (0xE0)
+#define MCF_PSC_PSCCSR_RCSEL_CTM             (0xF0)
+
+/* Bit definitions and macros for MCF_PSC_PSCSR */
+#define MCF_PSC_PSCSR_ERR                    (0x40)
+#define MCF_PSC_PSCSR_CDE_DEOF               (0x80)
+#define MCF_PSC_PSCSR_RXRDY                  (0x100)
+#define MCF_PSC_PSCSR_FU                     (0x200)
+#define MCF_PSC_PSCSR_TXRDY                  (0x400)
+#define MCF_PSC_PSCSR_TXEMP_URERR            (0x800)
+#define MCF_PSC_PSCSR_OE                     (0x1000)
+#define MCF_PSC_PSCSR_PE_CRCERR              (0x2000)
+#define MCF_PSC_PSCSR_FE_PHYERR              (0x4000)
+#define MCF_PSC_PSCSR_RB_NEOF                (0x8000)
+
+/* Bit definitions and macros for MCF_PSC_PSCCR */
+#define MCF_PSC_PSCCR_RXC(x)                 (((x)&0x3)<<0)
+#define MCF_PSC_PSCCR_RX_ENABLED             (0x1)
+#define MCF_PSC_PSCCR_RX_DISABLED            (0x2)
+#define MCF_PSC_PSCCR_TXC(x)                 (((x)&0x3)<<0x2)
+#define MCF_PSC_PSCCR_TX_ENABLED             (0x4)
+#define MCF_PSC_PSCCR_TX_DISABLED            (0x8)
+#define MCF_PSC_PSCCR_MISC(x)                (((x)&0x7)<<0x4)
+#define MCF_PSC_PSCCR_NONE                   (0)
+#define MCF_PSC_PSCCR_RESET_MR               (0x10)
+#define MCF_PSC_PSCCR_RESET_RX               (0x20)
+#define MCF_PSC_PSCCR_RESET_TX               (0x30)
+#define MCF_PSC_PSCCR_RESET_ERROR            (0x40)
+#define MCF_PSC_PSCCR_RESET_BKCHGINT         (0x50)
+#define MCF_PSC_PSCCR_START_BREAK            (0x60)
+#define MCF_PSC_PSCCR_STOP_BREAK             (0x70)
+
+/* Bit definitions and macros for MCF_PSC_PSCRB_8BIT */
+#define MCF_PSC_PSCRB_8BIT_RB3(x)            (((x)&0xFF)<<0)
+#define MCF_PSC_PSCRB_8BIT_RB2(x)            (((x)&0xFF)<<0x8)
+#define MCF_PSC_PSCRB_8BIT_RB1(x)            (((x)&0xFF)<<0x10)
+#define MCF_PSC_PSCRB_8BIT_RB0(x)            (((x)&0xFF)<<0x18)
+
+/* Bit definitions and macros for MCF_PSC_PSCTB_8BIT */
+#define MCF_PSC_PSCTB_8BIT_TB3(x)            (((x)&0xFF)<<0)
+#define MCF_PSC_PSCTB_8BIT_TB2(x)            (((x)&0xFF)<<0x8)
+#define MCF_PSC_PSCTB_8BIT_TB1(x)            (((x)&0xFF)<<0x10)
+#define MCF_PSC_PSCTB_8BIT_TB0(x)            (((x)&0xFF)<<0x18)
+
+/* Bit definitions and macros for MCF_PSC_PSCRB_16BIT */
+#define MCF_PSC_PSCRB_16BIT_RB1(x)           (((x)&0xFFFF)<<0)
+#define MCF_PSC_PSCRB_16BIT_RB0(x)           (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_PSC_PSCTB_16BIT */
+#define MCF_PSC_PSCTB_16BIT_TB1(x)           (((x)&0xFFFF)<<0)
+#define MCF_PSC_PSCTB_16BIT_TB0(x)           (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_PSC_PSCRB_AC97 */
+#define MCF_PSC_PSCRB_AC97_SOF               (0x800)
+#define MCF_PSC_PSCRB_AC97_RB(x)             (((x)&0xFFFFF)<<0xC)
+
+/* Bit definitions and macros for MCF_PSC_PSCTB_AC97 */
+#define MCF_PSC_PSCTB_AC97_TB(x)             (((x)&0xFFFFF)<<0xC)
+
+/* Bit definitions and macros for MCF_PSC_PSCIPCR */
+#define MCF_PSC_PSCIPCR_RESERVED             (0xC)
+#define MCF_PSC_PSCIPCR_CTS                  (0xD)
+#define MCF_PSC_PSCIPCR_D_CTS                (0x1C)
+#define MCF_PSC_PSCIPCR_SYNC                 (0x8C)
+
+/* Bit definitions and macros for MCF_PSC_PSCACR */
+#define MCF_PSC_PSCACR_IEC0                  (0x1)
+
+/* Bit definitions and macros for MCF_PSC_PSCIMR */
+#define MCF_PSC_PSCIMR_ERR                   (0x40)
+#define MCF_PSC_PSCIMR_DEOF                  (0x80)
+#define MCF_PSC_PSCIMR_TXRDY                 (0x100)
+#define MCF_PSC_PSCIMR_RXRDY_FU              (0x200)
+#define MCF_PSC_PSCIMR_DB                    (0x400)
+#define MCF_PSC_PSCIMR_IPC                   (0x8000)
+
+/* Bit definitions and macros for MCF_PSC_PSCISR */
+#define MCF_PSC_PSCISR_ERR                   (0x40)
+#define MCF_PSC_PSCISR_DEOF                  (0x80)
+#define MCF_PSC_PSCISR_TXRDY                 (0x100)
+#define MCF_PSC_PSCISR_RXRDY_FU              (0x200)
+#define MCF_PSC_PSCISR_DB                    (0x400)
+#define MCF_PSC_PSCISR_IPC                   (0x8000)
+
+/* Bit definitions and macros for MCF_PSC_PSCCTUR */
+#define MCF_PSC_PSCCTUR_CT(x)                (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCCTLR */
+#define MCF_PSC_PSCCTLR_CT(x)                (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCIP */
+#define MCF_PSC_PSCIP_CTS                    (0x1)
+#define MCF_PSC_PSCIP_TGL                    (0x40)
+#define MCF_PSC_PSCIP_LPWR_B                 (0x80)
+
+/* Bit definitions and macros for MCF_PSC_PSCOPSET */
+#define MCF_PSC_PSCOPSET_RTS                 (0x1)
+
+/* Bit definitions and macros for MCF_PSC_PSCOPRESET */
+#define MCF_PSC_PSCOPRESET_RTS               (0x1)
+
+/* Bit definitions and macros for MCF_PSC_PSCSICR */
+#define MCF_PSC_PSCSICR_SIM(x)               (((x)&0x7)<<0)
+#define MCF_PSC_PSCSICR_SIM_UART             (0)
+#define MCF_PSC_PSCSICR_SIM_MODEM8           (0x1)
+#define MCF_PSC_PSCSICR_SIM_MODEM16          (0x2)
+#define MCF_PSC_PSCSICR_SIM_AC97             (0x3)
+#define MCF_PSC_PSCSICR_SIM_SIR              (0x4)
+#define MCF_PSC_PSCSICR_SIM_MIR              (0x5)
+#define MCF_PSC_PSCSICR_SIM_FIR              (0x6)
+#define MCF_PSC_PSCSICR_SHDIR                (0x10)
+#define MCF_PSC_PSCSICR_DTS1                 (0x20)
+#define MCF_PSC_PSCSICR_AWR                  (0x40)
+#define MCF_PSC_PSCSICR_ACRB                 (0x80)
+
+/* Bit definitions and macros for MCF_PSC_PSCIRCR1 */
+#define MCF_PSC_PSCIRCR1_SPUL                (0x1)
+#define MCF_PSC_PSCIRCR1_SIPEN               (0x2)
+#define MCF_PSC_PSCIRCR1_FD                  (0x4)
+
+/* Bit definitions and macros for MCF_PSC_PSCIRCR2 */
+#define MCF_PSC_PSCIRCR2_NXTEOF              (0x1)
+#define MCF_PSC_PSCIRCR2_ABORT               (0x2)
+#define MCF_PSC_PSCIRCR2_SIPREQ              (0x4)
+
+/* Bit definitions and macros for MCF_PSC_PSCIRSDR */
+#define MCF_PSC_PSCIRSDR_IRSTIM(x)           (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCIRMDR */
+#define MCF_PSC_PSCIRMDR_M_FDIV(x)           (((x)&0x7F)<<0)
+#define MCF_PSC_PSCIRMDR_FREQ                (0x80)
+
+/* Bit definitions and macros for MCF_PSC_PSCIRFDR */
+#define MCF_PSC_PSCIRFDR_F_FDIV(x)           (((x)&0xF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCRFCNT */
+#define MCF_PSC_PSCRFCNT_CNT(x)              (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCTFCNT */
+#define MCF_PSC_PSCTFCNT_CNT(x)              (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCRFDR */
+#define MCF_PSC_PSCRFDR_DATA(x)              (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCRFSR */
+#define MCF_PSC_PSCRFSR_EMT                  (0x1)
+#define MCF_PSC_PSCRFSR_ALARM                (0x2)
+#define MCF_PSC_PSCRFSR_FU                   (0x4)
+#define MCF_PSC_PSCRFSR_FRMRDY               (0x8)
+#define MCF_PSC_PSCRFSR_OF                   (0x10)
+#define MCF_PSC_PSCRFSR_UF                   (0x20)
+#define MCF_PSC_PSCRFSR_RXW                  (0x40)
+#define MCF_PSC_PSCRFSR_FAE                  (0x80)
+#define MCF_PSC_PSCRFSR_FRM(x)               (((x)&0xF)<<0x8)
+#define MCF_PSC_PSCRFSR_FRM_BYTE0            (0x800)
+#define MCF_PSC_PSCRFSR_FRM_BYTE1            (0x400)
+#define MCF_PSC_PSCRFSR_FRM_BYTE2            (0x200)
+#define MCF_PSC_PSCRFSR_FRM_BYTE3            (0x100)
+#define MCF_PSC_PSCRFSR_TAG(x)               (((x)&0x3)<<0xC)
+#define MCF_PSC_PSCRFSR_TXW                  (0x4000)
+#define MCF_PSC_PSCRFSR_IP                   (0x8000)
+
+/* Bit definitions and macros for MCF_PSC_PSCRFCR */
+#define MCF_PSC_PSCRFCR_CNTR(x)              (((x)&0xFFFF)<<0)
+#define MCF_PSC_PSCRFCR_TXW_MSK              (0x40000)
+#define MCF_PSC_PSCRFCR_OF_MSK               (0x80000)
+#define MCF_PSC_PSCRFCR_UF_MSK               (0x100000)
+#define MCF_PSC_PSCRFCR_RXW_MSK              (0x200000)
+#define MCF_PSC_PSCRFCR_FAE_MSK              (0x400000)
+#define MCF_PSC_PSCRFCR_IP_MSK               (0x800000)
+#define MCF_PSC_PSCRFCR_GR(x)                (((x)&0x7)<<0x18)
+#define MCF_PSC_PSCRFCR_FRMEN                (0x8000000)
+#define MCF_PSC_PSCRFCR_TIMER                (0x10000000)
+
+/* Bit definitions and macros for MCF_PSC_PSCRFAR */
+#define MCF_PSC_PSCRFAR_ALARM(x)             (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCRFRP */
+#define MCF_PSC_PSCRFRP_READ(x)              (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCRFWP */
+#define MCF_PSC_PSCRFWP_WRITE(x)             (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCRLRFP */
+#define MCF_PSC_PSCRLRFP_LRFP(x)             (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCRLWFP */
+#define MCF_PSC_PSCRLWFP_LWFP(x)             (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCTFDR */
+#define MCF_PSC_PSCTFDR_DATA(x)              (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCTFSR */
+#define MCF_PSC_PSCTFSR_EMT                  (0x1)
+#define MCF_PSC_PSCTFSR_ALARM                (0x2)
+#define MCF_PSC_PSCTFSR_FU                   (0x4)
+#define MCF_PSC_PSCTFSR_FRMRDY               (0x8)
+#define MCF_PSC_PSCTFSR_OF                   (0x10)
+#define MCF_PSC_PSCTFSR_UF                   (0x20)
+#define MCF_PSC_PSCTFSR_RXW                  (0x40)
+#define MCF_PSC_PSCTFSR_FAE                  (0x80)
+#define MCF_PSC_PSCTFSR_FRM(x)               (((x)&0xF)<<0x8)
+#define MCF_PSC_PSCTFSR_FRM_BYTE0            (0x800)
+#define MCF_PSC_PSCTFSR_FRM_BYTE1            (0x400)
+#define MCF_PSC_PSCTFSR_FRM_BYTE2            (0x200)
+#define MCF_PSC_PSCTFSR_FRM_BYTE3            (0x100)
+#define MCF_PSC_PSCTFSR_TAG(x)               (((x)&0x3)<<0xC)
+#define MCF_PSC_PSCTFSR_TXW                  (0x4000)
+#define MCF_PSC_PSCTFSR_IP                   (0x8000)
+
+/* Bit definitions and macros for MCF_PSC_PSCTFCR */
+#define MCF_PSC_PSCTFCR_CNTR(x)              (((x)&0xFFFF)<<0)
+#define MCF_PSC_PSCTFCR_TXW_MSK              (0x40000)
+#define MCF_PSC_PSCTFCR_OF_MSK               (0x80000)
+#define MCF_PSC_PSCTFCR_UF_MSK               (0x100000)
+#define MCF_PSC_PSCTFCR_RXW_MSK              (0x200000)
+#define MCF_PSC_PSCTFCR_FAE_MSK              (0x400000)
+#define MCF_PSC_PSCTFCR_IP_MSK               (0x800000)
+#define MCF_PSC_PSCTFCR_GR(x)                (((x)&0x7)<<0x18)
+#define MCF_PSC_PSCTFCR_FRMEN                (0x8000000)
+#define MCF_PSC_PSCTFCR_TIMER                (0x10000000)
+#define MCF_PSC_PSCTFCR_WFR                  (0x20000000)
+
+/* Bit definitions and macros for MCF_PSC_PSCTFAR */
+#define MCF_PSC_PSCTFAR_ALARM(x)             (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCTFRP */
+#define MCF_PSC_PSCTFRP_READ(x)              (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCTFWP */
+#define MCF_PSC_PSCTFWP_WRITE(x)             (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCTLRFP */
+#define MCF_PSC_PSCTLRFP_LRFP(x)             (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCTLWFP */
+#define MCF_PSC_PSCTLWFP_LWFP(x)             (((x)&0x1FF)<<0)
+
+
+#endif /* __MCF5475_PSC_H__ */
--- a/tos/fpga_test/include/MCF5475_SDRAMC.h
+++ b/tos/fpga_test/include/MCF5475_SDRAMC.h
@@ -0,0 +1,106 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_SDRAMC_H__
+#define __MCF5475_SDRAMC_H__
+
+
+/*********************************************************************
+*
+* Synchronous DRAM Controller (SDRAMC)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_SDRAMC_SDRAMDS                   (*(volatile uint32_t*)(&_MBAR[0x4]))
+#define MCF_SDRAMC_CS0CFG                    (*(volatile uint32_t*)(&_MBAR[0x20]))
+#define MCF_SDRAMC_CS1CFG                    (*(volatile uint32_t*)(&_MBAR[0x24]))
+#define MCF_SDRAMC_CS2CFG                    (*(volatile uint32_t*)(&_MBAR[0x28]))
+#define MCF_SDRAMC_CS3CFG                    (*(volatile uint32_t*)(&_MBAR[0x2C]))
+#define MCF_SDRAMC_SDMR                      (*(volatile uint32_t*)(&_MBAR[0x100]))
+#define MCF_SDRAMC_SDCR                      (*(volatile uint32_t*)(&_MBAR[0x104]))
+#define MCF_SDRAMC_SDCFG1                    (*(volatile uint32_t*)(&_MBAR[0x108]))
+#define MCF_SDRAMC_SDCFG2                    (*(volatile uint32_t*)(&_MBAR[0x10C]))
+#define MCF_SDRAMC_CSCFG(x)                  (*(volatile uint32_t*)(&_MBAR[0x20 + ((x)*0x4)]))
+
+
+/* Bit definitions and macros for MCF_SDRAMC_SDRAMDS */
+#define MCF_SDRAMC_SDRAMDS_SB_D(x)           (((x)&0x3)<<0)
+#define MCF_SDRAMC_SDRAMDS_SB_S(x)           (((x)&0x3)<<0x2)
+#define MCF_SDRAMC_SDRAMDS_SB_A(x)           (((x)&0x3)<<0x4)
+#define MCF_SDRAMC_SDRAMDS_SB_C(x)           (((x)&0x3)<<0x6)
+#define MCF_SDRAMC_SDRAMDS_SB_E(x)           (((x)&0x3)<<0x8)
+#define MCF_SDRAMC_SDRAMDS_DRIVE_24MA        (0)
+#define MCF_SDRAMC_SDRAMDS_DRIVE_16MA        (0x1)
+#define MCF_SDRAMC_SDRAMDS_DRIVE_8MA         (0x2)
+#define MCF_SDRAMC_SDRAMDS_DRIVE_NONE        (0x3)
+
+/* Bit definitions and macros for MCF_SDRAMC_CSCFG */
+#define MCF_SDRAMC_CSCFG_CSSZ(x)             (((x)&0x1F)<<0)
+#define MCF_SDRAMC_CSCFG_CSSZ_DISABLED       (0)
+#define MCF_SDRAMC_CSCFG_CSSZ_1MBYTE         (0x13)
+#define MCF_SDRAMC_CSCFG_CSSZ_2MBYTE         (0x14)
+#define MCF_SDRAMC_CSCFG_CSSZ_4MBYTE         (0x15)
+#define MCF_SDRAMC_CSCFG_CSSZ_8MBYTE         (0x16)
+#define MCF_SDRAMC_CSCFG_CSSZ_16MBYTE        (0x17)
+#define MCF_SDRAMC_CSCFG_CSSZ_32MBYTE        (0x18)
+#define MCF_SDRAMC_CSCFG_CSSZ_64MBYTE        (0x19)
+#define MCF_SDRAMC_CSCFG_CSSZ_128MBYTE       (0x1A)
+#define MCF_SDRAMC_CSCFG_CSSZ_256MBYTE       (0x1B)
+#define MCF_SDRAMC_CSCFG_CSSZ_512MBYTE       (0x1C)
+#define MCF_SDRAMC_CSCFG_CSSZ_1GBYTE         (0x1D)
+#define MCF_SDRAMC_CSCFG_CSSZ_2GBYTE         (0x1E)
+#define MCF_SDRAMC_CSCFG_CSSZ_4GBYTE         (0x1F)
+#define MCF_SDRAMC_CSCFG_CSBA(x)             (((x)&0xFFF)<<0x14)
+#define MCF_SDRAMC_CSCFG_BA(x)               ((x)&0xFFF00000)
+
+/* Bit definitions and macros for MCF_SDRAMC_SDMR */
+#define MCF_SDRAMC_SDMR_CMD                  (0x10000)
+#define MCF_SDRAMC_SDMR_AD(x)                (((x)&0xFFF)<<0x12)
+#define MCF_SDRAMC_SDMR_BNKAD(x)             (((x)&0x3)<<0x1E)
+#define MCF_SDRAMC_SDMR_BK_LMR               (0)
+#define MCF_SDRAMC_SDMR_BK_LEMR              (0x40000000)
+
+/* Bit definitions and macros for MCF_SDRAMC_SDCR */
+#define MCF_SDRAMC_SDCR_IPALL                (0x2)
+#define MCF_SDRAMC_SDCR_IREF                 (0x4)
+#define MCF_SDRAMC_SDCR_BUFF                 (0x10)
+#define MCF_SDRAMC_SDCR_DQS_OE(x)            (((x)&0xF)<<0x8)
+#define MCF_SDRAMC_SDCR_RCNT(x)              (((x)&0x3F)<<0x10)
+#define MCF_SDRAMC_SDCR_DRIVE                (0x400000)
+#define MCF_SDRAMC_SDCR_AP                   (0x800000)
+#define MCF_SDRAMC_SDCR_MUX(x)               (((x)&0x3)<<0x18)
+#define MCF_SDRAMC_SDCR_REF                  (0x10000000)
+#define MCF_SDRAMC_SDCR_DDR                  (0x20000000)
+#define MCF_SDRAMC_SDCR_CKE                  (0x40000000)
+#define MCF_SDRAMC_SDCR_MODE_EN              (0x80000000)
+
+/* Bit definitions and macros for MCF_SDRAMC_SDCFG1 */
+#define MCF_SDRAMC_SDCFG1_WTLAT(x)           (((x)&0x7)<<0x4)
+#define MCF_SDRAMC_SDCFG1_REF2ACT(x)         (((x)&0xF)<<0x8)
+#define MCF_SDRAMC_SDCFG1_PRE2ACT(x)         (((x)&0x7)<<0xC)
+#define MCF_SDRAMC_SDCFG1_ACT2RW(x)          (((x)&0x7)<<0x10)
+#define MCF_SDRAMC_SDCFG1_RDLAT(x)           (((x)&0xF)<<0x14)
+#define MCF_SDRAMC_SDCFG1_SWT2RD(x)          (((x)&0x7)<<0x18)
+#define MCF_SDRAMC_SDCFG1_SRD2RW(x)          (((x)&0xF)<<0x1C)
+
+/* Bit definitions and macros for MCF_SDRAMC_SDCFG2 */
+#define MCF_SDRAMC_SDCFG2_BL(x)              (((x)&0xF)<<0x10)
+#define MCF_SDRAMC_SDCFG2_BRD2WT(x)          (((x)&0xF)<<0x14)
+#define MCF_SDRAMC_SDCFG2_BWT2RW(x)          (((x)&0xF)<<0x18)
+#define MCF_SDRAMC_SDCFG2_BRD2PRE(x)         (((x)&0xF)<<0x1C)
+
+
+#endif /* __MCF5475_SDRAMC_H__ */
--- a/tos/fpga_test/include/MCF5475_SEC.h
+++ b/tos/fpga_test/include/MCF5475_SEC.h
@@ -0,0 +1,398 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_SEC_H__
+#define __MCF5475_SEC_H__
+
+
+/*********************************************************************
+*
+* Integrated Security Engine (SEC)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_SEC_EUACRH                       (*(volatile uint32_t*)(&_MBAR[0x21000]))
+#define MCF_SEC_EUACRL                       (*(volatile uint32_t*)(&_MBAR[0x21004]))
+#define MCF_SEC_SIMRH                        (*(volatile uint32_t*)(&_MBAR[0x21008]))
+#define MCF_SEC_SIMRL                        (*(volatile uint32_t*)(&_MBAR[0x2100C]))
+#define MCF_SEC_SISRH                        (*(volatile uint32_t*)(&_MBAR[0x21010]))
+#define MCF_SEC_SISRL                        (*(volatile uint32_t*)(&_MBAR[0x21014]))
+#define MCF_SEC_SICRH                        (*(volatile uint32_t*)(&_MBAR[0x21018]))
+#define MCF_SEC_SICRL                        (*(volatile uint32_t*)(&_MBAR[0x2101C]))
+#define MCF_SEC_SIDR                         (*(volatile uint32_t*)(&_MBAR[0x21020]))
+#define MCF_SEC_EUASRH                       (*(volatile uint32_t*)(&_MBAR[0x21028]))
+#define MCF_SEC_EUASRL                       (*(volatile uint32_t*)(&_MBAR[0x2102C]))
+#define MCF_SEC_SMCR                         (*(volatile uint32_t*)(&_MBAR[0x21030]))
+#define MCF_SEC_MEAR                         (*(volatile uint32_t*)(&_MBAR[0x21038]))
+#define MCF_SEC_CCCR0                        (*(volatile uint32_t*)(&_MBAR[0x2200C]))
+#define MCF_SEC_CCPSRH0                      (*(volatile uint32_t*)(&_MBAR[0x22010]))
+#define MCF_SEC_CCPSRL0                      (*(volatile uint32_t*)(&_MBAR[0x22014]))
+#define MCF_SEC_CDPR0                        (*(volatile uint32_t*)(&_MBAR[0x22044]))
+#define MCF_SEC_FR0                          (*(volatile uint32_t*)(&_MBAR[0x2204C]))
+#define MCF_SEC_CCCR1                        (*(volatile uint32_t*)(&_MBAR[0x2300C]))
+#define MCF_SEC_CCPSRH1                      (*(volatile uint32_t*)(&_MBAR[0x23010]))
+#define MCF_SEC_CCPSRL1                      (*(volatile uint32_t*)(&_MBAR[0x23014]))
+#define MCF_SEC_CDPR1                        (*(volatile uint32_t*)(&_MBAR[0x23044]))
+#define MCF_SEC_FR1                          (*(volatile uint32_t*)(&_MBAR[0x2304C]))
+#define MCF_SEC_AFRCR                        (*(volatile uint32_t*)(&_MBAR[0x28018]))
+#define MCF_SEC_AFSR                         (*(volatile uint32_t*)(&_MBAR[0x28028]))
+#define MCF_SEC_AFISR                        (*(volatile uint32_t*)(&_MBAR[0x28030]))
+#define MCF_SEC_AFIMR                        (*(volatile uint32_t*)(&_MBAR[0x28038]))
+#define MCF_SEC_DRCR                         (*(volatile uint32_t*)(&_MBAR[0x2A018]))
+#define MCF_SEC_DSR                          (*(volatile uint32_t*)(&_MBAR[0x2A028]))
+#define MCF_SEC_DISR                         (*(volatile uint32_t*)(&_MBAR[0x2A030]))
+#define MCF_SEC_DIMR                         (*(volatile uint32_t*)(&_MBAR[0x2A038]))
+#define MCF_SEC_MDRCR                        (*(volatile uint32_t*)(&_MBAR[0x2C018]))
+#define MCF_SEC_MDSR                         (*(volatile uint32_t*)(&_MBAR[0x2C028]))
+#define MCF_SEC_MDISR                        (*(volatile uint32_t*)(&_MBAR[0x2C030]))
+#define MCF_SEC_MDIMR                        (*(volatile uint32_t*)(&_MBAR[0x2C038]))
+#define MCF_SEC_RNGRCR                       (*(volatile uint32_t*)(&_MBAR[0x2E018]))
+#define MCF_SEC_RNGSR                        (*(volatile uint32_t*)(&_MBAR[0x2E028]))
+#define MCF_SEC_RNGISR                       (*(volatile uint32_t*)(&_MBAR[0x2E030]))
+#define MCF_SEC_RNGIMR                       (*(volatile uint32_t*)(&_MBAR[0x2E038]))
+#define MCF_SEC_AESRCR                       (*(volatile uint32_t*)(&_MBAR[0x32018]))
+#define MCF_SEC_AESSR                        (*(volatile uint32_t*)(&_MBAR[0x32028]))
+#define MCF_SEC_AESISR                       (*(volatile uint32_t*)(&_MBAR[0x32030]))
+#define MCF_SEC_AESIMR                       (*(volatile uint32_t*)(&_MBAR[0x32038]))
+#define MCF_SEC_CCCRn(x)                     (*(volatile uint32_t*)(&_MBAR[0x2200C + ((x)*0x1000)]))
+#define MCF_SEC_CCPSRHn(x)                   (*(volatile uint32_t*)(&_MBAR[0x22010 + ((x)*0x1000)]))
+#define MCF_SEC_CCPSRLn(x)                   (*(volatile uint32_t*)(&_MBAR[0x22014 + ((x)*0x1000)]))
+#define MCF_SEC_CDPRn(x)                     (*(volatile uint32_t*)(&_MBAR[0x22044 + ((x)*0x1000)]))
+#define MCF_SEC_FRn(x)                       (*(volatile uint32_t*)(&_MBAR[0x2204C + ((x)*0x1000)]))
+
+
+/* Bit definitions and macros for MCF_SEC_EUACRH */
+#define MCF_SEC_EUACRH_AFEU(x)               (((x)&0xF)<<0)
+#define MCF_SEC_EUACRH_AFFEU_NOASSIGN        (0)
+#define MCF_SEC_EUACRH_AFFEU_CHA0            (0x1)
+#define MCF_SEC_EUACRH_AFFEU_CHA1            (0x2)
+#define MCF_SEC_EUACRH_MDEU(x)               (((x)&0xF)<<0x8)
+#define MCF_SEC_EUACRH_MDEU_NOASSIGN         (0)
+#define MCF_SEC_EUACRH_MDEU_CHA0             (0x100)
+#define MCF_SEC_EUACRH_MDEU_CHA1             (0x200)
+#define MCF_SEC_EUACRH_RNG(x)                (((x)&0xF)<<0x18)
+#define MCF_SEC_EUACRH_RNG_NOASSIGN          (0)
+#define MCF_SEC_EUACRH_RNG_CHA0              (0x1000000)
+#define MCF_SEC_EUACRH_RNG_CHA1              (0x2000000)
+
+/* Bit definitions and macros for MCF_SEC_EUACRL */
+#define MCF_SEC_EUACRL_AESU(x)               (((x)&0xF)<<0x10)
+#define MCF_SEC_EUACRL_AESU_NOASSIGN         (0)
+#define MCF_SEC_EUACRL_AESU_CHA0             (0x10000)
+#define MCF_SEC_EUACRL_AESU_CHA1             (0x20000)
+#define MCF_SEC_EUACRL_DEU(x)                (((x)&0xF)<<0x18)
+
+/* Bit definitions and macros for MCF_SEC_SIMRH */
+#define MCF_SEC_SIMRH_AERR                   (0x8000000)
+#define MCF_SEC_SIMRH_CHA_0_DN               (0x10000000)
+#define MCF_SEC_SIMRH_CHA_0_ERR              (0x20000000)
+#define MCF_SEC_SIMRH_CHA_1_DN               (0x40000000)
+#define MCF_SEC_SIMRH_CHA_1_ERR              (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_SIMRL */
+#define MCF_SEC_SIMRL_TEA                    (0x40)
+#define MCF_SEC_SIMRL_DEU_DN                 (0x100)
+#define MCF_SEC_SIMRL_DEU_ERR                (0x200)
+#define MCF_SEC_SIMRL_AESU_DN                (0x1000)
+#define MCF_SEC_SIMRL_AESU_ERR               (0x2000)
+#define MCF_SEC_SIMRL_MDEU_DN                (0x10000)
+#define MCF_SEC_SIMRL_MDEU_ERR               (0x20000)
+#define MCF_SEC_SIMRL_AFEU_DN                (0x100000)
+#define MCF_SEC_SIMRL_AFEU_ERR               (0x200000)
+#define MCF_SEC_SIMRL_RNG_DN                 (0x1000000)
+#define MCF_SEC_SIMRL_RNG_ERR                (0x2000000)
+
+/* Bit definitions and macros for MCF_SEC_SISRH */
+#define MCF_SEC_SISRH_AERR                   (0x8000000)
+#define MCF_SEC_SISRH_CHA_0_DN               (0x10000000)
+#define MCF_SEC_SISRH_CHA_0_ERR              (0x20000000)
+#define MCF_SEC_SISRH_CHA_1_DN               (0x40000000)
+#define MCF_SEC_SISRH_CHA_1_ERR              (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_SISRL */
+#define MCF_SEC_SISRL_TEA                    (0x40)
+#define MCF_SEC_SISRL_DEU_DN                 (0x100)
+#define MCF_SEC_SISRL_DEU_ERR                (0x200)
+#define MCF_SEC_SISRL_AESU_DN                (0x1000)
+#define MCF_SEC_SISRL_AESU_ERR               (0x2000)
+#define MCF_SEC_SISRL_MDEU_DN                (0x10000)
+#define MCF_SEC_SISRL_MDEU_ERR               (0x20000)
+#define MCF_SEC_SISRL_AFEU_DN                (0x100000)
+#define MCF_SEC_SISRL_AFEU_ERR               (0x200000)
+#define MCF_SEC_SISRL_RNG_DN                 (0x1000000)
+#define MCF_SEC_SISRL_RNG_ERR                (0x2000000)
+
+/* Bit definitions and macros for MCF_SEC_SICRH */
+#define MCF_SEC_SICRH_AERR                   (0x8000000)
+#define MCF_SEC_SICRH_CHA_0_DN               (0x10000000)
+#define MCF_SEC_SICRH_CHA_0_ERR              (0x20000000)
+#define MCF_SEC_SICRH_CHA_1_DN               (0x40000000)
+#define MCF_SEC_SICRH_CHA_1_ERR              (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_SICRL */
+#define MCF_SEC_SICRL_TEA                    (0x40)
+#define MCF_SEC_SICRL_DEU_DN                 (0x100)
+#define MCF_SEC_SICRL_DEU_ERR                (0x200)
+#define MCF_SEC_SICRL_AESU_DN                (0x1000)
+#define MCF_SEC_SICRL_AESU_ERR               (0x2000)
+#define MCF_SEC_SICRL_MDEU_DN                (0x10000)
+#define MCF_SEC_SICRL_MDEU_ERR               (0x20000)
+#define MCF_SEC_SICRL_AFEU_DN                (0x100000)
+#define MCF_SEC_SICRL_AFEU_ERR               (0x200000)
+#define MCF_SEC_SICRL_RNG_DN                 (0x1000000)
+#define MCF_SEC_SICRL_RNG_ERR                (0x2000000)
+
+/* Bit definitions and macros for MCF_SEC_SIDR */
+#define MCF_SEC_SIDR_VERSION(x)              (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_SEC_EUASRH */
+#define MCF_SEC_EUASRH_AFEU(x)               (((x)&0xF)<<0)
+#define MCF_SEC_EUASRH_MDEU(x)               (((x)&0xF)<<0x8)
+#define MCF_SEC_EUASRH_RNG(x)                (((x)&0xF)<<0x18)
+
+/* Bit definitions and macros for MCF_SEC_EUASRL */
+#define MCF_SEC_EUASRL_AESU(x)               (((x)&0xF)<<0x10)
+#define MCF_SEC_EUASRL_DEU(x)                (((x)&0xF)<<0x18)
+
+/* Bit definitions and macros for MCF_SEC_SMCR */
+#define MCF_SEC_SMCR_CURR_CHAN(x)            (((x)&0xF)<<0x4)
+#define MCF_SEC_SMCR_CURR_CHAN_1             (0x10)
+#define MCF_SEC_SMCR_CURR_CHAN_2             (0x20)
+#define MCF_SEC_SMCR_SWR                     (0x1000000)
+
+/* Bit definitions and macros for MCF_SEC_MEAR */
+#define MCF_SEC_MEAR_ADDRESS(x)              (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_SEC_CCCRn */
+#define MCF_SEC_CCCRn_RST                    (0x1)
+#define MCF_SEC_CCCRn_CDIE                   (0x2)
+#define MCF_SEC_CCCRn_NT                     (0x4)
+#define MCF_SEC_CCCRn_NE                     (0x8)
+#define MCF_SEC_CCCRn_WE                     (0x10)
+#define MCF_SEC_CCCRn_BURST_SIZE(x)          (((x)&0x7)<<0x8)
+#define MCF_SEC_CCCRn_BURST_SIZE_2           (0)
+#define MCF_SEC_CCCRn_BURST_SIZE_8           (0x100)
+#define MCF_SEC_CCCRn_BURST_SIZE_16          (0x200)
+#define MCF_SEC_CCCRn_BURST_SIZE_24          (0x300)
+#define MCF_SEC_CCCRn_BURST_SIZE_32          (0x400)
+#define MCF_SEC_CCCRn_BURST_SIZE_40          (0x500)
+#define MCF_SEC_CCCRn_BURST_SIZE_48          (0x600)
+#define MCF_SEC_CCCRn_BURST_SIZE_56          (0x700)
+
+/* Bit definitions and macros for MCF_SEC_CCPSRHn */
+#define MCF_SEC_CCPSRHn_STATE(x)             (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_SEC_CCPSRLn */
+#define MCF_SEC_CCPSRLn_PAIR_PTR(x)          (((x)&0xFF)<<0)
+#define MCF_SEC_CCPSRLn_EUERR                (0x100)
+#define MCF_SEC_CCPSRLn_SERR                 (0x200)
+#define MCF_SEC_CCPSRLn_DERR                 (0x400)
+#define MCF_SEC_CCPSRLn_PERR                 (0x1000)
+#define MCF_SEC_CCPSRLn_TEA                  (0x2000)
+#define MCF_SEC_CCPSRLn_SD                   (0x10000)
+#define MCF_SEC_CCPSRLn_PD                   (0x20000)
+#define MCF_SEC_CCPSRLn_SRD                  (0x40000)
+#define MCF_SEC_CCPSRLn_PRD                  (0x80000)
+#define MCF_SEC_CCPSRLn_SG                   (0x100000)
+#define MCF_SEC_CCPSRLn_PG                   (0x200000)
+#define MCF_SEC_CCPSRLn_SR                   (0x400000)
+#define MCF_SEC_CCPSRLn_PR                   (0x800000)
+#define MCF_SEC_CCPSRLn_MO                   (0x1000000)
+#define MCF_SEC_CCPSRLn_MI                   (0x2000000)
+#define MCF_SEC_CCPSRLn_STAT                 (0x4000000)
+
+/* Bit definitions and macros for MCF_SEC_CDPRn */
+#define MCF_SEC_CDPRn_CDP(x)                 (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_SEC_FRn */
+#define MCF_SEC_FRn_FETCH_ADDR(x)            (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_SEC_AFRCR */
+#define MCF_SEC_AFRCR_SR                     (0x1000000)
+#define MCF_SEC_AFRCR_MI                     (0x2000000)
+#define MCF_SEC_AFRCR_RI                     (0x4000000)
+
+/* Bit definitions and macros for MCF_SEC_AFSR */
+#define MCF_SEC_AFSR_RD                      (0x1000000)
+#define MCF_SEC_AFSR_ID                      (0x2000000)
+#define MCF_SEC_AFSR_IE                      (0x4000000)
+#define MCF_SEC_AFSR_OFR                     (0x8000000)
+#define MCF_SEC_AFSR_IFW                     (0x10000000)
+#define MCF_SEC_AFSR_HALT                    (0x20000000)
+
+/* Bit definitions and macros for MCF_SEC_AFISR */
+#define MCF_SEC_AFISR_DSE                    (0x10000)
+#define MCF_SEC_AFISR_KSE                    (0x20000)
+#define MCF_SEC_AFISR_CE                     (0x40000)
+#define MCF_SEC_AFISR_ERE                    (0x80000)
+#define MCF_SEC_AFISR_IE                     (0x100000)
+#define MCF_SEC_AFISR_OFU                    (0x2000000)
+#define MCF_SEC_AFISR_IFO                    (0x4000000)
+#define MCF_SEC_AFISR_IFE                    (0x10000000)
+#define MCF_SEC_AFISR_OFE                    (0x20000000)
+#define MCF_SEC_AFISR_AE                     (0x40000000)
+#define MCF_SEC_AFISR_ME                     (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_AFIMR */
+#define MCF_SEC_AFIMR_DSE                    (0x10000)
+#define MCF_SEC_AFIMR_KSE                    (0x20000)
+#define MCF_SEC_AFIMR_CE                     (0x40000)
+#define MCF_SEC_AFIMR_ERE                    (0x80000)
+#define MCF_SEC_AFIMR_IE                     (0x100000)
+#define MCF_SEC_AFIMR_OFU                    (0x2000000)
+#define MCF_SEC_AFIMR_IFO                    (0x4000000)
+#define MCF_SEC_AFIMR_IFE                    (0x10000000)
+#define MCF_SEC_AFIMR_OFE                    (0x20000000)
+#define MCF_SEC_AFIMR_AE                     (0x40000000)
+#define MCF_SEC_AFIMR_ME                     (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_DRCR */
+#define MCF_SEC_DRCR_SR                      (0x1000000)
+#define MCF_SEC_DRCR_MI                      (0x2000000)
+#define MCF_SEC_DRCR_RI                      (0x4000000)
+
+/* Bit definitions and macros for MCF_SEC_DSR */
+#define MCF_SEC_DSR_RD                       (0x1000000)
+#define MCF_SEC_DSR_ID                       (0x2000000)
+#define MCF_SEC_DSR_IE                       (0x4000000)
+#define MCF_SEC_DSR_OFR                      (0x8000000)
+#define MCF_SEC_DSR_IFW                      (0x10000000)
+#define MCF_SEC_DSR_HALT                     (0x20000000)
+
+/* Bit definitions and macros for MCF_SEC_DISR */
+#define MCF_SEC_DISR_DSE                     (0x10000)
+#define MCF_SEC_DISR_KSE                     (0x20000)
+#define MCF_SEC_DISR_CE                      (0x40000)
+#define MCF_SEC_DISR_ERE                     (0x80000)
+#define MCF_SEC_DISR_IE                      (0x100000)
+#define MCF_SEC_DISR_KPE                     (0x200000)
+#define MCF_SEC_DISR_OFU                     (0x2000000)
+#define MCF_SEC_DISR_IFO                     (0x4000000)
+#define MCF_SEC_DISR_IFE                     (0x10000000)
+#define MCF_SEC_DISR_OFE                     (0x20000000)
+#define MCF_SEC_DISR_AE                      (0x40000000)
+#define MCF_SEC_DISR_ME                      (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_DIMR */
+#define MCF_SEC_DIMR_DSE                     (0x10000)
+#define MCF_SEC_DIMR_KSE                     (0x20000)
+#define MCF_SEC_DIMR_CE                      (0x40000)
+#define MCF_SEC_DIMR_ERE                     (0x80000)
+#define MCF_SEC_DIMR_IE                      (0x100000)
+#define MCF_SEC_DIMR_KPE                     (0x200000)
+#define MCF_SEC_DIMR_OFU                     (0x2000000)
+#define MCF_SEC_DIMR_IFO                     (0x4000000)
+#define MCF_SEC_DIMR_IFE                     (0x10000000)
+#define MCF_SEC_DIMR_OFE                     (0x20000000)
+#define MCF_SEC_DIMR_AE                      (0x40000000)
+#define MCF_SEC_DIMR_ME                      (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_MDRCR */
+#define MCF_SEC_MDRCR_SR                     (0x1000000)
+#define MCF_SEC_MDRCR_MI                     (0x2000000)
+#define MCF_SEC_MDRCR_RI                     (0x4000000)
+
+/* Bit definitions and macros for MCF_SEC_MDSR */
+#define MCF_SEC_MDSR_RD                      (0x1000000)
+#define MCF_SEC_MDSR_ID                      (0x2000000)
+#define MCF_SEC_MDSR_IE                      (0x4000000)
+#define MCF_SEC_MDSR_IFW                     (0x10000000)
+#define MCF_SEC_MDSR_HALT                    (0x20000000)
+
+/* Bit definitions and macros for MCF_SEC_MDISR */
+#define MCF_SEC_MDISR_DSE                    (0x10000)
+#define MCF_SEC_MDISR_KSE                    (0x20000)
+#define MCF_SEC_MDISR_CE                     (0x40000)
+#define MCF_SEC_MDISR_ERE                    (0x80000)
+#define MCF_SEC_MDISR_IE                     (0x100000)
+#define MCF_SEC_MDISR_IFO                    (0x4000000)
+#define MCF_SEC_MDISR_AE                     (0x40000000)
+#define MCF_SEC_MDISR_ME                     (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_MDIMR */
+#define MCF_SEC_MDIMR_DSE                    (0x10000)
+#define MCF_SEC_MDIMR_KSE                    (0x20000)
+#define MCF_SEC_MDIMR_CE                     (0x40000)
+#define MCF_SEC_MDIMR_ERE                    (0x80000)
+#define MCF_SEC_MDIMR_IE                     (0x100000)
+#define MCF_SEC_MDIMR_IFO                    (0x4000000)
+#define MCF_SEC_MDIMR_AE                     (0x40000000)
+#define MCF_SEC_MDIMR_ME                     (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_RNGRCR */
+#define MCF_SEC_RNGRCR_SR                    (0x1000000)
+#define MCF_SEC_RNGRCR_MI                    (0x2000000)
+#define MCF_SEC_RNGRCR_RI                    (0x4000000)
+
+/* Bit definitions and macros for MCF_SEC_RNGSR */
+#define MCF_SEC_RNGSR_RD                     (0x1000000)
+#define MCF_SEC_RNGSR_IE                     (0x4000000)
+#define MCF_SEC_RNGSR_OFR                    (0x8000000)
+#define MCF_SEC_RNGSR_HALT                   (0x20000000)
+
+/* Bit definitions and macros for MCF_SEC_RNGISR */
+#define MCF_SEC_RNGISR_IE                    (0x100000)
+#define MCF_SEC_RNGISR_OFU                   (0x2000000)
+#define MCF_SEC_RNGISR_AE                    (0x40000000)
+#define MCF_SEC_RNGISR_ME                    (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_RNGIMR */
+#define MCF_SEC_RNGIMR_IE                    (0x100000)
+#define MCF_SEC_RNGIMR_OFU                   (0x2000000)
+#define MCF_SEC_RNGIMR_AE                    (0x40000000)
+#define MCF_SEC_RNGIMR_ME                    (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_AESRCR */
+#define MCF_SEC_AESRCR_SR                    (0x1000000)
+#define MCF_SEC_AESRCR_MI                    (0x2000000)
+#define MCF_SEC_AESRCR_RI                    (0x4000000)
+
+/* Bit definitions and macros for MCF_SEC_AESSR */
+#define MCF_SEC_AESSR_RD                     (0x1000000)
+#define MCF_SEC_AESSR_ID                     (0x2000000)
+#define MCF_SEC_AESSR_IE                     (0x4000000)
+#define MCF_SEC_AESSR_OFR                    (0x8000000)
+#define MCF_SEC_AESSR_IFW                    (0x10000000)
+#define MCF_SEC_AESSR_HALT                   (0x20000000)
+
+/* Bit definitions and macros for MCF_SEC_AESISR */
+#define MCF_SEC_AESISR_DSE                   (0x10000)
+#define MCF_SEC_AESISR_KSE                   (0x20000)
+#define MCF_SEC_AESISR_CE                    (0x40000)
+#define MCF_SEC_AESISR_ERE                   (0x80000)
+#define MCF_SEC_AESISR_IE                    (0x100000)
+#define MCF_SEC_AESISR_OFU                   (0x2000000)
+#define MCF_SEC_AESISR_IFO                   (0x4000000)
+#define MCF_SEC_AESISR_IFE                   (0x10000000)
+#define MCF_SEC_AESISR_OFE                   (0x20000000)
+#define MCF_SEC_AESISR_AE                    (0x40000000)
+#define MCF_SEC_AESISR_ME                    (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_AESIMR */
+#define MCF_SEC_AESIMR_DSE                   (0x10000)
+#define MCF_SEC_AESIMR_KSE                   (0x20000)
+#define MCF_SEC_AESIMR_CE                    (0x40000)
+#define MCF_SEC_AESIMR_ERE                   (0x80000)
+#define MCF_SEC_AESIMR_IE                    (0x100000)
+#define MCF_SEC_AESIMR_OFU                   (0x2000000)
+#define MCF_SEC_AESIMR_IFO                   (0x4000000)
+#define MCF_SEC_AESIMR_IFE                   (0x10000000)
+#define MCF_SEC_AESIMR_OFE                   (0x20000000)
+#define MCF_SEC_AESIMR_AE                    (0x40000000)
+#define MCF_SEC_AESIMR_ME                    (0x80000000)
+
+
+#endif /* __MCF5475_SEC_H__ */
--- a/tos/fpga_test/include/MCF5475_SIU.h
+++ b/tos/fpga_test/include/MCF5475_SIU.h
@@ -0,0 +1,67 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_SIU_H__
+#define __MCF5475_SIU_H__
+
+
+/*********************************************************************
+*
+* System Integration Unit (SIU)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_SIU_SBCR                         (*(volatile uint32_t*)(&_MBAR[0x10]))
+#define MCF_SIU_SECSACR                      (*(volatile uint32_t*)(&_MBAR[0x38]))
+#define MCF_SIU_RSR                          (*(volatile uint32_t*)(&_MBAR[0x44]))
+#define MCF_SIU_JTAGID                       (*(volatile uint32_t*)(&_MBAR[0x50]))
+
+
+/* Bit definitions and macros for MCF_SIU_SBCR */
+#define MCF_SIU_SBCR_PIN2DSPI                (0x8000000)
+#define MCF_SIU_SBCR_DMA2CPU                 (0x10000000)
+#define MCF_SIU_SBCR_CPU2DMA                 (0x20000000)
+#define MCF_SIU_SBCR_PIN2DMA                 (0x40000000)
+#define MCF_SIU_SBCR_PIN2CPU                 (0x80000000)
+
+/* Bit definitions and macros for MCF_SIU_SECSACR */
+#define MCF_SIU_SECSACR_SEQEN                (0x1)
+
+/* Bit definitions and macros for MCF_SIU_RSR */
+#define MCF_SIU_RSR_RST                      (0x1)
+#define MCF_SIU_RSR_RSTWD                    (0x2)
+#define MCF_SIU_RSR_RSTJTG                   (0x8)
+
+/* Bit definitions and macros for MCF_SIU_JTAGID */
+#define MCF_SIU_JTAGID_JTAGID(x)             (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_SIU_JTAGID */
+#define MCF_SIU_JTAGID_REV          (0xF0000000)
+#define MCF_SIU_JTAGID_PROCESSOR    (0x0FFFFFFF)
+#define MCF_SIU_JTAGID_MCF5485      (0x0800C01D)
+#define MCF_SIU_JTAGID_MCF5484      (0x0800D01D)
+#define MCF_SIU_JTAGID_MCF5483      (0x0800E01D)
+#define MCF_SIU_JTAGID_MCF5482      (0x0800F01D)
+#define MCF_SIU_JTAGID_MCF5481      (0x0801001D)
+#define MCF_SIU_JTAGID_MCF5480      (0x0801101D)
+#define MCF_SIU_JTAGID_MCF5475      (0x0801201D)
+#define MCF_SIU_JTAGID_MCF5474      (0x0801301D)
+#define MCF_SIU_JTAGID_MCF5473      (0x0801401D)
+#define MCF_SIU_JTAGID_MCF5472      (0x0801501D)
+#define MCF_SIU_JTAGID_MCF5471      (0x0801601D)
+#define MCF_SIU_JTAGID_MCF5470      (0x0801701D)
+
+#endif /* __MCF5475_SIU_H__ */
--- a/tos/fpga_test/include/MCF5475_SLT.h
+++ b/tos/fpga_test/include/MCF5475_SLT.h
@@ -0,0 +1,59 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_SLT_H__
+#define __MCF5475_SLT_H__
+
+
+/*********************************************************************
+*
+* Slice Timers (SLT)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_SLT0_STCNT                       (*(volatile uint32_t*)(&_MBAR[0x900]))
+#define MCF_SLT0_SCR                         (*(volatile uint32_t*)(&_MBAR[0x904]))
+#define MCF_SLT0_SCNT                        (*(volatile uint32_t*)(&_MBAR[0x908]))
+#define MCF_SLT0_SSR                         (*(volatile uint32_t*)(&_MBAR[0x90C]))
+
+#define MCF_SLT1_STCNT                       (*(volatile uint32_t*)(&_MBAR[0x910]))
+#define MCF_SLT1_SCR                         (*(volatile uint32_t*)(&_MBAR[0x914]))
+#define MCF_SLT1_SCNT                        (*(volatile uint32_t*)(&_MBAR[0x918]))
+#define MCF_SLT1_SSR                         (*(volatile uint32_t*)(&_MBAR[0x91C]))
+
+#define MCF_SLT_STCNT(x)                     (*(volatile uint32_t*)(&_MBAR[0x900 + ((x)*0x10)]))
+#define MCF_SLT_SCR(x)                       (*(volatile uint32_t*)(&_MBAR[0x904 + ((x)*0x10)]))
+#define MCF_SLT_SCNT(x)                      (*(volatile int32_t*)(&_MBAR[0x908 + ((x)*0x10)]))
+#define MCF_SLT_SSR(x)                       (*(volatile uint32_t*)(&_MBAR[0x90C + ((x)*0x10)]))
+
+
+/* Bit definitions and macros for MCF_SLT_STCNT */
+#define MCF_SLT_STCNT_TC(x)                  (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_SLT_SCR */
+#define MCF_SLT_SCR_TEN                      (0x1000000)
+#define MCF_SLT_SCR_IEN                      (0x2000000)
+#define MCF_SLT_SCR_RUN                      (0x4000000)
+
+/* Bit definitions and macros for MCF_SLT_SCNT */
+#define MCF_SLT_SCNT_CNT(x)                  (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_SLT_SSR */
+#define MCF_SLT_SSR_ST                       (0x1000000)
+#define MCF_SLT_SSR_BE                       (0x2000000)
+
+
+#endif /* __MCF5475_SLT_H__ */
--- a/tos/fpga_test/include/MCF5475_SRAM.h
+++ b/tos/fpga_test/include/MCF5475_SRAM.h
@@ -0,0 +1,62 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_SRAM_H__
+#define __MCF5475_SRAM_H__
+
+
+/*********************************************************************
+*
+* System SRAM Module (SRAM)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_SRAM_SSCR                        (*(volatile uint32_t*)(&__MBAR[0x1FFC0]))
+#define MCF_SRAM_TCCR                        (*(volatile uint32_t*)(&__MBAR[0x1FFC4]))
+#define MCF_SRAM_TCCRDR                      (*(volatile uint32_t*)(&__MBAR[0x1FFC8]))
+#define MCF_SRAM_TCCRDW                      (*(volatile uint32_t*)(&__MBAR[0x1FFCC]))
+#define MCF_SRAM_TCCRSEC                     (*(volatile uint32_t*)(&__MBAR[0x1FFD0]))
+
+
+/* Bit definitions and macros for MCF_SRAM_SSCR */
+#define MCF_SRAM_SSCR_INLV                   (0x10000)
+
+/* Bit definitions and macros for MCF_SRAM_TCCR */
+#define MCF_SRAM_TCCR_BANK0_TC(x)            (((x)&0xF)<<0)
+#define MCF_SRAM_TCCR_BANK1_TC(x)            (((x)&0xF)<<0x8)
+#define MCF_SRAM_TCCR_BANK2_TC(x)            (((x)&0xF)<<0x10)
+#define MCF_SRAM_TCCR_BANK3_TC(x)            (((x)&0xF)<<0x18)
+
+/* Bit definitions and macros for MCF_SRAM_TCCRDR */
+#define MCF_SRAM_TCCRDR_BANK0_TC(x)          (((x)&0xF)<<0)
+#define MCF_SRAM_TCCRDR_BANK1_TC(x)          (((x)&0xF)<<0x8)
+#define MCF_SRAM_TCCRDR_BANK2_TC(x)          (((x)&0xF)<<0x10)
+#define MCF_SRAM_TCCRDR_BANK3_TC(x)          (((x)&0xF)<<0x18)
+
+/* Bit definitions and macros for MCF_SRAM_TCCRDW */
+#define MCF_SRAM_TCCRDW_BANK0_TC(x)          (((x)&0xF)<<0)
+#define MCF_SRAM_TCCRDW_BANK1_TC(x)          (((x)&0xF)<<0x8)
+#define MCF_SRAM_TCCRDW_BANK2_TC(x)          (((x)&0xF)<<0x10)
+#define MCF_SRAM_TCCRDW_BANK3_TC(x)          (((x)&0xF)<<0x18)
+
+/* Bit definitions and macros for MCF_SRAM_TCCRSEC */
+#define MCF_SRAM_TCCRSEC_BANK0_TC(x)         (((x)&0xF)<<0)
+#define MCF_SRAM_TCCRSEC_BANK1_TC(x)         (((x)&0xF)<<0x8)
+#define MCF_SRAM_TCCRSEC_BANK2_TC(x)         (((x)&0xF)<<0x10)
+#define MCF_SRAM_TCCRSEC_BANK3_TC(x)         (((x)&0xF)<<0x18)
+
+
+#endif /* __MCF5475_SRAM_H__ */
--- a/tos/fpga_test/include/MCF5475_USB.h
+++ b/tos/fpga_test/include/MCF5475_USB.h
@@ -0,0 +1,554 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_USB_H__
+#define __MCF5475_USB_H__
+
+
+/*********************************************************************
+*
+* Universal Serial Bus Interface (USB)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_USB_USBAISR                      (*(volatile uint8_t *)(&__MBAR[0xB000]))
+#define MCF_USB_USBAIMR                      (*(volatile uint8_t *)(&__MBAR[0xB001]))
+#define MCF_USB_EPINFO                       (*(volatile uint8_t *)(&__MBAR[0xB003]))
+#define MCF_USB_CFGR                         (*(volatile uint8_t *)(&__MBAR[0xB004]))
+#define MCF_USB_CFGAR                        (*(volatile uint8_t *)(&__MBAR[0xB005]))
+#define MCF_USB_SPEEDR                       (*(volatile uint8_t *)(&__MBAR[0xB006]))
+#define MCF_USB_FRMNUMR                      (*(volatile uint16_t*)(&__MBAR[0xB00E]))
+#define MCF_USB_EPTNR                        (*(volatile uint16_t*)(&__MBAR[0xB010]))
+#define MCF_USB_IFUR                         (*(volatile uint16_t*)(&__MBAR[0xB014]))
+#define MCF_USB_IFR0                         (*(volatile uint16_t*)(&__MBAR[0xB040]))
+#define MCF_USB_IFR1                         (*(volatile uint16_t*)(&__MBAR[0xB042]))
+#define MCF_USB_IFR2                         (*(volatile uint16_t*)(&__MBAR[0xB044]))
+#define MCF_USB_IFR3                         (*(volatile uint16_t*)(&__MBAR[0xB046]))
+#define MCF_USB_IFR4                         (*(volatile uint16_t*)(&__MBAR[0xB048]))
+#define MCF_USB_IFR5                         (*(volatile uint16_t*)(&__MBAR[0xB04A]))
+#define MCF_USB_IFR6                         (*(volatile uint16_t*)(&__MBAR[0xB04C]))
+#define MCF_USB_IFR7                         (*(volatile uint16_t*)(&__MBAR[0xB04E]))
+#define MCF_USB_IFR8                         (*(volatile uint16_t*)(&__MBAR[0xB050]))
+#define MCF_USB_IFR9                         (*(volatile uint16_t*)(&__MBAR[0xB052]))
+#define MCF_USB_IFR10                        (*(volatile uint16_t*)(&__MBAR[0xB054]))
+#define MCF_USB_IFR11                        (*(volatile uint16_t*)(&__MBAR[0xB056]))
+#define MCF_USB_IFR12                        (*(volatile uint16_t*)(&__MBAR[0xB058]))
+#define MCF_USB_IFR13                        (*(volatile uint16_t*)(&__MBAR[0xB05A]))
+#define MCF_USB_IFR14                        (*(volatile uint16_t*)(&__MBAR[0xB05C]))
+#define MCF_USB_IFR15                        (*(volatile uint16_t*)(&__MBAR[0xB05E]))
+#define MCF_USB_IFR16                        (*(volatile uint16_t*)(&__MBAR[0xB060]))
+#define MCF_USB_IFR17                        (*(volatile uint16_t*)(&__MBAR[0xB062]))
+#define MCF_USB_IFR18                        (*(volatile uint16_t*)(&__MBAR[0xB064]))
+#define MCF_USB_IFR19                        (*(volatile uint16_t*)(&__MBAR[0xB066]))
+#define MCF_USB_IFR20                        (*(volatile uint16_t*)(&__MBAR[0xB068]))
+#define MCF_USB_IFR21                        (*(volatile uint16_t*)(&__MBAR[0xB06A]))
+#define MCF_USB_IFR22                        (*(volatile uint16_t*)(&__MBAR[0xB06C]))
+#define MCF_USB_IFR23                        (*(volatile uint16_t*)(&__MBAR[0xB06E]))
+#define MCF_USB_IFR24                        (*(volatile uint16_t*)(&__MBAR[0xB070]))
+#define MCF_USB_IFR25                        (*(volatile uint16_t*)(&__MBAR[0xB072]))
+#define MCF_USB_IFR26                        (*(volatile uint16_t*)(&__MBAR[0xB074]))
+#define MCF_USB_IFR27                        (*(volatile uint16_t*)(&__MBAR[0xB076]))
+#define MCF_USB_IFR28                        (*(volatile uint16_t*)(&__MBAR[0xB078]))
+#define MCF_USB_IFR29                        (*(volatile uint16_t*)(&__MBAR[0xB07A]))
+#define MCF_USB_IFR30                        (*(volatile uint16_t*)(&__MBAR[0xB07C]))
+#define MCF_USB_IFR31                        (*(volatile uint16_t*)(&__MBAR[0xB07E]))
+#define MCF_USB_PPCNT                        (*(volatile uint16_t*)(&__MBAR[0xB080]))
+#define MCF_USB_DPCNT                        (*(volatile uint16_t*)(&__MBAR[0xB082]))
+#define MCF_USB_CRCECNT                      (*(volatile uint16_t*)(&__MBAR[0xB084]))
+#define MCF_USB_BSECNT                       (*(volatile uint16_t*)(&__MBAR[0xB086]))
+#define MCF_USB_PIDECNT                      (*(volatile uint16_t*)(&__MBAR[0xB088]))
+#define MCF_USB_FRMECNT                      (*(volatile uint16_t*)(&__MBAR[0xB08A]))
+#define MCF_USB_TXPCNT                       (*(volatile uint16_t*)(&__MBAR[0xB08C]))
+#define MCF_USB_CNTOVR                       (*(volatile uint8_t *)(&__MBAR[0xB08E]))
+#define MCF_USB_EP0ACR                       (*(volatile uint8_t *)(&__MBAR[0xB101]))
+#define MCF_USB_EP0MPSR                      (*(volatile uint16_t*)(&__MBAR[0xB102]))
+#define MCF_USB_EP0IFR                       (*(volatile uint8_t *)(&__MBAR[0xB104]))
+#define MCF_USB_EP0SR                        (*(volatile uint8_t *)(&__MBAR[0xB105]))
+#define MCF_USB_BMRTR                        (*(volatile uint8_t *)(&__MBAR[0xB106]))
+#define MCF_USB_BRTR                         (*(volatile uint8_t *)(&__MBAR[0xB107]))
+#define MCF_USB_WVALUER                      (*(volatile uint16_t*)(&__MBAR[0xB108]))
+#define MCF_USB_WINDEXR                      (*(volatile uint16_t*)(&__MBAR[0xB10A]))
+#define MCF_USB_WLENGTHR                     (*(volatile uint16_t*)(&__MBAR[0xB10C]))
+#define MCF_USB_EP1OUTACR                    (*(volatile uint8_t *)(&__MBAR[0xB131]))
+#define MCF_USB_EP1OUTMPSR                   (*(volatile uint16_t*)(&__MBAR[0xB132]))
+#define MCF_USB_EP1OUTIFR                    (*(volatile uint8_t *)(&__MBAR[0xB134]))
+#define MCF_USB_EP1OUTSR                     (*(volatile uint8_t *)(&__MBAR[0xB135]))
+#define MCF_USB_EP1OUTSFR                    (*(volatile uint16_t*)(&__MBAR[0xB13E]))
+#define MCF_USB_EP1INACR                     (*(volatile uint8_t *)(&__MBAR[0xB149]))
+#define MCF_USB_EP1INMPSR                    (*(volatile uint16_t*)(&__MBAR[0xB14A]))
+#define MCF_USB_EP1INIFR                     (*(volatile uint8_t *)(&__MBAR[0xB14C]))
+#define MCF_USB_EP1INSR                      (*(volatile uint8_t *)(&__MBAR[0xB14D]))
+#define MCF_USB_EP1INSFR                     (*(volatile uint16_t*)(&__MBAR[0xB156]))
+#define MCF_USB_EP2OUTACR                    (*(volatile uint8_t *)(&__MBAR[0xB161]))
+#define MCF_USB_EP2OUTMPSR                   (*(volatile uint16_t*)(&__MBAR[0xB162]))
+#define MCF_USB_EP2OUTIFR                    (*(volatile uint8_t *)(&__MBAR[0xB164]))
+#define MCF_USB_EP2OUTSR                     (*(volatile uint8_t *)(&__MBAR[0xB165]))
+#define MCF_USB_EP2OUTSFR                    (*(volatile uint16_t*)(&__MBAR[0xB16E]))
+#define MCF_USB_EP2INACR                     (*(volatile uint8_t *)(&__MBAR[0xB179]))
+#define MCF_USB_EP2INMPSR                    (*(volatile uint16_t*)(&__MBAR[0xB17A]))
+#define MCF_USB_EP2INIFR                     (*(volatile uint8_t *)(&__MBAR[0xB17C]))
+#define MCF_USB_EP2INSR                      (*(volatile uint8_t *)(&__MBAR[0xB17D]))
+#define MCF_USB_EP2INSFR                     (*(volatile uint16_t*)(&__MBAR[0xB186]))
+#define MCF_USB_EP3OUTACR                    (*(volatile uint8_t *)(&__MBAR[0xB191]))
+#define MCF_USB_EP3OUTMPSR                   (*(volatile uint16_t*)(&__MBAR[0xB192]))
+#define MCF_USB_EP3OUTIFR                    (*(volatile uint8_t *)(&__MBAR[0xB194]))
+#define MCF_USB_EP3OUTSR                     (*(volatile uint8_t *)(&__MBAR[0xB195]))
+#define MCF_USB_EP3OUTSFR                    (*(volatile uint16_t*)(&__MBAR[0xB19E]))
+#define MCF_USB_EP3INACR                     (*(volatile uint8_t *)(&__MBAR[0xB1A9]))
+#define MCF_USB_EP3INMPSR                    (*(volatile uint16_t*)(&__MBAR[0xB1AA]))
+#define MCF_USB_EP3INIFR                     (*(volatile uint8_t *)(&__MBAR[0xB1AC]))
+#define MCF_USB_EP3INSR                      (*(volatile uint8_t *)(&__MBAR[0xB1AD]))
+#define MCF_USB_EP3INSFR                     (*(volatile uint16_t*)(&__MBAR[0xB1B6]))
+#define MCF_USB_EP4OUTACR                    (*(volatile uint8_t *)(&__MBAR[0xB1C1]))
+#define MCF_USB_EP4OUTMPSR                   (*(volatile uint16_t*)(&__MBAR[0xB1C2]))
+#define MCF_USB_EP4OUTIFR                    (*(volatile uint8_t *)(&__MBAR[0xB1C4]))
+#define MCF_USB_EP4OUTSR                     (*(volatile uint8_t *)(&__MBAR[0xB1C5]))
+#define MCF_USB_EP4OUTSFR                    (*(volatile uint16_t*)(&__MBAR[0xB1CE]))
+#define MCF_USB_EP4INACR                     (*(volatile uint8_t *)(&__MBAR[0xB1D9]))
+#define MCF_USB_EP4INMPSR                    (*(volatile uint16_t*)(&__MBAR[0xB1DA]))
+#define MCF_USB_EP4INIFR                     (*(volatile uint8_t *)(&__MBAR[0xB1DC]))
+#define MCF_USB_EP4INSR                      (*(volatile uint8_t *)(&__MBAR[0xB1DD]))
+#define MCF_USB_EP4INSFR                     (*(volatile uint16_t*)(&__MBAR[0xB1E6]))
+#define MCF_USB_EP5OUTACR                    (*(volatile uint8_t *)(&__MBAR[0xB1F1]))
+#define MCF_USB_EP5OUTMPSR                   (*(volatile uint16_t*)(&__MBAR[0xB1F2]))
+#define MCF_USB_EP5OUTIFR                    (*(volatile uint8_t *)(&__MBAR[0xB1F4]))
+#define MCF_USB_EP5OUTSR                     (*(volatile uint8_t *)(&__MBAR[0xB1F5]))
+#define MCF_USB_EP5OUTSFR                    (*(volatile uint16_t*)(&__MBAR[0xB1FE]))
+#define MCF_USB_EP5INACR                     (*(volatile uint8_t *)(&__MBAR[0xB209]))
+#define MCF_USB_EP5INMPSR                    (*(volatile uint16_t*)(&__MBAR[0xB20A]))
+#define MCF_USB_EP5INIFR                     (*(volatile uint8_t *)(&__MBAR[0xB20C]))
+#define MCF_USB_EP5INSR                      (*(volatile uint8_t *)(&__MBAR[0xB20D]))
+#define MCF_USB_EP5INSFR                     (*(volatile uint16_t*)(&__MBAR[0xB216]))
+#define MCF_USB_EP6OUTACR                    (*(volatile uint8_t *)(&__MBAR[0xB221]))
+#define MCF_USB_EP6OUTMPSR                   (*(volatile uint16_t*)(&__MBAR[0xB222]))
+#define MCF_USB_EP6OUTIFR                    (*(volatile uint8_t *)(&__MBAR[0xB224]))
+#define MCF_USB_EP6OUTSR                     (*(volatile uint8_t *)(&__MBAR[0xB225]))
+#define MCF_USB_EP6OUTSFR                    (*(volatile uint16_t*)(&__MBAR[0xB22E]))
+#define MCF_USB_EP6INACR                     (*(volatile uint8_t *)(&__MBAR[0xB239]))
+#define MCF_USB_EP6INMPSR                    (*(volatile uint16_t*)(&__MBAR[0xB23A]))
+#define MCF_USB_EP6INIFR                     (*(volatile uint8_t *)(&__MBAR[0xB23C]))
+#define MCF_USB_EP6INSR                      (*(volatile uint8_t *)(&__MBAR[0xB23D]))
+#define MCF_USB_EP6INSFR                     (*(volatile uint16_t*)(&__MBAR[0xB246]))
+#define MCF_USB_USBSR                        (*(volatile uint32_t*)(&__MBAR[0xB400]))
+#define MCF_USB_USBCR                        (*(volatile uint32_t*)(&__MBAR[0xB404]))
+#define MCF_USB_DRAMCR                       (*(volatile uint32_t*)(&__MBAR[0xB408]))
+#define MCF_USB_DRAMDR                       (*(volatile uint32_t*)(&__MBAR[0xB40C]))
+#define MCF_USB_USBISR                       (*(volatile uint32_t*)(&__MBAR[0xB410]))
+#define MCF_USB_USBIMR                       (*(volatile uint32_t*)(&__MBAR[0xB414]))
+#define MCF_USB_EP0STAT                      (*(volatile uint32_t*)(&__MBAR[0xB440]))
+#define MCF_USB_EP0ISR                       (*(volatile uint32_t*)(&__MBAR[0xB444]))
+#define MCF_USB_EP0IMR                       (*(volatile uint32_t*)(&__MBAR[0xB448]))
+#define MCF_USB_EP0FRCFGR                    (*(volatile uint32_t*)(&__MBAR[0xB44C]))
+#define MCF_USB_EP0FDR                       (*(volatile uint32_t*)(&__MBAR[0xB450]))
+#define MCF_USB_EP0FSR                       (*(volatile uint32_t*)(&__MBAR[0xB454]))
+#define MCF_USB_EP0FCR                       (*(volatile uint32_t*)(&__MBAR[0xB458]))
+#define MCF_USB_EP0FAR                       (*(volatile uint32_t*)(&__MBAR[0xB45C]))
+#define MCF_USB_EP0FRP                       (*(volatile uint32_t*)(&__MBAR[0xB460]))
+#define MCF_USB_EP0FWP                       (*(volatile uint32_t*)(&__MBAR[0xB464]))
+#define MCF_USB_EP0LRFP                      (*(volatile uint32_t*)(&__MBAR[0xB468]))
+#define MCF_USB_EP0LWFP                      (*(volatile uint32_t*)(&__MBAR[0xB46C]))
+#define MCF_USB_EP1STAT                      (*(volatile uint32_t*)(&__MBAR[0xB470]))
+#define MCF_USB_EP1ISR                       (*(volatile uint32_t*)(&__MBAR[0xB474]))
+#define MCF_USB_EP1IMR                       (*(volatile uint32_t*)(&__MBAR[0xB478]))
+#define MCF_USB_EP1FRCFGR                    (*(volatile uint32_t*)(&__MBAR[0xB47C]))
+#define MCF_USB_EP1FDR                       (*(volatile uint32_t*)(&__MBAR[0xB480]))
+#define MCF_USB_EP1FSR                       (*(volatile uint32_t*)(&__MBAR[0xB484]))
+#define MCF_USB_EP1FCR                       (*(volatile uint32_t*)(&__MBAR[0xB488]))
+#define MCF_USB_EP1FAR                       (*(volatile uint32_t*)(&__MBAR[0xB48C]))
+#define MCF_USB_EP1FRP                       (*(volatile uint32_t*)(&__MBAR[0xB490]))
+#define MCF_USB_EP1FWP                       (*(volatile uint32_t*)(&__MBAR[0xB494]))
+#define MCF_USB_EP1LRFP                      (*(volatile uint32_t*)(&__MBAR[0xB498]))
+#define MCF_USB_EP1LWFP                      (*(volatile uint32_t*)(&__MBAR[0xB49C]))
+#define MCF_USB_EP2STAT                      (*(volatile uint32_t*)(&__MBAR[0xB4A0]))
+#define MCF_USB_EP2ISR                       (*(volatile uint32_t*)(&__MBAR[0xB4A4]))
+#define MCF_USB_EP2IMR                       (*(volatile uint32_t*)(&__MBAR[0xB4A8]))
+#define MCF_USB_EP2FRCFGR                    (*(volatile uint32_t*)(&__MBAR[0xB4AC]))
+#define MCF_USB_EP2FDR                       (*(volatile uint32_t*)(&__MBAR[0xB4B0]))
+#define MCF_USB_EP2FSR                       (*(volatile uint32_t*)(&__MBAR[0xB4B4]))
+#define MCF_USB_EP2FCR                       (*(volatile uint32_t*)(&__MBAR[0xB4B8]))
+#define MCF_USB_EP2FAR                       (*(volatile uint32_t*)(&__MBAR[0xB4BC]))
+#define MCF_USB_EP2FRP                       (*(volatile uint32_t*)(&__MBAR[0xB4C0]))
+#define MCF_USB_EP2FWP                       (*(volatile uint32_t*)(&__MBAR[0xB4C4]))
+#define MCF_USB_EP2LRFP                      (*(volatile uint32_t*)(&__MBAR[0xB4C8]))
+#define MCF_USB_EP2LWFP                      (*(volatile uint32_t*)(&__MBAR[0xB4CC]))
+#define MCF_USB_EP3STAT                      (*(volatile uint32_t*)(&__MBAR[0xB4D0]))
+#define MCF_USB_EP3ISR                       (*(volatile uint32_t*)(&__MBAR[0xB4D4]))
+#define MCF_USB_EP3IMR                       (*(volatile uint32_t*)(&__MBAR[0xB4D8]))
+#define MCF_USB_EP3FRCFGR                    (*(volatile uint32_t*)(&__MBAR[0xB4DC]))
+#define MCF_USB_EP3FDR                       (*(volatile uint32_t*)(&__MBAR[0xB4E0]))
+#define MCF_USB_EP3FSR                       (*(volatile uint32_t*)(&__MBAR[0xB4E4]))
+#define MCF_USB_EP3FCR                       (*(volatile uint32_t*)(&__MBAR[0xB4E8]))
+#define MCF_USB_EP3FAR                       (*(volatile uint32_t*)(&__MBAR[0xB4EC]))
+#define MCF_USB_EP3FRP                       (*(volatile uint32_t*)(&__MBAR[0xB4F0]))
+#define MCF_USB_EP3FWP                       (*(volatile uint32_t*)(&__MBAR[0xB4F4]))
+#define MCF_USB_EP3LRFP                      (*(volatile uint32_t*)(&__MBAR[0xB4F8]))
+#define MCF_USB_EP3LWFP                      (*(volatile uint32_t*)(&__MBAR[0xB4FC]))
+#define MCF_USB_EP4STAT                      (*(volatile uint32_t*)(&__MBAR[0xB500]))
+#define MCF_USB_EP4ISR                       (*(volatile uint32_t*)(&__MBAR[0xB504]))
+#define MCF_USB_EP4IMR                       (*(volatile uint32_t*)(&__MBAR[0xB508]))
+#define MCF_USB_EP4FRCFGR                    (*(volatile uint32_t*)(&__MBAR[0xB50C]))
+#define MCF_USB_EP4FDR                       (*(volatile uint32_t*)(&__MBAR[0xB510]))
+#define MCF_USB_EP4FSR                       (*(volatile uint32_t*)(&__MBAR[0xB514]))
+#define MCF_USB_EP4FCR                       (*(volatile uint32_t*)(&__MBAR[0xB518]))
+#define MCF_USB_EP4FAR                       (*(volatile uint32_t*)(&__MBAR[0xB51C]))
+#define MCF_USB_EP4FRP                       (*(volatile uint32_t*)(&__MBAR[0xB520]))
+#define MCF_USB_EP4FWP                       (*(volatile uint32_t*)(&__MBAR[0xB524]))
+#define MCF_USB_EP4LRFP                      (*(volatile uint32_t*)(&__MBAR[0xB528]))
+#define MCF_USB_EP4LWFP                      (*(volatile uint32_t*)(&__MBAR[0xB52C]))
+#define MCF_USB_EP5STAT                      (*(volatile uint32_t*)(&__MBAR[0xB530]))
+#define MCF_USB_EP5ISR                       (*(volatile uint32_t*)(&__MBAR[0xB534]))
+#define MCF_USB_EP5IMR                       (*(volatile uint32_t*)(&__MBAR[0xB538]))
+#define MCF_USB_EP5FRCFGR                    (*(volatile uint32_t*)(&__MBAR[0xB53C]))
+#define MCF_USB_EP5FDR                       (*(volatile uint32_t*)(&__MBAR[0xB540]))
+#define MCF_USB_EP5FSR                       (*(volatile uint32_t*)(&__MBAR[0xB544]))
+#define MCF_USB_EP5FCR                       (*(volatile uint32_t*)(&__MBAR[0xB548]))
+#define MCF_USB_EP5FAR                       (*(volatile uint32_t*)(&__MBAR[0xB54C]))
+#define MCF_USB_EP5FRP                       (*(volatile uint32_t*)(&__MBAR[0xB550]))
+#define MCF_USB_EP5FWP                       (*(volatile uint32_t*)(&__MBAR[0xB554]))
+#define MCF_USB_EP5LRFP                      (*(volatile uint32_t*)(&__MBAR[0xB558]))
+#define MCF_USB_EP5LWFP                      (*(volatile uint32_t*)(&__MBAR[0xB55C]))
+#define MCF_USB_EP6STAT                      (*(volatile uint32_t*)(&__MBAR[0xB560]))
+#define MCF_USB_EP6ISR                       (*(volatile uint32_t*)(&__MBAR[0xB564]))
+#define MCF_USB_EP6IMR                       (*(volatile uint32_t*)(&__MBAR[0xB568]))
+#define MCF_USB_EP6FRCFGR                    (*(volatile uint32_t*)(&__MBAR[0xB56C]))
+#define MCF_USB_EP6FDR                       (*(volatile uint32_t*)(&__MBAR[0xB570]))
+#define MCF_USB_EP6FSR                       (*(volatile uint32_t*)(&__MBAR[0xB574]))
+#define MCF_USB_EP6FCR                       (*(volatile uint32_t*)(&__MBAR[0xB578]))
+#define MCF_USB_EP6FAR                       (*(volatile uint32_t*)(&__MBAR[0xB57C]))
+#define MCF_USB_EP6FRP                       (*(volatile uint32_t*)(&__MBAR[0xB580]))
+#define MCF_USB_EP6FWP                       (*(volatile uint32_t*)(&__MBAR[0xB584]))
+#define MCF_USB_EP6LRFP                      (*(volatile uint32_t*)(&__MBAR[0xB588]))
+#define MCF_USB_EP6LWFP                      (*(volatile uint32_t*)(&__MBAR[0xB58C]))
+#define MCF_USB_IFR(x)                       (*(volatile uint16_t*)(&__MBAR[0xB040 + ((x)*0x2)]))
+#define MCF_USB_EPOUTACR(x)                  (*(volatile uint8_t *)(&__MBAR[0xB131 + ((x-1)*0x30)]))
+#define MCF_USB_EPOUTMPSR(x)                 (*(volatile uint16_t*)(&__MBAR[0xB132 + ((x-1)*0x30)]))
+#define MCF_USB_EPOUTIFR(x)                  (*(volatile uint8_t *)(&__MBAR[0xB134 + ((x-1)*0x30)]))
+#define MCF_USB_EPOUTSR(x)                   (*(volatile uint8_t *)(&__MBAR[0xB135 + ((x-1)*0x30)]))
+#define MCF_USB_EPOUTSFR(x)                  (*(volatile uint16_t*)(&__MBAR[0xB13E + ((x-1)*0x30)]))
+#define MCF_USB_EPINACR(x)                   (*(volatile uint8_t *)(&__MBAR[0xB149 + ((x-1)*0x30)]))
+#define MCF_USB_EPINMPSR(x)                  (*(volatile uint16_t*)(&__MBAR[0xB14A + ((x-1)*0x30)]))
+#define MCF_USB_EPINIFR(x)                   (*(volatile uint8_t *)(&__MBAR[0xB14C + ((x-1)*0x30)]))
+#define MCF_USB_EPINSR(x)                    (*(volatile uint8_t *)(&__MBAR[0xB14D + ((x-1)*0x30)]))
+#define MCF_USB_EPINSFR(x)                   (*(volatile uint16_t*)(&__MBAR[0xB156 + ((x-1)*0x30)]))
+#define MCF_USB_EPSTAT(x)                    (*(volatile uint32_t*)(&__MBAR[0xB440 + ((x)*0x30)]))
+#define MCF_USB_EPISR(x)                     (*(volatile uint32_t*)(&__MBAR[0xB444 + ((x)*0x30)]))
+#define MCF_USB_EPIMR(x)                     (*(volatile uint32_t*)(&__MBAR[0xB448 + ((x)*0x30)]))
+#define MCF_USB_EPFRCFGR(x)                  (*(volatile uint32_t*)(&__MBAR[0xB44C + ((x)*0x30)]))
+#define MCF_USB_EPFDR(x)                     (*(volatile uint32_t*)(&__MBAR[0xB450 + ((x)*0x30)]))
+#define MCF_USB_EPFSR(x)                     (*(volatile uint32_t*)(&__MBAR[0xB454 + ((x)*0x30)]))
+#define MCF_USB_EPFCR(x)                     (*(volatile uint32_t*)(&__MBAR[0xB458 + ((x)*0x30)]))
+#define MCF_USB_EPFAR(x)                     (*(volatile uint32_t*)(&__MBAR[0xB45C + ((x)*0x30)]))
+#define MCF_USB_EPFRP(x)                     (*(volatile uint32_t*)(&__MBAR[0xB460 + ((x)*0x30)]))
+#define MCF_USB_EPFWP(x)                     (*(volatile uint32_t*)(&__MBAR[0xB464 + ((x)*0x30)]))
+#define MCF_USB_EPLRFP(x)                    (*(volatile uint32_t*)(&__MBAR[0xB468 + ((x)*0x30)]))
+#define MCF_USB_EPLWFP(x)                    (*(volatile uint32_t*)(&__MBAR[0xB46C + ((x)*0x30)]))
+
+
+/* Bit definitions and macros for MCF_USB_USBAISR */
+#define MCF_USB_USBAISR_SETUP                (0x1)
+#define MCF_USB_USBAISR_IN                   (0x2)
+#define MCF_USB_USBAISR_OUT                  (0x4)
+#define MCF_USB_USBAISR_EPHALT               (0x8)
+#define MCF_USB_USBAISR_TRANSERR             (0x10)
+#define MCF_USB_USBAISR_ACK                  (0x20)
+#define MCF_USB_USBAISR_CTROVFL              (0x40)
+#define MCF_USB_USBAISR_EPSTALL              (0x80)
+
+/* Bit definitions and macros for MCF_USB_USBAIMR */
+#define MCF_USB_USBAIMR_SETUPEN              (0x1)
+#define MCF_USB_USBAIMR_INEN                 (0x2)
+#define MCF_USB_USBAIMR_OUTEN                (0x4)
+#define MCF_USB_USBAIMR_EPHALTEN             (0x8)
+#define MCF_USB_USBAIMR_TRANSERREN           (0x10)
+#define MCF_USB_USBAIMR_ACKEN                (0x20)
+#define MCF_USB_USBAIMR_CTROVFLEN            (0x40)
+#define MCF_USB_USBAIMR_EPSTALLEN            (0x80)
+
+/* Bit definitions and macros for MCF_USB_EPINFO */
+#define MCF_USB_EPINFO_EPDIR                 (0x1)
+#define MCF_USB_EPINFO_EPNUM(x)              (((x)&0x7)<<0x1)
+
+/* Bit definitions and macros for MCF_USB_CFGR */
+#define MCF_USB_CFGR_Configuration_Value(x)  (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_CFGAR */
+#define MCF_USB_CFGAR_RESERVED               (0xA0)
+#define MCF_USB_CFGAR_RMTWKEUP               (0xE0)
+
+/* Bit definitions and macros for MCF_USB_SPEEDR */
+#define MCF_USB_SPEEDR_SPEED(x)              (((x)&0x3)<<0)
+
+/* Bit definitions and macros for MCF_USB_FRMNUMR */
+#define MCF_USB_FRMNUMR_FRMNUM(x)            (((x)&0xFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_EPTNR */
+#define MCF_USB_EPTNR_EP1T(x)                (((x)&0x3)<<0)
+#define MCF_USB_EPTNR_EP2T(x)                (((x)&0x3)<<0x2)
+#define MCF_USB_EPTNR_EP3T(x)                (((x)&0x3)<<0x4)
+#define MCF_USB_EPTNR_EP4T(x)                (((x)&0x3)<<0x6)
+#define MCF_USB_EPTNR_EP5T(x)                (((x)&0x3)<<0x8)
+#define MCF_USB_EPTNR_EP6T(x)                (((x)&0x3)<<0xA)
+#define MCF_USB_EPTNR_EPnT1                  (0)
+#define MCF_USB_EPTNR_EPnT2                  (0x1)
+#define MCF_USB_EPTNR_EPnT3                  (0x2)
+
+/* Bit definitions and macros for MCF_USB_IFUR */
+#define MCF_USB_IFUR_ALTSET(x)               (((x)&0xFF)<<0)
+#define MCF_USB_IFUR_IFNUM(x)                (((x)&0xFF)<<0x8)
+
+/* Bit definitions and macros for MCF_USB_IFR */
+#define MCF_USB_IFR_ALTSET(x)                (((x)&0xFF)<<0)
+#define MCF_USB_IFR_IFNUM(x)                 (((x)&0xFF)<<0x8)
+
+/* Bit definitions and macros for MCF_USB_PPCNT */
+#define MCF_USB_PPCNT_PPCNT(x)               (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_DPCNT */
+#define MCF_USB_DPCNT_DPCNT(x)               (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_CRCECNT */
+#define MCF_USB_CRCECNT_CRCECNT(x)           (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_BSECNT */
+#define MCF_USB_BSECNT_BSECNT(x)             (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_PIDECNT */
+#define MCF_USB_PIDECNT_PIDECNT(x)           (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_FRMECNT */
+#define MCF_USB_FRMECNT_FRMECNT(x)           (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_TXPCNT */
+#define MCF_USB_TXPCNT_TXPCNT(x)             (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_CNTOVR */
+#define MCF_USB_CNTOVR_PPCNT                 (0x1)
+#define MCF_USB_CNTOVR_DPCNT                 (0x2)
+#define MCF_USB_CNTOVR_CRCECNT               (0x4)
+#define MCF_USB_CNTOVR_BSECNT                (0x8)
+#define MCF_USB_CNTOVR_PIDECNT               (0x10)
+#define MCF_USB_CNTOVR_FRMECNT               (0x20)
+#define MCF_USB_CNTOVR_TXPCNT                (0x40)
+
+/* Bit definitions and macros for MCF_USB_EP0ACR */
+#define MCF_USB_EP0ACR_TTYPE(x)              (((x)&0x3)<<0)
+#define MCF_USB_EP0ACR_TTYPE_CTRL            (0)
+#define MCF_USB_EP0ACR_TTYPE_ISOC            (0x1)
+#define MCF_USB_EP0ACR_TTYPE_BULK            (0x2)
+#define MCF_USB_EP0ACR_TTYPE_INT             (0x3)
+
+/* Bit definitions and macros for MCF_USB_EP0MPSR */
+#define MCF_USB_EP0MPSR_MAXPKTSZ(x)          (((x)&0x7FF)<<0)
+#define MCF_USB_EP0MPSR_ADDTRANS(x)          (((x)&0x3)<<0xB)
+
+/* Bit definitions and macros for MCF_USB_EP0IFR */
+#define MCF_USB_EP0IFR_IFNUM(x)              (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_EP0SR */
+#define MCF_USB_EP0SR_HALT                   (0x1)
+#define MCF_USB_EP0SR_ACTIVE                 (0x2)
+#define MCF_USB_EP0SR_PSTALL                 (0x4)
+#define MCF_USB_EP0SR_CCOMP                  (0x8)
+#define MCF_USB_EP0SR_TXZERO                 (0x20)
+#define MCF_USB_EP0SR_INT                    (0x80)
+
+/* Bit definitions and macros for MCF_USB_BMRTR */
+#define MCF_USB_BMRTR_REC(x)                 (((x)&0x1F)<<0)
+#define MCF_USB_BMRTR_REC_DEVICE             (0)
+#define MCF_USB_BMRTR_REC_INTERFACE          (0x1)
+#define MCF_USB_BMRTR_REC_ENDPOINT           (0x2)
+#define MCF_USB_BMRTR_REC_OTHER              (0x3)
+#define MCF_USB_BMRTR_TYPE(x)                (((x)&0x3)<<0x5)
+#define MCF_USB_BMRTR_TYPE_STANDARD          (0)
+#define MCF_USB_BMRTR_TYPE_CLASS             (0x20)
+#define MCF_USB_BMRTR_TYPE_VENDOR            (0x40)
+#define MCF_USB_BMRTR_DIR                    (0x80)
+
+/* Bit definitions and macros for MCF_USB_BRTR */
+#define MCF_USB_BRTR_BREQ(x)                 (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_WVALUER */
+#define MCF_USB_WVALUER_WVALUE(x)            (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_WINDEXR */
+#define MCF_USB_WINDEXR_WINDEX(x)            (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_WLENGTHR */
+#define MCF_USB_WLENGTHR_WLENGTH(x)          (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_EPOUTACR */
+#define MCF_USB_EPOUTACR_TTYPE(x)            (((x)&0x3)<<0)
+#define MCF_USB_EPOUTACR_TTYPE_ISOC          (0x1)
+#define MCF_USB_EPOUTACR_TTYPE_BULK          (0x2)
+#define MCF_USB_EPOUTACR_TTYPE_INT           (0x3)
+
+/* Bit definitions and macros for MCF_USB_EPOUTMPSR */
+#define MCF_USB_EPOUTMPSR_MAXPKTSZ(x)        (((x)&0x7FF)<<0)
+#define MCF_USB_EPOUTMPSR_ADDTRANS(x)        (((x)&0x3)<<0xB)
+
+/* Bit definitions and macros for MCF_USB_EPOUTIFR */
+#define MCF_USB_EPOUTIFR_IFNUM(x)            (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_EPOUTSR */
+#define MCF_USB_EPOUTSR_HALT                 (0x1)
+#define MCF_USB_EPOUTSR_ACTIVE               (0x2)
+#define MCF_USB_EPOUTSR_PSTALL               (0x4)
+#define MCF_USB_EPOUTSR_CCOMP                (0x8)
+#define MCF_USB_EPOUTSR_TXZERO               (0x20)
+#define MCF_USB_EPOUTSR_INT                  (0x80)
+
+/* Bit definitions and macros for MCF_USB_EPOUTSFR */
+#define MCF_USB_EPOUTSFR_FRMNUM(x)           (((x)&0x7FF)<<0)
+
+/* Bit definitions and macros for MCF_USB_EPINACR */
+#define MCF_USB_EPINACR_TTYPE(x)             (((x)&0x3)<<0)
+#define MCF_USB_EPINACR_TTYPE_ISOC           (0x1)
+#define MCF_USB_EPINACR_TTYPE_BULK           (0x2)
+#define MCF_USB_EPINACR_TTYPE_INT            (0x3)
+
+/* Bit definitions and macros for MCF_USB_EPINMPSR */
+#define MCF_USB_EPINMPSR_MAXPKTSZ(x)         (((x)&0x7FF)<<0)
+#define MCF_USB_EPINMPSR_ADDTRANS(x)         (((x)&0x3)<<0xB)
+
+/* Bit definitions and macros for MCF_USB_EPINIFR */
+#define MCF_USB_EPINIFR_IFNUM(x)             (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_EPINSR */
+#define MCF_USB_EPINSR_HALT                  (0x1)
+#define MCF_USB_EPINSR_ACTIVE                (0x2)
+#define MCF_USB_EPINSR_PSTALL                (0x4)
+#define MCF_USB_EPINSR_CCOMP                 (0x8)
+#define MCF_USB_EPINSR_TXZERO                (0x20)
+#define MCF_USB_EPINSR_INT                   (0x80)
+
+/* Bit definitions and macros for MCF_USB_EPINSFR */
+#define MCF_USB_EPINSFR_FRMNUM(x)            (((x)&0x7FF)<<0)
+
+/* Bit definitions and macros for MCF_USB_USBSR */
+#define MCF_USB_USBSR_ISOERREP(x)            (((x)&0xF)<<0)
+#define MCF_USB_USBSR_SUSP                   (0x80)
+
+/* Bit definitions and macros for MCF_USB_USBCR */
+#define MCF_USB_USBCR_RESUME                 (0x1)
+#define MCF_USB_USBCR_APPLOCK                (0x2)
+#define MCF_USB_USBCR_RST                    (0x4)
+#define MCF_USB_USBCR_RAMEN                  (0x8)
+#define MCF_USB_USBCR_RAMSPLIT               (0x20)
+
+/* Bit definitions and macros for MCF_USB_DRAMCR */
+#define MCF_USB_DRAMCR_DADR(x)               (((x)&0x3FF)<<0)
+#define MCF_USB_DRAMCR_DSIZE(x)              (((x)&0x7FF)<<0x10)
+#define MCF_USB_DRAMCR_BSY                   (0x40000000)
+#define MCF_USB_DRAMCR_START                 (0x80000000)
+
+/* Bit definitions and macros for MCF_USB_DRAMDR */
+#define MCF_USB_DRAMDR_DDAT(x)               (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_USBISR */
+#define MCF_USB_USBISR_ISOERR                (0x1)
+#define MCF_USB_USBISR_FTUNLCK               (0x2)
+#define MCF_USB_USBISR_SUSP                  (0x4)
+#define MCF_USB_USBISR_RES                   (0x8)
+#define MCF_USB_USBISR_UPDSOF                (0x10)
+#define MCF_USB_USBISR_RSTSTOP               (0x20)
+#define MCF_USB_USBISR_SOF                   (0x40)
+#define MCF_USB_USBISR_MSOF                  (0x80)
+
+/* Bit definitions and macros for MCF_USB_USBIMR */
+#define MCF_USB_USBIMR_ISOERR                (0x1)
+#define MCF_USB_USBIMR_FTUNLCK               (0x2)
+#define MCF_USB_USBIMR_SUSP                  (0x4)
+#define MCF_USB_USBIMR_RES                   (0x8)
+#define MCF_USB_USBIMR_UPDSOF                (0x10)
+#define MCF_USB_USBIMR_RSTSTOP               (0x20)
+#define MCF_USB_USBIMR_SOF                   (0x40)
+#define MCF_USB_USBIMR_MSOF                  (0x80)
+
+/* Bit definitions and macros for MCF_USB_EPSTAT */
+#define MCF_USB_EPSTAT_RST                   (0x1)
+#define MCF_USB_EPSTAT_FLUSH                 (0x2)
+#define MCF_USB_EPSTAT_DIR                   (0x80)
+#define MCF_USB_EPSTAT_BYTECNT(x)            (((x)&0xFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_USB_EPISR */
+#define MCF_USB_EPISR_EOF                    (0x1)
+#define MCF_USB_EPISR_EOT                    (0x4)
+#define MCF_USB_EPISR_FIFOLO                 (0x10)
+#define MCF_USB_EPISR_FIFOHI                 (0x20)
+#define MCF_USB_EPISR_ERR                    (0x40)
+#define MCF_USB_EPISR_EMT                    (0x80)
+#define MCF_USB_EPISR_FU                     (0x100)
+
+/* Bit definitions and macros for MCF_USB_EPIMR */
+#define MCF_USB_EPIMR_EOF                    (0x1)
+#define MCF_USB_EPIMR_EOT                    (0x4)
+#define MCF_USB_EPIMR_FIFOLO                 (0x10)
+#define MCF_USB_EPIMR_FIFOHI                 (0x20)
+#define MCF_USB_EPIMR_ERR                    (0x40)
+#define MCF_USB_EPIMR_EMT                    (0x80)
+#define MCF_USB_EPIMR_FU                     (0x100)
+
+/* Bit definitions and macros for MCF_USB_EPFRCFGR */
+#define MCF_USB_EPFRCFGR_DEPTH(x)            (((x)&0x1FFF)<<0)
+#define MCF_USB_EPFRCFGR_BASE(x)             (((x)&0xFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_USB_EPFDR */
+#define MCF_USB_EPFDR_RX_TXDATA(x)           (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_EPFSR */
+#define MCF_USB_EPFSR_EMT                    (0x10000)
+#define MCF_USB_EPFSR_ALRM                   (0x20000)
+#define MCF_USB_EPFSR_FU                     (0x40000)
+#define MCF_USB_EPFSR_FR                     (0x80000)
+#define MCF_USB_EPFSR_OF                     (0x100000)
+#define MCF_USB_EPFSR_UF                     (0x200000)
+#define MCF_USB_EPFSR_RXW                    (0x400000)
+#define MCF_USB_EPFSR_FAE                    (0x800000)
+#define MCF_USB_EPFSR_FRM(x)                 (((x)&0xF)<<0x18)
+#define MCF_USB_EPFSR_TXW                    (0x40000000)
+#define MCF_USB_EPFSR_IP                     (0x80000000)
+
+/* Bit definitions and macros for MCF_USB_EPFCR */
+#define MCF_USB_EPFCR_COUNTER(x)             (((x)&0xFFFF)<<0)
+#define MCF_USB_EPFCR_TXWMSK                 (0x40000)
+#define MCF_USB_EPFCR_OFMSK                  (0x80000)
+#define MCF_USB_EPFCR_UFMSK                  (0x100000)
+#define MCF_USB_EPFCR_RXWMSK                 (0x200000)
+#define MCF_USB_EPFCR_FAEMSK                 (0x400000)
+#define MCF_USB_EPFCR_IPMSK                  (0x800000)
+#define MCF_USB_EPFCR_GR(x)                  (((x)&0x7)<<0x18)
+#define MCF_USB_EPFCR_FRM                    (0x8000000)
+#define MCF_USB_EPFCR_TMR                    (0x10000000)
+#define MCF_USB_EPFCR_WFR                    (0x20000000)
+#define MCF_USB_EPFCR_SHAD                   (0x80000000)
+
+/* Bit definitions and macros for MCF_USB_EPFAR */
+#define MCF_USB_EPFAR_ALRMP(x)               (((x)&0xFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_EPFRP */
+#define MCF_USB_EPFRP_RP(x)                  (((x)&0xFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_EPFWP */
+#define MCF_USB_EPFWP_WP(x)                  (((x)&0xFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_EPLRFP */
+#define MCF_USB_EPLRFP_LRFP(x)               (((x)&0xFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_EPLWFP */
+#define MCF_USB_EPLWFP_LWFP(x)               (((x)&0xFFF)<<0)
+
+
+#endif /* __MCF5475_USB_H__ */
--- a/tos/fpga_test/include/MCF5475_XLB.h
+++ b/tos/fpga_test/include/MCF5475_XLB.h
@@ -0,0 +1,101 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_XLB_H__
+#define __MCF5475_XLB_H__
+
+
+/*********************************************************************
+*
+* XL Bus Arbiter (XLB)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_XLB_XARB_CFG                     (*(volatile uint32_t*)(&_MBAR[0x240]))
+#define MCF_XLB_XARB_VER                     (*(volatile uint32_t*)(&_MBAR[0x244]))
+#define MCF_XLB_XARB_SR                      (*(volatile uint32_t*)(&_MBAR[0x248]))
+#define MCF_XLB_XARB_IMR                     (*(volatile uint32_t*)(&_MBAR[0x24C]))
+#define MCF_XLB_XARB_ADRCAP                  (*(volatile uint32_t*)(&_MBAR[0x250]))
+#define MCF_XLB_XARB_SIGCAP                  (*(volatile uint32_t*)(&_MBAR[0x254]))
+#define MCF_XLB_XARB_ADRTO                   (*(volatile uint32_t*)(&_MBAR[0x258]))
+#define MCF_XLB_XARB_DATTO                   (*(volatile uint32_t*)(&_MBAR[0x25C]))
+#define MCF_XLB_XARB_BUSTO                   (*(volatile uint32_t*)(&_MBAR[0x260]))
+#define MCF_XLB_XARB_PRIEN                   (*(volatile uint32_t*)(&_MBAR[0x264]))
+#define MCF_XLB_XARB_PRI                     (*(volatile uint32_t*)(&_MBAR[0x268]))
+
+
+/* Bit definitions and macros for MCF_XLB_XARB_CFG */
+#define MCF_XLB_XARB_CFG_AT                  (0x2)
+#define MCF_XLB_XARB_CFG_DT                  (0x4)
+#define MCF_XLB_XARB_CFG_BA                  (0x8)
+#define MCF_XLB_XARB_CFG_PM(x)               (((x)&0x3)<<0x5)
+#define MCF_XLB_XARB_CFG_SP(x)               (((x)&0x7)<<0x8)
+#define MCF_XLB_XARB_CFG_PLDIS               (0x80000000)
+
+/* Bit definitions and macros for MCF_XLB_XARB_VER */
+#define MCF_XLB_XARB_VER_VER(x)              (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_XLB_XARB_SR */
+#define MCF_XLB_XARB_SR_AT                   (0x1)
+#define MCF_XLB_XARB_SR_DT                   (0x2)
+#define MCF_XLB_XARB_SR_BA                   (0x4)
+#define MCF_XLB_XARB_SR_TTM                  (0x8)
+#define MCF_XLB_XARB_SR_ECW                  (0x10)
+#define MCF_XLB_XARB_SR_TTR                  (0x20)
+#define MCF_XLB_XARB_SR_TTA                  (0x40)
+#define MCF_XLB_XARB_SR_MM                   (0x80)
+#define MCF_XLB_XARB_SR_SEA                  (0x100)
+
+/* Bit definitions and macros for MCF_XLB_XARB_IMR */
+#define MCF_XLB_XARB_IMR_ATE                 (0x1)
+#define MCF_XLB_XARB_IMR_DTE                 (0x2)
+#define MCF_XLB_XARB_IMR_BAE                 (0x4)
+#define MCF_XLB_XARB_IMR_TTME                (0x8)
+#define MCF_XLB_XARB_IMR_ECWE                (0x10)
+#define MCF_XLB_XARB_IMR_TTRE                (0x20)
+#define MCF_XLB_XARB_IMR_TTAE                (0x40)
+#define MCF_XLB_XARB_IMR_MME                 (0x80)
+#define MCF_XLB_XARB_IMR_SEAE                (0x100)
+
+/* Bit definitions and macros for MCF_XLB_XARB_ADRCAP */
+#define MCF_XLB_XARB_ADRCAP_ADRCAP(x)        (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_XLB_XARB_SIGCAP */
+#define MCF_XLB_XARB_SIGCAP_TT(x)            (((x)&0x1F)<<0)
+#define MCF_XLB_XARB_SIGCAP_TBST             (0x20)
+#define MCF_XLB_XARB_SIGCAP_TSIZ(x)          (((x)&0x7)<<0x7)
+
+/* Bit definitions and macros for MCF_XLB_XARB_ADRTO */
+#define MCF_XLB_XARB_ADRTO_ADRTO(x)          (((x)&0xFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_XLB_XARB_DATTO */
+#define MCF_XLB_XARB_DATTO_DATTO(x)          (((x)&0xFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_XLB_XARB_BUSTO */
+#define MCF_XLB_XARB_BUSTO_BUSTO(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_XLB_XARB_PRIEN */
+#define MCF_XLB_XARB_PRIEN_M0                (0x1)
+#define MCF_XLB_XARB_PRIEN_M2                (0x4)
+#define MCF_XLB_XARB_PRIEN_M3                (0x8)
+
+/* Bit definitions and macros for MCF_XLB_XARB_PRI */
+#define MCF_XLB_XARB_PRI_M0P(x)              (((x)&0x7)<<0)
+#define MCF_XLB_XARB_PRI_M2P(x)              (((x)&0x7)<<0x8)
+#define MCF_XLB_XARB_PRI_M3P(x)              (((x)&0x7)<<0xC)
+
+
+#endif /* __MCF5475_XLB_H__ */
--- a/tos/fpga_test/include/bas_printf.h
+++ b/tos/fpga_test/include/bas_printf.h
@@ -0,0 +1,35 @@
+/*
+ *
+ * This file is part of BaS_gcc.
+ *
+ * BaS_gcc is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * BaS_gcc is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with BaS_gcc.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ */
+
+#ifndef _BAS_PRINTF_H_
+#define _BAS_PRINTF_H_
+#include <stdarg.h>
+#include <stddef.h>
+
+extern void xvsnprintf(char *str, size_t size, const char *fmt, va_list va);
+extern void xvprintf(const char *fmt, va_list va);
+extern void xprintf(const char *fmt, ...);
+extern void xsnprintf(char *str, size_t size, const char *fmt, ...);
+extern void xputchar(int c);
+extern int sprintf(char *str, const char *format, ...);
+
+
+extern void display_progress(void);
+extern void hexdump(volatile uint8_t buffer[], int size);
+#endif /* _BAS_PRINTF_H_ */
--- a/tos/fpga_test/include/bas_string.h
+++ b/tos/fpga_test/include/bas_string.h
@@ -0,0 +1,47 @@
+/*
+ * bas_string.h
+ *
+ * This file is part of BaS_gcc.
+ *
+ * BaS_gcc is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * BaS_gcc is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with BaS_gcc.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ *  Created on: 26.02.2013
+ *      Author: Markus Fröschle
+ */
+
+#ifndef BAS_STRING_H_
+#define BAS_STRING_H_
+
+#include <stddef.h>
+
+extern int strncmp(const char *s1, const char *s2, size_t max);
+extern char *strcpy(char *dst, const char *src);
+char *strncpy(char *dst, const char *src, size_t max);
+extern int strcmp(const char *s1, const char *s2);
+extern size_t strlen(const char *str);
+extern char *strcat(char *dst, const char *src);
+extern char *strncat(char *dst, const char *src, size_t max);
+extern int atoi(const char *c);
+extern void *memcpy(void *dst, const void *src, size_t n);
+extern void *memset(void *s, int c, size_t n);
+extern int memcmp(const void *s1, const void *s2, size_t max);
+extern void bzero(void *s, size_t n);
+
+#define isdigit(c)	(((c) >= '0') && ((c) <= '9'))
+#define isupper(c)	((c) >= 'A' && ((c) <= 'Z'))
+#define islower(c)	((c) >= 'a' && ((c) <= 'z'))
+#define isalpha(c)	(isupper((c)) || islower(c))
+#define tolower(c)	(isupper(c) ? ((c) + 'a' - 'A') : (c))
+
+#endif /* BAS_STRING_H_ */
--- a/tos/fpga_test/include/driver_vec.h
+++ b/tos/fpga_test/include/driver_vec.h
@@ -0,0 +1,125 @@
+/*
+ * driver_vec.h
+ *
+ * Interface for exposure of BaS drivers to the OS
+ *
+ * This file is part of BaS_gcc.
+ *
+ * BaS_gcc is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * BaS_gcc is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with BaS_gcc.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ *  Created on: 24.10.2013
+ *      Author: Markus Fröschle
+ */
+
+#ifndef _DRIVER_VEC_H_
+#define _DRIVER_VEC_H_
+
+
+enum driver_type
+{
+	END_OF_DRIVERS,		/* marks end of driver list */
+	BLOCKDEV_DRIVER,
+	CHARDEV_DRIVER,
+	VIDEO_DRIVER,
+	XHDI_DRIVER,
+	MCD_DRIVER,
+};
+
+struct generic_driver_interface
+{
+	uint32_t (*init)(void);
+	uint32_t (*read)(void *buf, size_t count);
+	uint32_t (*write)(const void *buf, size_t count);
+	uint32_t (*ioctl)(uint32_t request, ...);
+};
+
+
+/* Chained buffer descriptor */
+typedef volatile struct MCD_bufDesc_struct MCD_bufDesc;
+struct MCD_bufDesc_struct {
+	uint32_t flags;         /* flags describing the DMA */
+    uint32_t csumResult;    /* checksum from checksumming performed since last checksum reset */
+	int8_t  *srcAddr;      /* the address to move data from */
+	int8_t  *destAddr;     /* the address to move data to */
+	int8_t  *lastDestAddr; /* the last address written to */
+    uint32_t dmaSize;       /* the number of bytes to transfer independent of the transfer size */
+    MCD_bufDesc *next; /* next buffer descriptor in chain */
+    uint32_t info;          /* private information about this descriptor;  DMA does not affect it */
+};
+
+/* Progress Query struct */
+typedef volatile struct MCD_XferProg_struct {
+	int8_t *lastSrcAddr;         /* the most-recent or last, post-increment source address */
+	int8_t *lastDestAddr;        /* the most-recent or last, post-increment destination address */
+	uint32_t  dmaSize;            /* the amount of data transferred for the current buffer */
+	MCD_bufDesc *currBufDesc;/* pointer to the current buffer descriptor being DMAed */
+} MCD_XferProg;
+
+struct dma_driver_interface
+{
+	int32_t version;
+	int32_t magic;
+	int32_t (*dma_set_initiator)(int initiator);
+	uint32_t (*dma_get_initiator)(int requestor);
+	void (*dma_free_initiator)(int requestor);
+	int32_t (*dma_set_channel)(int requestor, void (*handler)(void));
+	int (*dma_get_channel)(int requestor);
+	void (*dma_free_channel)(int requestor);
+	void (*dma_clear_channel)(int channel);
+	int (*MCD_startDma)(int channel, int8_t *srcAddr, int16_t srcIncr, int8_t *destAddr, int16_t destIncr,
+						uint32_t dmaSize, uint32_t xferSize, uint32_t initiator, int32_t priority, uint32_t flags,
+						uint32_t funcDesc);
+	int (*MCD_dmaStatus)(int channel);
+	int (*MCD_XferProgrQuery)(int channel, MCD_XferProg *progRep);
+	int (*MCD_killDma)(int channel);
+	int (*MCD_continDma)(int channel);
+	int (*MCD_pauseDma)(int channel);
+	int (*MCD_resumeDma)(int channel);
+	int (*MCD_csumQuery)(int channel, uint32_t *csum);
+	void *(*dma_malloc)(long amount);
+	int (*dma_free)(void *addr);
+};
+	
+struct xhdi_driver_interface
+{
+	uint32_t (*xhdivec)();
+};
+
+union interface
+{
+	struct generic_driver_interface *gdi;
+	struct xhdi_driver_interface *xhdi;
+	struct dma_driver_interface *dma;
+};
+
+struct generic_interface
+{
+	enum driver_type type;
+	char name[16];
+	char description[64];
+	int version;
+	int revision;
+	union interface interface;
+};
+
+struct driver_table
+{
+	uint32_t bas_version;
+	uint32_t bas_revision;
+	uint32_t (*remove_handler)();			/* calling this will disable the BaS' hook into trap #0 */
+	struct generic_interface *interfaces;
+};
+
+
+#endif /* _DRIVER_VEC_H_ */
--- a/tos/fpga_test/sources/bas_printf.c
+++ b/tos/fpga_test/sources/bas_printf.c
@@ -0,0 +1,457 @@
+/*
+ * tc.printf.c: A public-domain, minimal printf/sprintf routine that prints
+ *         through the putchar() routine.  Feel free to use for
+ *         anything...  -- 7/17/87 Paul Placeway
+ */
+/*-
+ * Copyright (c) 1980, 1991 The Regents of the University of California.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ * 3. Neither the name of the University nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+
+#include <stdarg.h>
+#include "MCF5475.h"
+#include "bas_printf.h"
+#include "bas_string.h"
+
+/*
+ * Lexical definitions.
+ *
+ * All lexical space is allocated dynamically.
+ * The eighth/sixteenth bit of characters is used to prevent recognition,
+ * and eventually stripped.
+ */
+#define META        0200
+#define ASCII       0177
+#define QUOTE       ((char) 0200)   /* Eighth char bit used for 'ing */
+#define TRIM        0177    /* Mask to strip quote bit */
+#define UNDER       0000000 /* No extra bits to do both */
+#define BOLD        0000000 /* Bold flag */
+#define STANDOUT    META    /* Standout flag */
+#define LITERAL     0000000 /* Literal character flag */
+#define ATTRIBUTES  0200    /* The bits used for attributes */
+#define CHAR        0000177 /* Mask to mask out the character */
+
+#define INF 32766       /* should be bigger than any field to print */
+
+static char snil[] = "(nil)";
+
+void xputchar(int c)
+{
+    __asm__ __volatile__
+    (
+            ".extern        printf_helper\n\t"
+            "move.b         %0,d0\n\t"
+            "bsr            printf_helper\n\t"
+            /* output */:
+            /* input */: "r" (c)
+            /* clobber */: "d0","d2","a0","memory"
+    );
+}
+
+static void doprnt(void (*addchar)(int), const char *sfmt, va_list ap)
+{
+    char buf[128];
+    char *bp;
+    const char *f;
+    float flt;
+    long l;
+    unsigned long u;
+    int i;
+    int fmt;
+    unsigned char pad = ' ';
+    int flush_left = 0;
+    int f_width = 0;
+    int prec = INF;
+    int hash = 0;
+    int do_long = 0;
+    int sign = 0;
+    int attributes = 0;
+
+    f = sfmt;
+    for (; *f; f++)
+    {
+        if (*f != '%')
+        {
+            /* then just out the char */
+            (*addchar)((int) (((unsigned char) *f) | attributes));
+        }
+        else
+        {
+            f++; /* skip the % */
+
+            if (*f == '-')
+            { /* minus: flush left */
+                flush_left = 1;
+                f++;
+            }
+
+            if (*f == '0' || *f == '.')
+            {
+                /* padding with 0 rather than blank */
+                pad = '0';
+                f++;
+            }
+            if (*f == '*')
+            {
+                /* field width */
+                f_width = va_arg(ap, int);
+                f++;
+            }
+            else if (isdigit((unsigned char)*f))
+            {
+                f_width = atoi(f);
+                while (isdigit((unsigned char)*f))
+                    f++; /* skip the digits */
+            }
+
+            if (*f == '.')
+            { /* precision */
+                f++;
+                if (*f == '*')
+                {
+                    prec = va_arg(ap, int);
+                    f++;
+                }
+                else if (isdigit((unsigned char)*f))
+                {
+                    prec = atoi(f);
+                    while (isdigit((unsigned char)*f))
+                        f++; /* skip the digits */
+                }
+            }
+
+            if (*f == '#')
+            { /* alternate form */
+                hash = 1;
+                f++;
+            }
+
+            if (*f == 'l')
+            { /* long format */
+                do_long++;
+                f++;
+                if (*f == 'l')
+                {
+                    do_long++;
+                    f++;
+                }
+            }
+
+            fmt = (unsigned char) *f;
+            if (fmt != 'S' && fmt != 'Q' && isupper(fmt))
+            {
+                do_long = 1;
+                fmt = tolower(fmt);
+            }
+            bp = buf;
+            switch (fmt)
+            { /* do the format */
+            case 'd':
+                switch (do_long)
+                {
+                case 0:
+                    l = (long) (va_arg(ap, int));
+                    break;
+                case 1:
+                default:
+                    l = va_arg(ap, long);
+                    break;
+                }
+
+                if (l < 0)
+                {
+                    sign = 1;
+                    l = -l;
+                }
+                do
+                {
+                    *bp++ = (char) (l % 10) + '0';
+                } while ((l /= 10) > 0);
+                if (sign)
+                    *bp++ = '-';
+                f_width = f_width - (int) (bp - buf);
+                if (!flush_left)
+                    while (f_width-- > 0)
+                        (*addchar)((int) (pad | attributes));
+                for (bp--; bp >= buf; bp--)
+                    (*addchar)((int) (((unsigned char) *bp) | attributes));
+                if (flush_left)
+                    while (f_width-- > 0)
+                        (*addchar)((int) (' ' | attributes));
+                break;
+
+         case 'f':
+            /* this is actually more than stupid, but does work for now */
+            flt = (float) (va_arg(ap, double)); /* beware: va_arg() extends float to double! */
+            if (flt < 0)
+            {
+               sign = 1;
+               flt = -flt;
+            }
+            {
+               int quotient, remainder;
+
+               quotient = (int) flt;
+               remainder = (flt - quotient) * 10E5;
+
+               for (i = 0; i < 6; i++)
+               {
+                  *bp++ = (char) (remainder % 10) + '0';
+                  remainder /= 10;
+               }
+               *bp++ = '.';
+               do
+               {
+                  *bp++ = (char) (quotient % 10) + '0';
+               } while ((quotient /= 10) > 0);
+               if (sign)
+                  *bp++ = '-';
+               f_width = f_width - (int) (bp - buf);
+               if (!flush_left)
+               while (f_width-- > 0)
+                  (*addchar)((int) (pad | attributes));
+               for (bp--; bp >= buf; bp--)
+                  (*addchar)((int) (((unsigned char) *bp) | attributes));
+               if (flush_left)
+                  while (f_width-- > 0)
+                     (*addchar)((int) (' ' | attributes));
+            }
+            break;
+
+            case 'p':
+                do_long = 1;
+                hash = 1;
+                fmt = 'x';
+                /* no break */
+            case 'o':
+            case 'x':
+            case 'u':
+                switch (do_long)
+                {
+                case 0:
+                    u = (unsigned long) (va_arg(ap, unsigned int));
+                    break;
+                case 1:
+                default:
+                    u = va_arg(ap, unsigned long);
+                    break;
+                }
+                if (fmt == 'u')
+                { /* unsigned decimal */
+                    do
+                    {
+                        *bp++ = (char) (u % 10) + '0';
+                    } while ((u /= 10) > 0);
+                }
+                else if (fmt == 'o')
+                { /* octal */
+                    do
+                    {
+                        *bp++ = (char) (u % 8) + '0';
+                    } while ((u /= 8) > 0);
+                    if (hash)
+                        *bp++ = '0';
+                }
+                else if (fmt == 'x')
+                { /* hex */
+                    do
+                    {
+                        i = (int) (u % 16);
+                        if (i < 10)
+                            *bp++ = i + '0';
+                        else
+                            *bp++ = i - 10 + 'a';
+                    } while ((u /= 16) > 0);
+                    if (hash)
+                    {
+                        *bp++ = 'x';
+                        *bp++ = '0';
+                    }
+                }
+                i = f_width - (int) (bp - buf);
+                if (!flush_left)
+                    while (i-- > 0)
+                        (*addchar)((int) (pad | attributes));
+                for (bp--; bp >= buf; bp--)
+                    (*addchar)((int) (((unsigned char) *bp) | attributes));
+                if (flush_left)
+                    while (i-- > 0)
+                        (*addchar)((int) (' ' | attributes));
+                break;
+
+            case 'c':
+                i = va_arg(ap, int);
+                (*addchar)((int) (i | attributes));
+                break;
+
+            case 'S':
+            case 'Q':
+            case 's':
+            case 'q':
+                bp = va_arg(ap, char *);
+                if (!bp)
+                    bp = snil;
+                f_width = f_width - strlen((char *) bp);
+                if (!flush_left)
+                    while (f_width-- > 0)
+                        (*addchar)((int) (pad | attributes));
+                for (i = 0; *bp && i < prec; i++)
+                {
+                    if (fmt == 'q' && (*bp & QUOTE))
+                        (*addchar)((int) ('\\' | attributes));
+                    (*addchar)(
+                            (int) (((unsigned char) *bp & TRIM) | attributes));
+                    bp++;
+                }
+                if (flush_left)
+                    while (f_width-- > 0)
+                        (*addchar)((int) (' ' | attributes));
+                break;
+
+            case 'a':
+                attributes = va_arg(ap, int);
+                break;
+
+            case '%':
+                (*addchar)((int) ('%' | attributes));
+                break;
+
+            default:
+                break;
+            }
+            flush_left = 0, f_width = 0, prec = INF, hash = 0, do_long = 0;
+            sign = 0;
+            pad = ' ';
+        }
+    }
+}
+
+static char *xstring, *xestring;
+
+void xaddchar(int c)
+{
+    if (xestring == xstring)
+        *xstring = '\0';
+    else
+        *xstring++ = (char) c;
+}
+
+int sprintf(char *str, const char *format, ...)
+{
+    va_list va;
+    va_start(va, format);
+
+    xstring = str;
+
+    doprnt(xaddchar, format, va);
+    va_end(va);
+    *xstring++ = '\0';
+
+    return 0;
+}
+
+void xsnprintf(char *str, size_t size, const char *fmt, ...)
+{
+    va_list va;
+    va_start(va, fmt);
+
+    xstring = str;
+    xestring = str + size - 1;
+    doprnt(xaddchar, fmt, va);
+    va_end(va);
+    *xstring++ = '\0';
+}
+
+void xprintf(const char *fmt, ...)
+{
+    va_list va;
+    va_start(va, fmt);
+    doprnt(xputchar, fmt, va);
+    va_end(va);
+}
+
+void xvprintf(const char *fmt, va_list va)
+{
+    doprnt(xputchar, fmt, va);
+}
+
+void xvsnprintf(char *str, size_t size, const char *fmt, va_list va)
+{
+    xstring = str;
+    xestring = str + size - 1;
+    doprnt(xaddchar, fmt, va);
+    *xstring++ = '\0';
+}
+
+
+void display_progress()
+{
+    static int _progress_index;
+    char progress_char[] = "|/-\\";
+
+    xputchar(progress_char[_progress_index++ % strlen(progress_char)]);
+    xputchar('\r');
+}
+
+void hexdump(volatile uint8_t buffer[], int size)
+{
+   int i;
+   int line = 0;
+   volatile uint8_t *bp = buffer;
+
+   while (bp < buffer + size) {
+      volatile uint8_t *lbp = bp;
+
+      xprintf("%08x  ", line);
+
+      for (i = 0; i < 16; i++) {
+          uint8_t c = *lbp++;
+         if (bp + i > buffer + size) {
+            break;
+         }
+         xprintf("%02x ", c);
+      }
+
+      lbp = bp;
+      for (i = 0; i < 16; i++) {
+         volatile int8_t c = *lbp++;
+
+         if (bp + i > buffer + size) {
+            break;
+         }
+         if (c > ' ' && c < '~') {
+            xprintf("%c", c);
+         } else {
+            xprintf(".");
+         }
+      }
+      xprintf("\r\n");
+
+      bp += 16;
+      line += 16;
+   }
+}
--- a/tos/fpga_test/sources/bas_string.c
+++ b/tos/fpga_test/sources/bas_string.c
@@ -0,0 +1,156 @@
+/*
+ * bas_string.c
+ *
+ * This file is part of BaS_gcc.
+ *
+ * BaS_gcc is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * BaS_gcc is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with BaS_gcc.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ *  Created on: 26.02.2013
+ *      Author: Markus Fröschle
+ */
+
+#include "bas_types.h"
+#include <stdint.h>
+#include "bas_string.h"
+
+void *memcpy(void *dst, const void *src, size_t n)
+{
+    uint8_t *to = dst;
+
+    while (to < (uint8_t *) dst + n)
+        *to++ = * (uint8_t *) src++;
+
+    return dst;
+}
+
+void bzero(void *s, size_t n)
+{
+    size_t i;
+
+    for (i = 0; i < n; i++)
+        ((unsigned char *) s)[i] = '\0';
+}
+
+void *memset(void *s, int c, size_t n)
+{
+    uint8_t *dst = s;
+
+    do
+    {
+        *dst++ = c;
+    } while ((dst - (uint8_t *) s) < n);
+
+    return s;
+}
+
+
+int memcmp(const void *s1, const void *s2, size_t max)
+{
+    int i;
+    int cmp;
+
+    for (i = 0; i < max; i++)
+    {
+        cmp = (* (const char *) s1 - * (const char *) s2);
+        if (cmp != 0) return cmp;
+    }
+    return cmp;
+}
+
+int strcmp(const char *s1, const char *s2)
+{
+    int i;
+    int cmp;
+
+    for (i = 0; *s1++ && *s2++; i++)
+    {
+        cmp = (*s1 - *s2);
+        if (cmp != 0) return cmp;
+    }
+    return cmp;
+}
+
+int strncmp(const char *s1, const char *s2, size_t max)
+{
+    int i;
+    int cmp;
+
+    for (i = 0; i < max && *s1++ && *s2++; i++);
+    {
+        cmp = (*s1 - *s2);
+        if (cmp != 0) return cmp;
+    }
+    return cmp;
+}
+
+char *strcpy(char *dst, const char *src)
+{
+    char *ptr = dst;
+
+    while ((*dst++ = *src++) != '\0');
+    return ptr;
+}
+
+char *strncpy(char *dst, const char *src, size_t max)
+{
+    char *ptr = dst;
+
+    while ((*dst++ = *src++) != '\0' && max-- >= 0);
+    return ptr;
+}
+
+int atoi(const char *c)
+{
+    int value = 0;
+    while (isdigit(*c))
+    {
+        value *= 10;
+        value += (int) (*c - '0');
+        c++;
+    }
+    return value;
+}
+
+size_t strlen(const char *s)
+{
+    const char *start = s;
+
+    while (*s++);
+
+    return s - start - 1;
+}
+
+
+char *strcat(char *dst, const char *src)
+{
+    char *ret = dst;
+    dst = &dst[strlen(dst)];
+    while ((*dst++ = *src++) != '\0');
+    return ret;
+}
+
+char *strncat(char *dst, const char *src, size_t max)
+{
+    size_t i;
+    char *ret = dst;
+
+    dst = &dst[strlen(dst)];
+    for (i = 0; i < max && *src; i++)
+    {
+        *dst++ = *src++;
+    }
+    *dst++ = '\0';
+
+    return ret;
+}
--- a/tos/fpga_test/sources/fpga_test.c
+++ b/tos/fpga_test/sources/fpga_test.c
@@ -0,0 +1,152 @@
+#include <stdio.h>
+#include <mint/osbind.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "bas_printf.h"
+#include "MCF5475.h"
+#include "driver_vec.h"
+
+#define FPGA_CONFIG                         (1 << 2)
+#define FPGA_CONF_DONE                      (1 << 5)
+
+#define SRAM1_START     0xff101000
+#define SRAM1_END       SRAM1_START + 0x1000
+#define SAFE_STACK      SRAM1_END - 4
+
+#define NOP() __asm__ __volatile__("nop\n\t" : : : "memory")
+
+#define SYSCLK 132000
+
+long bas_start = 0xe0000000;
+extern volatile uint32_t _VRAM[];
+
+volatile int32_t time, start, end;
+int i;
+
+void do_tests(void)
+{
+    volatile unsigned long *t1 = (volatile unsigned long *) 0xf0000000;
+    volatile unsigned short *t2 = (volatile unsigned short *) 0xf0000000;
+    volatile unsigned short *t3 = (volatile unsigned short *) 0xf0000002;
+    long value = 0;
+
+    while (1)
+    {
+        *t1 = value;
+        *t2 = (short) value;
+        *t3 = (short) (value >> 16);
+        xprintf("W: 0x%lx R: 0x%lx W: 0x%04x R: 0x%04x W: 0x%04x R: 0x%04x\r\n", value, *t1,
+                 (unsigned short) value, *t2, (unsigned short)(value >> 16), *t3);
+        value++;
+    }
+}
+
+
+void wait_for_jtag(void)
+{
+    long i;
+
+    /* set supervisor stack to end of SRAM1 */
+    __asm__ __volatile__ (
+        "       move    #0x2700,sr\n\t"         /* disable interrupts */
+        "       move.l  %[stack],d0\n\t"        /* 4KB on-chip core SRAM1 */
+        "       move.l  d0,sp\n\t"              /* set stack pointer */
+        :
+        : [stack] "i" (SAFE_STACK)
+        : "d0", "cc"    /* clobber */
+    );
+
+    MCF_EPORT_EPIER = 0x0;              /* disable EPORT interrupts */
+    MCF_INTC_IMRL = 0xffffffff;
+    MCF_INTC_IMRH = 0xffffffff;         /* disable interrupt controller */
+
+    MCF_MMU_MMUCR &= ~MCF_MMU_MMUCR_EN; /* disable MMU */
+
+    xprintf("relocated supervisor stack, disabled interrupts and disabled MMU\r\n");
+
+    /*
+     * configure FEC1L port directions to enable external JTAG configuration download to FPGA
+     */
+    MCF_GPIO_PDDR_FEC1L = 0 |
+                          MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4;  /* bit 4 = LED => output */
+                                                            /* all other bits = input */
+
+    /*
+     * configure DSPI_CS3 as GPIO input to avoid the MCU driving against the FPGA blink
+     */
+    MCF_PAD_PAR_DSPI &= ~MCF_PAD_PAR_DSPI_PAR_CS3(MCF_PAD_PAR_DSPI_PAR_CS3_DSPICS3);
+    /*
+     * now that GPIO ports have been switched to input, we can poll for FPGA config
+     * started from the JTAG interface (CONF_DONE goes low) and finish (CONF_DONE goes high)
+     */
+    xprintf("waiting for JTAG configuration start\r\n");
+    while ((MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE));       /* wait for JTAG config load started */
+
+    xprintf("waiting for JTAG configuration to finish\r\n");
+    while (!(MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE));     /* wait for JTAG config load finished */
+
+    xprintf("JTAG configuration finished.\r\n");
+
+    /* wait */
+    xprintf("wait a little to let things settle...\r\n");
+    for (i = 0; i < 100000L; i++);
+
+    xprintf("disable caches\r\n");
+    __asm__ __volatile(
+                "move.l     #0x01000000,d0      \r\n"
+                "movec      d0,CACR             \r\n"
+                : /* no output */
+                : /* no input */
+                : "d0", "memory");
+
+    /* begin of tests */
+
+    do_tests();
+
+    xprintf("wait a little to let things settle...\r\n");
+    for (i = 0; i < 100000L; i++);
+
+    xprintf("INFO: endless loop now. Press reset to reboot\r\n");
+    while (1)
+        ;
+}
+
+int main(int argc, char *argv[])
+{
+    printf("FPGA JTAG configuration support\r\n");
+    printf("test FPGA DDR RAM controller\r\n");
+    printf("\xbd 2014 M. F\x94schle\r\n");
+
+    printf("You may now savely load a new FPGA configuration through the JTAG interface\r\n"
+           "and your Firebee will reboot once finished using that new configuration.\r\n");
+    if (argc == 2)
+    {
+        /*
+         * we got an argument. This is supposed to be the address that we need to jump to after JTAG
+         * configuration has been finished. Meant to support BaS in RAM testing
+         */
+        char *addr_str = argv[1];
+        char *addr = NULL;
+        char *end = NULL;
+
+        addr = (char *) strtol(addr_str, &end, 16);
+        if (addr != NULL && addr <= (char *) 0xe0000000 && addr >= (char *) 0x10000000)
+        {
+            /*
+             * seems to be a valid address
+             */
+            bas_start = (long) addr;
+
+            printf("BaS start address set to %p\r\n", (void *) bas_start);
+        }
+        else
+        {
+            printf("\r\nNote: BaS start address %p not valid. Stick to %p.\r\n", addr, (void *) bas_start);
+        }
+    }
+    Supexec(wait_for_jtag);
+
+    return 0;       /* just to make the compiler happy, we will never return */
+}
+
--- a/tos/fpga_test/sources/printf_helper.S
+++ b/tos/fpga_test/sources/printf_helper.S
@@ -0,0 +1,38 @@
+/*
+ * printf_helper.S
+ *
+ * assembler trampoline to let printf (compiled -mpcrel) indirectly reference __MBAR
+ *
+ * This file is part of BaS_gcc.
+ *
+ * BaS_gcc is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * BaS_gcc is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with BaS_gcc.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * Copyright 2010 - 2012 F. Aschwanden
+ * Copyright 2011 - 2012 V. Riviere
+ * Copyright 2012 - 2025 M. Froeschle
+ */
+
+
+	.globl	printf_helper
+
+printf_helper:
+	.extern	__MBAR
+
+.wait_txready:
+	move.w	__MBAR+0x8604,d2		// PSCSCR0 status register
+	btst	#10,d2				// space left in TX fifo?
+	beq.s	.wait_txready			// no, loop
+	lea	__MBAR+0x860C,a0		// PSCSTB0 transmitter buffer register
+	move.b	d0,(a0)				// send byte
+	rts
--- a/tos/fpga_test/sources/vmem_test.c
+++ b/tos/fpga_test/sources/vmem_test.c
@@ -0,0 +1,390 @@
+#include <stdio.h>
+#include <mint/osbind.h>
+#include <stdint.h>
+#include <stdbool.h>
+
+#include "bas_printf.h"
+#include "MCF5475.h"
+#include "driver_vec.h"
+
+#define FPGA_CONFIG                         (1 << 2)
+#define FPGA_CONF_DONE                      (1 << 5)
+
+#define SRAM1_START     0xff101000
+#define SRAM1_END       SRAM1_START + 0x1000
+#define SAFE_STACK      SRAM1_END - 4
+
+#define NOP() __asm__ __volatile__("nop\n\t" : : : "memory")
+
+#define SYSCLK 132000
+
+long bas_start = 0xe0000000;
+extern volatile uint32_t _VRAM[];
+
+volatile int32_t time, start, end;
+int i;
+
+static void wait_pll(void)
+{
+    int32_t trgt = MCF_SLT0_SCNT - 100000;
+    do
+    {
+        ;
+    } while ((* (volatile int16_t *) 0xf0000800 < 0) && MCF_SLT0_SCNT > trgt);
+}
+
+static volatile uint8_t *pll_base = (volatile uint8_t *) 0xf0000600;
+
+static void init_pll(void)
+{
+    xprintf("FPGA PLL initialization: ");
+
+    wait_pll();
+    * (volatile uint16_t *) (pll_base + 0x48) = 27;     /* loopfilter  r */
+
+    wait_pll();
+    * (volatile uint16_t *) (pll_base + 0x08) = 1;      /* charge pump 1 */
+
+    wait_pll();
+    * (volatile uint16_t *) (pll_base + 0x00) = 12;     /* N counter high = 12 */
+
+    wait_pll();
+    * (volatile uint16_t *) (pll_base + 0x40) = 12;     /* N counter low = 12 */
+
+    wait_pll();
+    * (volatile uint16_t *) (pll_base + 0x114) = 1;     /* ck1 bypass */
+
+    wait_pll();
+    * (volatile uint16_t *) (pll_base + 0x118) = 1;     /* ck2 bypass */
+
+    wait_pll();
+    * (volatile uint16_t *) (pll_base + 0x11c) = 1;     /* ck3 bypass */
+
+    wait_pll();
+    * (volatile uint16_t *) (pll_base + 0x10) = 1;      /* ck0 high  = 1 */
+
+    wait_pll();
+    * (volatile uint16_t *) (pll_base + 0x50) = 1;      /* ck0 low = 1 */
+
+    wait_pll();
+    * (volatile uint16_t *) (pll_base + 0x144) = 1;     /* M odd division */
+
+    wait_pll();
+    * (volatile uint16_t *) (pll_base + 0x44) = 1;      /* M low = 1 */
+
+    wait_pll();
+    * (volatile uint16_t *) (pll_base + 0x04) = 145;    /* M high = 145 = 146 MHz */
+
+    wait_pll();
+
+    * (volatile uint8_t *) 0xf0000800 = 0;              /* set */
+
+    xprintf("finished\r\n");
+}
+
+/*
+ * INIT VIDEO DDR RAM
+ */
+static void init_video_ddr(void)
+{
+    xprintf("init video RAM: ");
+
+    * (volatile uint16_t *) 0xf0000400 = 0xb;   /* set cke = 1, cs=1, config = 1 */
+    NOP();
+
+    _VRAM[0] = 0x00050400; /* IPALL */
+    NOP();
+
+    _VRAM[0] = 0x00072000; /* load EMR pll on */
+    NOP();
+
+    _VRAM[0] = 0x00070122; /* load MR: reset pll, cl=2, burst=4lw */
+    NOP();
+
+    _VRAM[0] = 0x00050400; /* IPALL */
+    NOP();
+
+    _VRAM[0] = 0x00060000; /* auto refresh */
+    NOP();
+
+    _VRAM[0] = 0x00060000; /* auto refresh */
+    NOP();
+
+    /* FIXME: what's this? */
+    _VRAM[0] = 0000070022; /* load MR dll on */
+    NOP();
+
+    * (uint32_t *) 0xf0000400 = 0x01070002; /* fifo on, refresh on, ddrcs und cke on, video dac on */
+
+    xprintf("sys_ctr = 0x%08x\r\n", * (uint32_t *) 0xf0000400);
+    xprintf("finished\r\n");
+}
+
+void memmove_b(uint8_t *dst, volatile uint8_t *src, size_t size)
+{
+    while (--size)
+    {
+        *dst++ = *src++;
+    }
+}
+
+void memmove_w(uint16_t *dst, volatile uint16_t *src, size_t size)
+{
+    size >>= 1;
+
+    while (--size)
+    {
+        *dst++ = *src++;
+    }
+}
+
+void memmove_l(uint32_t *dst, volatile uint32_t *src, size_t size)
+{
+    size >>= 2;
+
+    while (--size)
+    {
+        *dst++ = *src++;
+    }
+}
+
+
+void do_tests(void)
+{
+    // uint32_t version;
+    const int buffer_size = 64;
+    uint8_t buffer[buffer_size * 4];
+
+    xprintf("initialize Firebee video PLL\r\n");
+    init_pll();
+    xprintf("finished\r\n");
+
+    xprintf("initialize video ddr memory\r\n");
+    init_video_ddr();
+    xprintf("finished\r\n");
+
+#ifdef _NOT_USED_
+    xprintf("try to read Configware version (only works on later configs)\r\n");
+    version = * (uint32_t *) 0xffffffff;
+
+    xprintf("version = 0x%08lx\r\n", version);
+#endif /* _NOT_USED_ */
+
+    xprintf("try to access Firebee FPGA memory\r\n");
+
+    xprintf("write\r\n");
+    start = MCF_SLT0_SCNT;
+
+    /*
+     * fill 4 lines of video memory with 64 consecutive byte values
+     */
+    for (i = 0; i < 64; i++)
+    {
+       ((uint8_t *) _VRAM)[i] = (uint32_t) i;
+    }
+    end = MCF_SLT0_SCNT;
+    time = (start - end) / (SYSCLK / 1000) / 1000;
+
+    xprintf("finished (took %f seconds).\r\n", time / 1000.0);
+
+
+    /*
+     * read back video memory into local fast ram buffer
+     */
+
+    xprintf("read\r\n");
+    start = MCF_SLT0_SCNT;
+
+    /*
+     * read byte-wise
+     */
+    xprintf("byte read\r\n");
+    memmove_b(buffer, (uint8_t *) _VRAM, buffer_size);
+    end = MCF_SLT0_SCNT;
+    time = (start - end) / (SYSCLK / 1000) / 1000;
+
+    xprintf("finished (took %f seconds).\r\n", time / 1000.0);
+
+    hexdump(buffer, 64);
+
+
+    /*
+     * read word-wise
+     */
+    xprintf("word read\r\n");
+    memmove_w((uint16_t *) buffer, (uint16_t *) _VRAM, buffer_size);
+    end = MCF_SLT0_SCNT;
+    time = (start - end) / (SYSCLK / 1000) / 1000;
+
+    xprintf("finished (took %f seconds).\r\n", time / 1000.0);
+
+    hexdump(buffer, 64);
+
+    /*
+     * read longword-wise
+     */
+    xprintf("longword read\r\n");
+    memmove_l((uint32_t *) buffer, (uint32_t *) _VRAM, buffer_size);
+    end = MCF_SLT0_SCNT;
+    time = (start - end) / (SYSCLK / 1000) / 1000;
+
+    xprintf("finished (took %f seconds).\r\n", time / 1000.0);
+
+    hexdump(buffer, 64);
+
+    /*
+     * do some Firebee register tests
+     */
+
+    volatile uint8_t *dbasef = (volatile uint8_t *) 0xffff8200;
+
+    xprintf("dbasef = 0x%02x\r\n", *dbasef);
+    *dbasef = 0x0;
+    xprintf("dbasef after clearing it = 0x%02x\r\n", *dbasef);
+
+    volatile uint8_t *dbaseh = (volatile uint8_t *) 0xffff8201;
+
+    xprintf("dbaseh = 0x%02x\r\n", *dbaseh);
+    *dbaseh = 0x0;
+    xprintf("dbaseh after clearing it = 0x%02x\r\n", *dbaseh);
+
+    volatile uint8_t *dbasel = (volatile uint8_t *) 0xffff8203;
+    xprintf("dbasel = 0x%02x\r\n", *dbasel);
+    *dbasel = 0x0;
+    xprintf("dbasel after clearing it = 0x%02x\r\n", *dbasel);
+
+    volatile uint8_t *dbaselow = (volatile uint8_t *) 0xffff820d;
+    xprintf("dbaselow = 0x%02x\r\n", *dbaselow);
+    *dbaselow = 0x0;
+    xprintf("dbaselow after clearing it = 0x%02x\r\n", *dbaselow);
+
+    volatile uint16_t *linewidth = (volatile uint16_t *) 0xffff820e;
+    xprintf("linewidth = 0x%04x\r\n", *linewidth);
+    *linewidth = 0x0;
+    xprintf("linewidth after clearing it = 0x%04x\r\n", *linewidth);
+    *linewidth = 0x1234;
+    xprintf("linewidth after setting it to 0x1234 = 0x%04x\r\n", *linewidth);
+
+    volatile uint16_t *vwrap = (volatile uint16_t *) 0xffff8210;
+    xprintf("VWRAP = 0x%04x\r\n", *vwrap);
+    *vwrap = 0;
+    xprintf("VWRAP after clearing it = 0x%04x\r\n", *vwrap);
+    *vwrap = 0x1234;
+    xprintf("VWRAP after setting it to 0x1234 = 0x%04x\r\n", *vwrap);
+}
+
+
+
+void wait_for_jtag(void)
+{
+    long i;
+
+    /* set supervisor stack to end of SRAM1 */
+    __asm__ __volatile__ (
+        "       move    #0x2700,sr\n\t"         /* disable interrupts */
+        "       move.l  %[stack],d0\n\t"        /* 4KB on-chip core SRAM1 */
+        "       move.l  d0,sp\n\t"              /* set stack pointer */
+        :
+        : [stack] "i" (SAFE_STACK)
+        : "d0", "cc"    /* clobber */
+    );
+
+    MCF_EPORT_EPIER = 0x0;              /* disable EPORT interrupts */
+    MCF_INTC_IMRL = 0xffffffff;
+    MCF_INTC_IMRH = 0xffffffff;         /* disable interrupt controller */
+
+    MCF_MMU_MMUCR &= ~MCF_MMU_MMUCR_EN; /* disable MMU */
+
+    xprintf("relocated supervisor stack, disabled interrupts and disabled MMU\r\n");
+
+    /*
+     * configure FEC1L port directions to enable external JTAG configuration download to FPGA
+     */
+    MCF_GPIO_PDDR_FEC1L = 0 |
+                          MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4;  /* bit 4 = LED => output */
+                                                            /* all other bits = input */
+
+    /*
+     * configure DSPI_CS3 as GPIO input to avoid the MCU driving against the FPGA blink
+     */
+    MCF_PAD_PAR_DSPI &= ~MCF_PAD_PAR_DSPI_PAR_CS3(MCF_PAD_PAR_DSPI_PAR_CS3_DSPICS3);
+    /*
+     * now that GPIO ports have been switched to input, we can poll for FPGA config
+     * started from the JTAG interface (CONF_DONE goes low) and finish (CONF_DONE goes high)
+     */
+    xprintf("waiting for JTAG configuration start\r\n");
+    while ((MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE));       /* wait for JTAG config load started */
+
+    xprintf("waiting for JTAG configuration to finish\r\n");
+    while (!(MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE));     /* wait for JTAG config load finished */
+
+    xprintf("JTAG configuration finished.\r\n");
+
+    /* wait */
+    xprintf("wait a little to let things settle...\r\n");
+    for (i = 0; i < 100000L; i++);
+
+    xprintf("disable caches\r\n");
+    __asm__ __volatile(
+                "move.l     #0x01000000,d0      \r\n"
+                "movec      d0,CACR             \r\n"
+                : /* no output */
+                : /* no input */
+                : "d0", "memory");
+
+    xprintf("init FPGA PLLs\r\n");
+    init_pll();
+
+    xprintf("init video DDR RAM\r\n");
+    init_video_ddr();
+
+    /* begin of tests */
+
+    do_tests();
+
+    xprintf("wait a little to let things settle...\r\n");
+    for (i = 0; i < 100000L; i++);
+
+    xprintf("INFO: endless loop now. Press reset to reboot\r\n");
+    while (1)
+        ;
+}
+
+int main(int argc, char *argv[])
+{
+    printf("FPGA JTAG configuration support\r\n");
+    printf("test FPGA DDR RAM controller\r\n");
+    printf("\xbd 2014 M. F\x94schle\r\n");
+
+    printf("You may now savely load a new FPGA configuration through the JTAG interface\r\n"
+           "and your Firebee will reboot once finished using that new configuration.\r\n");
+    if (argc == 2)
+    {
+        /*
+         * we got an argument. This is supposed to be the address that we need to jump to after JTAG
+         * configuration has been finished. Meant to support BaS in RAM testing
+         */
+        char *addr_str = argv[1];
+        char *addr = NULL;
+        char *end = NULL;
+
+        addr = (char *) strtol(addr_str, &end, 16);
+        if (addr != NULL && addr <= (char *) 0xe0000000 && addr >= (char *) 0x10000000)
+        {
+            /*
+             * seems to be a valid address
+             */
+            bas_start = (long) addr;
+
+            printf("BaS start address set to %p\r\n", (void *) bas_start);
+        }
+        else
+        {
+            printf("\r\nNote: BaS start address %p not valid. Stick to %p.\r\n", addr, (void *) bas_start);
+        }
+    }
+    Supexec(wait_for_jtag);
+
+    return 0;       /* just to make the compiler happy, we will never return */
+}
+
--- a/tos/fpga_test/vmem_test.config
+++ b/tos/fpga_test/vmem_test.config
@@ -0,0 +1 @@
+// ADD PREDEFINED MACROS HERE!
--- a/tos/fpga_test/vmem_test.creator
+++ b/tos/fpga_test/vmem_test.creator
@@ -0,0 +1 @@
+[General]
--- a/tos/fpga_test/vmem_test.files
+++ b/tos/fpga_test/vmem_test.files
@@ -0,0 +1,7 @@
+include/driver_vec.h
+sources/jtagwait.c
+Makefile
+sources/bas_printf.c
+sources/bas_string.c
+sources/printf_helper.S
+sources/vmem_test.c
--- a/tos/fpga_test/vmem_test.includes
+++ b/tos/fpga_test/vmem_test.includes
@@ -0,0 +1,2 @@
+include
+/usr/m68k-atari-mint/include
--- a/tos/jtagwait/Makefile
+++ b/tos/jtagwait/Makefile
@@ -21,7 +21,9 @@ endif
 DEPEND=depend
 TOPDIR = ../..

-INCLUDE=-I$(TOPDIR)/../libcmini/include -nostdlib
+LIBCMINI=$(TOPDIR)/../libcmini/libcmini
+
+INCLUDE=-I$(LIBCMINI)/include -nostdlib
 LIBS=-lcmini -nostdlib -lgcc
 CC=$(PREFIX)/bin/gcc

@@ -78,7 +80,7 @@ $(1)/objs/%.o:$(SRCDIR)/%.S

 $(1)_OBJS=$(patsubst %,$(1)/objs/%,$(OBJS))
 $(1)/$(APP): $$($(1)_OBJS)
-	$(CC) $$(CFLAGS) -o $$@ $(TOPDIR)/../libcmini/$(1)/startup.o $$($(1)_OBJS) -L$(TOPDIR)/../libcmini/$(1) $(LIBS)
+	$(CC) $$(CFLAGS) -o $$@ $(LIBCMINI)/$(1)/startup.o $$($(1)_OBJS) -L$(LIBCMINI)/$(1) $(LIBS)
 	$(STRIP) $$@
 endef
 $(foreach DIR,$(TRGTDIRS),$(eval $(call CC_TEMPLATE,$(DIR))))
--- a/tos/pci_test/Makefile
+++ b/tos/pci_test/Makefile
@@ -21,7 +21,9 @@ endif
 DEPEND=depend
 TOPDIR = ../..

-INCLUDE=-I$(TOPDIR)/../libcmini/include -nostdlib
+LIBCMINI=$(TOPDIR)/../libcmini/libcmini
+
+INCLUDE=-I$(LIBCMINI)/include -nostdlib
 LIBS=-lcmini -nostdlib -lgcc
 CC=$(PREFIX)/bin/gcc

@@ -79,7 +81,7 @@ $(1)/objs/%.o:$(SRCDIR)/%.S

 $(1)_OBJS=$(patsubst %,$(1)/objs/%,$(OBJS))
 $(1)/$(APP): $$($(1)_OBJS)
-	$(CC) $$(CFLAGS) -o $$@ $(TOPDIR)/../libcmini/$(1)/startup.o $$($(1)_OBJS) -L$(TOPDIR)/../libcmini/$(1) $(LIBS)
+	$(CC) $$(CFLAGS) -o $$@ $(LIBCMINI)/$(1)/startup.o $$($(1)_OBJS) -L$(LIBCMINI)/$(1) $(LIBS)
 	$(STRIP) $$@
 endef
 $(foreach DIR,$(TRGTDIRS),$(eval $(call CC_TEMPLATE,$(DIR))))
--- a/tos/vmem_test/Makefile
+++ b/tos/vmem_test/Makefile
@@ -21,7 +21,9 @@ endif
 DEPEND=depend
 TOPDIR = ../..

-INCLUDE=-I$(TOPDIR)/../libcmini/include -nostdlib
+LIBCMINI=$(TOPDIR)/../libcmini/libcmini
+
+INCLUDE=-I$(LIBCMINI)/include -nostdlib
 LIBS=-lcmini -nostdlib -lgcc
 CC=$(PREFIX)/bin/gcc

@@ -79,7 +81,7 @@ $(1)/objs/%.o:$(SRCDIR)/%.S

 $(1)_OBJS=$(patsubst %,$(1)/objs/%,$(OBJS))
 $(1)/$(APP): $$($(1)_OBJS)
-	$(CC) $$(CFLAGS) -o $$@ $(TOPDIR)/../libcmini/$(1)/startup.o $$($(1)_OBJS) -L$(TOPDIR)/../libcmini/$(1) $(LIBS)
+	$(CC) $$(CFLAGS) -o $$@ $(LIBCMINI)/$(1)/startup.o $$($(1)_OBJS) -L$(LIBCMINI)/$(1) $(LIBS)
 	#$(STRIP) $$@
 endef
 $(foreach DIR,$(TRGTDIRS),$(eval $(call CC_TEMPLATE,$(DIR))))
--- a/tos/vmem_test/include/bas_printf.h
+++ b/tos/vmem_test/include/bas_printf.h
@@ -31,5 +31,5 @@ extern int sprintf(char *str, const char *format, ...);


 extern void display_progress(void);
-extern void hexdump(uint8_t buffer[], int size);
+extern void hexdump(volatile uint8_t buffer[], int size);
 #endif /* _BAS_PRINTF_H_ */
--- a/tos/vmem_test/sources/bas_printf.c
+++ b/tos/vmem_test/sources/bas_printf.c
@@ -417,27 +417,28 @@ void display_progress()
    xputchar('\r');
 }

-void hexdump(uint8_t buffer[], int size)
+void hexdump(volatile uint8_t buffer[], int size)
 {
   int i;
   int line = 0;
-   uint8_t *bp = buffer;
+   volatile uint8_t *bp = buffer;

   while (bp < buffer + size) {
-      uint8_t *lbp = bp;
+      volatile uint8_t *lbp = bp;

      xprintf("%08x  ", line);

      for (i = 0; i < 16; i++) {
+          uint8_t c = *lbp++;
         if (bp + i > buffer + size) {
            break;
         }
-         xprintf("%02x ", (uint8_t) *lbp++);
+         xprintf("%02x ", c);
      }

      lbp = bp;
      for (i = 0; i < 16; i++) {
-         int8_t c = *lbp++;
+         volatile int8_t c = *lbp++;

         if (bp + i > buffer + size) {
            break;
--- a/tos/vmem_test/sources/vmem_test.c
+++ b/tos/vmem_test/sources/vmem_test.c
@@ -85,7 +85,8 @@ static void init_pll(void)
 /*
 * INIT VIDEO DDR RAM
 */
-static void init_video_ddr(void) {
+static void init_video_ddr(void)
+{
    xprintf("init video RAM: ");

    * (volatile uint16_t *) 0xf0000400 = 0xb;   /* set cke = 1, cs=1, config = 1 */
@@ -119,9 +120,40 @@ static void init_video_ddr(void) {
    xprintf("finished\r\n");
 }

+void memmove_b(uint8_t *dst, volatile uint8_t *src, size_t size)
+{
+    while (--size)
+    {
+        *dst++ = *src++;
+    }
+}
+
+void memmove_w(uint16_t *dst, volatile uint16_t *src, size_t size)
+{
+    size >>= 1;
+
+    while (--size)
+    {
+        *dst++ = *src++;
+    }
+}
+
+void memmove_l(uint32_t *dst, volatile uint32_t *src, size_t size)
+{
+    size >>= 2;
+
+    while (--size)
+    {
+        *dst++ = *src++;
+    }
+}
+
+
 void do_tests(void)
 {
-    uint32_t version;
+    // uint32_t version;
+    const int buffer_size = 64;
+    uint8_t buffer[buffer_size * 4];

    xprintf("initialize Firebee video PLL\r\n");
    init_pll();
@@ -131,23 +163,21 @@ void do_tests(void)
    init_video_ddr();
    xprintf("finished\r\n");

+#ifdef _NOT_USED_
    xprintf("try to read Configware version (only works on later configs)\r\n");
    version = * (uint32_t *) 0xffffffff;

    xprintf("version = 0x%08lx\r\n", version);
+#endif /* _NOT_USED_ */

    xprintf("try to access Firebee FPGA memory\r\n");

-    xprintf("read\r\n");
-    start = MCF_SLT0_SCNT;
-    hexdump((uint8_t *) _VRAM, 64);
-    end = MCF_SLT0_SCNT;
-    time = (start - end) / (SYSCLK / 1000) / 1000;
-
-    xprintf("finished (took %f seconds).\r\n", time / 1000.0);
-
    xprintf("write\r\n");
    start = MCF_SLT0_SCNT;
+
+    /*
+     * fill 4 lines of video memory with 64 consecutive byte values
+     */
    for (i = 0; i < 64; i++)
    {
       ((uint8_t *) _VRAM)[i] = (uint32_t) i;
@@ -157,13 +187,90 @@ void do_tests(void)

    xprintf("finished (took %f seconds).\r\n", time / 1000.0);

+
+    /*
+     * read back video memory into local fast ram buffer
+     */
+
    xprintf("read\r\n");
    start = MCF_SLT0_SCNT;
-    hexdump((uint8_t *) _VRAM, 64);
+
+    /*
+     * read byte-wise
+     */
+    xprintf("byte read\r\n");
+    memmove_b(buffer, (uint8_t *) _VRAM, buffer_size);
    end = MCF_SLT0_SCNT;
    time = (start - end) / (SYSCLK / 1000) / 1000;

    xprintf("finished (took %f seconds).\r\n", time / 1000.0);
+
+    hexdump(buffer, 64);
+
+
+    /*
+     * read word-wise
+     */
+    xprintf("word read\r\n");
+    memmove_w((uint16_t *) buffer, (uint16_t *) _VRAM, buffer_size);
+    end = MCF_SLT0_SCNT;
+    time = (start - end) / (SYSCLK / 1000) / 1000;
+
+    xprintf("finished (took %f seconds).\r\n", time / 1000.0);
+
+    hexdump(buffer, 64);
+
+    /*
+     * read longword-wise
+     */
+    xprintf("longword read\r\n");
+    memmove_l((uint32_t *) buffer, (uint32_t *) _VRAM, buffer_size);
+    end = MCF_SLT0_SCNT;
+    time = (start - end) / (SYSCLK / 1000) / 1000;
+
+    xprintf("finished (took %f seconds).\r\n", time / 1000.0);
+
+    hexdump(buffer, 64);
+
+    /*
+     * do some Firebee register tests
+     */
+
+    volatile uint8_t *dbasef = (volatile uint8_t *) 0xffff8200;
+
+    xprintf("dbasef = 0x%02x\r\n", *dbasef);
+    *dbasef = 0x0;
+    xprintf("dbasef after clearing it = 0x%02x\r\n", *dbasef);
+
+    volatile uint8_t *dbaseh = (volatile uint8_t *) 0xffff8201;
+
+    xprintf("dbaseh = 0x%02x\r\n", *dbaseh);
+    *dbaseh = 0x0;
+    xprintf("dbaseh after clearing it = 0x%02x\r\n", *dbaseh);
+
+    volatile uint8_t *dbasel = (volatile uint8_t *) 0xffff8203;
+    xprintf("dbasel = 0x%02x\r\n", *dbasel);
+    *dbasel = 0x0;
+    xprintf("dbasel after clearing it = 0x%02x\r\n", *dbasel);
+
+    volatile uint8_t *dbaselow = (volatile uint8_t *) 0xffff820d;
+    xprintf("dbaselow = 0x%02x\r\n", *dbaselow);
+    *dbaselow = 0x0;
+    xprintf("dbaselow after clearing it = 0x%02x\r\n", *dbaselow);
+
+    volatile uint16_t *linewidth = (volatile uint16_t *) 0xffff820e;
+    xprintf("linewidth = 0x%04x\r\n", *linewidth);
+    *linewidth = 0x0;
+    xprintf("linewidth after clearing it = 0x%04x\r\n", *linewidth);
+    *linewidth = 0x1234;
+    xprintf("linewidth after setting it to 0x1234 = 0x%04x\r\n", *linewidth);
+
+    volatile uint16_t *vwrap = (volatile uint16_t *) 0xffff8210;
+    xprintf("VWRAP = 0x%04x\r\n", *vwrap);
+    *vwrap = 0;
+    xprintf("VWRAP after clearing it = 0x%04x\r\n", *vwrap);
+    *vwrap = 0x1234;
+    xprintf("VWRAP after setting it to 0x1234 = 0x%04x\r\n", *vwrap);
 }


@@ -233,7 +340,7 @@ void wait_for_jtag(void)

    /* begin of tests */

-    while (1) do_tests();
+    do_tests();

    xprintf("wait a little to let things settle...\r\n");
    for (i = 0; i < 100000L; i++);
--- a/video/videl.c
+++ b/video/videl.c
@@ -11,7 +11,7 @@
 * option any later version.  See doc/license.txt for details.
 */

-#define DBG_VIDEL
+// #define DBG_VIDEL
 #ifdef DBG_VIDEL
 #define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
 #else
--- a/video/video.c
+++ b/video/video.c
@@ -7,7 +7,7 @@
 #include "fb.h"
 #include "radeonfb.h"

-#define DBG_VIDEO
+// #define DBG_VIDEO
 #ifdef DBG_VIDEO
 #define dbg(format, arg...) do { xprintf("DEBUG (%s()): " format, __FUNCTION__, ##arg);} while(0)
 #else
@@ -344,6 +344,7 @@ void video_init(void)
                    radeon_found = true;

                    dbg("matched\r\n");
+#if 0                    
                    if (radeonfb_pci_register(handle, board) >= 0)
                    {
                        xprintf("RADEON video card found and registered\r\n");
@@ -352,6 +353,7 @@ void video_init(void)
                    {
                        dbg("failed to register RADEON PCI video card\r\n");
                    }
+#endif
                    return;
                }
                board++;
Author	SHA1	Message	Date
Markus Fröschle	891f26433e	remove debug output	2016-09-27 04:37:42 +00:00
Markus Fröschle	5edcc93e3f	release 0.91. Fixes FireTOS cold boot problem	2016-08-14 10:00:25 +00:00
Markus Fröschle	a0a6a36e0c	make FireTOS always cold boot (clear sys vars)	2016-08-14 09:55:28 +00:00
Markus Fröschle	d28c05918e	bump version	2016-08-14 09:09:12 +00:00
Markus Fröschle	9653fa601e	disabled debug output. This is version 0.88, "official" release	2016-08-14 08:16:20 +00:00
Markus Fröschle	b2015265e2	Fixed comments (that were obviously copy/pasted wrongly long ago)	2016-08-02 08:45:26 +00:00
Markus Fröschle	bc4a45aba4	did some beautifying on the code	2016-07-31 19:13:16 +00:00
Markus Fröschle	1c64feb4cb	add fpga_test	2016-07-30 09:55:11 +00:00
Markus Fröschle	2fbbbcc072	add fpga_test tos prg	2016-07-30 09:54:42 +00:00
Markus Fröschle	78b0f1133f	back to original VRAM address	2016-06-09 20:57:59 +00:00
Markus Fröschle	1feb4f2c7a	do more FPGA register tests	2016-06-09 18:04:17 +00:00
Markus Fröschle	bac9e62074	cleanup vmem_test	2016-06-06 05:19:25 +00:00
Markus Fröschle	eb7009ccfc	added memory test for VHDL config	2016-06-04 21:16:01 +00:00
Markus Fröschle	5edc91aa9f	general overhaul. Prepare for smaller pagesize	2016-04-17 19:37:19 +00:00
Markus Fröschle	98b9803ddf	make set_ipl() a true function (was inlined before)	2016-04-17 18:21:09 +00:00
Markus Fröschle	9a46235b91	experimental: directly jump through bus error vector on bus error	2016-04-17 18:20:28 +00:00
Markus Fröschle	a280a8f901	introduce SIZE_DEFAULT and MMU_PAGESIZE_DEFAULT to make experiments with smaller pagesize more versatile	2016-04-17 18:19:21 +00:00
Markus Fröschle	bff912704e	modify to _not_ inline set_ipl()	2016-04-17 18:17:55 +00:00
Markus Fröschle	3cc79212a3	changed return type to uint32_t instead of int32_t	2016-04-17 18:16:48 +00:00
Markus Fröschle	478563479a	activate m68k-elf compile again	2016-04-17 18:15:13 +00:00
Markus Fröschle	d2271ca7d9	fix wrong variable for ram target mapfile generation	2016-04-16 12:01:26 +00:00
Markus Fröschle	f06bf5fe8e	add missing include of pci_errata.h enable -O2 optimization	2016-04-04 19:04:15 +00:00
Markus Fröschle	a409f40593	fix failed alignment of pci_errata_xxx() functions which caused the code to hang when compiled with m68k-atari-mint-gcc	2016-04-04 09:31:25 +00:00
Markus Fröschle	e73333d893	put libcmini dependencies into a variable, cleanup clean target	2016-04-03 19:04:18 +00:00
Markus Fröschle	627aa0c2c4	modify 1st page to cache mode PASSTHROUGH	2016-04-02 18:56:20 +00:00
Markus Fröschle	181a83db5a	fix ST RAM values for initial SP & PC to allow FreeMint reboots on CTRL-ALT-DELETE	2016-04-02 10:39:26 +00:00
Markus Fröschle	11628b7167	skip FPGA config load at reset ("warm start")	2016-04-02 08:04:26 +00:00
David Gálvez	a97cebe140	Post increment makes that we send 65 bytes. Reported by Daroou.	2016-02-16 15:21:30 +00:00
David Gálvez	4c765b2512	Move functions declaration to header file	2016-02-07 18:35:04 +00:00
David Gálvez	0658bde430	Fix date and time saving to PIC process. Use wrapped functions to acces PIC registers.	2016-02-07 14:20:22 +00:00
Markus Fröschle	fe2e85b984	fix PSC3 interrupt level and prio fix PIC communication in PSC3 interrupt handler	2016-02-07 12:28:13 +00:00
Markus Fröschle	88e9fe0007	fix wrong IRQ priority for PCI arbiter interrupt (was identical to DMA interrupt)	2016-02-07 10:27:42 +00:00