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Firebee:R_0_9_5 Firebee:R_0_9_4 Firebee:R_0_9_3 Firebee:R_0_9_1 Firebee:R_0_9 Firebee:R_0_8_8 Firebee:R_0_8_7 Firebee:R_0_8_6 Firebee:R_0_8_5 Firebee:R_0_8_3 Firebee:R_0_8 Firebee:r_0.1

1 Commits
R_0_8_7 ... R_0_8_6

Author SHA1 Message Date
Markus Fröschle
40162047d8 (hopefully) fixed a problem with hang when i2c communication to TFP410 fails 2014-12-28 22:47:43 +00:00
160 changed files with 11438 additions and 26111 deletions
Expand all files Collapse all files

5
.gdbinit
View File

@@ -1,9 +1,8 @@
#set disassemble-next-line on
define tr
#!killall m68k-bdm-gdbserver
!killall m68k-bdm-gdbserver
target remote | m68k-bdm-gdbserver pipe /dev/bdmcf3
#target remote localhost:1234
#target remote | m68k-bdm-gdbserver pipe /dev/tblcf1
#target remote | m68k-bdm-gdbserver pipe /dev/tblcf3
#target dbug /dev/ttyS0
#monitor bdm-reset
end

119
BaS_gcc.files
View File

@@ -4,6 +4,20 @@ dma/MCD_tasks.c
dma/MCD_tasksInit.c
exe/basflash.c
exe/basflash_start.c
firebee/bas.elf
firebee/bas.lk
firebee/bas.map
firebee/bas.s19
firebee/basflash.elf
firebee/basflash.map
firebee/basflash.s19
firebee/bashflash.lk
firebee/depend
firebee/libbas.a
firebee/ram.elf
firebee/ram.lk
firebee/ram.map
firebee/ram.s19
flash/flash.c
flash/s19reader.c
fs/cc932.c
@@ -39,7 +53,6 @@ include/fecbd.h
include/ff.h
include/ffconf.h
include/firebee.h
include/font.h
include/i2c-algo-bit.h
include/i2c.h
include/icmp.h
@@ -98,7 +111,6 @@ include/tftp.h
include/udp.h
include/usb.h
include/usb_defs.h
include/usb_hub.h
include/user_io.h
include/util.h
include/version.h
@@ -118,6 +130,34 @@ include/x86prim_ops.h
include/x86regs.h
include/xhdi_sd.h
kbd/ikbd.c
m54455/bas.elf
m54455/bas.lk
m54455/bas.map
m54455/bas.s19
m54455/basflash.elf
m54455/basflash.map
m54455/basflash.s19
m54455/bashflash.lk
m54455/depend
m54455/libbas.a
m54455/ram.elf
m54455/ram.lk
m54455/ram.map
m54455/ram.s19
m5484lite/bas.elf
m5484lite/bas.lk
m5484lite/bas.map
m5484lite/bas.s19
m5484lite/basflash.elf
m5484lite/basflash.map
m5484lite/basflash.s19
m5484lite/bashflash.lk
m5484lite/depend
m5484lite/libbas.a
m5484lite/ram.elf
m5484lite/ram.lk
m5484lite/ram.map
m5484lite/ram.s19
net/am79c874.c
net/arp.c
net/bcm5222.c
@@ -131,6 +171,7 @@ net/nif.c
net/queue.c
net/tftp.c
net/udp.c
nutil/s19header
nutil/s19header.c
pci/ehci-hcd.c
pci/ohci-hcd.c
@@ -145,56 +186,46 @@ spi/sd_card.c
sys/BaS.c
sys/cache.c
sys/driver_mem.c
sys/exceptions.S
sys/fault_vectors.c
sys/init_fpga.c
sys/interrupts.c
sys/mmu.c
sys/sysinit.c
tos/bascook/sources/bascook.c
tos/jtagwait/include/bas_printf.h
tos/jtagwait/include/bas_string.h
tos/jtagwait/include/driver_vec.h
tos/jtagwait/include/MCF5475.h
tos/jtagwait/include/MCF5475_CLOCK.h
tos/jtagwait/include/MCF5475_CTM.h
tos/jtagwait/include/MCF5475_DMA.h
tos/jtagwait/include/MCF5475_DSPI.h
tos/jtagwait/include/MCF5475_EPORT.h
tos/jtagwait/include/MCF5475_FBCS.h
tos/jtagwait/include/MCF5475_FEC.h
tos/jtagwait/include/MCF5475_GPIO.h
tos/jtagwait/include/MCF5475_GPT.h
tos/jtagwait/include/MCF5475_I2C.h
tos/jtagwait/include/MCF5475_INTC.h
tos/jtagwait/include/MCF5475_MMU.h
tos/jtagwait/include/MCF5475_PAD.h
tos/jtagwait/include/MCF5475_PCI.h
tos/jtagwait/include/MCF5475_PCIARB.h
tos/jtagwait/include/MCF5475_PSC.h
tos/jtagwait/include/MCF5475_SDRAMC.h
tos/jtagwait/include/MCF5475_SEC.h
tos/jtagwait/include/MCF5475_SIU.h
tos/jtagwait/include/MCF5475_SLT.h
tos/jtagwait/include/MCF5475_SRAM.h
tos/jtagwait/include/MCF5475_USB.h
tos/jtagwait/include/MCF5475_XLB.h
tos/jtagwait/sources/jtagwait.c
usb/usb.c
usb/usb_hub.c
usb/usb_kbd.c
tos/jtagwait/sources/bas_printf.c
tos/jtagwait/sources/bas_string.c
tos/vmem_test/Makefile
tos/vmem_test/sources/bas_printf.c
tos/vmem_test/sources/bas_string.c
tos/vmem_test/sources/printf_helper.S
tos/vmem_test/sources/vmem_test.c
sys/startcf.S
sys/exceptions.S
sys/sysinit.c
usb/usb.c
usb/usb_mouse.c
util/bas_printf.c
util/bas_string.c
util/printf_helper.S
util/wait.c
video/fbmem.c
video/fbmodedb.c
video/fbmon.c
video/fnt_st_8x16.c
video/offscreen.c
video/vdi_fill.c
video/videl.c
video/video.c
x86emu/x86biosemu.c
x86emu/x86debug.c
x86emu/x86decode.c
x86emu/x86fpu.c
x86emu/x86ops.c
x86emu/x86ops2.c
x86emu/x86pcibios.c
x86emu/x86prim_ops.c
x86emu/x86sys.c
xhdi/xhdi_interface.c
xhdi/xhdi_sd.c
xhdi/xhdi_vec.S
bas.lk.in
i2c/i2c.c
bas_firebee.bdm
bas_m5484.bdm
basflash.lk.in
check.bdm
COPYING
COPYING.LESSER
dump.bdm
mcf5474.gdb
Makefile

2
BaS_gcc.includes
View File

@@ -1,2 +1,2 @@
include
tos/jtagwait/include
/usr/m68k-elf/include

23
Makefile
View File

@@ -1,4 +1,4 @@
# Makefile for Firebee BaS
# # Makefile for Firebee BaS
#
# This Makefile is meant for cross compiling the BaS with Vincent Riviere's cross compilers.
# If you want to compile native on an Atari (you will need at least GCC 4.6.3), set
@@ -31,28 +31,26 @@ NATIVECC=gcc
INCLUDE=-Iinclude
CFLAGS=-mcpu=5474 \
-g \
-Wall \
-g3 \
-fomit-frame-pointer \
-ffreestanding \
-fleading-underscore \
-mno-strict-align \
-Wa,--register-prefix-optional
CFLAGS_OPTIMIZED = -mcpu=5474 \
-Wall \
-g3 \
-O2 \
-g \
-fomit-frame-pointer \
-ffreestanding \
-fleading-underscore \
-Wa,--register-prefix-optional
LDFLAGS=-g
TRGTDIRS= ./firebee ./m5484lite ./m54455
OBJDIRS=$(patsubst %, %/objs,$(TRGTDIRS))
TOOLDIR=util
VPATH=dma exe flash fs i2c if kbd pci spi sys usb net util video radeon x86emu xhdi
VPATH=dma exe flash fs if kbd pci spi sys usb net util video radeon x86emu xhdi
# Linker control file. The final $(LDCFILE) is intermediate only (preprocessed version of $(LDCSRC)
LDCFILE=bas.lk
@@ -85,7 +83,6 @@ CSRCS= \
s19reader.c \
flash.c \
dma.c \
i2c.c \
xhdi_sd.c \
xhdi_interface.c \
pci.c \
@@ -98,9 +95,7 @@ CSRCS= \
usb.c \
ohci-hcd.c \
ehci-hcd.c \
usb_hub.c \
usb_mouse.c \
usb_kbd.c \
ikbd.c \
\
nbuf.c \
@@ -161,18 +156,12 @@ LIBBAS=libbas.a
LIBS=$(patsubst %,%/$(LIBBAS),$(TRGTDIRS))
all: ver fls ram bfl lib tos
all: fls ram bfl lib
fls: $(patsubst %,%/$(FLASH_EXEC),$(TRGTDIRS))
ram: $(patsubst %,%/$(RAM_EXEC),$(TRGTDIRS))
bfl: $(patsubst %,%/$(BASFLASH_EXEC),$(TRGTDIRS))
lib: $(LIBS)
.PHONY: ver
ver:
touch include/version.h
.PHONY: tos
tos:
(cd tos; make)
.PHONY: clean
clean:
@@ -274,7 +263,7 @@ endif
$(1)_MAPFILE_RAM=$(1)/$$(basename $$(RAM_EXEC)).map
$(1)/$$(RAM_EXEC): $(1)/$(LIBBAS) $(LDCSRC)
$(CPP) $(INCLUDE) -DCOMPILE_RAM -DOBJDIR=$(1)/objs -P -DFORMAT_ELF=$(FORMAT_ELF) -D$$(MACHINE) $(LDCSRC) -o $(1)/$$(LDRFILE)
$(LD) $(LDFLAGS) --oformat $$(FORMAT) -Map $$($(1)_MAPFILE_RAM) --cref -T $(1)/$$(LDRFILE) -o $$@
$(LD) -g --oformat $$(FORMAT) -Map $$($(1)_MAPFILE_RAM) --cref -T $(1)/$$(LDRFILE) -o $$@
ifeq ($(COMPILE_ELF),Y)
$(OBJCOPY) -O srec $$@ $$(basename $$@).s19
else

65
bas.lk.in
View File

@@ -10,21 +10,21 @@
/* make bas_rom access flags rx if compiling to RAM */
#ifdef COMPILE_RAM
#define ROMFLAGS WX
#define ROMFLAGS WX
#else
#define ROMFLAGS RX
#define ROMFLAGS RX
#endif /* COMPILE_RAM */
MEMORY
{
bas_rom (ROMFLAGS) : ORIGIN = TARGET_ADDRESS, LENGTH = 0x00100000
/*
* target to copy BaS data segment to. 1M should be enough for now
*/
* target to copy BaS data segment to. 1M should be enough for now
*/
bas_ram (WX) : ORIGIN = SDRAM_START + SDRAM_SIZE - 0x00200000, LENGTH = 0x00100000
/*
* driver_ram is an uncached, reserved memory area for drivers (e.g. USB) that need this type of memory
*/
* driver_ram is an uncached, reserved memory area for drivers (e.g. USB) that need this type of memory
*/
driver_ram (WX) : ORIGIN = SDRAM_START + SDRAM_SIZE - 0x00100000, LENGTH = 0x00100000
}
@@ -51,9 +51,7 @@ SECTIONS
OBJDIR/pci_wrappers.o(.text)
OBJDIR/usb.o(.text)
OBJDIR/driver_mem.o(.text)
OBJDIR/usb_hub.o(.text)
OBJDIR/usb_mouse.o(.text)
OBJDIR/usb_kbd.o(.text)
OBJDIR/ohci-hcd.o(.text)
OBJDIR/ehci-hcd.o(.text)
OBJDIR/wait.o(.text)
@@ -138,7 +136,7 @@ SECTIONS
.bas :
AT (ALIGN(ADDR(.text) + SIZEOF(.text), 4))
{
. = ALIGN(4); /* same alignment than AT() statement! */
. = ALIGN(4); /* same alignment than AT() statement! */
__BAS_DATA_START = .;
*(.data)
__BAS_DATA_END = .;
@@ -164,7 +162,7 @@ SECTIONS
/* SDRAM Initialization */
___SDRAM = SDRAM_START;
___SDRAM_SIZE = SDRAM_SIZE;
_SDRAM_VECTOR_TABLE = ___SDRAM;
_SDRAM_VECTOR_TABLE = ___SDRAM;
/* ST-RAM */
__STRAM = ___SDRAM;
@@ -175,14 +173,14 @@ SECTIONS
/* FastRAM */
__FASTRAM = 0x10000000;
__TARGET_ADDRESS = TARGET_ADDRESS;
__TARGET_ADDRESS = TARGET_ADDRESS;
#if TARGET_ADDRESS == BOOTFLASH_BASE_ADDRESS
__FASTRAM_END = __BAS_IN_RAM;
#else
__FASTRAM_END = TARGET_ADDRESS;
__FASTRAM_END = TARGET_ADDRESS;
#endif
__FASTRAM_SIZE = __FASTRAM_END - __FASTRAM;
__FASTRAM_SIZE = __FASTRAM_END - __FASTRAM;
/* Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes) */
___BOOT_FLASH = BOOTFLASH_BASE_ADDRESS;
@@ -195,9 +193,9 @@ SECTIONS
__BAS_SIZE = SIZEOF(.bas);
#else
/* BaS is already in RAM - no need to copy anything */
__BAS_IN_RAM = __FASTRAM_END;
__BAS_SIZE = 0;
__BAS_LMA = __BAS_IN_RAM;
__BAS_IN_RAM = __FASTRAM_END;
__BAS_SIZE = 0;
__BAS_LMA = __BAS_IN_RAM;
#endif
/* Other flash components */
@@ -206,8 +204,8 @@ SECTIONS
__EMUTOS_SIZE = 0x00100000;
/* where FPGA data lives in flash */
__FPGA_CONFIG = 0xe0700000;
__FPGA_CONFIG_SIZE = 0x100000;
__FPGA_CONFIG = 0xe0700000;
__FPGA_CONFIG_SIZE = 0x100000;
/* VIDEO RAM BASIS */
__VRAM = 0x60000000;
@@ -233,13 +231,12 @@ SECTIONS
__RAMBAR1_SIZE = 0x00001000;
__SUP_SP = __RAMBAR1 + __RAMBAR1_SIZE - 4;
/*
* this flag (if 1) indicates that FPGA configuration has been loaded through JTAG
* and shouldn't be overwritten on boot
*/
__FPGA_JTAG_LOADED = __RAMBAR1;
__FPGA_JTAG_VALID = __RAMBAR1 + 4;
/* system variables */
/*
* this flag (if 1) indicates that FPGA configuration has been loaded through JTAG
* and shouldn't be overwritten on boot
*/
__FPGA_JTAG_LOADED = __RAMBAR1;
__FPGA_JTAG_VALID = __FPGA_JTAG_LOADED + 4;
/* system variables */
@@ -247,19 +244,19 @@ SECTIONS
_rt_mod = __RAMBAR0 + 0x800;
_rt_ssp = __RAMBAR0 + 0x804;
_rt_usp = __RAMBAR0 + 0x808;
_rt_vbr = __RAMBAR0 + 0x80C; /* (8)01 */
_rt_cacr = __RAMBAR0 + 0x810; /* 002 */
_rt_asid = __RAMBAR0 + 0x814; /* 003 */
_rt_acr0 = __RAMBAR0 + 0x818; /* 004 */
_rt_acr1 = __RAMBAR0 + 0x81c; /* 005 */
_rt_acr2 = __RAMBAR0 + 0x820; /* 006 */
_rt_acr3 = __RAMBAR0 + 0x824; /* 007 */
_rt_mmubar = __RAMBAR0 + 0x828; /* 008 */
_rt_vbr = __RAMBAR0 + 0x80C; /* (8)01 */
_rt_cacr = __RAMBAR0 + 0x810; /* 002 */
_rt_asid = __RAMBAR0 + 0x814; /* 003 */
_rt_acr0 = __RAMBAR0 + 0x818; /* 004 */
_rt_acr1 = __RAMBAR0 + 0x81c; /* 005 */
_rt_acr2 = __RAMBAR0 + 0x820; /* 006 */
_rt_acr3 = __RAMBAR0 + 0x824; /* 007 */
_rt_mmubar = __RAMBAR0 + 0x828; /* 008 */
_rt_sr = __RAMBAR0 + 0x82c;
_d0_save = __RAMBAR0 + 0x830;
_a7_save = __RAMBAR0 + 0x834;
_video_tlb = __RAMBAR0 + 0x838;
_video_sbt = __RAMBAR0 + 0x83C;
_rt_mbar = __RAMBAR0 + 0x844; /* (c)0f */
_rt_mbar = __RAMBAR0 + 0x844; /* (c)0f */
}

6
bas_firebee.bdm
View File

@@ -63,6 +63,10 @@ write 0xFF000104 0x710D0F00 4 # SDCR (lock SDMR and enable refresh)
sleep 100
load -v firebee/ram.elf
write-ctrl 0x80e 0x2700
write-ctrl 0x2 0xa50c8120
dump-register SR
dump-register CACR
dump-register MBAR
execute
wait

1072
dma/MCD_dmaApi.c
View File

File diff suppressed because it is too large Load Diff

370
dma/MCD_tasks.c
View File

@@ -7,253 +7,253 @@
#include "MCD_dma.h"
u32 MCD_varTab0[];
u32 MCD_varTab1[];
u32 MCD_varTab2[];
u32 MCD_varTab3[];
u32 MCD_varTab4[];
u32 MCD_varTab5[];
u32 MCD_varTab6[];
u32 MCD_varTab7[];
u32 MCD_varTab8[];
u32 MCD_varTab9[];
u32 MCD_varTab10[];
u32 MCD_varTab11[];
u32 MCD_varTab12[];
u32 MCD_varTab13[];
u32 MCD_varTab14[];
u32 MCD_varTab15[];
uint32_t MCD_varTab0[];
uint32_t MCD_varTab1[];
uint32_t MCD_varTab2[];
uint32_t MCD_varTab3[];
uint32_t MCD_varTab4[];
uint32_t MCD_varTab5[];
uint32_t MCD_varTab6[];
uint32_t MCD_varTab7[];
uint32_t MCD_varTab8[];
uint32_t MCD_varTab9[];
uint32_t MCD_varTab10[];
uint32_t MCD_varTab11[];
uint32_t MCD_varTab12[];
uint32_t MCD_varTab13[];
uint32_t MCD_varTab14[];
uint32_t MCD_varTab15[];
u32 MCD_funcDescTab0[];
uint32_t MCD_funcDescTab0[];
#ifdef MCD_INCLUDE_EU
u32 MCD_funcDescTab1[];
u32 MCD_funcDescTab2[];
u32 MCD_funcDescTab3[];
u32 MCD_funcDescTab4[];
u32 MCD_funcDescTab5[];
u32 MCD_funcDescTab6[];
u32 MCD_funcDescTab7[];
u32 MCD_funcDescTab8[];
u32 MCD_funcDescTab9[];
u32 MCD_funcDescTab10[];
u32 MCD_funcDescTab11[];
u32 MCD_funcDescTab12[];
u32 MCD_funcDescTab13[];
u32 MCD_funcDescTab14[];
u32 MCD_funcDescTab15[];
uint32_t MCD_funcDescTab1[];
uint32_t MCD_funcDescTab2[];
uint32_t MCD_funcDescTab3[];
uint32_t MCD_funcDescTab4[];
uint32_t MCD_funcDescTab5[];
uint32_t MCD_funcDescTab6[];
uint32_t MCD_funcDescTab7[];
uint32_t MCD_funcDescTab8[];
uint32_t MCD_funcDescTab9[];
uint32_t MCD_funcDescTab10[];
uint32_t MCD_funcDescTab11[];
uint32_t MCD_funcDescTab12[];
uint32_t MCD_funcDescTab13[];
uint32_t MCD_funcDescTab14[];
uint32_t MCD_funcDescTab15[];
#endif
u32 MCD_contextSave0[];
u32 MCD_contextSave1[];
u32 MCD_contextSave2[];
u32 MCD_contextSave3[];
u32 MCD_contextSave4[];
u32 MCD_contextSave5[];
u32 MCD_contextSave6[];
u32 MCD_contextSave7[];
u32 MCD_contextSave8[];
u32 MCD_contextSave9[];
u32 MCD_contextSave10[];
u32 MCD_contextSave11[];
u32 MCD_contextSave12[];
u32 MCD_contextSave13[];
u32 MCD_contextSave14[];
u32 MCD_contextSave15[];
uint32_t MCD_contextSave0[];
uint32_t MCD_contextSave1[];
uint32_t MCD_contextSave2[];
uint32_t MCD_contextSave3[];
uint32_t MCD_contextSave4[];
uint32_t MCD_contextSave5[];
uint32_t MCD_contextSave6[];
uint32_t MCD_contextSave7[];
uint32_t MCD_contextSave8[];
uint32_t MCD_contextSave9[];
uint32_t MCD_contextSave10[];
uint32_t MCD_contextSave11[];
uint32_t MCD_contextSave12[];
uint32_t MCD_contextSave13[];
uint32_t MCD_contextSave14[];
uint32_t MCD_contextSave15[];
u32 MCD_realTaskTableSrc[] =
uint32_t MCD_realTaskTableSrc[] =
{
0x00000000,
0x00000000,
(u32)MCD_varTab0, /* Task 0 Variable Table */
(u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */
(uint32_t)MCD_varTab0, /* Task 0 Variable Table */
(uint32_t)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */
0x00000000,
0x00000000,
(u32)MCD_contextSave0, /* Task 0 context save space */
(uint32_t)MCD_contextSave0, /* Task 0 context save space */
0x00000000,
0x00000000,
0x00000000,
(u32)MCD_varTab1, /* Task 1 Variable Table */
(uint32_t)MCD_varTab1, /* Task 1 Variable Table */
#ifdef MCD_INCLUDE_EU
(u32)MCD_funcDescTab1, /* Task 1 Function Descriptor Table & Flags */
(uint32_t)MCD_funcDescTab1, /* Task 1 Function Descriptor Table & Flags */
#else
(u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */
(uint32_t)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */
#endif
0x00000000,
0x00000000,
(u32)MCD_contextSave1, /* Task 1 context save space */
(uint32_t)MCD_contextSave1, /* Task 1 context save space */
0x00000000,
0x00000000,
0x00000000,
(u32)MCD_varTab2, /* Task 2 Variable Table */
(uint32_t)MCD_varTab2, /* Task 2 Variable Table */
#ifdef MCD_INCLUDE_EU
(u32)MCD_funcDescTab2, /* Task 2 Function Descriptor Table & Flags */
(uint32_t)MCD_funcDescTab2, /* Task 2 Function Descriptor Table & Flags */
#else
(u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */
(uint32_t)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */
#endif
0x00000000,
0x00000000,
(u32)MCD_contextSave2, /* Task 2 context save space */
(uint32_t)MCD_contextSave2, /* Task 2 context save space */
0x00000000,
0x00000000,
0x00000000,
(u32)MCD_varTab3, /* Task 3 Variable Table */
(uint32_t)MCD_varTab3, /* Task 3 Variable Table */
#ifdef MCD_INCLUDE_EU
(u32)MCD_funcDescTab3, /* Task 3 Function Descriptor Table & Flags */
(uint32_t)MCD_funcDescTab3, /* Task 3 Function Descriptor Table & Flags */
#else
(u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */
(uint32_t)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */
#endif
0x00000000,
0x00000000,
(u32)MCD_contextSave3, /* Task 3 context save space */
(uint32_t)MCD_contextSave3, /* Task 3 context save space */
0x00000000,
0x00000000,
0x00000000,
(u32)MCD_varTab4, /* Task 4 Variable Table */
(uint32_t)MCD_varTab4, /* Task 4 Variable Table */
#ifdef MCD_INCLUDE_EU
(u32)MCD_funcDescTab4, /* Task 4 Function Descriptor Table & Flags */
(uint32_t)MCD_funcDescTab4, /* Task 4 Function Descriptor Table & Flags */
#else
(u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */
(uint32_t)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */
#endif
0x00000000,
0x00000000,
(u32)MCD_contextSave4, /* Task 4 context save space */
(uint32_t)MCD_contextSave4, /* Task 4 context save space */
0x00000000,
0x00000000,
0x00000000,
(u32)MCD_varTab5, /* Task 5 Variable Table */
(uint32_t)MCD_varTab5, /* Task 5 Variable Table */
#ifdef MCD_INCLUDE_EU
(u32)MCD_funcDescTab5, /* Task 5 Function Descriptor Table & Flags */
(uint32_t)MCD_funcDescTab5, /* Task 5 Function Descriptor Table & Flags */
#else
(u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */
(uint32_t)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */
#endif
0x00000000,
0x00000000,
(u32)MCD_contextSave5, /* Task 5 context save space */
(uint32_t)MCD_contextSave5, /* Task 5 context save space */
0x00000000,
0x00000000,
0x00000000,
(u32)MCD_varTab6, /* Task 6 Variable Table */
(uint32_t)MCD_varTab6, /* Task 6 Variable Table */
#ifdef MCD_INCLUDE_EU
(u32)MCD_funcDescTab6, /* Task 6 Function Descriptor Table & Flags */
(uint32_t)MCD_funcDescTab6, /* Task 6 Function Descriptor Table & Flags */
#else
(u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */
(uint32_t)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */
#endif
0x00000000,
0x00000000,
(u32)MCD_contextSave6, /* Task 6 context save space */
(uint32_t)MCD_contextSave6, /* Task 6 context save space */
0x00000000,
0x00000000,
0x00000000,
(u32)MCD_varTab7, /* Task 7 Variable Table */
(uint32_t)MCD_varTab7, /* Task 7 Variable Table */
#ifdef MCD_INCLUDE_EU
(u32)MCD_funcDescTab7, /* Task 7 Function Descriptor Table & Flags */
(uint32_t)MCD_funcDescTab7, /* Task 7 Function Descriptor Table & Flags */
#else
(u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */
(uint32_t)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */
#endif
0x00000000,
0x00000000,
(u32)MCD_contextSave7, /* Task 7 context save space */
(uint32_t)MCD_contextSave7, /* Task 7 context save space */
0x00000000,
0x00000000,
0x00000000,
(u32)MCD_varTab8, /* Task 8 Variable Table */
(uint32_t)MCD_varTab8, /* Task 8 Variable Table */
#ifdef MCD_INCLUDE_EU
(u32)MCD_funcDescTab8, /* Task 8 Function Descriptor Table & Flags */
(uint32_t)MCD_funcDescTab8, /* Task 8 Function Descriptor Table & Flags */
#else
(u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */
(uint32_t)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */
#endif
0x00000000,
0x00000000,
(u32)MCD_contextSave8, /* Task 8 context save space */
(uint32_t)MCD_contextSave8, /* Task 8 context save space */
0x00000000,
0x00000000,
0x00000000,
(u32)MCD_varTab9, /* Task 9 Variable Table */
(uint32_t)MCD_varTab9, /* Task 9 Variable Table */
#ifdef MCD_INCLUDE_EU
(u32)MCD_funcDescTab9, /* Task 9 Function Descriptor Table & Flags */
(uint32_t)MCD_funcDescTab9, /* Task 9 Function Descriptor Table & Flags */
#else
(u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */
(uint32_t)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */
#endif
0x00000000,
0x00000000,
(u32)MCD_contextSave9, /* Task 9 context save space */
(uint32_t)MCD_contextSave9, /* Task 9 context save space */
0x00000000,
0x00000000,
0x00000000,
(u32)MCD_varTab10, /* Task 10 Variable Table */
(uint32_t)MCD_varTab10, /* Task 10 Variable Table */
#ifdef MCD_INCLUDE_EU
(u32)MCD_funcDescTab10, /* Task 10 Function Descriptor Table & Flags */
(uint32_t)MCD_funcDescTab10, /* Task 10 Function Descriptor Table & Flags */
#else
(u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */
(uint32_t)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */
#endif
0x00000000,
0x00000000,
(u32)MCD_contextSave10, /* Task 10 context save space */
(uint32_t)MCD_contextSave10, /* Task 10 context save space */
0x00000000,
0x00000000,
0x00000000,
(u32)MCD_varTab11, /* Task 11 Variable Table */
(uint32_t)MCD_varTab11, /* Task 11 Variable Table */
#ifdef MCD_INCLUDE_EU
(u32)MCD_funcDescTab11, /* Task 11 Function Descriptor Table & Flags */
(uint32_t)MCD_funcDescTab11, /* Task 11 Function Descriptor Table & Flags */
#else
(u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */
(uint32_t)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */
#endif
0x00000000,
0x00000000,
(u32)MCD_contextSave11, /* Task 11 context save space */
(uint32_t)MCD_contextSave11, /* Task 11 context save space */
0x00000000,
0x00000000,
0x00000000,
(u32)MCD_varTab12, /* Task 12 Variable Table */
(uint32_t)MCD_varTab12, /* Task 12 Variable Table */
#ifdef MCD_INCLUDE_EU
(u32)MCD_funcDescTab12, /* Task 12 Function Descriptor Table & Flags */
(uint32_t)MCD_funcDescTab12, /* Task 12 Function Descriptor Table & Flags */
#else
(u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */
(uint32_t)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */
#endif
0x00000000,
0x00000000,
(u32)MCD_contextSave12, /* Task 12 context save space */
(uint32_t)MCD_contextSave12, /* Task 12 context save space */
0x00000000,
0x00000000,
0x00000000,
(u32)MCD_varTab13, /* Task 13 Variable Table */
(uint32_t)MCD_varTab13, /* Task 13 Variable Table */
#ifdef MCD_INCLUDE_EU
(u32)MCD_funcDescTab13, /* Task 13 Function Descriptor Table & Flags */
(uint32_t)MCD_funcDescTab13, /* Task 13 Function Descriptor Table & Flags */
#else
(u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */
(uint32_t)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */
#endif
0x00000000,
0x00000000,
(u32)MCD_contextSave13, /* Task 13 context save space */
(uint32_t)MCD_contextSave13, /* Task 13 context save space */
0x00000000,
0x00000000,
0x00000000,
(u32)MCD_varTab14, /* Task 14 Variable Table */
(uint32_t)MCD_varTab14, /* Task 14 Variable Table */
#ifdef MCD_INCLUDE_EU
(u32)MCD_funcDescTab14, /* Task 14 Function Descriptor Table & Flags */
(uint32_t)MCD_funcDescTab14, /* Task 14 Function Descriptor Table & Flags */
#else
(u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */
(uint32_t)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */
#endif
0x00000000,
0x00000000,
(u32)MCD_contextSave14, /* Task 14 context save space */
(uint32_t)MCD_contextSave14, /* Task 14 context save space */
0x00000000,
0x00000000,
0x00000000,
(u32)MCD_varTab15, /* Task 15 Variable Table */
(uint32_t)MCD_varTab15, /* Task 15 Variable Table */
#ifdef MCD_INCLUDE_EU
(u32)MCD_funcDescTab15, /* Task 15 Function Descriptor Table & Flags */
(uint32_t)MCD_funcDescTab15, /* Task 15 Function Descriptor Table & Flags */
#else
(u32)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */
(uint32_t)MCD_funcDescTab0, /* Task 0 Function Descriptor Table & Flags */
#endif
0x00000000,
0x00000000,
(u32)MCD_contextSave15, /* Task 15 context save space */
(uint32_t)MCD_contextSave15, /* Task 15 context save space */
0x00000000,
};
u32 MCD_varTab0[] =
uint32_t MCD_varTab0[] =
{ /* Task 0 Variable Table */
0x00000000, /* var[0] */
0x00000000, /* var[1] */
@@ -290,7 +290,7 @@ u32 MCD_varTab0[] =
};
u32 MCD_varTab1[] =
uint32_t MCD_varTab1[] =
{ /* Task 1 Variable Table */
0x00000000, /* var[0] */
0x00000000, /* var[1] */
@@ -326,7 +326,7 @@ u32 MCD_varTab1[] =
0x00000000, /* inc[7] */
};
u32 MCD_varTab2[]=
uint32_t MCD_varTab2[]=
{ /* Task 2 Variable Table */
0x00000000, /* var[0] */
0x00000000, /* var[1] */
@@ -362,7 +362,7 @@ u32 MCD_varTab2[]=
0x00000000, /* inc[7] */
};
u32 MCD_varTab3[]=
uint32_t MCD_varTab3[]=
{ /* Task 3 Variable Table */
0x00000000, /* var[0] */
0x00000000, /* var[1] */
@@ -398,7 +398,7 @@ u32 MCD_varTab3[]=
0x00000000, /* inc[7] */
};
u32 MCD_varTab4[]=
uint32_t MCD_varTab4[]=
{ /* Task 4 Variable Table */
0x00000000, /* var[0] */
0x00000000, /* var[1] */
@@ -434,7 +434,7 @@ u32 MCD_varTab4[]=
0x00000000, /* inc[7] */
};
u32 MCD_varTab5[]=
uint32_t MCD_varTab5[]=
{ /* Task 5 Variable Table */
0x00000000, /* var[0] */
0x00000000, /* var[1] */
@@ -470,7 +470,7 @@ u32 MCD_varTab5[]=
0x00000000, /* inc[7] */
};
u32 MCD_varTab6[]=
uint32_t MCD_varTab6[]=
{ /* Task 6 Variable Table */
0x00000000, /* var[0] */
0x00000000, /* var[1] */
@@ -506,7 +506,7 @@ u32 MCD_varTab6[]=
0x00000000, /* inc[7] */
};
u32 MCD_varTab7[]=
uint32_t MCD_varTab7[]=
{ /* Task 7 Variable Table */
0x00000000, /* var[0] */
0x00000000, /* var[1] */
@@ -542,7 +542,7 @@ u32 MCD_varTab7[]=
0x00000000, /* inc[7] */
};
u32 MCD_varTab8[]=
uint32_t MCD_varTab8[]=
{ /* Task 8 Variable Table */
0x00000000, /* var[0] */
0x00000000, /* var[1] */
@@ -578,7 +578,7 @@ u32 MCD_varTab8[]=
0x00000000, /* inc[7] */
};
u32 MCD_varTab9[]=
uint32_t MCD_varTab9[]=
{ /* Task 9 Variable Table */
0x00000000, /* var[0] */
0x00000000, /* var[1] */
@@ -614,7 +614,7 @@ u32 MCD_varTab9[]=
0x00000000, /* inc[7] */
};
u32 MCD_varTab10[]=
uint32_t MCD_varTab10[]=
{ /* Task 10 Variable Table */
0x00000000, /* var[0] */
0x00000000, /* var[1] */
@@ -650,7 +650,7 @@ u32 MCD_varTab10[]=
0x00000000, /* inc[7] */
};
u32 MCD_varTab11[]=
uint32_t MCD_varTab11[]=
{ /* Task 11 Variable Table */
0x00000000, /* var[0] */
0x00000000, /* var[1] */
@@ -686,7 +686,7 @@ u32 MCD_varTab11[]=
0x00000000, /* inc[7] */
};
u32 MCD_varTab12[]=
uint32_t MCD_varTab12[]=
{ /* Task 12 Variable Table */
0x00000000, /* var[0] */
0x00000000, /* var[1] */
@@ -722,7 +722,7 @@ u32 MCD_varTab12[]=
0x00000000, /* inc[7] */
};
u32 MCD_varTab13[]=
uint32_t MCD_varTab13[]=
{ /* Task 13 Variable Table */
0x00000000, /* var[0] */
0x00000000, /* var[1] */
@@ -758,7 +758,7 @@ u32 MCD_varTab13[]=
0x00000000, /* inc[7] */
};
u32 MCD_varTab14[]=
uint32_t MCD_varTab14[]=
{ /* Task 14 Variable Table */
0x00000000, /* var[0] */
0x00000000, /* var[1] */
@@ -794,7 +794,7 @@ u32 MCD_varTab14[]=
0x00000000, /* inc[7] */
};
u32 MCD_varTab15[]=
uint32_t MCD_varTab15[]=
{ /* Task 15 Variable Table */
0x00000000, /* var[0] */
0x00000000, /* var[1] */
@@ -830,7 +830,7 @@ u32 MCD_varTab15[]=
0x00000000, /* inc[7] */
};
u32 MCD_funcDescTab0[]=
uint32_t MCD_funcDescTab0[]=
{ /* Task 0 Function Descriptor Table */
0x00000000,
0x00000000,
@@ -899,7 +899,7 @@ u32 MCD_funcDescTab0[]=
};
#ifdef MCD_INCLUDE_EU
u32 MCD_funcDescTab1[]=
uint32_t MCD_funcDescTab1[]=
{ /* Task 1 Function Descriptor Table */
0x00000000,
0x00000000,
@@ -967,7 +967,7 @@ u32 MCD_funcDescTab1[]=
0x202f2000, /* andCrcRestartBit(), EU# 3 */
};
u32 MCD_funcDescTab2[]=
uint32_t MCD_funcDescTab2[]=
{ /* Task 2 Function Descriptor Table */
0x00000000,
0x00000000,
@@ -1035,7 +1035,7 @@ u32 MCD_funcDescTab2[]=
0x202f2000, /* andCrcRestartBit(), EU# 3 */
};
u32 MCD_funcDescTab3[]=
uint32_t MCD_funcDescTab3[]=
{ /* Task 3 Function Descriptor Table */
0x00000000,
0x00000000,
@@ -1103,7 +1103,7 @@ u32 MCD_funcDescTab3[]=
0x202f2000, /* andCrcRestartBit(), EU# 3 */
};
u32 MCD_funcDescTab4[]=
uint32_t MCD_funcDescTab4[]=
{ /* Task 4 Function Descriptor Table */
0x00000000,
0x00000000,
@@ -1171,7 +1171,7 @@ u32 MCD_funcDescTab4[]=
0x202f2000, /* andCrcRestartBit(), EU# 3 */
};
u32 MCD_funcDescTab5[]=
uint32_t MCD_funcDescTab5[]=
{ /* Task 5 Function Descriptor Table */
0x00000000,
0x00000000,
@@ -1239,7 +1239,7 @@ u32 MCD_funcDescTab5[]=
0x202f2000, /* andCrcRestartBit(), EU# 3 */
};
u32 MCD_funcDescTab6[]=
uint32_t MCD_funcDescTab6[]=
{ /* Task 6 Function Descriptor Table */
0x00000000,
0x00000000,
@@ -1307,7 +1307,7 @@ u32 MCD_funcDescTab6[]=
0x202f2000, /* andCrcRestartBit(), EU# 3 */
};
u32 MCD_funcDescTab7[]=
uint32_t MCD_funcDescTab7[]=
{ /* Task 7 Function Descriptor Table */
0x00000000,
0x00000000,
@@ -1375,7 +1375,7 @@ u32 MCD_funcDescTab7[]=
0x202f2000, /* andCrcRestartBit(), EU# 3 */
};
u32 MCD_funcDescTab8[]=
uint32_t MCD_funcDescTab8[]=
{ /* Task 8 Function Descriptor Table */
0x00000000,
0x00000000,
@@ -1443,7 +1443,7 @@ u32 MCD_funcDescTab8[]=
0x202f2000, /* andCrcRestartBit(), EU# 3 */
};
u32 MCD_funcDescTab9[]=
uint32_t MCD_funcDescTab9[]=
{ /* Task 9 Function Descriptor Table */
0x00000000,
0x00000000,
@@ -1511,7 +1511,7 @@ u32 MCD_funcDescTab9[]=
0x202f2000, /* andCrcRestartBit(), EU# 3 */
};
u32 MCD_funcDescTab10[]=
uint32_t MCD_funcDescTab10[]=
{ /* Task 10 Function Descriptor Table */
0x00000000,
0x00000000,
@@ -1579,7 +1579,7 @@ u32 MCD_funcDescTab10[]=
0x202f2000, /* andCrcRestartBit(), EU# 3 */
};
u32 MCD_funcDescTab11[]=
uint32_t MCD_funcDescTab11[]=
{ /* Task 11 Function Descriptor Table */
0x00000000,
0x00000000,
@@ -1647,7 +1647,7 @@ u32 MCD_funcDescTab11[]=
0x202f2000, /* andCrcRestartBit(), EU# 3 */
};
u32 MCD_funcDescTab12[]=
uint32_t MCD_funcDescTab12[]=
{ /* Task 12 Function Descriptor Table */
0x00000000,
0x00000000,
@@ -1715,7 +1715,7 @@ u32 MCD_funcDescTab12[]=
0x202f2000, /* andCrcRestartBit(), EU# 3 */
};
u32 MCD_funcDescTab13[]=
uint32_t MCD_funcDescTab13[]=
{ /* Task 13 Function Descriptor Table */
0x00000000,
0x00000000,
@@ -1783,7 +1783,7 @@ u32 MCD_funcDescTab13[]=
0x202f2000, /* andCrcRestartBit(), EU# 3 */
};
u32 MCD_funcDescTab14[]=
uint32_t MCD_funcDescTab14[]=
{ /* Task 14 Function Descriptor Table */
0x00000000,
0x00000000,
@@ -1851,7 +1851,7 @@ u32 MCD_funcDescTab14[]=
0x202f2000, /* andCrcRestartBit(), EU# 3 */
};
u32 MCD_funcDescTab15[]=
uint32_t MCD_funcDescTab15[]=
{ /* Task 15 Function Descriptor Table */
0x00000000,
0x00000000,
@@ -1920,45 +1920,45 @@ u32 MCD_funcDescTab15[]=
};
#endif /*MCD_INCLUDE_EU*/
u32 MCD_contextSave0[128]; /* Task 0 context save space */
u32 MCD_contextSave1[128]; /* Task 1 context save space */
u32 MCD_contextSave2[128]; /* Task 2 context save space */
u32 MCD_contextSave3[128]; /* Task 3 context save space */
u32 MCD_contextSave4[128]; /* Task 4 context save space */
u32 MCD_contextSave5[128]; /* Task 5 context save space */
u32 MCD_contextSave6[128]; /* Task 6 context save space */
u32 MCD_contextSave7[128]; /* Task 7 context save space */
u32 MCD_contextSave8[128]; /* Task 8 context save space */
u32 MCD_contextSave9[128]; /* Task 9 context save space */
u32 MCD_contextSave10[128]; /* Task 10 context save space */
u32 MCD_contextSave11[128]; /* Task 11 context save space */
u32 MCD_contextSave12[128]; /* Task 12 context save space */
u32 MCD_contextSave13[128]; /* Task 13 context save space */
u32 MCD_contextSave14[128]; /* Task 14 context save space */
u32 MCD_contextSave15[128]; /* Task 15 context save space */
uint32_t MCD_contextSave0[128]; /* Task 0 context save space */
uint32_t MCD_contextSave1[128]; /* Task 1 context save space */
uint32_t MCD_contextSave2[128]; /* Task 2 context save space */
uint32_t MCD_contextSave3[128]; /* Task 3 context save space */
uint32_t MCD_contextSave4[128]; /* Task 4 context save space */
uint32_t MCD_contextSave5[128]; /* Task 5 context save space */
uint32_t MCD_contextSave6[128]; /* Task 6 context save space */
uint32_t MCD_contextSave7[128]; /* Task 7 context save space */
uint32_t MCD_contextSave8[128]; /* Task 8 context save space */
uint32_t MCD_contextSave9[128]; /* Task 9 context save space */
uint32_t MCD_contextSave10[128]; /* Task 10 context save space */
uint32_t MCD_contextSave11[128]; /* Task 11 context save space */
uint32_t MCD_contextSave12[128]; /* Task 12 context save space */
uint32_t MCD_contextSave13[128]; /* Task 13 context save space */
uint32_t MCD_contextSave14[128]; /* Task 14 context save space */
uint32_t MCD_contextSave15[128]; /* Task 15 context save space */
u32 MCD_ChainNoEu_TDT[];
u32 MCD_SingleNoEu_TDT[];
uint32_t MCD_ChainNoEu_TDT[];
uint32_t MCD_SingleNoEu_TDT[];
#ifdef MCD_INCLUDE_EU
u32 MCD_ChainEu_TDT[];
u32 MCD_SingleEu_TDT[];
uint32_t MCD_ChainEu_TDT[];
uint32_t MCD_SingleEu_TDT[];
#endif
u32 MCD_ENetRcv_TDT[];
u32 MCD_ENetXmit_TDT[];
uint32_t MCD_ENetRcv_TDT[];
uint32_t MCD_ENetXmit_TDT[];
u32 MCD_modelTaskTableSrc[]=
uint32_t MCD_modelTaskTableSrc[]=
{
(u32)MCD_ChainNoEu_TDT,
(u32)&((u8*)MCD_ChainNoEu_TDT)[0x0000016c],
(uint32_t)MCD_ChainNoEu_TDT,
(uint32_t)&((uint8_t*)MCD_ChainNoEu_TDT)[0x0000016c],
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
(u32)MCD_SingleNoEu_TDT,
(u32)&((u8*)MCD_SingleNoEu_TDT)[0x000000d4],
(uint32_t)MCD_SingleNoEu_TDT,
(uint32_t)&((uint8_t*)MCD_SingleNoEu_TDT)[0x000000d4],
0x00000000,
0x00000000,
0x00000000,
@@ -1966,16 +1966,16 @@ u32 MCD_modelTaskTableSrc[]=
0x00000000,
0x00000000,
#ifdef MCD_INCLUDE_EU
(u32)MCD_ChainEu_TDT,
(u32)&((u8*)MCD_ChainEu_TDT)[0x000001b4],
(uint32_t)MCD_ChainEu_TDT,
(uint32_t)&((uint8_t*)MCD_ChainEu_TDT)[0x000001b4],
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
(u32)MCD_SingleEu_TDT,
(u32)&((u8*)MCD_SingleEu_TDT)[0x00000124],
(uint32_t)MCD_SingleEu_TDT,
(uint32_t)&((uint8_t*)MCD_SingleEu_TDT)[0x00000124],
0x00000000,
0x00000000,
0x00000000,
@@ -1983,16 +1983,16 @@ u32 MCD_modelTaskTableSrc[]=
0x00000000,
0x00000000,
#endif
(u32)MCD_ENetRcv_TDT,
(u32)&((u8*)MCD_ENetRcv_TDT)[0x0000009c],
(uint32_t)MCD_ENetRcv_TDT,
(uint32_t)&((uint8_t*)MCD_ENetRcv_TDT)[0x0000009c],
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
(u32)MCD_ENetXmit_TDT,
(u32)&((u8*)MCD_ENetXmit_TDT)[0x000000d0],
(uint32_t)MCD_ENetXmit_TDT,
(uint32_t)&((uint8_t*)MCD_ENetXmit_TDT)[0x000000d0],
0x00000000,
0x00000000,
0x00000000,
@@ -2000,7 +2000,7 @@ u32 MCD_modelTaskTableSrc[]=
0x00000000,
0x00000000,
};
u32 MCD_ChainNoEu_TDT[]=
uint32_t MCD_ChainNoEu_TDT[]=
{
0x80004000, /* 0000(:370): LCDEXT: idx0 = 0x00000000; ; */
0x8118801b, /* 0004(:370): LCD: idx1 = var2; idx1 once var0; idx1 += inc3 */
@@ -2095,7 +2095,7 @@ u32 MCD_ChainNoEu_TDT[]=
0x000001f8, /* 0168(:0): NOP */
0x000001f8, /* 016C(:0): NOP */
};
u32 MCD_SingleNoEu_TDT[]=
uint32_t MCD_SingleNoEu_TDT[]=
{
0x8198001b, /* 0000(:657): LCD: idx0 = var3; idx0 once var0; idx0 += inc3 */
0x7000000d, /* 0004(:658): DRD2A: EU0=0 EU1=0 EU2=0 EU3=13 EXT MORE init=0 WS=0 RS=0 */
@@ -2153,7 +2153,7 @@ u32 MCD_SingleNoEu_TDT[]=
0x040001f8, /* 00D4(:713): DRD1A: FN=0 INT init=0 WS=0 RS=0 */
};
#ifdef MCD_INCLUDE_EU
u32 MCD_ChainEu_TDT[]=
uint32_t MCD_ChainEu_TDT[]=
{
0x80004000, /* 0000(:947): LCDEXT: idx0 = 0x00000000; ; */
0x8198801b, /* 0004(:947): LCD: idx1 = var3; idx1 once var0; idx1 += inc3 */
@@ -2266,7 +2266,7 @@ u32 MCD_ChainEu_TDT[]=
0x000001f8, /* 01B0(:0): NOP */
0x000001f8, /* 01B4(:0): NOP */
};
u32 MCD_SingleEu_TDT[]=
uint32_t MCD_SingleEu_TDT[]=
{
0x8218001b, /* 0000(:1248): LCD: idx0 = var4; idx0 once var0; idx0 += inc3 */
0x7000000d, /* 0004(:1249): DRD2A: EU0=0 EU1=0 EU2=0 EU3=13 EXT MORE init=0 WS=0 RS=0 */
@@ -2344,7 +2344,7 @@ u32 MCD_SingleEu_TDT[]=
0x040001f8, /* 0124(:1316): DRD1A: FN=0 INT init=0 WS=0 RS=0 */
};
#endif
u32 MCD_ENetRcv_TDT[]=
uint32_t MCD_ENetRcv_TDT[]=
{
0x80004000, /* 0000(:1389): LCDEXT: idx0 = 0x00000000; ; */
0x81988000, /* 0004(:1389): LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */
@@ -2387,7 +2387,7 @@ u32 MCD_ENetRcv_TDT[]=
0x040001f8, /* 0098(:1441): DRD1A: FN=0 INT init=0 WS=0 RS=0 */
0x000001f8, /* 009C(:0): NOP */
};
u32 MCD_ENetXmit_TDT[]=
uint32_t MCD_ENetXmit_TDT[]=
{
0x80004000, /* 0000(:1516): LCDEXT: idx0 = 0x00000000; ; */
0x81988000, /* 0004(:1516): LCD: idx1 = var3; idx1 once var0; idx1 += inc0 */

283
dma/MCD_tasksInit.c
View File

@@ -11,6 +11,7 @@
*/
#include "MCD_dma.h"
#include "MCD_tasksInit.h"
extern dmaRegs *MCD_dmaBar;
@@ -22,33 +23,33 @@ extern dmaRegs *MCD_dmaBar;
void MCD_startDmaChainNoEu(int *currBD, short srcIncr, short destIncr, int xferSize, short xferSizeIncr, int *cSave, volatile TaskTableEntry *taskTable, int channel)
{
MCD_SET_VAR(taskTable+channel, 2, (u32)currBD); /* var[2] */
MCD_SET_VAR(taskTable+channel, 25, (u32)(0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */
MCD_SET_VAR(taskTable+channel, 24, (u32)(0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */
MCD_SET_VAR(taskTable+channel, 11, (u32)xferSize); /* var[11] */
MCD_SET_VAR(taskTable+channel, 26, (u32)(0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */
MCD_SET_VAR(taskTable+channel, 0, (u32)cSave); /* var[0] */
MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */
MCD_SET_VAR(taskTable+channel, 3, (u32)0x00000000); /* var[3] */
MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */
MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */
MCD_SET_VAR(taskTable+channel, 6, (u32)0x00000000); /* var[6] */
MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */
MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */
MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000000); /* var[9] */
MCD_SET_VAR(taskTable+channel, 10, (u32)0x00000000); /* var[10] */
MCD_SET_VAR(taskTable+channel, 12, (u32)0x00000000); /* var[12] */
MCD_SET_VAR(taskTable+channel, 13, (u32)0x80000000); /* var[13] */
MCD_SET_VAR(taskTable+channel, 14, (u32)0x00000010); /* var[14] */
MCD_SET_VAR(taskTable+channel, 15, (u32)0x00000004); /* var[15] */
MCD_SET_VAR(taskTable+channel, 16, (u32)0x08000000); /* var[16] */
MCD_SET_VAR(taskTable+channel, 27, (u32)0x00000000); /* inc[3] */
MCD_SET_VAR(taskTable+channel, 28, (u32)0x80000000); /* inc[4] */
MCD_SET_VAR(taskTable+channel, 29, (u32)0x80000001); /* inc[5] */
MCD_SET_VAR(taskTable+channel, 30, (u32)0x40000000); /* inc[6] */
MCD_SET_VAR(taskTable+channel, 2, (uint32_t)currBD); /* var[2] */
MCD_SET_VAR(taskTable+channel, 25, (uint32_t)(0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */
MCD_SET_VAR(taskTable+channel, 24, (uint32_t)(0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */
MCD_SET_VAR(taskTable+channel, 11, (uint32_t)xferSize); /* var[11] */
MCD_SET_VAR(taskTable+channel, 26, (uint32_t)(0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */
MCD_SET_VAR(taskTable+channel, 0, (uint32_t)cSave); /* var[0] */
MCD_SET_VAR(taskTable+channel, 1, (uint32_t)0x00000000); /* var[1] */
MCD_SET_VAR(taskTable+channel, 3, (uint32_t)0x00000000); /* var[3] */
MCD_SET_VAR(taskTable+channel, 4, (uint32_t)0x00000000); /* var[4] */
MCD_SET_VAR(taskTable+channel, 5, (uint32_t)0x00000000); /* var[5] */
MCD_SET_VAR(taskTable+channel, 6, (uint32_t)0x00000000); /* var[6] */
MCD_SET_VAR(taskTable+channel, 7, (uint32_t)0x00000000); /* var[7] */
MCD_SET_VAR(taskTable+channel, 8, (uint32_t)0x00000000); /* var[8] */
MCD_SET_VAR(taskTable+channel, 9, (uint32_t)0x00000000); /* var[9] */
MCD_SET_VAR(taskTable+channel, 10, (uint32_t)0x00000000); /* var[10] */
MCD_SET_VAR(taskTable+channel, 12, (uint32_t)0x00000000); /* var[12] */
MCD_SET_VAR(taskTable+channel, 13, (uint32_t)0x80000000); /* var[13] */
MCD_SET_VAR(taskTable+channel, 14, (uint32_t)0x00000010); /* var[14] */
MCD_SET_VAR(taskTable+channel, 15, (uint32_t)0x00000004); /* var[15] */
MCD_SET_VAR(taskTable+channel, 16, (uint32_t)0x08000000); /* var[16] */
MCD_SET_VAR(taskTable+channel, 27, (uint32_t)0x00000000); /* inc[3] */
MCD_SET_VAR(taskTable+channel, 28, (uint32_t)0x80000000); /* inc[4] */
MCD_SET_VAR(taskTable+channel, 29, (uint32_t)0x80000001); /* inc[5] */
MCD_SET_VAR(taskTable+channel, 30, (uint32_t)0x40000000); /* inc[6] */
/* Set the task's Enable bit in its Task Control Register */
MCD_dmaBar->taskControl[channel] |= (u16)0x8000;
MCD_dmaBar->taskControl[channel] |= (uint16_t)0x8000;
}
@@ -56,29 +57,29 @@ void MCD_startDmaChainNoEu(int *currBD, short srcIncr, short destIncr, int xfer
* Task 1
*/
void MCD_startDmaSingleNoEu(char *srcAddr, short srcIncr, char *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel)
void MCD_startDmaSingleNoEu(int8_t *srcAddr, short srcIncr, int8_t *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel)
{
MCD_SET_VAR(taskTable+channel, 7, (u32)srcAddr); /* var[7] */
MCD_SET_VAR(taskTable+channel, 25, (u32)(0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */
MCD_SET_VAR(taskTable+channel, 2, (u32)destAddr); /* var[2] */
MCD_SET_VAR(taskTable+channel, 24, (u32)(0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */
MCD_SET_VAR(taskTable+channel, 3, (u32)dmaSize); /* var[3] */
MCD_SET_VAR(taskTable+channel, 26, (u32)(0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */
MCD_SET_VAR(taskTable+channel, 5, (u32)flags); /* var[5] */
MCD_SET_VAR(taskTable+channel, 1, (u32)currBD); /* var[1] */
MCD_SET_VAR(taskTable+channel, 0, (u32)cSave); /* var[0] */
MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */
MCD_SET_VAR(taskTable+channel, 6, (u32)0x00000000); /* var[6] */
MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */
MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000004); /* var[9] */
MCD_SET_VAR(taskTable+channel, 10, (u32)0x08000000); /* var[10] */
MCD_SET_VAR(taskTable+channel, 27, (u32)0x00000000); /* inc[3] */
MCD_SET_VAR(taskTable+channel, 28, (u32)0x80000001); /* inc[4] */
MCD_SET_VAR(taskTable+channel, 29, (u32)0x40000000); /* inc[5] */
MCD_SET_VAR(taskTable+channel, 7, (uint32_t)srcAddr); /* var[7] */
MCD_SET_VAR(taskTable+channel, 25, (uint32_t)(0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */
MCD_SET_VAR(taskTable+channel, 2, (uint32_t)destAddr); /* var[2] */
MCD_SET_VAR(taskTable+channel, 24, (uint32_t)(0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */
MCD_SET_VAR(taskTable+channel, 3, (uint32_t)dmaSize); /* var[3] */
MCD_SET_VAR(taskTable+channel, 26, (uint32_t)(0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */
MCD_SET_VAR(taskTable+channel, 5, (uint32_t)flags); /* var[5] */
MCD_SET_VAR(taskTable+channel, 1, (uint32_t)currBD); /* var[1] */
MCD_SET_VAR(taskTable+channel, 0, (uint32_t)cSave); /* var[0] */
MCD_SET_VAR(taskTable+channel, 4, (uint32_t)0x00000000); /* var[4] */
MCD_SET_VAR(taskTable+channel, 6, (uint32_t)0x00000000); /* var[6] */
MCD_SET_VAR(taskTable+channel, 8, (uint32_t)0x00000000); /* var[8] */
MCD_SET_VAR(taskTable+channel, 9, (uint32_t)0x00000004); /* var[9] */
MCD_SET_VAR(taskTable+channel, 10, (uint32_t)0x08000000); /* var[10] */
MCD_SET_VAR(taskTable+channel, 27, (uint32_t)0x00000000); /* inc[3] */
MCD_SET_VAR(taskTable+channel, 28, (uint32_t)0x80000001); /* inc[4] */
MCD_SET_VAR(taskTable+channel, 29, (uint32_t)0x40000000); /* inc[5] */
/* Set the task's Enable bit in its Task Control Register */
MCD_dmaBar->taskControl[channel] |= (u16)0x8000;
MCD_dmaBar->taskControl[channel] |= (uint16_t)0x8000;
}
@@ -89,36 +90,36 @@ void MCD_startDmaSingleNoEu(char *srcAddr, short srcIncr, char *destAddr, short
void MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr, int xferSize, short xferSizeIncr, int *cSave, volatile TaskTableEntry *taskTable, int channel)
{
MCD_SET_VAR(taskTable+channel, 3, (u32)currBD); /* var[3] */
MCD_SET_VAR(taskTable+channel, 25, (u32)(0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */
MCD_SET_VAR(taskTable+channel, 24, (u32)(0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */
MCD_SET_VAR(taskTable+channel, 12, (u32)xferSize); /* var[12] */
MCD_SET_VAR(taskTable+channel, 26, (u32)(0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */
MCD_SET_VAR(taskTable+channel, 0, (u32)cSave); /* var[0] */
MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */
MCD_SET_VAR(taskTable+channel, 2, (u32)0x00000000); /* var[2] */
MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */
MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */
MCD_SET_VAR(taskTable+channel, 6, (u32)0x00000000); /* var[6] */
MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */
MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */
MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000000); /* var[9] */
MCD_SET_VAR(taskTable+channel, 10, (u32)0x00000000); /* var[10] */
MCD_SET_VAR(taskTable+channel, 11, (u32)0x00000000); /* var[11] */
MCD_SET_VAR(taskTable+channel, 13, (u32)0x00000000); /* var[13] */
MCD_SET_VAR(taskTable+channel, 14, (u32)0x80000000); /* var[14] */
MCD_SET_VAR(taskTable+channel, 15, (u32)0x00000010); /* var[15] */
MCD_SET_VAR(taskTable+channel, 16, (u32)0x00000001); /* var[16] */
MCD_SET_VAR(taskTable+channel, 17, (u32)0x00000004); /* var[17] */
MCD_SET_VAR(taskTable+channel, 18, (u32)0x08000000); /* var[18] */
MCD_SET_VAR(taskTable+channel, 27, (u32)0x00000000); /* inc[3] */
MCD_SET_VAR(taskTable+channel, 28, (u32)0x80000000); /* inc[4] */
MCD_SET_VAR(taskTable+channel, 29, (u32)0xc0000000); /* inc[5] */
MCD_SET_VAR(taskTable+channel, 30, (u32)0x80000001); /* inc[6] */
MCD_SET_VAR(taskTable+channel, 31, (u32)0x40000000); /* inc[7] */
MCD_SET_VAR(taskTable+channel, 3, (uint32_t)currBD); /* var[3] */
MCD_SET_VAR(taskTable+channel, 25, (uint32_t)(0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */
MCD_SET_VAR(taskTable+channel, 24, (uint32_t)(0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */
MCD_SET_VAR(taskTable+channel, 12, (uint32_t)xferSize); /* var[12] */
MCD_SET_VAR(taskTable+channel, 26, (uint32_t)(0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */
MCD_SET_VAR(taskTable+channel, 0, (uint32_t)cSave); /* var[0] */
MCD_SET_VAR(taskTable+channel, 1, (uint32_t)0x00000000); /* var[1] */
MCD_SET_VAR(taskTable+channel, 2, (uint32_t)0x00000000); /* var[2] */
MCD_SET_VAR(taskTable+channel, 4, (uint32_t)0x00000000); /* var[4] */
MCD_SET_VAR(taskTable+channel, 5, (uint32_t)0x00000000); /* var[5] */
MCD_SET_VAR(taskTable+channel, 6, (uint32_t)0x00000000); /* var[6] */
MCD_SET_VAR(taskTable+channel, 7, (uint32_t)0x00000000); /* var[7] */
MCD_SET_VAR(taskTable+channel, 8, (uint32_t)0x00000000); /* var[8] */
MCD_SET_VAR(taskTable+channel, 9, (uint32_t)0x00000000); /* var[9] */
MCD_SET_VAR(taskTable+channel, 10, (uint32_t)0x00000000); /* var[10] */
MCD_SET_VAR(taskTable+channel, 11, (uint32_t)0x00000000); /* var[11] */
MCD_SET_VAR(taskTable+channel, 13, (uint32_t)0x00000000); /* var[13] */
MCD_SET_VAR(taskTable+channel, 14, (uint32_t)0x80000000); /* var[14] */
MCD_SET_VAR(taskTable+channel, 15, (uint32_t)0x00000010); /* var[15] */
MCD_SET_VAR(taskTable+channel, 16, (uint32_t)0x00000001); /* var[16] */
MCD_SET_VAR(taskTable+channel, 17, (uint32_t)0x00000004); /* var[17] */
MCD_SET_VAR(taskTable+channel, 18, (uint32_t)0x08000000); /* var[18] */
MCD_SET_VAR(taskTable+channel, 27, (uint32_t)0x00000000); /* inc[3] */
MCD_SET_VAR(taskTable+channel, 28, (uint32_t)0x80000000); /* inc[4] */
MCD_SET_VAR(taskTable+channel, 29, (uint32_t)0xc0000000); /* inc[5] */
MCD_SET_VAR(taskTable+channel, 30, (uint32_t)0x80000001); /* inc[6] */
MCD_SET_VAR(taskTable+channel, 31, (uint32_t)0x40000000); /* inc[7] */
/* Set the task's Enable bit in its Task Control Register */
MCD_dmaBar->taskControl[channel] |= (u16)0x8000;
MCD_dmaBar->taskControl[channel] |= (uint16_t)0x8000;
}
@@ -126,33 +127,33 @@ void MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr, int xferSi
* Task 3
*/
void MCD_startDmaSingleEu(char *srcAddr, short srcIncr, char *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel)
void MCD_startDmaSingleEu(int8_t *srcAddr, short srcIncr, int8_t *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel)
{
MCD_SET_VAR(taskTable+channel, 8, (u32)srcAddr); /* var[8] */
MCD_SET_VAR(taskTable+channel, 25, (u32)(0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */
MCD_SET_VAR(taskTable+channel, 3, (u32)destAddr); /* var[3] */
MCD_SET_VAR(taskTable+channel, 24, (u32)(0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */
MCD_SET_VAR(taskTable+channel, 4, (u32)dmaSize); /* var[4] */
MCD_SET_VAR(taskTable+channel, 26, (u32)(0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */
MCD_SET_VAR(taskTable+channel, 6, (u32)flags); /* var[6] */
MCD_SET_VAR(taskTable+channel, 2, (u32)currBD); /* var[2] */
MCD_SET_VAR(taskTable+channel, 0, (u32)cSave); /* var[0] */
MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */
MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */
MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */
MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000000); /* var[9] */
MCD_SET_VAR(taskTable+channel, 10, (u32)0x00000001); /* var[10] */
MCD_SET_VAR(taskTable+channel, 11, (u32)0x00000004); /* var[11] */
MCD_SET_VAR(taskTable+channel, 12, (u32)0x08000000); /* var[12] */
MCD_SET_VAR(taskTable+channel, 27, (u32)0x00000000); /* inc[3] */
MCD_SET_VAR(taskTable+channel, 28, (u32)0xc0000000); /* inc[4] */
MCD_SET_VAR(taskTable+channel, 29, (u32)0x80000000); /* inc[5] */
MCD_SET_VAR(taskTable+channel, 30, (u32)0x80000001); /* inc[6] */
MCD_SET_VAR(taskTable+channel, 31, (u32)0x40000000); /* inc[7] */
MCD_SET_VAR(taskTable+channel, 8, (uint32_t)srcAddr); /* var[8] */
MCD_SET_VAR(taskTable+channel, 25, (uint32_t)(0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */
MCD_SET_VAR(taskTable+channel, 3, (uint32_t)destAddr); /* var[3] */
MCD_SET_VAR(taskTable+channel, 24, (uint32_t)(0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */
MCD_SET_VAR(taskTable+channel, 4, (uint32_t)dmaSize); /* var[4] */
MCD_SET_VAR(taskTable+channel, 26, (uint32_t)(0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */
MCD_SET_VAR(taskTable+channel, 6, (uint32_t)flags); /* var[6] */
MCD_SET_VAR(taskTable+channel, 2, (uint32_t)currBD); /* var[2] */
MCD_SET_VAR(taskTable+channel, 0, (uint32_t)cSave); /* var[0] */
MCD_SET_VAR(taskTable+channel, 1, (uint32_t)0x00000000); /* var[1] */
MCD_SET_VAR(taskTable+channel, 5, (uint32_t)0x00000000); /* var[5] */
MCD_SET_VAR(taskTable+channel, 7, (uint32_t)0x00000000); /* var[7] */
MCD_SET_VAR(taskTable+channel, 9, (uint32_t)0x00000000); /* var[9] */
MCD_SET_VAR(taskTable+channel, 10, (uint32_t)0x00000001); /* var[10] */
MCD_SET_VAR(taskTable+channel, 11, (uint32_t)0x00000004); /* var[11] */
MCD_SET_VAR(taskTable+channel, 12, (uint32_t)0x08000000); /* var[12] */
MCD_SET_VAR(taskTable+channel, 27, (uint32_t)0x00000000); /* inc[3] */
MCD_SET_VAR(taskTable+channel, 28, (uint32_t)0xc0000000); /* inc[4] */
MCD_SET_VAR(taskTable+channel, 29, (uint32_t)0x80000000); /* inc[5] */
MCD_SET_VAR(taskTable+channel, 30, (uint32_t)0x80000001); /* inc[6] */
MCD_SET_VAR(taskTable+channel, 31, (uint32_t)0x40000000); /* inc[7] */
/* Set the task's Enable bit in its Task Control Register */
MCD_dmaBar->taskControl[channel] |= (u16)0x8000;
MCD_dmaBar->taskControl[channel] |= (uint16_t)0x8000;
}
@@ -160,29 +161,29 @@ void MCD_startDmaSingleEu(char *srcAddr, short srcIncr, char *destAddr, short d
* Task 4
*/
void MCD_startDmaENetRcv(char *bDBase, char *currBD, char *rcvFifoPtr, volatile TaskTableEntry *taskTable, int channel)
void MCD_startDmaENetRcv(int8_t *bDBase, int8_t *currBD, int8_t *rcvFifoPtr, volatile TaskTableEntry *taskTable, int channel)
{
MCD_SET_VAR(taskTable+channel, 0, (u32)bDBase); /* var[0] */
MCD_SET_VAR(taskTable+channel, 3, (u32)currBD); /* var[3] */
MCD_SET_VAR(taskTable+channel, 6, (u32)rcvFifoPtr); /* var[6] */
MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */
MCD_SET_VAR(taskTable+channel, 2, (u32)0x00000000); /* var[2] */
MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */
MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */
MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */
MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */
MCD_SET_VAR(taskTable+channel, 9, (u32)0x0000ffff); /* var[9] */
MCD_SET_VAR(taskTable+channel, 10, (u32)0x30000000); /* var[10] */
MCD_SET_VAR(taskTable+channel, 11, (u32)0x0fffffff); /* var[11] */
MCD_SET_VAR(taskTable+channel, 12, (u32)0x00000008); /* var[12] */
MCD_SET_VAR(taskTable+channel, 24, (u32)0x00000000); /* inc[0] */
MCD_SET_VAR(taskTable+channel, 25, (u32)0x60000000); /* inc[1] */
MCD_SET_VAR(taskTable+channel, 26, (u32)0x20000004); /* inc[2] */
MCD_SET_VAR(taskTable+channel, 27, (u32)0x40000000); /* inc[3] */
MCD_SET_VAR(taskTable+channel, 0, (uint32_t)bDBase); /* var[0] */
MCD_SET_VAR(taskTable+channel, 3, (uint32_t)currBD); /* var[3] */
MCD_SET_VAR(taskTable+channel, 6, (uint32_t)rcvFifoPtr); /* var[6] */
MCD_SET_VAR(taskTable+channel, 1, (uint32_t)0x00000000); /* var[1] */
MCD_SET_VAR(taskTable+channel, 2, (uint32_t)0x00000000); /* var[2] */
MCD_SET_VAR(taskTable+channel, 4, (uint32_t)0x00000000); /* var[4] */
MCD_SET_VAR(taskTable+channel, 5, (uint32_t)0x00000000); /* var[5] */
MCD_SET_VAR(taskTable+channel, 7, (uint32_t)0x00000000); /* var[7] */
MCD_SET_VAR(taskTable+channel, 8, (uint32_t)0x00000000); /* var[8] */
MCD_SET_VAR(taskTable+channel, 9, (uint32_t)0x0000ffff); /* var[9] */
MCD_SET_VAR(taskTable+channel, 10, (uint32_t)0x30000000); /* var[10] */
MCD_SET_VAR(taskTable+channel, 11, (uint32_t)0x0fffffff); /* var[11] */
MCD_SET_VAR(taskTable+channel, 12, (uint32_t)0x00000008); /* var[12] */
MCD_SET_VAR(taskTable+channel, 24, (uint32_t)0x00000000); /* inc[0] */
MCD_SET_VAR(taskTable+channel, 25, (uint32_t)0x60000000); /* inc[1] */
MCD_SET_VAR(taskTable+channel, 26, (uint32_t)0x20000004); /* inc[2] */
MCD_SET_VAR(taskTable+channel, 27, (uint32_t)0x40000000); /* inc[3] */
/* Set the task's Enable bit in its Task Control Register */
MCD_dmaBar->taskControl[channel] |= (u16)0x8000;
MCD_dmaBar->taskControl[channel] |= (uint16_t)0x8000;
}
@@ -190,35 +191,35 @@ void MCD_startDmaENetRcv(char *bDBase, char *currBD, char *rcvFifoPtr, volatile
* Task 5
*/
void MCD_startDmaENetXmit(char *bDBase, char *currBD, char *xmitFifoPtr, volatile TaskTableEntry *taskTable, int channel)
void MCD_startDmaENetXmit(int8_t *bDBase, int8_t *currBD, int8_t *xmitFifoPtr, volatile TaskTableEntry *taskTable, int channel)
{
MCD_SET_VAR(taskTable+channel, 0, (u32)bDBase); /* var[0] */
MCD_SET_VAR(taskTable+channel, 3, (u32)currBD); /* var[3] */
MCD_SET_VAR(taskTable+channel, 11, (u32)xmitFifoPtr); /* var[11] */
MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */
MCD_SET_VAR(taskTable+channel, 2, (u32)0x00000000); /* var[2] */
MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */
MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */
MCD_SET_VAR(taskTable+channel, 6, (u32)0x00000000); /* var[6] */
MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */
MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */
MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000000); /* var[9] */
MCD_SET_VAR(taskTable+channel, 10, (u32)0x00000000); /* var[10] */
MCD_SET_VAR(taskTable+channel, 12, (u32)0x00000000); /* var[12] */
MCD_SET_VAR(taskTable+channel, 13, (u32)0x0000ffff); /* var[13] */
MCD_SET_VAR(taskTable+channel, 14, (u32)0xffffffff); /* var[14] */
MCD_SET_VAR(taskTable+channel, 15, (u32)0x00000004); /* var[15] */
MCD_SET_VAR(taskTable+channel, 16, (u32)0x00000008); /* var[16] */
MCD_SET_VAR(taskTable+channel, 24, (u32)0x00000000); /* inc[0] */
MCD_SET_VAR(taskTable+channel, 25, (u32)0x60000000); /* inc[1] */
MCD_SET_VAR(taskTable+channel, 26, (u32)0x40000000); /* inc[2] */
MCD_SET_VAR(taskTable+channel, 27, (u32)0xc000fffc); /* inc[3] */
MCD_SET_VAR(taskTable+channel, 28, (u32)0xe0000004); /* inc[4] */
MCD_SET_VAR(taskTable+channel, 29, (u32)0x80000000); /* inc[5] */
MCD_SET_VAR(taskTable+channel, 30, (u32)0x4000ffff); /* inc[6] */
MCD_SET_VAR(taskTable+channel, 31, (u32)0xe0000001); /* inc[7] */
MCD_SET_VAR(taskTable+channel, 0, (uint32_t)bDBase); /* var[0] */
MCD_SET_VAR(taskTable+channel, 3, (uint32_t)currBD); /* var[3] */
MCD_SET_VAR(taskTable+channel, 11, (uint32_t)xmitFifoPtr); /* var[11] */
MCD_SET_VAR(taskTable+channel, 1, (uint32_t)0x00000000); /* var[1] */
MCD_SET_VAR(taskTable+channel, 2, (uint32_t)0x00000000); /* var[2] */
MCD_SET_VAR(taskTable+channel, 4, (uint32_t)0x00000000); /* var[4] */
MCD_SET_VAR(taskTable+channel, 5, (uint32_t)0x00000000); /* var[5] */
MCD_SET_VAR(taskTable+channel, 6, (uint32_t)0x00000000); /* var[6] */
MCD_SET_VAR(taskTable+channel, 7, (uint32_t)0x00000000); /* var[7] */
MCD_SET_VAR(taskTable+channel, 8, (uint32_t)0x00000000); /* var[8] */
MCD_SET_VAR(taskTable+channel, 9, (uint32_t)0x00000000); /* var[9] */
MCD_SET_VAR(taskTable+channel, 10, (uint32_t)0x00000000); /* var[10] */
MCD_SET_VAR(taskTable+channel, 12, (uint32_t)0x00000000); /* var[12] */
MCD_SET_VAR(taskTable+channel, 13, (uint32_t)0x0000ffff); /* var[13] */
MCD_SET_VAR(taskTable+channel, 14, (uint32_t)0xffffffff); /* var[14] */
MCD_SET_VAR(taskTable+channel, 15, (uint32_t)0x00000004); /* var[15] */
MCD_SET_VAR(taskTable+channel, 16, (uint32_t)0x00000008); /* var[16] */
MCD_SET_VAR(taskTable+channel, 24, (uint32_t)0x00000000); /* inc[0] */
MCD_SET_VAR(taskTable+channel, 25, (uint32_t)0x60000000); /* inc[1] */
MCD_SET_VAR(taskTable+channel, 26, (uint32_t)0x40000000); /* inc[2] */
MCD_SET_VAR(taskTable+channel, 27, (uint32_t)0xc000fffc); /* inc[3] */
MCD_SET_VAR(taskTable+channel, 28, (uint32_t)0xe0000004); /* inc[4] */
MCD_SET_VAR(taskTable+channel, 29, (uint32_t)0x80000000); /* inc[5] */
MCD_SET_VAR(taskTable+channel, 30, (uint32_t)0x4000ffff); /* inc[6] */
MCD_SET_VAR(taskTable+channel, 31, (uint32_t)0xe0000001); /* inc[7] */
/* Set the task's Enable bit in its Task Control Register */
MCD_dmaBar->taskControl[channel] |= (u16)0x8000;
MCD_dmaBar->taskControl[channel] |= (uint16_t)0x8000;
}

895
dma/dma.c
View File

File diff suppressed because it is too large Load Diff

303
exe/basflash.c
View File

@@ -21,9 +21,10 @@
* Author: Markus Fröschle
*/
#include <bas_types.h>
#include "bas_printf.h"
#include <stdint.h>
#include <stdbool.h>
#include "bas_string.h"
#include "bas_printf.h"
#include "diskio.h"
#include "ff.h"
#include "s19reader.h"
@@ -219,190 +220,190 @@ static const int num_flash_areas = sizeof(flash_areas) / sizeof(struct romram);
*/
void amd_flash_sector_erase(int n)
{
volatile AMD_FLASH_CELL status;
volatile AMD_FLASH_CELL status;
pFlash[0x555] = AMD_FLASH_CMD_DATA(0xAA);
pFlash[0x2AA] = AMD_FLASH_CMD_DATA(0x55);
pFlash[0x555] = AMD_FLASH_CMD_DATA(0x80);
pFlash[0x555] = AMD_FLASH_CMD_DATA(0xAA);
pFlash[0x2AA] = AMD_FLASH_CMD_DATA(0x55);
pFlash[SADDR(n)] = AMD_FLASH_CMD_DATA(0x30);
pFlash[0x555] = AMD_FLASH_CMD_DATA(0xAA);
pFlash[0x2AA] = AMD_FLASH_CMD_DATA(0x55);
pFlash[0x555] = AMD_FLASH_CMD_DATA(0x80);
pFlash[0x555] = AMD_FLASH_CMD_DATA(0xAA);
pFlash[0x2AA] = AMD_FLASH_CMD_DATA(0x55);
pFlash[SADDR(n)] = AMD_FLASH_CMD_DATA(0x30);
do
status = pFlash[SADDR(n)];
while ((status & AMD_FLASH_CMD_DATA(0x80)) != AMD_FLASH_CMD_DATA(0x80));
do
status = pFlash[SADDR(n)];
while ((status & AMD_FLASH_CMD_DATA(0x80)) != AMD_FLASH_CMD_DATA(0x80));
/*
* Place device in read mode
*/
pFlash[0] = AMD_FLASH_CMD_DATA(0xAA);
pFlash[0] = AMD_FLASH_CMD_DATA(0x55);
pFlash[0] = AMD_FLASH_CMD_DATA(0xF0);
/*
* Place device in read mode
*/
pFlash[0] = AMD_FLASH_CMD_DATA(0xAA);
pFlash[0] = AMD_FLASH_CMD_DATA(0x55);
pFlash[0] = AMD_FLASH_CMD_DATA(0xF0);
}
int amd_flash_erase(void *start, int bytes, void (*putchar)(int))
{
int i, ebytes = 0;
int i, ebytes = 0;
if (bytes == 0)
return 0;
if (bytes == 0)
return 0;
for (i = 0; i < AMD_FLASH_SECTORS; i++)
{
if (start >= (void *)((void *) pFlash + SOFFSET(i)) &&
start <= (void *)((void *) pFlash + SOFFSET(i) + (SSIZE(i) - 1)))
{
break;
}
}
for (i = 0; i < AMD_FLASH_SECTORS; i++)
{
if (start >= (void *)((void *) pFlash + SOFFSET(i)) &&
start <= (void *)((void *) pFlash + SOFFSET(i) + (SSIZE(i) - 1)))
{
break;
}
}
while (ebytes < bytes)
{
if (putchar != NULL)
{
putchar('.');
}
amd_flash_sector_erase(i);
ebytes += SSIZE(i);
i++;
}
while (ebytes < bytes)
{
if (putchar != NULL)
{
putchar('.');
}
amd_flash_sector_erase(i);
ebytes += SSIZE(i);
i++;
}
if (putchar != NULL)
{
putchar(10); /* LF */
putchar(13); /* CR */
}
if (putchar != NULL)
{
putchar(10); /* LF */
putchar(13); /* CR */
}
return ebytes;
return ebytes;
}
void amd_flash_program_cell(AMD_FLASH_CELL *dst, AMD_FLASH_CELL data)
{
volatile AMD_FLASH_CELL status;
int retry;
volatile AMD_FLASH_CELL status;
int retry;
pFlash[0x555] = AMD_FLASH_CMD_DATA(0xAA);
pFlash[0x2AA] = AMD_FLASH_CMD_DATA(0x55);
pFlash[0x555] = AMD_FLASH_CMD_DATA(0xA0);
*dst = data;
pFlash[0x555] = AMD_FLASH_CMD_DATA(0xAA);
pFlash[0x2AA] = AMD_FLASH_CMD_DATA(0x55);
pFlash[0x555] = AMD_FLASH_CMD_DATA(0xA0);
*dst = data;
/*
* Wait for program operation to finish
* (Data# Polling Algorithm)
*/
retry = 0;
while (1)
{
status = *dst;
if ((status & AMD_FLASH_CMD_DATA(0x80)) ==
(data & AMD_FLASH_CMD_DATA(0x80)))
{
break;
}
if (status & AMD_FLASH_CMD_DATA(0x20))
{
status = *dst;
if ((status & AMD_FLASH_CMD_DATA(0x80)) ==
(data & AMD_FLASH_CMD_DATA(0x80)))
{
break;
}
if (++retry > 1024)
{
break;
}
}
}
/*
* Wait for program operation to finish
* (Data# Polling Algorithm)
*/
retry = 0;
while (1)
{
status = *dst;
if ((status & AMD_FLASH_CMD_DATA(0x80)) ==
(data & AMD_FLASH_CMD_DATA(0x80)))
{
break;
}
if (status & AMD_FLASH_CMD_DATA(0x20))
{
status = *dst;
if ((status & AMD_FLASH_CMD_DATA(0x80)) ==
(data & AMD_FLASH_CMD_DATA(0x80)))
{
break;
}
if (++retry > 1024)
{
break;
}
}
}
}
int amd_flash_program(void *dest, void *source, int bytes, int erase, void (*func)(void), void (*putchar)(int))
{
AMD_FLASH_CELL *src, *dst;
int hashi=1,hashj=0;
char hash[5];
AMD_FLASH_CELL *src, *dst;
int hashi=1,hashj=0;
char hash[5];
hash[0]=8; /* Backspace */
hash[1]=124;/* "|" */
hash[2]=47; /* "/" */
hash[3]=45; /* "-" */
hash[4]=92; /* "\" */
hash[0]=8; /* Backspace */
hash[1]=124;/* "|" */
hash[2]=47; /* "/" */
hash[3]=45; /* "-" */
hash[4]=92; /* "\" */
src = (AMD_FLASH_CELL *)source;
dst = (AMD_FLASH_CELL *)dest;
src = (AMD_FLASH_CELL *)source;
dst = (AMD_FLASH_CELL *)dest;
/*
* Place device in read mode
*/
pFlash[0] = AMD_FLASH_CMD_DATA(0xAA);
pFlash[0] = AMD_FLASH_CMD_DATA(0x55);
pFlash[0] = AMD_FLASH_CMD_DATA(0xF0);
/*
* Place device in read mode
*/
pFlash[0] = AMD_FLASH_CMD_DATA(0xAA);
pFlash[0] = AMD_FLASH_CMD_DATA(0x55);
pFlash[0] = AMD_FLASH_CMD_DATA(0xF0);
/*
* Erase device if necessary
*/
if (erase)
{
amd_flash_erase(dest, bytes, putchar);
}
/*
* Erase device if necessary
*/
if (erase)
{
amd_flash_erase(dest, bytes, putchar);
}
/*
* Program device
*/
while (bytes > 0)
{
amd_flash_program_cell(dst,*src);
/*
* Program device
*/
while (bytes > 0)
{
amd_flash_program_cell(dst,*src);
/* Verify Write */
if (*dst == *src)
{
bytes -= AMD_FLASH_CELL_BYTES;
*dst++, *src++;
/* Verify Write */
if (*dst == *src)
{
bytes -= AMD_FLASH_CELL_BYTES;
*dst++, *src++;
if ((putchar != NULL))
{
/* Hash marks to indicate progress */
if (hashj == 0x1000)
{
hashj = -1;
putchar(hash[0]);
putchar(hash[hashi]);
if ((putchar != NULL))
{
/* Hash marks to indicate progress */
if (hashj == 0x1000)
{
hashj = -1;
putchar(hash[0]);
putchar(hash[hashi]);
hashi++;
if (hashi == 5)
{
hashi=1;
}
hashi++;
if (hashi == 5)
{
hashi=1;
}
}
hashj++;
}
}
else
break;
}
}
hashj++;
}
}
else
break;
}
/*
* Place device in read mode
*/
pFlash[0] = AMD_FLASH_CMD_DATA(0xAA);
pFlash[0] = AMD_FLASH_CMD_DATA(0x55);
pFlash[0] = AMD_FLASH_CMD_DATA(0xF0);
/*
* Place device in read mode
*/
pFlash[0] = AMD_FLASH_CMD_DATA(0xAA);
pFlash[0] = AMD_FLASH_CMD_DATA(0x55);
pFlash[0] = AMD_FLASH_CMD_DATA(0xF0);
if (putchar != NULL)
{
putchar(hash[0]);
}
if (putchar != NULL)
{
putchar(hash[0]);
}
/*
* If a function was passed in, call it now
*/
if ((func != NULL))
{
func();
}
/*
* If a function was passed in, call it now
*/
if ((func != NULL))
{
func();
}
return ((int)src - (int)source);
return ((int)src - (int)source);
}
/*
@@ -634,7 +635,7 @@ void basflash(void)
if (strlen(fileinfo.fname) >= 4
&& strncmp(
&fileinfo.fname[strlen(fileinfo.fname)
- 4], srec_ext, 4) == 0) /* we have a .S19 file */
- 4], srec_ext, 4) == 0) /* we have a .S19 file */
{
/*
* build path + filename

2
exe/basflash_start.c
View File

@@ -21,7 +21,7 @@
* Author: Markus Fröschle
*/
#include <bas_types.h>
#include <stdint.h>
static uint32_t ownstack[4096];
static uint32_t *stackptr = &ownstack[4095];

297
flash/flash.c
View File

@@ -1,3 +1,4 @@
#include <stdint.h>
#include <stddef.h>
#include "bas_types.h"
@@ -191,191 +192,191 @@ static const int num_flash_areas = sizeof(flash_areas) / sizeof(struct romram);
*/
void amd_flash_sector_erase(int n)
{
volatile AMD_FLASH_CELL status;
volatile AMD_FLASH_CELL status;
pFlash[0x555] = AMD_FLASH_CMD_DATA(0xAA);
pFlash[0x2AA] = AMD_FLASH_CMD_DATA(0x55);
pFlash[0x555] = AMD_FLASH_CMD_DATA(0x80);
pFlash[0x555] = AMD_FLASH_CMD_DATA(0xAA);
pFlash[0x2AA] = AMD_FLASH_CMD_DATA(0x55);
pFlash[SADDR(n)] = AMD_FLASH_CMD_DATA(0x30);
pFlash[0x555] = AMD_FLASH_CMD_DATA(0xAA);
pFlash[0x2AA] = AMD_FLASH_CMD_DATA(0x55);
pFlash[0x555] = AMD_FLASH_CMD_DATA(0x80);
pFlash[0x555] = AMD_FLASH_CMD_DATA(0xAA);
pFlash[0x2AA] = AMD_FLASH_CMD_DATA(0x55);
pFlash[SADDR(n)] = AMD_FLASH_CMD_DATA(0x30);
do
status = pFlash[SADDR(n)];
while ((status & AMD_FLASH_CMD_DATA(0x80)) != AMD_FLASH_CMD_DATA(0x80));
do
status = pFlash[SADDR(n)];
while ((status & AMD_FLASH_CMD_DATA(0x80)) != AMD_FLASH_CMD_DATA(0x80));
/*
* Place device in read mode
*/
pFlash[0] = AMD_FLASH_CMD_DATA(0xAA);
pFlash[0] = AMD_FLASH_CMD_DATA(0x55);
pFlash[0] = AMD_FLASH_CMD_DATA(0xF0);
/*
* Place device in read mode
*/
pFlash[0] = AMD_FLASH_CMD_DATA(0xAA);
pFlash[0] = AMD_FLASH_CMD_DATA(0x55);
pFlash[0] = AMD_FLASH_CMD_DATA(0xF0);
}
int amd_flash_erase(void *start, int bytes, void (*putchar)(int))
{
int i, ebytes = 0;
int i, ebytes = 0;
if (bytes == 0)
return 0;
if (bytes == 0)
return 0;
for (i = 0; i < AMD_FLASH_SECTORS; i++)
{
if (start >= (void *)((void *) pFlash + SOFFSET(i)) &&
start <= (void *)((void *) pFlash + SOFFSET(i) + (SSIZE(i) - 1)))
{
break;
}
}
for (i = 0; i < AMD_FLASH_SECTORS; i++)
{
if (start >= (void *)((void *) pFlash + SOFFSET(i)) &&
start <= (void *)((void *) pFlash + SOFFSET(i) + (SSIZE(i) - 1)))
{
break;
}
}
while (ebytes < bytes)
{
if (putchar != NULL)
{
putchar('.');
}
amd_flash_sector_erase(i);
ebytes += SSIZE(i);
i++;
}
while (ebytes < bytes)
{
if (putchar != NULL)
{
putchar('.');
}
amd_flash_sector_erase(i);
ebytes += SSIZE(i);
i++;
}
if (putchar != NULL)
{
putchar(10); /* LF */
putchar(13); /* CR */
}
if (putchar != NULL)
{
putchar(10); /* LF */
putchar(13); /* CR */
}
return ebytes;
return ebytes;
}
void amd_flash_program_cell(AMD_FLASH_CELL *dst, AMD_FLASH_CELL data)
{
volatile AMD_FLASH_CELL status;
int retry;
volatile AMD_FLASH_CELL status;
int retry;
pFlash[0x555] = AMD_FLASH_CMD_DATA(0xAA);
pFlash[0x2AA] = AMD_FLASH_CMD_DATA(0x55);
pFlash[0x555] = AMD_FLASH_CMD_DATA(0xA0);
*dst = data;
pFlash[0x555] = AMD_FLASH_CMD_DATA(0xAA);
pFlash[0x2AA] = AMD_FLASH_CMD_DATA(0x55);
pFlash[0x555] = AMD_FLASH_CMD_DATA(0xA0);
*dst = data;
/*
* Wait for program operation to finish
* (Data# Polling Algorithm)
*/
retry = 0;
while (1)
{
status = *dst;
if ((status & AMD_FLASH_CMD_DATA(0x80)) ==
(data & AMD_FLASH_CMD_DATA(0x80)))
{
break;
}
if (status & AMD_FLASH_CMD_DATA(0x20))
{
status = *dst;
if ((status & AMD_FLASH_CMD_DATA(0x80)) ==
(data & AMD_FLASH_CMD_DATA(0x80)))
{
break;
}
if (++retry > 1024)
{
break;
}
}
}
/*
* Wait for program operation to finish
* (Data# Polling Algorithm)
*/
retry = 0;
while (1)
{
status = *dst;
if ((status & AMD_FLASH_CMD_DATA(0x80)) ==
(data & AMD_FLASH_CMD_DATA(0x80)))
{
break;
}
if (status & AMD_FLASH_CMD_DATA(0x20))
{
status = *dst;
if ((status & AMD_FLASH_CMD_DATA(0x80)) ==
(data & AMD_FLASH_CMD_DATA(0x80)))
{
break;
}
if (++retry > 1024)
{
break;
}
}
}
}
int amd_flash_program(void *dest, void *source, int bytes, int erase, void (*func)(void), void (*putchar)(int))
{
AMD_FLASH_CELL *src;
AMD_FLASH_CELL *src;
AMD_FLASH_CELL *dst;
int hashi = 1;
int hashi = 1;
int hashj = 0;
char hash[5];
char hash[5];
hash[0] = 8; /* Backspace */
hash[1] = 124;/* "|" */
hash[2] = 47; /* "/" */
hash[3] = 45; /* "-" */
hash[4] = 92; /* "\" */
hash[0] = 8; /* Backspace */
hash[1] = 124;/* "|" */
hash[2] = 47; /* "/" */
hash[3] = 45; /* "-" */
hash[4] = 92; /* "\" */
src = (AMD_FLASH_CELL *)source;
dst = (AMD_FLASH_CELL *)dest;
src = (AMD_FLASH_CELL *)source;
dst = (AMD_FLASH_CELL *)dest;
/*
* Place device in read mode
*/
pFlash[0] = AMD_FLASH_CMD_DATA(0xAA);
pFlash[0] = AMD_FLASH_CMD_DATA(0x55);
pFlash[0] = AMD_FLASH_CMD_DATA(0xF0);
/*
* Place device in read mode
*/
pFlash[0] = AMD_FLASH_CMD_DATA(0xAA);
pFlash[0] = AMD_FLASH_CMD_DATA(0x55);
pFlash[0] = AMD_FLASH_CMD_DATA(0xF0);
/*
* Erase device if necessary
*/
if (erase)
{
amd_flash_erase(dest, bytes, putchar);
}
/*
* Erase device if necessary
*/
if (erase)
{
amd_flash_erase(dest, bytes, putchar);
}
/*
* Program device
*/
while (bytes > 0)
{
amd_flash_program_cell(dst, *src);
/*
* Program device
*/
while (bytes > 0)
{
amd_flash_program_cell(dst, *src);
/* Verify Write */
if (*dst == *src)
{
bytes -= AMD_FLASH_CELL_BYTES;
*dst++, *src++;
/* Verify Write */
if (*dst == *src)
{
bytes -= AMD_FLASH_CELL_BYTES;
*dst++, *src++;
if ((putchar != NULL))
{
/* Hash marks to indicate progress */
if (hashj == 0x1000)
{
hashj = -1;
putchar(hash[0]);
putchar(hash[hashi]);
if ((putchar != NULL))
{
/* Hash marks to indicate progress */
if (hashj == 0x1000)
{
hashj = -1;
putchar(hash[0]);
putchar(hash[hashi]);
hashi++;
if (hashi == 5)
{
hashi = 1;
}
hashi++;
if (hashi == 5)
{
hashi = 1;
}
}
hashj++;
}
}
else
break;
}
}
hashj++;
}
}
else
break;
}
/*
* Place device in read mode
*/
pFlash[0] = AMD_FLASH_CMD_DATA(0xAA);
pFlash[0] = AMD_FLASH_CMD_DATA(0x55);
pFlash[0] = AMD_FLASH_CMD_DATA(0xF0);
/*
* Place device in read mode
*/
pFlash[0] = AMD_FLASH_CMD_DATA(0xAA);
pFlash[0] = AMD_FLASH_CMD_DATA(0x55);
pFlash[0] = AMD_FLASH_CMD_DATA(0xF0);
if (putchar != NULL)
{
putchar(hash[0]);
}
if (putchar != NULL)
{
putchar(hash[0]);
}
/*
* If a function was passed in, call it now
*/
if ((func != NULL))
{
func();
}
/*
* If a function was passed in, call it now
*/
if ((func != NULL))
{
func();
}
return ((int)src - (int)source);
return ((int)src - (int)source);
}

11
flash/s19reader.c
View File

@@ -23,7 +23,8 @@
* Copyright 2012 M. Froeschle
*/
#include <bas_types.h>
#include <stdint.h>
#include <stdbool.h>
#include "bas_printf.h"
#include "bas_string.h"
@@ -344,10 +345,10 @@ static err_t verify(uint8_t *dst, uint8_t *src, uint32_t length)
*/
static inline err_t srec_memcpy(uint8_t *dst, uint8_t *src, size_t n)
{
err_t e = OK;
err_t e = OK;
memcpy((void *) dst, (void *) src, n);
return e;
memcpy((void *) dst, (void *) src, n);
return e;
}
void srec_execute(char *flasher_filename)
@@ -382,7 +383,7 @@ void srec_execute(char *flasher_filename)
{
/* next pass: copy data to destination */
xprintf("OK.\r\ncopy/flash data: ");
err = read_srecords(flasher_filename, &start_address, &length, srec_memcpy);
err = read_srecords(flasher_filename, &start_address, &length, srec_memcpy);
if (err == OK)
{
/* next pass: verify data */

97
flash_scripts/flash_firebee_bas.bdm
View File

@@ -4,10 +4,43 @@
#
open $1
reset
sleep 1
sleep 10
wait
# Turn on MBAR at 0xFF00_0000
write-ctrl 0x0C0F 0xFF000000
# set VBR
write-ctrl 0x0801 0x00000000
#
# Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes)
write 0xFF000500 0xE0000000 4
write 0xFF000508 0x00001180 4
write 0xFF000504 0x007F0001 4
# SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes
#write 0xFF000004 0x000002AA 4 # SDRAMDS configuration
#write 0xFF000020 0x0000001A 4 # SDRAM CS0 configuration (128Mbytes 0000_0000 - 07FF_FFFF)
#write 0xFF000024 0x0800001A 4 # SDRAM CS1 configuration (128Mbytes 0800_0000 - 0FFF_FFFF)
#write 0xFF000028 0x1000001A 4 # SDRAM CS2 configuration (128Mbytes 1000_0000 - 17FF_FFFF)
#write 0xFF00002C 0x1800001A 4 # SDRAM CS3 configuration (128Mbytes 1800_0000 - 1FFF_FFFF)
#write 0xFF000108 0x73622830 4 # SDCFG1
#write 0xFF00010C 0x46770000 4 # SDCFG2
#write 0xFF000104 0xE10D0002 4 # SDCR + IPALL
#write 0xFF000100 0x40010000 4 # SDMR (write to LEMR)
#write 0xFF000100 0x048D0000 4 # SDMR (write to LMR)
#sleep 100
#write 0xFF000104 0xE10D0002 4 # SDCR + IPALL
#write 0xFF000104 0xE10D0004 4 # SDCR + IREF (first refresh)
#write 0xFF000104 0xE10D0004 4 # SDCR + IREF (first refresh)
#write 0xFF000100 0x008D0000 4 # SDMR (write to LMR)
#write 0xFF000104 0x710D0F00 4 # SDCR (lock SDMR and enable refresh)
#sleep 10
# use system sdram as flashlib scratch area.
# TODO: plugin flashing seems to work o.k. now for smaller binaries, while it doesn't for larger ones (EmuTOS) yet.
# This seems to be related to large flash buffers and PC-relative adressing of the plugin
@@ -20,34 +53,46 @@ flash 0xe0000000
# Caution: sector offset numbers need to be the ones from the x16 address range
# column and they vary in size - needs to be exactly as in the data sheet (p. 9)
#
# contrary to documentation, it seems we need to erase-wait after each sector
erase 0xe0000000 0
erase 0xe0000000 0x1000
erase 0xe0000000 0x2000
erase 0xe0000000 0x3000
erase 0xe0000000 0x4000
erase 0xe0000000 0x5000
erase 0xe0000000 0x6000
erase 0xe0000000 0x7000
erase 0xe0000000 0x8000
erase 0xe0000000 0x10000
erase 0xe0000000 0x18000
erase 0xe0000000 0x20000
erase 0xe0000000 0x28000
erase 0xe0000000 0x30000
erase 0xe0000000 0x38000
erase 0xe0000000 0x40000
erase 0xe0000000 0x48000
erase 0xe0000000 0x50000
erase 0xe0000000 0x58000
erase 0xe0000000 0x60000
erase 0xe0000000 0x70000
erase 0xe0000000 0x78000
erase-wait 0xe0000000
# should now have erased from 0xe0000000 to 0xe00fffff
dump-mem 0xe0010000 0x20 b
erase 0xe0000000 0x1000
erase-wait 0xe0000000
erase 0xe0000000 0x2000
erase-wait 0xe0000000
erase 0xe0000000 0x3000
erase-wait 0xe0000000
erase 0xe0000000 0x4000
erase-wait 0xe0000000
erase 0xe0000000 0x5000
erase-wait 0xe0000000
erase 0xe0000000 0x6000
erase-wait 0xe0000000
erase 0xe0000000 0x7000
erase-wait 0xe0000000
erase 0xe0000000 0x8000
erase-wait 0xe0000000
erase 0xe0000000 0x10000
erase-wait 0xe0000000
erase 0xe0000000 0x18000
erase-wait 0xe0000000
erase 0xe0000000 0x20000
erase-wait 0xe0000000
erase 0xe0000000 0x28000
erase-wait 0xe0000000
erase 0xe0000000 0x30000
erase-wait 0xe0000000
erase 0xe0000000 0x38000
erase-wait 0xe0000000
erase 0xe0000000 0x40000
erase-wait 0xe0000000
erase 0xe0000000 0x48000
erase-wait 0xe0000000
erase 0xe0000000 0x50000
erase-wait 0xe0000000
erase 0xe0000000 0x58000
erase-wait 0xe0000000
load -v ../firebee/bas.elf
wait

2
flash_scripts/flash_m548x_etos.bdm
View File

@@ -63,4 +63,4 @@ erase 0xe0000000 37
erase 0xe0000000 38
erase 0xe0000000 39
load ../../emutos/emutos-m548x-bas_gcc.elf
load ../../emutos/emutos-m548x_bas.elf

2
fs/ccsbcs.c
View File

@@ -26,7 +26,7 @@
*/
#include <ff.h>
#include <bas_types.h>
#include <stdint.h>
#if _CODE_PAGE == 437
#define _TBLDEF 1

20
fs/ff.c
View File

@@ -95,7 +95,7 @@
/ Changed option name _FS_SHARE to _FS_LOCK.
/---------------------------------------------------------------------------*/
#include <bas_types.h>
#include <stdint.h>
#include <ff.h> /* FatFs configurations and declarations */
#include <diskio.h> /* Declarations of low level disk I/O functions */
@@ -356,11 +356,11 @@ typedef struct {
uint32_t get_fattime (void)
{
return ((uint32_t)(2012 - 1980) << 25) /* Year = 2012 */
| ((uint32_t)1 << 21) /* Month = 1 */
| ((uint32_t)1 << 16) /* Day_m = 1*/
| ((uint32_t)0 << 11) /* Hour = 0 */
| ((uint32_t)0 << 5) /* Min = 0 */
| ((uint32_t)0 >> 1); /* Sec = 0 */
| ((uint32_t)1 << 21) /* Month = 1 */
| ((uint32_t)1 << 16) /* Day_m = 1*/
| ((uint32_t)0 << 11) /* Hour = 0 */
| ((uint32_t)0 << 5) /* Min = 0 */
| ((uint32_t)0 >> 1); /* Sec = 0 */
}
/* Character code support macros */
@@ -970,7 +970,7 @@ FRESULT remove_chain (
#if _USE_ERASE
if (ecl + 1 == nxt) { /* Is next cluster contiguous? */
ecl = nxt;
} else { /* End of contiguous clusters */
} else { /* End of contiguous clusters */
rt[0] = clust2sect(fs, scl); /* Start sector */
rt[1] = clust2sect(fs, ecl) + fs->csize - 1; /* End sector */
disk_ioctl(fs->drv, CTRL_ERASE_SECTOR, rt); /* Erase the block */
@@ -2190,7 +2190,7 @@ FRESULT chk_mounted ( /* FR_OK(0): successful, !=0: any error occurred */
/* Get fsinfo if available */
if (fmt == FS_FAT32) {
fs->fsi_flag = 0;
fs->fsi_flag = 0;
fs->fsi_sector = bsect + LD_WORD(fs->win+BPB_FSInfo);
if (disk_read(fs->drv, fs->win, fs->fsi_sector, 1) == RES_OK &&
LD_WORD(fs->win+BS_55AA) == 0xAA55 &&
@@ -2721,7 +2721,7 @@ FRESULT f_close (
FATFS *fs = fp->fs;;
res = validate(fp);
if (res == FR_OK) {
res = dec_lock(fp->lockid);
res = dec_lock(fp->lockid);
unlock_fs(fs, FR_OK);
}
#else
@@ -2820,7 +2820,7 @@ FRESULT f_getcwd (
res = dir_read(&dj);
if (res != FR_OK) break;
if (ccl == ld_clust(dj.fs, dj.dir)) break; /* Found the entry */
res = dir_next(&dj, 0);
res = dir_next(&dj, 0);
} while (res == FR_OK);
if (res == FR_NO_FILE) res = FR_INT_ERR;/* It cannot be 'not found'. */
if (res != FR_OK) break;

41
i2c/i2c.c
View File

@@ -1,41 +0,0 @@
#include <bas_types.h>
void i2c_init(void)
{
}
void i2c_set_frequency(int hz)
{
}
int i2c_read(int address, char *data, int length, bool repeated)
{
return 0;
}
int i2c_read_byte(int ack)
{
return 0;
}
int i2c_write(int address, const char *data, int length, bool repeated)
{
return 0;
}
int i2c_write_byte(int data)
{
return 0;
}
void i2c_start(void)
{
}
void i2c_stop(void)
{
}

12
if/driver_vec.c
View File

@@ -132,16 +132,6 @@ static struct framebuffer_driver_interface framebuffer_interface =
.framebuffer_info = &info_fb
};
/*
* driver interface struct for the BaS MMU driver
*/
static struct mmu_driver_interface mmu_interface =
{
.map_page_locked = &mmu_map_data_page_locked,
.unlock_page = &mmu_unlock_data_page,
.report_locked_pages = &mmu_report_locked_pages,
.report_pagesize = &mmu_report_pagesize
};
static struct generic_interface interfaces[] =
{
@@ -185,7 +175,7 @@ static struct generic_interface interfaces[] =
.description = "BaS MMU driver",
.version = 0,
.revision = 1,
.interface.mmu = &mmu_interface,
.interface.mmu = NULL,
},
/* insert new drivers here */

143
include/MCD_dma.h
View File

@@ -7,11 +7,14 @@
#ifndef _MCD_API_H
#define _MCD_API_H
#include "bas_types.h"
/*
* Turn Execution Unit tasks ON (#define) or OFF (#undef)
*/
#undef MCD_INCLUDE_EU
//#define MCD_INCLUDE_EU
/*
* Number of DMA channels
*/
@@ -46,39 +49,33 @@
/*
* Portability typedefs
*/
typedef int s32;
typedef unsigned int u32;
typedef short s16;
typedef unsigned short u16;
typedef char s8;
typedef unsigned char u8;
/*
* These structures represent the internal registers of the
* multi-channel DMA
*/
struct dmaRegs_s {
u32 taskbar; /* task table base address register */
u32 currPtr;
u32 endPtr;
u32 varTablePtr;
u16 dma_rsvd0;
u16 ptdControl; /* ptd control */
u32 intPending; /* interrupt pending register */
u32 intMask; /* interrupt mask register */
u16 taskControl[16]; /* task control registers */
u8 priority[32]; /* priority registers */
u32 initiatorMux; /* initiator mux control */
u32 taskSize0; /* task size control register 0. */
u32 taskSize1; /* task size control register 1. */
u32 dma_rsvd1; /* reserved */
u32 dma_rsvd2; /* reserved */
u32 debugComp1; /* debug comparator 1 */
u32 debugComp2; /* debug comparator 2 */
u32 debugControl; /* debug control */
u32 debugStatus; /* debug status */
u32 ptdDebug; /* priority task decode debug */
u32 dma_rsvd3[31]; /* reserved */
uint32_t taskbar; /* task table base address register */
uint32_t currPtr;
uint32_t endPtr;
uint32_t varTablePtr;
uint16_t dma_rsvd0;
uint16_t ptdControl; /* ptd control */
uint32_t intPending; /* interrupt pending register */
uint32_t intMask; /* interrupt mask register */
uint16_t taskControl[16]; /* task control registers */
uint8_t priority[32]; /* priority registers */
uint32_t initiatorMux; /* initiator mux control */
uint32_t taskSize0; /* task size control register 0. */
uint32_t taskSize1; /* task size control register 1. */
uint32_t dma_rsvd1; /* reserved */
uint32_t dma_rsvd2; /* reserved */
uint32_t debugComp1; /* debug comparator 1 */
uint32_t debugComp2; /* debug comparator 2 */
uint32_t debugControl; /* debug control */
uint32_t debugStatus; /* debug status */
uint32_t ptdDebug; /* priority task decode debug */
uint32_t dma_rsvd3[31]; /* reserved */
};
typedef volatile struct dmaRegs_s dmaRegs;
@@ -164,7 +161,7 @@ typedef volatile struct dmaRegs_s dmaRegs;
*/
/* Byte swapping: */
#define MCD_NO_BYTE_SWAP 0x00045670 /* to disable byte swapping. */
#define MCD_BYTE_REVERSE 0x00076540 /* to reverse the bytes of each u32 of the DMAed data. */
#define MCD_BYTE_REVERSE 0x00076540 /* to reverse the bytes of each uint32_t of the DMAed data. */
#define MCD_U16_REVERSE 0x00067450 /* to reverse the 16-bit halves of
each 32-bit data value being DMAed.*/
#define MCD_U16_BYTE_REVERSE 0x00054760 /* to reverse the byte halves of each
@@ -231,44 +228,44 @@ typedef volatile struct dmaRegs_s dmaRegs;
/* Task Table Entry struct*/
typedef struct {
u32 TDTstart; /* task descriptor table start */
u32 TDTend; /* task descriptor table end */
u32 varTab; /* variable table start */
u32 FDTandFlags; /* function descriptor table start and flags */
volatile u32 descAddrAndStatus;
volatile u32 modifiedVarTab;
u32 contextSaveSpace; /* context save space start */
u32 literalBases;
uint32_t TDTstart; /* task descriptor table start */
uint32_t TDTend; /* task descriptor table end */
uint32_t varTab; /* variable table start */
uint32_t FDTandFlags; /* function descriptor table start and flags */
volatile uint32_t descAddrAndStatus;
volatile uint32_t modifiedVarTab;
uint32_t contextSaveSpace; /* context save space start */
uint32_t literalBases;
} TaskTableEntry;
/* Chained buffer descriptor */
typedef volatile struct MCD_bufDesc_struct MCD_bufDesc;
struct MCD_bufDesc_struct {
u32 flags; /* flags describing the DMA */
u32 csumResult; /* checksum from checksumming performed since last checksum reset */
s8 *srcAddr; /* the address to move data from */
s8 *destAddr; /* the address to move data to */
s8 *lastDestAddr; /* the last address written to */
u32 dmaSize; /* the number of bytes to transfer independent of the transfer size */
uint32_t flags; /* flags describing the DMA */
uint32_t csumResult; /* checksum from checksumming performed since last checksum reset */
int8_t *srcAddr; /* the address to move data from */
int8_t *destAddr; /* the address to move data to */
int8_t *lastDestAddr; /* the last address written to */
uint32_t dmaSize; /* the number of bytes to transfer independent of the transfer size */
MCD_bufDesc *next; /* next buffer descriptor in chain */
u32 info; /* private information about this descriptor; DMA does not affect it */
uint32_t info; /* private information about this descriptor; DMA does not affect it */
};
/* Progress Query struct */
typedef volatile struct MCD_XferProg_struct {
s8 *lastSrcAddr; /* the most-recent or last, post-increment source address */
s8 *lastDestAddr; /* the most-recent or last, post-increment destination address */
u32 dmaSize; /* the amount of data transferred for the current buffer */
int8_t *lastSrcAddr; /* the most-recent or last, post-increment source address */
int8_t *lastDestAddr; /* the most-recent or last, post-increment destination address */
uint32_t dmaSize; /* the amount of data transferred for the current buffer */
MCD_bufDesc *currBufDesc;/* pointer to the current buffer descriptor being DMAed */
} MCD_XferProg;
/* FEC buffer descriptor */
typedef volatile struct MCD_bufDescFec_struct {
u16 statCtrl;
u16 length;
u32 dataPointer;
uint16_t statCtrl;
uint16_t length;
uint32_t dataPointer;
} MCD_bufDescFec;
@@ -282,65 +279,65 @@ typedef volatile struct MCD_bufDescFec_struct {
*/
int MCD_startDma (
int channel, /* the channel on which to run the DMA */
s8 *srcAddr, /* the address to move data from, or buffer-descriptor address */
s16 srcIncr, /* the amount to increment the source address per transfer */
s8 *destAddr, /* the address to move data to */
s16 destIncr, /* the amount to increment the destination address per transfer */
u32 dmaSize, /* the number of bytes to transfer independent of the transfer size */
u32 xferSize, /* the number bytes in of each data movement (1, 2, or 4) */
u32 initiator, /* what device initiates the DMA */
int8_t *srcAddr, /* the address to move data from, or buffer-descriptor address */
int16_t srcIncr, /* the amount to increment the source address per transfer */
int8_t *destAddr, /* the address to move data to */
int16_t destIncr, /* the amount to increment the destination address per transfer */
uint32_t dmaSize, /* the number of bytes to transfer independent of the transfer size */
uint32_t xferSize, /* the number bytes in of each data movement (1, 2, or 4) */
uint32_t initiator, /* what device initiates the DMA */
int priority, /* priority of the DMA */
u32 flags, /* flags describing the DMA */
u32 funcDesc /* a description of byte swapping, bit swapping, and CRC actions */
uint32_t flags, /* flags describing the DMA */
uint32_t funcDesc /* a description of byte swapping, bit swapping, and CRC actions */
);
/*
* MCD_initDma() initializes the DMA API by setting up a pointer to the DMA
* registers, relocating and creating the appropriate task structures, and
/*
* MCD_initDma() initializes the DMA API by setting up a pointer to the DMA
* registers, relocating and creating the appropriate task structures, and
* setting up some global settings
*/
int MCD_initDma (dmaRegs *sDmaBarAddr, void *taskTableDest, u32 flags);
int MCD_initDma (dmaRegs *sDmaBarAddr, void *taskTableDest, uint32_t flags);
/*
/*
* MCD_dmaStatus() returns the status of the DMA on the requested channel.
*/
int MCD_dmaStatus (int channel);
/*
/*
* MCD_XferProgrQuery() returns progress of DMA on requested channel
*/
int MCD_XferProgrQuery (int channel, MCD_XferProg *progRep);
/*
/*
* MCD_killDma() halts the DMA on the requested channel, without any
* intention of resuming the DMA.
*/
int MCD_killDma (int channel);
/*
/*
* MCD_continDma() continues a DMA which as stopped due to encountering an
* unready buffer descriptor.
*/
int MCD_continDma (int channel);
/*
/*
* MCD_pauseDma() pauses the DMA on the given channel ( if any DMA is
* running on that channel).
* running on that channel).
*/
int MCD_pauseDma (int channel);
/*
/*
* MCD_resumeDma() resumes the DMA on a given channel (if any DMA is
* running on that channel).
*/
int MCD_resumeDma (int channel);
/*
/*
* MCD_csumQuery provides the checksum/CRC after performing a non-chained DMA
*/
int MCD_csumQuery (int channel, u32 *csum);
int MCD_csumQuery (int channel, uint32_t *csum);
/*
/*
* MCD_getCodeSize provides the packed size required by the microcoded task
* and structures.
*/
@@ -353,7 +350,7 @@ int MCD_getCodeSize(void);
int MCD_getVersion(char **longVersion);
/* macro for setting a location in the variable table */
#define MCD_SET_VAR(taskTab,idx,value) ((u32 *)(taskTab)->varTab)[idx] = value
#define MCD_SET_VAR(taskTab,idx,value) ((uint32_t *)(taskTab)->varTab)[idx] = value
/* Note that MCD_SET_VAR() is invoked many times in firing up a DMA function,
so I'm avoiding surrounding it with "do {} while(0)" */

8
include/MCD_tasksInit.h
View File

@@ -15,7 +15,7 @@ void MCD_startDmaChainNoEu(int *currBD, short srcIncr, short destIncr, int xfer
/*
* Task 1
*/
void MCD_startDmaSingleNoEu(char *srcAddr, short srcIncr, char *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel);
void MCD_startDmaSingleNoEu(int8_t *srcAddr, short srcIncr, int8_t *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel);
/*
@@ -27,18 +27,18 @@ void MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr, int xferSi
/*
* Task 3
*/
void MCD_startDmaSingleEu(char *srcAddr, short srcIncr, char *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel);
void MCD_startDmaSingleEu(int8_t *srcAddr, short srcIncr, int8_t *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel);
/*
* Task 4
*/
void MCD_startDmaENetRcv(char *bDBase, char *currBD, char *rcvFifoPtr, volatile TaskTableEntry *taskTable, int channel);
void MCD_startDmaENetRcv(int8_t *bDBase, int8_t *currBD, int8_t *rcvFifoPtr, volatile TaskTableEntry *taskTable, int channel);
/*
* Task 5
*/
void MCD_startDmaENetXmit(char *bDBase, char *currBD, char *xmitFifoPtr, volatile TaskTableEntry *taskTable, int channel);
void MCD_startDmaENetXmit(int8_t *bDBase, int8_t *currBD, int8_t *xmitFifoPtr, volatile TaskTableEntry *taskTable, int channel);
#endif /* MCD_TSK_INIT_H */

2
include/MCF5475.h
View File

@@ -16,7 +16,7 @@
#ifndef __MCF5475_H__
#define __MCF5475_H__
#include <bas_types.h>
#include <stdint.h>
/***
* MCF5475 Derivative Memory map definitions from linker command files:
* __MBAR, __MMUBAR, __RAMBAR0, __RAMBAR0_SIZE, __RAMBAR1, __RAMBAR1_SIZE

1
include/MCF5475_INTC.h
View File

@@ -107,6 +107,7 @@
#define MCF_INTC_LIACK(x) (*(volatile uint8_t *)(&_MBAR[0x7E4 + ((x-1)*0x4)]))
/* Bit definitions and macros for MCF_INTC_IPRH */
#define MCF_INTC_IPRH_INT32 (0x1)
#define MCF_INTC_IPRH_INT33 (0x2)

8
include/MCF5475_MMU.h
View File

@@ -62,7 +62,7 @@
/* Bit definitions and macros for MCF_MMU_MMUTR */
#define MCF_MMU_MMUTR_V (0x1)
#define MCF_MMU_MMUTR_SG (0x2)
#define MCF_MMU_MMUTR_ID(x) (((x) & 0xFF) << 0x2)
#define MCF_MMU_MMUTR_ID(x) (((x)&0xFF)<<0x2)
#define MCF_MMU_MMUTR_VA(x) (((x)&0x3FFFFF)<<0xA)
/* Bit definitions and macros for MCF_MMU_MMUDR */
@@ -71,9 +71,9 @@
#define MCF_MMU_MMUDR_W (0x8)
#define MCF_MMU_MMUDR_R (0x10)
#define MCF_MMU_MMUDR_SP (0x20)
#define MCF_MMU_MMUDR_CM(x) (((x) & 0x3) << 0x6)
#define MCF_MMU_MMUDR_SZ(x) (((x) & 0x3) << 0x8)
#define MCF_MMU_MMUDR_PA(x) (((x) & 0x3FFFFF) << 0xA)
#define MCF_MMU_MMUDR_CM(x) (((x)&0x3)<<0x6)
#define MCF_MMU_MMUDR_SZ(x) (((x)&0x3)<<0x8)
#define MCF_MMU_MMUDR_PA(x) (((x)&0x3FFFFF)<<0xA)
#endif /* __MCF5475_MMU_H__ */

1
include/bas_types.h
View File

@@ -30,6 +30,5 @@
#include <stdint.h>
#include <stdbool.h>
#include <stddef.h> /* for sizeof() etc. */
#endif /* BAS_TYPES_H_ */

6
include/cache.h
View File

@@ -25,7 +25,8 @@
*
*/
#include <bas_types.h>
#include <stdint.h>
#include <stddef.h>
/*
* CACR Cache Control Register
@@ -53,7 +54,6 @@
#define CF_CACR_ICINVA (0x00000100) /* Instr Cache Invalidate All */
#define CF_CACR_IDSP (0x00000080) /* Ins default supervisor-protect */
#define CF_CACR_EUSP (0x00000020) /* Switch stacks in user mode */
#define CF_CACR_DF (0x00000010) /* Disable FPU */
#define _DCACHE_SET_MASK ((DCACHE_SIZE/64-1)<<CACHE_WAYS)
#define _ICACHE_SET_MASK ((ICACHE_SIZE/64-1)<<CACHE_WAYS)
@@ -83,7 +83,7 @@ extern uint32_t cacr_get(void);
extern void cacr_set(uint32_t);
extern void flush_icache_range(void *address, size_t size);
extern void flush_dcache_range(void *address, size_t size);
extern void flush_cache_range(void *address, size_t size);
#endif /* _CACHE_H_ */

2
include/diskio.h
View File

@@ -12,7 +12,7 @@ extern "C" {
#define _USE_WRITE 1 /* 1: Enable disk_write function */
#define _USE_IOCTL 1 /* 1: Enable disk_ioctl fucntion */
#include <bas_types.h>
#include <stdint.h>
/* Status of Disk Functions */

8
include/dma.h
View File

@@ -26,6 +26,10 @@
#include "MCD_dma.h"
#include "bas_string.h"
#define DMA_INTC_LVL 6
#define DMA_INTC_PRI 0
void *dma_memcpy(void *dst, void *src, size_t n);
extern int dma_init(void);
extern int dma_get_channel(int requestor);
@@ -35,9 +39,9 @@ extern void dma_clear_channel(int channel);
extern uint32_t dma_get_initiator(int requestor);
extern int dma_set_initiator(int initiator);
extern void dma_free_initiator(int initiator);
extern void dma_irq_enable(void);
extern void dma_irq_enable(uint8_t lvl, uint8_t pri);
extern void dma_irq_disable(void);
extern bool dma_interrupt_handler(void *arg1, void *arg2);
extern int dma_interrupt_handler(void *arg1, void *arg2);
#endif /* _DMA_H_ */

119
include/driver_vec.h
View File

@@ -38,7 +38,7 @@ enum driver_type
VIDEO_DRIVER,
PCI_DRIVER,
MMU_DRIVER,
END_OF_DRIVERS = 0xffffffff, /* marks end of driver list */
END_OF_DRIVERS = 0xffffffff /* marks end of driver list */
};
struct generic_driver_interface
@@ -80,8 +80,7 @@ struct xhdi_driver_interface
uint32_t (*xhdivec)();
};
/*
* Interpretation of offset for color fields: All offsets are from the right,
/* Interpretation of offset for color fields: All offsets are from the right,
* inside a "pixel" value, which is exactly 'bits_per_pixel' wide (means: you
* can use the offset as right argument to <<). A pixel afterwards is a bit
* stream and is written to video memory as that unmodified. This implies
@@ -92,7 +91,7 @@ struct fb_bitfield
unsigned long offset; /* beginning of bitfield */
unsigned long length; /* length of bitfield */
unsigned long msb_right; /* != 0 : Most significant bit is */
/* right */
/* right */
};
/*
@@ -105,19 +104,19 @@ struct fb_var_screeninfo
unsigned long xres_virtual; /* virtual resolution */
unsigned long yres_virtual;
unsigned long xoffset; /* offset from virtual to visible */
unsigned long yoffset; /* resolution */
unsigned long yoffset; /* resolution */
unsigned long bits_per_pixel; /* guess what */
unsigned long bits_per_pixel; /* guess what */
unsigned long grayscale; /* != 0 Graylevels instead of colors */
struct fb_bitfield red; /* bitfield in fb mem if true color, */
struct fb_bitfield green; /* else only length is significant */
struct fb_bitfield blue;
struct fb_bitfield transp; /* transparency */
struct fb_bitfield transp; /* transparency */
unsigned long nonstd; /* != 0 Non standard pixel format */
unsigned long activate; /* see FB_ACTIVATE_* */
unsigned long activate; /* see FB_ACTIVATE_* */
unsigned long height; /* height of picture in mm */
unsigned long width; /* width of picture in mm */
@@ -132,7 +131,7 @@ struct fb_var_screeninfo
unsigned long lower_margin;
unsigned long hsync_len; /* length of horizontal sync */
unsigned long vsync_len; /* length of vertical sync */
unsigned long sync; /* see FB_SYNC_* */
unsigned long sync; /* see FB_SYNC_* */
unsigned long vmode; /* see FB_VMODE_* */
unsigned long rotate; /* angle we rotate counter clockwise */
unsigned long refresh;
@@ -143,9 +142,9 @@ struct fb_fix_screeninfo
{
char id[16]; /* identification string eg "TT Builtin" */
unsigned long smem_start; /* Start of frame buffer mem */
/* (physical address) */
/* (physical address) */
unsigned long smem_len; /* Length of frame buffer mem */
unsigned long type; /* see FB_TYPE_* */
unsigned long type; /* see FB_TYPE_* */
unsigned long type_aux; /* Interleave for interleaved Planes */
unsigned long visual; /* see FB_VISUAL_* */
unsigned short xpanstep; /* zero if no hardware panning */
@@ -153,10 +152,10 @@ struct fb_fix_screeninfo
unsigned short ywrapstep; /* zero if no hardware ywrap */
unsigned long line_length; /* length of a line in bytes */
unsigned long mmio_start; /* Start of Memory Mapped I/O */
/* (physical address) */
/* (physical address) */
unsigned long mmio_len; /* Length of Memory Mapped I/O */
unsigned long accel; /* Indicate to driver which */
/* specific chip/card we have */
/* specific chip/card we have */
unsigned short reserved[3]; /* Reserved for future compatibility */
};
@@ -205,7 +204,7 @@ struct fb_monspecs
struct framebuffer_driver_interface
{
struct fb_info **framebuffer_info; /* pointer to an fb_info struct (defined in include/fb.h) */
struct fb_info **framebuffer_info; /* pointer to an fb_info struct (defined in include/fb.h) */
};
struct pci_bios_interface
@@ -213,53 +212,53 @@ struct pci_bios_interface
uint32_t subjar;
uint32_t version;
/* Although we declare this functions as standard gcc functions (cdecl),
* they expect parameters inside registers (fastcall) unsupported by gcc m68k.
* they expect paramenters inside registers (fastcall) unsupported by gcc m68k.
* Caller will take care of parameters passing convention.
*/
int32_t (*find_pci_device)(uint32_t id, uint16_t index);
int32_t (*find_pci_classcode)(uint32_t class, uint16_t index);
int32_t (*read_config_byte)(int32_t handle, uint16_t reg, uint8_t *address);
int32_t (*read_config_word)(int32_t handle, uint16_t reg, uint16_t *address);
int32_t (*read_config_longword)(int32_t handle, uint16_t reg, uint32_t *address);
uint8_t (*fast_read_config_byte)(int32_t handle, uint16_t reg);
uint16_t (*fast_read_config_word)(int32_t handle, uint16_t reg);
uint32_t (*fast_read_config_longword)(int32_t handle, uint16_t reg);
int32_t (*write_config_byte)(int32_t handle, uint16_t reg, uint16_t val);
int32_t (*write_config_word)(int32_t handle, uint16_t reg, uint16_t val);
int32_t (*write_config_longword)(int32_t handle, uint16_t reg, uint32_t val);
int32_t (*hook_interrupt)(int32_t handle, uint32_t *routine, uint32_t *parameter);
int32_t (*unhook_interrupt)(int32_t handle);
int32_t (*special_cycle)(uint16_t bus, uint32_t data);
int32_t (*get_routing)(int32_t handle);
int32_t (*set_interrupt)(int32_t handle);
int32_t (*get_resource)(int32_t handle);
int32_t (*get_card_used)(int32_t handle, uint32_t *address);
int32_t (*set_card_used)(int32_t handle, uint32_t *callback);
int32_t (*read_mem_byte)(int32_t handle, uint32_t offset, uint8_t *address);
int32_t (*read_mem_word)(int32_t handle, uint32_t offset, uint16_t *address);
int32_t (*read_mem_longword)(int32_t handle, uint32_t offset, uint32_t *address);
uint8_t (*fast_read_mem_byte)(int32_t handle, uint32_t offset);
uint16_t (*fast_read_mem_word)(int32_t handle, uint32_t offset);
uint32_t (*fast_read_mem_longword)(int32_t handle, uint32_t offset);
int32_t (*write_mem_byte)(int32_t handle, uint32_t offset, uint16_t val);
int32_t (*write_mem_word)(int32_t handle, uint32_t offset, uint16_t val);
int32_t (*write_mem_longword)(int32_t handle, uint32_t offset, uint32_t val);
int32_t (*read_io_byte)(int32_t handle, uint32_t offset, uint8_t *address);
int32_t (*read_io_word)(int32_t handle, uint32_t offset, uint16_t *address);
int32_t (*read_io_longword)(int32_t handle, uint32_t offset, uint32_t *address);
uint8_t (*fast_read_io_byte)(int32_t handle, uint32_t offset);
uint16_t (*fast_read_io_word)(int32_t handle, uint32_t offset);
uint32_t (*fast_read_io_longword)(int32_t handle, uint32_t offset);
int32_t (*write_io_byte)(int32_t handle, uint32_t offset, uint16_t val);
int32_t (*write_io_word)(int32_t handle, uint32_t offset, uint16_t val);
int32_t (*write_io_longword)(int32_t handle, uint32_t offset, uint32_t val);
int32_t (*get_machine_id)(void);
int32_t (*get_pagesize)(void);
int32_t (*virt_to_bus)(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer);
int32_t (*bus_to_virt)(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer);
int32_t (*virt_to_phys)(uint32_t address, PCI_CONV_ADR *pointer);
int32_t (*phys_to_virt)(uint32_t address, PCI_CONV_ADR *pointer);
// int32_t reserved[2];
int32_t (*find_pci_device) (uint32_t id, uint16_t index);
int32_t (*find_pci_classcode) (uint32_t class, uint16_t index);
int32_t (*read_config_byte) (int32_t handle, uint16_t reg, uint8_t *address);
int32_t (*read_config_word) (int32_t handle, uint16_t reg, uint16_t *address);
int32_t (*read_config_longword) (int32_t handle, uint16_t reg, uint32_t *address);
uint8_t (*fast_read_config_byte) (int32_t handle, uint16_t reg);
uint16_t (*fast_read_config_word) (int32_t handle, uint16_t reg);
uint32_t (*fast_read_config_longword) (int32_t handle, uint16_t reg);
int32_t (*write_config_byte) (int32_t handle, uint16_t reg, uint16_t val);
int32_t (*write_config_word) (int32_t handle, uint16_t reg, uint16_t val);
int32_t (*write_config_longword) (int32_t handle, uint16_t reg, uint32_t val);
int32_t (*hook_interrupt) (int32_t handle, uint32_t *routine, uint32_t *parameter);
int32_t (*unhook_interrupt) (int32_t handle);
int32_t (*special_cycle) (uint16_t bus, uint32_t data);
int32_t (*get_routing) (int32_t handle);
int32_t (*set_interrupt) (int32_t handle);
int32_t (*get_resource) (int32_t handle);
int32_t (*get_card_used) (int32_t handle, uint32_t *address);
int32_t (*set_card_used) (int32_t handle, uint32_t *callback);
int32_t (*read_mem_byte) (int32_t handle, uint32_t offset, uint8_t *address);
int32_t (*read_mem_word) (int32_t handle, uint32_t offset, uint16_t *address);
int32_t (*read_mem_longword) (int32_t handle, uint32_t offset, uint32_t *address);
uint8_t (*fast_read_mem_byte) (int32_t handle, uint32_t offset);
uint16_t (*fast_read_mem_word) (int32_t handle, uint32_t offset);
uint32_t (*fast_read_mem_longword) (int32_t handle, uint32_t offset);
int32_t (*write_mem_byte) (int32_t handle, uint32_t offset, uint16_t val);
int32_t (*write_mem_word) (int32_t handle, uint32_t offset, uint16_t val);
int32_t (*write_mem_longword) (int32_t handle, uint32_t offset, uint32_t val);
int32_t (*read_io_byte) (int32_t handle, uint32_t offset, uint8_t *address);
int32_t (*read_io_word) (int32_t handle, uint32_t offset, uint16_t *address);
int32_t (*read_io_longword) (int32_t handle, uint32_t offset, uint32_t *address);
uint8_t (*fast_read_io_byte) (int32_t handle, uint32_t offset);
uint16_t (*fast_read_io_word) (int32_t handle, uint32_t offset);
uint32_t (*fast_read_io_longword) (int32_t handle, uint32_t offset);
int32_t (*write_io_byte) (int32_t handle, uint32_t offset, uint16_t val);
int32_t (*write_io_word) (int32_t handle, uint32_t offset, uint16_t val);
int32_t (*write_io_longword) (int32_t handle, uint32_t offset, uint32_t val);
int32_t (*get_machine_id) (void);
int32_t (*get_pagesize) (void);
int32_t (*virt_to_bus) (int32_t handle, uint32_t address, PCI_CONV_ADR *pointer);
int32_t (*bus_to_virt) (int32_t handle, uint32_t address, PCI_CONV_ADR *pointer);
int32_t (*virt_to_phys) (uint32_t address, PCI_CONV_ADR *pointer);
int32_t (*phys_to_virt) (uint32_t address, PCI_CONV_ADR *pointer);
// int32_t reserved[2];
};
struct mmu_driver_interface
@@ -294,7 +293,7 @@ struct driver_table
{
uint32_t bas_version;
uint32_t bas_revision;
void (*remove_handler)(void); /* calling this will disable the BaS' hook into trap #0 */
void (*remove_handler)(void); /* calling this will disable the BaS' hook into trap #0 */
struct generic_interface *interfaces;
};

183
include/ehci.h
View File

@@ -23,42 +23,43 @@
#define USB_EHCI_H
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 5
#if !defined(CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS)
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2
#endif
/* (shifted) direction/type/recipient from the USB 2.0 spec, table 9.2 */
#define DeviceRequest \
((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8)
((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8)
#define DeviceOutRequest \
((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8)
((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8)
#define InterfaceRequest \
((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
#define EndpointRequest \
((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
#define EndpointOutRequest \
((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
/*
* Register Space.
*/
struct ehci_hccr
{
uint32_t cr_capbase;
struct ehci_hccr {
uint32_t cr_capbase;
#define HC_LENGTH(p) (((p) >> 0) & 0x00ff)
#define HC_VERSION(p) (((p) >> 16) & 0xffff)
uint32_t cr_hcsparams;
#define HCS_PPC(p) ((p) & (1 << 4))
uint32_t cr_hcsparams;
#define HCS_PPC(p) ((p) & (1 << 4))
#define HCS_INDICATOR(p) ((p) & (1 << 16)) /* Port indicators */
#define HCS_N_PORTS(p) (((p) >> 0) & 0xf)
uint32_t cr_hccparams;
uint8_t cr_hcsp_portrt[8];
uint32_t cr_hccparams;
uint8_t cr_hcsp_portrt[8];
} __attribute__ ((packed));
struct ehci_hcor
{
uint32_t or_usbcmd;
struct ehci_hcor {
uint32_t or_usbcmd;
#define CMD_PARK (1 << 11) /* enable "park" */
#define CMD_PARK_CNT(c) (((c) >> 8) & 3) /* how many transfers to park */
#define CMD_ASE (1 << 5) /* async schedule enable */
@@ -67,74 +68,72 @@ struct ehci_hcor
#define CMD_PSE (1 << 4) /* periodic schedule enable */
#define CMD_RESET (1 << 1) /* reset HC not bus */
#define CMD_RUN (1 << 0) /* start/stop HC */
uint32_t or_usbsts;
uint32_t or_usbsts;
#define STD_ASS (1 << 15)
#define STS_PSSTAT (1 << 14)
#define STS_RECL (1 << 13)
#define STS_PSSTAT (1 << 14)
#define STS_RECL ( 1 << 13)
#define STS_HALT (1 << 12)
#define STS_IAA (1 << 5)
#define STS_HSE (1 << 4)
#define STS_FLR (1 << 3)
#define STS_PCD (1 << 2)
#define STS_IAA (1 << 5)
#define STS_HSE (1 << 4)
#define STS_FLR (1 << 3)
#define STS_PCD (1 << 2)
#define STS_USBERRINT (1 << 1)
#define STS_USBINT (1 << 0)
uint32_t or_usbintr;
#define INTR_IAAE (1 << 5)
#define INTR_HSEE (1 << 4)
#define INTR_FLRE (1 << 3)
#define INTR_PCDE (1 << 2)
#define STS_USBINT (1 << 0)
uint32_t or_usbintr;
#define INTR_IAAE (1 << 5)
#define INTR_HSEE (1 << 4)
#define INTR_FLRE (1 << 3)
#define INTR_PCDE (1 << 2)
#define INTR_USBERRINTE (1 << 1)
#define INTR_USBINTE (1 << 0)
uint32_t or_frindex;
uint32_t or_ctrldssegment;
uint32_t or_periodiclistbase;
uint32_t or_asynclistaddr;
uint32_t _reserved_[9];
uint32_t or_configflag;
uint32_t or_frindex;
uint32_t or_ctrldssegment;
uint32_t or_periodiclistbase;
uint32_t or_asynclistaddr;
uint32_t _reserved_[9];
uint32_t or_configflag;
#define FLAG_CF (1 << 0) /* true: we'll support "high speed" */
uint32_t or_portsc[CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS];
uint32_t or_systune;
uint32_t or_portsc[CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS];
uint32_t or_systune;
} __attribute__ ((packed));
#define USBMODE 0x68 /* USB Device mode */
#define USBMODE 0x68 /* USB Device mode */
#define USBMODE_SDIS (1 << 3) /* Stream disable */
#define USBMODE_BE (1 << 2) /* BE/LE endiannes select */
#define USBMODE_BE (1 << 2) /* BE/LE endiannes select */
#define USBMODE_CM_HC (3 << 0) /* host controller mode */
#define USBMODE_CM_IDLE (0 << 0) /* idle state */
/* Interface descriptor */
struct usb_linux_interface_descriptor
{
unsigned char bLength;
unsigned char bDescriptorType;
unsigned char bInterfaceNumber;
unsigned char bAlternateSetting;
unsigned char bNumEndpoints;
unsigned char bInterfaceClass;
unsigned char bInterfaceSubClass;
unsigned char bInterfaceProtocol;
unsigned char iInterface;
struct usb_linux_interface_descriptor {
unsigned char bLength;
unsigned char bDescriptorType;
unsigned char bInterfaceNumber;
unsigned char bAlternateSetting;
unsigned char bNumEndpoints;
unsigned char bInterfaceClass;
unsigned char bInterfaceSubClass;
unsigned char bInterfaceProtocol;
unsigned char iInterface;
} __attribute__ ((packed));
/* Configuration descriptor information.. */
struct usb_linux_config_descriptor
{
unsigned char bLength;
unsigned char bDescriptorType;
unsigned short wTotalLength;
unsigned char bNumInterfaces;
unsigned char bConfigurationValue;
unsigned char iConfiguration;
unsigned char bmAttributes;
unsigned char MaxPower;
struct usb_linux_config_descriptor {
unsigned char bLength;
unsigned char bDescriptorType;
unsigned short wTotalLength;
unsigned char bNumInterfaces;
unsigned char bConfigurationValue;
unsigned char iConfiguration;
unsigned char bmAttributes;
unsigned char MaxPower;
} __attribute__ ((packed));
#if defined CONFIG_EHCI_DESC_BIG_ENDIAN
#define ehci_readl(x) (*((volatile uint32_t *)(x)))
#define ehci_writel(a, b) (*((volatile uint32_t *)(a)) = ((volatile uint32_t) b))
#define ehci_readl(x) (*((volatile u32 *)(x)))
#define ehci_writel(a, b) (*((volatile u32 *)(a)) = ((volatile u32)b))
#else
#define ehci_readl(x) swpl((*((volatile uint32_t *)(x))))
#define ehci_writel(a, b) (*((volatile uint32_t *)(a)) = swpl(((volatile uint32_t) b)))
#define ehci_readl(x) swpl((*((volatile u32 *)(x))))
#define ehci_writel(a, b) (*((volatile u32 *)(a)) = swpl(((volatile u32)b)))
#endif
#if defined CONFIG_EHCI_MMIO_BIG_ENDIAN
@@ -148,18 +147,18 @@ struct usb_linux_config_descriptor
#define EHCI_PS_WKOC_E (1 << 22) /* RW wake on over current */
#define EHCI_PS_WKDSCNNT_E (1 << 21) /* RW wake on disconnect */
#define EHCI_PS_WKCNNT_E (1 << 20) /* RW wake on connect */
#define EHCI_PS_PO (1 << 13) /* RW port owner */
#define EHCI_PS_PP (1 << 12) /* RW,RO port power */
#define EHCI_PS_LS (3 << 10) /* RO line status */
#define EHCI_PS_PR (1 << 8) /* RW port reset */
#define EHCI_PS_SUSP (1 << 7) /* RW suspend */
#define EHCI_PS_FPR (1 << 6) /* RW force port resume */
#define EHCI_PS_OCC (1 << 5) /* RWC over current change */
#define EHCI_PS_OCA (1 << 4) /* RO over current active */
#define EHCI_PS_PEC (1 << 3) /* RWC port enable change */
#define EHCI_PS_PE (1 << 2) /* RW port enable */
#define EHCI_PS_CSC (1 << 1) /* RWC connect status change */
#define EHCI_PS_CS (1 << 0) /* RO connect status */
#define EHCI_PS_PO (1 << 13) /* RW port owner */
#define EHCI_PS_PP (1 << 12) /* RW,RO port power */
#define EHCI_PS_LS (3 << 10) /* RO line status */
#define EHCI_PS_PR (1 << 8) /* RW port reset */
#define EHCI_PS_SUSP (1 << 7) /* RW suspend */
#define EHCI_PS_FPR (1 << 6) /* RW force port resume */
#define EHCI_PS_OCC (1 << 5) /* RWC over current change */
#define EHCI_PS_OCA (1 << 4) /* RO over current active */
#define EHCI_PS_PEC (1 << 3) /* RWC port enable change */
#define EHCI_PS_PE (1 << 2) /* RW port enable */
#define EHCI_PS_CSC (1 << 1) /* RWC connect status change */
#define EHCI_PS_CS (1 << 0) /* RO connect status */
#define EHCI_PS_CLEAR (EHCI_PS_OCC | EHCI_PS_PEC | EHCI_PS_CSC)
#define EHCI_PS_IS_LOWSPEED(x) (((x) & EHCI_PS_LS) == (1 << 10))
@@ -175,33 +174,31 @@ struct usb_linux_config_descriptor
*/
/* Queue Element Transfer Descriptor (qTD). */
struct qTD
{
uint32_t qt_next;
struct qTD {
uint32_t qt_next;
#define QT_NEXT_TERMINATE 1
uint32_t qt_altnext;
uint32_t qt_token;
uint32_t qt_buffer[5];
uint32_t qt_altnext;
uint32_t qt_token;
uint32_t qt_buffer[5];
};
/* Queue Head (QH). */
struct QH
{
uint32_t qh_link;
struct QH {
uint32_t qh_link;
#define QH_LINK_TERMINATE 1
#define QH_LINK_TYPE_ITD 0
#define QH_LINK_TYPE_QH 2
#define QH_LINK_TYPE_SITD 4
#define QH_LINK_TYPE_FSTN 6
uint32_t qh_endpt1;
uint32_t qh_endpt2;
uint32_t qh_curtd;
struct qTD qh_overlay;
/*
* Add dummy fill value to make the size of this struct
* aligned to 32 bytes
*/
uint8_t fill[16];
uint32_t qh_endpt1;
uint32_t qh_endpt2;
uint32_t qh_curtd;
struct qTD qh_overlay;
/*
* Add dummy fill value to make the size of this struct
* aligned to 32 bytes
*/
uint8_t fill[16];
};
/* Low level init functions */

4
include/exceptions.h
View File

@@ -1,7 +1,7 @@
#ifndef _EXCEPTIONS_H_
#define _EXCEPTIONS_H_
#include <bas_types.h>
#include <stdint.h>
static inline uint32_t set_ipl(uint32_t ipl)
{
@@ -19,7 +19,7 @@ static inline uint32_t set_ipl(uint32_t ipl)
" lsr.l #8,%[ret]\r\n" /* shift them to position */
: [ret] "=&d" (ret) /* output */
: [ipl] "d" (ipl) /* input */
: "cc", "d0" /* clobber */
: "d0" /* clobber */
);
return ret;

2
include/fb.h
View File

@@ -528,6 +528,7 @@ struct fb_videomode {
extern const struct fb_videomode vesa_modes[];
/* timer */
extern void udelay(long usec);
#ifdef COLDFIRE
#ifdef MCF5445X
#define US_TO_TIMER(a) (a)
@@ -540,7 +541,6 @@ extern const struct fb_videomode vesa_modes[];
#define US_TO_TIMER(a) (((a)*256)/5000)
#define TIMER_TO_US(a) (((a)*5000)/256)
#endif
extern void start_timeout(void);
extern int end_timeout(long msec);
extern void mdelay(long msec);

54
include/fec.h
View File

@@ -2,7 +2,7 @@
* File: fec.h
* Purpose: Driver for the Fast Ethernet Controller (FEC)
*
* Notes:
* Notes:
*/
#ifndef _FEC_H_
@@ -30,30 +30,30 @@
*/
typedef struct
{
int total; /* total count of errors */
int hberr; /* heartbeat error */
int babr; /* babbling receiver */
int babt; /* babbling transmitter */
int gra; /* graceful stop complete */
int txf; /* transmit frame */
int mii; /* MII */
int lc; /* late collision */
int rl; /* collision retry limit */
int xfun; /* transmit FIFO underrrun */
int xferr; /* transmit FIFO error */
int rferr; /* receive FIFO error */
int dtxf; /* DMA transmit frame */
int drxf; /* DMA receive frame */
int rfsw_inv; /* Invalid bit in RFSW */
int rfsw_l; /* RFSW Last in Frame */
int rfsw_m; /* RFSW Miss */
int rfsw_bc; /* RFSW Broadcast */
int rfsw_mc; /* RFSW Multicast */
int rfsw_lg; /* RFSW Length Violation */
int rfsw_no; /* RFSW Non-octet */
int rfsw_cr; /* RFSW Bad CRC */
int rfsw_ov; /* RFSW Overflow */
int rfsw_tr; /* RFSW Truncated */
int total; /* total count of errors */
int hberr; /* heartbeat error */
int babr; /* babbling receiver */
int babt; /* babbling transmitter */
int gra; /* graceful stop complete */
int txf; /* transmit frame */
int mii; /* MII */
int lc; /* late collision */
int rl; /* collision retry limit */
int xfun; /* transmit FIFO underrrun */
int xferr; /* transmit FIFO error */
int rferr; /* receive FIFO error */
int dtxf; /* DMA transmit frame */
int drxf; /* DMA receive frame */
int rfsw_inv; /* Invalid bit in RFSW */
int rfsw_l; /* RFSW Last in Frame */
int rfsw_m; /* RFSW Miss */
int rfsw_bc; /* RFSW Broadcast */
int rfsw_mc; /* RFSW Multicast */
int rfsw_lg; /* RFSW Length Violation */
int rfsw_no; /* RFSW Non-octet */
int rfsw_cr; /* RFSW Bad CRC */
int rfsw_ov; /* RFSW Overflow */
int rfsw_tr; /* RFSW Truncated */
} FEC_EVENT_LOG;
@@ -87,8 +87,8 @@ extern int fec1_send(NIF *, uint8_t *, uint8_t *, uint16_t , NBUF *);
extern void fec_irq_enable(uint8_t, uint8_t, uint8_t);
extern void fec_irq_disable(uint8_t);
extern void fec_interrupt_handler(uint8_t);
extern bool fec0_interrupt_handler(void *, void *);
extern bool fec1_interrupt_handler(void *, void *);
extern int fec0_interrupt_handler(void *, void *);
extern int fec1_interrupt_handler(void *, void *);
extern void fec_eth_setup(uint8_t, uint8_t, uint8_t, uint8_t, const uint8_t *);
extern void fec_eth_reset(uint8_t);
extern void fec_eth_stop(uint8_t);

2
include/ff.h
View File

@@ -21,7 +21,7 @@
extern "C" {
#endif
#include <bas_types.h>
#include <stdint.h>
#include <ffconf.h> /* FatFs configuration options */
#if _FATFS != _FFCONF

23
include/i2c-algo-bit.h
View File

@@ -32,19 +32,18 @@
* manipulate the line states, and to init any hw-specific features. This is
* only used if you have more than one hw-type of adapter running.
*/
struct i2c_algo_bit_data
{
void *data; /* private data for lowlevel routines */
void (*setsda) (void *data, int state);
void (*setscl) (void *data, int state);
int (*getsda) (void *data);
int (*getscl) (void *data);
struct i2c_algo_bit_data {
void *data; /* private data for lowlevel routines */
void (*setsda) (void *data, int state);
void (*setscl) (void *data, int state);
int (*getsda) (void *data);
int (*getscl) (void *data);
/* local settings */
int udelay; /* half-clock-cycle time in microsecs */
/* i.e. clock is (500 / udelay) KHz */
int mdelay; /* in millisecs, unused */
int timeout; /* in jiffies */
/* local settings */
int udelay; /* half-clock-cycle time in microsecs */
/* i.e. clock is (500 / udelay) KHz */
int mdelay; /* in millisecs, unused */
int timeout; /* in jiffies */
};
#define I2C_BIT_ADAP_MAX 16

58
include/i2c.h
View File

@@ -28,8 +28,6 @@
#ifndef _I2C_H
#define _I2C_H
#include "bas_types.h"
/* --- General options ------------------------------------------------ */
struct i2c_msg;
@@ -46,51 +44,39 @@ extern int i2c_transfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
* be addressed using the same bus algorithms - i.e. bit-banging or the PCF8584
* to name two of the most common.
*/
struct i2c_algorithm
{
unsigned int id;
int (*master_xfer)(struct i2c_adapter *adap,struct i2c_msg *msgs, int num);
/* --- ioctl like call to set div. parameters. */
int (*algo_control)(struct i2c_adapter *, unsigned int, unsigned long);
struct i2c_algorithm {
unsigned int id;
int (*master_xfer)(struct i2c_adapter *adap,struct i2c_msg *msgs, int num);
/* --- ioctl like call to set div. parameters. */
int (*algo_control)(struct i2c_adapter *, unsigned int, unsigned long);
};
/*
* i2c_adapter is the structure used to identify a physical i2c bus along
* with the access algorithms necessary to access it.
*/
struct i2c_adapter
{
struct i2c_algorithm *algo; /* the algorithm to access the bus */
void *algo_data;
int timeout;
int retries;
int nr;
struct i2c_adapter {
struct i2c_algorithm *algo;/* the algorithm to access the bus */
void *algo_data;
int timeout;
int retries;
int nr;
};
/*
* I2C Message - used for pure i2c transaction, also from /dev interface
*/
struct i2c_msg
{
unsigned short addr; /* slave address */
unsigned short flags;
#define I2C_M_TEN 0x10 /* we have a ten bit chip address */
#define I2C_M_RD 0x01
#define I2C_M_NOSTART 0x4000
#define I2C_M_REV_DIR_ADDR 0x2000
#define I2C_M_IGNORE_NAK 0x1000
#define I2C_M_NO_RD_ACK 0x0800
unsigned short len; /* msg length */
unsigned char *buf; /* pointer to msg data */
struct i2c_msg {
unsigned short addr; /* slave address */
unsigned short flags;
#define I2C_M_TEN 0x10 /* we have a ten bit chip address */
#define I2C_M_RD 0x01
#define I2C_M_NOSTART 0x4000
#define I2C_M_REV_DIR_ADDR 0x2000
#define I2C_M_IGNORE_NAK 0x1000
#define I2C_M_NO_RD_ACK 0x0800
unsigned short len; /* msg length */
unsigned char *buf; /* pointer to msg data */
};
extern void i2c_init(void);
extern void i2c_set_frequency(int hz);
extern int i2c_read(int address, char *data, int lengt, bool repeated);
extern int i2c_read_byte(int ack);
extern int i2c_write(int address, const char *data, int length, bool repeated);
extern int i2c_write_byte(int data);
extern void i2c_start(void);
extern void i2c_stop(void);
#endif /* _I2C_H */

170
include/interrupts.h
View File

@@ -27,123 +27,81 @@
#include <stdbool.h>
/* interrupt sources */
#define INT_SOURCE_EPORT_EPF1 1 // edge port flag 1
#define INT_SOURCE_EPORT_EPF2 2 // edge port flag 2
#define INT_SOURCE_EPORT_EPF3 3 // edge port flag 3
#define INT_SOURCE_EPORT_EPF4 4 // edge port flag 4
#define INT_SOURCE_EPORT_EPF5 5 // edge port flag 5
#define INT_SOURCE_EPORT_EPF6 6 // edge port flag 6
#define INT_SOURCE_EPORT_EPF7 7 // edge port flag 7
#define INT_SOURCE_USB_EP0ISR 15 // USB endpoint 0 interrupt
#define INT_SOURCE_USB_EP1ISR 16 // USB endpoint 1 interrupt
#define INT_SOURCE_USB_EP2ISR 17 // USB endpoint 2 interrupt
#define INT_SOURCE_USB_EP3ISR 18 // USB endpoint 3 interrupt
#define INT_SOURCE_USB_EP4ISR 19 // USB endpoint 4 interrupt
#define INT_SOURCE_USB_EP5ISR 20 // USB endpoint 5 interrupt
#define INT_SOURCE_USB_EP6ISR 21 // USB endpoint 6 interrupt
#define INT_SOURCE_USB_USBISR 22 // USB general interrupt
#define INT_SOURCE_USB_USBAISR 23 // USB core interrupt
#define INT_SOURCE_USB_ANY 24 // OR of all USB interrupts
#define INT_SOURCE_USB_DSPI_OVF 25 // DSPI overflow or underflow
#define INT_SOURCE_USB_DSPI_RFOF 26 // receive FIFO overflow interrupt
#define INT_SOURCE_USB_DSPI_RFDF 27 // receive FIFO drain interrupt
#define INT_SOURCE_USB_DSPI_TFUF 28 // transmit FIFO underflow interrupt
#define INT_SOURCE_USB_DSPI_TCF 29 // transfer complete interrupt
#define INT_SOURCE_USB_DSPI_TFFF 30 // transfer FIFO fill interrupt
#define INT_SOURCE_USB_DSPI_EOQF 31 // end of queue interrupt
#define INT_SOURCE_PSC3 32 // PSC3 interrupt
#define INT_SOURCE_PSC2 33 // PSC2 interrupt
#define INT_SOURCE_PSC1 34 // PSC1 interrupt
#define INT_SOURCE_PSC0 35 // PSC0 interrupt
#define INT_SOURCE_CTIMERS 36 // combined source for comm timers
#define INT_SOURCE_SEC 37 // SEC interrupt
#define INT_SOURCE_FEC1 38 // FEC1 interrupt
#define INT_SOURCE_FEC0 39 // FEC0 interrupt
#define INT_SOURCE_I2C 40 // I2C interrupt
#define INT_SOURCE_PCIARB 41 // PCI arbiter interrupt
#define INT_SOURCE_CBPCI 42 // COMM bus PCI interrupt
#define INT_SOURCE_XLBPCI 43 // XLB PCI interrupt
#define INT_SOURCE_XLBARB 47 // XLBARB to PCI interrupt
#define INT_SOURCE_DMA 48 // multichannel DMA interrupt
#define INT_SOURCE_CAN0_ERROR 49 // FlexCAN error interrupt
#define INT_SOURCE_CAN0_BUSOFF 50 // FlexCAN bus off interrupt
#define INT_SOURCE_CAN0_MBOR 51 // message buffer ORed interrupt
#define INT_SOURCE_SLT1 53 // slice timer 1 interrupt
#define INT_SOURCE_SLT0 54 // slice timer 0 interrupt
#define INT_SOURCE_CAN1_ERROR 55 // FlexCAN error interrupt
#define INT_SOURCE_CAN1_BUSOFF 56 // FlexCAN bus off interrupt
#define INT_SOURCE_CAN1_MBOR 57 // message buffer ORed interrupt
#define INT_SOURCE_GPT3 59 // GPT3 timer interrupt
#define INT_SOURCE_GPT2 60 // GPT2 timer interrupt
#define INT_SOURCE_GPT1 61 // GPT1 timer interrupt
#define INT_SOURCE_GPT0 62 // GPT0 timer interrupt
#define INT_SOURCE_EPORT_EPF1 1 // edge port flag 1
#define INT_SOURCE_EPORT_EPF2 2 // edge port flag 2
#define INT_SOURCE_EPORT_EPF3 3 // edge port flag 3
#define INT_SOURCE_EPORT_EPF4 4 // edge port flag 4
#define INT_SOURCE_EPORT_EPF5 5 // edge port flag 5
#define INT_SOURCE_EPORT_EPF6 6 // edge port flag 6
#define INT_SOURCE_EPORT_EPF7 7 // edge port flag 7
#define INT_SOURCE_USB_EP0ISR 15 // USB endpoint 0 interrupt
#define INT_SOURCE_USB_EP1ISR 16 // USB endpoint 1 interrupt
#define INT_SOURCE_USB_EP2ISR 17 // USB endpoint 2 interrupt
#define INT_SOURCE_USB_EP3ISR 18 // USB endpoint 3 interrupt
#define INT_SOURCE_USB_EP4ISR 19 // USB endpoint 4 interrupt
#define INT_SOURCE_USB_EP5ISR 20 // USB endpoint 5 interrupt
#define INT_SOURCE_USB_EP6ISR 21 // USB endpoint 6 interrupt
#define INT_SOURCE_USB_USBISR 22 // USB general interrupt
#define INT_SOURCE_USB_USBAISR 23 // USB core interrupt
#define INT_SOURCE_USB_ANY 24 // OR of all USB interrupts
#define INT_SOURCE_USB_DSPI_OVF 25 // DSPI overflow or underflow
#define INT_SOURCE_USB_DSPI_RFOF 26 // receive FIFO overflow interrupt
#define INT_SOURCE_USB_DSPI_RFDF 27 // receive FIFO drain interrupt
#define INT_SOURCE_USB_DSPI_TFUF 28 // transmit FIFO underflow interrupt
#define INT_SOURCE_USB_DSPI_TCF 29 // transfer complete interrupt
#define INT_SOURCE_USB_DSPI_TFFF 30 // transfer FIFO fill interrupt
#define INT_SOURCE_USB_DSPI_EOQF 31 // end of queue interrupt
#define INT_SOURCE_PSC3 32 // PSC3 interrupt
#define INT_SOURCE_PSC2 33 // PSC2 interrupt
#define INT_SOURCE_PSC1 34 // PSC1 interrupt
#define INT_SOURCE_PSC0 35 // PSC0 interrupt
#define INT_SOURCE_CTIMERS 36 // combined source for comm timers
#define INT_SOURCE_SEC 37 // SEC interrupt
#define INT_SOURCE_FEC1 38 // FEC1 interrupt
#define INT_SOURCE_FEC0 39 // FEC0 interrupt
#define INT_SOURCE_I2C 40 // I2C interrupt
#define INT_SOURCE_PCIARB 41 // PCI arbiter interrupt
#define INT_SOURCE_CBPCI 42 // COMM bus PCI interrupt
#define INT_SOURCE_XLBPCI 43 // XLB PCI interrupt
#define INT_SOURCE_XLBARB 47 // XLBARB to PCI interrupt
#define INT_SOURCE_DMA 48 // multichannel DMA interrupt
#define INT_SOURCE_CAN0_ERROR 49 // FlexCAN error interrupt
#define INT_SOURCE_CAN0_BUSOFF 50 // FlexCAN bus off interrupt
#define INT_SOURCE_CAN0_MBOR 51 // message buffer ORed interrupt
#define INT_SOURCE_SLT1 53 // slice timer 1 interrupt
#define INT_SOURCE_SLT0 54 // slice timer 0 interrupt
#define INT_SOURCE_CAN1_ERROR 55 // FlexCAN error interrupt
#define INT_SOURCE_CAN1_BUSOFF 56 // FlexCAN bus off interrupt
#define INT_SOURCE_CAN1_MBOR 57 // message buffer ORed interrupt
#define INT_SOURCE_GPT3 59 // GPT3 timer interrupt
#define INT_SOURCE_GPT2 60 // GPT2 timer interrupt
#define INT_SOURCE_GPT1 61 // GPT1 timer interrupt
#define INT_SOURCE_GPT0 62 // GPT0 timer interrupt
#define FEC0_INTC_LVL 6 /* interrupt level for FEC0 */
#define FEC0_INTC_PRI 7 /* interrupt priority for FEC0 */
#define FEC0_INTC_LVL 1 /* interrupt level for FEC0 */
#define FEC0_INTC_PRI 2 /* interrupt priority for FEC0 */
#define FEC1_INTC_LVL 6 /* interrupt level for FEC1 */
#define FEC1_INTC_PRI 6 /* interrupt priority for FEC1 */
#define FEC1_INTC_LVL 1 /* interrupt level for FEC1 */
#define FEC1_INTC_PRI 2 /* interrupt priority for FEC1 */
#define FEC_INTC_LVL(x) ((x == 0) ? FEC0_INTC_LVL : FEC1_INTC_LVL)
#define FEC_INTC_PRI(x) ((x == 0) ? FEC0_INTC_PRI : FEC1_INTC_PRI)
#define FEC_INTC_LVL(x) ((x == 0) ? FEC0_INTC_LVL : FEC1_INTC_LVL)
#define FEC_INTC_PRI(x) ((x == 0) ? FEC0_INTC_PRI : FEC1_INTC_PRI)
#define FEC0RX_DMA_PRI 5
#define FEC1RX_DMA_PRI 4
#define FEC1RX_DMA_PRI 5
#define FECRX_DMA_PRI(x) ((x == 0) ? FEC0RX_DMA_PRI : FEC1RX_DMA_PRI)
#define FEC0TX_DMA_PRI 2
#define FEC1TX_DMA_PRI 1
#define FEC0TX_DMA_PRI 6
#define FEC1TX_DMA_PRI 6
#define FECTX_DMA_PRI(x) ((x == 0) ? FEC0TX_DMA_PRI : FEC1TX_DMA_PRI)
#if defined(MACHINE_FIREBEE)
extern int register_interrupt_handler(uint8_t source, uint8_t level, uint8_t priority, uint8_t intr, void (*handler)(void));
/* Firebee FPGA interrupt controller */
#define FBEE_INTR_CONTROL * ((volatile uint32_t *) 0xf0010000)
#define FBEE_INTR_ENABLE * ((volatile uint32_t *) 0xf0010004)
#define FBEE_INTR_CLEAR * ((volatile uint32_t *) 0xf0010008)
#define FBEE_INTR_PENDING * ((volatile uint32_t *) 0xff01000c)
/* register bits for Firebee FPGA-based interrupt controller */
#define FBEE_INTR_PIC (1 << 0) /* PIC interrupt enable/pending/clear bit */
#define FBEE_INTR_ETHERNET (1 << 1) /* ethernet PHY interrupt enable/pending/clear bit */
#define FBEE_INTR_DVI (1 << 2) /* TFP410 monitor sense interrupt enable/pending/clear bit */
#define FBEE_INTR_PCI_INTA (1 << 3) /* /PCIINTA enable/pending clear bit */
#define FBEE_INTR_PCI_INTB (1 << 4) /* /PCIINTB enable/pending clear bit */
#define FBEE_INTR_PCI_INTC (1 << 5) /* /PCIINTC enable/pending clear bit */
#define FBEE_INTR_PCI_INTD (1 << 6) /* /PCIINTD enable/pending clear bit */
#define FBEE_INTR_DSP (1 << 7) /* DSP interrupt enable/pending/clear bit */
#define FBEE_INTR_VSYNC (1 << 8) /* VSYNC interrupt enable/pending/clear bit */
#define FBEE_INTR_HSYNC (1 << 9) /* HSYNC interrupt enable/pending/clear bit */
#define FBEE_INTR_INT_HSYNC_IRQ2 (1 << 26) /* these bits are only meaningful for the FBEE_INTR_ENABLE register */
#define FBEE_INTR_INT_CTR0_IRQ3 (1 << 27)
#define FBEE_INTR_INT_VSYNC_IRQ4 (1 << 28)
#define FBEE_INTR_INT_FPGA_IRQ5 (1 << 29)
#define FBEE_INTR_INT_MFP_IRQ6 (1 << 30)
#define FBEE_INTR_INT_IRQ7 (1 << 31)
/*
* Atari MFP interrupt registers.
*/
#define FALCON_MFP_IERA *((volatile uint8_t *) 0xfffffa07)
#define FALCON_MFP_IERB *((volatile uint8_t *) 0xfffffa09)
#define FALCON_MFP_IPRA *((volatile uint8_t *) 0xfffffa0b)
#define FALCON_MFP_IPRB *((volatile uint8_t *) 0xfffffa0d)
#define FALCON_MFP_IMRA *((volatile uint8_t *) 0xfffffa13)
#define FALCON_MFP_IMRB *((volatile uint8_t *) 0xfffffa15)
#endif /* MACHINE_FIREBEE */
#define ISR_DBUG_ISR 0x01
#define ISR_USER_ISR 0x02
extern void isr_init(void);
extern bool isr_set_prio_and_level(int int_source, int priority, int level);
extern bool isr_enable_int_source(int int_source);
extern bool isr_register_handler(int vector, int level, int priority, bool (*handler)(void *, void *), void *hdev, void *harg);
extern void isr_remove_handler(bool (*handler)(void *, void *));
extern int isr_register_handler(int vector, int (*handler)(void *, void *), void *hdev, void *harg);
extern void isr_remove_handler(int (*handler)(void *, void *));
extern bool isr_execute_handler(int vector);
extern bool pic_interrupt_handler(void *arg1, void *arg2);
extern bool xlbpci_interrupt_handler(void *arg1, void *arg2);
extern bool pciarb_interrupt_handler(void *arg1, void *arg2);
extern bool gpt0_interrupt_handler(void *arg1, void *arg2);
extern bool irq5_handler(void *arg1, void *arg2);
#endif /* _INTERRUPTS_H_ */

39
include/mmu.h
View File

@@ -24,7 +24,6 @@
#ifndef _MMU_H_
#define _MMU_H_
#include <stddef.h>
#include "bas_types.h"
/*
@@ -55,21 +54,10 @@
/*
* MMU page sizes
*/
enum mmu_page_size
{
MMU_PAGE_SIZE_1M = 0,
MMU_PAGE_SIZE_4K = 1,
MMU_PAGE_SIZE_8K = 2,
MMU_PAGE_SIZE_1K = 3
};
#define SIZE_1M 0x100000 /* 1 Megabyte */
#define SIZE_4K 0x1000 /* 4 KB */
#define SIZE_8K 0x2000 /* 8 KB */
#define SIZE_1K 0x400 /* 1 KB */
#define DEFAULT_PAGE_SIZE 0x00100000 /* 1M pagesize */
#define MMU_PAGE_SIZE_1M 0
#define MMU_PAGE_SIZE_4K 1
#define MMU_PAGE_SIZE_8K 2
#define MMU_PAGE_SIZE_1K 3
/*
* cache modes
@@ -90,6 +78,14 @@ enum mmu_page_size
#define ACCESS_WRITE (1 << 1)
#define ACCESS_EXECUTE (1 << 2)
struct map_flags
{
unsigned cache_mode:2;
unsigned protection:1;
unsigned page_id:8;
unsigned access:3;
unsigned unused:18;
};
/*
* global variables from linker script
@@ -97,16 +93,7 @@ enum mmu_page_size
extern long video_tlb;
extern long video_sbt;
struct mmu_page_descriptor;
extern void mmu_init(void);
extern int mmu_map_page(int32_t virt, int32_t phys, enum mmu_page_size sz, uint8_t page_id, const struct mmu_page_descriptor *flags);
extern void mmu_map_page(uint32_t virt, uint32_t phys, uint32_t map_size, struct map_flags flags);
/*
* API functions for the BaS driver interface
*/
extern int32_t mmu_map_data_page_locked(uint32_t address, uint32_t length, int asid);
extern int32_t mmu_unlock_data_page(uint32_t address, uint32_t length, int asid);
extern int32_t mmu_report_locked_pages(uint32_t *num_itlb, uint32_t *num_dtlb);
extern uint32_t mmu_report_pagesize(void);
#endif /* _MMU_H_ */

51
include/mod_devicetable.h
View File

@@ -3,14 +3,10 @@
#define PCI_ANY_ID (~0)
struct pci_device_id
{
unsigned long vendor; /* Vendor and device ID or PCI_ANY_ID*/
unsigned long device;
unsigned long subvendor; /* Subsystem ID's or PCI_ANY_ID */
unsigned long subdevice;
unsigned long class; /* (class,subclass,prog-if) triplet */
unsigned long class_mask;
struct pci_device_id {
unsigned long vendor, device; /* Vendor and device ID or PCI_ANY_ID*/
unsigned long subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */
unsigned long class, class_mask; /* (class,subclass,prog-if) triplet */
unsigned long driver_data; /* Data private to the driver */
};
@@ -19,8 +15,7 @@ struct pci_device_id
#define IEEE1394_MATCH_SPECIFIER_ID 0x0004
#define IEEE1394_MATCH_VERSION 0x0008
struct ieee1394_device_id
{
struct ieee1394_device_id {
unsigned long match_flags;
unsigned long vendor_id;
unsigned long model_id;
@@ -86,8 +81,7 @@ struct ieee1394_device_id
* matches towards the beginning of your table, so that driver_info can
* record quirks of specific products.
*/
struct usb_device_id
{
struct usb_device_id {
/* which fields to match against? */
unsigned short match_flags;
@@ -112,10 +106,10 @@ struct usb_device_id
};
/* Some useful macros to use to create struct usb_device_id */
#define USB_DEVICE_ID_MATCH_VENDOR 0x0001
#define USB_DEVICE_ID_MATCH_PRODUCT 0x0002
#define USB_DEVICE_ID_MATCH_DEV_LO 0x0004
#define USB_DEVICE_ID_MATCH_DEV_HI 0x0008
#define USB_DEVICE_ID_MATCH_VENDOR 0x0001
#define USB_DEVICE_ID_MATCH_PRODUCT 0x0002
#define USB_DEVICE_ID_MATCH_DEV_LO 0x0004
#define USB_DEVICE_ID_MATCH_DEV_HI 0x0008
#define USB_DEVICE_ID_MATCH_DEV_CLASS 0x0010
#define USB_DEVICE_ID_MATCH_DEV_SUBCLASS 0x0020
#define USB_DEVICE_ID_MATCH_DEV_PROTOCOL 0x0040
@@ -124,19 +118,18 @@ struct usb_device_id
#define USB_DEVICE_ID_MATCH_INT_PROTOCOL 0x0200
/* s390 CCW devices */
struct ccw_device_id
{
struct ccw_device_id {
unsigned short match_flags; /* which fields to match against */
unsigned short cu_type; /* control unit type */
unsigned short dev_type; /* device type */
unsigned char cu_model; /* control unit model */
unsigned char dev_model; /* device model */
unsigned short cu_type; /* control unit type */
unsigned short dev_type; /* device type */
unsigned char cu_model; /* control unit model */
unsigned char dev_model; /* device model */
unsigned long driver_info;
};
#define CCW_DEVICE_ID_MATCH_CU_TYPE 0x01
#define CCW_DEVICE_ID_MATCH_CU_TYPE 0x01
#define CCW_DEVICE_ID_MATCH_CU_MODEL 0x02
#define CCW_DEVICE_ID_MATCH_DEVICE_TYPE 0x04
#define CCW_DEVICE_ID_MATCH_DEVICE_MODEL 0x08
@@ -145,18 +138,15 @@ struct ccw_device_id
#define PNP_ID_LEN 8
#define PNP_MAX_DEVICES 8
struct pnp_device_id
{
struct pnp_device_id {
unsigned char id[PNP_ID_LEN];
unsigned long driver_data;
};
struct pnp_card_device_id
{
struct pnp_card_device_id {
unsigned char id[PNP_ID_LEN];
unsigned long driver_data;
struct
{
struct {
unsigned char id[PNP_ID_LEN];
} devs[PNP_MAX_DEVICES];
};
@@ -164,8 +154,7 @@ struct pnp_card_device_id
#define SERIO_ANY 0xff
struct serio_device_id
{
struct serio_device_id {
unsigned char type;
unsigned char extra;
unsigned char id;

1
include/nbuf.h
View File

@@ -10,6 +10,7 @@
#include "bas_types.h"
/********************************************************************/
/*
* Include the Queue structure definitions
*/

4
include/net_timer.h
View File

@@ -8,7 +8,9 @@
#ifndef _TIMER_H_
#define _TIMER_H_
#include <bas_types.h>
#include <stdint.h>
#include <stdbool.h>
#include <stddef.h>
typedef struct
{

355
include/ohci.h
View File

@@ -6,63 +6,63 @@
*
* usb-ohci.h
*/
#define USB_OHCI_MAX_ROOT_PORTS 4
static int cc_to_error[16] =
{
static int cc_to_error[16] = {
/* mapping of the OHCI CC status to error codes */
/* No Error */ 0,
/* CRC Error */ USB_ST_CRC_ERR,
/* Bit Stuff */ USB_ST_BIT_ERR,
/* Data Togg */ USB_ST_CRC_ERR,
/* Stall */ USB_ST_STALLED,
/* DevNotResp */ -1,
/* PIDCheck */ USB_ST_BIT_ERR,
/* UnExpPID */ USB_ST_BIT_ERR,
/* DataOver */ USB_ST_BUF_ERR,
/* DataUnder */ USB_ST_BUF_ERR,
/* reservd */ -1,
/* reservd */ -1,
/* BufferOver */ USB_ST_BUF_ERR,
/* BuffUnder */ USB_ST_BUF_ERR,
/* Not Access */ -1,
/* Not Access */ -1
/* No Error */ 0,
/* CRC Error */ USB_ST_CRC_ERR,
/* Bit Stuff */ USB_ST_BIT_ERR,
/* Data Togg */ USB_ST_CRC_ERR,
/* Stall */ USB_ST_STALLED,
/* DevNotResp */ -1,
/* PIDCheck */ USB_ST_BIT_ERR,
/* UnExpPID */ USB_ST_BIT_ERR,
/* DataOver */ USB_ST_BUF_ERR,
/* DataUnder */ USB_ST_BUF_ERR,
/* reservd */ -1,
/* reservd */ -1,
/* BufferOver */ USB_ST_BUF_ERR,
/* BuffUnder */ USB_ST_BUF_ERR,
/* Not Access */ -1,
/* Not Access */ -1
};
static const char *cc_to_string[16] =
{
"No Error",
"CRC: Last data packet from endpoint contained a CRC error.",
"BITSTUFFING:\r\nLast data packet from endpoint contained a bit stuffing violation",
"DATATOGGLEMISMATCH:\r\n Last packet from endpoint had data toggle PID\r\n" \
"that did not match the expected value.",
"STALL: TD was moved to the Done Queue because the endpoint returned a STALL PID",
"DEVICENOTRESPONDING:\r\nDevice did not respond to token (IN) or did\r\n" \
"not provide a handshake (OUT)",
"PIDCHECKFAILURE:\r\nCheck bits on PID from endpoint failed on data PID\r\n"\
"(IN) or handshake (OUT)",
"UNEXPECTEDPID:\r\nReceive PID was not valid when encountered or PID\r\n" \
"value is not defined.",
"DATAOVERRUN:\r\nThe amount of data returned by the endpoint exceeded\r\n" \
"either the size of the maximum data packet allowed\r\n" \
"from the endpoint (found in MaximumPacketSize field\r\n" \
"of ED) or the remaining buffer size.",
"DATAUNDERRUN:\r\nThe endpoint returned less than MaximumPacketSize\r\n" \
"and that amount was not sufficient to fill the\r\n" \
"specified buffer",
"reserved1",
"reserved2",
"BUFFEROVERRUN:\r\nDuring an IN, HC received data from endpoint faster\r\n" \
"than it could be written to system memory",
"BUFFERUNDERRUN:\r\nDuring an OUT, HC could not retrieve data from\r\n" \
"system memory fast enough to keep up with data USB data rate.",
"NOT ACCESSED:\r\nThis code is set by software before the TD is placed\r\n" \
"on a list to be processed by the HC.(1)",
"NOT ACCESSED:\r\nThis code is set by software before the TD is placed\r\n" \
"on a list to be processed by the HC.(2)",
#ifdef DEBUG
static const char *cc_to_string[16] = {
"No Error",
"CRC: Last data packet from endpoint contained a CRC error.",
"BITSTUFFING:\r\nLast data packet from endpoint contained a bit stuffing violation",
"DATATOGGLEMISMATCH:\r\n Last packet from endpoint had data toggle PID\r\n" \
"that did not match the expected value.",
"STALL: TD was moved to the Done Queue because the endpoint returned a STALL PID",
"DEVICENOTRESPONDING:\r\nDevice did not respond to token (IN) or did\r\n" \
"not provide a handshake (OUT)",
"PIDCHECKFAILURE:\r\nCheck bits on PID from endpoint failed on data PID\r\n"\
"(IN) or handshake (OUT)",
"UNEXPECTEDPID:\r\nReceive PID was not valid when encountered or PID\r\n" \
"value is not defined.",
"DATAOVERRUN:\r\nThe amount of data returned by the endpoint exceeded\r\n" \
"either the size of the maximum data packet allowed\r\n" \
"from the endpoint (found in MaximumPacketSize field\r\n" \
"of ED) or the remaining buffer size.",
"DATAUNDERRUN:\r\nThe endpoint returned less than MaximumPacketSize\r\n" \
"and that amount was not sufficient to fill the\r\n" \
"specified buffer",
"reserved1",
"reserved2",
"BUFFEROVERRUN:\r\nDuring an IN, HC received data from endpoint faster\r\n" \
"than it could be written to system memory",
"BUFFERUNDERRUN:\r\nDuring an OUT, HC could not retrieve data from\r\n" \
"system memory fast enough to keep up with data USB data rate.",
"NOT ACCESSED:\r\nThis code is set by software before the TD is placed\r\n" \
"on a list to be processed by the HC.(1)",
"NOT ACCESSED:\r\nThis code is set by software before the TD is placed\r\n" \
"on a list to be processed by the HC.(2)",
};
#endif /* DEBUG */
/* ED States */
@@ -73,26 +73,25 @@ static const char *cc_to_string[16] =
#define ED_URB_DEL 0x08
/* usb_ohci_ed */
struct ed
{
uint32_t hwINFO;
uint32_t hwTailP;
uint32_t hwHeadP;
uint32_t hwNextED;
struct ed {
uint32_t hwINFO;
uint32_t hwTailP;
uint32_t hwHeadP;
uint32_t hwNextED;
struct ed *ed_prev;
uint8_t int_period;
uint8_t int_branch;
uint8_t int_load;
uint8_t int_interval;
uint8_t state;
uint8_t type;
uint16_t last_iso;
struct ed *ed_rm_list;
struct ed *ed_prev;
uint8_t int_period;
uint8_t int_branch;
uint8_t int_load;
uint8_t int_interval;
uint8_t state;
uint8_t type;
uint16_t last_iso;
struct ed *ed_rm_list;
struct usb_device *usb_dev;
void *purb;
uint32_t unused[2];
struct usb_device *usb_dev;
void *purb;
uint32_t unused[2];
} __attribute__((aligned(16)));
typedef struct ed ed_t;
@@ -135,23 +134,22 @@ typedef struct ed ed_t;
#define MAXPSW 1
struct td
{
uint32_t hwINFO;
uint32_t hwCBP; /* Current Buffer Pointer */
uint32_t hwNextTD; /* Next TD Pointer */
uint32_t hwBE; /* Memory Buffer End Pointer */
struct td {
uint32_t hwINFO;
uint32_t hwCBP; /* Current Buffer Pointer */
uint32_t hwNextTD; /* Next TD Pointer */
uint32_t hwBE; /* Memory Buffer End Pointer */
uint16_t hwPSW[MAXPSW];
uint8_t unused;
uint8_t index;
struct ed *ed;
struct td *next_dl_td;
struct usb_device *usb_dev;
int transfer_len;
uint32_t data;
uint16_t hwPSW[MAXPSW];
uint8_t unused;
uint8_t index;
struct ed *ed;
struct td *next_dl_td;
struct usb_device *usb_dev;
int transfer_len;
uint32_t data;
uint32_t unused2[2];
uint32_t unused2[2];
} __attribute__((aligned(32)));
typedef struct td td_t;
@@ -164,18 +162,17 @@ typedef struct td td_t;
*/
#define NUM_INTS 32 /* part of the OHCI standard */
struct ohci_hcca
{
uint32_t int_table[NUM_INTS]; /* Interrupt ED table */
struct ohci_hcca {
uint32_t int_table[NUM_INTS]; /* Interrupt ED table */
#if defined(CONFIG_MPC5200)
uint16_t pad1; /* set to 0 on each frame_no change */
uint16_t frame_no; /* current frame number */
uint16_t pad1; /* set to 0 on each frame_no change */
uint16_t frame_no; /* current frame number */
#else
uint16_t frame_no; /* current frame number */
uint16_t pad1; /* set to 0 on each frame_no change */
uint16_t frame_no; /* current frame number */
uint16_t pad1; /* set to 0 on each frame_no change */
#endif
uint32_t done_head; /* info returned for an interrupt */
uint8_t reserved_for_hc[116];
uint32_t done_head; /* info returned for an interrupt */
uint8_t reserved_for_hc[116];
} __attribute__((aligned(256)));
/*
@@ -183,37 +180,35 @@ struct ohci_hcca
* region. This is Memory Mapped I/O. You must use the readl() and
* writel() macros defined in asm/io.h to access these!!
*/
struct ohci_regs
{
/* control and status registers */
uint32_t revision;
uint32_t control;
uint32_t cmdstatus;
uint32_t intrstatus;
uint32_t intrenable;
uint32_t intrdisable;
/* memory pointers */
uint32_t hcca;
uint32_t ed_periodcurrent;
uint32_t ed_controlhead;
uint32_t ed_controlcurrent;
uint32_t ed_bulkhead;
uint32_t ed_bulkcurrent;
uint32_t donehead;
/* frame counters */
uint32_t fminterval;
uint32_t fmremaining;
uint32_t fmnumber;
uint32_t periodicstart;
uint32_t lsthresh;
/* Root hub ports */
struct ohci_roothub_regs
{
uint32_t a;
uint32_t b;
uint32_t status;
uint32_t portstatus[USB_OHCI_MAX_ROOT_PORTS];
} roothub;
struct ohci_regs {
/* control and status registers */
uint32_t revision;
uint32_t control;
uint32_t cmdstatus;
uint32_t intrstatus;
uint32_t intrenable;
uint32_t intrdisable;
/* memory pointers */
uint32_t hcca;
uint32_t ed_periodcurrent;
uint32_t ed_controlhead;
uint32_t ed_controlcurrent;
uint32_t ed_bulkhead;
uint32_t ed_bulkcurrent;
uint32_t donehead;
/* frame counters */
uint32_t fminterval;
uint32_t fmremaining;
uint32_t fmnumber;
uint32_t periodicstart;
uint32_t lsthresh;
/* Root hub ports */
struct ohci_roothub_regs {
uint32_t a;
uint32_t b;
uint32_t status;
uint32_t portstatus[USB_OHCI_MAX_ROOT_PORTS];
} roothub;
} __attribute__((aligned(32)));
/* Some EHCI controls */
@@ -268,13 +263,12 @@ struct ohci_regs
/* Virtual Root HUB */
struct virt_root_hub
{
int devnum; /* Address of Root Hub endpoint */
void *dev; /* was urb */
void *int_addr;
int send;
int interval;
struct virt_root_hub {
int devnum; /* Address of Root Hub endpoint */
void *dev; /* was urb */
void *int_addr;
int send;
int interval;
};
/* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */
@@ -372,27 +366,26 @@ struct virt_root_hub
#define N_URB_TD 48
typedef struct
{
ed_t *ed;
uint16_t length; /* number of tds associated with this request */
uint16_t td_cnt; /* number of tds already serviced */
struct usb_device *dev;
int state;
uint32_t pipe;
void *transfer_buffer;
int transfer_buffer_length;
int interval;
int actual_length;
int finished;
td_t *td[N_URB_TD]; /* list pointer to all corresponding TDs associated with this request */
ed_t *ed;
uint16_t length; /* number of tds associated with this request */
uint16_t td_cnt; /* number of tds already serviced */
struct usb_device *dev;
int state;
uint32_t pipe;
void *transfer_buffer;
int transfer_buffer_length;
int interval;
int actual_length;
int finished;
td_t *td[N_URB_TD]; /* list pointer to all corresponding TDs associated with this request */
} urb_priv_t;
#define URB_DEL 1
#define NUM_EDS 8 /* num of preallocated endpoint descriptors */
struct ohci_device
{
ed_t ed[NUM_EDS];
int ed_cnt;
struct ohci_device {
ed_t ed[NUM_EDS];
int ed_cnt;
};
/*
@@ -402,47 +395,46 @@ struct ohci_device
* a subset of what the full implementation needs. (Linus)
*/
typedef struct ohci
{
/* ------- common part -------- */
long handle; /* PCI BIOS */
const struct pci_device_id *ent;
int usbnum;
typedef struct ohci {
/* ------- common part -------- */
long handle; /* PCI BIOS */
const struct pci_device_id *ent;
int usbnum;
/* ---- end of common part ---- */
int big_endian; /* PCI BIOS */
int controller;
struct ohci_hcca *hcca_unaligned;
struct ohci_hcca *hcca; /* hcca */
td_t *td_unaligned;
struct ohci_device *ohci_dev_unaligned;
/* this allocates EDs for all possible endpoints */
struct ohci_device *ohci_dev;
int big_endian; /* PCI BIOS */
int controller;
struct ohci_hcca *hcca_unaligned;
struct ohci_hcca *hcca; /* hcca */
td_t *td_unaligned;
struct ohci_device *ohci_dev_unaligned;
/* this allocates EDs for all possible endpoints */
struct ohci_device *ohci_dev;
int irq_enabled;
int stat_irq;
int irq;
int disabled; /* e.g. got a UE, we're hung */
int sleeping;
int irq_enabled;
int stat_irq;
int irq;
int disabled; /* e.g. got a UE, we're hung */
int sleeping;
#define OHCI_FLAGS_NEC 0x80000000
uint32_t flags; /* for HC bugs */
uint32_t flags; /* for HC bugs */
uint32_t offset;
uint32_t dma_offset;
struct ohci_regs *regs; /* OHCI controller's memory */
uint32_t offset;
uint32_t dma_offset;
struct ohci_regs *regs; /* OHCI controller's memory */
int ohci_int_load[32]; /* load of the 32 Interrupt Chains (for load balancing)*/
ed_t *ed_rm_list[2]; /* lists of all endpoints to be removed */
ed_t *ed_bulktail; /* last endpoint of bulk list */
ed_t *ed_controltail; /* last endpoint of control list */
int intrstatus;
uint32_t hc_control; /* copy of the hc control reg */
uint32_t ndp; /* copy NDP from roothub_a */
struct virt_root_hub rh;
int ohci_int_load[32]; /* load of the 32 Interrupt Chains (for load balancing)*/
ed_t *ed_rm_list[2]; /* lists of all endpoints to be removed */
ed_t *ed_bulktail; /* last endpoint of bulk list */
ed_t *ed_controltail; /* last endpoint of control list */
int intrstatus;
uint32_t hc_control; /* copy of the hc control reg */
uint32_t ndp; /* copy NDP from roothub_a */
struct virt_root_hub rh;
const char *slot_name;
const char *slot_name;
/* device which was disconnected */
struct usb_device *devgone;
/* device which was disconnected */
struct usb_device *devgone;
} ohci_t;
/* hcd */
@@ -451,6 +443,7 @@ static int ep_link(ohci_t * ohci, ed_t * ed);
static int ep_unlink(ohci_t * ohci, ed_t * ed);
static ed_t * ep_add_ed(ohci_t * ohci, struct usb_device * usb_dev, uint32_t pipe, int interval, int load);
/*-------------------------------------------------------------------------*/
/* we need more TDs than EDs */
#define NUM_TD 64
@@ -458,7 +451,7 @@ static ed_t * ep_add_ed(ohci_t * ohci, struct usb_device * usb_dev, uint32_t pip
static inline void ed_free(struct ed *ed)
{
ed->usb_dev = NULL;
ed->usb_dev = NULL;
}

3
include/part.h
View File

@@ -26,8 +26,7 @@
typedef unsigned long long uint64_t;
typedef unsigned long lbaint_t;
typedef struct block_dev_desc
{
typedef struct block_dev_desc {
int if_type; /* type of the interface */
int dev; /* device number */
unsigned char part_type; /* partition type */

26
include/pci.h
View File

@@ -21,7 +21,7 @@
* Author: Markus Fröschle
*/
#include <bas_types.h>
#include <stdint.h>
#include "util.h" /* for swpX() */
#define PCI_MEMORY_OFFSET (0x80000000)
@@ -50,7 +50,7 @@
#define PCIBAR2 0x18 /* PCI Base Address Register for Memory
Accesses to Local Address Space 0 */
#define PCIBAR3 0x1C /* PCI Base Address Register for Memory
Accesses to Local Address Space 1 */
Accesses to Local Address Space 1 */
#define PCIBAR4 0x20 /* PCI Base Address Register, reserved */
#define PCIBAR5 0x24 /* PCI Base Address Register, reserved */
#define PCICIS 0x28 /* PCI Cardbus CIS Pointer, not support*/
@@ -91,12 +91,9 @@
#define PCICSR_STEPPING (1 << 7) /* if set: stepping enabled */
#define PCICSR_SERR (1 << 8) /* if set: SERR pin enabled */
#define PCICSR_FAST_BTOB_E (1 << 9) /* if set: fast back-to-back enabled */
#define PCICSR_INT_DISABLE (1 << 10) /* if set: disable interrupts from this device */
/*
* bit definitions for PCICSR upper half (Status Register)
*/
#define PCICSR_INTERRUPT (1 << 3) /* device requested interrupt */
#define PCICSR_CAPABILITIES (1 << 4) /* if set, capabilities pointer is valid */
#define PCICSR_66MHZ (1 << 5) /* 66 MHz capable */
#define PCICSR_UDF (1 << 6) /* UDF supported */
#define PCICSR_FAST_BTOB (1 << 7) /* Fast back-to-back enabled */
@@ -194,8 +191,8 @@ typedef struct /* structure of address conversion */
#define PCI_COMMAND(i) (((i) >> 16) & 0xffff)
/* register 0x08 macros */
#define PCI_CLASS_CODE(i) ((swpl((i)) & 0xffff0000) >> 16)
#define PCI_SUBCLASS(i) ((swpl((i)) & 0xffffff00) >> 8)
#define PCI_CLASS_CODE(i) ((swpl((i)) & 0xff000000) >> 24)
#define PCI_SUBCLASS(i) ((swpl((i)) & 0x00ff0000) >> 16)
#define PCI_PROG_IF(i) ((swpl((i)) & 0x0000ff00) >> 8)
#define PCI_REVISION_ID(i) ((swpl((i)) & 0x000000ff))
@@ -227,14 +224,10 @@ typedef struct /* structure of address conversion */
extern void init_eport(void);
extern void init_xlbus_arbiter(void);
extern void init_pci(void);
extern int pci_handle2index(int32_t handle);
extern int32_t pci_find_device(uint16_t device_id, uint16_t vendor_id, int index);
extern int32_t pci_find_classcode(uint32_t classcode, int index);
extern int32_t pci_get_interrupt_cause(void);
extern int32_t pci_call_interrupt_chain(int32_t handle, int32_t data);
/*
* match bits for pci_find_classcode()
*/
@@ -250,9 +243,7 @@ extern int32_t pci_write_config_longword(int32_t handle, int offset, uint32_t va
extern int32_t pci_write_config_word(int32_t handle, int offset, uint16_t value);
extern int32_t pci_write_config_byte(int32_t handle, int offset, uint8_t value);
typedef int (*pci_interrupt_handler)(int param);
extern int32_t pci_hook_interrupt(int32_t handle, void *handler, void *parameter);
extern int32_t pci_hook_interrupt(int32_t handle, void *interrupt_handler, void *parameter);
extern int32_t pci_unhook_interrupt(int32_t handle);
extern struct pci_rd *pci_get_resource(int32_t handle);
@@ -341,13 +332,14 @@ extern int32_t wrapper_virt_to_phys(uint32_t address, PCI_CONV_ADR *pointer);
extern int32_t wrapper_phys_to_virt(uint32_t address, PCI_CONV_ADR *pointer);
#define PCI_MK_CONF_ADDR(bus, device, function) (MCF_PCI_PCICAR_E | \
((bus) << 16) | \
((device << 8) | \
(function))
((bus) << 16) | \
((device << 8) | \
(function))
#define PCI_HANDLE(bus, slot, function) (0 | ((bus & 0xff) << 10 | (slot & 0x1f) << 3 | (function & 7)))
#define PCI_BUS_FROM_HANDLE(h) (((h) & 0xff00) >> 10)
#define PCI_DEVICE_FROM_HANDLE(h) (((h) & 0xf8) >> 3)
#define PCI_FUNCTION_FROM_HANDLE(h) (((h) & 0x7))
extern void chip_errata_135(void); /* needed in ohci-hcd.c */
#endif /* _PCI_H_ */

20
include/pci_ids.h
View File

@@ -598,10 +598,8 @@
#define PCI_DEVICE_ID_NEC_VL 0x0016 /* PCI-VL Bridge */
#define PCI_DEVICE_ID_NEC_STARALPHA2 0x002c /* STAR ALPHA2 */
#define PCI_DEVICE_ID_NEC_CBUS_2 0x002d /* PCI-Cbus Bridge */
#define PCI_DEVICE_ID_NEC_USB_A 0x0031
#define PCI_DEVICE_ID_NEC_USB 0x0035 /* PCI-USB Host */
#define PCI_DEVICE_ID_NEC_USB_2 0x00e0 /* PCI-USB 2 Host */
#define PCI_DEVICE_ID_NEC_USB_3 0x00f0
#define PCI_DEVICE_ID_NEC_CBUS_3 0x003b
#define PCI_DEVICE_ID_NEC_NAPCCARD 0x003e
#define PCI_DEVICE_ID_NEC_PCX2 0x0046 /* PowerVR */
@@ -800,7 +798,7 @@
#define PCI_VENDOR_ID_ANIGMA 0x1051
#define PCI_DEVICE_ID_ANIGMA_MC145575 0x0100
#define PCI_VENDOR_ID_EFAR 0x1055
#define PCI_DEVICE_ID_EFAR_SLC90E66_1 0x9130
#define PCI_DEVICE_ID_EFAR_SLC90E66_0 0x9460
@@ -1509,7 +1507,7 @@
#define PCI_VENDOR_ID_ZIATECH 0x1138
#define PCI_DEVICE_ID_ZIATECH_5550_HC 0x5550
#define PCI_VENDOR_ID_CYCLONE 0x113c
#define PCI_DEVICE_ID_CYCLONE_SDK 0x0001
@@ -1709,8 +1707,8 @@
#define PCI_DEVICE_ID_RP8OCTA 0x0005
#define PCI_DEVICE_ID_RP8J 0x0006
#define PCI_DEVICE_ID_RP4J 0x0007
#define PCI_DEVICE_ID_RP8SNI 0x0008
#define PCI_DEVICE_ID_RP16SNI 0x0009
#define PCI_DEVICE_ID_RP8SNI 0x0008
#define PCI_DEVICE_ID_RP16SNI 0x0009
#define PCI_DEVICE_ID_RPP4 0x000A
#define PCI_DEVICE_ID_RPP8 0x000B
#define PCI_DEVICE_ID_RP8M 0x000C
@@ -1721,9 +1719,9 @@
#define PCI_DEVICE_ID_URP8INTF 0x0802
#define PCI_DEVICE_ID_URP16INTF 0x0803
#define PCI_DEVICE_ID_URP8OCTA 0x0805
#define PCI_DEVICE_ID_UPCI_RM3_8PORT 0x080C
#define PCI_DEVICE_ID_UPCI_RM3_8PORT 0x080C
#define PCI_DEVICE_ID_UPCI_RM3_4PORT 0x080D
#define PCI_DEVICE_ID_CRP16INTF 0x0903
#define PCI_DEVICE_ID_CRP16INTF 0x0903
#define PCI_VENDOR_ID_CYCLADES 0x120e
#define PCI_DEVICE_ID_CYCLOM_Y_Lo 0x0100
@@ -2145,7 +2143,7 @@
#define PCI_DEVICE_ID_RASTEL_2PORT 0x2000
#define PCI_VENDOR_ID_ZOLTRIX 0x15b0
#define PCI_DEVICE_ID_ZOLTRIX_2BD0 0x2bd0
#define PCI_DEVICE_ID_ZOLTRIX_2BD0 0x2bd0
#define PCI_VENDOR_ID_MELLANOX 0x15b3
#define PCI_DEVICE_ID_MELLANOX_TAVOR 0x5a44
@@ -2290,8 +2288,8 @@
#define PCI_DEVICE_ID_INTEL_82092AA_0 0x1221
#define PCI_DEVICE_ID_INTEL_82092AA_1 0x1222
#define PCI_DEVICE_ID_INTEL_7116 0x1223
#define PCI_DEVICE_ID_INTEL_7505_0 0x2550
#define PCI_DEVICE_ID_INTEL_7505_1 0x2552
#define PCI_DEVICE_ID_INTEL_7505_0 0x2550
#define PCI_DEVICE_ID_INTEL_7505_1 0x2552
#define PCI_DEVICE_ID_INTEL_7205_0 0x255d
#define PCI_DEVICE_ID_INTEL_82596 0x1226
#define PCI_DEVICE_ID_INTEL_82865 0x1227

2
include/queue.h
View File

@@ -8,6 +8,8 @@
#ifndef _QUEUE_H_
#define _QUEUE_H_
/********************************************************************/
/*
* Individual queue node
*/

2
include/radeonfb.h
View File

@@ -10,9 +10,7 @@
#include "i2c-algo-bit.h"
#include "util.h" /* for swpX() */
#include "wait.h"
//#include "radeon_theatre.h"
#include "radeon_reg.h"
/* Buffer are aligned on 4096 byte boundaries */

2
include/sd_card.h
View File

@@ -31,7 +31,7 @@
#define _SD_CARD_H_
#include <MCF5475.h>
#include <bas_types.h>
#include <stdint.h>
extern void sd_card_init(void);

455
include/usb.h
View File

@@ -26,6 +26,7 @@
#ifndef _USB_H_
#define _USB_H_
//#include <stdlib.h>
#include <bas_string.h>
#include "driver_mem.h"
#include "pci.h"
@@ -36,10 +37,18 @@
extern long *tab_funcs_pci;
#define in8(addr) Fast_read_mem_byte(usb_handle,addr)
#define in16r(addr) Fast_read_mem_word(usb_handle,addr)
#define in32r(addr) Fast_read_mem_longword(usb_handle,addr)
#define out8(addr,val) Write_mem_byte(usb_handle,addr,val)
#define out16r(addr,val) Write_mem_word(usb_handle,addr,val)
#define out32r(addr,val) Write_mem_longword(usb_handle,addr,val)
#define __u8 uint8_t
#define __u16 uint16_t
#define __u32 uint32_t
//#define u8 uint8_t
#define u8 uint8_t
#define u16 uint16_t
#define u32 uint32_t
#define uint8_t uint8_t
@@ -55,241 +64,232 @@ extern int sprintD(char *s, const char *fmt, ...);
#define USB_ALTSETTINGALLOC 4
#define USB_MAXALTSETTING 128 /* Hard limit */
#define USB_MAX_BUS 3
#define USB_MAX_DEVICE 16
#define USB_MAXCONFIG 8
#define USB_MAXINTERFACES 8
#define USB_MAXENDPOINTS 16
#define USB_MAXCHILDREN 8 /* This is arbitrary */
#define USB_MAX_HUB 16
#define USB_MAX_BUS 3
#define USB_MAX_DEVICE 16
#define USB_MAXCONFIG 8
#define USB_MAXINTERFACES 8
#define USB_MAXENDPOINTS 16
#define USB_MAXCHILDREN 8 /* This is arbitrary */
#define USB_MAX_HUB 16
#define USB_CNTL_TIMEOUT 100 /* 100 ms timeout */
#define USB_BUFSIZ 512
#define USB_CNTL_TIMEOUT 100 /* 100ms timeout */
/* String descriptor */
struct usb_string_descriptor
{
uint8_t bLength;
uint8_t bDescriptorType;
uint16_t wData[1];
struct usb_string_descriptor {
uint8_t bLength;
uint8_t bDescriptorType;
uint16_t wData[1];
} __attribute__ ((packed));
/* device request (setup) */
struct devrequest
{
uint8_t requesttype;
uint8_t request;
uint16_t value;
uint16_t index;
uint16_t length;
struct devrequest {
uint8_t requesttype;
uint8_t request;
uint16_t value;
uint16_t index;
uint16_t length;
} __attribute__ ((packed));
/* All standard descriptors have these 2 fields in common */
struct usb_descriptor_header
{
uint8_t bLength;
uint8_t bDescriptorType;
struct usb_descriptor_header {
uint8_t bLength;
uint8_t bDescriptorType;
} __attribute__ ((packed));
/* Device descriptor */
struct usb_device_descriptor
{
uint8_t bLength;
uint8_t bDescriptorType;
uint16_t bcdUSB;
uint8_t bDeviceClass;
uint8_t bDeviceSubClass;
uint8_t bDeviceProtocol;
uint8_t bMaxPacketSize0;
uint16_t idVendor;
uint16_t idProduct;
uint16_t bcdDevice;
uint8_t iManufacturer;
uint8_t iProduct;
uint8_t iSerialNumber;
uint8_t bNumConfigurations;
struct usb_device_descriptor {
uint8_t bLength;
uint8_t bDescriptorType;
uint16_t bcdUSB;
uint8_t bDeviceClass;
uint8_t bDeviceSubClass;
uint8_t bDeviceProtocol;
uint8_t bMaxPacketSize0;
uint16_t idVendor;
uint16_t idProduct;
uint16_t bcdDevice;
uint8_t iManufacturer;
uint8_t iProduct;
uint8_t iSerialNumber;
uint8_t bNumConfigurations;
} __attribute__ ((packed));
/* Endpoint descriptor */
struct usb_endpoint_descriptor
{
uint8_t bLength;
uint8_t bDescriptorType;
uint8_t bEndpointAddress;
uint8_t bmAttributes;
uint16_t wMaxPacketSize;
uint8_t bInterval;
uint8_t bRefresh;
uint8_t bSynchAddress;
struct usb_endpoint_descriptor {
uint8_t bLength;
uint8_t bDescriptorType;
uint8_t bEndpointAddress;
uint8_t bmAttributes;
uint16_t wMaxPacketSize;
uint8_t bInterval;
uint8_t bRefresh;
uint8_t bSynchAddress;
} __attribute__ ((packed)) __attribute__ ((aligned(2)));
/* Interface descriptor */
struct usb_interface_descriptor
{
uint8_t bLength;
uint8_t bDescriptorType;
uint8_t bInterfaceNumber;
uint8_t bAlternateSetting;
uint8_t bNumEndpoints;
uint8_t bInterfaceClass;
uint8_t bInterfaceSubClass;
uint8_t bInterfaceProtocol;
uint8_t iInterface;
struct usb_interface_descriptor {
uint8_t bLength;
uint8_t bDescriptorType;
uint8_t bInterfaceNumber;
uint8_t bAlternateSetting;
uint8_t bNumEndpoints;
uint8_t bInterfaceClass;
uint8_t bInterfaceSubClass;
uint8_t bInterfaceProtocol;
uint8_t iInterface;
uint8_t no_of_ep;
uint8_t num_altsetting;
uint8_t act_altsetting;
uint8_t no_of_ep;
uint8_t num_altsetting;
uint8_t act_altsetting;
struct usb_endpoint_descriptor ep_desc[USB_MAXENDPOINTS];
struct usb_endpoint_descriptor ep_desc[USB_MAXENDPOINTS];
} __attribute__ ((packed));
/* Configuration descriptor information.. */
struct usb_config_descriptor
{
uint8_t bLength;
uint8_t bDescriptorType;
uint16_t wTotalLength;
uint8_t bNumInterfaces;
uint8_t bConfigurationValue;
uint8_t iConfiguration;
uint8_t bmAttributes;
uint8_t MaxPower;
struct usb_config_descriptor {
uint8_t bLength;
uint8_t bDescriptorType;
uint16_t wTotalLength;
uint8_t bNumInterfaces;
uint8_t bConfigurationValue;
uint8_t iConfiguration;
uint8_t bmAttributes;
uint8_t MaxPower;
uint8_t no_of_if; /* number of interfaces */
struct usb_interface_descriptor if_desc[USB_MAXINTERFACES];
uint8_t no_of_if; /* number of interfaces */
struct usb_interface_descriptor if_desc[USB_MAXINTERFACES];
} __attribute__ ((packed));
enum
{
/* Maximum packet size; encoded as 0,1,2,3 = 8,16,32,64 */
PACKET_SIZE_8 = 0,
PACKET_SIZE_16 = 1,
PACKET_SIZE_32 = 2,
PACKET_SIZE_64 = 3,
enum {
/* Maximum packet size; encoded as 0,1,2,3 = 8,16,32,64 */
PACKET_SIZE_8 = 0,
PACKET_SIZE_16 = 1,
PACKET_SIZE_32 = 2,
PACKET_SIZE_64 = 3,
};
struct usb_device
{
int devnum; /* Device number on USB bus */
int speed; /* full/low/high */
char mf[32]; /* manufacturer */
char prod[32]; /* product */
char serial[32]; /* serial number */
struct usb_device {
int devnum; /* Device number on USB bus */
int speed; /* full/low/high */
char mf[32]; /* manufacturer */
char prod[32]; /* product */
char serial[32]; /* serial number */
/* Maximum packet size; one of: PACKET_SIZE_* */
int maxpacketsize;
/* Maximum packet size; one of: PACKET_SIZE_* */
int maxpacketsize;
/* one bit for each endpoint ([0] = IN, [1] = OUT) */
unsigned int toggle[2];
/* endpoint halts; one bit per endpoint # & direction;
* [0] = IN, [1] = OUT
*/
unsigned int halted[2];
int epmaxpacketin[16]; /* INput endpoint specific maximums */
int epmaxpacketout[16]; /* OUTput endpoint specific maximums */
/* one bit for each endpoint ([0] = IN, [1] = OUT) */
unsigned int toggle[2];
int configno; /* selected config number */
struct usb_device_descriptor descriptor; /* Device Descriptor */
struct usb_config_descriptor config; /* config descriptor */
/* endpoint halts; one bit per endpoint # & direction;
* [0] = IN, [1] = OUT
*/
unsigned int halted[2];
int epmaxpacketin[16]; /* INput endpoint specific maximums */
int epmaxpacketout[16]; /* OUTput endpoint specific maximums */
int have_langid; /* whether string_langid is valid yet */
int string_langid; /* language ID for strings */
int (*irq_handle)(struct usb_device *dev);
uint32_t irq_status;
int irq_act_len; /* transfered bytes */
void *privptr;
/*
* Child devices - if this is a hub device
* Each instance needs its own set of data structures.
*/
uint32_t status;
int act_len; /* transfered bytes */
int maxchild; /* Number of ports if hub */
int portnr;
struct usb_device *parent;
struct usb_device *children[USB_MAXCHILDREN];
void *priv_hcd;
int (*deregister)(struct usb_device *dev);
int configno; /* selected config number */
struct usb_device_descriptor descriptor; /* Device Descriptor */
struct usb_config_descriptor config; /* config descriptor */
int have_langid; /* whether string_langid is valid yet */
int string_langid; /* language ID for strings */
int (*irq_handle)(struct usb_device *dev);
uint32_t irq_status;
int irq_act_len; /* transfered bytes */
void *privptr;
/*
* Child devices - if this is a hub device
* Each instance needs its own set of data structures.
*/
uint32_t status;
int act_len; /* transfered bytes */
int maxchild; /* Number of ports if hub */
int portnr;
struct usb_device *parent;
struct usb_device *children[USB_MAXCHILDREN];
void *priv_hcd;
int (*deregister)(struct usb_device *dev);
struct usb_hub_device *hub;
int usbnum;
struct usb_hub_device *hub;
int usbnum;
};
typedef struct
{
long ident;
union
{
long l;
short i[2];
char c[4];
} v;
long ident;
union
{
long l;
short i[2];
char c[4];
} v;
} USB_COOKIE;
/*
/**********************************************************************
* this is how the lowlevel part communicate with the outer world
*/
extern int ohci_usb_lowlevel_init(int32_t handle, const struct pci_device_id *ent, void **priv);
extern int ohci_usb_lowlevel_stop(void *priv);
extern int ohci_submit_bulk_msg(struct usb_device *dev, uint32_t pipe, void *buffer, int transfer_len);
extern int ohci_submit_control_msg(struct usb_device *dev, uint32_t pipe, void *buffer, int transfer_len, struct devrequest *setup);
extern int ohci_submit_int_msg(struct usb_device *dev, uint32_t pipe, void *buffer, int transfer_len, int interval);
extern void ohci_usb_enable_interrupt(int enable);
int ohci_usb_lowlevel_init(int32_t handle, const struct pci_device_id *ent, void **priv);
int ohci_usb_lowlevel_stop(void *priv);
int ohci_submit_bulk_msg(struct usb_device *dev, uint32_t pipe, void *buffer, int transfer_len);
int ohci_submit_control_msg(struct usb_device *dev, uint32_t pipe, void *buffer, int transfer_len, struct devrequest *setup);
int ohci_submit_int_msg(struct usb_device *dev, uint32_t pipe, void *buffer, int transfer_len, int interval);
void ohci_usb_enable_interrupt(int enable);
extern int ehci_usb_lowlevel_init(long handle, const struct pci_device_id *ent, void **priv);
extern int ehci_usb_lowlevel_stop(void *priv);
extern int ehci_submit_bulk_msg(struct usb_device *dev, uint32_t pipe, void *buffer, int transfer_len);
extern int ehci_submit_control_msg(struct usb_device *dev, uint32_t pipe, void *buffer, int transfer_len, struct devrequest *setup);
extern int ehci_submit_int_msg(struct usb_device *dev, uint32_t pipe, void *buffer, int transfer_len, int interval);
extern void ehci_usb_enable_interrupt(int enable);
int ehci_usb_lowlevel_init(long handle, const struct pci_device_id *ent, void **priv);
int ehci_usb_lowlevel_stop(void *priv);
int ehci_submit_bulk_msg(struct usb_device *dev, uint32_t pipe, void *buffer, int transfer_len);
int ehci_submit_control_msg(struct usb_device *dev, uint32_t pipe, void *buffer, int transfer_len, struct devrequest *setup);
int ehci_submit_int_msg(struct usb_device *dev, uint32_t pipe, void *buffer, int transfer_len, int interval);
void ehci_usb_enable_interrupt(int enable);
extern void usb_enable_interrupt(int enable);
extern int usb_new_device(struct usb_device *dev);
extern struct usb_device *usb_alloc_new_device(int bus_index, void *priv);
extern void usb_disconnect(struct usb_device **pdev);
void usb_enable_interrupt(int enable);
#define USB_MAX_STOR_DEV 5
block_dev_desc_t *usb_stor_get_dev(int index);
int usb_stor_scan(void);
int usb_stor_info(void);
int usb_stor_register(struct usb_device *dev);
int usb_stor_deregister(struct usb_device *dev);
extern block_dev_desc_t *usb_stor_get_dev(int index);
extern int usb_stor_scan(void);
extern int usb_stor_info(void);
extern int usb_stor_register(struct usb_device *dev);
extern int usb_stor_deregister(struct usb_device *dev);
int drv_usb_kbd_init(void);
int usb_kbd_register(struct usb_device *dev);
int usb_kbd_deregister(struct usb_device *dev);
extern int drv_usb_kbd_init(void);
extern int usb_kbd_register(struct usb_device *dev);
extern int usb_kbd_deregister(struct usb_device *dev);
int drv_usb_mouse_init(void);
int usb_mouse_register(struct usb_device *dev);
int usb_mouse_deregister(struct usb_device *dev);
extern int drv_usb_mouse_init(void);
extern int usb_mouse_register(struct usb_device *dev);
extern int usb_mouse_deregister(struct usb_device *dev);
extern char usb_error_str[256];
/* memory */
void *usb_malloc(long amount);
int usb_free(void *addr);
int usb_mem_init(void);
void usb_mem_stop(void);
/* routines */
extern int usb_init(int32_t handle, const struct pci_device_id *ent); /* initialize the USB Controller */
extern int usb_stop(void); /* stop the USB Controller */
USB_COOKIE *usb_get_cookie(long id);
void usb_error_msg(const char *const fmt, ... );
int usb_init(int32_t handle, const struct pci_device_id *ent); /* initialize the USB Controller */
int usb_stop(void); /* stop the USB Controller */
extern int usb_set_protocol(struct usb_device *dev, int ifnum, int protocol);
extern int usb_set_idle(struct usb_device *dev, int ifnum, int duration, int report_id);
extern struct usb_device *usb_get_dev_index(int index, int bus);
extern int usb_control_msg(struct usb_device *dev, unsigned int pipe, uint8_t request, uint8_t requesttype,
uint16_t value, uint16_t index, void *data, uint16_t size, int timeout);
extern int usb_bulk_msg(struct usb_device *dev, unsigned int pipe, void *data, int len, int *actual_length, int timeout);
extern int usb_submit_int_msg(struct usb_device *dev, uint32_t pipe, void *buffer, int transfer_len, int interval);
extern void usb_disable_asynch(int disable);
extern int usb_maxpacket(struct usb_device *dev, uint32_t pipe);
extern int usb_get_configuration_no(struct usb_device *dev, uint8_t *buffer, int cfgno);
extern int usb_get_report(struct usb_device *dev, int ifnum, uint8_t type, uint8_t id, void *buf, int size);
extern int usb_get_class_descriptor(struct usb_device *dev, int ifnum, uint8_t type, uint8_t id, void *buf, int size);
extern int usb_clear_halt(struct usb_device *dev, int pipe);
extern int usb_string(struct usb_device *dev, int index, char *buf, size_t size);
extern int usb_set_interface(struct usb_device *dev, int interface, int alternate);
int usb_set_protocol(struct usb_device *dev, int ifnum, int protocol);
int usb_set_idle(struct usb_device *dev, int ifnum, int duration, int report_id);
struct usb_device *usb_get_dev_index(int index, int bus);
int usb_control_msg(struct usb_device *dev, unsigned int pipe, uint8_t request, uint8_t requesttype, uint16_t value,
uint16_t index, void *data, uint16_t size, int timeout);
int usb_bulk_msg(struct usb_device *dev, unsigned int pipe, void *data, int len, int *actual_length, int timeout);
int usb_submit_int_msg(struct usb_device *dev, uint32_t pipe, void *buffer, int transfer_len, int interval);
void usb_disable_asynch(int disable);
int usb_maxpacket(struct usb_device *dev, uint32_t pipe);
void wait_ms(uint32_t ms);
int usb_get_configuration_no(struct usb_device *dev, uint8_t *buffer, int cfgno);
int usb_get_report(struct usb_device *dev, int ifnum, uint8_t type, uint8_t id, void *buf, int size);
int usb_get_class_descriptor(struct usb_device *dev, int ifnum, uint8_t type, uint8_t id, void *buf, int size);
int usb_clear_halt(struct usb_device *dev, int pipe);
int usb_string(struct usb_device *dev, int index, char *buf, size_t size);
int usb_set_interface(struct usb_device *dev, int interface, int alternate);
/*
* Calling this entity a "pipe" is glorifying it. A USB pipe
@@ -325,45 +325,44 @@ extern int usb_set_interface(struct usb_device *dev, int interface, int alternat
* specification, so that much of the uhci driver can just mask the bits
* appropriately.
*/
/* Create various pipes... */
#define create_pipe(dev, endpoint) \
(((dev)->devnum << 8) | (endpoint << 15) | \
((dev)->speed << 26) | (dev)->maxpacketsize)
#define create_pipe(dev,endpoint) \
(((dev)->devnum << 8) | (endpoint << 15) | \
((dev)->speed << 26) | (dev)->maxpacketsize)
#define default_pipe(dev) ((dev)->speed << 26)
#define usb_sndctrlpipe(dev, endpoint) ((PIPE_CONTROL << 30) | \
create_pipe(dev, endpoint))
create_pipe(dev, endpoint))
#define usb_rcvctrlpipe(dev, endpoint) ((PIPE_CONTROL << 30) | \
create_pipe(dev, endpoint) | \
USB_DIR_IN)
create_pipe(dev, endpoint) | \
USB_DIR_IN)
#define usb_sndisocpipe(dev, endpoint) ((PIPE_ISOCHRONOUS << 30) | \
create_pipe(dev, endpoint))
create_pipe(dev, endpoint))
#define usb_rcvisocpipe(dev, endpoint) ((PIPE_ISOCHRONOUS << 30) | \
create_pipe(dev, endpoint) | \
USB_DIR_IN)
create_pipe(dev, endpoint) | \
USB_DIR_IN)
#define usb_sndbulkpipe(dev, endpoint) ((PIPE_BULK << 30) | \
create_pipe(dev, endpoint))
create_pipe(dev, endpoint))
#define usb_rcvbulkpipe(dev, endpoint) ((PIPE_BULK << 30) | \
create_pipe(dev, endpoint) | \
USB_DIR_IN)
create_pipe(dev, endpoint) | \
USB_DIR_IN)
#define usb_sndintpipe(dev, endpoint) ((PIPE_INTERRUPT << 30) | \
create_pipe(dev, endpoint))
create_pipe(dev, endpoint))
#define usb_rcvintpipe(dev, endpoint) ((PIPE_INTERRUPT << 30) | \
create_pipe(dev, endpoint) | \
USB_DIR_IN)
create_pipe(dev, endpoint) | \
USB_DIR_IN)
#define usb_snddefctrl(dev) ((PIPE_CONTROL << 30) | \
default_pipe(dev))
default_pipe(dev))
#define usb_rcvdefctrl(dev) ((PIPE_CONTROL << 30) | \
default_pipe(dev) | \
USB_DIR_IN)
default_pipe(dev) | \
USB_DIR_IN)
/* The D0/D1 toggle bits */
#define usb_gettoggle(dev, ep, out) (((dev)->toggle[out] >> ep) & 1)
#define usb_dotoggle(dev, ep, out) ((dev)->toggle[out] ^= (1 << ep))
#define usb_settoggle(dev, ep, out, bit) ((dev)->toggle[out] = \
((dev)->toggle[out] & \
~(1 << ep)) | ((bit) << ep))
((dev)->toggle[out] & \
~(1 << ep)) | ((bit) << ep))
/* Endpoint halt control/status */
#define usb_endpoint_out(ep_dir) (((ep_dir >> 7) & 1) ^ 1)
@@ -372,7 +371,7 @@ extern int usb_set_interface(struct usb_device *dev, int interface, int alternat
#define usb_endpoint_halted(dev, ep, out) ((dev)->halted[out] & (1 << (ep)))
#define usb_packetid(pipe) (((pipe) & USB_DIR_IN) ? USB_PID_IN : \
USB_PID_OUT)
USB_PID_OUT)
#define usb_pipeout(pipe) ((((pipe) >> 7) & 1) ^ 1)
#define usb_pipein(pipe) (((pipe) >> 7) & 1)
@@ -392,39 +391,35 @@ extern int usb_set_interface(struct usb_device *dev, int interface, int alternat
/*************************************************************************
* Hub Stuff
*/
struct usb_port_status
{
uint16_t wPortStatus;
uint16_t wPortChange;
struct usb_port_status {
uint16_t wPortStatus;
uint16_t wPortChange;
} __attribute__ ((packed));
struct usb_hub_status
{
uint16_t wHubStatus;
uint16_t wHubChange;
struct usb_hub_status {
uint16_t wHubStatus;
uint16_t wHubChange;
} __attribute__ ((packed));
/* Hub descriptor */
struct usb_hub_descriptor
{
uint8_t bLength;
uint8_t bDescriptorType;
uint8_t bNbrPorts;
uint16_t wHubCharacteristics;
uint8_t bPwrOn2PwrGood;
uint8_t bHubContrCurrent;
uint8_t DeviceRemovable[(USB_MAXCHILDREN+1+7)/8];
uint8_t PortPowerCtrlMask[(USB_MAXCHILDREN+1+7)/8];
/* DeviceRemovable and PortPwrCtrlMask want to be variable-length
bitmaps that hold max 255 entries. (bit0 is ignored) */
struct usb_hub_descriptor {
uint8_t bLength;
uint8_t bDescriptorType;
uint8_t bNbrPorts;
uint16_t wHubCharacteristics;
uint8_t bPwrOn2PwrGood;
uint8_t bHubContrCurrent;
uint8_t DeviceRemovable[(USB_MAXCHILDREN+1+7)/8];
uint8_t PortPowerCtrlMask[(USB_MAXCHILDREN+1+7)/8];
/* DeviceRemovable and PortPwrCtrlMask want to be variable-length
bitmaps that hold max 255 entries. (bit0 is ignored) */
} __attribute__ ((packed));
struct usb_hub_device
{
struct usb_device *pusb_dev;
struct usb_hub_descriptor desc;
struct usb_hub_device {
struct usb_device *pusb_dev;
struct usb_hub_descriptor desc;
};
#endif /*_USB_H_ */

10
include/usb_hub.h
View File

@@ -1,10 +0,0 @@
#ifndef USB_HUB_H
#define USB_HUB_H
extern int bus_index;
extern void usb_hub_reset(int bus_index);
extern int usb_hub_probe(struct usb_device *dev, int ifnum);
extern int hub_port_reset(struct usb_device *dev, int port, unsigned short *portstat);
#endif // USB_HUB_H

32
include/util.h
View File

@@ -25,7 +25,7 @@
#ifndef UTIL_H_
#define UTIL_H_
#include <bas_types.h>
#include <stdint.h>
#define NOP() __asm__ __volatile__("nop\n\t" : : : "memory")
@@ -59,7 +59,7 @@ static inline uint32_t swpl(uint32_t l)
register uint32_t result asm("d0");
__asm__ __volatile__
(
(
"lea %[input],a0\n\t" \
"mvz.b 3(a0),%[output]\n\t" \
"lsl.l #8,%[output]\n\t" \
@@ -74,7 +74,7 @@ static inline uint32_t swpl(uint32_t l)
);
return result;
}
/*
* WORD swpw2(ULONG val);
@@ -85,17 +85,17 @@ static inline uint32_t swpl(uint32_t l)
#define swpw2(a) \
__extension__ \
({unsigned long _tmp; \
__asm__ __volatile__ \
("move.b (%1),%0\n\t" \
"move.b 1(%1),(%1)\n\t" \
"move.b %0,1(%1)\n\t" \
"move.b 2(%1),%0\n\t" \
"move.b 3(%1),2(%1)\n\t" \
"move.b %0,3(%1)" \
: "=d"(_tmp) /* outputs */ \
: "a"(&a) /* inputs */ \
: "cc", "memory" /* clobbered */ \
); \
__asm__ __volatile__ \
("move.b (%1),%0\n\t" \
"move.b 1(%1),(%1)\n\t" \
"move.b %0,1(%1)\n\t" \
"move.b 2(%1),%0\n\t" \
"move.b 3(%1),2(%1)\n\t" \
"move.b %0,3(%1)" \
: "=d"(_tmp) /* outputs */ \
: "a"(&a) /* inputs */ \
: "cc", "memory" /* clobbered */ \
); \
})
/*
@@ -144,10 +144,10 @@ __extension__ \
#define regsafe_call(addr) \
__extension__ \
({__asm__ volatile ("lea -60(sp),sp\n\t" \
"movem.l d0-d7/a0-a6,(sp)"); \
"movem.l d0-d7/a0-a6,(sp)"); \
((void (*) (void)) addr)(); \
__asm__ volatile ("movem.l (sp),d0-d7/a0-a6\n\t" \
"lea 60(sp),sp"); \
"lea 60(sp),sp"); \
})

2
include/version.h
View File

@@ -29,7 +29,7 @@
*/
#define MAJOR_VERSION 0
#define MINOR_VERSION 87
#define MINOR_VERSION 86
#endif /* VERSION_H_ */

4
include/video.h
View File

@@ -1,7 +1,9 @@
#ifndef _VIDEO_H_
#define _VIDEO_H_
#include <bas_types.h>
#include <stddef.h>
#include <stdint.h>
#include <stdbool.h>
#include "bas_printf.h"
extern void video_init(void);

7
include/wait.h
View File

@@ -44,13 +44,6 @@
typedef bool (*checker_func)(void);
extern void wait(uint32_t);
extern void wait_us(uint32_t); /* this is just an alias to the above */
inline static void udelay(long us)
{
wait((uint32_t) us);
}
extern bool waitfor(uint32_t us, checker_func condition);
extern uint32_t get_timer(void);
extern void wait_ms(uint32_t ms);

4
include/x86debug.h
View File

@@ -37,7 +37,7 @@
****************************************************************************/
/* $XFree86: xc/extras/x86emu/src/x86emu/x86emu/debug.h,v 1.4 2000/11/21 23:10:27 tsi Exp $ */
#include <bas_types.h>
#include <stdint.h>
#include "bas_printf.h"
/*
@@ -135,7 +135,7 @@
#define SAVE_IP_CS(x,y) \
if (DEBUG_DECODE() | DEBUG_TRACECALL() | DEBUG_BREAK() \
| DEBUG_IO_TRACE() | DEBUG_SAVE_IP_CS()) { \
| DEBUG_IO_TRACE() | DEBUG_SAVE_IP_CS()) { \
M.x86.saved_cs = x; \
M.x86.saved_ip = y; \
}

2
include/xhdi_sd.h
View File

@@ -85,7 +85,7 @@ typedef struct _BPB
/* a riddle: how do you typedef a function pointer to a function that returns its own type? ;) */
typedef void* (*xhdi_call_fun)(int xhdi_fun, ...);
extern uint32_t xhdi_call(uint16_t *stack);
extern unsigned long xhdi_call(uint16_t *stack);
extern xhdi_call_fun xhdi_sd_install(xhdi_call_fun old_vector) __attribute__((__interrupt__));

416
kbd/ikbd.c
View File

@@ -18,7 +18,7 @@
*/
#include <bas_types.h>
#include <stdint.h>
#include "bas_printf.h"
#include "bas_string.h"
@@ -42,298 +42,298 @@ static unsigned char wptr = 0, rptr = 0;
// structure to keep track of ikbd state
static struct
{
unsigned char cmd;
unsigned char state;
unsigned char expect;
unsigned char cmd;
unsigned char state;
unsigned char expect;
// joystick state
unsigned char joystick[2];
// joystick state
unsigned char joystick[2];
// mouse state
unsigned short mouse_pos_x, mouse_pos_y;
unsigned char mouse_buttons;
// mouse state
unsigned short mouse_pos_x, mouse_pos_y;
unsigned char mouse_buttons;
} ikbd;
// #define IKBD_DEBUG
void ikbd_init()
{
// reset ikbd state
memset(&ikbd, 0, sizeof(ikbd));
ikbd.state = IKBD_DEFAULT;
// reset ikbd state
memset(&ikbd, 0, sizeof(ikbd));
ikbd.state = IKBD_DEFAULT;
}
static void enqueue(unsigned char b)
{
if (((wptr + 1)&(QUEUE_LEN-1)) == rptr)
{
xprintf("IKBD: !!!!!!! tx queue overflow !!!!!!!!!\n");
return;
}
if (((wptr + 1)&(QUEUE_LEN-1)) == rptr)
{
xprintf("IKBD: !!!!!!! tx queue overflow !!!!!!!!!\n");
return;
}
tx_queue[wptr] = b;
wptr = (wptr + 1) & (QUEUE_LEN - 1);
tx_queue[wptr] = b;
wptr = (wptr + 1) & (QUEUE_LEN - 1);
}
// convert internal joystick format into atari ikbd format
static unsigned char joystick_map2ikbd(unsigned in)
{
unsigned char out = 0;
unsigned char out = 0;
if (in & JOY_UP) out |= 0x01;
if (in & JOY_DOWN) out |= 0x02;
if (in & JOY_LEFT) out |= 0x04;
if (in & JOY_RIGHT) out |= 0x08;
if (in & JOY_BTN1) out |= 0x80;
if (in & JOY_UP) out |= 0x01;
if (in & JOY_DOWN) out |= 0x02;
if (in & JOY_LEFT) out |= 0x04;
if (in & JOY_RIGHT) out |= 0x08;
if (in & JOY_BTN1) out |= 0x80;
return out;
return out;
}
// process inout from atari core into ikbd
void ikbd_handle_input(unsigned char cmd)
{
// expecting a second byte for command
if (ikbd.expect)
{
ikbd.expect--;
// expecting a second byte for command
if (ikbd.expect)
{
ikbd.expect--;
// last byte of command received
if (!ikbd.expect)
{
switch(ikbd.cmd)
{
case 0x07: // set mouse button action
xprintf("IKBD: mouse button action = %x\n", cmd);
// last byte of command received
if (!ikbd.expect)
{
switch(ikbd.cmd)
{
case 0x07: // set mouse button action
xprintf("IKBD: mouse button action = %x\n", cmd);
// bit 2: Mouse buttons act like keys (LEFT=0x74 & RIGHT=0x75)
if(cmd & 0x04) ikbd.state |= IKBD_STATE_MOUSE_BUTTON_AS_KEY;
else ikbd.state &= ~IKBD_STATE_MOUSE_BUTTON_AS_KEY;
// bit 2: Mouse buttons act like keys (LEFT=0x74 & RIGHT=0x75)
if(cmd & 0x04) ikbd.state |= IKBD_STATE_MOUSE_BUTTON_AS_KEY;
else ikbd.state &= ~IKBD_STATE_MOUSE_BUTTON_AS_KEY;
break;
break;
case 0x80: // ibkd reset
// reply "everything is ok"
enqueue(0xf0);
break;
case 0x80: // ibkd reset
// reply "everything is ok"
enqueue(0xf0);
break;
default:
break;
}
}
default:
break;
}
}
return;
}
return;
}
ikbd.cmd = cmd;
ikbd.cmd = cmd;
switch(cmd)
{
case 0x07:
xprintf("IKBD: Set mouse button action");
ikbd.expect = 1;
break;
switch(cmd)
{
case 0x07:
xprintf("IKBD: Set mouse button action");
ikbd.expect = 1;
break;
case 0x08:
xprintf("IKBD: Set relative mouse positioning");
ikbd.state &= ~IKBD_STATE_MOUSE_DISABLED;
ikbd.state &= ~IKBD_STATE_MOUSE_ABSOLUTE;
break;
case 0x08:
xprintf("IKBD: Set relative mouse positioning");
ikbd.state &= ~IKBD_STATE_MOUSE_DISABLED;
ikbd.state &= ~IKBD_STATE_MOUSE_ABSOLUTE;
break;
case 0x09:
xprintf("IKBD: Set absolute mouse positioning");
ikbd.state &= ~IKBD_STATE_MOUSE_DISABLED;
ikbd.state |= IKBD_STATE_MOUSE_ABSOLUTE;
ikbd.expect = 4;
break;
case 0x09:
xprintf("IKBD: Set absolute mouse positioning");
ikbd.state &= ~IKBD_STATE_MOUSE_DISABLED;
ikbd.state |= IKBD_STATE_MOUSE_ABSOLUTE;
ikbd.expect = 4;
break;
case 0x0b:
xprintf("IKBD: Set Mouse threshold");
ikbd.expect = 2;
break;
case 0x0b:
xprintf("IKBD: Set Mouse threshold");
ikbd.expect = 2;
break;
case 0x0f:
xprintf("IKBD: Set Y at bottom");
ikbd.state |= IKBD_STATE_MOUSE_Y_BOTTOM;
break;
case 0x0f:
xprintf("IKBD: Set Y at bottom");
ikbd.state |= IKBD_STATE_MOUSE_Y_BOTTOM;
break;
case 0x10:
xprintf("IKBD: Set Y at top");
ikbd.state &= ~IKBD_STATE_MOUSE_Y_BOTTOM;
break;
case 0x10:
xprintf("IKBD: Set Y at top");
ikbd.state &= ~IKBD_STATE_MOUSE_Y_BOTTOM;
break;
case 0x12:
xprintf("IKBD: Disable mouse");
ikbd.state |= IKBD_STATE_MOUSE_DISABLED;
break;
case 0x12:
xprintf("IKBD: Disable mouse");
ikbd.state |= IKBD_STATE_MOUSE_DISABLED;
break;
case 0x14:
xprintf("IKBD: Set Joystick event reporting");
ikbd.state |= IKBD_STATE_JOYSTICK_EVENT_REPORTING;
break;
case 0x14:
xprintf("IKBD: Set Joystick event reporting");
ikbd.state |= IKBD_STATE_JOYSTICK_EVENT_REPORTING;
break;
case 0x15:
xprintf("IKBD: Set Joystick interrogation mode");
ikbd.state &= ~IKBD_STATE_JOYSTICK_EVENT_REPORTING;
break;
case 0x15:
xprintf("IKBD: Set Joystick interrogation mode");
ikbd.state &= ~IKBD_STATE_JOYSTICK_EVENT_REPORTING;
break;
case 0x16: // interrogate joystick
// send reply
enqueue(0xfd);
enqueue(joystick_map2ikbd(ikbd.joystick[0]));
enqueue(joystick_map2ikbd(ikbd.joystick[1]));
break;
case 0x16: // interrogate joystick
// send reply
enqueue(0xfd);
enqueue(joystick_map2ikbd(ikbd.joystick[0]));
enqueue(joystick_map2ikbd(ikbd.joystick[1]));
break;
case 0x1a:
xprintf("IKBD: Disable joysticks");
ikbd.state &= ~IKBD_STATE_JOYSTICK_EVENT_REPORTING;
break;
case 0x1a:
xprintf("IKBD: Disable joysticks");
ikbd.state &= ~IKBD_STATE_JOYSTICK_EVENT_REPORTING;
break;
case 0x1c:
xprintf("IKBD: Interrogate time of day");
case 0x1c:
xprintf("IKBD: Interrogate time of day");
enqueue(0xfc);
enqueue(0x13); // year bcd
enqueue(0x03); // month bcd
enqueue(0x07); // day bcd
enqueue(0x20); // hour bcd
enqueue(0x58); // minute bcd
enqueue(0x00); // second bcd
break;
enqueue(0xfc);
enqueue(0x13); // year bcd
enqueue(0x03); // month bcd
enqueue(0x07); // day bcd
enqueue(0x20); // hour bcd
enqueue(0x58); // minute bcd
enqueue(0x00); // second bcd
break;
case 0x80:
xprintf("IKBD: Reset");
ikbd.expect = 1;
ikbd.state = IKBD_DEFAULT;
break;
case 0x80:
xprintf("IKBD: Reset");
ikbd.expect = 1;
ikbd.state = IKBD_DEFAULT;
break;
default:
xprintf("IKBD: unknown command: %x\n", cmd);
break;
}
default:
xprintf("IKBD: unknown command: %x\n", cmd);
break;
}
}
void ikbd_poll(void) {
static int mtimer = 0;
if (CheckTimer(mtimer))
{
mtimer = GetTimer(10);
static int mtimer = 0;
if (CheckTimer(mtimer))
{
mtimer = GetTimer(10);
// check for incoming ikbd data
EnableIO();
SPI(UIO_IKBD_IN);
// check for incoming ikbd data
EnableIO();
SPI(UIO_IKBD_IN);
while(SPI(0))
ikbd_handle_input(SPI(0));
while(SPI(0))
ikbd_handle_input(SPI(0));
DisableIO();
}
DisableIO();
}
// send data from queue if present
if(rptr == wptr) return;
// send data from queue if present
if(rptr == wptr) return;
// transmit data from queue
EnableIO();
SPI(UIO_IKBD_OUT);
SPI(tx_queue[rptr]);
DisableIO();
// transmit data from queue
EnableIO();
SPI(UIO_IKBD_OUT);
SPI(tx_queue[rptr]);
DisableIO();
rptr = (rptr + 1) & (QUEUE_LEN - 1);
rptr = (rptr + 1) & (QUEUE_LEN - 1);
}
void ikbd_joystick(unsigned char joystick, unsigned char map)
{
// todo: suppress events for joystick 0 as long as mouse
// is enabled?
// todo: suppress events for joystick 0 as long as mouse
// is enabled?
if (ikbd.state & IKBD_STATE_JOYSTICK_EVENT_REPORTING)
{
if (ikbd.state & IKBD_STATE_JOYSTICK_EVENT_REPORTING)
{
#ifdef IKBD_DEBUG
xprintf("IKBD: joy %d %x\n", joystick, map);
xprintf("IKBD: joy %d %x\n", joystick, map);
#endif
// only report joystick data for joystick 0 if the mouse is disabled
if ((ikbd.state & IKBD_STATE_MOUSE_DISABLED) || (joystick == 1))
{
enqueue(0xfe + joystick);
enqueue(joystick_map2ikbd(map));
}
// only report joystick data for joystick 0 if the mouse is disabled
if ((ikbd.state & IKBD_STATE_MOUSE_DISABLED) || (joystick == 1))
{
enqueue(0xfe + joystick);
enqueue(joystick_map2ikbd(map));
}
if (!(ikbd.state & IKBD_STATE_MOUSE_DISABLED))
{
// the fire button also generates a mouse event if
// mouse reporting is enabled
if ((map & JOY_BTN1) != (ikbd.joystick[joystick] & JOY_BTN1))
{
// generate mouse event (ikbd_joystick_buttons is evaluated inside
// user_io_mouse)
ikbd.joystick[joystick] = map;
ikbd_mouse(0, 0, 0);
}
}
}
if (!(ikbd.state & IKBD_STATE_MOUSE_DISABLED))
{
// the fire button also generates a mouse event if
// mouse reporting is enabled
if ((map & JOY_BTN1) != (ikbd.joystick[joystick] & JOY_BTN1))
{
// generate mouse event (ikbd_joystick_buttons is evaluated inside
// user_io_mouse)
ikbd.joystick[joystick] = map;
ikbd_mouse(0, 0, 0);
}
}
}
#ifdef IKBD_DEBUG
else
xprintf("IKBD: no monitor, drop joy %d %x\n", joystick, map);
else
xprintf("IKBD: no monitor, drop joy %d %x\n", joystick, map);
#endif
// save state of joystick for interrogation mode
ikbd.joystick[joystick] = map;
// save state of joystick for interrogation mode
ikbd.joystick[joystick] = map;
}
void ikbd_keyboard(unsigned char code)
{
#ifdef IKBD_DEBUG
xprintf("IKBD: send keycode %x%s\n", code&0x7f, (code&0x80)?" BREAK":"");
xprintf("IKBD: send keycode %x%s\n", code&0x7f, (code&0x80)?" BREAK":"");
#endif
enqueue(code);
enqueue(code);
}
void ikbd_mouse(uint8_t b, int8_t x, int8_t y)
{
if (ikbd.state & IKBD_STATE_MOUSE_DISABLED)
return;
if (ikbd.state & IKBD_STATE_MOUSE_DISABLED)
return;
// joystick and mouse buttons are wired together in
// atari st
b |= (ikbd.joystick[0] & JOY_BTN1)?1:0;
b |= (ikbd.joystick[1] & JOY_BTN1)?2:0;
// joystick and mouse buttons are wired together in
// atari st
b |= (ikbd.joystick[0] & JOY_BTN1)?1:0;
b |= (ikbd.joystick[1] & JOY_BTN1)?2:0;
static unsigned char b_old = 0;
// monitor state of two mouse buttons
if (b != b_old)
{
// check if mouse buttons are supposed to be treated like keys
if (ikbd.state & IKBD_STATE_MOUSE_BUTTON_AS_KEY)
{
// Mouse buttons act like keys (LEFT=0x74 & RIGHT=0x75)
static unsigned char b_old = 0;
// monitor state of two mouse buttons
if (b != b_old)
{
// check if mouse buttons are supposed to be treated like keys
if (ikbd.state & IKBD_STATE_MOUSE_BUTTON_AS_KEY)
{
// Mouse buttons act like keys (LEFT=0x74 & RIGHT=0x75)
// handle left mouse button
if((b ^ b_old) & 1) ikbd_keyboard(0x74 | ((b&1)?0x00:0x80));
// handle right mouse button
if((b ^ b_old) & 2) ikbd_keyboard(0x75 | ((b&2)?0x00:0x80));
}
b_old = b;
}
// handle left mouse button
if((b ^ b_old) & 1) ikbd_keyboard(0x74 | ((b&1)?0x00:0x80));
// handle right mouse button
if((b ^ b_old) & 2) ikbd_keyboard(0x75 | ((b&2)?0x00:0x80));
}
b_old = b;
}
#if 0
if(ikbd.state & IKBD_STATE_MOUSE_BUTTON_AS_KEY)
{
b = 0;
// if mouse position is 0/0 quit here
if(!x && !y) return;
}
if(ikbd.state & IKBD_STATE_MOUSE_BUTTON_AS_KEY)
{
b = 0;
// if mouse position is 0/0 quit here
if(!x && !y) return;
}
#endif
if (ikbd.state & IKBD_STATE_MOUSE_ABSOLUTE)
{
}
else
{
// atari has mouse button bits swapped
enqueue(0xf8|((b&1)?2:0)|((b&2)?1:0));
enqueue(x);
enqueue((ikbd.state & IKBD_STATE_MOUSE_Y_BOTTOM)?-y:y);
}
if (ikbd.state & IKBD_STATE_MOUSE_ABSOLUTE)
{
}
else
{
// atari has mouse button bits swapped
enqueue(0xf8|((b&1)?2:0)|((b&2)?1:0));
enqueue(x);
enqueue((ikbd.state & IKBD_STATE_MOUSE_Y_BOTTOM)?-y:y);
}
}

2
net/am79c874.c
View File

@@ -26,7 +26,7 @@
#define dbg(format, arg...) do { ; } while (0)
#endif /* DBG_AM79 */
/********************************************************************/
/* Initialize the AM79C874 PHY
*
* This function sets up the Auto-Negotiate Advertisement register

776
net/arp.c
View File

@@ -13,7 +13,7 @@
//#define DBG_ARP
#ifdef DBG_ARP
#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
#define dbg(format, arg...) do { xprintf("DEBUG: " format, ##arg); } while (0)
#else
#define dbg(format, arg...) do { ; } while (0)
#endif /* DBG_ARP */
@@ -22,469 +22,459 @@
static uint8_t *arp_find_pair(ARP_INFO *arptab, uint16_t protocol, uint8_t *hwa, uint8_t *pa)
{
/*
* This function searches through the ARP table for the
* specified <protocol,hwa> or <protocol,pa> address pair.
* If it is found, then a a pointer to the non-specified
* address is returned. Otherwise NULL is returned.
* If you pass in <protocol,pa> then you get <hwa> out.
* If you pass in <protocol,hwa> then you get <pa> out.
*/
int slot, i, match = false;
uint8_t *rvalue;
/*
* This function searches through the ARP table for the
* specified <protocol,hwa> or <protocol,pa> address pair.
* If it is found, then a a pointer to the non-specified
* address is returned. Otherwise NULL is returned.
* If you pass in <protocol,pa> then you get <hwa> out.
* If you pass in <protocol,hwa> then you get <pa> out.
*/
int slot, i, match = false;
uint8_t *rvalue;
if (((hwa == 0) && (pa == 0)) || (arptab == 0))
return NULL;
if (((hwa == 0) && (pa == 0)) || (arptab == 0))
return NULL;
rvalue = NULL;
rvalue = NULL;
/*
* Check each protocol address for a match
*/
for (slot = 0; slot < arptab->tab_size; slot++)
{
if ((arptab->table[slot].longevity != ARP_ENTRY_EMPTY) &&
(arptab->table[slot].protocol == protocol))
{
match = true;
if (hwa != 0)
{
/*
* Check the Hardware Address field
*/
rvalue = &arptab->table[slot].pa[0];
for (i = 0; i < arptab->table[slot].hwa_size; i++)
{
if (arptab->table[slot].hwa[i] != hwa[i])
{
match = false;
break;
}
}
}
else
{
/*
* Check the Protocol Address field
*/
rvalue = &arptab->table[slot].hwa[0];
for (i = 0; i < arptab->table[slot].pa_size; i++)
{
if (arptab->table[slot].pa[i] != pa[i])
{
match = false;
break;
}
}
}
if (match)
{
break;
}
}
}
/*
* Check each protocol address for a match
*/
for (slot = 0; slot < arptab->tab_size; slot++)
{
if ((arptab->table[slot].longevity != ARP_ENTRY_EMPTY) &&
(arptab->table[slot].protocol == protocol))
{
match = true;
if (hwa != 0)
{
/*
* Check the Hardware Address field
*/
rvalue = &arptab->table[slot].pa[0];
for (i = 0; i < arptab->table[slot].hwa_size; i++)
{
if (arptab->table[slot].hwa[i] != hwa[i])
{
match = false;
break;
}
}
}
else
{
/*
* Check the Protocol Address field
*/
rvalue = &arptab->table[slot].hwa[0];
for (i = 0; i < arptab->table[slot].pa_size; i++)
{
if (arptab->table[slot].pa[i] != pa[i])
{
match = false;
break;
}
}
}
if (match)
{
break;
}
}
}
if (match)
return rvalue;
else
return NULL;
if (match)
return rvalue;
else
return NULL;
}
void arp_merge(ARP_INFO *arptab, uint16_t protocol, int hwa_size, uint8_t *hwa,
int pa_size, uint8_t *pa, int longevity)
int pa_size, uint8_t *pa, int longevity)
{
/*
* This function merges an entry into the ARP table. If
* either piece is NULL, the function exits, otherwise
* the entry is merged or added, provided there is space.
*/
int i, slot;
uint8_t *ta;
/*
* This function merges an entry into the ARP table. If
* either piece is NULL, the function exits, otherwise
* the entry is merged or added, provided there is space.
*/
int i, slot;
uint8_t *ta;
if ((hwa == NULL) || (pa == NULL) || (arptab == NULL) ||
((longevity != ARP_ENTRY_TEMP) &&
(longevity != ARP_ENTRY_PERM)))
{
return;
}
if ((hwa == NULL) || (pa == NULL) || (arptab == NULL) ||
((longevity != ARP_ENTRY_TEMP) &&
(longevity != ARP_ENTRY_PERM)))
{
return;
}
/* First search ARP table for existing entry */
if ((ta = arp_find_pair(arptab,protocol,NULL,pa)) != 0)
{
/* Update hardware address */
for (i = 0; i < hwa_size; i++)
ta[i] = hwa[i];
return;
}
/* First search ARP table for existing entry */
if ((ta = arp_find_pair(arptab,protocol,NULL,pa)) != 0)
{
/* Update hardware address */
for (i = 0; i < hwa_size; i++)
ta[i] = hwa[i];
return;
}
/* Next try to find an empty slot */
slot = -1;
for (i = 0; i < MAX_ARP_ENTRY; i++)
{
if (arptab->table[i].longevity == ARP_ENTRY_EMPTY)
{
slot = i;
break;
}
}
/* Next try to find an empty slot */
slot = -1;
for (i = 0; i < MAX_ARP_ENTRY; i++)
{
if (arptab->table[i].longevity == ARP_ENTRY_EMPTY)
{
slot = i;
break;
}
}
/* if no empty slot was found, pick a temp slot */
if (slot == -1)
{
for (i = 0; i < MAX_ARP_ENTRY; i++)
{
if (arptab->table[i].longevity == ARP_ENTRY_TEMP)
{
slot = i;
break;
}
}
}
/* if no empty slot was found, pick a temp slot */
if (slot == -1)
{
for (i = 0; i < MAX_ARP_ENTRY; i++)
{
if (arptab->table[i].longevity == ARP_ENTRY_TEMP)
{
slot = i;
break;
}
}
}
/* if after all this, still no slot found, add in last slot */
if (slot == -1)
slot = (MAX_ARP_ENTRY - 1);
/* if after all this, still no slot found, add in last slot */
if (slot == -1)
slot = (MAX_ARP_ENTRY - 1);
/* add the entry into the slot */
arptab->table[slot].protocol = protocol;
/* add the entry into the slot */
arptab->table[slot].protocol = protocol;
arptab->table[slot].hwa_size = (uint8_t) hwa_size;
for (i = 0; i < hwa_size; i++)
arptab->table[slot].hwa[i] = hwa[i];
arptab->table[slot].hwa_size = (uint8_t) hwa_size;
for (i = 0; i < hwa_size; i++)
arptab->table[slot].hwa[i] = hwa[i];
arptab->table[slot].pa_size = (uint8_t) pa_size;
for (i = 0; i < pa_size; i++)
arptab->table[slot].pa[i] = pa[i];
arptab->table[slot].pa_size = (uint8_t) pa_size;
for (i = 0; i < pa_size; i++)
arptab->table[slot].pa[i] = pa[i];
arptab->table[slot].longevity = longevity;
arptab->table[slot].longevity = longevity;
}
void arp_remove(ARP_INFO *arptab, uint16_t protocol, uint8_t *hwa, uint8_t *pa)
{
/*
* This function removes an entry from the ARP table. The
* ARP table is searched according to the non-NULL address
* that is provided.
*/
int slot, i, match;
/*
* This function removes an entry from the ARP table. The
* ARP table is searched according to the non-NULL address
* that is provided.
*/
int slot, i, match;
if (((hwa == 0) && (pa == 0)) || (arptab == 0))
return;
if (((hwa == 0) && (pa == 0)) || (arptab == 0))
return;
/* check each hardware adress for a match */
for (slot = 0; slot < arptab->tab_size; slot++)
{
if ((arptab->table[slot].longevity != ARP_ENTRY_EMPTY) &&
(arptab->table[slot].protocol == protocol))
{
match = true;
if (hwa != 0)
{
/* Check Hardware Address field */
for (i = 0; i < arptab->table[slot].hwa_size; i++)
{
if (arptab->table[slot].hwa[i] != hwa[i])
{
match = false;
break;
}
}
}
else
{
/* Check Protocol Address field */
for (i = 0; i < arptab->table[slot].pa_size; i++)
{
if (arptab->table[slot].pa[i] != pa[i])
{
match = false;
break;
}
}
}
if (match)
{
for (i = 0; i < arptab->table[slot].hwa_size; i++)
arptab->table[slot].hwa[i] = 0;
for (i = 0; i < arptab->table[slot].pa_size; i++)
arptab->table[slot].pa[i] = 0;
arptab->table[slot].longevity = ARP_ENTRY_EMPTY;
break;
}
}
}
/* check each hardware adress for a match */
for (slot = 0; slot < arptab->tab_size; slot++)
{
if ((arptab->table[slot].longevity != ARP_ENTRY_EMPTY) &&
(arptab->table[slot].protocol == protocol))
{
match = true;
if (hwa != 0)
{
/* Check Hardware Address field */
for (i = 0; i < arptab->table[slot].hwa_size; i++)
{
if (arptab->table[slot].hwa[i] != hwa[i])
{
match = false;
break;
}
}
}
else
{
/* Check Protocol Address field */
for (i = 0; i < arptab->table[slot].pa_size; i++)
{
if (arptab->table[slot].pa[i] != pa[i])
{
match = false;
break;
}
}
}
if (match)
{
for (i = 0; i < arptab->table[slot].hwa_size; i++)
arptab->table[slot].hwa[i] = 0;
for (i = 0; i < arptab->table[slot].pa_size; i++)
arptab->table[slot].pa[i] = 0;
arptab->table[slot].longevity = ARP_ENTRY_EMPTY;
break;
}
}
}
}
void arp_request(NIF *nif, uint8_t *pa)
{
/*
* This function broadcasts an ARP request for the protocol
* address "pa"
*/
uint8_t *addr;
NBUF *pNbuf;
arp_frame_hdr *arpframe;
int i, result;
/*
* This function broadcasts an ARP request for the protocol
* address "pa"
*/
uint8_t *addr;
NBUF *pNbuf;
arp_frame_hdr *arpframe;
int i, result;
pNbuf = nbuf_alloc();
if (pNbuf == NULL)
{
dbg("could not allocate Tx buffer\n");
return;
}
arpframe = (arp_frame_hdr *)&pNbuf->data[ARP_HDR_OFFSET];
dbg("%s\r\n", __FUNCTION__);
/* Build the ARP request packet */
arpframe->ar_hrd = ETHERNET;
arpframe->ar_pro = ETH_FRM_IP;
arpframe->ar_hln = 6;
arpframe->ar_pln = 4;
arpframe->opcode = ARP_REQUEST;
pNbuf = nbuf_alloc();
if (pNbuf == NULL)
{
dbg("%s: arp_request couldn't allocate Tx buffer\n", __FUNCTION__);
return;
}
addr = &nif->hwa[0];
for (i = 0; i < 6; i++)
arpframe->ar_sha[i] = addr[i];
arpframe = (arp_frame_hdr *)&pNbuf->data[ARP_HDR_OFFSET];
addr = ip_get_myip(nif_get_protocol_info(nif,ETH_FRM_IP));
for (i = 0; i < 4; i++)
arpframe->ar_spa[i] = addr[i];
/* Build the ARP request packet */
arpframe->ar_hrd = ETHERNET;
arpframe->ar_pro = ETH_FRM_IP;
arpframe->ar_hln = 6;
arpframe->ar_pln = 4;
arpframe->opcode = ARP_REQUEST;
for (i = 0; i < 6; i++)
arpframe->ar_tha[i] = 0x00;
addr = &nif->hwa[0];
for (i = 0; i < 6; i++)
arpframe->ar_sha[i] = addr[i];
for (i = 0; i < 4; i++)
arpframe->ar_tpa[i] = pa[i];
addr = ip_get_myip(nif_get_protocol_info(nif,ETH_FRM_IP));
for (i = 0; i < 4; i++)
arpframe->ar_spa[i] = addr[i];
pNbuf->length = ARP_HDR_LEN;
for (i = 0; i < 6; i++)
arpframe->ar_tha[i] = 0x00;
/* Send the ARP request */
dbg("sending ARP request\r\n");
result = nif->send(nif, nif->broadcast, nif->hwa, ETH_FRM_ARP, pNbuf);
for (i = 0; i < 4; i++)
arpframe->ar_tpa[i] = pa[i];
if (result == 0)
nbuf_free(pNbuf);
pNbuf->length = ARP_HDR_LEN;
/* Send the ARP request */
dbg("%s: sending ARP request\r\n", __FUNCTION__);
result = nif->send(nif, nif->broadcast, nif->hwa, ETH_FRM_ARP, pNbuf);
if (result == 0)
nbuf_free(pNbuf);
}
static int arp_resolve_pa(NIF *nif, uint16_t protocol, uint8_t *pa, uint8_t **ha)
{
/*
* This function accepts a pointer to a protocol address and
* searches the ARP table for a hardware address match. If no
* no match found, false is returned.
*/
ARP_INFO *arptab;
/*
* This function accepts a pointer to a protocol address and
* searches the ARP table for a hardware address match. If no
* no match found, false is returned.
*/
ARP_INFO *arptab;
if ((pa == NULL) || (nif == NULL) || (protocol == 0))
return 0;
if ((pa == NULL) || (nif == NULL) || (protocol == 0))
return 0;
arptab = nif_get_protocol_info (nif,ETH_FRM_ARP);
*ha = arp_find_pair(arptab,protocol,0,pa);
arptab = nif_get_protocol_info (nif,ETH_FRM_ARP);
*ha = arp_find_pair(arptab,protocol,0,pa);
if (*ha == NULL)
return 0;
else
return 1;
if (*ha == NULL)
return 0;
else
return 1;
}
uint8_t *arp_resolve(NIF *nif, uint16_t protocol, uint8_t *pa)
{
int i;
uint8_t *hwa;
int i;
uint8_t *hwa;
/*
* Check to see if the necessary MAC-to-IP translation information
* is in table already
*/
if (arp_resolve_pa(nif, protocol, pa, &hwa))
return hwa;
/*
* Check to see if the necessary MAC-to-IP translation information
* is in table already
*/
if (arp_resolve_pa(nif, protocol, pa, &hwa))
return hwa;
/*
* Ok, it's not, so we need to try to obtain it by broadcasting
* an ARP request. Hopefully the desired host is listening and
* will respond with it's MAC address
*/
for (i = 0; i < 3; i++)
{
arp_request(nif, pa);
/*
* Ok, it's not, so we need to try to obtain it by broadcasting
* an ARP request. Hopefully the desired host is listening and
* will respond with it's MAC address
*/
for (i = 0; i < 3; i++)
{
arp_request(nif, pa);
timer_set_secs(TIMER_NETWORK, ARP_TIMEOUT);
while (timer_get_reference(TIMER_NETWORK))
{
dbg("try to resolve %d.%d.%d.%d\r\n",
pa[0], pa[1], pa[2], pa[3], pa[4]);
if (arp_resolve_pa(nif, protocol, pa, &hwa))
{
dbg("resolved to %02x:%02x:%02x:%02x:%02x:%02x.\r\n",
hwa[0], hwa[1], hwa[2], hwa[3], hwa[4], hwa[5], hwa[6]);
timer_set_secs(TIMER_NETWORK, ARP_TIMEOUT);
while (timer_get_reference(TIMER_NETWORK))
{
dbg("%s: try to resolve %d.%d.%d.%d\r\n", __FUNCTION__,
pa[0], pa[1], pa[2], pa[3], pa[4]);
if (arp_resolve_pa(nif, protocol, pa, &hwa))
{
dbg("%s: resolved to %02x:%02x:%02x:%02x:%02x:%02x.\r\n", __FUNCTION__,
hwa[0], hwa[1], hwa[2], hwa[3], hwa[4], hwa[5], hwa[6]);
return hwa;
}
}
}
return hwa;
}
}
}
return NULL;
return NULL;
}
void arp_init(ARP_INFO *arptab)
{
int slot, i;
int slot, i;
arptab->tab_size = MAX_ARP_ENTRY;
for (slot = 0; slot < arptab->tab_size; slot++)
{
for (i = 0; i < MAX_HWA_SIZE; i++)
arptab->table[slot].hwa[i] = 0;
for (i = 0; i < MAX_PA_SIZE; i++)
arptab->table[slot].pa[i] = 0;
arptab->table[slot].longevity = ARP_ENTRY_EMPTY;
arptab->table[slot].hwa_size = 0;
arptab->table[slot].pa_size = 0;
}
arptab->tab_size = MAX_ARP_ENTRY;
for (slot = 0; slot < arptab->tab_size; slot++)
{
for (i = 0; i < MAX_HWA_SIZE; i++)
arptab->table[slot].hwa[i] = 0;
for (i = 0; i < MAX_PA_SIZE; i++)
arptab->table[slot].pa[i] = 0;
arptab->table[slot].longevity = ARP_ENTRY_EMPTY;
arptab->table[slot].hwa_size = 0;
arptab->table[slot].pa_size = 0;
}
}
void arp_handler(NIF *nif, NBUF *pNbuf)
{
/*
* ARP protocol handler
*/
uint8_t *addr;
ARP_INFO *arptab;
int longevity;
arp_frame_hdr *rx_arpframe, *tx_arpframe;
/*
* ARP protocol handler
*/
uint8_t *addr;
ARP_INFO *arptab;
int longevity;
arp_frame_hdr *rx_arpframe, *tx_arpframe;
arptab = nif_get_protocol_info(nif, ETH_FRM_ARP);
rx_arpframe = (arp_frame_hdr *) &pNbuf->data[pNbuf->offset];
arptab = nif_get_protocol_info(nif, ETH_FRM_ARP);
rx_arpframe = (arp_frame_hdr *) &pNbuf->data[pNbuf->offset];
/*
* Check for an appropriate ARP packet
*/
if ((pNbuf->length < ARP_HDR_LEN) ||
(rx_arpframe->ar_hrd != ETHERNET) ||
(rx_arpframe->ar_hln != 6) ||
(rx_arpframe->ar_pro != ETH_FRM_IP) ||
(rx_arpframe->ar_pln != 4))
{
dbg("received packet is not an ARP packet, discard it\r\n");
nbuf_free(pNbuf);
return;
}
/*
* Check for an appropriate ARP packet
*/
if ((pNbuf->length < ARP_HDR_LEN) ||
(rx_arpframe->ar_hrd != ETHERNET) ||
(rx_arpframe->ar_hln != 6) ||
(rx_arpframe->ar_pro != ETH_FRM_IP) ||
(rx_arpframe->ar_pln != 4))
{
nbuf_free(pNbuf);
return;
}
/*
* Check to see if it was addressed to me - if it was, keep this
* ARP entry in the table permanently; if not, mark it so that it
* can be displaced later if necessary
*/
addr = ip_get_myip(nif_get_protocol_info(nif,ETH_FRM_IP));
if ((rx_arpframe->ar_tpa[0] == addr[0]) &&
(rx_arpframe->ar_tpa[1] == addr[1]) &&
(rx_arpframe->ar_tpa[2] == addr[2]) &&
(rx_arpframe->ar_tpa[3] == addr[3]) )
{
dbg("received ARP packet is a permanent one, store it\r\n");
longevity = ARP_ENTRY_PERM;
}
else
{
dbg("received ARP packet was not addressed to us, keep only temporarily\r\n");
longevity = ARP_ENTRY_TEMP;
}
/*
* Check to see if it was addressed to me - if it was, keep this
* ARP entry in the table permanently; if not, mark it so that it
* can be displaced later if necessary
*/
addr = ip_get_myip(nif_get_protocol_info(nif,ETH_FRM_IP));
if ((rx_arpframe->ar_tpa[0] == addr[0]) &&
(rx_arpframe->ar_tpa[1] == addr[1]) &&
(rx_arpframe->ar_tpa[2] == addr[2]) &&
(rx_arpframe->ar_tpa[3] == addr[3]) )
{
longevity = ARP_ENTRY_PERM;
}
else
longevity = ARP_ENTRY_TEMP;
/*
* Add ARP info into the table
*/
arp_merge(arptab,
rx_arpframe->ar_pro,
rx_arpframe->ar_hln,
&rx_arpframe->ar_sha[0],
rx_arpframe->ar_pln,
&rx_arpframe->ar_spa[0],
longevity
);
/*
* Add ARP info into the table
*/
arp_merge(arptab,
rx_arpframe->ar_pro,
rx_arpframe->ar_hln,
&rx_arpframe->ar_sha[0],
rx_arpframe->ar_pln,
&rx_arpframe->ar_spa[0],
longevity
);
switch (rx_arpframe->opcode)
{
case ARP_REQUEST:
/*
* Check to see if request is directed to me
*/
if ((rx_arpframe->ar_tpa[0] == addr[0]) &&
(rx_arpframe->ar_tpa[1] == addr[1]) &&
(rx_arpframe->ar_tpa[2] == addr[2]) &&
(rx_arpframe->ar_tpa[3] == addr[3]) )
{
dbg("received arp request directed to us, replying\r\n");
/*
* Reuse the current network buffer to assemble an ARP reply
*/
tx_arpframe = (arp_frame_hdr *)&pNbuf->data[ARP_HDR_OFFSET];
switch (rx_arpframe->opcode)
{
case ARP_REQUEST:
/*
* Check to see if request is directed to me
*/
if ((rx_arpframe->ar_tpa[0] == addr[0]) &&
(rx_arpframe->ar_tpa[1] == addr[1]) &&
(rx_arpframe->ar_tpa[2] == addr[2]) &&
(rx_arpframe->ar_tpa[3] == addr[3]) )
{
/*
* Reuse the current network buffer to assemble an ARP reply
*/
tx_arpframe = (arp_frame_hdr *)&pNbuf->data[ARP_HDR_OFFSET];
/*
* Build new ARP frame from the received data
*/
tx_arpframe->ar_hrd = ETHERNET;
tx_arpframe->ar_pro = ETH_FRM_IP;
tx_arpframe->ar_hln = 6;
tx_arpframe->ar_pln = 4;
tx_arpframe->opcode = ARP_REPLY;
tx_arpframe->ar_tha[0] = rx_arpframe->ar_sha[0];
tx_arpframe->ar_tha[1] = rx_arpframe->ar_sha[1];
tx_arpframe->ar_tha[2] = rx_arpframe->ar_sha[2];
tx_arpframe->ar_tha[3] = rx_arpframe->ar_sha[3];
tx_arpframe->ar_tha[4] = rx_arpframe->ar_sha[4];
tx_arpframe->ar_tha[5] = rx_arpframe->ar_sha[5];
tx_arpframe->ar_tpa[0] = rx_arpframe->ar_spa[0];
tx_arpframe->ar_tpa[1] = rx_arpframe->ar_spa[1];
tx_arpframe->ar_tpa[2] = rx_arpframe->ar_spa[2];
tx_arpframe->ar_tpa[3] = rx_arpframe->ar_spa[3];
/*
* Build new ARP frame from the received data
*/
tx_arpframe->ar_hrd = ETHERNET;
tx_arpframe->ar_pro = ETH_FRM_IP;
tx_arpframe->ar_hln = 6;
tx_arpframe->ar_pln = 4;
tx_arpframe->opcode = ARP_REPLY;
tx_arpframe->ar_tha[0] = rx_arpframe->ar_sha[0];
tx_arpframe->ar_tha[1] = rx_arpframe->ar_sha[1];
tx_arpframe->ar_tha[2] = rx_arpframe->ar_sha[2];
tx_arpframe->ar_tha[3] = rx_arpframe->ar_sha[3];
tx_arpframe->ar_tha[4] = rx_arpframe->ar_sha[4];
tx_arpframe->ar_tha[5] = rx_arpframe->ar_sha[5];
tx_arpframe->ar_tpa[0] = rx_arpframe->ar_spa[0];
tx_arpframe->ar_tpa[1] = rx_arpframe->ar_spa[1];
tx_arpframe->ar_tpa[2] = rx_arpframe->ar_spa[2];
tx_arpframe->ar_tpa[3] = rx_arpframe->ar_spa[3];
/*
* Now copy in the new information
*/
addr = &nif->hwa[0];
tx_arpframe->ar_sha[0] = addr[0];
tx_arpframe->ar_sha[1] = addr[1];
tx_arpframe->ar_sha[2] = addr[2];
tx_arpframe->ar_sha[3] = addr[3];
tx_arpframe->ar_sha[4] = addr[4];
tx_arpframe->ar_sha[5] = addr[5];
/*
* Now copy in the new information
*/
addr = &nif->hwa[0];
tx_arpframe->ar_sha[0] = addr[0];
tx_arpframe->ar_sha[1] = addr[1];
tx_arpframe->ar_sha[2] = addr[2];
tx_arpframe->ar_sha[3] = addr[3];
tx_arpframe->ar_sha[4] = addr[4];
tx_arpframe->ar_sha[5] = addr[5];
addr = ip_get_myip(nif_get_protocol_info(nif,ETH_FRM_IP));
tx_arpframe->ar_spa[0] = addr[0];
tx_arpframe->ar_spa[1] = addr[1];
tx_arpframe->ar_spa[2] = addr[2];
tx_arpframe->ar_spa[3] = addr[3];
addr = ip_get_myip(nif_get_protocol_info(nif,ETH_FRM_IP));
tx_arpframe->ar_spa[0] = addr[0];
tx_arpframe->ar_spa[1] = addr[1];
tx_arpframe->ar_spa[2] = addr[2];
tx_arpframe->ar_spa[3] = addr[3];
/*
* Save the length of my packet in the buffer structure
*/
pNbuf->length = ARP_HDR_LEN;
/*
* Save the length of my packet in the buffer structure
*/
pNbuf->length = ARP_HDR_LEN;
nif->send(nif,
&tx_arpframe->ar_tha[0],
&tx_arpframe->ar_sha[0],
ETH_FRM_ARP,
pNbuf);
}
else
{
dbg("ARP request not addressed to us, discarding\r\n");
nbuf_free(pNbuf);
}
break;
nif->send(nif,
&tx_arpframe->ar_tha[0],
&tx_arpframe->ar_sha[0],
ETH_FRM_ARP,
pNbuf);
}
else
nbuf_free(pNbuf);
break;
case ARP_REPLY:
/*
* The ARP Reply case is already taken care of
*/
default:
nbuf_free(pNbuf);
break;
}
case ARP_REPLY:
/*
* The ARP Reply case is already taken care of
*/
/* missing break is intentional */
default:
nbuf_free(pNbuf);
break;
}
return;
return;
}

5
net/bootp.c
View File

@@ -99,9 +99,7 @@ void bootp_handler(NIF *nif, NBUF *nbuf)
rx_p = (struct bootp_packet *) &nbuf->data[nbuf->offset];
udpframe = (udp_frame_hdr *) &nbuf->data[nbuf->offset - UDP_HDR_SIZE];
/*
* check packet if it is valid and if it is really intended for us
*/
/* check packet if it is valid and if it is really intended for us */
if (rx_p->type == BOOTP_TYPE_BOOTREPLY && rx_p->xid == XID)
{
@@ -111,7 +109,6 @@ void bootp_handler(NIF *nif, NBUF *nbuf)
}
else
{
dbg("received invalid bootp reply\r\n");
/* not valid */
return;
}

1723
net/fec.c
View File

File diff suppressed because it is too large Load Diff

20
net/ip.c
View File

@@ -6,10 +6,11 @@
*
* Modifications:
*/
#include <bas_types.h>
#include "net.h"
#include "bas_printf.h"
#include "bas_string.h"
#include <stdint.h>
#include <stddef.h>
//#define IP_DEBUG
@@ -75,7 +76,7 @@ uint8_t *ip_resolve_route(NIF *nif, IP_ADDR_P destip)
if (memcmp(destip, bc, 4) == 0)
{
dbg("destip is broadcast address, no gateway needed\r\n");
dbg("destip is broadcast address, no gateway needed\r\n");
return destip;
}
@@ -169,7 +170,7 @@ int ip_send(NIF *nif, uint8_t *dest, uint8_t *src, uint8_t protocol, NBUF *pNbuf
route = ip_resolve_route(nif, dest);
if (route == NULL)
{
dbg("Unable to locate %d.%d.%d.%d\r\n",
dbg("Unable to locate %d.%d.%d.%d\r\n",
dest[0], dest[1], dest[2], dest[3]);
return 0;
}
@@ -177,9 +178,9 @@ int ip_send(NIF *nif, uint8_t *dest, uint8_t *src, uint8_t protocol, NBUF *pNbuf
else
{
route = bc;
dbg("route = broadcast\r\n");
dbg("nif = %p\r\n", nif);
dbg("nif->send = %p\r\n", nif->send);
dbg("route = broadcast\r\n");
dbg("nif = %p\r\n", nif);
dbg("nif->send = %p\r\n", nif->send);
}
return nif->send(nif, route, &nif->hwa[0], ETH_FRM_IP, pNbuf);
@@ -290,12 +291,15 @@ void ip_handler(NIF *nif, NBUF *pNbuf)
*/
if (!validate_ip_hdr(nif, ipframe))
{
dbg("not a valid IP packet!\r\n");
dbg("not a valid IP packet!\r\n");
nbuf_free(pNbuf);
return;
}
pNbuf->offset += (IP_IHL(ipframe) * 4);
pNbuf->length = (uint16_t)(IP_LENGTH(ipframe) - (IP_IHL(ipframe) * 4));
/*
* Call the appriopriate handler
*/
@@ -308,7 +312,7 @@ void ip_handler(NIF *nif, NBUF *pNbuf)
udp_handler(nif,pNbuf);
break;
default:
dbg("no protocol handler registered for protocol %d\r\n",
dbg("no protocol handler registered for protocol %d\r\n",
__FUNCTION__, IP_PROTOCOL(ipframe));
nbuf_free(pNbuf);
break;

29
net/nbuf.c
View File

@@ -2,7 +2,7 @@
* File: nbuf.c
* Purpose: Implementation of network buffer scheme.
*
* Notes:
* Notes:
*/
#include "queue.h"
#include "net.h"
@@ -12,9 +12,9 @@
#include "bas_printf.h"
#define DBG_NBUF
//#define DBG_NBUF
#if defined(DBG_NBUF)
#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
#define dbg(format, arg...) do { xprintf("DEBUG: " format, ##arg); } while (0)
#else
#define dbg(format, arg...) do { ; } while (0)
#endif /* DBG_NBUF */
@@ -42,13 +42,13 @@ int nbuf_init(void)
int i;
NBUF *nbuf;
for (i = 0; i < NBUF_MAXQ; ++i)
for (i=0; i<NBUF_MAXQ; ++i)
{
/* Initialize all the queues */
queue_init(&nbuf_queue[i]);
}
dbg("Creating %d net buffers of %d bytes\r\n", NBUF_MAX, NBUF_SZ);
dbg("%s: Creating %d net buffers of %d bytes\r\n", __FUNCTION__, NBUF_MAX, NBUF_SZ);
for (i = 0; i < NBUF_MAX; ++i)
{
@@ -76,19 +76,18 @@ int nbuf_init(void)
queue_add(&nbuf_queue[NBUF_FREE], (QNODE *)nbuf);
}
dbg("NBUF allocation complete\r\n");
dbg("%s: NBUF allocation complete\r\n", __FUNCTION__);
return 0;
}
/*
/*
* Return all the allocated memory to the heap
*/
void nbuf_flush(void)
{
NBUF *nbuf;
int i;
int level = set_ipl(7);
int i, level = set_ipl(7);
int n = 0;
for (i = 0; i < NBUF_MAX; ++i)
@@ -105,7 +104,7 @@ void nbuf_flush(void)
set_ipl(level);
}
/*
/*
* Allocate a network buffer from the free list
*
* Return Value:
@@ -172,13 +171,12 @@ void nbuf_add(int q, NBUF *nbuf)
}
/*
* Put all the network buffers back into the free list
* Put all the network buffers back into the free list
*/
void nbuf_reset(void)
{
NBUF *nbuf;
int i;
int level = set_ipl(7);
int i, level = set_ipl(7);
for (i = 1; i < NBUF_MAXQ; ++i)
{
@@ -195,9 +193,7 @@ void nbuf_debug_dump(void)
{
#ifdef DBG_NBUF
NBUF *nbuf;
int i;
int j;
int level;
int i, j, level;
level = set_ipl(7);
@@ -208,7 +204,6 @@ void nbuf_debug_dump(void)
dbg("--------------------------------------\r\n");
j = 0;
nbuf = (NBUF *) queue_peek(&nbuf_queue[i]);
while (nbuf != NULL)
{
dbg("%d\t0x%08x\t0x%04x\t0x%04x\r\n", j++, nbuf->data,

260
net/net_timer.c
View File

@@ -5,15 +5,16 @@
*
* Notes:
*/
#include "net_timer.h"
#include <stdint.h>
#include <stdbool.h>
#include "bas_printf.h"
#include "MCF5475.h"
#include "interrupts.h"
//#define DBG_TMR
#ifdef DBG_TMR
#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
#define dbg(format, arg...) do { xprintf("DEBUG: " format, ##arg); } while (0)
#else
#define dbg(format, arg...) do { ; } while (0)
#endif /* DBG_TMR */
@@ -31,172 +32,167 @@
static NET_TIMER net_timer[4] =
{
{0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0}
{0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0}
};
bool timer_default_isr(void *not_used, NET_TIMER *t)
int timer_default_isr(void *not_used, NET_TIMER *t)
{
(void) not_used;
(void) not_used;
/*
* Clear the pending event
*/
MCF_GPT_GMS(t->ch) = 0;
/*
* Clear the pending event
*/
MCF_GPT_GMS(t->ch) = 0;
dbg("timer isr called for timer channel %d\r\n");
dbg("%s: timer isr called for timer channel %d\r\n", __FUNCTION__);
/*
* Clear the reference - the desired seconds have expired
*/
t->reference = 0;
/*
* Clear the reference - the desired seconds have expired
*/
t->reference = 0;
return 1;
return 1;
}
void timer_irq_enable(uint8_t ch)
{
/*
* Setup the appropriate ICR
*/
MCF_INTC_ICR(TIMER_VECTOR(ch) - 64) = MCF_INTC_ICR_IP(net_timer[ch].pri) |
MCF_INTC_ICR_IL(net_timer[ch].lvl);
/*
* Setup the appropriate ICR
*/
MCF_INTC_ICR(TIMER_VECTOR(ch) - 64) =
(uint8_t)(0
| MCF_INTC_ICR_IP(net_timer[ch].pri)
| MCF_INTC_ICR_IL(net_timer[ch].lvl));
/*
* Unmask the FEC interrupt in the interrupt controller
*/
if (ch == 3)
{
MCF_INTC_IMRH &= ~MCF_INTC_IMRH_INT_MASK59;
}
else if (ch == 2)
{
MCF_INTC_IMRH &= ~MCF_INTC_IMRH_INT_MASK60;
}
else if (ch == 1)
{
MCF_INTC_IMRH &= ~MCF_INTC_IMRH_INT_MASK61;
}
else
{
MCF_INTC_IMRH &= ~MCF_INTC_IMRH_INT_MASK62;
}
/*
* Unmask the FEC interrupt in the interrupt controller
*/
if (ch == 3)
MCF_INTC_IMRH &= ~MCF_INTC_IMRH_INT_MASK59;
else if (ch == 2)
MCF_INTC_IMRH &= ~MCF_INTC_IMRH_INT_MASK60;
else if (ch == 1)
MCF_INTC_IMRH &= ~MCF_INTC_IMRH_INT_MASK61;
else
MCF_INTC_IMRH &= ~MCF_INTC_IMRH_INT_MASK62;
}
bool timer_set_secs(uint8_t ch, uint32_t secs)
{
uint16_t timeout;
uint16_t timeout;
/*
* Reset the timer
*/
MCF_GPT_GMS(ch) = 0;
/*
* Reset the timer
*/
MCF_GPT_GMS(ch) = 0;
/*
* Get the timeout in seconds
*/
timeout = (uint16_t)(secs * net_timer[ch].cnt);
/*
* Get the timeout in seconds
*/
timeout = (uint16_t)(secs * net_timer[ch].cnt);
/*
* Set the reference indicating that we have not yet reached the
* desired timeout
*/
net_timer[ch].reference = 1;
/*
* Set the reference indicating that we have not yet reached the
* desired timeout
*/
net_timer[ch].reference = 1;
/*
* Enable timer interrupt to the processor
*/
timer_irq_enable(ch);
/*
* Enable timer interrupt to the processor
*/
timer_irq_enable(ch);
/*
* Enable the timer using the pre-calculated values
*/
MCF_GPT_GCIR(ch) = (0
| MCF_GPT_GCIR_CNT(timeout)
| MCF_GPT_GCIR_PRE(net_timer[ch].pre)
);
MCF_GPT_GMS(ch) = net_timer[ch].gms;
/*
* Enable the timer using the pre-calculated values
*/
MCF_GPT_GCIR(ch) = (0
| MCF_GPT_GCIR_CNT(timeout)
| MCF_GPT_GCIR_PRE(net_timer[ch].pre)
);
MCF_GPT_GMS(ch) = net_timer[ch].gms;
return true;
return true;
}
uint32_t timer_get_reference(uint8_t ch)
{
return (uint32_t) net_timer[ch].reference;
{
return (uint32_t) net_timer[ch].reference;
}
bool timer_init(uint8_t ch, uint8_t lvl, uint8_t pri)
{
/*
* Initialize the timer to expire after one second
*
* This routine should only be called by the project (board) specific
* initialization code.
*/
if (!((ch <= 3) && (lvl <= 7) && (lvl >= 1) && (pri <= 7)))
{
dbg("illegal parameters (ch=%d, lvl=%d, pri=%d)\r\n", ch, lvl, pri);
/*
* Initialize the timer to expire after one second
*
* This routine should only be called by the project (board) specific
* initialization code.
*/
if (!((ch <= 3) && (lvl <= 7) && (lvl >= 1) && (pri <= 7)))
{
dbg("%s: illegal parameters (ch=%d, lvl=%d, pri=%d)\r\n", __FUNCTION__,
ch, lvl, pri);
return false;
}
return false;
}
/*
* Reset the timer
*/
MCF_GPT_GMS(ch) = 0;
/*
* Reset the timer
*/
MCF_GPT_GMS(ch) = 0;
/*
* Save off the channel, and interrupt lvl/pri information
*/
net_timer[ch].ch = ch;
net_timer[ch].lvl = lvl;
net_timer[ch].pri = pri;
/*
* Save off the channel, and interrupt lvl/pri information
*/
net_timer[ch].ch = ch;
net_timer[ch].lvl = lvl;
net_timer[ch].pri = pri;
/*
* Register the timer interrupt handler
*/
if (!isr_register_handler(TIMER_VECTOR(ch), 3, 0,
(bool (*)(void *,void *)) timer_default_isr,
NULL,
(void *) &net_timer[ch])
)
{
dbg("could not register timer interrupt handler\r\n");
return false;
}
dbg("timer handler registered\r\n", __FUNCTION__);
/*
* Register the timer interrupt handler
*/
if (!isr_register_handler(TIMER_VECTOR(ch),
(int (*)(void *,void *)) timer_default_isr,
NULL,
(void *) &net_timer[ch])
)
{
dbg("%s: could not register timer interrupt handler\r\n", __FUNCTION__);
return false;
}
dbg("%s: timer handler registered\r\n", __FUNCTION__);
/*
* Calculate the require CNT value to get a 1 second timeout
*
* 1 sec = CNT * Clk Period * PRE
* CNT = 1 sec / (Clk Period * PRE)
* CNT = Clk Freq / PRE
*
* The system clock frequency is defined as SYSTEM_CLOCK and
* is given in MHz. We need to multiple it by 1000000 to get the
* true value. If we assume PRE to be the maximum of 0xFFFF,
* then the CNT value needed to achieve a 1 second timeout is
* given by:
*
* CNT = SYSTEM_CLOCK * (1000000/0xFFFF)
*/
net_timer[ch].pre = 0xFFFF;
net_timer[ch].cnt = (uint16_t) ((SYSCLK / 1000) * (1000000 / 0xFFFF));
/*
* Calculate the require CNT value to get a 1 second timeout
*
* 1 sec = CNT * Clk Period * PRE
* CNT = 1 sec / (Clk Period * PRE)
* CNT = Clk Freq / PRE
*
* The system clock frequency is defined as SYSTEM_CLOCK and
* is given in MHz. We need to multiple it by 1000000 to get the
* true value. If we assume PRE to be the maximum of 0xFFFF,
* then the CNT value needed to achieve a 1 second timeout is
* given by:
*
* CNT = SYSTEM_CLOCK * (1000000/0xFFFF)
*/
net_timer[ch].pre = 0xFFFF;
net_timer[ch].cnt = (uint16_t) ((SYSCLK / 1000) * (1000000 / 0xFFFF));
/*
* Save off the appropriate mode select register value
*/
net_timer[ch].gms = (0
| MCF_GPT_GMS_TMS_GPIO
| MCF_GPT_GMS_IEN
| MCF_GPT_GMS_SC
| MCF_GPT_GMS_CE
);
/*
* Save off the appropriate mode select register value
*/
net_timer[ch].gms = (0
| MCF_GPT_GMS_TMS_GPIO
| MCF_GPT_GMS_IEN
| MCF_GPT_GMS_SC
| MCF_GPT_GMS_CE
);
return true;
return true;
}

13
net/nif.c
View File

@@ -11,9 +11,12 @@
#include "bas_types.h"
#include "bas_printf.h"
#include <stdint.h>
#include <stdbool.h>
#define DBG_NIF
#ifdef DBG_NIF
#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
#define dbg(format, arg...) do { xprintf("DEBUG: " format, ##arg); } while (0)
#else
#define dbg(format, arg...) do { ; } while (0)
#endif /* DBG_NIF */
@@ -53,13 +56,13 @@ void nif_protocol_handler(NIF *nif, uint16_t protocol, NBUF *pNbuf)
{
if (nif->protocol[index].protocol == protocol)
{
dbg("call protocol handler for protocol %d at %p\r\n", protocol,
dbg("%s: call protocol handler for protocol %d at %p\r\n", __FUNCTION__, protocol,
nif->protocol[index].handler);
nif->protocol[index].handler(nif,pNbuf);
return;
}
}
dbg("no protocol handler found for protocol %d\r\n", protocol);
dbg("%s: no protocol handler found for protocol %d\r\n", __FUNCTION__, protocol);
}
void *nif_get_protocol_info(NIF *nif, uint16_t protocol)
@@ -84,12 +87,12 @@ int nif_bind_protocol(NIF *nif, uint16_t protocol, void (*handler)(NIF *,NBUF *)
{
/*
* This function registers 'protocol' as a supported
* protocol in 'nif'.
* protocol in 'nif'.
*/
if (nif->num_protocol < (MAX_SUP_PROTO - 1))
{
nif->protocol[nif->num_protocol].protocol = protocol;
nif->protocol[nif->num_protocol].handler = (void(*)(NIF *, NBUF *)) handler;
nif->protocol[nif->num_protocol].handler = (void(*)(NIF*,NBUF*))handler;
nif->protocol[nif->num_protocol].info = info;
++nif->num_protocol;

31
net/tftp.c
View File

@@ -9,7 +9,10 @@
*
*/
#include "bas_types.h"
#include <stdint.h>
#include <stdbool.h>
#include <stddef.h>
#include "bas_printf.h"
#include "bas_string.h"
#include "net.h"
@@ -100,7 +103,7 @@ static int tftp_ack(uint16_t blocknum)
nbuf_free(pNbuf);
return result;
}
}
static int tftp_error(uint16_t error_code, uint16_t server_port)
{
@@ -169,7 +172,7 @@ void tftp_handler(NIF *nif, NBUF *pNbuf)
cnt = 0;
}
else
{
{
/* Check the server's transfer ID */
if (tcxn.server_port != UDP_SOURCE(udpframe))
{
@@ -271,10 +274,10 @@ void tftp_handler(NIF *nif, NBUF *pNbuf)
void tftp_end(int success)
{
/*
* Following a successful transfer the caller should pass in
* true, there should have been no ERROR packets received, and
* the connection should have been marked as closed by the
/*
* Following a successful transfer the caller should pass in
* true, there should have been no ERROR packets received, and
* the connection should have been marked as closed by the
* tftp_in_char() routine.
*/
if (success && !tcxn.error && (tcxn.open == false))
@@ -408,10 +411,10 @@ int tftp_write(NIF *nif, char *fn, IP_ADDR_P server, uint32_t begin, uint32_t en
/* Attempt to send the packet */
for (i = 0; i < 3; ++i)
{
result = udp_send(tcxn.nif,
tcxn.server_ip,
tcxn.my_port,
tcxn.server_port,
result = udp_send(tcxn.nif,
tcxn.server_ip,
tcxn.my_port,
tcxn.server_port,
pNbuf);
if (result == 1)
@@ -549,8 +552,8 @@ int tftp_in_char(void)
if (tcxn.next_char != NULL)
{
/*
* A buffer is already being worked on - grab next
/*
* A buffer is already being worked on - grab next
* byte from it
*/
retval = *tcxn.next_char++;
@@ -558,7 +561,7 @@ int tftp_in_char(void)
{
/* The buffer is depleted; add it back to the free queue */
pNbuf = (NBUF *)queue_remove(&tcxn.queue);
nbuf_free(pNbuf);
tcxn.next_char = NULL;
}

10
net/udp.c
View File

@@ -14,7 +14,7 @@
//#define DBG_UDP
#if defined(DBG_UDP)
#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
#define dbg(format, arg...) do { xprintf("DEBUG: " format "\r\n", ##arg); } while (0)
#else
#define dbg(format, arg...) do { ; } while (0)
#endif /* DBG_UDP */
@@ -112,7 +112,7 @@ int udp_send(NIF *nif, uint8_t *dest, int sport, int dport, NBUF *pNbuf)
if (nif == NULL)
{
dbg("nif is NULL\r\n");
dbg("%s: nif is NULL\r\n", __FUNCTION__);
return 0;
}
@@ -141,7 +141,7 @@ int udp_send(NIF *nif, uint8_t *dest, int sport, int dport, NBUF *pNbuf)
myip = ip_get_myip(nif_get_protocol_info(nif, ETH_FRM_IP));
dbg("sent UDP request to %d.%d.%d.%d from %d.%d.%d.%d\r\n",
dbg("%s: sent UDP request to %d.%d.%d.%d from %d.%d.%d.%d\r\n", __FUNCTION__,
dest[0], dest[1], dest[2], dest[3],
myip[0], myip[1], myip[2], myip[3]);
@@ -159,7 +159,7 @@ void udp_handler(NIF *nif, NBUF *pNbuf)
udpframe = (udp_frame_hdr *) &pNbuf->data[pNbuf->offset];
dbg("packet received\r\n",);
dbg("%s: packet received\r\n", __FUNCTION__);
/*
* Adjust the length and valid data offset of the packet we are
@@ -176,7 +176,7 @@ void udp_handler(NIF *nif, NBUF *pNbuf)
handler(nif, pNbuf);
else
{
dbg("received UDP packet for non-supported port\n");
dbg("%s: received UDP packet for non-supported port\n", __FUNCTION__);
nbuf_free(pNbuf);
}

1911
pci/ehci-hcd.c
View File

File diff suppressed because it is too large Load Diff

3510
pci/ohci-hcd.c
View File

File diff suppressed because it is too large Load Diff

1625
pci/pci.c
View File

File diff suppressed because it is too large Load Diff

3
spi/dspi.c
View File

@@ -25,6 +25,7 @@
* Author: mfro
*/
#include <stdint.h>
#include <bas_types.h>
#include <MCF5475.h>
@@ -35,7 +36,7 @@ struct baudrate
int divider;
};
static const int system_clock = 132000000; /* System clock in Hz */
static const int system_clock = 133000000; /* System clock in Hz */
struct baudrate baudrates[] =
{

3
spi/mmc.c
View File

@@ -1,3 +1,4 @@
#include <stdint.h>
#include <bas_types.h>
#include <sd_card.h>
#include <bas_printf.h>
@@ -465,7 +466,7 @@ DSTATUS disk_initialize(uint8_t drv)
{
uint8_t buff[16];
res = disk_ioctl(0, MMC_GET_CSD, buff);
if (res == RES_OK)
{
debug_printf("CSD of card:\r\n");

540
sys/BaS.c
View File

@@ -21,7 +21,8 @@
* Copyright 2012 M. Froeschle
*/
#include <bas_types.h>
#include <stdint.h>
#include <stdbool.h>
#include "MCF5475.h"
#include "startcf.h"
@@ -48,16 +49,13 @@
#include "interrupts.h"
#include "exceptions.h"
#include "net_timer.h"
#include "pci.h"
#include "video.h"
//#define BAS_DEBUG
#if defined(BAS_DEBUG)
#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
#define dbg(format, arg...) do { xprintf("DEBUG: " format "\r\n", ##arg); } while (0)
#else
#define dbg(format, arg...) do { ; } while (0)
#endif
#define err(format, arg...) do { xprintf("ERROR: %s(): " format, __FUNCTION__, ##arg); } while (0)
/* imported routines */
extern int vec_init();
@@ -79,12 +77,10 @@ extern uint8_t _EMUTOS_SIZE[];
*/
static inline bool pic_txready(void)
{
if (MCF_PSC3_PSCSR & MCF_PSC_PSCSR_TXRDY)
{
return true;
}
if (MCF_PSC3_PSCSR & MCF_PSC_PSCSR_TXRDY)
return true;
return false;
return false;
}
/*
@@ -92,367 +88,373 @@ static inline bool pic_txready(void)
*/
static inline bool pic_rxready(void)
{
if (MCF_PSC3_PSCSR & MCF_PSC_PSCSR_RXRDY)
{
return true;
}
if (MCF_PSC3_PSCSR & MCF_PSC_PSCSR_RXRDY)
return true;
return false;
return false;
}
void write_pic_byte(uint8_t value)
{
/*
* Wait until the transmitter is ready or 1000us are passed
*/
waitfor(1000, pic_txready);
/* Wait until the transmitter is ready or 1000us are passed */
waitfor(1000, pic_txready);
/*
* Transmit the byte
*/
*(volatile uint8_t*)(&MCF_PSC3_PSCTB_8BIT) = value; // Really 8-bit
/* Transmit the byte */
*(volatile uint8_t*)(&MCF_PSC3_PSCTB_8BIT) = value; // Really 8-bit
}
uint8_t read_pic_byte(void)
{
/*
* Wait until a byte has been received or 1000us are passed
*/
waitfor(1000, pic_rxready);
/* Wait until a byte has been received or 1000us are passed */
waitfor(1000, pic_rxready);
/*
* Return the received byte
*/
return * (volatile uint8_t *) (&MCF_PSC3_PSCTB_8BIT); // Really 8-bit
/* Return the received byte */
return *(volatile uint8_t*)(&MCF_PSC3_PSCTB_8BIT); // Really 8-bit
}
void pic_init(void)
{
char answer[4] = "OLD";
char answer[4] = "OLD";
xprintf("initialize the PIC: ");
xprintf("initialize the PIC: ");
/*
* Send the PIC initialization string
*/
write_pic_byte('A');
write_pic_byte('C');
write_pic_byte('P');
write_pic_byte('F');
/* Send the PIC initialization string */
write_pic_byte('A');
write_pic_byte('C');
write_pic_byte('P');
write_pic_byte('F');
/*
* Read the 3-char answer string. Should be "OK!".
*/
answer[0] = read_pic_byte();
answer[1] = read_pic_byte();
answer[2] = read_pic_byte();
answer[3] = '\0';
/* Read the 3-char answer string. Should be "OK!". */
answer[0] = read_pic_byte();
answer[1] = read_pic_byte();
answer[2] = read_pic_byte();
answer[3] = '\0';
if (answer[0] != 'O' || answer[1] != 'K' || answer[2] != '!')
{
dbg("PIC initialization failed. Already initialized?\r\n");
}
else
{
xprintf("%s\r\n", answer);
}
if (answer[0] != 'O' || answer[1] != 'K' || answer[2] != '!')
{
dbg("%s: PIC initialization failed. Already initialized?\r\n", __FUNCTION__);
}
else
{
xprintf("%s\r\n", answer);
}
}
void nvram_init(void)
{
int i;
int i;
xprintf("Restore the NVRAM data: ");
xprintf("Restore the NVRAM data: ");
/* Request for NVRAM backup data */
write_pic_byte(0x01);
/* Request for NVRAM backup data */
write_pic_byte(0x01);
/* Check answer type */
if (read_pic_byte() != 0x81)
{
// FIXME: PIC protocol error
xprintf("FAILED\r\n");
return;
}
/* Check answer type */
if (read_pic_byte() != 0x81)
{
// FIXME: PIC protocol error
xprintf("FAILED\r\n");
return;
}
/* Restore the NVRAM backup to the FPGA */
for (i = 0; i < 64; i++)
{
uint8_t data = read_pic_byte();
*(volatile uint8_t*)0xffff8961 = i;
*(volatile uint8_t*)0xffff8963 = data;
}
/* Restore the NVRAM backup to the FPGA */
for (i = 0; i < 64; i++)
{
uint8_t data = read_pic_byte();
*(volatile uint8_t*)0xffff8961 = i;
*(volatile uint8_t*)0xffff8963 = data;
}
xprintf("finished\r\n");
xprintf("finished\r\n");
}
#define KBD_ACIA_CONTROL * ((uint8_t *) 0xfffffc00)
#define MIDI_ACIA_CONTROL * ((uint8_t *) 0xfffffc04)
#define MFP_INTR_IN_SERVICE_A * ((uint8_t *) 0xfffffa0f)
#define MFP_INTR_IN_SERVICE_B * ((uint8_t *) 0xfffffa11)
#define KBD_ACIA_CONTROL ((uint8_t *) 0xfffffc00)
#define MIDI_ACIA_CONTROL ((uint8_t *) 0xfffffc04)
#define MFP_INTR_IN_SERVICE_A ((uint8_t *) 0xfffffa0f)
#define MFP_INTR_IN_SERVICE_B ((uint8_t *) 0xfffffa11)
void acia_init()
{
xprintf("init ACIA: ");
/* init ACIA */
KBD_ACIA_CONTROL = 3; /* master reset */
NOP();
xprintf("init ACIA: ");
/* init ACIA */
* KBD_ACIA_CONTROL = 3; /* master reset */
NOP();
MIDI_ACIA_CONTROL = 3; /* master reset */
NOP();
* MIDI_ACIA_CONTROL = 3; /* master reset */
NOP();
KBD_ACIA_CONTROL = 0x96; /* clock div = 64, 8N1, RTS low, TX int disable, RX int enable */
NOP();
* KBD_ACIA_CONTROL = 0x96; /* clock div = 64, 8N1, RTS low, TX int disable, RX int enable */
NOP();
MFP_INTR_IN_SERVICE_A = 0xff;
NOP();
* MFP_INTR_IN_SERVICE_A = -1;
NOP();
MFP_INTR_IN_SERVICE_B = 0xff;
NOP();
* MFP_INTR_IN_SERVICE_B = -1;
NOP();
xprintf("finished\r\n");
xprintf("finished\r\n");
}
/* ACP interrupt controller */
#define FPGA_INTR_CONTRL (volatile uint32_t *) 0xf0010000
#define FPGA_INTR_ENABLE (volatile uint8_t *) 0xf0010004
#define FPGA_INTR_PENDIN (volatile uint32_t *) 0xf0010008
void enable_coldfire_interrupts()
{
xprintf("enable interrupts: ");
#if defined(MACHINE_FIREBEE)
FBEE_INTR_CONTROL = 0L; /* disable all interrupts */
xprintf("enable interrupts: ");
#if MACHINE_FIREBEE
*FPGA_INTR_CONTRL = 0L; /* disable all interrupts */
#endif /* MACHINE_FIREBEE */
MCF_EPORT_EPPAR = 0xaaa8; /* all interrupts on falling edge */
MCF_EPORT_EPPAR = 0xaaa8; /* all interrupts on falling edge */
#if MACHINE_FIREBEE
/*
* TIN0 on the Coldfire is connected to the FPGA. TIN0 triggers every write
* access to 0xff8201 (vbasehi), i.e. everytime the video base address is written
*/
MCF_GPT0_GMS = MCF_GPT_GMS_ICT(1) | /* timer 0 on, video change capture on rising edge */
MCF_GPT_GMS_IEN |
MCF_GPT_GMS_TMS(1);
/* route GPT0 interrupt on interrupt controller */
MCF_INTC_ICR62 = 0x3f; /* interrupt level 7, interrupt priority 7 */
#if defined(MACHINE_FIREBEE)
/*
* TIN0 on the Coldfire is connected to the FPGA. TIN0 triggers every write
* access to 0xff8201 (vbasehi), i.e. everytime the video base address is written
*/
MCF_GPT0_GMS = MCF_GPT_GMS_ICT(1) | /* timer 0 on, video change capture on rising edge */
MCF_GPT_GMS_IEN |
MCF_GPT_GMS_TMS(1); /* route GPT0 interrupt on interrupt controller */
MCF_INTC_ICR62 = MCF_INTC_ICR_IL(7) |
MCF_INTC_ICR_IP(6); /* interrupt level 7, interrupt priority 7 */
MCF_EPORT_EPIER = 0xfe; /* int 1-7 on */
MCF_EPORT_EPFR = 0xff; /* clear all pending interrupts */
MCF_INTC_IMRL = 0xffffff00; /* int 1-7 on */
//MCF_INTC_IMRH = 0xbffffffe; /* psc3 and timer 0 int on */
MCF_INTC_IMRH = 0;
FBEE_INTR_ENABLE = FBEE_INTR_INT_IRQ7 | /* enable pseudo bus error */
FBEE_INTR_INT_MFP_IRQ6 | /* enable MFP interrupts */
FBEE_INTR_INT_FPGA_IRQ5 | /* enable Firebee (PIC, PCI, ETH PHY, DVI, DSP) interrupts */
FBEE_INTR_INT_VSYNC_IRQ4 | /* enable vsync interrupts */
FBEE_INTR_PCI_INTA | /* enable PCI interrupts */
FBEE_INTR_PCI_INTB |
FBEE_INTR_PCI_INTC |
FBEE_INTR_PCI_INTD;
*FPGA_INTR_ENABLE = 0xfe; /* enable int 1-7 */
MCF_EPORT_EPIER = 0xfe; /* int 1-7 on */
MCF_EPORT_EPFR = 0xff; /* clear all pending interrupts */
MCF_INTC_IMRL = 0xffffff00; /* int 1-7 on */
MCF_INTC_IMRH = 0xbffffffe; /* psc3 and timer 0 int on */
#endif
xprintf("finished\r\n");
xprintf("finished\r\n");
}
void disable_coldfire_interrupts()
{
#if defined(MACHINE_FIREBEE)
FBEE_INTR_ENABLE = 0; /* disable all interrupts */
#ifdef MACHINE_FIREBEE
*FPGA_INTR_ENABLE = 0; /* disable all interrupts */
#endif /* MACHINE_FIREBEE */
MCF_EPORT_EPIER = 0x0;
MCF_INTC_IMRL = 0xfffffffe;
MCF_INTC_IMRH = 0xffffffff;
MCF_EPORT_EPIER = 0x0;
MCF_EPORT_EPFR = 0x0;
MCF_INTC_IMRL = 0xfffffffe;
MCF_INTC_IMRH = 0xffffffff;
}
NIF nif1;
#if defined(MACHINE_M5484LITE)
#ifdef MACHINE_M5484LITE
NIF nif2;
#endif
static IP_INFO ip_info;
static ARP_INFO arp_info;
/*
* initialize the interrupt handler tables to dispatch interrupt requests from Coldfire devices
*/
void init_isr(void)
void network_init(void)
{
isr_init(); /* need to call that explicitely, otherwise isr table might be full */
uint8_t mac[6] = {0x00, 0xcf, 0x54, 0x85, 0xcf, 0x01}; /* this is the original MAC address dbug assigns */
uint8_t bc[6] = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}; /* this is our broadcast MAC address */
IP_ADDR myip = {192, 168, 1, 100};
IP_ADDR gateway = {192, 168, 1, 1};
IP_ADDR netmask = {255, 255, 255, 0};
int vector;
int (*handler)(void *, void *);
/*
* register the FEC interrupt handler
*/
if (!isr_register_handler(64 + INT_SOURCE_FEC0, 5, 1, fec0_interrupt_handler, NULL, (void *) &nif1))
{
err("unable to register isr for FEC0\r\n");
}
handler = fec0_interrupt_handler;
vector = 103;
/*
* Register the DMA interrupt handler
*/
isr_init(); /* need to call that explicitely, otherwise isr table might be full */
if (!isr_register_handler(64 + INT_SOURCE_DMA, 5, 3, dma_interrupt_handler, NULL, NULL))
{
err("unable to register isr for DMA\r\n");
}
if (!isr_register_handler(vector, handler, NULL, (void *) &nif1))
{
dbg("%s: unable to register handler for vector %d\r\n", __FUNCTION__, vector);
return;
}
#ifdef MACHINE_FIREBEE
/*
* register GPT0 timer interrupt vector
*/
if (!isr_register_handler(64 + INT_SOURCE_GPT0, 5, 2, gpt0_interrupt_handler, NULL, NULL))
{
err("unable to register isr for GPT0 timer\r\n");
}
/*
* Register the DMA interrupt handler
*/
handler = dma_interrupt_handler;
vector = 112;
/*
* register the PIC interrupt handler
*/
if (!isr_register_handler(64 + INT_SOURCE_PSC3, 5, 5, pic_interrupt_handler, NULL, NULL))
{
err("Error: unable to register ISR for PSC3\r\n");
}
#endif /* MACHINE_FIREBEE */
if (!isr_register_handler(vector, handler, NULL,NULL))
{
dbg("%s: Error: Unable to register handler for vector %s\r\n", __FUNCTION__, vector);
return;
}
/*
* register the XLB PCI interrupt handler
*/
if (!isr_register_handler(64 + INT_SOURCE_XLBPCI, 7, 0, xlbpci_interrupt_handler, NULL, NULL))
{
err("Error: unable to register isr for XLB PCI interrupts\r\n");
}
nif_init(&nif1);
nif1.mtu = ETH_MTU;
nif1.send = fec0_send;
fec_eth_setup(0, FEC_MODE_MII, FEC_MII_100BASE_TX, FEC_MII_FULL_DUPLEX, mac);
// fec_eth_setup(1, FEC_MODE_MII, FEC_MII_100BASE_TX, FEC_MII_FULL_DUPLEX, mac);
memcpy(nif1.hwa, mac, 6);
memcpy(nif1.broadcast, bc, 6);
MCF_XLB_XARB_IMR = MCF_XLB_XARB_IMR_SEAE | /* slave error acknowledge interrupt */
MCF_XLB_XARB_IMR_MME | /* multiple master at prio 0 interrupt */
MCF_XLB_XARB_IMR_TTAE | /* TT address only interrupt */
MCF_XLB_XARB_IMR_TTRE | /* TT reserved interrupt enable */
MCF_XLB_XARB_IMR_ECWE | /* external control word interrupt */
MCF_XLB_XARB_IMR_TTME | /* TBST/TSIZ mismatch interrupt */
MCF_XLB_XARB_IMR_BAE; /* bus activity tenure timeout interrupt */
dbg("%s: ethernet address is %02X:%02X:%02X:%02X:%02X:%02X\r\n", __FUNCTION__,
nif1.hwa[0], nif1.hwa[1], nif1.hwa[2],
nif1.hwa[3], nif1.hwa[4], nif1.hwa[5]);
if (!isr_register_handler(64 + INT_SOURCE_PCIARB, 7, 1, pciarb_interrupt_handler, NULL, NULL))
{
err("Error: unable to register isr for PCIARB interrupts\r\n");
timer_init(TIMER_NETWORK, TMR_INTC_LVL, TMR_INTC_PRI);
return;
}
MCF_PCIARB_PACR = MCF_PCIARB_PACR_EXTMINTEN(0x1f) | /* external master broken interrupt */
MCF_PCIARB_PACR_INTMINTEN; /* internal master broken interrupt */
arp_init(&arp_info);
nif_bind_protocol(&nif1, ETH_FRM_ARP, arp_handler, (void *) &arp_info);
ip_init(&ip_info, myip, gateway, netmask);
nif_bind_protocol(&nif1, ETH_FRM_IP, ip_handler, (void *) &ip_info);
udp_init();
dma_irq_enable(6, 6);
set_ipl(0);
bootp_request(&nif1, 0);
fec_eth_stop(0);
}
void BaS(void)
{
uint8_t *src;
uint8_t *dst = (uint8_t *) TOS;
uint8_t *src;
uint8_t *dst = (uint8_t *) TOS;
#if defined(MACHINE_FIREBEE) /* LITE board has no pic and (currently) no nvram */
pic_init();
nvram_init();
#if MACHINE_FIREBEE /* LITE board has no pic and (currently) no nvram */
pic_init();
nvram_init();
#endif /* MACHINE_FIREBEE */
xprintf("initialize MMU: ");
mmu_init();
xprintf("finished\r\n");
xprintf("copy EmuTOS: ");
xprintf("copy EmuTOS: ");
/* copy EMUTOS */
src = (uint8_t *) EMUTOS;
dma_memcpy(dst, src, EMUTOS_SIZE);
xprintf("finished\r\n");
dma_init();
xprintf("initialize MMU: ");
mmu_init();
xprintf("finished\r\n");
/* copy EMUTOS */
src = (uint8_t *) EMUTOS;
dma_memcpy(dst, src, EMUTOS_SIZE);
xprintf("finished\r\n");
xprintf("initialize exception vector table: ");
vec_init();
xprintf("finished\r\n");
xprintf("initialize exception vector table: ");
vec_init();
xprintf("finished\r\n");
xprintf("flush caches: ");
flush_and_invalidate_caches();
xprintf("finished\r\n");
xprintf("enable MMU: ");
MCF_MMU_MMUCR = MCF_MMU_MMUCR_EN; /* MMU on */
NOP(); /* force pipeline sync */
xprintf("finished\r\n");
xprintf("flush caches: ");
flush_and_invalidate_caches();
xprintf("finished\r\n");
xprintf("enable MMU: ");
MCF_MMU_MMUCR = MCF_MMU_MMUCR_EN; /* MMU on */
NOP(); /* force pipeline sync */
xprintf("finished\r\n");
#ifdef MACHINE_FIREBEE
xprintf("IDE reset: ");
/* IDE reset */
* (volatile uint8_t *) (0xffff8802 - 2) = 14;
* (volatile uint8_t *) (0xffff8802 - 0) = 0x80;
wait(1);
#ifdef MACHINE_FIREBEE
xprintf("IDE reset: ");
/* IDE reset */
* (volatile uint8_t *) (0xffff8802 - 2) = 14;
* (volatile uint8_t *) (0xffff8802 - 0) = 0x80;
wait(1);
* (volatile uint8_t *) (0xffff8802 - 0) = 0;
* (volatile uint8_t *) (0xffff8802 - 0) = 0;
xprintf("finished\r\n");
xprintf("enable video: ");
/*
* video setup (25MHz)
*/
* (volatile uint32_t *) (0xf0000410 + 0) = 0x032002ba; /* horizontal 640x480 */
* (volatile uint32_t *) (0xf0000410 + 4) = 0x020c020a; /* vertical 640x480 */
* (volatile uint32_t *) (0xf0000410 + 8) = 0x0190015d; /* horizontal 320x240 */
* (volatile uint32_t *) (0xf0000410 + 12) = 0x020C020A; /* vertical 320x230 */
xprintf("finished\r\n");
xprintf("enable video: ");
/*
* video setup (25MHz)
*/
* (volatile uint32_t *) (0xf0000410 + 0) = 0x032002ba; /* horizontal 640x480 */
* (volatile uint32_t *) (0xf0000410 + 4) = 0x020c020a; /* vertical 640x480 */
* (volatile uint32_t *) (0xf0000410 + 8) = 0x0190015d; /* horizontal 320x240 */
* (volatile uint32_t *) (0xf0000410 + 12) = 0x020C020A; /* vertical 320x230 */
#ifdef _NOT_USED_
// 32MHz
* (volatile uint32_t *) (0xf0000410 + 0) = 0x037002ba; /* horizontal 640x480 */
* (volatile uint32_t *) (0xf0000410 + 4) = 0x020d020a; /* vertical 640x480 */
* (volatile uint32_t *) (0xf0000410 + 8) = 0x02a001e0; /* horizontal 320x240 */
* (volatile uint32_t *) (0xf0000410 + 12) = 0x05a00160; /* vertical 320x230 */
#endif /* _NOT_USED_ */
/* fifo on, refresh on, ddrcs and cke on, video dac on */
* (volatile uint32_t *) (0xf0000410 - 0x20) = 0x01070002;
/* fifo on, refresh on, ddrcs and cke on, video dac on */
* (volatile uint32_t *) (0xf0000410 - 0x20) = 0x01070002;
xprintf("finished\r\n");
enable_coldfire_interrupts();
#ifdef _NOT_USED_
screen_init();
/* experimental */
{
int i;
uint32_t *scradr = 0xd00000;
for (i = 0; i < 100; i++)
{
uint32_t *p = scradr;
for (p = scradr; p < scradr + 1024 * 150L; p++)
{
*p = 0xffffffff;
}
for (p = scradr; p < scradr + 1024 * 150L; p++)
{
*p = 0x0;
}
}
}
#endif /* _NOT_USED_ */
xprintf("finished\r\n");
#endif /* MACHINE_FIREBEE */
sd_card_init();
sd_card_init();
/*
* memory setup
*/
memset((void *) 0x400, 0, 0x400);
/*
* memory setup
*/
memset((void *) 0x400, 0, 0x400);
#if defined(MACHINE_FIREBEE)
/* set Falcon bus control register */
/* sets bit 3 and 6. Both are undefined on an original Falcon? */
#ifdef MACHINE_FIREBEE
/* set Falcon bus control register */
/* sets bit 3 and 6. Both are undefined on an original Falcon? */
* (volatile uint8_t *) 0xffff8007 = 0x48;
* (volatile uint8_t *) 0xffff8007 = 0x48;
#endif /* MACHINE_FIREBEE */
/* ST RAM */
/* ST RAM */
* (uint32_t *) 0x42e = STRAM_END; /* phystop TOS system variable */
* (uint32_t *) 0x420 = 0x752019f3; /* memvalid TOS system variable */
* (uint32_t *) 0x43a = 0x237698aa; /* memval2 TOS system variable */
* (uint32_t *) 0x51a = 0x5555aaaa; /* memval3 TOS system variable */
* (uint32_t *) 0x42e = STRAM_END; /* phystop TOS system variable */
* (uint32_t *) 0x420 = 0x752019f3; /* memvalid TOS system variable */
* (uint32_t *) 0x43a = 0x237698aa; /* memval2 TOS system variable */
* (uint32_t *) 0x51a = 0x5555aaaa; /* memval3 TOS system variable */
/* TT-RAM */
/* TT-RAM */
* (uint32_t *) 0x5a4 = FASTRAM_END; /* ramtop TOS system variable */
* (uint32_t *) 0x5a8 = 0x1357bd13; /* ramvalid TOS system variable */
* (uint32_t *) 0x5a4 = FASTRAM_END; /* ramtop TOS system variable */
* (uint32_t *) 0x5a8 = 0x1357bd13; /* ramvalid TOS system variable */
#if defined(MACHINE_FIREBEE) /* m5484lite has no ACIA and no dip switch... */
acia_init();
#ifdef MACHINE_FIREBEE /* m5484lite has no ACIA and no dip switch... */
acia_init();
#endif /* MACHINE_FIREBEE */
srec_execute("BASFLASH.S19");
srec_execute("BASFLASH.S19");
/* Jump into the OS */
typedef void void_func(void);
struct rom_header
{
void *initial_sp;
void_func *initial_pc;
};
/* Jump into the OS */
typedef void void_func(void);
struct rom_header
{
void *initial_sp;
void_func *initial_pc;
};
xprintf("BaS initialization finished, enable interrupts\r\n");
init_isr();
xprintf("BaS initialization finished, enable interrupts\r\n");
enable_coldfire_interrupts();
enable_coldfire_interrupts();
dma_irq_enable();
//set_ipl(0);
network_init();
init_pci();
// video_init();
/* initialize USB devices */
//init_usb();
set_ipl(7); /* disable interrupts */
xprintf("call EmuTOS\r\n");
struct rom_header *os_header = (struct rom_header *) TOS;
os_header->initial_pc();
xprintf("call EmuTOS\r\n");
struct rom_header *os_header = (struct rom_header *) TOS;
os_header->initial_pc();
}

200
sys/cache.c
View File

@@ -32,7 +32,7 @@ void cacr_set(uint32_t value)
__asm__ __volatile__("movec %0, cacr\n\t"
: /* output */
: "r" (rt_cacr)
: "memory" /* clobbers */);
: /* clobbers */);
}
uint32_t cacr_get(void)
@@ -42,43 +42,26 @@ uint32_t cacr_get(void)
return rt_cacr;
}
void disable_data_cache(void)
{
flush_and_invalidate_caches();
cacr_set((cacr_get() | CF_CACR_DCINVA) & ~CF_CACR_DEC);
}
void disable_instruction_cache(void)
{
flush_and_invalidate_caches();
cacr_set((cacr_get() | CF_CACR_ICINVA) & ~CF_CACR_IEC);
}
void enable_data_cache(void)
{
cacr_set(cacr_get() & ~CF_CACR_DCINVA);
}
void flush_and_invalidate_caches(void)
{
__asm__ __volatile__(
" clr.l d0 \n\t"
" clr.l d1 \n\t"
" move.l d0,a0 \n\t"
"cfa_setloop: \n\t"
" cpushl bc,(a0) | flush\n\t"
" lea 0x10(a0),a0 | index+1\n\t"
" addq.l #1,d1 | index+1\n\t"
" cmpi.w #512,d1 | all sets?\n\t"
" bne.s cfa_setloop | no->\n\t"
" clr.l d1 \n\t"
" addq.l #1,d0 \n\t"
" move.l d0,a0 \n\t"
" cmpi.w #4,d0 | all ways?\n\t"
" bne.s cfa_setloop | no->\n\t"
/* input */ :
/* output */ :
/* clobber */ : "cc", "d0", "d1", "a0"
__asm__ __volatile__(
" clr.l d0 \n\t"
" clr.l d1 \n\t"
" move.l d0,a0 \n\t"
"cfa_setloop: \n\t"
" cpushl bc,(a0) | flush\n\t"
" lea 0x10(a0),a0 | index+1\n\t"
" addq.l #1,d1 | index+1\n\t"
" cmpi.w #512,d1 | all sets?\n\t"
" bne.s cfa_setloop | no->\n\t"
" clr.l d1 \n\t"
" addq.l #1,d0 \n\t"
" move.l d0,a0 \n\t"
" cmpi.w #4,d0 | all ways?\n\t"
" bne.s cfa_setloop | no->\n\t"
/* input */ :
/* output */ :
/* clobber */ : "d0", "d1", "a0"
);
}
@@ -97,37 +80,36 @@ void flush_icache_range(void *address, size_t size)
if (start_set > end_set) {
/* from the begining to the lowest address */
for (set = 0; set <= end_set; set += (0x10 - 3))
{
__asm__ __volatile__(
" cpushl ic,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl ic,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl ic,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl ic,(%[set]) \n\t"
: /* output parameters */
: [set] "a" (set) /* input parameters */
: "cc" /* clobbered registers */
);
for (set = 0; set <= end_set; set += (0x10 - 3)) {
__asm__ __volatile__(
" cpushl ic,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl ic,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl ic,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl ic,(%[set]) \n\t"
: /* output parameters */
: [set] "a" (set) /* input parameters */
:
);
}
/* next loop will finish the cache ie pass the hole */
end_set = LAST_ICACHE_ADDR;
}
for (set = start_set; set <= end_set; set += (0x10 - 3)) {
__asm__ __volatile__(
" cpushl ic,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl ic,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl ic,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl ic,(%[set])"
: /* output parameters */
: [set] "a" (set)
: "cc"
);
__asm__ __volatile__(
" cpushl ic,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl ic,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl ic,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl ic,(%[set])"
: /* output parameters */
: [set] "a" (set)
:
);
}
}
@@ -149,91 +131,37 @@ void flush_dcache_range(void *address, size_t size)
if (start_set > end_set) {
/* from the begining to the lowest address */
for (set = 0; set <= end_set; set += (0x10 - 3))
{
__asm__ __volatile__(
" cpushl dc,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl dc,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl dc,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl dc,(%[set]) \n\t"
: /* output parameters */
: [set] "a" (set)
: "cc" /* clobbered registers */
);
for (set = 0; set <= end_set; set += (0x10 - 3))
{
__asm__ __volatile__(
" cpushl dc,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl dc,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl dc,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl dc,(%[set]) \n\t"
: /* output parameters */
: [set] "a" (set)
: /* clobbered registers */
);
}
/* next loop will finish the cache ie pass the hole */
end_set = LAST_DCACHE_ADDR;
}
for (set = start_set; set <= end_set; set += (0x10 - 3))
{
__asm__ __volatile__(
" cpushl dc,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl dc,(%[set]) \n\t"
" addq%.l #1,%[set] \n\t"
" cpushl dc,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl dc,(%[set]) \n\t"
: /* output parameters */
: [set] "a" (set)
: "cc" /* clobbered registers */
);
}
}
/*
* flush and invalidate a specific region from the both caches. We do not know if the area is cached
* at all, we do not know in which of the four ways it is cached, but we know the index where they
* would be cached if they are, so we only need to flush and invalidate only a subset of the 512 index
* entries, but all four ways.
*/
void flush_cache_range(void *address, size_t size)
{
unsigned long set;
unsigned long start_set;
unsigned long end_set;
void *endaddr;
endaddr = address + size;
start_set = (uint32_t) address & _DCACHE_SET_MASK;
end_set = (uint32_t) endaddr & _DCACHE_SET_MASK;
if (start_set > end_set) {
/* from the begining to the lowest address */
for (set = 0; set <= end_set; set += (0x10 - 3))
{
__asm__ __volatile__(
" cpushl bc,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl bc,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl bc,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl bc,(%[set]) \n\t"
: /* output parameters */
: [set] "a" (set)
: "cc" /* clobbered registers */
);
}
/* next loop will finish the cache ie pass the hole */
end_set = LAST_DCACHE_ADDR;
}
for (set = start_set; set <= end_set; set += (0x10 - 3))
{
__asm__ __volatile__(
" cpushl bc,(%[set]) \n\t"
" cpushl dc,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl bc,(%[set]) \n\t"
" cpushl dc,(%[set]) \n\t"
" addq%.l #1,%[set] \n\t"
" cpushl bc,(%[set]) \n\t"
" cpushl dc,(%[set]) \n\t"
" addq.l #1,%[set] \n\t"
" cpushl bc,(%[set]) \n\t"
" cpushl dc,(%[set]) \n\t"
: /* output parameters */
: [set] "a" (set)
: "cc" /* clobbered registers */
: /* clobbered registers */
);
}
}
}

481
sys/driver_mem.c
View File

@@ -2,7 +2,7 @@
* driver_mem.c
*
* based from Emutos / BDOS
*
*
* Copyright (c) 2001 Lineo, Inc.
*
* Authors: Karl T. Braun, Martin Doering, Laurent Vogel
@@ -11,7 +11,8 @@
* option any later version.
*/
#include <bas_types.h>
#include <stdint.h>
#include <stdbool.h>
#include "bas_string.h"
#include "bas_printf.h"
#include "usb.h"
@@ -28,6 +29,7 @@
#endif
//#define DBG_DM
#ifdef DBG_DM
#define dbg(fmt, args...) xprintf(fmt, ##args)
#else
@@ -44,10 +46,10 @@ extern uint8_t driver_mem_buffer[DRIVER_MEM_BUFFER_SIZE]; /* defined in linker c
MD
{
MD *m_link;
long m_start;
long m_length;
void *m_own;
MD *m_link;
long m_start;
long m_length;
void *m_own;
};
/* MPB - Memory Partition Block */
@@ -56,9 +58,9 @@ MD
MPB
{
MD *mp_mfl;
MD *mp_mal;
MD *mp_rover;
MD *mp_mfl;
MD *mp_mal;
MD *mp_rover;
};
#define MAXMD 256
@@ -68,273 +70,272 @@ static MPB pmd;
static void *xmgetblk(void)
{
int i;
for (i = 0; i < MAXMD; i++)
{
if (tab_md[i].m_own == NULL)
{
tab_md[i].m_own = (void*)1L;
return(&tab_md[i]);
}
}
return NULL;
int i;
for (i = 0; i < MAXMD; i++)
{
if (tab_md[i].m_own == NULL)
{
tab_md[i].m_own = (void*)1L;
return(&tab_md[i]);
}
}
return NULL;
}
static void xmfreblk(void *m)
{
int i = (int)(((long) m - (long) tab_md) / sizeof(MD));
if ((i > 0) && (i < MAXMD))
{
tab_md[i].m_own = NULL;
}
int i = (int)(((long) m - (long) tab_md) / sizeof(MD));
if ((i > 0) && (i < MAXMD))
{
tab_md[i].m_own = NULL;
}
}
static MD *ffit(long amount, MPB *mp)
{
MD *p, *q, *p1; /* free list is composed of MD's */
int maxflg;
long maxval;
if (amount != -1)
{
amount += 15; /* 16 bytes alignment */
amount &= 0xFFFFFFF0;
}
if ((q = mp->mp_rover) == 0) /* get rotating pointer */
{
return 0;
}
maxval = 0;
maxflg = ((amount == -1) ? true : false) ;
p = q->m_link; /* start with next MD */
do /* search the list for an MD with enough space */
{
if (p == 0)
{
/* at end of list, wrap back to start */
q = (MD *) &mp->mp_mfl; /* q => mfl field */
p = q->m_link; /* p => 1st MD */
}
if ((!maxflg) && (p->m_length >= amount))
{
/* big enough */
if (p->m_length == amount)
{
q->m_link = p->m_link; /* take the whole thing */
}
else
{
/*
* break it up - 1st allocate a new
* MD to describe the remainder
*/
p1 = xmgetblk();
if (p1 == NULL)
{
return(NULL);
}
/* init new MD */
p1->m_length = p->m_length - amount;
p1->m_start = p->m_start + amount;
p1->m_link = p->m_link;
p->m_length = amount; /* adjust allocated block */
q->m_link = p1;
}
/* link allocate block into allocated list,
mark owner of block, & adjust rover */
p->m_link = mp->mp_mal;
mp->mp_mal = p;
mp->mp_rover = (q == (MD *) &mp->mp_mfl ? q->m_link : q);
return(p); /* got some */
}
else if (p->m_length > maxval)
maxval = p->m_length;
p = ( q=p )->m_link;
} while(q != mp->mp_rover);
/*
* return either the max, or 0 (error)
*/
if (maxflg)
{
maxval -= 15; /* 16 bytes alignment */
if (maxval < 0)
{
maxval = 0;
}
else
{
maxval &= 0xFFFFFFF0;
}
}
return(maxflg ? (MD *) maxval : 0);
MD *p, *q, *p1; /* free list is composed of MD's */
int maxflg;
long maxval;
if (amount != -1)
{
amount += 15; /* 16 bytes alignment */
amount &= 0xFFFFFFF0;
}
if ((q = mp->mp_rover) == 0) /* get rotating pointer */
{
return 0;
}
maxval = 0;
maxflg = ((amount == -1) ? true : false) ;
p = q->m_link; /* start with next MD */
do /* search the list for an MD with enough space */
{
if (p == 0)
{
/* at end of list, wrap back to start */
q = (MD *) &mp->mp_mfl; /* q => mfl field */
p = q->m_link; /* p => 1st MD */
}
if ((!maxflg) && (p->m_length >= amount))
{
/* big enough */
if (p->m_length == amount)
{
q->m_link = p->m_link; /* take the whole thing */
}
else
{
/*
* break it up - 1st allocate a new
* MD to describe the remainder
*/
p1 = xmgetblk();
if (p1 == NULL)
{
return(NULL);
}
/* init new MD */
p1->m_length = p->m_length - amount;
p1->m_start = p->m_start + amount;
p1->m_link = p->m_link;
p->m_length = amount; /* adjust allocated block */
q->m_link = p1;
}
/* link allocate block into allocated list,
mark owner of block, & adjust rover */
p->m_link = mp->mp_mal;
mp->mp_mal = p;
mp->mp_rover = (q == (MD *) &mp->mp_mfl ? q->m_link : q);
return(p); /* got some */
}
else if (p->m_length > maxval)
maxval = p->m_length;
p = ( q=p )->m_link;
} while(q != mp->mp_rover);
/*
* return either the max, or 0 (error)
*/
if (maxflg)
{
maxval -= 15; /* 16 bytes alignment */
if (maxval < 0)
{
maxval = 0;
}
else
{
maxval &= 0xFFFFFFF0;
}
}
return(maxflg ? (MD *) maxval : 0);
}
static void freeit(MD *m, MPB *mp)
{
MD *p, *q;
q = 0;
for (p = mp->mp_mfl; p ; p = (q = p) -> m_link)
{
if (m->m_start <= p->m_start)
{
break;
}
}
m->m_link = p;
if (q)
{
q->m_link = m;
}
else
{
mp->mp_mfl = m;
}
if (!mp->mp_rover)
{
mp->mp_rover = m;
}
if (p)
{
if (m->m_start + m->m_length == p->m_start)
{
/* join to higher neighbor */
m->m_length += p->m_length;
m->m_link = p->m_link;
if (p == mp->mp_rover)
{
mp->mp_rover = m;
}
xmfreblk(p);
}
}
if (q)
{
if (q->m_start + q->m_length == m->m_start)
{
/* join to lower neighbor */
q->m_length += m->m_length;
q->m_link = m->m_link;
if (m == mp->mp_rover)
{
mp->mp_rover = q;
}
xmfreblk(m);
}
}
MD *p, *q;
q = 0;
for (p = mp->mp_mfl; p ; p = (q = p) -> m_link)
{
if (m->m_start <= p->m_start)
{
break;
}
}
m->m_link = p;
if (q)
{
q->m_link = m;
}
else
{
mp->mp_mfl = m;
}
if (!mp->mp_rover)
{
mp->mp_rover = m;
}
if (p)
{
if (m->m_start + m->m_length == p->m_start)
{
/* join to higher neighbor */
m->m_length += p->m_length;
m->m_link = p->m_link;
if (p == mp->mp_rover)
{
mp->mp_rover = m;
}
xmfreblk(p);
}
}
if (q)
{
if (q->m_start + q->m_length == m->m_start)
{
/* join to lower neighbor */
q->m_length += m->m_length;
q->m_link = m->m_link;
if (m == mp->mp_rover)
{
mp->mp_rover = q;
}
xmfreblk(m);
}
}
}
int32_t driver_mem_free(void *addr)
{
int level;
MD *p, **q;
MPB *mpb;
mpb = &pmd;
level = set_ipl(7);
for(p = *(q = &mpb->mp_mal); p; p = *(q = &p->m_link))
{
if ((long) addr == p->m_start)
{
break;
}
}
if (!p)
{
set_ipl(level);
return(-1);
}
*q = p->m_link;
freeit(p, mpb);
set_ipl(level);
dbg("%s: driver_mem_free(0x%08X)\r\n", __FUNCTION__, addr);
return(0);
int level;
MD *p, **q;
MPB *mpb;
mpb = &pmd;
level = set_ipl(7);
for(p = *(q = &mpb->mp_mal); p; p = *(q = &p->m_link))
{
if ((long) addr == p->m_start)
{
break;
}
}
if (!p)
{
set_ipl(level);
return(-1);
}
*q = p->m_link;
freeit(p, mpb);
set_ipl(level);
dbg("%s: driver_mem_free(0x%08X)\r\n", __FUNCTION__, addr);
return(0);
}
void *driver_mem_alloc(uint32_t amount)
{
void *ret = NULL;
int level;
MD *m;
if (amount == -1L)
{
return (void *) ffit(-1L, &pmd);
}
if (amount <= 0 )
{
return(0);
}
if ((amount & 1))
{
amount++;
}
level = set_ipl(7);
m = ffit(amount, &pmd);
if (m != NULL)
{
ret = (void *) m->m_start;
}
set_ipl(level);
dbg("%s: driver_mem_alloc(%d) = 0x%08X\r\n", __FUNCTION__, amount, ret);
return ret;
void *ret = NULL;
int level;
MD *m;
if (amount == -1L)
{
return((void *)ffit(-1L, &pmd));
}
if (amount <= 0 )
{
return(0);
}
if ((amount & 1))
{
amount++;
}
level = set_ipl(7);
m = ffit(amount, &pmd);
if (m != NULL)
{
ret = (void *)m->m_start;
}
set_ipl(level);
dbg("%s: driver_mem_alloc(%d) = 0x%08X\r\n", __FUNCTION__, amount, ret);
return(ret);
}
static int use_count = 0;
int driver_mem_init(void)
{
if (use_count == 0)
{
dbg("%s: initialise driver_mem_buffer[] at %p, size 0x%x\r\n", __FUNCTION__, driver_mem_buffer, DRIVER_MEM_BUFFER_SIZE);
memset(driver_mem_buffer, 0, DRIVER_MEM_BUFFER_SIZE);
if (use_count == 0)
{
dbg("%s: initialise driver_mem_buffer[] at %p, size 0x%x\r\n", __FUNCTION__, driver_mem_buffer, DRIVER_MEM_BUFFER_SIZE);
memset(driver_mem_buffer, 0, DRIVER_MEM_BUFFER_SIZE);
pmd.mp_mfl = pmd.mp_rover = &tab_md[0];
tab_md[0].m_link = (MD *) NULL;
tab_md[0].m_start = ((long) driver_mem_buffer + 15) & ~15;
tab_md[0].m_length = DRIVER_MEM_BUFFER_SIZE;
tab_md[0].m_own = (void *) 1L;
pmd.mp_mal = (MD *) NULL;
memset(driver_mem_buffer, 0, tab_md[0].m_length);
pmd.mp_mfl = pmd.mp_rover = &tab_md[0];
tab_md[0].m_link = (MD *) NULL;
tab_md[0].m_start = ((long) driver_mem_buffer + 15) & ~15;
tab_md[0].m_length = DRIVER_MEM_BUFFER_SIZE;
tab_md[0].m_own = (void *) 1L;
pmd.mp_mal = (MD *) NULL;
memset(driver_mem_buffer, 0, tab_md[0].m_length);
dbg("%s: uncached driver memory buffer at 0x%08X size %d\r\n", __FUNCTION__, tab_md[0].m_start, tab_md[0].m_length);
}
use_count++;
dbg("%s: driver_mem now has a use count of %d\r\n", __FUNCTION__, use_count);
return 0;
dbg("%s: uncached driver memory buffer at 0x%08X size %d\r\n", __FUNCTION__, tab_md[0].m_start, tab_md[0].m_length);
}
use_count++;
dbg("%s: driver_mem now has a use count of %d\r\n", __FUNCTION__, use_count);
return(0);
}
void driver_mem_release(void)
{
if (use_count-- == 0)
{
if (use_count-- == 0)
{
#ifndef CONFIG_USB_MEM_NO_CACHE
#ifdef USE_RADEON_MEMORY
if (driver_mem_buffer == (void *) offscren_reserved())
return;
if (driver_mem_buffer == (void *) offscren_reserved())
return;
#endif
#endif
}
dbg("%s: driver_mem use count now %d\r\n", __FUNCTION__, use_count);
}
dbg("%s: driver_mem use count now %d\r\n", __FUNCTION__, use_count);
}

1030
sys/exceptions.S
View File

File diff suppressed because it is too large Load Diff

310
sys/fault_vectors.c
View File

@@ -30,181 +30,169 @@ extern exception_handler SDRAM_VECTOR_TABLE[];
*/
void fault_handler(uint32_t pc, uint32_t format_status)
{
int format;
int fault_status;
int vector;
int sr;
int format;
int fault_status;
int vector;
int sr;
xprintf("\007\007exception! Processor halted.\r\n");
xprintf("format_status: %lx\r\n", format_status);
xprintf("pc: %lx\r\n", pc);
xprintf("\007\007exception! Processor halted.\r\n");
xprintf("format_status: %lx\r\n", format_status);
xprintf("pc: %lx\r\n", pc);
/*
* extract info from format-/status word
*/
format = (format_status & 0b11110000000000000000000000000000) >> 28;
fault_status = ((format_status & 0b00001100000000000000000000000000) >> 26) |
((format_status & 0b00000000000000110000000000000000) >> 16);
vector = (format_status & 0b00000011111111000000000000000000) >> 18;
sr = (format_status & 0b00000000000000001111111111111111);
/*
* extract info from format-/status word
*/
format = (format_status & 0b11110000000000000000000000000000) >> 28;
fault_status = ((format_status & 0b00001100000000000000000000000000) >> 26) |
((format_status & 0b00000000000000110000000000000000) >> 16);
vector = (format_status & 0b00000011111111000000000000000000) >> 18;
sr = (format_status & 0b00000000000000001111111111111111);
xprintf("format: %x\r\n", format);
xprintf("fault_status: %x (", fault_status);
switch (fault_status)
{
case 0:
xprintf("not an access or address error nor an interrupted debug service routine");
break;
case 1:
case 3:
case 11:
xprintf("reserved");
break;
case 2:
xprintf("interrupt during a debug service routine for faults other than access errors");
break;
case 4:
xprintf("error (for example, protection fault) on instruction fetch");
break;
case 5:
xprintf("TLB miss on opword or instruction fetch");
break;
case 6:
xprintf("TLB miss on extension word of instruction fetch");
break;
case 7:
xprintf("IFP access error while executing in emulator mode");
break;
case 8:
xprintf("error on data write");
break;
case 9:
xprintf("error on attempted write to write-protected space");
break;
case 10:
xprintf("TLB miss on data write");
break;
case 12:
xprintf("error on data read");
break;
case 13:
xprintf("attempted read, read-modify-write of protected space");
break;
case 14:
xprintf("TLB miss on data read or read-modify-write");
break;
case 15:
xprintf("OEP access error while executing in emulator mode");
}
xprintf(")\r\n");
xprintf("format: %x\r\n", format);
xprintf("fault_status: %x (", fault_status);
switch (fault_status)
{
case 0:
xprintf("not an access or address error nor an interrupted debug service routine");
break;
case 1:
case 3:
case 11:
xprintf("reserved");
break;
case 2:
xprintf("interrupt during a debug service routine for faults other than access errors");
break;
case 4:
xprintf("error (for example, protection fault) on instruction fetch");
break;
case 5:
xprintf("TLB miss on opword or instruction fetch");
break;
case 6:
xprintf("TLB miss on extension word of instruction fetch");
break;
case 7:
xprintf("IFP access error while executing in emulator mode");
break;
case 8:
xprintf("error on data write");
break;
case 9:
xprintf("error on attempted write to write-protected space");
break;
case 10:
xprintf("TLB miss on data write");
break;
case 12:
xprintf("error on data read");
break;
case 13:
xprintf("attempted read, read-modify-write of protected space");
break;
case 14:
xprintf("TLB miss on data read or read-modify-write");
break;
case 15:
xprintf("OEP access error while executing in emulator mode");
}
xprintf(")\r\n");
xprintf("vector = %02x (", vector);
switch (vector)
{
case 2:
xprintf("access error");
break;
case 3:
xprintf("address error");
break;
case 4:
xprintf("illegal instruction");
break;
case 5:
xprintf("divide by zero");
break;
case 8:
xprintf("privilege violation");
break;
case 9:
xprintf("trace");
break;
case 10:
xprintf("unimplemented line-a opcode");
break;
case 11:
xprintf("unimplemented line-f opcode");
break;
case 12:
xprintf("non-PC breakpoint debug interrupt");
break;
case 13:
xprintf("PC breakpoint debug interrupt");
break;
case 14:
xprintf("format error");
break;
case 24:
xprintf("spurious interrupt");
break;
default:
if ( ((vector >= 6) && (vector <= 7)) ||
((vector >= 16) && (vector <= 23)))
{
xprintf("reserved");
}
else if ((vector >= 25) && (vector <= 31))
{
xprintf("level %d autovectored interrupt", fault_status - 24);
}
else if ((vector >= 32) && (vector <= 47))
{
xprintf("trap #%d", vector - 32);
}
else
{
xprintf("unknown vector\r\n");
}
}
xprintf(")\r\n");
xprintf("sr=%4x\r\n", sr);
__asm__ __volatile__(
" move.w 0x2700,d0 \r\n" // disable interrupts
" move.w d0,sr \r\n"
" halt \r\n" // stop processor
: /* no output */
: /* no input */
: "memory");
xprintf("vector = %02x (", vector);
switch (vector)
{
case 2:
xprintf("access error");
break;
case 3:
xprintf("address error");
break;
case 4:
xprintf("illegal instruction");
break;
case 5:
xprintf("divide by zero");
break;
case 8:
xprintf("privilege violation");
break;
case 9:
xprintf("trace");
break;
case 10:
xprintf("unimplemented line-a opcode");
break;
case 11:
xprintf("unimplemented line-f opcode");
break;
case 12:
xprintf("non-PC breakpoint debug interrupt");
break;
case 13:
xprintf("PC breakpoint debug interrupt");
break;
case 14:
xprintf("format error");
break;
case 24:
xprintf("spurious interrupt");
break;
default:
if ( ((fault_status >= 6) && (fault_status <= 7)) ||
((fault_status >= 16) && (fault_status <= 23)))
{
xprintf("reserved");
}
else if ((fault_status >= 25) && (fault_status <= 31))
{
xprintf("level %d autovectored interrupt", fault_status - 24);
}
else if ((fault_status >= 32) && (fault_status <= 47))
{
xprintf("trap #%d", fault_status - 32);
}
else
{
xprintf("unknown fault status");
}
}
xprintf(")\r\n");
xprintf("sr=%4x\r\n", sr);
}
void __attribute__((interrupt)) handler(void)
{
/*
* Prepare exception stack contents so it can be handled by a C routine.
*
* For standard routines, we'd have to save registers here.
* Since we do not intend to return anyway, we just ignore that requirement.
*/
__asm__ __volatile__("move.l (sp),-(sp)\n\t"\
"move.l 8(sp),-(sp)\n\t"\
"bsr _fault_handler\n\t"\
"halt\n\t"\
: : : "memory");
/*
* Prepare exception stack contents so it can be handled by a C routine.
*
* For standard routines, we'd have to save registers here.
* Since we do not intend to return anyway, we just ignore that requirement.
*/
__asm__ __volatile__("move.l (sp),-(sp)\n\t"\
"move.l 8(sp),-(sp)\n\t"\
"bsr _fault_handler\n\t"\
"halt\n\t"\
: : : "memory");
}
void setup_vectors(void)
{
int i;
int i;
xprintf("\r\ninstall early exception vector table:");
xprintf("\r\ninstall early exception vector table:");
for (i = 8; i < 256; i++)
{
SDRAM_VECTOR_TABLE[i] = &handler;
}
for (i = 8; i < 256; i++)
{
SDRAM_VECTOR_TABLE[i] = &handler;
}
/*
* make sure VBR points to our table
*/
__asm__ __volatile__("clr.l d0\n\t"\
"movec.l d0,VBR\n\t"\
"nop\n\t"\
"move.l d0,_rt_vbr"
: /* outputs */
: /* inputs */
: "d0", "memory", "cc" /* clobbered registers */
);
/*
* make sure VBR points to our table
*/
__asm__ __volatile__("clr.l d0\n\t"\
"movec.l d0,VBR\n\t"\
"nop\n\t"\
"move.l d0,_rt_vbr" ::: "d0", "memory");
xprintf("finished.\r\n");
xprintf("finished.\r\n");
}

38
sys/init_fpga.c
View File

@@ -27,30 +27,23 @@
#include "bas_printf.h"
#include "wait.h"
// #define FPGA_DEBUG
#if defined(FPGA_DEBUG)
#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
#else
#define dbg(format, arg...) do { ; } while (0)
#endif
#define FPGA_STATUS (1 << 0)
#define FPGA_CLOCK (1 << 1)
#define FPGA_CONFIG (1 << 2)
#define FPGA_DATA0 (1 << 3)
#define FPGA_CONF_DONE (1 << 5)
#define FPGA_STATUS (1 << 0)
#define FPGA_CLOCK (1 << 1)
#define FPGA_CONFIG (1 << 2)
#define FPGA_DATA0 (1 << 3)
#define FPGA_CONF_DONE (1 << 5)
extern uint8_t _FPGA_CONFIG[];
#define FPGA_FLASH_DATA &_FPGA_CONFIG[0]
#define FPGA_FLASH_DATA &_FPGA_CONFIG[0]
extern uint8_t _FPGA_CONFIG_SIZE[];
#define FPGA_FLASH_DATA_SIZE ((uint32_t) &_FPGA_CONFIG_SIZE[0])
#define FPGA_FLASH_DATA_SIZE ((uint32_t) &_FPGA_CONFIG_SIZE[0])
/*
* flag located in processor SRAM1 that indicates that the FPGA configuration has
* been loaded through the onboard JTAG interface.
* init_fpga() will honour this and not overwrite config.
*/
extern bool _FPGA_JTAG_LOADED;
extern int32_t _FPGA_JTAG_LOADED;
extern int32_t _FPGA_JTAG_VALID;
#define VALID_JTAG 0xaffeaffe
@@ -61,7 +54,7 @@ void config_gpio_for_fpga_config(void)
* Configure GPIO FEC1L port directions (needed to load FPGA configuration)
*/
MCF_GPIO_PDDR_FEC1L = 0 | /* bit 7 = input */
0 | /* bit 6 = input */
0 | /* bit 6 = input */
0 | /* bit 5 = input */
MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4 | /* bit 4 = LED => output */
MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L3 | /* bit 3 = PRG_DQ0 => output */
@@ -77,10 +70,10 @@ void config_gpio_for_jtag_config(void)
* configure FEC1L port directions to enable external JTAG configuration download to FPGA
*/
MCF_GPIO_PDDR_FEC1L = 0 |
MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4; /* bit 4 = LED => output */
/* all other bits = input */
MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4; /* bit 4 = LED => output */
/* all other bits = input */
/*
* unfortunately, the GPIO module cannot trigger interrupts. That means CONF_DONE needs to be polled to detect
* unfortunately, the GPIO module cannot trigger interrupts. That means FPGA_CONFIG needs to be polled to detect
* external FPGA (re)configuration and reset the system in that case. Could be done from the OS as well...
*/
}
@@ -94,10 +87,11 @@ bool init_fpga(void)
volatile int32_t time, start, end;
int i;
dbg("FPGA load config\r\n(_FPGA_JTAG_LOADED = %x, _FPGA_JTAG_VALID = %x)...\r\n", _FPGA_JTAG_LOADED, _FPGA_JTAG_VALID);
if (_FPGA_JTAG_LOADED == true && _FPGA_JTAG_VALID == VALID_JTAG)
xprintf("FPGA load config...\r\n");
xprintf("_FPGA_JTAG_LOADED = %x, _FPGA_JTAG_VALID = %x)\r\n", _FPGA_JTAG_LOADED, _FPGA_JTAG_VALID);
if (_FPGA_JTAG_LOADED == 1 && _FPGA_JTAG_VALID == VALID_JTAG)
{
dbg("detected _FPGA_JTAG_LOADED flag. Not overwriting FPGA config.\r\n");
xprintf("detected _FPGA_JTAG_LOADED flag. Not overwriting FPGA config.\r\n");
/* reset the flag so that next boot will load config again from flash */
_FPGA_JTAG_LOADED = 0;

655
sys/interrupts.c
View File

@@ -3,7 +3,6 @@
*
* Handle interrupts, the levels.
*
*
* This file is part of BaS_gcc.
*
* BaS_gcc is free software: you can redistribute it and/or modify
@@ -23,356 +22,335 @@
* Author: Markus Fröschle
*/
#include <bas_types.h>
#include <stdint.h>
#include <stdbool.h>
#include "MCF5475.h"
#include "bas_utils.h"
#include "bas_printf.h"
#include "bas_string.h"
#include "exceptions.h"
#include "interrupts.h"
#include "bas_printf.h"
#include "startcf.h"
#include "cache.h"
#include "util.h"
#include "dma.h"
#include "pci.h"
//#define IRQ_DEBUG
extern void (*rt_vbr[])(void);
#define VBR rt_vbr
#define IRQ_DEBUG
#if defined(IRQ_DEBUG)
#define dbg(format, arg...) do { xprintf("DEBUG %s(): " format, __FUNCTION__, ##arg); } while (0)
#else
#define dbg(format, arg...) do { ; } while (0)
#endif
#define err(format, arg...) do { xprintf("DEBUG %s(): " format, __FUNCTION__, ##arg); } while (0)
/*
* register an interrupt handler at the Coldfire interrupt controller and add the handler to
* the interrupt vector table
*/
int register_interrupt_handler(uint8_t source, uint8_t level, uint8_t priority, uint8_t intr, void (*handler)(void))
{
int ipl;
int i;
volatile uint8_t *ICR = &MCF_INTC_ICR01 - 1;
uint8_t lp;
source &= 63;
priority &= 7;
if (source < 1 || source > 63)
{
dbg("interrupt source %d not defined\r\n", source);
return -1;
}
lp = MCF_INTC_ICR_IL(level) | MCF_INTC_ICR_IP(priority);
/* check if this combination is already set somewhere */
for (i = 1; i < 64; i++)
{
if (ICR[i] == lp)
{
dbg("level %d and priority %d already used for interrupt source %d!\r\n",
level, priority, i);
return -1;
}
}
/* disable interrupts */
ipl = set_ipl(7);
VBR[64 + source] = handler; /* first 64 vectors are system exceptions */
/* set level and priority in interrupt controller */
ICR[source] = lp;
/* set interrupt mask to where it was before */
set_ipl(ipl);
return 0;
}
#ifndef MAX_ISR_ENTRY
#define MAX_ISR_ENTRY (20)
#endif
struct isrentry
typedef struct
{
int vector;
bool (*handler)(void *, void *);
void *hdev;
void *harg;
};
int vector;
int (*handler)(void *, void *);
void *hdev;
void *harg;
} ISRENTRY;
ISRENTRY isrtab[MAX_ISR_ENTRY];
static struct isrentry isrtab[MAX_ISR_ENTRY]; /* list of interrupt service routines */
/*
* clear the table of interrupt service handlers
*/
void isr_init(void)
{
memset(isrtab, 0, sizeof(isrtab));
int index;
for (index = 0; index < MAX_ISR_ENTRY; index++)
{
isrtab[index].vector = 0;
isrtab[index].handler = 0;
isrtab[index].hdev = 0;
isrtab[index].harg = 0;
}
}
bool isr_set_prio_and_level(int int_source, int priority, int level)
int isr_register_handler(int vector, int (*handler)(void *, void *), void *hdev, void *harg)
{
if (int_source > 8 && int_source <= 62)
{
/*
* preset interrupt control registers with level and priority
*/
dbg("set MCF_INTC_ICR(%d) to priority %d, level %d\r\n",
int_source, priority, level);
MCF_INTC_ICR(int_source) = MCF_INTC_ICR_IP(priority) |
MCF_INTC_ICR_IL(level);
}
else if (int_source >= 1 && int_source <= 8)
{
dbg("interrrupt control register for vector %d is read only!\r\n");
}
else
{
err("invalid vector - interrupt control register not set.\r\n");
return false;
}
/*
* This function places an interrupt handler in the ISR table,
* thereby registering it so that the low-level handler may call it.
*
* The two parameters are intended for the first arg to be a
* pointer to the device itself, and the second a pointer to a data
* structure used by the device driver for that particular device.
*/
int index;
return true;
if ((vector == 0) || (handler == NULL))
{
dbg("illegal vector or handler!\r\n");
return false;
}
for (index = 0; index < MAX_ISR_ENTRY; index++)
{
if (isrtab[index].vector == vector)
{
/* one cross each, only! */
dbg("already set handler with this vector (%d, %d)\r\n", vector);
return false;
}
if (isrtab[index].vector == 0)
{
isrtab[index].vector = vector;
isrtab[index].handler = handler;
isrtab[index].hdev = hdev;
isrtab[index].harg = harg;
return true;
}
}
dbg("no available slots to register handler for vector %d\n\r", vector);
return false; /* no available slots */
}
/*
* enable internal int source in interrupt controller
*/
bool isr_enable_int_source(int int_source)
void isr_remove_handler(int (*handler)(void *, void *))
{
dbg("anding int_source %d, MCF_INTC_IMR%c = 0x%08x, now 0x%08x\r\n",
int_source,
int_source < 32 && int_source > 0 ? 'L' :
int_source >= 32 && int_source <= 62 ? 'H' : 'U',
int_source < 32 && int_source > 0 ? ~(1 << int_source) :
int_source >= 32 && int_source <= 62 ? ~(1 << (int_source - 32)) : 0,
MCF_INTC_IMRH);
/*
* This routine removes from the ISR table all
* entries that matches 'handler'.
*/
int index;
if (int_source < 32 && int_source > 0)
{
MCF_INTC_IMRL &= ~(1 << int_source);
}
else if (int_source >= 32 && int_source <= 62)
{
MCF_INTC_IMRH &= ~(1 << (int_source - 32));
}
else
{
err("vector %d does not correspond to an internal interrupt source\r\n");
return false;
}
for (index = 0; index < MAX_ISR_ENTRY; index++)
{
if (isrtab[index].handler == handler)
{
isrtab[index].vector = 0;
isrtab[index].handler = 0;
isrtab[index].hdev = 0;
isrtab[index].harg = 0;
return true;
return;
}
}
dbg("no such handler registered (handler=%p\r\n", handler);
}
/*
* This function places an interrupt handler in the ISR table,
* thereby registering it so that the low-level handler may call it.
*
* The two parameters are intended for the first arg to be a
* pointer to the device itself, and the second a pointer to a data
* structure used by the device driver for that particular device.
*/
bool isr_register_handler(int vector, int level, int priority, bool (*handler)(void *, void *), void *hdev, void *harg)
{
int index;
int int_source;
if ((vector == 0) || (handler == NULL))
{
dbg("illegal vector or handler!\r\n");
return false;
}
for (index = 0; index < MAX_ISR_ENTRY; index++)
{
if (isrtab[index].vector == vector)
{
/* one cross each, only! */
dbg("already set handler with this vector (%d, %d)\r\n", vector);
return false;
}
if (isrtab[index].vector == 0)
{
isrtab[index].vector = vector;
isrtab[index].handler = handler;
isrtab[index].hdev = hdev;
isrtab[index].harg = harg;
int_source = vector - 64;
if (!isr_enable_int_source(int_source))
{
err("failed to enable internal interrupt souce %d in IMRL/IMRH\r\n", int_source);
return false;
}
if (!isr_set_prio_and_level(int_source, priority, level))
{
err("failed to set priority and level for interrupt source %d\r\n", int_source);
return false;
}
return true;
}
}
dbg("no available slots to register handler for vector %d\n\r", vector);
return false; /* no available slots */
}
void isr_remove_handler(bool (*handler)(void *, void *))
{
/*
* This routine removes from the ISR table all
* entries that matches 'handler'.
*/
int index;
for (index = 0; index < MAX_ISR_ENTRY; index++)
{
if (isrtab[index].handler == handler)
{
memset(&isrtab[index], 0, sizeof(struct isrentry));
return;
}
}
dbg("no such handler registered (handler=%p\r\n", handler);
}
/*
* This routine searches the ISR table for an entry that matches
* 'vector'. If one is found, then 'handler' is executed.
*
* This routine returns either true or false where
* true = interrupt has been handled, return to caller
* false= interrupt has been handled or hasn't, but needs to be forwarded to TOS
*/
bool isr_execute_handler(int vector)
{
int index;
/*
* This routine searches the ISR table for an entry that matches
* 'vector'. If one is found, then 'handler' is executed.
*/
int index;
bool retval = false;
dbg("vector = %d\r\n", vector);
/*
* locate a BaS Interrupt Service Routine handler.
*/
for (index = 0; index < MAX_ISR_ENTRY; index++)
{
if (isrtab[index].vector == vector)
{
retval = true;
/*
* locate an interrupt service routine handler.
*/
for (index = 0; index < MAX_ISR_ENTRY; index++)
{
if (isrtab[index].vector == vector)
{
isrtab[index].handler(isrtab[index].hdev, isrtab[index].harg);
return true;
}
}
err("no isr handler for vector %d found. Spurious?\r\n", vector);
if (isrtab[index].handler(isrtab[index].hdev, isrtab[index].harg))
{
return retval;
}
}
}
dbg("no BaS isr handler for vector %d found\r\n", vector);
return true;
return retval;
}
/*
* PIC interrupt handler for Firebee
*
* Handles PIC requests that come in from PSC3 serial interface. Currently, that
* is RTC/NVRAM requests only
*/
bool pic_interrupt_handler(void *arg1, void *arg2)
void pic_interrupt_handler(void)
{
uint8_t rcv_byte;
uint8_t rcv_byte;
rcv_byte = MCF_PSC3_PSCRB_8BIT;
if (rcv_byte == 2) /* PIC requests RTC data */
{
uint8_t *rtc_reg = (uint8_t *) 0xffff8961;
uint8_t *rtc_data = (uint8_t *) 0xffff8963;
int index = 0;
rcv_byte = MCF_PSC3_PSCRB_8BIT;
if (rcv_byte == 2) // PIC requests RTC data
{
uint8_t *rtc_reg= (uint8_t *) 0xffff8961;
uint8_t *rtc_data = (uint8_t *) 0xffff8963;
int index = 0;
err("PIC interrupt: requesting RTC data\r\n");
xprintf("PIC interrupt requesting RTC data\r\n");
MCF_PSC3_PSCTB_8BIT = 0x82; // header byte to PIC
do
{
*rtc_reg = 0;
MCF_PSC3_PSCTB_8BIT = *rtc_data;
} while (index++ < 64);
}
return true;
MCF_PSC3_PSCTB_8BIT = 0x82; // header byte to PIC
do
{
*rtc_reg = 0;
MCF_PSC3_PSCTB_8BIT = *rtc_data;
} while (index++ < 64);
}
}
bool xlbpci_interrupt_handler(void *arg1, void *arg2)
extern int32_t video_sbt;
extern int32_t video_tlb;
void video_addr_timeout(void)
{
uint32_t reason;
uint32_t addr = 0x0L;
uint32_t *src;
uint32_t *dst;
uint32_t asid;
dbg("XLB PCI interrupt\r\n");
dbg("video address timeout\r\n");
flush_and_invalidate_caches();
reason = MCF_PCI_PCIISR;
do
{
uint32_t tlb;
uint32_t page_attr;
if (reason & MCF_PCI_PCIISR_RE)
{
dbg("Retry error. Retry terminated or max retries reached. Cleared\r\n");
MCF_PCI_PCIISR |= MCF_PCI_PCIISR_RE;
}
/*
* search tlb entry id for addr (if not available, the MMU
* will provide a new one based on its LRU algorithm)
*/
MCF_MMU_MMUAR = addr;
MCF_MMU_MMUOR =
MCF_MMU_MMUOR_STLB |
MCF_MMU_MMUOR_RW |
MCF_MMU_MMUOR_ACC;
NOP();
tlb = (MCF_MMU_MMUOR >> 16) & 0xffff;
if (reason & MCF_PCI_PCIISR_IA)
{
dbg("Initiator abort. No target answered in time. Cleared.\r\n");
MCF_PCI_PCIISR |= MCF_PCI_PCIISR_IA;
}
/*
* retrieve tlb entry with the found TLB entry id
*/
MCF_MMU_MMUAR = tlb;
MCF_MMU_MMUOR =
MCF_MMU_MMUOR_STLB |
MCF_MMU_MMUOR_ADR |
MCF_MMU_MMUOR_RW |
MCF_MMU_MMUOR_ACC;
NOP();
if (reason & MCF_PCI_PCIISR_TA)
{
dbg("Target abort. Cleared.\r\n");
MCF_PCI_PCIISR |= MCF_PCI_PCIISR_TA;
}
asid = (MCF_MMU_MMUTR >> 2) & 0x1fff; /* fetch ASID of page */;
if (asid != sca_page_ID) /* check if screen area */
{
addr += 0x100000;
continue; /* next page */
}
return true;
/* modify found TLB entry */
if (addr == 0x0)
{
page_attr =
MCF_MMU_MMUDR_LK |
MCF_MMU_MMUDR_SZ(0) |
MCF_MMU_MMUDR_CM(0) |
MCF_MMU_MMUDR_R |
MCF_MMU_MMUDR_W |
MCF_MMU_MMUDR_X;
}
else
{
page_attr =
MCF_MMU_MMUTR_SG |
MCF_MMU_MMUTR_V;
}
MCF_MMU_MMUTR = addr;
MCF_MMU_MMUDR = page_attr;
MCF_MMU_MMUOR =
MCF_MMU_MMUOR_STLB |
MCF_MMU_MMUOR_ADR |
MCF_MMU_MMUOR_ACC |
MCF_MMU_MMUOR_UAA;
NOP();
dst = (uint32_t *) 0x60000000 + addr;
src = (uint32_t *) addr;
while (dst < (uint32_t *) 0x60000000 + addr + 0x10000)
{
*dst++ = *src++;
*dst++ = *src++;
*dst++ = *src++;
*dst++ = *src++;
}
addr += 0x100000;
} while (addr < 0xd00000);
video_tlb = 0x2000;
video_sbt = 0;
}
bool pciarb_interrupt_handler(void *arg1, void *arg2)
{
dbg("PCI ARB interrupt\r\n");
return true;
}
#if defined(MACHINE_FIREBEE)
/*
* This gets called from irq5 in exceptions.S
*
* IRQ5 are the "FBEE" (PIC, ETH PHY, PCI, DVI monitor sense and DSP) interrupts multiplexed by the FPGA interrupt handler
*/
bool irq5_handler(void *arg1, void *arg2)
{
uint32_t pending_interrupts = FBEE_INTR_PENDING;
dbg("IRQ5!\r\n");
if (pending_interrupts & FBEE_INTR_PIC)
{
dbg("PIC interrupt\r\n");
FBEE_INTR_CLEAR = FBEE_INTR_PIC;
}
if (pending_interrupts & FBEE_INTR_ETHERNET)
{
dbg("ethernet 0 PHY interrupt\r\n");
FBEE_INTR_CLEAR = FBEE_INTR_ETHERNET;
}
if (pending_interrupts & FBEE_INTR_DVI)
{
dbg("DVI monitor sense interrupt\r\n");
FBEE_INTR_CLEAR = FBEE_INTR_DVI;
}
if (pending_interrupts & FBEE_INTR_PCI_INTA ||
pending_interrupts & FBEE_INTR_PCI_INTB ||
pending_interrupts & FBEE_INTR_PCI_INTC ||
pending_interrupts & FBEE_INTR_PCI_INTD)
{
dbg("PCI interrupt IRQ5\r\n");
FBEE_INTR_CLEAR = FBEE_INTR_PCI_INTA |
FBEE_INTR_PCI_INTB |
FBEE_INTR_PCI_INTC |
FBEE_INTR_PCI_INTD;
}
if (pending_interrupts & FBEE_INTR_DSP)
{
dbg("DSP interrupt\r\n");
FBEE_INTR_CLEAR = FBEE_INTR_DSP;
}
if (pending_interrupts & FBEE_INTR_VSYNC || pending_interrupts & FBEE_INTR_HSYNC)
{
dbg("vsync or hsync interrupt!\r\n");
FBEE_INTR_CLEAR = FBEE_INTR_VSYNC | FBEE_INTR_HSYNC;
/* hsync and vsync should go to TOS unhandled */
return false;
}
MCF_EPORT_EPFR |= (1 << 5); /* clear interrupt from edge port */
return true;
}
/*
* blink the Firebee's LED to show we are still alive
*/
void blink_led(void)
{
static uint16_t blinker = 0;
static uint16_t blinker = 0;
if ((blinker++ & 0x80) > 0)
{
MCF_GPIO_PODR_FEC1L |= (1 << 4); /* LED off */
}
else
{
MCF_GPIO_PODR_FEC1L &= ~(1 << 4); /* LED on */
}
if ((blinker++ & 0x80) > 0)
{
MCF_GPIO_PODR_FEC1L |= (1 << 4); /* LED off */
}
else
{
MCF_GPIO_PODR_FEC1L &= ~(1 << 4); /* LED on */
}
}
/*
@@ -390,96 +368,45 @@ void blink_led(void)
bool irq6_acsi_dma_interrupt(void)
{
dbg("ACSI DMA interrupt\r\n");
dbg("ACSI DMA interrupt\r\n");
/*
* TODO: implement handler
*/
/*
* TODO: implement handler
*/
return false;
return false;
}
bool irq6_handler(uint32_t sf1, uint32_t sf2)
bool irq6_interrupt_handler(uint32_t sf1, uint32_t sf2)
{
//err("IRQ6!\r\n");
bool handled = false;
if (FALCON_MFP_IPRA || FALCON_MFP_IPRB)
{
blink_led();
}
MCF_EPORT_EPFR |= (1 << 6); /* clear int6 from edge port */
MCF_EPORT_EPFR |= (1 << 6); /* clear int6 from edge port */
if (video_sbt != 0 && (video_sbt - 0x70000000) > MCF_SLT0_SCNT)
{
video_addr_timeout();
handled = true;
}
return false; /* always forward IRQ6 to TOS */
/*
* check if ACSI DMA interrupt
*/
if (FALCON_MFP_IERA & (1 << 7))
{
/* ACSI interrupt is enabled */
if (FALCON_MFP_IPRA & (1 << 7))
{
irq6_acsi_dma_interrupt();
handled = true;
}
}
if (FALCON_MFP_IPRA || FALCON_MFP_IPRB)
{
blink_led();
}
return handled;
}
#else /* MACHINE_FIREBEE */
bool irq5_handler(void *arg1, void *arg2)
{
MCF_EPORT_EPFR |= (1 << 5); /* clear int5 from edge port */
return true;
}
bool irq6_handler(void *arg1, void *arg2)
{
err("IRQ6!\r\n");
MCF_EPORT_EPFR |= (1 << 6); /* clear int6 from edge port */
return false; /* always forward IRQ6 to TOS */
}
/*
* This gets called from irq7 in exceptions.S
* Once we arrive here, the SR has been set to disable interrupts and the gcc scratch registers have been saved
*/
bool irq7_handler(void)
{
int32_t handle;
int32_t value = 0;
int32_t newvalue;
MCF_EPORT_EPFR |= (1 << 7);
dbg("IRQ7!\r\n");
if ((handle = pci_get_interrupt_cause()) > 0)
{
newvalue = pci_call_interrupt_chain(handle, value);
if (newvalue == value)
{
dbg("interrupt not handled!\r\n");
}
}
MCF_EPORT_EPFR |= (1 << 7); /* clear int7 from edge port */
return true;
}
#endif /* MACHINE_M548X */
#if defined(MACHINE_FIREBEE)
/*
* this is the higlevel interrupt service routine for gpt0 timer interrupts.
*
* It is called from handler_gpt0 in exceptions.S
*
* The gpt0 timer is not used as a timer, but as interrupt trigger by the FPGA which fires
* everytime the video base address high byte (0xffff8201) gets written by user code (i.e.
* everytime the video base address is set).
* The interrupt service routine checks if that page was already set as a video page (in that
* case it does nothing), if not (if we have a newly set page), it sets up an MMU mapping for
* that page (effectively rerouting any further access to Falcon video RAM to Firebee FPGA
* video RAM starting at 0x60000000) and copies SDRAM contents of that page to the video
* RAM page.
*/
bool gpt0_interrupt_handler(void *arg0, void *arg1)
{
dbg("handler called\n\r");
MCF_GPT0_GMS &= ~1; /* rearm trigger */
NOP();
MCF_GPT0_GMS |= 1;
return true;
}
#endif /* MACHINE_FIREBEE */

1095
sys/mmu.c
View File

File diff suppressed because it is too large Load Diff

25
sys/sysinit.c
View File

@@ -267,8 +267,7 @@ void init_serial(void)
MCF_PSC3_PSCCR = 0x05;
#endif /* MACHINE_FIREBEE */
MCF_INTC_ICR32 = MCF_INTC_ICR_IL(7) |
MCF_INTC_ICR_IL(4); /* PSC3 interrupt vector. Do we need it? */
MCF_INTC_ICR32 = 0x3F; /* PSC3 interrupt vector. Do we need it? */
xprintf("\r\nserial interfaces initialization: finished\r\n");
}
@@ -560,7 +559,6 @@ void init_video_ddr(void) {
_VRAM = 0x00060000; /* auto refresh */
NOP();
/* FIXME: what's this? */
_VRAM = 0000070022; /* load MR dll on */
NOP();
@@ -647,7 +645,7 @@ static bool i2c_transfer_finished(void)
static void wait_i2c_transfer_finished(void)
{
waitfor(1000, i2c_transfer_finished); /* wait until interrupt bit has been set */
waitfor(10000, i2c_transfer_finished); /* wait until interrupt bit has been set */
MCF_I2C_I2SR &= ~MCF_I2C_I2SR_IIF; /* clear interrupt bit (byte transfer finished */
}
@@ -662,7 +660,7 @@ static bool i2c_bus_free(void)
void dvi_on(void)
{
uint8_t receivedByte;
uint8_t dummyByte; /* only used for a dummy read */
uint8_t dummyByte; /* only used for a dummy read */
int num_tries = 0;
xprintf("DVI digital video output initialization: ");
@@ -680,12 +678,11 @@ void dvi_on(void)
/* repeat start, transmit acknowledge */
MCF_I2C_I2CR = MCF_I2C_I2CR_RSTA | MCF_I2C_I2CR_TXAK;
receivedByte = MCF_I2C_I2DR; /* read a byte */
MCF_I2C_I2SR = 0x0; /* clear status register */
MCF_I2C_I2CR = 0x0; /* clear control register */
MCF_I2C_I2ICR = MCF_I2C_I2ICR_IE; /* route i2c interrupts to cpu */
receivedByte = MCF_I2C_I2DR; /* read a byte */
MCF_I2C_I2SR = 0x0; /* clear status register */
MCF_I2C_I2CR = 0x0; /* disable i2c */
MCF_I2C_I2ICR = MCF_I2C_I2ICR_IE; /* route i2c interrupts to cpu */
/* i2c enable, master mode, transmit acknowledge */
MCF_I2C_I2CR = MCF_I2C_I2CR_IEN | MCF_I2C_I2CR_MSTA | MCF_I2C_I2CR_MTX;
@@ -1114,10 +1111,18 @@ void initialize_hardware(void)
#endif /* MACHINE_FIREBEE */
driver_mem_init();
init_pci();
video_init();
/* do not try to init USB for now on the Firebee, it hangs the machine */
#ifndef MACHINE_FIREBEE
//init_usb();
#endif
#if MACHINE_FIREBEE
init_ac97();
#endif /* MACHINE_FIREBEE */
dma_init();
/* jump into the BaS */
extern void BaS(void);

15
tos/Makefile
View File

@@ -1,15 +0,0 @@
.PHONY: tos
.PHONY: jtagwait
.PHONY: bascook
.PHONY: vmem_test
tos: jtagwait bascook vmem_test
jtagwait:
(cd $@; make)
bascook:
(cd $@; make)
vmem_test:
(cd $@; make)

97
tos/bascook/Makefile
View File

@@ -1,97 +0,0 @@
CROSS=Y
CROSSBINDIR_IS_Y=m68k-atari-mint-
CROSSBINDIR_IS_N=
CROSSBINDIR=$(CROSSBINDIR_IS_$(CROSS))
UNAME := $(shell uname)
ifeq ($(CROSS), Y)
ifeq ($(UNAME),Linux)
PREFIX=m68k-atari-mint
HATARI=hatari
else
PREFIX=m68k-atari-mint
HATARI=/usr/local/bin/hatari
endif
else
PREFIX=/usr
endif
DEPEND=depend
TOPDIR= ../..
BAS_INCLUDE=-I$(TOPDIR)/../BaS_gcc/include
INCLUDE=-I$(TOPDIR)/../libcmini/include $(BAS_INCLUDE) -nostdlib
LIBS=-lcmini -nostdlib -lgcc
CC=$(PREFIX)/bin/gcc
CC=$(CROSSBINDIR)gcc
STRIP=$(CROSSBINDIR)strip
STACK=$(CROSSBINDIR)stack
APP=bascook.prg
TEST_APP=$(APP)
CFLAGS=\
-Os\
-g\
-Wl,-Map,mapfile\
-Wall
SRCDIR=sources
CSRCS=\
$(SRCDIR)/bascook.c
ASRCS=
COBJS=$(patsubst $(SRCDIR)/%.o,%.o,$(patsubst %.c,%.o,$(CSRCS)))
AOBJS=$(patsubst $(SRCDIR)/%.o,%.o,$(patsubst %.S,%.o,$(ASRCS)))
OBJS=$(COBJS) $(AOBJS)
TRGTDIRS=.
OBJDIRS=$(patsubst %,%/objs,$(TRGTDIRS))
#
# multilib flags. These must match m68k-atari-mint-gcc -print-multi-lib output
#
$(APP):CFLAGS += -mcpu=5475
all: $(TEST_APP)
#
# generate pattern rules for multilib object files.
#
define CC_TEMPLATE
$(1)/objs/%.o:$(SRCDIR)/%.c
$(CC) $$(CFLAGS) $(INCLUDE) -c $$< -o $$@
$(1)/objs/%.o:$(SRCDIR)/%.S
$(CC) $$(CFLAGS) $(INCLUDE) -c $$< -o $$@
$(1)_OBJS=$(patsubst %,$(1)/objs/%,$(OBJS))
$(1)/$(APP): $$($(1)_OBJS)
$(CC) $$(CFLAGS) -o $$@ $(TOPDIR)/../libcmini/m5475/startup.o $$($(1)_OBJS) -L$(TOPDIR)/../libcmini/m5475 $(LIBS)
$(STRIP) $$@
endef
$(foreach DIR,$(TRGTDIRS),$(eval $(call CC_TEMPLATE,$(DIR))))
$(DEPEND): $(ASRCS) $(CSRCS)
-rm -f $(DEPEND)
for d in $(TRGTDIRS);\
do $(CC) $(CFLAGS) $(INCLUDE) -M $(ASRCS) $(CSRCS) | sed -e "s#^\(.*\).o:#$$d/objs/\1.o:#" >> $(DEPEND); \
done
clean:
@rm -f $(patsubst %,%/objs/*.o,$(TRGTDIRS)) $(patsubst %,%/$(APP),$(TRGTDIRS))
@rm -f $(DEPEND) mapfile
.PHONY: printvars
printvars:
@$(foreach V,$(.VARIABLES), $(if $(filter-out environment% default automatic, $(origin $V)),$(warning $V=$($V))))
ifneq (clean,$(MAKECMDGOALS))
-include $(DEPEND)
endif

164
tos/bascook/sources/bascook.c
View File

@@ -1,164 +0,0 @@
#include <stdio.h>
#include <mint/osbind.h>
#include <stdint.h>
#include <stdbool.h>
#include "driver_vec.h"
struct driver_table *get_bas_drivers(void)
{
struct driver_table *ret = NULL;
__asm__ __volatile__(
" bra.s do_trap \n\t"
" .dc.l 0x5f424153 \n\t" // '_BAS'
"do_trap: trap #0 \n\t"
" move.l d0,%[ret] \n\t"
: [ret] "=m" (ret) /* output */
: /* no inputs */
: /* clobbered */
);
return ret;
}
/*
* temporarily replace the trap 0 handler with this so we can avoid
* getting caught by BaS versions that don't understand the driver interface
* exposure call.
* If we get here, we have a BaS version that doesn't support the trap 0 interface
*/
static void __attribute__((interrupt)) my_own_trap0_handler(void)
{
__asm__ __volatile__(
" clr.l d0 \n\t" // return 0 to indicate not supported
:
:
:
);
}
static uint32_t cookieptr(void)
{
return * (uint32_t *) 0x5a0L;
}
void setcookie(uint32_t cookie, uint32_t value)
{
uint32_t *cookiejar = (uint32_t *) Supexec(cookieptr);
int num_slots;
int max_slots;
num_slots = max_slots = 0;
do
{
if (cookiejar[0] == cookie)
{
cookiejar[1] = value;
return;
}
cookiejar = &(cookiejar[2]);
num_slots++;
} while (cookiejar[-2]);
/*
* Here we are at the end of the list and did not find our cookie.
* Let's check if there is any space left and append our value to the
* list if so. If not, we are lost (extending the cookie jar does only
* work from TSRs)
*/
if (cookiejar[-1])
{
max_slots = cookiejar[-1];
}
if (max_slots > num_slots)
{
/* relief, there is space left, extend the list */
cookiejar[0] = cookiejar[-2];
cookiejar[1] = cookiejar[-1];
/* add the new element */
cookiejar[-2] = cookie;
cookiejar[-1] = value;
}
else
printf("cannot set cookie, cookie jar is full!\r\n");
}
#define COOKIE_DMAC 0x444d4143L /* FireTOS DMA API */
static char *dt_to_str(enum driver_type dt)
{
switch (dt)
{
case BLOCKDEV_DRIVER: return "generic block device driver";
case CHARDEV_DRIVER: return "generic character device driver";
case VIDEO_DRIVER: return "video/framebuffer driver";
case XHDI_DRIVER: return "XHDI compatible hard disk driver";
case MCD_DRIVER: return "multichannel DMA driver";
case PCI_DRIVER: return "PCI interface driver";
case MMU_DRIVER: return "MMU lock/unlock pages driver";
default: return "unknown driver type";
}
}
int main(int argc, char *argv[])
{
struct driver_table *dt;
void *ssp;
void *old_vector;
char **sysbase = (char **) 0x4f2;
uint32_t sig;
(void) Cconws("retrieve BaS driver interface\r\n");
ssp = (void *) Super(0L); /* go to supervisor mode, we are doing dirty tricks */
sig = * (long *)((*sysbase) + 0x2c);
/*
* first check if we are on EmuTOS, FireTOS want's to do everything itself
*/
if (sig == 0x45544f53)
{
old_vector = Setexc(0x20, my_own_trap0_handler); /* set our own temporarily */
dt = get_bas_drivers(); /* trap #0 */
(void) Setexc(0x20, old_vector); /* restore original vector */
if (dt)
{
struct generic_interface *ifc = &dt->interfaces[0];
printf("BaS driver table found at %p, BaS version is %d.%d\r\n", dt,
dt->bas_version, dt->bas_revision);
while (ifc->type != END_OF_DRIVERS)
{
printf("driver \"%s (%s)\" found,\r\n"
"interface type is %d (%s),\r\n"
"version %d.%d\r\n\r\n",
ifc->name, ifc->description, ifc->type, dt_to_str(ifc->type),
ifc->version, ifc->revision);
if (ifc->type == MCD_DRIVER)
{
setcookie(COOKIE_DMAC, (uint32_t) ifc->interface.dma);
printf("\r\nDMAC cookie set to %p\r\n", ifc->interface.dma);
}
ifc++;
}
}
else
{
printf("driver table not found.\r\n");
}
}
else
{
printf("not running on EmuTOS,\r\n(signature 0x%04x instead of 0x%04x\r\n",
(uint32_t) sig, 0x45544f53);
}
Super(ssp);
while (Cconis()) Cconin(); /* eat keys */
return 0;
}

16
tos/jtagwait/Makefile
View File

@@ -33,24 +33,18 @@ APP=jtagwait.prg
TEST_APP=$(APP)
CFLAGS=\
-O0\
-Os\
-g\
-Wl,-Map,mapfile\
-Wl,--defsym -Wl,__MBAR=0xff000000\
-Wl,--defsym -Wl,__MMUBAR=0xff040000\
-Wl,--defsym -Wl,__FPGA_JTAG_LOADED=0xff101000\
-Wl,--defsym -Wl,__FPGA_JTAG_VALID=0xff101004\
-Wall
SRCDIR=sources
INCDIR=include
INCLUDE+=-I$(INCDIR)
CSRCS=\
$(SRCDIR)/jtagwait.c \
$(SRCDIR)/bas_printf.c
ASRCS=$(SRCDIR)/printf_helper.S
$(SRCDIR)/jtagwait.c
ASRCS=
COBJS=$(patsubst $(SRCDIR)/%.o,%.o,$(patsubst %.c,%.o,$(CSRCS)))
AOBJS=$(patsubst $(SRCDIR)/%.o,%.o,$(patsubst %.S,%.o,$(ASRCS)))
@@ -97,7 +91,7 @@ clean:
.PHONY: printvars
printvars:
@$(foreach V,$(.VARIABLES), $(if $(filter-out environment% default automatic, $(origin $V)),$(warning $V=$($V))))
ifneq (clean,$(MAKECMDGOALS))
-include $(DEPEND)
endif

67
tos/jtagwait/include/MCF5475.h
View File

@@ -1,67 +0,0 @@
/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.81
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF5475_H__
#define __MCF5475_H__
#include <stdint.h>
/***
* MCF5475 Derivative Memory map definitions from linker command files:
* __MBAR, __MMUBAR, __RAMBAR0, __RAMBAR0_SIZE, __RAMBAR1, __RAMBAR1_SIZE
* linker symbols must be defined in the linker command file.
*/
typedef uint32_t __attribute__((__may_alias__)) uint32_t_a; /* a type to avoid gcc's complaints about pointer aliasing */
extern uint8_t _MBAR[];
extern uint8_t _MMUBAR[];
extern uint8_t _RAMBAR0[];
extern uint8_t _RAMBAR0_SIZE[];
extern uint8_t _RAMBAR1[];
extern uint8_t _RAMBAR1_SIZE[];
#define MBAR_ADDRESS (uint32_t)_MBAR
#define MMUBAR_ADDRESS (uint32_t)_MMUBAR
#define RAMBAR0_ADDRESS (uint32_t)_RAMBAR0
#define RAMBAR0_SIZE (uint32_t)_RAMBAR0_SIZE
#define RAMBAR1_ADDRESS (uint32_t)_RAMBAR1
#define RAMBAR1_SIZE (uint32_t)_RAMBAR1_SIZE
#include "MCF5475_SIU.h"
#include "MCF5475_MMU.h"
#include "MCF5475_SDRAMC.h"
#include "MCF5475_XLB.h"
#include "MCF5475_CLOCK.h"
#include "MCF5475_FBCS.h"
#include "MCF5475_INTC.h"
#include "MCF5475_GPT.h"
#include "MCF5475_SLT.h"
#include "MCF5475_GPIO.h"
#include "MCF5475_PAD.h"
#include "MCF5475_PCI.h"
#include "MCF5475_PCIARB.h"
#include "MCF5475_EPORT.h"
#include "MCF5475_CTM.h"
#include "MCF5475_DMA.h"
#include "MCF5475_PSC.h"
#include "MCF5475_DSPI.h"
#include "MCF5475_I2C.h"
#include "MCF5475_FEC.h"
#include "MCF5475_USB.h"
#include "MCF5475_SRAM.h"
#include "MCF5475_SEC.h"
#endif /* __MCF5475_H__ */

47
tos/jtagwait/include/MCF5475_CLOCK.h
View File

@@ -1,47 +0,0 @@
/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.81
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF5475_CLOCK_H__
#define __MCF5475_CLOCK_H__
/*********************************************************************
*
* Clock Module (CLOCK)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_CLOCK_SPCR (*(volatile uint32_t*)(&_MBAR[0x300]))
/* Bit definitions and macros for MCF_CLOCK_SPCR */
#define MCF_CLOCK_SPCR_MEMEN (0x1)
#define MCF_CLOCK_SPCR_PCIEN (0x2)
#define MCF_CLOCK_SPCR_FBEN (0x4)
#define MCF_CLOCK_SPCR_CAN0EN (0x8)
#define MCF_CLOCK_SPCR_DMAEN (0x10)
#define MCF_CLOCK_SPCR_FEC0EN (0x20)
#define MCF_CLOCK_SPCR_FEC1EN (0x40)
#define MCF_CLOCK_SPCR_USBEN (0x80)
#define MCF_CLOCK_SPCR_PSCEN (0x200)
#define MCF_CLOCK_SPCR_CAN1EN (0x800)
#define MCF_CLOCK_SPCR_CRYENA (0x1000)
#define MCF_CLOCK_SPCR_CRYENB (0x2000)
#define MCF_CLOCK_SPCR_COREN (0x4000)
#define MCF_CLOCK_SPCR_PLLK (0x80000000)
#endif /* __MCF5475_CLOCK_H__ */

76
tos/jtagwait/include/MCF5475_CTM.h
View File

@@ -1,76 +0,0 @@
/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.81
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF5475_CTM_H__
#define __MCF5475_CTM_H__
/*********************************************************************
*
* Comm Timer Module (CTM)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_CTM_CTCR0 (*(volatile uint32_t*)(&_MBAR[0x7F00]))
#define MCF_CTM_CTCR1 (*(volatile uint32_t*)(&_MBAR[0x7F04]))
#define MCF_CTM_CTCR2 (*(volatile uint32_t*)(&_MBAR[0x7F08]))
#define MCF_CTM_CTCR3 (*(volatile uint32_t*)(&_MBAR[0x7F0C]))
#define MCF_CTM_CTCR4 (*(volatile uint32_t*)(&_MBAR[0x7F10]))
#define MCF_CTM_CTCR5 (*(volatile uint32_t*)(&_MBAR[0x7F14]))
#define MCF_CTM_CTCR6 (*(volatile uint32_t*)(&_MBAR[0x7F18]))
#define MCF_CTM_CTCR7 (*(volatile uint32_t*)(&_MBAR[0x7F1C]))
#define MCF_CTM_CTCRF(x) (*(volatile uint32_t*)(&_MBAR[0x7F00 + ((x)*0x4)]))
#define MCF_CTM_CTCRV(x) (*(volatile uint32_t*)(&_MBAR[0x7F10 + ((x-4)*0x4)]))
/* Bit definitions and macros for MCF_CTM_CTCRF */
#define MCF_CTM_CTCRF_CRV(x) (((x)&0xFFFF)<<0)
#define MCF_CTM_CTCRF_S(x) (((x)&0xF)<<0x10)
#define MCF_CTM_CTCRF_S_CLK_1 (0)
#define MCF_CTM_CTCRF_S_CLK_2 (0x10000)
#define MCF_CTM_CTCRF_S_CLK_4 (0x20000)
#define MCF_CTM_CTCRF_S_CLK_8 (0x30000)
#define MCF_CTM_CTCRF_S_CLK_16 (0x40000)
#define MCF_CTM_CTCRF_S_CLK_32 (0x50000)
#define MCF_CTM_CTCRF_S_CLK_64 (0x60000)
#define MCF_CTM_CTCRF_S_CLK_128 (0x70000)
#define MCF_CTM_CTCRF_S_CLK_256 (0x80000)
#define MCF_CTM_CTCRF_S_CLK_EXT (0x90000)
#define MCF_CTM_CTCRF_PCT(x) (((x)&0x7)<<0x14)
#define MCF_CTM_CTCRF_PCT_100 (0)
#define MCF_CTM_CTCRF_PCT_50 (0x100000)
#define MCF_CTM_CTCRF_PCT_25 (0x200000)
#define MCF_CTM_CTCRF_PCT_12p5 (0x300000)
#define MCF_CTM_CTCRF_PCT_6p25 (0x400000)
#define MCF_CTM_CTCRF_PCT_OFF (0x500000)
#define MCF_CTM_CTCRF_M (0x800000)
#define MCF_CTM_CTCRF_IM (0x1000000)
#define MCF_CTM_CTCRF_I (0x80000000)
/* Bit definitions and macros for MCF_CTM_CTCRV */
#define MCF_CTM_CTCRV_CRV(x) (((x)&0xFFFFFF)<<0)
#define MCF_CTM_CTCRV_PCT(x) (((x)&0x7)<<0x18)
#define MCF_CTM_CTCRV_PCT_100 (0)
#define MCF_CTM_CTCRV_PCT_50 (0x1000000)
#define MCF_CTM_CTCRV_PCT_25 (0x2000000)
#define MCF_CTM_CTCRV_PCT_12p5 (0x3000000)
#define MCF_CTM_CTCRV_PCT_6p25 (0x4000000)
#define MCF_CTM_CTCRV_PCT_OFF (0x5000000)
#define MCF_CTM_CTCRV_M (0x8000000)
#define MCF_CTM_CTCRV_S (0x10000000)
#endif /* __MCF5475_CTM_H__ */

234
tos/jtagwait/include/MCF5475_DMA.h
View File

@@ -1,234 +0,0 @@
/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.81
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF5475_DMA_H__
#define __MCF5475_DMA_H__
/*********************************************************************
*
* Multichannel DMA (DMA)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_DMA_TASKBAR (*(volatile uint32_t*)(&_MBAR[0x8000]))
#define MCF_DMA_CP (*(volatile uint32_t*)(&_MBAR[0x8004]))
#define MCF_DMA_EP (*(volatile uint32_t*)(&_MBAR[0x8008]))
#define MCF_DMA_VP (*(volatile uint32_t*)(&_MBAR[0x800C]))
#define MCF_DMA_PTD (*(volatile uint32_t*)(&_MBAR[0x8010]))
#define MCF_DMA_DIPR (*(volatile uint32_t*)(&_MBAR[0x8014]))
#define MCF_DMA_DIMR (*(volatile uint32_t*)(&_MBAR[0x8018]))
#define MCF_DMA_TCR0 (*(volatile uint16_t*)(&_MBAR[0x801C]))
#define MCF_DMA_TCR1 (*(volatile uint16_t*)(&_MBAR[0x801E]))
#define MCF_DMA_TCR2 (*(volatile uint16_t*)(&_MBAR[0x8020]))
#define MCF_DMA_TCR3 (*(volatile uint16_t*)(&_MBAR[0x8022]))
#define MCF_DMA_TCR4 (*(volatile uint16_t*)(&_MBAR[0x8024]))
#define MCF_DMA_TCR5 (*(volatile uint16_t*)(&_MBAR[0x8026]))
#define MCF_DMA_TCR6 (*(volatile uint16_t*)(&_MBAR[0x8028]))
#define MCF_DMA_TCR7 (*(volatile uint16_t*)(&_MBAR[0x802A]))
#define MCF_DMA_TCR8 (*(volatile uint16_t*)(&_MBAR[0x802C]))
#define MCF_DMA_TCR9 (*(volatile uint16_t*)(&_MBAR[0x802E]))
#define MCF_DMA_TCR10 (*(volatile uint16_t*)(&_MBAR[0x8030]))
#define MCF_DMA_TCR11 (*(volatile uint16_t*)(&_MBAR[0x8032]))
#define MCF_DMA_TCR12 (*(volatile uint16_t*)(&_MBAR[0x8034]))
#define MCF_DMA_TCR13 (*(volatile uint16_t*)(&_MBAR[0x8036]))
#define MCF_DMA_TCR14 (*(volatile uint16_t*)(&_MBAR[0x8038]))
#define MCF_DMA_TCR15 (*(volatile uint16_t*)(&_MBAR[0x803A]))
#define MCF_DMA_PRIOR0 (*(volatile uint8_t *)(&_MBAR[0x803C]))
#define MCF_DMA_PRIOR1 (*(volatile uint8_t *)(&_MBAR[0x803D]))
#define MCF_DMA_PRIOR2 (*(volatile uint8_t *)(&_MBAR[0x803E]))
#define MCF_DMA_PRIOR3 (*(volatile uint8_t *)(&_MBAR[0x803F]))
#define MCF_DMA_PRIOR4 (*(volatile uint8_t *)(&_MBAR[0x8040]))
#define MCF_DMA_PRIOR5 (*(volatile uint8_t *)(&_MBAR[0x8041]))
#define MCF_DMA_PRIOR6 (*(volatile uint8_t *)(&_MBAR[0x8042]))
#define MCF_DMA_PRIOR7 (*(volatile uint8_t *)(&_MBAR[0x8043]))
#define MCF_DMA_PRIOR8 (*(volatile uint8_t *)(&_MBAR[0x8044]))
#define MCF_DMA_PRIOR9 (*(volatile uint8_t *)(&_MBAR[0x8045]))
#define MCF_DMA_PRIOR10 (*(volatile uint8_t *)(&_MBAR[0x8046]))
#define MCF_DMA_PRIOR11 (*(volatile uint8_t *)(&_MBAR[0x8047]))
#define MCF_DMA_PRIOR12 (*(volatile uint8_t *)(&_MBAR[0x8048]))
#define MCF_DMA_PRIOR13 (*(volatile uint8_t *)(&_MBAR[0x8049]))
#define MCF_DMA_PRIOR14 (*(volatile uint8_t *)(&_MBAR[0x804A]))
#define MCF_DMA_PRIOR15 (*(volatile uint8_t *)(&_MBAR[0x804B]))
#define MCF_DMA_PRIOR16 (*(volatile uint8_t *)(&_MBAR[0x804C]))
#define MCF_DMA_PRIOR17 (*(volatile uint8_t *)(&_MBAR[0x804D]))
#define MCF_DMA_PRIOR18 (*(volatile uint8_t *)(&_MBAR[0x804E]))
#define MCF_DMA_PRIOR19 (*(volatile uint8_t *)(&_MBAR[0x804F]))
#define MCF_DMA_PRIOR20 (*(volatile uint8_t *)(&_MBAR[0x8050]))
#define MCF_DMA_PRIOR21 (*(volatile uint8_t *)(&_MBAR[0x8051]))
#define MCF_DMA_PRIOR22 (*(volatile uint8_t *)(&_MBAR[0x8052]))
#define MCF_DMA_PRIOR23 (*(volatile uint8_t *)(&_MBAR[0x8053]))
#define MCF_DMA_PRIOR24 (*(volatile uint8_t *)(&_MBAR[0x8054]))
#define MCF_DMA_PRIOR25 (*(volatile uint8_t *)(&_MBAR[0x8055]))
#define MCF_DMA_PRIOR26 (*(volatile uint8_t *)(&_MBAR[0x8056]))
#define MCF_DMA_PRIOR27 (*(volatile uint8_t *)(&_MBAR[0x8057]))
#define MCF_DMA_PRIOR28 (*(volatile uint8_t *)(&_MBAR[0x8058]))
#define MCF_DMA_PRIOR29 (*(volatile uint8_t *)(&_MBAR[0x8059]))
#define MCF_DMA_PRIOR30 (*(volatile uint8_t *)(&_MBAR[0x805A]))
#define MCF_DMA_PRIOR31 (*(volatile uint8_t *)(&_MBAR[0x805B]))
#define MCF_DMA_IMCR (*(volatile uint32_t*)(&_MBAR[0x805C]))
#define MCF_DMA_TSKSZ0 (*(volatile uint32_t*)(&_MBAR[0x8060]))
#define MCF_DMA_TSKSZ1 (*(volatile uint32_t*)(&_MBAR[0x8064]))
#define MCF_DMA_DBGCOMP0 (*(volatile uint32_t*)(&_MBAR[0x8070]))
#define MCF_DMA_DBGCOMP2 (*(volatile uint32_t*)(&_MBAR[0x8074]))
#define MCF_DMA_DBGCTL (*(volatile uint32_t*)(&_MBAR[0x8078]))
#define MCF_DMA_TCR(x) (*(volatile uint16_t*)(&_MBAR[0x801C + ((x)*0x2)]))
#define MCF_DMA_PRIOR(x) (*(volatile uint8_t *)(&_MBAR[0x803C + ((x)*0x1)]))
/* Bit definitions and macros for MCF_DMA_TASKBAR */
#define MCF_DMA_TASKBAR_TASK_BASE_ADDRESS(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_DMA_CP */
#define MCF_DMA_CP_DESCRIPTOR_POINTER(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_DMA_EP */
#define MCF_DMA_EP_DESCRIPTOR_POINTER(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_DMA_VP */
#define MCF_DMA_VP_VARIABLE_POINTER(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_DMA_PTD */
#define MCF_DMA_PTD_PCTL0 (0x1)
#define MCF_DMA_PTD_PCTL1 (0x2)
#define MCF_DMA_PTD_PCTL13 (0x2000)
#define MCF_DMA_PTD_PCTL14 (0x4000)
#define MCF_DMA_PTD_PCTL15 (0x8000)
/* Bit definitions and macros for MCF_DMA_DIPR */
#define MCF_DMA_DIPR_TASK(x) (((x)&0xFFFF)<<0)
/* Bit definitions and macros for MCF_DMA_DIMR */
#define MCF_DMA_DIMR_TASK(x) (((x)&0xFFFF)<<0)
/* Bit definitions and macros for MCF_DMA_TCR */
#define MCF_DMA_TCR_ASTSKNUM(x) (((x)&0xF)<<0)
#define MCF_DMA_TCR_HLDINITNUM (0x20)
#define MCF_DMA_TCR_HIPRITSKEN (0x40)
#define MCF_DMA_TCR_ASTRT (0x80)
#define MCF_DMA_TCR_INITNUM(x) (((x)&0x1F)<<0x8)
#define MCF_DMA_TCR_ALWINIT (0x2000)
#define MCF_DMA_TCR_V (0x4000)
#define MCF_DMA_TCR_EN (0x8000)
/* Bit definitions and macros for MCF_DMA_PRIOR */
#define MCF_DMA_PRIOR_PRI(x) (((x)&0x7)<<0)
#define MCF_DMA_PRIOR_HLD (0x80)
/* Bit definitions and macros for MCF_DMA_IMCR */
#define MCF_DMA_IMCR_IMC16(x) (((x)&0x3)<<0)
#define MCF_DMA_IMCR_IMC17(x) (((x)&0x3)<<0x2)
#define MCF_DMA_IMCR_IMC18(x) (((x)&0x3)<<0x4)
#define MCF_DMA_IMCR_IMC19(x) (((x)&0x3)<<0x6)
#define MCF_DMA_IMCR_IMC20(x) (((x)&0x3)<<0x8)
#define MCF_DMA_IMCR_IMC21(x) (((x)&0x3)<<0xA)
#define MCF_DMA_IMCR_IMC22(x) (((x)&0x3)<<0xC)
#define MCF_DMA_IMCR_IMC23(x) (((x)&0x3)<<0xE)
#define MCF_DMA_IMCR_IMC24(x) (((x)&0x3)<<0x10)
#define MCF_DMA_IMCR_IMC25(x) (((x)&0x3)<<0x12)
#define MCF_DMA_IMCR_IMC26(x) (((x)&0x3)<<0x14)
#define MCF_DMA_IMCR_IMC27(x) (((x)&0x3)<<0x16)
#define MCF_DMA_IMCR_IMC28(x) (((x)&0x3)<<0x18)
#define MCF_DMA_IMCR_IMC29(x) (((x)&0x3)<<0x1A)
#define MCF_DMA_IMCR_IMC30(x) (((x)&0x3)<<0x1C)
#define MCF_DMA_IMCR_IMC31(x) (((x)&0x3)<<0x1E)
#define MCF_DMA_IMCR_IMC16_FEC0RX (0x00000000)
#define MCF_DMA_IMCR_IMC17_FEC0TX (0x00000000)
#define MCF_DMA_IMCR_IMC18_FEC0RX (0x00000020)
#define MCF_DMA_IMCR_IMC19_FEC0TX (0x00000080)
#define MCF_DMA_IMCR_IMC20_FEC1RX (0x00000100)
#define MCF_DMA_IMCR_IMC21_DREQ1 (0x00000000)
#define MCF_DMA_IMCR_IMC21_FEC1TX (0x00000400)
#define MCF_DMA_IMCR_IMC22_FEC0RX (0x00001000)
#define MCF_DMA_IMCR_IMC23_FEC0TX (0x00004000)
#define MCF_DMA_IMCR_IMC24_CTM0 (0x00010000)
#define MCF_DMA_IMCR_IMC24_FEC1RX (0x00020000)
#define MCF_DMA_IMCR_IMC25_CTM1 (0x00040000)
#define MCF_DMA_IMCR_IMC25_FEC1TX (0x00080000)
#define MCF_DMA_IMCR_IMC26_USBEP4 (0x00000000)
#define MCF_DMA_IMCR_IMC26_CTM2 (0x00200000)
#define MCF_DMA_IMCR_IMC27_USBEP5 (0x00000000)
#define MCF_DMA_IMCR_IMC27_CTM3 (0x00800000)
#define MCF_DMA_IMCR_IMC28_USBEP6 (0x00000000)
#define MCF_DMA_IMCR_IMC28_CTM4 (0x01000000)
#define MCF_DMA_IMCR_IMC28_DREQ1 (0x02000000)
#define MCF_DMA_IMCR_IMC28_PSC2RX (0x03000000)
#define MCF_DMA_IMCR_IMC29_DREQ1 (0x04000000)
#define MCF_DMA_IMCR_IMC29_CTM5 (0x08000000)
#define MCF_DMA_IMCR_IMC29_PSC2TX (0x0C000000)
#define MCF_DMA_IMCR_IMC30_FEC1RX (0x00000000)
#define MCF_DMA_IMCR_IMC30_CTM6 (0x10000000)
#define MCF_DMA_IMCR_IMC30_PSC3RX (0x30000000)
#define MCF_DMA_IMCR_IMC31_FEC1TX (0x00000000)
#define MCF_DMA_IMCR_IMC31_CTM7 (0x80000000)
#define MCF_DMA_IMCR_IMC31_PSC3TX (0xC0000000)
/* Bit definitions and macros for MCF_DMA_TSKSZ0 */
#define MCF_DMA_TSKSZ0_DSTSZ7(x) (((x)&0x3)<<0)
#define MCF_DMA_TSKSZ0_SRCSZ7(x) (((x)&0x3)<<0x2)
#define MCF_DMA_TSKSZ0_DSTSZ6(x) (((x)&0x3)<<0x4)
#define MCF_DMA_TSKSZ0_SRCSZ6(x) (((x)&0x3)<<0x6)
#define MCF_DMA_TSKSZ0_DSTSZ5(x) (((x)&0x3)<<0x8)
#define MCF_DMA_TSKSZ0_SRCSZ5(x) (((x)&0x3)<<0xA)
#define MCF_DMA_TSKSZ0_DSTSZ4(x) (((x)&0x3)<<0xC)
#define MCF_DMA_TSKSZ0_SRCSZ4(x) (((x)&0x3)<<0xE)
#define MCF_DMA_TSKSZ0_DSTSZ3(x) (((x)&0x3)<<0x10)
#define MCF_DMA_TSKSZ0_SRCSZ3(x) (((x)&0x3)<<0x12)
#define MCF_DMA_TSKSZ0_DSTSZ2(x) (((x)&0x3)<<0x14)
#define MCF_DMA_TSKSZ0_SRCSZ2(x) (((x)&0x3)<<0x16)
#define MCF_DMA_TSKSZ0_DSTSZ1(x) (((x)&0x3)<<0x18)
#define MCF_DMA_TSKSZ0_SRCSZ1(x) (((x)&0x3)<<0x1A)
#define MCF_DMA_TSKSZ0_DSTSZ0(x) (((x)&0x3)<<0x1C)
#define MCF_DMA_TSKSZ0_SRCSZ0(x) (((x)&0x3)<<0x1E)
/* Bit definitions and macros for MCF_DMA_TSKSZ1 */
#define MCF_DMA_TSKSZ1_DSTSZ15(x) (((x)&0x3)<<0)
#define MCF_DMA_TSKSZ1_SRCSZ15(x) (((x)&0x3)<<0x2)
#define MCF_DMA_TSKSZ1_DSTSZ14(x) (((x)&0x3)<<0x4)
#define MCF_DMA_TSKSZ1_SRCSZ14(x) (((x)&0x3)<<0x6)
#define MCF_DMA_TSKSZ1_DSTSZ13(x) (((x)&0x3)<<0x8)
#define MCF_DMA_TSKSZ1_SRCSZ13(x) (((x)&0x3)<<0xA)
#define MCF_DMA_TSKSZ1_DSTSZ12(x) (((x)&0x3)<<0xC)
#define MCF_DMA_TSKSZ1_SRCSZ12(x) (((x)&0x3)<<0xE)
#define MCF_DMA_TSKSZ1_DSTSZ11(x) (((x)&0x3)<<0x10)
#define MCF_DMA_TSKSZ1_SRCSZ11(x) (((x)&0x3)<<0x12)
#define MCF_DMA_TSKSZ1_DSTSZ10(x) (((x)&0x3)<<0x14)
#define MCF_DMA_TSKSZ1_SRCSZ10(x) (((x)&0x3)<<0x16)
#define MCF_DMA_TSKSZ1_DSTSZ9(x) (((x)&0x3)<<0x18)
#define MCF_DMA_TSKSZ1_SRCSZ9(x) (((x)&0x3)<<0x1A)
#define MCF_DMA_TSKSZ1_DSTSZ8(x) (((x)&0x3)<<0x1C)
#define MCF_DMA_TSKSZ1_SRCSZ8(x) (((x)&0x3)<<0x1E)
/* Bit definitions and macros for MCF_DMA_DBGCOMP0 */
#define MCF_DMA_DBGCOMP0_COMPARATOR_VALUE(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_DMA_DBGCOMP2 */
#define MCF_DMA_DBGCOMP2_COMPARATOR_VALUE(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_DMA_DBGCTL */
#define MCF_DMA_DBGCTL_I (0x2)
#define MCF_DMA_DBGCTL_E (0x4)
#define MCF_DMA_DBGCTL_AND_OR (0x80)
#define MCF_DMA_DBGCTL_COMPARATOR_TYPE_2(x) (((x)&0x7)<<0x8)
#define MCF_DMA_DBGCTL_COMPARATOR_TYPE_1(x) (((x)&0x7)<<0xB)
#define MCF_DMA_DBGCTL_B (0x4000)
#define MCF_DMA_DBGCTL_AA (0x8000)
#define MCF_DMA_DBGCTL_BLOCK_TASKS(x) (((x)&0xFFFF)<<0x10)
#endif /* __MCF5475_DMA_H__ */

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tos/jtagwait/include/MCF5475_DSPI.h
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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.81
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF5475_DSPI_H__
#define __MCF5475_DSPI_H__
/*********************************************************************
*
* DMA Serial Peripheral Interface (DSPI)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_DSPI_DMCR (*(volatile uint32_t*)(&_MBAR[0x8A00]))
#define MCF_DSPI_DTCR (*(volatile uint32_t*)(&_MBAR[0x8A08]))
#define MCF_DSPI_DCTAR0 (*(volatile uint32_t*)(&_MBAR[0x8A0C]))
#define MCF_DSPI_DCTAR1 (*(volatile uint32_t*)(&_MBAR[0x8A10]))
#define MCF_DSPI_DCTAR2 (*(volatile uint32_t*)(&_MBAR[0x8A14]))
#define MCF_DSPI_DCTAR3 (*(volatile uint32_t*)(&_MBAR[0x8A18]))
#define MCF_DSPI_DCTAR4 (*(volatile uint32_t*)(&_MBAR[0x8A1C]))
#define MCF_DSPI_DCTAR5 (*(volatile uint32_t*)(&_MBAR[0x8A20]))
#define MCF_DSPI_DCTAR6 (*(volatile uint32_t*)(&_MBAR[0x8A24]))
#define MCF_DSPI_DCTAR7 (*(volatile uint32_t*)(&_MBAR[0x8A28]))
#define MCF_DSPI_DSR (*(volatile uint32_t*)(&_MBAR[0x8A2C]))
#define MCF_DSPI_DIRSR (*(volatile uint32_t*)(&_MBAR[0x8A30]))
#define MCF_DSPI_DTFR (*(volatile uint32_t*)(&_MBAR[0x8A34]))
#define MCF_DSPI_DRFR (*(volatile uint32_t*)(&_MBAR[0x8A38]))
#define MCF_DSPI_DTFDR0 (*(volatile uint32_t*)(&_MBAR[0x8A3C]))
#define MCF_DSPI_DTFDR1 (*(volatile uint32_t*)(&_MBAR[0x8A40]))
#define MCF_DSPI_DTFDR2 (*(volatile uint32_t*)(&_MBAR[0x8A44]))
#define MCF_DSPI_DTFDR3 (*(volatile uint32_t*)(&_MBAR[0x8A48]))
#define MCF_DSPI_DRFDR0 (*(volatile uint32_t*)(&_MBAR[0x8A7C]))
#define MCF_DSPI_DRFDR1 (*(volatile uint32_t*)(&_MBAR[0x8A80]))
#define MCF_DSPI_DRFDR2 (*(volatile uint32_t*)(&_MBAR[0x8A84]))
#define MCF_DSPI_DRFDR3 (*(volatile uint32_t*)(&_MBAR[0x8A88]))
#define MCF_DSPI_DCTAR(x) (*(volatile uint32_t*)(&_MBAR[0x8A0C + ((x)*0x4)]))
#define MCF_DSPI_DTFDR(x) (*(volatile uint32_t*)(&_MBAR[0x8A3C + ((x)*0x4)]))
#define MCF_DSPI_DRFDR(x) (*(volatile uint32_t*)(&_MBAR[0x8A7C + ((x)*0x4)]))
/* Bit definitions and macros for MCF_DSPI_DMCR */
#define MCF_DSPI_DMCR_HALT (0x1)
#define MCF_DSPI_DMCR_SMPL_PT(x) (((x)&0x3)<<0x8)
#define MCF_DSPI_DMCR_SMPL_PT_0CLK (0)
#define MCF_DSPI_DMCR_SMPL_PT_1CLK (0x100)
#define MCF_DSPI_DMCR_SMPL_PT_2CLK (0x200)
#define MCF_DSPI_DMCR_CRXF (0x400)
#define MCF_DSPI_DMCR_CTXF (0x800)
#define MCF_DSPI_DMCR_DRXF (0x1000)
#define MCF_DSPI_DMCR_DTXF (0x2000)
#define MCF_DSPI_DMCR_CSIS0 (0x10000)
#define MCF_DSPI_DMCR_CSIS2 (0x40000)
#define MCF_DSPI_DMCR_CSIS3 (0x80000)
#define MCF_DSPI_DMCR_CSIS5 (0x200000)
#define MCF_DSPI_DMCR_ROOE (0x1000000)
#define MCF_DSPI_DMCR_PCSSE (0x2000000)
#define MCF_DSPI_DMCR_MTFE (0x4000000)
#define MCF_DSPI_DMCR_FRZ (0x8000000)
#define MCF_DSPI_DMCR_DCONF(x) (((x)&0x3)<<0x1C)
#define MCF_DSPI_DMCR_CSCK (0x40000000)
#define MCF_DSPI_DMCR_MSTR (0x80000000)
/* Bit definitions and macros for MCF_DSPI_DTCR */
#define MCF_DSPI_DTCR_SPI_TCNT(x) (((x)&0xFFFF)<<0x10)
/* Bit definitions and macros for MCF_DSPI_DCTAR */
#define MCF_DSPI_DCTAR_BR(x) (((x)&0xF)<<0)
#define MCF_DSPI_DCTAR_DT(x) (((x)&0xF)<<0x4)
#define MCF_DSPI_DCTAR_ASC(x) (((x)&0xF)<<0x8)
#define MCF_DSPI_DCTAR_CSSCK(x) (((x)&0xF)<<0xC)
#define MCF_DSPI_DCTAR_PBR(x) (((x)&0x3)<<0x10)
#define MCF_DSPI_DCTAR_PBR_1CLK (0)
#define MCF_DSPI_DCTAR_PBR_3CLK (0x10000)
#define MCF_DSPI_DCTAR_PBR_5CLK (0x20000)
#define MCF_DSPI_DCTAR_PBR_7CLK (0x30000)
#define MCF_DSPI_DCTAR_PDT(x) (((x)&0x3)<<0x12)
#define MCF_DSPI_DCTAR_PDT_1CLK (0)
#define MCF_DSPI_DCTAR_PDT_3CLK (0x40000)
#define MCF_DSPI_DCTAR_PDT_5CLK (0x80000)
#define MCF_DSPI_DCTAR_PDT_7CLK (0xC0000)
#define MCF_DSPI_DCTAR_PASC(x) (((x)&0x3)<<0x14)
#define MCF_DSPI_DCTAR_PASC_1CLK (0)
#define MCF_DSPI_DCTAR_PASC_3CLK (0x100000)
#define MCF_DSPI_DCTAR_PASC_5CLK (0x200000)
#define MCF_DSPI_DCTAR_PASC_7CLK (0x300000)
#define MCF_DSPI_DCTAR_PCSSCK(x) (((x)&0x3)<<0x16)
#define MCF_DSPI_DCTAR_LSBFE (0x1000000)
#define MCF_DSPI_DCTAR_CPHA (0x2000000)
#define MCF_DSPI_DCTAR_CPOL (0x4000000)
#define MCF_DSPI_DCTAR_TRSZ(x) (((x)&0xF)<<0x1B)
/* Bit definitions and macros for MCF_DSPI_DSR */
#define MCF_DSPI_DSR_RXPTR(x) (((x)&0xF)<<0)
#define MCF_DSPI_DSR_RXCTR(x) (((x)&0xF)<<0x4)
#define MCF_DSPI_DSR_TXPTR(x) (((x)&0xF)<<0x8)
#define MCF_DSPI_DSR_TXCTR(x) (((x)&0xF)<<0xC)
#define MCF_DSPI_DSR_RFDF (0x20000)
#define MCF_DSPI_DSR_RFOF (0x80000)
#define MCF_DSPI_DSR_TFFF (0x2000000)
#define MCF_DSPI_DSR_TFUF (0x8000000)
#define MCF_DSPI_DSR_EOQF (0x10000000)
#define MCF_DSPI_DSR_TXRXS (0x40000000)
#define MCF_DSPI_DSR_TCF (0x80000000)
/* Bit definitions and macros for MCF_DSPI_DIRSR */
#define MCF_DSPI_DIRSR_RFDFS (0x10000)
#define MCF_DSPI_DIRSR_RFDFE (0x20000)
#define MCF_DSPI_DIRSR_RFOFE (0x80000)
#define MCF_DSPI_DIRSR_TFFFS (0x1000000)
#define MCF_DSPI_DIRSR_TFFFE (0x2000000)
#define MCF_DSPI_DIRSR_TFUFE (0x8000000)
#define MCF_DSPI_DIRSR_EOQFE (0x10000000)
#define MCF_DSPI_DIRSR_TCFE (0x80000000)
/* Bit definitions and macros for MCF_DSPI_DTFR */
#define MCF_DSPI_DTFR_TXDATA(x) (((x)&0xFFFF)<<0)
#define MCF_DSPI_DTFR_CS0 (0x10000)
#define MCF_DSPI_DTFR_CS2 (0x40000)
#define MCF_DSPI_DTFR_CS3 (0x80000)
#define MCF_DSPI_DTFR_CS5 (0x200000)
#define MCF_DSPI_DTFR_CTCNT (0x4000000)
#define MCF_DSPI_DTFR_EOQ (0x8000000)
#define MCF_DSPI_DTFR_CTAS(x) (((x)&0x7)<<0x1C)
#define MCF_DSPI_DTFR_CONT (0x80000000)
/* Bit definitions and macros for MCF_DSPI_DRFR */
#define MCF_DSPI_DRFR_RXDATA(x) (((x)&0xFFFF)<<0)
/* Bit definitions and macros for MCF_DSPI_DTFDR */
#define MCF_DSPI_DTFDR_TXDATA(x) (((x)&0xFFFF)<<0)
#define MCF_DSPI_DTFDR_TXCMD(x) (((x)&0xFFFF)<<0x10)
/* Bit definitions and macros for MCF_DSPI_DRFDR */
#define MCF_DSPI_DRFDR_RXDATA(x) (((x)&0xFFFF)<<0)
#endif /* __MCF5475_DSPI_H__ */

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tos/jtagwait/include/MCF5475_EPORT.h
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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.81
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF5475_EPORT_H__
#define __MCF5475_EPORT_H__
/*********************************************************************
*
* Edge Port Module (EPORT)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_EPORT_EPPAR (*(volatile uint16_t*)(&_MBAR[0xF00]))
#define MCF_EPORT_EPDDR (*(volatile uint8_t *)(&_MBAR[0xF04]))
#define MCF_EPORT_EPIER (*(volatile uint8_t *)(&_MBAR[0xF05]))
#define MCF_EPORT_EPDR (*(volatile uint8_t *)(&_MBAR[0xF08]))
#define MCF_EPORT_EPPDR (*(volatile uint8_t *)(&_MBAR[0xF09]))
#define MCF_EPORT_EPFR (*(volatile uint8_t *)(&_MBAR[0xF0C]))
/* Bit definitions and macros for MCF_EPORT_EPPAR */
#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x3)<<0x2)
#define MCF_EPORT_EPPAR_EPPA1_LEVEL (0)
#define MCF_EPORT_EPPAR_EPPA1_RISING (0x4)
#define MCF_EPORT_EPPAR_EPPA1_FALLING (0x8)
#define MCF_EPORT_EPPAR_EPPA1_BOTH (0xC)
#define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x3)<<0x4)
#define MCF_EPORT_EPPAR_EPPA2_LEVEL (0)
#define MCF_EPORT_EPPAR_EPPA2_RISING (0x10)
#define MCF_EPORT_EPPAR_EPPA2_FALLING (0x20)
#define MCF_EPORT_EPPAR_EPPA2_BOTH (0x30)
#define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x3)<<0x6)
#define MCF_EPORT_EPPAR_EPPA3_LEVEL (0)
#define MCF_EPORT_EPPAR_EPPA3_RISING (0x40)
#define MCF_EPORT_EPPAR_EPPA3_FALLING (0x80)
#define MCF_EPORT_EPPAR_EPPA3_BOTH (0xC0)
#define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x3)<<0x8)
#define MCF_EPORT_EPPAR_EPPA4_LEVEL (0)
#define MCF_EPORT_EPPAR_EPPA4_RISING (0x100)
#define MCF_EPORT_EPPAR_EPPA4_FALLING (0x200)
#define MCF_EPORT_EPPAR_EPPA4_BOTH (0x300)
#define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x3)<<0xA)
#define MCF_EPORT_EPPAR_EPPA5_LEVEL (0)
#define MCF_EPORT_EPPAR_EPPA5_RISING (0x400)
#define MCF_EPORT_EPPAR_EPPA5_FALLING (0x800)
#define MCF_EPORT_EPPAR_EPPA5_BOTH (0xC00)
#define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x3)<<0xC)
#define MCF_EPORT_EPPAR_EPPA6_LEVEL (0)
#define MCF_EPORT_EPPAR_EPPA6_RISING (0x1000)
#define MCF_EPORT_EPPAR_EPPA6_FALLING (0x2000)
#define MCF_EPORT_EPPAR_EPPA6_BOTH (0x3000)
#define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x3)<<0xE)
#define MCF_EPORT_EPPAR_EPPA7_LEVEL (0)
#define MCF_EPORT_EPPAR_EPPA7_RISING (0x4000)
#define MCF_EPORT_EPPAR_EPPA7_FALLING (0x8000)
#define MCF_EPORT_EPPAR_EPPA7_BOTH (0xC000)
#define MCF_EPORT_EPPAR_LEVEL (0)
#define MCF_EPORT_EPPAR_RISING (0x1)
#define MCF_EPORT_EPPAR_FALLING (0x2)
#define MCF_EPORT_EPPAR_BOTH (0x3)
/* Bit definitions and macros for MCF_EPORT_EPDDR */
#define MCF_EPORT_EPDDR_EPDD1 (0x2)
#define MCF_EPORT_EPDDR_EPDD2 (0x4)
#define MCF_EPORT_EPDDR_EPDD3 (0x8)
#define MCF_EPORT_EPDDR_EPDD4 (0x10)
#define MCF_EPORT_EPDDR_EPDD5 (0x20)
#define MCF_EPORT_EPDDR_EPDD6 (0x40)
#define MCF_EPORT_EPDDR_EPDD7 (0x80)
/* Bit definitions and macros for MCF_EPORT_EPIER */
#define MCF_EPORT_EPIER_EPIE1 (0x2)
#define MCF_EPORT_EPIER_EPIE2 (0x4)
#define MCF_EPORT_EPIER_EPIE3 (0x8)
#define MCF_EPORT_EPIER_EPIE4 (0x10)
#define MCF_EPORT_EPIER_EPIE5 (0x20)
#define MCF_EPORT_EPIER_EPIE6 (0x40)
#define MCF_EPORT_EPIER_EPIE7 (0x80)
/* Bit definitions and macros for MCF_EPORT_EPDR */
#define MCF_EPORT_EPDR_EPD1 (0x2)
#define MCF_EPORT_EPDR_EPD2 (0x4)
#define MCF_EPORT_EPDR_EPD3 (0x8)
#define MCF_EPORT_EPDR_EPD4 (0x10)
#define MCF_EPORT_EPDR_EPD5 (0x20)
#define MCF_EPORT_EPDR_EPD6 (0x40)
#define MCF_EPORT_EPDR_EPD7 (0x80)
/* Bit definitions and macros for MCF_EPORT_EPPDR */
#define MCF_EPORT_EPPDR_EPPD1 (0x2)
#define MCF_EPORT_EPPDR_EPPD2 (0x4)
#define MCF_EPORT_EPPDR_EPPD3 (0x8)
#define MCF_EPORT_EPPDR_EPPD4 (0x10)
#define MCF_EPORT_EPPDR_EPPD5 (0x20)
#define MCF_EPORT_EPPDR_EPPD6 (0x40)
#define MCF_EPORT_EPPDR_EPPD7 (0x80)
/* Bit definitions and macros for MCF_EPORT_EPFR */
#define MCF_EPORT_EPFR_EPF1 (0x2)
#define MCF_EPORT_EPFR_EPF2 (0x4)
#define MCF_EPORT_EPFR_EPF3 (0x8)
#define MCF_EPORT_EPFR_EPF4 (0x10)
#define MCF_EPORT_EPFR_EPF5 (0x20)
#define MCF_EPORT_EPFR_EPF6 (0x40)
#define MCF_EPORT_EPFR_EPF7 (0x80)
#endif /* __MCF5475_EPORT_H__ */

100
tos/jtagwait/include/MCF5475_FBCS.h
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@@ -1,100 +0,0 @@
/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.81
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF5475_FBCS_H__
#define __MCF5475_FBCS_H__
/*********************************************************************
*
* FlexBus Chip Select Module (FBCS)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_FBCS0_CSAR (*(volatile uint32_t*)(&_MBAR[0x500]))
#define MCF_FBCS0_CSMR (*(volatile uint32_t*)(&_MBAR[0x504]))
#define MCF_FBCS0_CSCR (*(volatile uint32_t*)(&_MBAR[0x508]))
#define MCF_FBCS1_CSAR (*(volatile uint32_t*)(&_MBAR[0x50C]))
#define MCF_FBCS1_CSMR (*(volatile uint32_t*)(&_MBAR[0x510]))
#define MCF_FBCS1_CSCR (*(volatile uint32_t*)(&_MBAR[0x514]))
#define MCF_FBCS2_CSAR (*(volatile uint32_t*)(&_MBAR[0x518]))
#define MCF_FBCS2_CSMR (*(volatile uint32_t*)(&_MBAR[0x51C]))
#define MCF_FBCS2_CSCR (*(volatile uint32_t*)(&_MBAR[0x520]))
#define MCF_FBCS3_CSAR (*(volatile uint32_t*)(&_MBAR[0x524]))
#define MCF_FBCS3_CSMR (*(volatile uint32_t*)(&_MBAR[0x528]))
#define MCF_FBCS3_CSCR (*(volatile uint32_t*)(&_MBAR[0x52C]))
#define MCF_FBCS4_CSAR (*(volatile uint32_t*)(&_MBAR[0x530]))
#define MCF_FBCS4_CSMR (*(volatile uint32_t*)(&_MBAR[0x534]))
#define MCF_FBCS4_CSCR (*(volatile uint32_t*)(&_MBAR[0x538]))
#define MCF_FBCS5_CSAR (*(volatile uint32_t*)(&_MBAR[0x53C]))
#define MCF_FBCS5_CSMR (*(volatile uint32_t*)(&_MBAR[0x540]))
#define MCF_FBCS5_CSCR (*(volatile uint32_t*)(&_MBAR[0x544]))
#define MCF_FBCS_CSAR(x) (*(volatile uint32_t*)(&_MBAR[0x500 + ((x)*0xC)]))
#define MCF_FBCS_CSMR(x) (*(volatile uint32_t*)(&_MBAR[0x504 + ((x)*0xC)]))
#define MCF_FBCS_CSCR(x) (*(volatile uint32_t*)(&_MBAR[0x508 + ((x)*0xC)]))
/* Bit definitions and macros for MCF_FBCS_CSAR */
#define MCF_FBCS_CSAR_BA(x) ((x)&0xFFFF0000)
/* Bit definitions and macros for MCF_FBCS_CSMR */
#define MCF_FBCS_CSMR_V (0x1)
#define MCF_FBCS_CSMR_WP (0x100)
#define MCF_FBCS_CSMR_BAM(x) (((x)&0xFFFF)<<0x10)
#define MCF_FBCS_CSMR_BAM_4G (0xFFFF0000)
#define MCF_FBCS_CSMR_BAM_2G (0x7FFF0000)
#define MCF_FBCS_CSMR_BAM_1G (0x3FFF0000)
#define MCF_FBCS_CSMR_BAM_1024M (0x3FFF0000)
#define MCF_FBCS_CSMR_BAM_512M (0x1FFF0000)
#define MCF_FBCS_CSMR_BAM_256M (0xFFF0000)
#define MCF_FBCS_CSMR_BAM_128M (0x7FF0000)
#define MCF_FBCS_CSMR_BAM_64M (0x3FF0000)
#define MCF_FBCS_CSMR_BAM_32M (0x1FF0000)
#define MCF_FBCS_CSMR_BAM_16M (0xFF0000)
#define MCF_FBCS_CSMR_BAM_8M (0x7F0000)
#define MCF_FBCS_CSMR_BAM_4M (0x3F0000)
#define MCF_FBCS_CSMR_BAM_2M (0x1F0000)
#define MCF_FBCS_CSMR_BAM_1M (0xF0000)
#define MCF_FBCS_CSMR_BAM_1024K (0xF0000)
#define MCF_FBCS_CSMR_BAM_512K (0x70000)
#define MCF_FBCS_CSMR_BAM_256K (0x30000)
#define MCF_FBCS_CSMR_BAM_128K (0x10000)
#define MCF_FBCS_CSMR_BAM_64K (0)
/* Bit definitions and macros for MCF_FBCS_CSCR */
#define MCF_FBCS_CSCR_BSTW (0x8)
#define MCF_FBCS_CSCR_BSTR (0x10)
#define MCF_FBCS_CSCR_BEM (0x20)
#define MCF_FBCS_CSCR_PS(x) (((x)&0x3)<<0x6)
#define MCF_FBCS_CSCR_PS_32 (0)
#define MCF_FBCS_CSCR_PS_8 (0x40)
#define MCF_FBCS_CSCR_PS_16 (0x80)
#define MCF_FBCS_CSCR_AA (0x100)
#define MCF_FBCS_CSCR_WS(x) (((x)&0x3F)<<0xA)
#define MCF_FBCS_CSCR_WRAH(x) (((x)&0x3)<<0x10)
#define MCF_FBCS_CSCR_RDAH(x) (((x)&0x3)<<0x12)
#define MCF_FBCS_CSCR_ASET(x) (((x)&0x3)<<0x14)
#define MCF_FBCS_CSCR_SWSEN (0x800000)
#define MCF_FBCS_CSCR_SWS(x) (((x)&0x3F)<<0x1A)
#endif /* __MCF5475_FBCS_H__ */

680
tos/jtagwait/include/MCF5475_FEC.h
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@@ -1,680 +0,0 @@
/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.81
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF5475_FEC_H__
#define __MCF5475_FEC_H__
/*********************************************************************
*
* Fast Ethernet Controller(FEC)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_FEC0_EIR (*(volatile uint32_t*)(&_MBAR[0x9004]))
#define MCF_FEC0_EIMR (*(volatile uint32_t*)(&_MBAR[0x9008]))
#define MCF_FEC0_ECR (*(volatile uint32_t*)(&_MBAR[0x9024]))
#define MCF_FEC0_MMFR (*(volatile uint32_t*)(&_MBAR[0x9040]))
#define MCF_FEC0_MSCR (*(volatile uint32_t*)(&_MBAR[0x9044]))
#define MCF_FEC0_MIBC (*(volatile uint32_t*)(&_MBAR[0x9064]))
#define MCF_FEC0_RCR (*(volatile uint32_t*)(&_MBAR[0x9084]))
#define MCF_FEC0_RHR (*(volatile uint32_t*)(&_MBAR[0x9088]))
#define MCF_FEC0_TCR (*(volatile uint32_t*)(&_MBAR[0x90C4]))
#define MCF_FEC0_PALR (*(volatile uint32_t*)(&_MBAR[0x90E4]))
#define MCF_FEC0_PAHR (*(volatile uint32_t*)(&_MBAR[0x90E8]))
#define MCF_FEC0_OPD (*(volatile uint32_t*)(&_MBAR[0x90EC]))
#define MCF_FEC0_IAUR (*(volatile uint32_t*)(&_MBAR[0x9118]))
#define MCF_FEC0_IALR (*(volatile uint32_t*)(&_MBAR[0x911C]))
#define MCF_FEC0_GAUR (*(volatile uint32_t*)(&_MBAR[0x9120]))
#define MCF_FEC0_GALR (*(volatile uint32_t*)(&_MBAR[0x9124]))
#define MCF_FEC0_FECTFWR (*(volatile uint32_t*)(&_MBAR[0x9144]))
#define MCF_FEC0_FECRFDR (*(volatile uint32_t*)(&_MBAR[0x9184]))
#define MCF_FEC0_FECRFSR (*(volatile uint32_t*)(&_MBAR[0x9188]))
#define MCF_FEC0_FECRFCR (*(volatile uint32_t*)(&_MBAR[0x918C]))
#define MCF_FEC0_FECRLRFP (*(volatile uint32_t*)(&_MBAR[0x9190]))
#define MCF_FEC0_FECRLWFP (*(volatile uint32_t*)(&_MBAR[0x9194]))
#define MCF_FEC0_FECRFAR (*(volatile uint32_t*)(&_MBAR[0x9198]))
#define MCF_FEC0_FECRFRP (*(volatile uint32_t*)(&_MBAR[0x919C]))
#define MCF_FEC0_FECRFWP (*(volatile uint32_t*)(&_MBAR[0x91A0]))
#define MCF_FEC0_FECTFDR (*(volatile uint32_t*)(&_MBAR[0x91A4]))
#define MCF_FEC0_FECTFSR (*(volatile uint32_t*)(&_MBAR[0x91A8]))
#define MCF_FEC0_FECTFCR (*(volatile uint32_t*)(&_MBAR[0x91AC]))
#define MCF_FEC0_FECTLRFP (*(volatile uint32_t*)(&_MBAR[0x91B0]))
#define MCF_FEC0_FECTLWFP (*(volatile uint32_t*)(&_MBAR[0x91B4]))
#define MCF_FEC0_FECTFAR (*(volatile uint32_t*)(&_MBAR[0x91B8]))
#define MCF_FEC0_FECTFRP (*(volatile uint32_t*)(&_MBAR[0x91BC]))
#define MCF_FEC0_FECTFWP (*(volatile uint32_t*)(&_MBAR[0x91C0]))
#define MCF_FEC0_FECFRST (*(volatile uint32_t*)(&_MBAR[0x91C4]))
#define MCF_FEC0_FECCTCWR (*(volatile uint32_t*)(&_MBAR[0x91C8]))
#define MCF_FEC0_RMON_T_DROP (*(volatile uint32_t*)(&_MBAR[0x9200]))
#define MCF_FEC0_RMON_T_PACKETS (*(volatile uint32_t*)(&_MBAR[0x9204]))
#define MCF_FEC0_RMON_T_BC_PKT (*(volatile uint32_t*)(&_MBAR[0x9208]))
#define MCF_FEC0_RMON_T_MC_PKT (*(volatile uint32_t*)(&_MBAR[0x920C]))
#define MCF_FEC0_RMON_T_CRC_ALIGN (*(volatile uint32_t*)(&_MBAR[0x9210]))
#define MCF_FEC0_RMON_T_UNDERSIZE (*(volatile uint32_t*)(&_MBAR[0x9214]))
#define MCF_FEC0_RMON_T_OVERSIZE (*(volatile uint32_t*)(&_MBAR[0x9218]))
#define MCF_FEC0_RMON_T_FRAG (*(volatile uint32_t*)(&_MBAR[0x921C]))
#define MCF_FEC0_RMON_T_JAB (*(volatile uint32_t*)(&_MBAR[0x9220]))
#define MCF_FEC0_RMON_T_COL (*(volatile uint32_t*)(&_MBAR[0x9224]))
#define MCF_FEC0_RMON_T_P64 (*(volatile uint32_t*)(&_MBAR[0x9228]))
#define MCF_FEC0_RMON_T_P65TO127 (*(volatile uint32_t*)(&_MBAR[0x922C]))
#define MCF_FEC0_RMON_T_P128TO255 (*(volatile uint32_t*)(&_MBAR[0x9230]))
#define MCF_FEC0_RMON_T_P256TO511 (*(volatile uint32_t*)(&_MBAR[0x9234]))
#define MCF_FEC0_RMON_T_P512TO1023 (*(volatile uint32_t*)(&_MBAR[0x9238]))
#define MCF_FEC0_RMON_T_P1024TO2047 (*(volatile uint32_t*)(&_MBAR[0x923C]))
#define MCF_FEC0_RMON_T_P_GTE2048 (*(volatile uint32_t*)(&_MBAR[0x9240]))
#define MCF_FEC0_RMON_T_OCTETS (*(volatile uint32_t*)(&_MBAR[0x9244]))
#define MCF_FEC0_IEEE_T_DROP (*(volatile uint32_t*)(&_MBAR[0x9248]))
#define MCF_FEC0_IEEE_T_FRAME_OK (*(volatile uint32_t*)(&_MBAR[0x924C]))
#define MCF_FEC0_IEEE_T_1COL (*(volatile uint32_t*)(&_MBAR[0x9250]))
#define MCF_FEC0_IEEE_T_MCOL (*(volatile uint32_t*)(&_MBAR[0x9254]))
#define MCF_FEC0_IEEE_T_DEF (*(volatile uint32_t*)(&_MBAR[0x9258]))
#define MCF_FEC0_IEEE_T_LCOL (*(volatile uint32_t*)(&_MBAR[0x925C]))
#define MCF_FEC0_IEEE_T_EXCOL (*(volatile uint32_t*)(&_MBAR[0x9260]))
#define MCF_FEC0_IEEE_T_MACERR (*(volatile uint32_t*)(&_MBAR[0x9264]))
#define MCF_FEC0_IEEE_T_CSERR (*(volatile uint32_t*)(&_MBAR[0x9268]))
#define MCF_FEC0_IEEE_T_SQE (*(volatile uint32_t*)(&_MBAR[0x926C]))
#define MCF_FEC0_IEEE_T_FDXFC (*(volatile uint32_t*)(&_MBAR[0x9270]))
#define MCF_FEC0_IEEE_T_OCTETS_OK (*(volatile uint32_t*)(&_MBAR[0x9274]))
#define MCF_FEC0_RMON_R_DROP (*(volatile uint32_t*)(&_MBAR[0x9280]))
#define MCF_FEC0_RMON_R_PACKETS (*(volatile uint32_t*)(&_MBAR[0x9284]))
#define MCF_FEC0_RMON_R_BC_PKT (*(volatile uint32_t*)(&_MBAR[0x9288]))
#define MCF_FEC0_RMON_R_MC_PKT (*(volatile uint32_t*)(&_MBAR[0x928C]))
#define MCF_FEC0_RMON_R_CRC_ALIGN (*(volatile uint32_t*)(&_MBAR[0x9290]))
#define MCF_FEC0_RMON_R_UNDERSIZE (*(volatile uint32_t*)(&_MBAR[0x9294]))
#define MCF_FEC0_RMON_R_OVERSIZE (*(volatile uint32_t*)(&_MBAR[0x9298]))
#define MCF_FEC0_RMON_R_FRAG (*(volatile uint32_t*)(&_MBAR[0x929C]))
#define MCF_FEC0_RMON_R_JAB (*(volatile uint32_t*)(&_MBAR[0x92A0]))
#define MCF_FEC0_RMON_R_RESVD_0 (*(volatile uint32_t*)(&_MBAR[0x92A4]))
#define MCF_FEC0_RMON_R_P64 (*(volatile uint32_t*)(&_MBAR[0x92A8]))
#define MCF_FEC0_RMON_R_P65TO127 (*(volatile uint32_t*)(&_MBAR[0x92AC]))
#define MCF_FEC0_RMON_R_P128TO255 (*(volatile uint32_t*)(&_MBAR[0x92B0]))
#define MCF_FEC0_RMON_R_P256TO511 (*(volatile uint32_t*)(&_MBAR[0x92B4]))
#define MCF_FEC0_RMON_R_P512TO1023 (*(volatile uint32_t*)(&_MBAR[0x92B8]))
#define MCF_FEC0_RMON_R_P1024TO2047 (*(volatile uint32_t*)(&_MBAR[0x92BC]))
#define MCF_FEC0_RMON_R_P_GTE2048 (*(volatile uint32_t*)(&_MBAR[0x92C0]))
#define MCF_FEC0_RMON_R_OCTETS (*(volatile uint32_t*)(&_MBAR[0x92C4]))
#define MCF_FEC0_IEEE_R_DROP (*(volatile uint32_t*)(&_MBAR[0x92C8]))
#define MCF_FEC0_IEEE_R_FRAME_OK (*(volatile uint32_t*)(&_MBAR[0x92CC]))
#define MCF_FEC0_IEEE_R_CRC (*(volatile uint32_t*)(&_MBAR[0x92D0]))
#define MCF_FEC0_IEEE_R_ALIGN (*(volatile uint32_t*)(&_MBAR[0x92D4]))
#define MCF_FEC0_IEEE_R_MACERR (*(volatile uint32_t*)(&_MBAR[0x92D8]))
#define MCF_FEC0_IEEE_R_FDXFC (*(volatile uint32_t*)(&_MBAR[0x92DC]))
#define MCF_FEC0_IEEE_R_OCTETS_OK (*(volatile uint32_t*)(&_MBAR[0x92E0]))
#define MCF_FEC1_EIR (*(volatile uint32_t*)(&_MBAR[0x9804]))
#define MCF_FEC1_EIMR (*(volatile uint32_t*)(&_MBAR[0x9808]))
#define MCF_FEC1_ECR (*(volatile uint32_t*)(&_MBAR[0x9824]))
#define MCF_FEC1_MMFR (*(volatile uint32_t*)(&_MBAR[0x9840]))
#define MCF_FEC1_MSCR (*(volatile uint32_t*)(&_MBAR[0x9844]))
#define MCF_FEC1_MIBC (*(volatile uint32_t*)(&_MBAR[0x9864]))
#define MCF_FEC1_RCR (*(volatile uint32_t*)(&_MBAR[0x9884]))
#define MCF_FEC1_RHR (*(volatile uint32_t*)(&_MBAR[0x9888]))
#define MCF_FEC1_TCR (*(volatile uint32_t*)(&_MBAR[0x98C4]))
#define MCF_FEC1_PALR (*(volatile uint32_t*)(&_MBAR[0x98E4]))
#define MCF_FEC1_PAHR (*(volatile uint32_t*)(&_MBAR[0x98E8]))
#define MCF_FEC1_OPD (*(volatile uint32_t*)(&_MBAR[0x98EC]))
#define MCF_FEC1_IAUR (*(volatile uint32_t*)(&_MBAR[0x9918]))
#define MCF_FEC1_IALR (*(volatile uint32_t*)(&_MBAR[0x991C]))
#define MCF_FEC1_GAUR (*(volatile uint32_t*)(&_MBAR[0x9920]))
#define MCF_FEC1_GALR (*(volatile uint32_t*)(&_MBAR[0x9924]))
#define MCF_FEC1_FECTFWR (*(volatile uint32_t*)(&_MBAR[0x9944]))
#define MCF_FEC1_FECRFDR (*(volatile uint32_t*)(&_MBAR[0x9984]))
#define MCF_FEC1_FECRFSR (*(volatile uint32_t*)(&_MBAR[0x9988]))
#define MCF_FEC1_FECRFCR (*(volatile uint32_t*)(&_MBAR[0x998C]))
#define MCF_FEC1_FECRLRFP (*(volatile uint32_t*)(&_MBAR[0x9990]))
#define MCF_FEC1_FECRLWFP (*(volatile uint32_t*)(&_MBAR[0x9994]))
#define MCF_FEC1_FECRFAR (*(volatile uint32_t*)(&_MBAR[0x9998]))
#define MCF_FEC1_FECRFRP (*(volatile uint32_t*)(&_MBAR[0x999C]))
#define MCF_FEC1_FECRFWP (*(volatile uint32_t*)(&_MBAR[0x99A0]))
#define MCF_FEC1_FECTFDR (*(volatile uint32_t*)(&_MBAR[0x99A4]))
#define MCF_FEC1_FECTFSR (*(volatile uint32_t*)(&_MBAR[0x99A8]))
#define MCF_FEC1_FECTFCR (*(volatile uint32_t*)(&_MBAR[0x99AC]))
#define MCF_FEC1_FECTLRFP (*(volatile uint32_t*)(&_MBAR[0x99B0]))
#define MCF_FEC1_FECTLWFP (*(volatile uint32_t*)(&_MBAR[0x99B4]))
#define MCF_FEC1_FECTFAR (*(volatile uint32_t*)(&_MBAR[0x99B8]))
#define MCF_FEC1_FECTFRP (*(volatile uint32_t*)(&_MBAR[0x99BC]))
#define MCF_FEC1_FECTFWP (*(volatile uint32_t*)(&_MBAR[0x99C0]))
#define MCF_FEC1_FECFRST (*(volatile uint32_t*)(&_MBAR[0x99C4]))
#define MCF_FEC1_FECCTCWR (*(volatile uint32_t*)(&_MBAR[0x99C8]))
#define MCF_FEC1_RMON_T_DROP (*(volatile uint32_t*)(&_MBAR[0x9A00]))
#define MCF_FEC1_RMON_T_PACKETS (*(volatile uint32_t*)(&_MBAR[0x9A04]))
#define MCF_FEC1_RMON_T_BC_PKT (*(volatile uint32_t*)(&_MBAR[0x9A08]))
#define MCF_FEC1_RMON_T_MC_PKT (*(volatile uint32_t*)(&_MBAR[0x9A0C]))
#define MCF_FEC1_RMON_T_CRC_ALIGN (*(volatile uint32_t*)(&_MBAR[0x9A10]))
#define MCF_FEC1_RMON_T_UNDERSIZE (*(volatile uint32_t*)(&_MBAR[0x9A14]))
#define MCF_FEC1_RMON_T_OVERSIZE (*(volatile uint32_t*)(&_MBAR[0x9A18]))
#define MCF_FEC1_RMON_T_FRAG (*(volatile uint32_t*)(&_MBAR[0x9A1C]))
#define MCF_FEC1_RMON_T_JAB (*(volatile uint32_t*)(&_MBAR[0x9A20]))
#define MCF_FEC1_RMON_T_COL (*(volatile uint32_t*)(&_MBAR[0x9A24]))
#define MCF_FEC1_RMON_T_P64 (*(volatile uint32_t*)(&_MBAR[0x9A28]))
#define MCF_FEC1_RMON_T_P65TO127 (*(volatile uint32_t*)(&_MBAR[0x9A2C]))
#define MCF_FEC1_RMON_T_P128TO255 (*(volatile uint32_t*)(&_MBAR[0x9A30]))
#define MCF_FEC1_RMON_T_P256TO511 (*(volatile uint32_t*)(&_MBAR[0x9A34]))
#define MCF_FEC1_RMON_T_P512TO1023 (*(volatile uint32_t*)(&_MBAR[0x9A38]))
#define MCF_FEC1_RMON_T_P1024TO2047 (*(volatile uint32_t*)(&_MBAR[0x9A3C]))
#define MCF_FEC1_RMON_T_P_GTE2048 (*(volatile uint32_t*)(&_MBAR[0x9A40]))
#define MCF_FEC1_RMON_T_OCTETS (*(volatile uint32_t*)(&_MBAR[0x9A44]))
#define MCF_FEC1_IEEE_T_DROP (*(volatile uint32_t*)(&_MBAR[0x9A48]))
#define MCF_FEC1_IEEE_T_FRAME_OK (*(volatile uint32_t*)(&_MBAR[0x9A4C]))
#define MCF_FEC1_IEEE_T_1COL (*(volatile uint32_t*)(&_MBAR[0x9A50]))
#define MCF_FEC1_IEEE_T_MCOL (*(volatile uint32_t*)(&_MBAR[0x9A54]))
#define MCF_FEC1_IEEE_T_DEF (*(volatile uint32_t*)(&_MBAR[0x9A58]))
#define MCF_FEC1_IEEE_T_LCOL (*(volatile uint32_t*)(&_MBAR[0x9A5C]))
#define MCF_FEC1_IEEE_T_EXCOL (*(volatile uint32_t*)(&_MBAR[0x9A60]))
#define MCF_FEC1_IEEE_T_MACERR (*(volatile uint32_t*)(&_MBAR[0x9A64]))
#define MCF_FEC1_IEEE_T_CSERR (*(volatile uint32_t*)(&_MBAR[0x9A68]))
#define MCF_FEC1_IEEE_T_SQE (*(volatile uint32_t*)(&_MBAR[0x9A6C]))
#define MCF_FEC1_IEEE_T_FDXFC (*(volatile uint32_t*)(&_MBAR[0x9A70]))
#define MCF_FEC1_IEEE_T_OCTETS_OK (*(volatile uint32_t*)(&_MBAR[0x9A74]))
#define MCF_FEC1_RMON_R_DROP (*(volatile uint32_t*)(&_MBAR[0x9A80]))
#define MCF_FEC1_RMON_R_PACKETS (*(volatile uint32_t*)(&_MBAR[0x9A84]))
#define MCF_FEC1_RMON_R_BC_PKT (*(volatile uint32_t*)(&_MBAR[0x9A88]))
#define MCF_FEC1_RMON_R_MC_PKT (*(volatile uint32_t*)(&_MBAR[0x9A8C]))
#define MCF_FEC1_RMON_R_CRC_ALIGN (*(volatile uint32_t*)(&_MBAR[0x9A90]))
#define MCF_FEC1_RMON_R_UNDERSIZE (*(volatile uint32_t*)(&_MBAR[0x9A94]))
#define MCF_FEC1_RMON_R_OVERSIZE (*(volatile uint32_t*)(&_MBAR[0x9A98]))
#define MCF_FEC1_RMON_R_FRAG (*(volatile uint32_t*)(&_MBAR[0x9A9C]))
#define MCF_FEC1_RMON_R_JAB (*(volatile uint32_t*)(&_MBAR[0x9AA0]))
#define MCF_FEC1_RMON_R_RESVD_0 (*(volatile uint32_t*)(&_MBAR[0x9AA4]))
#define MCF_FEC1_RMON_R_P64 (*(volatile uint32_t*)(&_MBAR[0x9AA8]))
#define MCF_FEC1_RMON_R_P65TO127 (*(volatile uint32_t*)(&_MBAR[0x9AAC]))
#define MCF_FEC1_RMON_R_P128TO255 (*(volatile uint32_t*)(&_MBAR[0x9AB0]))
#define MCF_FEC1_RMON_R_P256TO511 (*(volatile uint32_t*)(&_MBAR[0x9AB4]))
#define MCF_FEC1_RMON_R_P512TO1023 (*(volatile uint32_t*)(&_MBAR[0x9AB8]))
#define MCF_FEC1_RMON_R_P1024TO2047 (*(volatile uint32_t*)(&_MBAR[0x9ABC]))
#define MCF_FEC1_RMON_R_P_GTE2048 (*(volatile uint32_t*)(&_MBAR[0x9AC0]))
#define MCF_FEC1_RMON_R_OCTETS (*(volatile uint32_t*)(&_MBAR[0x9AC4]))
#define MCF_FEC1_IEEE_R_DROP (*(volatile uint32_t*)(&_MBAR[0x9AC8]))
#define MCF_FEC1_IEEE_R_FRAME_OK (*(volatile uint32_t*)(&_MBAR[0x9ACC]))
#define MCF_FEC1_IEEE_R_CRC (*(volatile uint32_t*)(&_MBAR[0x9AD0]))
#define MCF_FEC1_IEEE_R_ALIGN (*(volatile uint32_t*)(&_MBAR[0x9AD4]))
#define MCF_FEC1_IEEE_R_MACERR (*(volatile uint32_t*)(&_MBAR[0x9AD8]))
#define MCF_FEC1_IEEE_R_FDXFC (*(volatile uint32_t*)(&_MBAR[0x9ADC]))
#define MCF_FEC1_IEEE_R_OCTETS_OK (*(volatile uint32_t*)(&_MBAR[0x9AE0]))
#define MCF_FEC_EIR(x) (*(volatile uint32_t*)(&_MBAR[0x9004 + ((x)*0x800)]))
#define MCF_FEC_EIMR(x) (*(volatile uint32_t*)(&_MBAR[0x9008 + ((x)*0x800)]))
#define MCF_FEC_ECR(x) (*(volatile uint32_t*)(&_MBAR[0x9024 + ((x)*0x800)]))
#define MCF_FEC_MMFR(x) (*(volatile uint32_t*)(&_MBAR[0x9040 + ((x)*0x800)]))
#define MCF_FEC_MSCR(x) (*(volatile uint32_t*)(&_MBAR[0x9044 + ((x)*0x800)]))
#define MCF_FEC_MIBC(x) (*(volatile uint32_t*)(&_MBAR[0x9064 + ((x)*0x800)]))
#define MCF_FEC_RCR(x) (*(volatile uint32_t*)(&_MBAR[0x9084 + ((x)*0x800)]))
#define MCF_FEC_RHR(x) (*(volatile uint32_t*)(&_MBAR[0x9088 + ((x)*0x800)]))
#define MCF_FEC_TCR(x) (*(volatile uint32_t*)(&_MBAR[0x90C4 + ((x)*0x800)]))
#define MCF_FEC_PALR(x) (*(volatile uint32_t*)(&_MBAR[0x90E4 + ((x)*0x800)]))
#define MCF_FEC_PAHR(x) (*(volatile uint32_t*)(&_MBAR[0x90E8 + ((x)*0x800)]))
#define MCF_FEC_OPD(x) (*(volatile uint32_t*)(&_MBAR[0x90EC + ((x)*0x800)]))
#define MCF_FEC_IAUR(x) (*(volatile uint32_t*)(&_MBAR[0x9118 + ((x)*0x800)]))
#define MCF_FEC_IALR(x) (*(volatile uint32_t*)(&_MBAR[0x911C + ((x)*0x800)]))
#define MCF_FEC_GAUR(x) (*(volatile uint32_t*)(&_MBAR[0x9120 + ((x)*0x800)]))
#define MCF_FEC_GALR(x) (*(volatile uint32_t*)(&_MBAR[0x9124 + ((x)*0x800)]))
#define MCF_FEC_FECTFWR(x) (*(volatile uint32_t*)(&_MBAR[0x9144 + ((x)*0x800)]))
#define MCF_FEC_FECRFDR(x) (*(volatile uint32_t*)(&_MBAR[0x9184 + ((x)*0x800)]))
#define MCF_FEC_FECRFSR(x) (*(volatile uint32_t*)(&_MBAR[0x9188 + ((x)*0x800)]))
#define MCF_FEC_FECRFCR(x) (*(volatile uint32_t*)(&_MBAR[0x918C + ((x)*0x800)]))
#define MCF_FEC_FECRLRFP(x) (*(volatile uint32_t*)(&_MBAR[0x9190 + ((x)*0x800)]))
#define MCF_FEC_FECRLWFP(x) (*(volatile uint32_t*)(&_MBAR[0x9194 + ((x)*0x800)]))
#define MCF_FEC_FECRFAR(x) (*(volatile uint32_t*)(&_MBAR[0x9198 + ((x)*0x800)]))
#define MCF_FEC_FECRFRP(x) (*(volatile uint32_t*)(&_MBAR[0x919C + ((x)*0x800)]))
#define MCF_FEC_FECRFWP(x) (*(volatile uint32_t*)(&_MBAR[0x91A0 + ((x)*0x800)]))
#define MCF_FEC_FECTFDR(x) (*(volatile uint32_t*)(&_MBAR[0x91A4 + ((x)*0x800)]))
#define MCF_FEC_FECTFSR(x) (*(volatile uint32_t*)(&_MBAR[0x91A8 + ((x)*0x800)]))
#define MCF_FEC_FECTFCR(x) (*(volatile uint32_t*)(&_MBAR[0x91AC + ((x)*0x800)]))
#define MCF_FEC_FECTLRFP(x) (*(volatile uint32_t*)(&_MBAR[0x91B0 + ((x)*0x800)]))
#define MCF_FEC_FECTLWFP(x) (*(volatile uint32_t*)(&_MBAR[0x91B4 + ((x)*0x800)]))
#define MCF_FEC_FECTFAR(x) (*(volatile uint32_t*)(&_MBAR[0x91B8 + ((x)*0x800)]))
#define MCF_FEC_FECTFRP(x) (*(volatile uint32_t*)(&_MBAR[0x91BC + ((x)*0x800)]))
#define MCF_FEC_FECTFWP(x) (*(volatile uint32_t*)(&_MBAR[0x91C0 + ((x)*0x800)]))
#define MCF_FEC_FECFRST(x) (*(volatile uint32_t*)(&_MBAR[0x91C4 + ((x)*0x800)]))
#define MCF_FEC_FECCTCWR(x) (*(volatile uint32_t*)(&_MBAR[0x91C8 + ((x)*0x800)]))
#define MCF_FEC_RMON_T_DROP(x) (*(volatile uint32_t*)(&_MBAR[0x9200 + ((x)*0x800)]))
#define MCF_FEC_RMON_T_PACKETS(x) (*(volatile uint32_t*)(&_MBAR[0x9204 + ((x)*0x800)]))
#define MCF_FEC_RMON_T_BC_PKT(x) (*(volatile uint32_t*)(&_MBAR[0x9208 + ((x)*0x800)]))
#define MCF_FEC_RMON_T_MC_PKT(x) (*(volatile uint32_t*)(&_MBAR[0x920C + ((x)*0x800)]))
#define MCF_FEC_RMON_T_CRC_ALIGN(x) (*(volatile uint32_t*)(&_MBAR[0x9210 + ((x)*0x800)]))
#define MCF_FEC_RMON_T_UNDERSIZE(x) (*(volatile uint32_t*)(&_MBAR[0x9214 + ((x)*0x800)]))
#define MCF_FEC_RMON_T_OVERSIZE(x) (*(volatile uint32_t*)(&_MBAR[0x9218 + ((x)*0x800)]))
#define MCF_FEC_RMON_T_FRAG(x) (*(volatile uint32_t*)(&_MBAR[0x921C + ((x)*0x800)]))
#define MCF_FEC_RMON_T_JAB(x) (*(volatile uint32_t*)(&_MBAR[0x9220 + ((x)*0x800)]))
#define MCF_FEC_RMON_T_COL(x) (*(volatile uint32_t*)(&_MBAR[0x9224 + ((x)*0x800)]))
#define MCF_FEC_RMON_T_P64(x) (*(volatile uint32_t*)(&_MBAR[0x9228 + ((x)*0x800)]))
#define MCF_FEC_RMON_T_P65TO127(x) (*(volatile uint32_t*)(&_MBAR[0x922C + ((x)*0x800)]))
#define MCF_FEC_RMON_T_P128TO255(x) (*(volatile uint32_t*)(&_MBAR[0x9230 + ((x)*0x800)]))
#define MCF_FEC_RMON_T_P256TO511(x) (*(volatile uint32_t*)(&_MBAR[0x9234 + ((x)*0x800)]))
#define MCF_FEC_RMON_T_P512TO1023(x) (*(volatile uint32_t*)(&_MBAR[0x9238 + ((x)*0x800)]))
#define MCF_FEC_RMON_T_P1024TO2047(x) (*(volatile uint32_t*)(&_MBAR[0x923C + ((x)*0x800)]))
#define MCF_FEC_RMON_T_P_GTE2048(x) (*(volatile uint32_t*)(&_MBAR[0x9240 + ((x)*0x800)]))
#define MCF_FEC_RMON_T_OCTETS(x) (*(volatile uint32_t*)(&_MBAR[0x9244 + ((x)*0x800)]))
#define MCF_FEC_IEEE_T_DROP(x) (*(volatile uint32_t*)(&_MBAR[0x9248 + ((x)*0x800)]))
#define MCF_FEC_IEEE_T_FRAME_OK(x) (*(volatile uint32_t*)(&_MBAR[0x924C + ((x)*0x800)]))
#define MCF_FEC_IEEE_T_1COL(x) (*(volatile uint32_t*)(&_MBAR[0x9250 + ((x)*0x800)]))
#define MCF_FEC_IEEE_T_MCOL(x) (*(volatile uint32_t*)(&_MBAR[0x9254 + ((x)*0x800)]))
#define MCF_FEC_IEEE_T_DEF(x) (*(volatile uint32_t*)(&_MBAR[0x9258 + ((x)*0x800)]))
#define MCF_FEC_IEEE_T_LCOL(x) (*(volatile uint32_t*)(&_MBAR[0x925C + ((x)*0x800)]))
#define MCF_FEC_IEEE_T_EXCOL(x) (*(volatile uint32_t*)(&_MBAR[0x9260 + ((x)*0x800)]))
#define MCF_FEC_IEEE_T_MACERR(x) (*(volatile uint32_t*)(&_MBAR[0x9264 + ((x)*0x800)]))
#define MCF_FEC_IEEE_T_CSERR(x) (*(volatile uint32_t*)(&_MBAR[0x9268 + ((x)*0x800)]))
#define MCF_FEC_IEEE_T_SQE(x) (*(volatile uint32_t*)(&_MBAR[0x926C + ((x)*0x800)]))
#define MCF_FEC_IEEE_T_FDXFC(x) (*(volatile uint32_t*)(&_MBAR[0x9270 + ((x)*0x800)]))
#define MCF_FEC_IEEE_T_OCTETS_OK(x) (*(volatile uint32_t*)(&_MBAR[0x9274 + ((x)*0x800)]))
#define MCF_FEC_RMON_R_DROP(x) (*(volatile uint32_t*)(&_MBAR[0x9280 + ((x)*0x800)]))
#define MCF_FEC_RMON_R_PACKETS(x) (*(volatile uint32_t*)(&_MBAR[0x9284 + ((x)*0x800)]))
#define MCF_FEC_RMON_R_BC_PKT(x) (*(volatile uint32_t*)(&_MBAR[0x9288 + ((x)*0x800)]))
#define MCF_FEC_RMON_R_MC_PKT(x) (*(volatile uint32_t*)(&_MBAR[0x928C + ((x)*0x800)]))
#define MCF_FEC_RMON_R_CRC_ALIGN(x) (*(volatile uint32_t*)(&_MBAR[0x9290 + ((x)*0x800)]))
#define MCF_FEC_RMON_R_UNDERSIZE(x) (*(volatile uint32_t*)(&_MBAR[0x9294 + ((x)*0x800)]))
#define MCF_FEC_RMON_R_OVERSIZE(x) (*(volatile uint32_t*)(&_MBAR[0x9298 + ((x)*0x800)]))
#define MCF_FEC_RMON_R_FRAG(x) (*(volatile uint32_t*)(&_MBAR[0x929C + ((x)*0x800)]))
#define MCF_FEC_RMON_R_JAB(x) (*(volatile uint32_t*)(&_MBAR[0x92A0 + ((x)*0x800)]))
#define MCF_FEC_RMON_R_RESVD_0(x) (*(volatile uint32_t*)(&_MBAR[0x92A4 + ((x)*0x800)]))
#define MCF_FEC_RMON_R_P64(x) (*(volatile uint32_t*)(&_MBAR[0x92A8 + ((x)*0x800)]))
#define MCF_FEC_RMON_R_P65TO127(x) (*(volatile uint32_t*)(&_MBAR[0x92AC + ((x)*0x800)]))
#define MCF_FEC_RMON_R_P128TO255(x) (*(volatile uint32_t*)(&_MBAR[0x92B0 + ((x)*0x800)]))
#define MCF_FEC_RMON_R_P256TO511(x) (*(volatile uint32_t*)(&_MBAR[0x92B4 + ((x)*0x800)]))
#define MCF_FEC_RMON_R_P512TO1023(x) (*(volatile uint32_t*)(&_MBAR[0x92B8 + ((x)*0x800)]))
#define MCF_FEC_RMON_R_P1024TO2047(x) (*(volatile uint32_t*)(&_MBAR[0x92BC + ((x)*0x800)]))
#define MCF_FEC_RMON_R_P_GTE2048(x) (*(volatile uint32_t*)(&_MBAR[0x92C0 + ((x)*0x800)]))
#define MCF_FEC_RMON_R_OCTETS(x) (*(volatile uint32_t*)(&_MBAR[0x92C4 + ((x)*0x800)]))
#define MCF_FEC_IEEE_R_DROP(x) (*(volatile uint32_t*)(&_MBAR[0x92C8 + ((x)*0x800)]))
#define MCF_FEC_IEEE_R_FRAME_OK(x) (*(volatile uint32_t*)(&_MBAR[0x92CC + ((x)*0x800)]))
#define MCF_FEC_IEEE_R_CRC(x) (*(volatile uint32_t*)(&_MBAR[0x92D0 + ((x)*0x800)]))
#define MCF_FEC_IEEE_R_ALIGN(x) (*(volatile uint32_t*)(&_MBAR[0x92D4 + ((x)*0x800)]))
#define MCF_FEC_IEEE_R_MACERR(x) (*(volatile uint32_t*)(&_MBAR[0x92D8 + ((x)*0x800)]))
#define MCF_FEC_IEEE_R_FDXFC(x) (*(volatile uint32_t*)(&_MBAR[0x92DC + ((x)*0x800)]))
#define MCF_FEC_IEEE_R_OCTETS_OK(x) (*(volatile uint32_t*)(&_MBAR[0x92E0 + ((x)*0x800)]))
/* Bit definitions and macros for MCF_FEC_EIR */
#define MCF_FEC_EIR_RFERR (0x20000)
#define MCF_FEC_EIR_XFERR (0x40000)
#define MCF_FEC_EIR_XFUN (0x80000)
#define MCF_FEC_EIR_RL (0x100000)
#define MCF_FEC_EIR_LC (0x200000)
#define MCF_FEC_EIR_MII (0x800000)
#define MCF_FEC_EIR_TXF (0x8000000)
#define MCF_FEC_EIR_GRA (0x10000000)
#define MCF_FEC_EIR_BABT (0x20000000)
#define MCF_FEC_EIR_BABR (0x40000000)
#define MCF_FEC_EIR_HBERR (0x80000000)
#define MCF_FEC_EIR_CLEAR_ALL (0xFFFFFFFF)
/* Bit definitions and macros for MCF_FEC_EIMR */
#define MCF_FEC_EIMR_RFERR (0x20000)
#define MCF_FEC_EIMR_XFERR (0x40000)
#define MCF_FEC_EIMR_XFUN (0x80000)
#define MCF_FEC_EIMR_RL (0x100000)
#define MCF_FEC_EIMR_LC (0x200000)
#define MCF_FEC_EIMR_MII (0x800000)
#define MCF_FEC_EIMR_TXF (0x8000000)
#define MCF_FEC_EIMR_GRA (0x10000000)
#define MCF_FEC_EIMR_BABT (0x20000000)
#define MCF_FEC_EIMR_BABR (0x40000000)
#define MCF_FEC_EIMR_HBERR (0x80000000)
#define MCF_FEC_EIMR_MASK_ALL (0)
#define MCF_FEC_EIMR_UNMASK_ALL (0xFFFFFFFF)
/* Bit definitions and macros for MCF_FEC_ECR */
#define MCF_FEC_ECR_RESET (0x1)
#define MCF_FEC_ECR_ETHER_EN (0x2)
/* Bit definitions and macros for MCF_FEC_MMFR */
#define MCF_FEC_MMFR_DATA(x) (((x)&0xFFFF)<<0)
#define MCF_FEC_MMFR_TA(x) (((x)&0x3)<<0x10)
#define MCF_FEC_MMFR_TA_10 (0x20000)
#define MCF_FEC_MMFR_RA(x) (((x)&0x1F)<<0x12)
#define MCF_FEC_MMFR_PA(x) (((x)&0x1F)<<0x17)
#define MCF_FEC_MMFR_OP(x) (((x)&0x3)<<0x1C)
#define MCF_FEC_MMFR_OP_READ (0x20000000)
#define MCF_FEC_MMFR_OP_WRITE (0x10000000)
#define MCF_FEC_MMFR_ST(x) (((x)&0x3)<<0x1E)
#define MCF_FEC_MMFR_ST_01 (0x40000000)
/* Bit definitions and macros for MCF_FEC_MSCR */
#define MCF_FEC_MSCR_MII_SPEED(x) (((x)&0x3F)<<0x1)
#define MCF_FEC_MSCR_DIS_PREAMBLE (0x80)
#define MCF_FEC_MSCR_MII_SPEED_133 (0x1B<<0x1)
#define MCF_FEC_MSCR_MII_SPEED_120 (0x18<<0x1)
#define MCF_FEC_MSCR_MII_SPEED_66 (0xE<<0x1)
#define MCF_FEC_MSCR_MII_SPEED_60 (0xC<<0x1)
/* Bit definitions and macros for MCF_FEC_MIBC */
#define MCF_FEC_MIBC_MIB_IDLE (0x40000000)
#define MCF_FEC_MIBC_MIB_DISABLE (0x80000000)
/* Bit definitions and macros for MCF_FEC_RCR */
#define MCF_FEC_RCR_LOOP (0x1)
#define MCF_FEC_RCR_DRT (0x2)
#define MCF_FEC_RCR_MII_MODE (0x4)
#define MCF_FEC_RCR_PROM (0x8)
#define MCF_FEC_RCR_BC_REJ (0x10)
#define MCF_FEC_RCR_FCE (0x20)
#define MCF_FEC_RCR_MAX_FL(x) (((x)&0x7FF)<<0x10)
/* Bit definitions and macros for MCF_FEC_RHR */
#define MCF_FEC_RHR_HASH(x) (((x)&0x3F)<<0x18)
#define MCF_FEC_RHR_MULTCAST (0x40000000)
#define MCF_FEC_RHR_FCE (0x80000000)
/* Bit definitions and macros for MCF_FEC_TCR */
#define MCF_FEC_TCR_GTS (0x1)
#define MCF_FEC_TCR_HBC (0x2)
#define MCF_FEC_TCR_FDEN (0x4)
#define MCF_FEC_TCR_TFC_PAUSE (0x8)
#define MCF_FEC_TCR_RFC_PAUSE (0x10)
/* Bit definitions and macros for MCF_FEC_PALR */
#define MCF_FEC_PALR_PADDR1(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_PAHR */
#define MCF_FEC_PAHR_TYPE(x) (((x)&0xFFFF)<<0)
#define MCF_FEC_PAHR_PADDR2(x) (((x)&0xFFFF)<<0x10)
/* Bit definitions and macros for MCF_FEC_OPD */
#define MCF_FEC_OPD_PAUSE_DUR(x) (((x)&0xFFFF)<<0)
#define MCF_FEC_OPD_OPCODE(x) (((x)&0xFFFF)<<0x10)
/* Bit definitions and macros for MCF_FEC_IAUR */
#define MCF_FEC_IAUR_IADDR1(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_IALR */
#define MCF_FEC_IALR_IADDR2(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_GAUR */
#define MCF_FEC_GAUR_GADDR1(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_GALR */
#define MCF_FEC_GALR_GADDR2(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_FECTFWR */
#define MCF_FEC_FECTFWR_X_WMRK(x) (((x)&0xF)<<0)
#define MCF_FEC_FECTFWR_X_WMRK_64 (0)
#define MCF_FEC_FECTFWR_X_WMRK_128 (0x1)
#define MCF_FEC_FECTFWR_X_WMRK_192 (0x2)
#define MCF_FEC_FECTFWR_X_WMRK_256 (0x3)
#define MCF_FEC_FECTFWR_X_WMRK_320 (0x4)
#define MCF_FEC_FECTFWR_X_WMRK_384 (0x5)
#define MCF_FEC_FECTFWR_X_WMRK_448 (0x6)
#define MCF_FEC_FECTFWR_X_WMRK_512 (0x7)
#define MCF_FEC_FECTFWR_X_WMRK_576 (0x8)
#define MCF_FEC_FECTFWR_X_WMRK_640 (0x9)
#define MCF_FEC_FECTFWR_X_WMRK_704 (0xA)
#define MCF_FEC_FECTFWR_X_WMRK_768 (0xB)
#define MCF_FEC_FECTFWR_X_WMRK_832 (0xC)
#define MCF_FEC_FECTFWR_X_WMRK_896 (0xD)
#define MCF_FEC_FECTFWR_X_WMRK_960 (0xE)
#define MCF_FEC_FECTFWR_X_WMRK_1024 (0xF)
/* Bit definitions and macros for MCF_FEC_FECRFDR */
#define MCF_FEC_FECRFDR_FIFO_DATA(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_FECRFSR */
#define MCF_FEC_FECRFSR_EMT (0x10000)
#define MCF_FEC_FECRFSR_ALARM (0x20000)
#define MCF_FEC_FECRFSR_FU (0x40000)
#define MCF_FEC_FECRFSR_FRMRDY (0x80000)
#define MCF_FEC_FECRFSR_OF (0x100000)
#define MCF_FEC_FECRFSR_UF (0x200000)
#define MCF_FEC_FECRFSR_RXW (0x400000)
#define MCF_FEC_FECRFSR_FAE (0x800000)
#define MCF_FEC_FECRFSR_FRM(x) (((x)&0xF)<<0x18)
#define MCF_FEC_FECRFSR_IP (0x80000000)
/* Bit definitions and macros for MCF_FEC_FECRFCR */
#define MCF_FEC_FECRFCR_COUNTER(x) (((x)&0xFFFF)<<0)
#define MCF_FEC_FECRFCR_OF_MSK (0x80000)
#define MCF_FEC_FECRFCR_UF_MSK (0x100000)
#define MCF_FEC_FECRFCR_RXW_MSK (0x200000)
#define MCF_FEC_FECRFCR_FAE_MSK (0x400000)
#define MCF_FEC_FECRFCR_IP_MSK (0x800000)
#define MCF_FEC_FECRFCR_GR(x) (((x)&0x7)<<0x18)
#define MCF_FEC_FECRFCR_FRMEN (0x8000000)
#define MCF_FEC_FECRFCR_TIMER (0x10000000)
/* Bit definitions and macros for MCF_FEC_FECRLRFP */
#define MCF_FEC_FECRLRFP_LRFP(x) (((x)&0x3FF)<<0)
/* Bit definitions and macros for MCF_FEC_FECRLWFP */
#define MCF_FEC_FECRLWFP_LWFP(x) (((x)&0x3FF)<<0)
/* Bit definitions and macros for MCF_FEC_FECRFAR */
#define MCF_FEC_FECRFAR_ALARM(x) (((x)&0x3FF)<<0)
/* Bit definitions and macros for MCF_FEC_FECRFRP */
#define MCF_FEC_FECRFRP_READ(x) (((x)&0x3FF)<<0)
/* Bit definitions and macros for MCF_FEC_FECRFWP */
#define MCF_FEC_FECRFWP_WRITE(x) (((x)&0x3FF)<<0)
/* Bit definitions and macros for MCF_FEC_FECTFDR */
#define MCF_FEC_FECTFDR_FIFO_DATA(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_FECTFSR */
#define MCF_FEC_FECTFSR_EMT (0x10000)
#define MCF_FEC_FECTFSR_ALARM (0x20000)
#define MCF_FEC_FECTFSR_FU (0x40000)
#define MCF_FEC_FECTFSR_FRMRDY (0x80000)
#define MCF_FEC_FECTFSR_OF (0x100000)
#define MCF_FEC_FECTFSR_UF (0x200000)
#define MCF_FEC_FECTFSR_FAE (0x800000)
#define MCF_FEC_FECTFSR_FRM(x) (((x)&0xF)<<0x18)
#define MCF_FEC_FECTFSR_TXW (0x40000000)
#define MCF_FEC_FECTFSR_IP (0x80000000)
/* Bit definitions and macros for MCF_FEC_FECTFCR */
#define MCF_FEC_FECTFCR_RESERVED (0x200000)
#define MCF_FEC_FECTFCR_COUNTER(x) (((x)&0xFFFF)<<0|0x200000)
#define MCF_FEC_FECTFCR_TXW_MASK (0x240000)
#define MCF_FEC_FECTFCR_OF_MSK (0x280000)
#define MCF_FEC_FECTFCR_UF_MSK (0x300000)
#define MCF_FEC_FECTFCR_FAE_MSK (0x600000)
#define MCF_FEC_FECTFCR_IP_MSK (0xA00000)
#define MCF_FEC_FECTFCR_GR(x) (((x)&0x7)<<0x18|0x200000)
#define MCF_FEC_FECTFCR_FRMEN (0x8200000)
#define MCF_FEC_FECTFCR_TIMER (0x10200000)
#define MCF_FEC_FECTFCR_WFR (0x20200000)
#define MCF_FEC_FECTFCR_WCTL (0x40200000)
/* Bit definitions and macros for MCF_FEC_FECTLRFP */
#define MCF_FEC_FECTLRFP_LRFP(x) (((x)&0x3FF)<<0)
/* Bit definitions and macros for MCF_FEC_FECTLWFP */
#define MCF_FEC_FECTLWFP_LWFP(x) (((x)&0x3FF)<<0)
/* Bit definitions and macros for MCF_FEC_FECTFAR */
#define MCF_FEC_FECTFAR_ALARM(x) (((x)&0x3FF)<<0)
/* Bit definitions and macros for MCF_FEC_FECTFRP */
#define MCF_FEC_FECTFRP_READ(x) (((x)&0x3FF)<<0)
/* Bit definitions and macros for MCF_FEC_FECTFWP */
#define MCF_FEC_FECTFWP_WRITE(x) (((x)&0x3FF)<<0)
/* Bit definitions and macros for MCF_FEC_FECFRST */
#define MCF_FEC_FECFRST_RST_CTL (0x1000000)
#define MCF_FEC_FECFRST_SW_RST (0x2000000)
/* Bit definitions and macros for MCF_FEC_FECCTCWR */
#define MCF_FEC_FECCTCWR_TFCW (0x1000000)
#define MCF_FEC_FECCTCWR_CRC (0x2000000)
/* Bit definitions and macros for MCF_FEC_RMON_T_DROP */
#define MCF_FEC_RMON_T_DROP_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_T_PACKETS */
#define MCF_FEC_RMON_T_PACKETS_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_T_BC_PKT */
#define MCF_FEC_RMON_T_BC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_T_MC_PKT */
#define MCF_FEC_RMON_T_MC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_T_CRC_ALIGN */
#define MCF_FEC_RMON_T_CRC_ALIGN_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_T_UNDERSIZE */
#define MCF_FEC_RMON_T_UNDERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_T_OVERSIZE */
#define MCF_FEC_RMON_T_OVERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_T_FRAG */
#define MCF_FEC_RMON_T_FRAG_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_T_JAB */
#define MCF_FEC_RMON_T_JAB_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_T_COL */
#define MCF_FEC_RMON_T_COL_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_T_P64 */
#define MCF_FEC_RMON_T_P64_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_T_P65TO127 */
#define MCF_FEC_RMON_T_P65TO127_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_T_P128TO255 */
#define MCF_FEC_RMON_T_P128TO255_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_T_P256TO511 */
#define MCF_FEC_RMON_T_P256TO511_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_T_P512TO1023 */
#define MCF_FEC_RMON_T_P512TO1023_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_T_P1024TO2047 */
#define MCF_FEC_RMON_T_P1024TO2047_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_T_P_GTE2048 */
#define MCF_FEC_RMON_T_P_GTE2048_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_T_OCTETS */
#define MCF_FEC_RMON_T_OCTETS_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_IEEE_T_DROP */
#define MCF_FEC_IEEE_T_DROP_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_IEEE_T_FRAME_OK */
#define MCF_FEC_IEEE_T_FRAME_OK_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_IEEE_T_1COL */
#define MCF_FEC_IEEE_T_1COL_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_IEEE_T_MCOL */
#define MCF_FEC_IEEE_T_MCOL_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_IEEE_T_DEF */
#define MCF_FEC_IEEE_T_DEF_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_IEEE_T_LCOL */
#define MCF_FEC_IEEE_T_LCOL_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_IEEE_T_EXCOL */
#define MCF_FEC_IEEE_T_EXCOL_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_IEEE_T_MACERR */
#define MCF_FEC_IEEE_T_MACERR_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_IEEE_T_CSERR */
#define MCF_FEC_IEEE_T_CSERR_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_IEEE_T_SQE */
#define MCF_FEC_IEEE_T_SQE_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_IEEE_T_FDXFC */
#define MCF_FEC_IEEE_T_FDXFC_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_IEEE_T_OCTETS_OK */
#define MCF_FEC_IEEE_T_OCTETS_OK_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_R_DROP */
#define MCF_FEC_RMON_R_DROP_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_R_PACKETS */
#define MCF_FEC_RMON_R_PACKETS_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_R_BC_PKT */
#define MCF_FEC_RMON_R_BC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_R_MC_PKT */
#define MCF_FEC_RMON_R_MC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_R_CRC_ALIGN */
#define MCF_FEC_RMON_R_CRC_ALIGN_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_R_UNDERSIZE */
#define MCF_FEC_RMON_R_UNDERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_R_OVERSIZE */
#define MCF_FEC_RMON_R_OVERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_R_FRAG */
#define MCF_FEC_RMON_R_FRAG_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_R_JAB */
#define MCF_FEC_RMON_R_JAB_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_R_RESVD_0 */
#define MCF_FEC_RMON_R_RESVD_0_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_R_P64 */
#define MCF_FEC_RMON_R_P64_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_R_P65TO127 */
#define MCF_FEC_RMON_R_P65TO127_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_R_P128TO255 */
#define MCF_FEC_RMON_R_P128TO255_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_R_P256TO511 */
#define MCF_FEC_RMON_R_P256TO511_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_R_P512TO1023 */
#define MCF_FEC_RMON_R_P512TO1023_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_R_P1024TO2047 */
#define MCF_FEC_RMON_R_P1024TO2047_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_R_P_GTE2048 */
#define MCF_FEC_RMON_R_P_GTE2048_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_RMON_R_OCTETS */
#define MCF_FEC_RMON_R_OCTETS_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_IEEE_R_DROP */
#define MCF_FEC_IEEE_R_DROP_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_IEEE_R_FRAME_OK */
#define MCF_FEC_IEEE_R_FRAME_OK_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_IEEE_R_CRC */
#define MCF_FEC_IEEE_R_CRC_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_IEEE_R_ALIGN */
#define MCF_FEC_IEEE_R_ALIGN_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_IEEE_R_MACERR */
#define MCF_FEC_IEEE_R_MACERR_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_IEEE_R_FDXFC */
#define MCF_FEC_IEEE_R_FDXFC_Value(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_FEC_IEEE_R_OCTETS_OK */
#define MCF_FEC_IEEE_R_OCTETS_OK_Value(x) (((x)&0xFFFFFFFF)<<0)
#endif /* __MCF5475_FEC_H__ */

543
tos/jtagwait/include/MCF5475_GPIO.h
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@@ -1,543 +0,0 @@
/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.81
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF5475_GPIO_H__
#define __MCF5475_GPIO_H__
/*********************************************************************
*
* General Purpose I/O (GPIO)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_GPIO_PODR_FBCTL (*(volatile uint8_t *)(&_MBAR[0xA00]))
#define MCF_GPIO_PDDR_FBCTL (*(volatile uint8_t *)(&_MBAR[0xA10]))
#define MCF_GPIO_PPDSDR_FBCTL (*(volatile uint8_t *)(&_MBAR[0xA20]))
#define MCF_GPIO_PCLRR_FBCTL (*(volatile uint8_t *)(&_MBAR[0xA30]))
#define MCF_GPIO_PODR_FBCS (*(volatile uint8_t *)(&_MBAR[0xA01]))
#define MCF_GPIO_PDDR_FBCS (*(volatile uint8_t *)(&_MBAR[0xA11]))
#define MCF_GPIO_PPDSDR_FBCS (*(volatile uint8_t *)(&_MBAR[0xA21]))
#define MCF_GPIO_PCLRR_FBCS (*(volatile uint8_t *)(&_MBAR[0xA31]))
#define MCF_GPIO_PODR_DMA (*(volatile uint8_t *)(&_MBAR[0xA02]))
#define MCF_GPIO_PDDR_DMA (*(volatile uint8_t *)(&_MBAR[0xA12]))
#define MCF_GPIO_PPDSDR_DMA (*(volatile uint8_t *)(&_MBAR[0xA22]))
#define MCF_GPIO_PCLRR_DMA (*(volatile uint8_t *)(&_MBAR[0xA32]))
#define MCF_GPIO_PODR_FEC0H (*(volatile uint8_t *)(&_MBAR[0xA04]))
#define MCF_GPIO_PDDR_FEC0H (*(volatile uint8_t *)(&_MBAR[0xA14]))
#define MCF_GPIO_PPDSDR_FEC0H (*(volatile uint8_t *)(&_MBAR[0xA24]))
#define MCF_GPIO_PCLRR_FEC0H (*(volatile uint8_t *)(&_MBAR[0xA34]))
#define MCF_GPIO_PODR_FEC0L (*(volatile uint8_t *)(&_MBAR[0xA05]))
#define MCF_GPIO_PDDR_FEC0L (*(volatile uint8_t *)(&_MBAR[0xA15]))
#define MCF_GPIO_PPDSDR_FEC0L (*(volatile uint8_t *)(&_MBAR[0xA25]))
#define MCF_GPIO_PCLRR_FEC0L (*(volatile uint8_t *)(&_MBAR[0xA35]))
#define MCF_GPIO_PODR_FEC1H (*(volatile uint8_t *)(&_MBAR[0xA06]))
#define MCF_GPIO_PDDR_FEC1H (*(volatile uint8_t *)(&_MBAR[0xA16]))
#define MCF_GPIO_PPDSDR_FEC1H (*(volatile uint8_t *)(&_MBAR[0xA26]))
#define MCF_GPIO_PCLRR_FEC1H (*(volatile uint8_t *)(&_MBAR[0xA36]))
#define MCF_GPIO_PODR_FEC1L (*(volatile uint8_t *)(&_MBAR[0xA07]))
#define MCF_GPIO_PDDR_FEC1L (*(volatile uint8_t *)(&_MBAR[0xA17]))
#define MCF_GPIO_PPDSDR_FEC1L (*(volatile uint8_t *)(&_MBAR[0xA27]))
#define MCF_GPIO_PCLRR_FEC1L (*(volatile uint8_t *)(&_MBAR[0xA37]))
#define MCF_GPIO_PODR_FECI2C (*(volatile uint8_t *)(&_MBAR[0xA08]))
#define MCF_GPIO_PDDR_FECI2C (*(volatile uint8_t *)(&_MBAR[0xA18]))
#define MCF_GPIO_PPDSDR_FECI2C (*(volatile uint8_t *)(&_MBAR[0xA28]))
#define MCF_GPIO_PCLRR_FECI2C (*(volatile uint8_t *)(&_MBAR[0xA38]))
#define MCF_GPIO_PODR_PCIBG (*(volatile uint8_t *)(&_MBAR[0xA09]))
#define MCF_GPIO_PDDR_PCIBG (*(volatile uint8_t *)(&_MBAR[0xA19]))
#define MCF_GPIO_PPDSDR_PCIBG (*(volatile uint8_t *)(&_MBAR[0xA29]))
#define MCF_GPIO_PCLRR_PCIBG (*(volatile uint8_t *)(&_MBAR[0xA39]))
#define MCF_GPIO_PODR_PCIBR (*(volatile uint8_t *)(&_MBAR[0xA0A]))
#define MCF_GPIO_PDDR_PCIBR (*(volatile uint8_t *)(&_MBAR[0xA1A]))
#define MCF_GPIO_PPDSDR_PCIBR (*(volatile uint8_t *)(&_MBAR[0xA2A]))
#define MCF_GPIO_PCLRR_PCIBR (*(volatile uint8_t *)(&_MBAR[0xA3A]))
#define MCF_GPIO2_PODR_PSC3PSC (*(volatile uint8_t *)(&_MBAR[0xA0C]))
#define MCF_GPIO2_PDDR_PSC3PSC (*(volatile uint8_t *)(&_MBAR[0xA1C]))
#define MCF_GPIO2_PPDSDR_PSC3PSC (*(volatile uint8_t *)(&_MBAR[0xA2C]))
#define MCF_GPIO2_PCLRR_PSC3PSC (*(volatile uint8_t *)(&_MBAR[0xA3C]))
#define MCF_GPIO0_PODR_PSC1PSC (*(volatile uint8_t *)(&_MBAR[0xA0D]))
#define MCF_GPIO0_PDDR_PSC1PSC (*(volatile uint8_t *)(&_MBAR[0xA1D]))
#define MCF_GPIO0_PPDSDR_PSC1PSC (*(volatile uint8_t *)(&_MBAR[0xA2D]))
#define MCF_GPIO0_PCLRR_PSC1PSC (*(volatile uint8_t *)(&_MBAR[0xA3D]))
#define MCF_GPIO_PODR_DSPI (*(volatile uint8_t *)(&_MBAR[0xA0E]))
#define MCF_GPIO_PDDR_DSPI (*(volatile uint8_t *)(&_MBAR[0xA1E]))
#define MCF_GPIO_PPDSDR_DSPI (*(volatile uint8_t *)(&_MBAR[0xA2E]))
#define MCF_GPIO_PCLRR_DSPI (*(volatile uint8_t *)(&_MBAR[0xA3E]))
/* Bit definitions and macros for MCF_GPIO_PODR_FBCTL */
#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL0 (0x1)
#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL1 (0x2)
#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL2 (0x4)
#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL3 (0x8)
#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL4 (0x10)
#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL5 (0x20)
#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL6 (0x40)
#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PDDR_FBCTL */
#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL0 (0x1)
#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL1 (0x2)
#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL2 (0x4)
#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL3 (0x8)
#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL4 (0x10)
#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL5 (0x20)
#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL6 (0x40)
#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCTL */
#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL0 (0x1)
#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL1 (0x2)
#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL2 (0x4)
#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL3 (0x8)
#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL4 (0x10)
#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL5 (0x20)
#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL6 (0x40)
#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCTL */
#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL0 (0x1)
#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL1 (0x2)
#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL2 (0x4)
#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL3 (0x8)
#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL4 (0x10)
#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL5 (0x20)
#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL6 (0x40)
#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PODR_FBCS */
#define MCF_GPIO_PODR_FBCS_PODR_FBCS1 (0x2)
#define MCF_GPIO_PODR_FBCS_PODR_FBCS2 (0x4)
#define MCF_GPIO_PODR_FBCS_PODR_FBCS3 (0x8)
#define MCF_GPIO_PODR_FBCS_PODR_FBCS4 (0x10)
#define MCF_GPIO_PODR_FBCS_PODR_FBCS5 (0x20)
/* Bit definitions and macros for MCF_GPIO_PDDR_FBCS */
#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS1 (0x2)
#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS2 (0x4)
#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS3 (0x8)
#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS4 (0x10)
#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS5 (0x20)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCS */
#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS1 (0x2)
#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS2 (0x4)
#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS3 (0x8)
#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS4 (0x10)
#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS5 (0x20)
/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCS */
#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS1 (0x2)
#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS2 (0x4)
#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS3 (0x8)
#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS4 (0x10)
#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS5 (0x20)
/* Bit definitions and macros for MCF_GPIO_PODR_DMA */
#define MCF_GPIO_PODR_DMA_PODR_DMA0 (0x1)
#define MCF_GPIO_PODR_DMA_PODR_DMA1 (0x2)
#define MCF_GPIO_PODR_DMA_PODR_DMA2 (0x4)
#define MCF_GPIO_PODR_DMA_PODR_DMA3 (0x8)
/* Bit definitions and macros for MCF_GPIO_PDDR_DMA */
#define MCF_GPIO_PDDR_DMA_PDDR_DMA0 (0x1)
#define MCF_GPIO_PDDR_DMA_PDDR_DMA1 (0x2)
#define MCF_GPIO_PDDR_DMA_PDDR_DMA2 (0x4)
#define MCF_GPIO_PDDR_DMA_PDDR_DMA3 (0x8)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_DMA */
#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA0 (0x1)
#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA1 (0x2)
#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA2 (0x4)
#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA3 (0x8)
/* Bit definitions and macros for MCF_GPIO_PCLRR_DMA */
#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA0 (0x1)
#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA1 (0x2)
#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA2 (0x4)
#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA3 (0x8)
/* Bit definitions and macros for MCF_GPIO_PODR_FEC0H */
#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H0 (0x1)
#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H1 (0x2)
#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H2 (0x4)
#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H3 (0x8)
#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H4 (0x10)
#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H5 (0x20)
#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H6 (0x40)
#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0H */
#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H0 (0x1)
#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H1 (0x2)
#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H2 (0x4)
#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H3 (0x8)
#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H4 (0x10)
#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H5 (0x20)
#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H6 (0x40)
#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0H */
#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H0 (0x1)
#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H1 (0x2)
#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H2 (0x4)
#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H3 (0x8)
#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H4 (0x10)
#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H5 (0x20)
#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H6 (0x40)
#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0H */
#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H0 (0x1)
#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H1 (0x2)
#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H2 (0x4)
#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H3 (0x8)
#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H4 (0x10)
#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H5 (0x20)
#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H6 (0x40)
#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PODR_FEC0L */
#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L0 (0x1)
#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L1 (0x2)
#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L2 (0x4)
#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L3 (0x8)
#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L4 (0x10)
#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L5 (0x20)
#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L6 (0x40)
#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0L */
#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L0 (0x1)
#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L1 (0x2)
#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L2 (0x4)
#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L3 (0x8)
#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L4 (0x10)
#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L5 (0x20)
#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L6 (0x40)
#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0L */
#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L0 (0x1)
#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L1 (0x2)
#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L2 (0x4)
#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L3 (0x8)
#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L4 (0x10)
#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L5 (0x20)
#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L6 (0x40)
#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0L */
#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L0 (0x1)
#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L1 (0x2)
#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L2 (0x4)
#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L3 (0x8)
#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L4 (0x10)
#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L5 (0x20)
#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L6 (0x40)
#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PODR_FEC1H */
#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H0 (0x1)
#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H1 (0x2)
#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H2 (0x4)
#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H3 (0x8)
#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H4 (0x10)
#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H5 (0x20)
#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H6 (0x40)
#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1H */
#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H0 (0x1)
#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H1 (0x2)
#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H2 (0x4)
#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H3 (0x8)
#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H4 (0x10)
#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H5 (0x20)
#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H6 (0x40)
#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1H */
#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H0 (0x1)
#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H1 (0x2)
#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H2 (0x4)
#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H3 (0x8)
#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H4 (0x10)
#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H5 (0x20)
#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H6 (0x40)
#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1H */
#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H0 (0x1)
#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H1 (0x2)
#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H2 (0x4)
#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H3 (0x8)
#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H4 (0x10)
#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H5 (0x20)
#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H6 (0x40)
#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PODR_FEC1L */
#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L0 (0x1)
#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L1 (0x2)
#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L2 (0x4)
#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L3 (0x8)
#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L4 (0x10)
#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L5 (0x20)
#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L6 (0x40)
#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1L */
#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L0 (0x1)
#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L1 (0x2)
#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L2 (0x4)
#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L3 (0x8)
#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4 (0x10)
#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L5 (0x20)
#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L6 (0x40)
#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1L */
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L0 (0x1)
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L1 (0x2)
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L2 (0x4)
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L3 (0x8)
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L4 (0x10)
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L5 (0x20)
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L6 (0x40)
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1L */
#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L0 (0x1)
#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L1 (0x2)
#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L2 (0x4)
#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L3 (0x8)
#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L4 (0x10)
#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L5 (0x20)
#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L6 (0x40)
#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L7 (0x80)
/* Bit definitions and macros for MCF_GPIO_PODR_FECI2C */
#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C0 (0x1)
#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C1 (0x2)
#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C2 (0x4)
#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C3 (0x8)
/* Bit definitions and macros for MCF_GPIO_PDDR_FECI2C */
#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0 (0x1)
#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1 (0x2)
#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C2 (0x4)
#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C3 (0x8)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECI2C */
#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C0 (0x1)
#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C1 (0x2)
#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C2 (0x4)
#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C3 (0x8)
/* Bit definitions and macros for MCF_GPIO_PCLRR_FECI2C */
#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C0 (0x1)
#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C1 (0x2)
#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C2 (0x4)
#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C3 (0x8)
/* Bit definitions and macros for MCF_GPIO_PODR_PCIBG */
#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG0 (0x1)
#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG1 (0x2)
#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG2 (0x4)
#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG3 (0x8)
#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG4 (0x10)
/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBG */
#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG0 (0x1)
#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG1 (0x2)
#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG2 (0x4)
#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG3 (0x8)
#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG4 (0x10)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBG */
#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG0 (0x1)
#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG1 (0x2)
#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG2 (0x4)
#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG3 (0x8)
#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG4 (0x10)
/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBG */
#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG0 (0x1)
#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG1 (0x2)
#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG2 (0x4)
#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG3 (0x8)
#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG4 (0x10)
/* Bit definitions and macros for MCF_GPIO_PODR_PCIBR */
#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR0 (0x1)
#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR1 (0x2)
#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR2 (0x4)
#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR3 (0x8)
#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR4 (0x10)
/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBR */
#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR0 (0x1)
#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR1 (0x2)
#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR2 (0x4)
#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR3 (0x8)
#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR4 (0x10)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBR */
#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR0 (0x1)
#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR1 (0x2)
#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR2 (0x4)
#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR3 (0x8)
#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR4 (0x10)
/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBR */
#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR0 (0x1)
#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR1 (0x2)
#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR2 (0x4)
#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR3 (0x8)
#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR4 (0x10)
/* Bit definitions and macros for MCF_GPIO_PODR_PSC3PSC */
#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC20 (0x1)
#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC21 (0x2)
#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC22 (0x4)
#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC23 (0x8)
#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC24 (0x10)
#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC25 (0x20)
#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC26 (0x40)
#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC27 (0x80)
/* Bit definitions and macros for MCF_GPIO_PDDR_PSC3PSC */
#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC20 (0x1)
#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC21 (0x2)
#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC22 (0x4)
#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC23 (0x8)
#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC24 (0x10)
#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC25 (0x20)
#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC26 (0x40)
#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC27 (0x80)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC3PSC */
#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC20 (0x1)
#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC21 (0x2)
#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC22 (0x4)
#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC23 (0x8)
#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC24 (0x10)
#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC25 (0x20)
#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC26 (0x40)
#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC27 (0x80)
/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC3PSC */
#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC20 (0x1)
#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC21 (0x2)
#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC22 (0x4)
#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC23 (0x8)
#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC24 (0x10)
#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC25 (0x20)
#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC26 (0x40)
#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC27 (0x80)
/* Bit definitions and macros for MCF_GPIO_PODR_PSC1PSC */
#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC00 (0x1)
#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC01 (0x2)
#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC02 (0x4)
#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC03 (0x8)
#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC04 (0x10)
#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC05 (0x20)
#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC06 (0x40)
#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC07 (0x80)
/* Bit definitions and macros for MCF_GPIO_PDDR_PSC1PSC */
#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC00 (0x1)
#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC01 (0x2)
#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC02 (0x4)
#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC03 (0x8)
#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC04 (0x10)
#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC05 (0x20)
#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC06 (0x40)
#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC07 (0x80)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC1PSC */
#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC00 (0x1)
#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC01 (0x2)
#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC02 (0x4)
#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC03 (0x8)
#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC04 (0x10)
#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC05 (0x20)
#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC06 (0x40)
#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC07 (0x80)
/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC1PSC */
#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC00 (0x1)
#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC01 (0x2)
#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC02 (0x4)
#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC03 (0x8)
#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC04 (0x10)
#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC05 (0x20)
#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC06 (0x40)
#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC07 (0x80)
/* Bit definitions and macros for MCF_GPIO_PODR_DSPI */
#define MCF_GPIO_PODR_DSPI_PODR_DSPI0 (0x1)
#define MCF_GPIO_PODR_DSPI_PODR_DSPI1 (0x2)
#define MCF_GPIO_PODR_DSPI_PODR_DSPI2 (0x4)
#define MCF_GPIO_PODR_DSPI_PODR_DSPI3 (0x8)
#define MCF_GPIO_PODR_DSPI_PODR_DSPI4 (0x10)
#define MCF_GPIO_PODR_DSPI_PODR_DSPI5 (0x20)
#define MCF_GPIO_PODR_DSPI_PODR_DSPI6 (0x40)
/* Bit definitions and macros for MCF_GPIO_PDDR_DSPI */
#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI0 (0x1)
#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI1 (0x2)
#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI2 (0x4)
#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI3 (0x8)
#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI4 (0x10)
#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI5 (0x20)
#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI6 (0x40)
/* Bit definitions and macros for MCF_GPIO_PPDSDR_DSPI */
#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI0 (0x1)
#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI1 (0x2)
#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI2 (0x4)
#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI3 (0x8)
#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI4 (0x10)
#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI5 (0x20)
#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI6 (0x40)
/* Bit definitions and macros for MCF_GPIO_PCLRR_DSPI */
#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI0 (0x1)
#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI1 (0x2)
#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI2 (0x4)
#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI3 (0x8)
#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI4 (0x10)
#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI5 (0x20)
#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI6 (0x40)
#endif /* __MCF5475_GPIO_H__ */

100
tos/jtagwait/include/MCF5475_GPT.h
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@@ -1,100 +0,0 @@
/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.81
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF5475_GPT_H__
#define __MCF5475_GPT_H__
/*********************************************************************
*
* General Purpose Timers (GPT)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_GPT0_GMS (*(volatile uint32_t*)(&_MBAR[0x800]))
#define MCF_GPT0_GCIR (*(volatile uint32_t*)(&_MBAR[0x804]))
#define MCF_GPT0_GPWM (*(volatile uint32_t*)(&_MBAR[0x808]))
#define MCF_GPT0_GSR (*(volatile uint32_t*)(&_MBAR[0x80C]))
#define MCF_GPT1_GMS (*(volatile uint32_t*)(&_MBAR[0x810]))
#define MCF_GPT1_GCIR (*(volatile uint32_t*)(&_MBAR[0x814]))
#define MCF_GPT1_GPWM (*(volatile uint32_t*)(&_MBAR[0x818]))
#define MCF_GPT1_GSR (*(volatile uint32_t*)(&_MBAR[0x81C]))
#define MCF_GPT2_GMS (*(volatile uint32_t*)(&_MBAR[0x820]))
#define MCF_GPT2_GCIR (*(volatile uint32_t*)(&_MBAR[0x824]))
#define MCF_GPT2_GPWM (*(volatile uint32_t*)(&_MBAR[0x828]))
#define MCF_GPT2_GSR (*(volatile uint32_t*)(&_MBAR[0x82C]))
#define MCF_GPT3_GMS (*(volatile uint32_t*)(&_MBAR[0x830]))
#define MCF_GPT3_GCIR (*(volatile uint32_t*)(&_MBAR[0x834]))
#define MCF_GPT3_GPWM (*(volatile uint32_t*)(&_MBAR[0x838]))
#define MCF_GPT3_GSR (*(volatile uint32_t*)(&_MBAR[0x83C]))
#define MCF_GPT_GMS(x) (*(volatile uint32_t*)(&_MBAR[0x800 + ((x)*0x10)]))
#define MCF_GPT_GCIR(x) (*(volatile uint32_t*)(&_MBAR[0x804 + ((x)*0x10)]))
#define MCF_GPT_GPWM(x) (*(volatile uint32_t*)(&_MBAR[0x808 + ((x)*0x10)]))
#define MCF_GPT_GSR(x) (*(volatile uint32_t*)(&_MBAR[0x80C + ((x)*0x10)]))
/* Bit definitions and macros for MCF_GPT_GMS */
#define MCF_GPT_GMS_TMS(x) (((x)&0x7)<<0)
#define MCF_GPT_GMS_TMS_DISABLE (0)
#define MCF_GPT_GMS_TMS_INCAPT (0x1)
#define MCF_GPT_GMS_TMS_OUTCAPT (0x2)
#define MCF_GPT_GMS_TMS_PWM (0x3)
#define MCF_GPT_GMS_TMS_GPIO (0x4)
#define MCF_GPT_GMS_GPIO(x) (((x)&0x3)<<0x4)
#define MCF_GPT_GMS_GPIO_INPUT (0)
#define MCF_GPT_GMS_GPIO_OUTLO (0x20)
#define MCF_GPT_GMS_GPIO_OUTHI (0x30)
#define MCF_GPT_GMS_IEN (0x100)
#define MCF_GPT_GMS_OD (0x200)
#define MCF_GPT_GMS_SC (0x400)
#define MCF_GPT_GMS_CE (0x1000)
#define MCF_GPT_GMS_WDEN (0x8000)
#define MCF_GPT_GMS_ICT(x) (((x)&0x3)<<0x10)
#define MCF_GPT_GMS_ICT_ANY (0)
#define MCF_GPT_GMS_ICT_RISE (0x10000)
#define MCF_GPT_GMS_ICT_FALL (0x20000)
#define MCF_GPT_GMS_ICT_PULSE (0x30000)
#define MCF_GPT_GMS_OCT(x) (((x)&0x3)<<0x14)
#define MCF_GPT_GMS_OCT_FRCLOW (0)
#define MCF_GPT_GMS_OCT_PULSEHI (0x100000)
#define MCF_GPT_GMS_OCT_PULSELO (0x200000)
#define MCF_GPT_GMS_OCT_TOGGLE (0x300000)
#define MCF_GPT_GMS_OCPW(x) (((x)&0xFF)<<0x18)
/* Bit definitions and macros for MCF_GPT_GCIR */
#define MCF_GPT_GCIR_CNT(x) (((x)&0xFFFF)<<0)
#define MCF_GPT_GCIR_PRE(x) (((x)&0xFFFF)<<0x10)
/* Bit definitions and macros for MCF_GPT_GPWM */
#define MCF_GPT_GPWM_LOAD (0x1)
#define MCF_GPT_GPWM_PWMOP (0x100)
#define MCF_GPT_GPWM_WIDTH(x) (((x)&0xFFFF)<<0x10)
/* Bit definitions and macros for MCF_GPT_GSR */
#define MCF_GPT_GSR_CAPT (0x1)
#define MCF_GPT_GSR_COMP (0x2)
#define MCF_GPT_GSR_PWMP (0x4)
#define MCF_GPT_GSR_TEXP (0x8)
#define MCF_GPT_GSR_PIN (0x100)
#define MCF_GPT_GSR_OVF(x) (((x)&0x7)<<0xC)
#define MCF_GPT_GSR_CAPTURE(x) (((x)&0xFFFF)<<0x10)
#endif /* __MCF5475_GPT_H__ */

69
tos/jtagwait/include/MCF5475_I2C.h
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@@ -1,69 +0,0 @@
/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.81
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF5475_I2C_H__
#define __MCF5475_I2C_H__
/*********************************************************************
*
* I2C Module (I2C)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_I2C_I2ADR (*(volatile uint8_t *)(&_MBAR[0x8F00]))
#define MCF_I2C_I2FDR (*(volatile uint8_t *)(&_MBAR[0x8F04]))
#define MCF_I2C_I2CR (*(volatile uint8_t *)(&_MBAR[0x8F08]))
#define MCF_I2C_I2SR (*(volatile uint8_t *)(&_MBAR[0x8F0C]))
#define MCF_I2C_I2DR (*(volatile uint8_t *)(&_MBAR[0x8F10]))
#define MCF_I2C_I2ICR (*(volatile uint8_t *)(&_MBAR[0x8F20]))
/* Bit definitions and macros for MCF_I2C_I2ADR */
#define MCF_I2C_I2ADR_ADR(x) (((x)&0x7F)<<0x1)
/* Bit definitions and macros for MCF_I2C_I2FDR */
#define MCF_I2C_I2FDR_IC(x) (((x)&0x3F)<<0)
/* Bit definitions and macros for MCF_I2C_I2CR */
#define MCF_I2C_I2CR_RSTA (0x4)
#define MCF_I2C_I2CR_TXAK (0x8)
#define MCF_I2C_I2CR_MTX (0x10)
#define MCF_I2C_I2CR_MSTA (0x20)
#define MCF_I2C_I2CR_IIEN (0x40)
#define MCF_I2C_I2CR_IEN (0x80)
/* Bit definitions and macros for MCF_I2C_I2SR */
#define MCF_I2C_I2SR_RXAK (0x1)
#define MCF_I2C_I2SR_IIF (0x2)
#define MCF_I2C_I2SR_SRW (0x4)
#define MCF_I2C_I2SR_IAL (0x10)
#define MCF_I2C_I2SR_IBB (0x20)
#define MCF_I2C_I2SR_IAAS (0x40)
#define MCF_I2C_I2SR_ICF (0x80)
/* Bit definitions and macros for MCF_I2C_I2DR */
#define MCF_I2C_I2DR_DATA(x) (((x)&0xFF)<<0)
/* Bit definitions and macros for MCF_I2C_I2ICR */
#define MCF_I2C_I2ICR_IE (0x1)
#define MCF_I2C_I2ICR_RE (0x2)
#define MCF_I2C_I2ICR_TE (0x4)
#define MCF_I2C_I2ICR_BNBE (0x8)
#endif /* __MCF5475_I2C_H__ */

331
tos/jtagwait/include/MCF5475_INTC.h
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@@ -1,331 +0,0 @@
/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.81
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF5475_INTC_H__
#define __MCF5475_INTC_H__
/*********************************************************************
*
* Interrupt Controller (INTC)
*
*********************************************************************/
/* Register read/write macros */
#define MCF_INTC_IPRH (*(volatile uint32_t*)(&_MBAR[0x700]))
#define MCF_INTC_IPRL (*(volatile uint32_t*)(&_MBAR[0x704]))
#define MCF_INTC_IMRH (*(volatile uint32_t*)(&_MBAR[0x708]))
#define MCF_INTC_IMRL (*(volatile uint32_t*)(&_MBAR[0x70C]))
#define MCF_INTC_INTFRCH (*(volatile uint32_t*)(&_MBAR[0x710]))
#define MCF_INTC_INTFRCL (*(volatile uint32_t*)(&_MBAR[0x714]))
#define MCF_INTC_IRLR (*(volatile uint8_t *)(&_MBAR[0x718]))
#define MCF_INTC_IACKLPR (*(volatile uint8_t *)(&_MBAR[0x719]))
#define MCF_INTC_ICR01 (*(volatile uint8_t *)(&_MBAR[0x741]))
#define MCF_INTC_ICR02 (*(volatile uint8_t *)(&_MBAR[0x742]))
#define MCF_INTC_ICR03 (*(volatile uint8_t *)(&_MBAR[0x743]))
#define MCF_INTC_ICR04 (*(volatile uint8_t *)(&_MBAR[0x744]))
#define MCF_INTC_ICR05 (*(volatile uint8_t *)(&_MBAR[0x745]))
#define MCF_INTC_ICR06 (*(volatile uint8_t *)(&_MBAR[0x746]))
#define MCF_INTC_ICR07 (*(volatile uint8_t *)(&_MBAR[0x747]))
#define MCF_INTC_ICR08 (*(volatile uint8_t *)(&_MBAR[0x748]))
#define MCF_INTC_ICR09 (*(volatile uint8_t *)(&_MBAR[0x749]))
#define MCF_INTC_ICR10 (*(volatile uint8_t *)(&_MBAR[0x74A]))
#define MCF_INTC_ICR11 (*(volatile uint8_t *)(&_MBAR[0x74B]))
#define MCF_INTC_ICR12 (*(volatile uint8_t *)(&_MBAR[0x74C]))
#define MCF_INTC_ICR13 (*(volatile uint8_t *)(&_MBAR[0x74D]))
#define MCF_INTC_ICR14 (*(volatile uint8_t *)(&_MBAR[0x74E]))
#define MCF_INTC_ICR15 (*(volatile uint8_t *)(&_MBAR[0x74F]))
#define MCF_INTC_ICR16 (*(volatile uint8_t *)(&_MBAR[0x750]))
#define MCF_INTC_ICR17 (*(volatile uint8_t *)(&_MBAR[0x751]))
#define MCF_INTC_ICR18 (*(volatile uint8_t *)(&_MBAR[0x752]))
#define MCF_INTC_ICR19 (*(volatile uint8_t *)(&_MBAR[0x753]))
#define MCF_INTC_ICR20 (*(volatile uint8_t *)(&_MBAR[0x754]))
#define MCF_INTC_ICR21 (*(volatile uint8_t *)(&_MBAR[0x755]))
#define MCF_INTC_ICR22 (*(volatile uint8_t *)(&_MBAR[0x756]))
#define MCF_INTC_ICR23 (*(volatile uint8_t *)(&_MBAR[0x757]))
#define MCF_INTC_ICR24 (*(volatile uint8_t *)(&_MBAR[0x758]))
#define MCF_INTC_ICR25 (*(volatile uint8_t *)(&_MBAR[0x759]))
#define MCF_INTC_ICR26 (*(volatile uint8_t *)(&_MBAR[0x75A]))
#define MCF_INTC_ICR27 (*(volatile uint8_t *)(&_MBAR[0x75B]))
#define MCF_INTC_ICR28 (*(volatile uint8_t *)(&_MBAR[0x75C]))
#define MCF_INTC_ICR29 (*(volatile uint8_t *)(&_MBAR[0x75D]))
#define MCF_INTC_ICR30 (*(volatile uint8_t *)(&_MBAR[0x75E]))
#define MCF_INTC_ICR31 (*(volatile uint8_t *)(&_MBAR[0x75F]))
#define MCF_INTC_ICR32 (*(volatile uint8_t *)(&_MBAR[0x760]))
#define MCF_INTC_ICR33 (*(volatile uint8_t *)(&_MBAR[0x761]))
#define MCF_INTC_ICR34 (*(volatile uint8_t *)(&_MBAR[0x762]))
#define MCF_INTC_ICR35 (*(volatile uint8_t *)(&_MBAR[0x763]))
#define MCF_INTC_ICR36 (*(volatile uint8_t *)(&_MBAR[0x764]))
#define MCF_INTC_ICR37 (*(volatile uint8_t *)(&_MBAR[0x765]))
#define MCF_INTC_ICR38 (*(volatile uint8_t *)(&_MBAR[0x766]))
#define MCF_INTC_ICR39 (*(volatile uint8_t *)(&_MBAR[0x767]))
#define MCF_INTC_ICR40 (*(volatile uint8_t *)(&_MBAR[0x768]))
#define MCF_INTC_ICR41 (*(volatile uint8_t *)(&_MBAR[0x769]))
#define MCF_INTC_ICR42 (*(volatile uint8_t *)(&_MBAR[0x76A]))
#define MCF_INTC_ICR43 (*(volatile uint8_t *)(&_MBAR[0x76B]))
#define MCF_INTC_ICR44 (*(volatile uint8_t *)(&_MBAR[0x76C]))
#define MCF_INTC_ICR45 (*(volatile uint8_t *)(&_MBAR[0x76D]))
#define MCF_INTC_ICR46 (*(volatile uint8_t *)(&_MBAR[0x76E]))
#define MCF_INTC_ICR47 (*(volatile uint8_t *)(&_MBAR[0x76F]))
#define MCF_INTC_ICR48 (*(volatile uint8_t *)(&_MBAR[0x770]))
#define MCF_INTC_ICR49 (*(volatile uint8_t *)(&_MBAR[0x771]))
#define MCF_INTC_ICR50 (*(volatile uint8_t *)(&_MBAR[0x772]))
#define MCF_INTC_ICR51 (*(volatile uint8_t *)(&_MBAR[0x773]))
#define MCF_INTC_ICR52 (*(volatile uint8_t *)(&_MBAR[0x774]))
#define MCF_INTC_ICR53 (*(volatile uint8_t *)(&_MBAR[0x775]))
#define MCF_INTC_ICR54 (*(volatile uint8_t *)(&_MBAR[0x776]))
#define MCF_INTC_ICR55 (*(volatile uint8_t *)(&_MBAR[0x777]))
#define MCF_INTC_ICR56 (*(volatile uint8_t *)(&_MBAR[0x778]))
#define MCF_INTC_ICR57 (*(volatile uint8_t *)(&_MBAR[0x779]))
#define MCF_INTC_ICR58 (*(volatile uint8_t *)(&_MBAR[0x77A]))
#define MCF_INTC_ICR59 (*(volatile uint8_t *)(&_MBAR[0x77B]))
#define MCF_INTC_ICR60 (*(volatile uint8_t *)(&_MBAR[0x77C]))
#define MCF_INTC_ICR61 (*(volatile uint8_t *)(&_MBAR[0x77D]))
#define MCF_INTC_ICR62 (*(volatile uint8_t *)(&_MBAR[0x77E]))
#define MCF_INTC_ICR63 (*(volatile uint8_t *)(&_MBAR[0x77F]))
#define MCF_INTC_SWIACK (*(volatile uint8_t *)(&_MBAR[0x7E0]))
#define MCF_INTC_L1IACK (*(volatile uint8_t *)(&_MBAR[0x7E4]))
#define MCF_INTC_L2IACK (*(volatile uint8_t *)(&_MBAR[0x7E8]))
#define MCF_INTC_L3IACK (*(volatile uint8_t *)(&_MBAR[0x7EC]))
#define MCF_INTC_L4IACK (*(volatile uint8_t *)(&_MBAR[0x7F0]))
#define MCF_INTC_L5IACK (*(volatile uint8_t *)(&_MBAR[0x7F4]))
#define MCF_INTC_L6IACK (*(volatile uint8_t *)(&_MBAR[0x7F8]))
#define MCF_INTC_L7IACK (*(volatile uint8_t *)(&_MBAR[0x7FC]))
#define MCF_INTC_ICR(x) (*(volatile uint8_t *)(&_MBAR[0x741 + ((x-1)*0x1)]))
#define MCF_INTC_LIACK(x) (*(volatile uint8_t *)(&_MBAR[0x7E4 + ((x-1)*0x4)]))
/* Bit definitions and macros for MCF_INTC_IPRH */
#define MCF_INTC_IPRH_INT32 (0x1)
#define MCF_INTC_IPRH_INT33 (0x2)
#define MCF_INTC_IPRH_INT34 (0x4)
#define MCF_INTC_IPRH_INT35 (0x8)
#define MCF_INTC_IPRH_INT36 (0x10)
#define MCF_INTC_IPRH_INT37 (0x20)
#define MCF_INTC_IPRH_INT38 (0x40)
#define MCF_INTC_IPRH_INT39 (0x80)
#define MCF_INTC_IPRH_INT40 (0x100)
#define MCF_INTC_IPRH_INT41 (0x200)
#define MCF_INTC_IPRH_INT42 (0x400)
#define MCF_INTC_IPRH_INT43 (0x800)
#define MCF_INTC_IPRH_INT44 (0x1000)
#define MCF_INTC_IPRH_INT45 (0x2000)
#define MCF_INTC_IPRH_INT46 (0x4000)
#define MCF_INTC_IPRH_INT47 (0x8000)
#define MCF_INTC_IPRH_INT48 (0x10000)
#define MCF_INTC_IPRH_INT49 (0x20000)
#define MCF_INTC_IPRH_INT50 (0x40000)
#define MCF_INTC_IPRH_INT51 (0x80000)
#define MCF_INTC_IPRH_INT52 (0x100000)
#define MCF_INTC_IPRH_INT53 (0x200000)
#define MCF_INTC_IPRH_INT54 (0x400000)
#define MCF_INTC_IPRH_INT55 (0x800000)
#define MCF_INTC_IPRH_INT56 (0x1000000)
#define MCF_INTC_IPRH_INT57 (0x2000000)
#define MCF_INTC_IPRH_INT58 (0x4000000)
#define MCF_INTC_IPRH_INT59 (0x8000000)
#define MCF_INTC_IPRH_INT60 (0x10000000)
#define MCF_INTC_IPRH_INT61 (0x20000000)
#define MCF_INTC_IPRH_INT62 (0x40000000)
#define MCF_INTC_IPRH_INT63 (0x80000000)
/* Bit definitions and macros for MCF_INTC_IPRL */
#define MCF_INTC_IPRL_INT1 (0x2)
#define MCF_INTC_IPRL_INT2 (0x4)
#define MCF_INTC_IPRL_INT3 (0x8)
#define MCF_INTC_IPRL_INT4 (0x10)
#define MCF_INTC_IPRL_INT5 (0x20)
#define MCF_INTC_IPRL_INT6 (0x40)
#define MCF_INTC_IPRL_INT7 (0x80)
#define MCF_INTC_IPRL_INT8 (0x100)
#define MCF_INTC_IPRL_INT9 (0x200)
#define MCF_INTC_IPRL_INT10 (0x400)
#define MCF_INTC_IPRL_INT11 (0x800)
#define MCF_INTC_IPRL_INT12 (0x1000)
#define MCF_INTC_IPRL_INT13 (0x2000)
#define MCF_INTC_IPRL_INT14 (0x4000)
#define MCF_INTC_IPRL_INT15 (0x8000)
#define MCF_INTC_IPRL_INT16 (0x10000)
#define MCF_INTC_IPRL_INT17 (0x20000)
#define MCF_INTC_IPRL_INT18 (0x40000)
#define MCF_INTC_IPRL_INT19 (0x80000)
#define MCF_INTC_IPRL_INT20 (0x100000)
#define MCF_INTC_IPRL_INT21 (0x200000)
#define MCF_INTC_IPRL_INT22 (0x400000)
#define MCF_INTC_IPRL_INT23 (0x800000)
#define MCF_INTC_IPRL_INT24 (0x1000000)
#define MCF_INTC_IPRL_INT25 (0x2000000)
#define MCF_INTC_IPRL_INT26 (0x4000000)
#define MCF_INTC_IPRL_INT27 (0x8000000)
#define MCF_INTC_IPRL_INT28 (0x10000000)
#define MCF_INTC_IPRL_INT29 (0x20000000)
#define MCF_INTC_IPRL_INT30 (0x40000000)
#define MCF_INTC_IPRL_INT31 (0x80000000)
/* Bit definitions and macros for MCF_INTC_IMRH */
#define MCF_INTC_IMRH_INT_MASK32 (0x1)
#define MCF_INTC_IMRH_INT_MASK33 (0x2)
#define MCF_INTC_IMRH_INT_MASK34 (0x4)
#define MCF_INTC_IMRH_INT_MASK35 (0x8)
#define MCF_INTC_IMRH_INT_MASK36 (0x10)
#define MCF_INTC_IMRH_INT_MASK37 (0x20)
#define MCF_INTC_IMRH_INT_MASK38 (0x40)
#define MCF_INTC_IMRH_INT_MASK39 (0x80)
#define MCF_INTC_IMRH_INT_MASK40 (0x100)
#define MCF_INTC_IMRH_INT_MASK41 (0x200)
#define MCF_INTC_IMRH_INT_MASK42 (0x400)
#define MCF_INTC_IMRH_INT_MASK43 (0x800)
#define MCF_INTC_IMRH_INT_MASK44 (0x1000)
#define MCF_INTC_IMRH_INT_MASK45 (0x2000)
#define MCF_INTC_IMRH_INT_MASK46 (0x4000)
#define MCF_INTC_IMRH_INT_MASK47 (0x8000)
#define MCF_INTC_IMRH_INT_MASK48 (0x10000)
#define MCF_INTC_IMRH_INT_MASK49 (0x20000)
#define MCF_INTC_IMRH_INT_MASK50 (0x40000)
#define MCF_INTC_IMRH_INT_MASK51 (0x80000)
#define MCF_INTC_IMRH_INT_MASK52 (0x100000)
#define MCF_INTC_IMRH_INT_MASK53 (0x200000)
#define MCF_INTC_IMRH_INT_MASK54 (0x400000)
#define MCF_INTC_IMRH_INT_MASK55 (0x800000)
#define MCF_INTC_IMRH_INT_MASK56 (0x1000000)
#define MCF_INTC_IMRH_INT_MASK57 (0x2000000)
#define MCF_INTC_IMRH_INT_MASK58 (0x4000000)
#define MCF_INTC_IMRH_INT_MASK59 (0x8000000)
#define MCF_INTC_IMRH_INT_MASK60 (0x10000000)
#define MCF_INTC_IMRH_INT_MASK61 (0x20000000)
#define MCF_INTC_IMRH_INT_MASK62 (0x40000000)
#define MCF_INTC_IMRH_INT_MASK63 (0x80000000)
/* Bit definitions and macros for MCF_INTC_IMRL */
#define MCF_INTC_IMRL_MASKALL (0x1)
#define MCF_INTC_IMRL_INT_MASK1 (0x2)
#define MCF_INTC_IMRL_INT_MASK2 (0x4)
#define MCF_INTC_IMRL_INT_MASK3 (0x8)
#define MCF_INTC_IMRL_INT_MASK4 (0x10)
#define MCF_INTC_IMRL_INT_MASK5 (0x20)
#define MCF_INTC_IMRL_INT_MASK6 (0x40)
#define MCF_INTC_IMRL_INT_MASK7 (0x80)
#define MCF_INTC_IMRL_INT_MASK8 (0x100)
#define MCF_INTC_IMRL_INT_MASK9 (0x200)
#define MCF_INTC_IMRL_INT_MASK10 (0x400)
#define MCF_INTC_IMRL_INT_MASK11 (0x800)
#define MCF_INTC_IMRL_INT_MASK12 (0x1000)
#define MCF_INTC_IMRL_INT_MASK13 (0x2000)
#define MCF_INTC_IMRL_INT_MASK14 (0x4000)
#define MCF_INTC_IMRL_INT_MASK15 (0x8000)
#define MCF_INTC_IMRL_INT_MASK16 (0x10000)
#define MCF_INTC_IMRL_INT_MASK17 (0x20000)
#define MCF_INTC_IMRL_INT_MASK18 (0x40000)
#define MCF_INTC_IMRL_INT_MASK19 (0x80000)
#define MCF_INTC_IMRL_INT_MASK20 (0x100000)
#define MCF_INTC_IMRL_INT_MASK21 (0x200000)
#define MCF_INTC_IMRL_INT_MASK22 (0x400000)
#define MCF_INTC_IMRL_INT_MASK23 (0x800000)
#define MCF_INTC_IMRL_INT_MASK24 (0x1000000)
#define MCF_INTC_IMRL_INT_MASK25 (0x2000000)
#define MCF_INTC_IMRL_INT_MASK26 (0x4000000)
#define MCF_INTC_IMRL_INT_MASK27 (0x8000000)
#define MCF_INTC_IMRL_INT_MASK28 (0x10000000)
#define MCF_INTC_IMRL_INT_MASK29 (0x20000000)
#define MCF_INTC_IMRL_INT_MASK30 (0x40000000)
#define MCF_INTC_IMRL_INT_MASK31 (0x80000000)
/* Bit definitions and macros for MCF_INTC_INTFRCH */
#define MCF_INTC_INTFRCH_INTFRC32 (0x1)
#define MCF_INTC_INTFRCH_INTFRC33 (0x2)
#define MCF_INTC_INTFRCH_INTFRC34 (0x4)
#define MCF_INTC_INTFRCH_INTFRC35 (0x8)
#define MCF_INTC_INTFRCH_INTFRC36 (0x10)
#define MCF_INTC_INTFRCH_INTFRC37 (0x20)
#define MCF_INTC_INTFRCH_INTFRC38 (0x40)
#define MCF_INTC_INTFRCH_INTFRC39 (0x80)
#define MCF_INTC_INTFRCH_INTFRC40 (0x100)
#define MCF_INTC_INTFRCH_INTFRC41 (0x200)
#define MCF_INTC_INTFRCH_INTFRC42 (0x400)
#define MCF_INTC_INTFRCH_INTFRC43 (0x800)
#define MCF_INTC_INTFRCH_INTFRC44 (0x1000)
#define MCF_INTC_INTFRCH_INTFRC45 (0x2000)
#define MCF_INTC_INTFRCH_INTFRC46 (0x4000)
#define MCF_INTC_INTFRCH_INTFRC47 (0x8000)
#define MCF_INTC_INTFRCH_INTFRC48 (0x10000)
#define MCF_INTC_INTFRCH_INTFRC49 (0x20000)
#define MCF_INTC_INTFRCH_INTFRC50 (0x40000)
#define MCF_INTC_INTFRCH_INTFRC51 (0x80000)
#define MCF_INTC_INTFRCH_INTFRC52 (0x100000)
#define MCF_INTC_INTFRCH_INTFRC53 (0x200000)
#define MCF_INTC_INTFRCH_INTFRC54 (0x400000)
#define MCF_INTC_INTFRCH_INTFRC55 (0x800000)
#define MCF_INTC_INTFRCH_INTFRC56 (0x1000000)
#define MCF_INTC_INTFRCH_INTFRC57 (0x2000000)
#define MCF_INTC_INTFRCH_INTFRC58 (0x4000000)
#define MCF_INTC_INTFRCH_INTFRC59 (0x8000000)
#define MCF_INTC_INTFRCH_INTFRC60 (0x10000000)
#define MCF_INTC_INTFRCH_INTFRC61 (0x20000000)
#define MCF_INTC_INTFRCH_INTFRC62 (0x40000000)
#define MCF_INTC_INTFRCH_INTFRC63 (0x80000000)
/* Bit definitions and macros for MCF_INTC_INTFRCL */
#define MCF_INTC_INTFRCL_INTFRC1 (0x2)
#define MCF_INTC_INTFRCL_INTFRC2 (0x4)
#define MCF_INTC_INTFRCL_INTFRC3 (0x8)
#define MCF_INTC_INTFRCL_INTFRC4 (0x10)
#define MCF_INTC_INTFRCL_INTFRC5 (0x20)
#define MCF_INTC_INTFRCL_INTFRC6 (0x40)
#define MCF_INTC_INTFRCL_INTFRC7 (0x80)
#define MCF_INTC_INTFRCL_INTFRC8 (0x100)
#define MCF_INTC_INTFRCL_INTFRC9 (0x200)
#define MCF_INTC_INTFRCL_INTFRC10 (0x400)
#define MCF_INTC_INTFRCL_INTFRC11 (0x800)
#define MCF_INTC_INTFRCL_INTFRC12 (0x1000)
#define MCF_INTC_INTFRCL_INTFRC13 (0x2000)
#define MCF_INTC_INTFRCL_INTFRC14 (0x4000)
#define MCF_INTC_INTFRCL_INTFRC15 (0x8000)
#define MCF_INTC_INTFRCL_INTFRC16 (0x10000)
#define MCF_INTC_INTFRCL_INTFRC17 (0x20000)
#define MCF_INTC_INTFRCL_INTFRC18 (0x40000)
#define MCF_INTC_INTFRCL_INTFRC19 (0x80000)
#define MCF_INTC_INTFRCL_INTFRC20 (0x100000)
#define MCF_INTC_INTFRCL_INTFRC21 (0x200000)
#define MCF_INTC_INTFRCL_INTFRC22 (0x400000)
#define MCF_INTC_INTFRCL_INTFRC23 (0x800000)
#define MCF_INTC_INTFRCL_INTFRC24 (0x1000000)
#define MCF_INTC_INTFRCL_INTFRC25 (0x2000000)
#define MCF_INTC_INTFRCL_INTFRC26 (0x4000000)
#define MCF_INTC_INTFRCL_INTFRC27 (0x8000000)
#define MCF_INTC_INTFRCL_INTFRC28 (0x10000000)
#define MCF_INTC_INTFRCL_INTFRC29 (0x20000000)
#define MCF_INTC_INTFRCL_INTFRC30 (0x40000000)
#define MCF_INTC_INTFRCL_INTFRC31 (0x80000000)
/* Bit definitions and macros for MCF_INTC_IRLR */
#define MCF_INTC_IRLR_IRQ(x) (((x)&0x7F)<<0x1)
/* Bit definitions and macros for MCF_INTC_IACKLPR */
#define MCF_INTC_IACKLPR_PRI(x) (((x)&0xF)<<0)
#define MCF_INTC_IACKLPR_LEVEL(x) (((x)&0x7)<<0x4)
/* Bit definitions and macros for MCF_INTC_ICR */
#define MCF_INTC_ICR_IP(x) (((x)&0x7)<<0)
#define MCF_INTC_ICR_IL(x) (((x)&0x7)<<0x3)
/* Bit definitions and macros for MCF_INTC_SWIACK */
#define MCF_INTC_SWIACK_VECTOR(x) (((x)&0xFF)<<0)
/* Bit definitions and macros for MCF_INTC_LIACK */
#define MCF_INTC_LIACK_VECTOR(x) (((x)&0xFF)<<0)
#endif /* __MCF5475_INTC_H__ */

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tos/jtagwait/include/MCF5475_MMU.h
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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.81
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF5475_MMU_H__
#define __MCF5475_MMU_H__
/*********************************************************************
*
* Memory Management Unit (MMU)
*
*********************************************************************/
/* Register read/write macros */
/* note the uint32_t_a - this is to avoid gcc warnings about pointer aliasing */
#define MCF_MMU_MMUCR (*(volatile uint32_t_a*)(&_MMUBAR[0]))
#define MCF_MMU_MMUOR (*(volatile uint32_t_a*)(&_MMUBAR[0x4]))
#define MCF_MMU_MMUSR (*(volatile uint32_t_a*)(&_MMUBAR[0x8]))
#define MCF_MMU_MMUAR (*(volatile uint32_t_a*)(&_MMUBAR[0x10]))
#define MCF_MMU_MMUTR (*(volatile uint32_t_a*)(&_MMUBAR[0x14]))
#define MCF_MMU_MMUDR (*(volatile uint32_t_a*)(&_MMUBAR[0x18]))
/* Bit definitions and macros for MCF_MMU_MMUCR */
#define MCF_MMU_MMUCR_EN (0x1)
#define MCF_MMU_MMUCR_ASM (0x2)
/* Bit definitions and macros for MCF_MMU_MMUOR */
#define MCF_MMU_MMUOR_UAA (0x1)
#define MCF_MMU_MMUOR_ACC (0x2)
#define MCF_MMU_MMUOR_RW (0x4)
#define MCF_MMU_MMUOR_ADR (0x8)
#define MCF_MMU_MMUOR_ITLB (0x10)
#define MCF_MMU_MMUOR_CAS (0x20)
#define MCF_MMU_MMUOR_CNL (0x40)
#define MCF_MMU_MMUOR_CA (0x80)
#define MCF_MMU_MMUOR_STLB (0x100)
#define MCF_MMU_MMUOR_AA(x) (((x)&0xFFFF)<<0x10)
/* Bit definitions and macros for MCF_MMU_MMUSR */
#define MCF_MMU_MMUSR_HIT (0x2)
#define MCF_MMU_MMUSR_WF (0x8)
#define MCF_MMU_MMUSR_RF (0x10)
#define MCF_MMU_MMUSR_SPF (0x20)
/* Bit definitions and macros for MCF_MMU_MMUAR */
#define MCF_MMU_MMUAR_FA(x) (((x)&0xFFFFFFFF)<<0)
/* Bit definitions and macros for MCF_MMU_MMUTR */
#define MCF_MMU_MMUTR_V (0x1)
#define MCF_MMU_MMUTR_SG (0x2)
#define MCF_MMU_MMUTR_ID(x) (((x)&0xFF)<<0x2)
#define MCF_MMU_MMUTR_VA(x) (((x)&0x3FFFFF)<<0xA)
/* Bit definitions and macros for MCF_MMU_MMUDR */
#define MCF_MMU_MMUDR_LK (0x2)
#define MCF_MMU_MMUDR_X (0x4)
#define MCF_MMU_MMUDR_W (0x8)
#define MCF_MMU_MMUDR_R (0x10)
#define MCF_MMU_MMUDR_SP (0x20)
#define MCF_MMU_MMUDR_CM(x) (((x)&0x3)<<0x6)
#define MCF_MMU_MMUDR_SZ(x) (((x)&0x3)<<0x8)
#define MCF_MMU_MMUDR_PA(x) (((x)&0x3FFFFF)<<0xA)
#endif /* __MCF5475_MMU_H__ */

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tos/jtagwait/include/MCF5475_PAD.h
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/* Coldfire C Header File
* Copyright Freescale Semiconductor Inc
* All rights reserved.
*
* 2008/05/23 Revision: 0.81
*
* (c) Copyright UNIS, a.s. 1997-2008
* UNIS, a.s.
* Jundrovska 33
* 624 00 Brno
* Czech Republic
* http : www.processorexpert.com
* mail : info@processorexpert.com
*/
#ifndef __MCF5475_PAD_H__
#define __MCF5475_PAD_H__
/*********************************************************************
*
* Common GPIO
*
*********************************************************************/
/* Register read/write macros */
#define MCF_PAD_PAR_FBCTL (*(volatile uint16_t*)(&_MBAR[0xA40]))
#define MCF_PAD_PAR_FBCS (*(volatile uint8_t *)(&_MBAR[0xA42]))
#define MCF_PAD_PAR_DMA (*(volatile uint8_t *)(&_MBAR[0xA43]))
#define MCF_PAD_PAR_FECI2CIRQ (*(volatile uint16_t*)(&_MBAR[0xA44]))
#define MCF_PAD_PAR_PCIBG (*(volatile uint16_t*)(&_MBAR[0xA48]))
#define MCF_PAD_PAR_PCIBR (*(volatile uint16_t*)(&_MBAR[0xA4A]))
#define MCF_PAD_PAR_PSC3 (*(volatile uint8_t *)(&_MBAR[0xA4C]))
#define MCF_PAD_PAR_PSC2 (*(volatile uint8_t *)(&_MBAR[0xA4D]))
#define MCF_PAD_PAR_PSC1 (*(volatile uint8_t *)(&_MBAR[0xA4E]))
#define MCF_PAD_PAR_PSC0 (*(volatile uint8_t *)(&_MBAR[0xA4F]))
#define MCF_PAD_PAR_DSPI (*(volatile uint16_t*)(&_MBAR[0xA50]))
#define MCF_PAD_PAR_TIMER (*(volatile uint8_t *)(&_MBAR[0xA52]))
/* Bit definitions and macros for MCF_PAD_PAR_FBCTL */
#define MCF_PAD_PAR_FBCTL_PAR_ALE(x) (((x)&0x3)<<0)
#define MCF_PAD_PAR_FBCTL_PAR_ALE_GPIO (0)
#define MCF_PAD_PAR_FBCTL_PAR_ALE_TBST (0x2)
#define MCF_PAD_PAR_FBCTL_PAR_ALE_ALE (0x3)
#define MCF_PAD_PAR_FBCTL_PAR_TA (0x4)
#define MCF_PAD_PAR_FBCTL_PAR_RWB(x) (((x)&0x3)<<0x4)
#define MCF_PAD_PAR_FBCTL_PAR_RWB_GPIO (0)
#define MCF_PAD_PAR_FBCTL_PAR_RWB_TBST (0x20)
#define MCF_PAD_PAR_FBCTL_PAR_RWB_RW (0x30)
#define MCF_PAD_PAR_FBCTL_PAR_OE (0x40)
#define MCF_PAD_PAR_FBCTL_PAR_BWE0 (0x100)
#define MCF_PAD_PAR_FBCTL_PAR_BWE1 (0x400)
#define MCF_PAD_PAR_FBCTL_PAR_BWE2 (0x1000)
#define MCF_PAD_PAR_FBCTL_PAR_BWE3 (0x4000)
/* Bit definitions and macros for MCF_PAD_PAR_FBCS */
#define MCF_PAD_PAR_FBCS_PAR_CS1 (0x2)
#define MCF_PAD_PAR_FBCS_PAR_CS2 (0x4)
#define MCF_PAD_PAR_FBCS_PAR_CS3 (0x8)
#define MCF_PAD_PAR_FBCS_PAR_CS4 (0x10)
#define MCF_PAD_PAR_FBCS_PAR_CS5 (0x20)
/* Bit definitions and macros for MCF_PAD_PAR_DMA */
#define MCF_PAD_PAR_DMA_PAR_DREQ0(x) (((x)&0x3)<<0)
#define MCF_PAD_PAR_DMA_PAR_DREQ0_GPIO (0)
#define MCF_PAD_PAR_DMA_PAR_DREQ0_TIN0 (0x2)
#define MCF_PAD_PAR_DMA_PAR_DREQ0_DREQ0 (0x3)
#define MCF_PAD_PAR_DMA_PAR_DREQ1(x) (((x)&0x3)<<0x2)
#define MCF_PAD_PAR_DMA_PAR_DREQ1_GPIO (0)
#define MCF_PAD_PAR_DMA_PAR_DREQ1_IRQ1 (0x4)
#define MCF_PAD_PAR_DMA_PAR_DREQ1_TIN1 (0x8)
#define MCF_PAD_PAR_DMA_PAR_DREQ1_DREQ1 (0xC)
#define MCF_PAD_PAR_DMA_PAR_DACK0(x) (((x)&0x3)<<0x4)
#define MCF_PAD_PAR_DMA_PAR_DACK0_GPIO (0)
#define MCF_PAD_PAR_DMA_PAR_DACK0_TOUT0 (0x20)
#define MCF_PAD_PAR_DMA_PAR_DACK0_DACK0 (0x30)
#define MCF_PAD_PAR_DMA_PAR_DACK1(x) (((x)&0x3)<<0x6)
#define MCF_PAD_PAR_DMA_PAR_DACK1_GPIO (0)
#define MCF_PAD_PAR_DMA_PAR_DACK1_TOUT1 (0x80)
#define MCF_PAD_PAR_DMA_PAR_DACK1_DACK1 (0xC0)
/* Bit definitions and macros for MCF_PAD_PAR_FECI2CIRQ */
#define MCF_PAD_PAR_FECI2CIRQ_PAR_IRQ5 (0x1)
#define MCF_PAD_PAR_FECI2CIRQ_PAR_IRQ6 (0x2)
#define MCF_PAD_PAR_FECI2CIRQ_PAR_SCL (0x4)
#define MCF_PAD_PAR_FECI2CIRQ_PAR_SDA (0x8)
#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDC(x) (((x)&0x3)<<0x6)
#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDC_SCL (0x80)
#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDC_E1MDC (0xC0)
#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDIO(x) (((x)&0x3)<<0x8)
#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDIO_SDA (0x200)
#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDIO_E1MDIO (0x300)
#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MII (0x400)
#define MCF_PAD_PAR_FECI2CIRQ_PAR_E17 (0x800)
#define MCF_PAD_PAR_FECI2CIRQ_PAR_E0MDC (0x1000)
#define MCF_PAD_PAR_FECI2CIRQ_PAR_E0MDIO (0x2000)
#define MCF_PAD_PAR_FECI2CIRQ_PAR_E0MII (0x4000)
#define MCF_PAD_PAR_FECI2CIRQ_PAR_E07 (0x8000)
/* Bit definitions and macros for MCF_PAD_PAR_PCIBG */
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0(x) (((x)&0x3)<<0)
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0_GPIO (0)
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0_TOUT0 (0x2)
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0_PCIBG0 (0x3)
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1(x) (((x)&0x3)<<0x2)
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1_GPIO (0)
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1_TOUT1 (0x8)
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1_PCIBG1 (0xC)
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2(x) (((x)&0x3)<<0x4)
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2_GPIO (0)
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2_TOUT2 (0x20)
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2_PCIBG2 (0x30)
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3(x) (((x)&0x3)<<0x6)
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3_GPIO (0)
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3_TOUT3 (0x80)
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3_PCIBG3 (0xC0)
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4(x) (((x)&0x3)<<0x8)
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4_GPIO (0)
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4_TBST (0x200)
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4_PCIBG4 (0x300)
/* Bit definitions and macros for MCF_PAD_PAR_PCIBR */
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0(x) (((x)&0x3)<<0)
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0_GPIO (0)
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0_TIN0 (0x2)
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0_PCIBR0 (0x3)
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1(x) (((x)&0x3)<<0x2)
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1_GPIO (0)
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1_TIN1 (0x8)
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1_PCIBR1 (0xC)
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2(x) (((x)&0x3)<<0x4)
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2_GPIO (0)
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2_TIN2 (0x20)
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2_PCIBR2 (0x30)
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3(x) (((x)&0x3)<<0x6)
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3_GPIO (0)
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3_TIN3 (0x80)
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3_PCIBR3 (0xC0)
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4(x) (((x)&0x3)<<0x8)
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4_GPIO (0)
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4_IRQ4 (0x200)
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4_PCIBR4 (0x300)
/* Bit definitions and macros for MCF_PAD_PAR_PSC3 */
#define MCF_PAD_PAR_PSC3_PAR_TXD3 (0x4)
#define MCF_PAD_PAR_PSC3_PAR_RXD3 (0x8)
#define MCF_PAD_PAR_PSC3_PAR_RTS3(x) (((x)&0x3)<<0x4)
#define MCF_PAD_PAR_PSC3_PAR_RTS3_GPIO (0)
#define MCF_PAD_PAR_PSC3_PAR_RTS3_FSYNC (0x20)
#define MCF_PAD_PAR_PSC3_PAR_RTS3_RTS (0x30)
#define MCF_PAD_PAR_PSC3_PAR_CTS3(x) (((x)&0x3)<<0x6)
#define MCF_PAD_PAR_PSC3_PAR_CTS3_GPIO (0)
#define MCF_PAD_PAR_PSC3_PAR_CTS3_BCLK (0x80)
#define MCF_PAD_PAR_PSC3_PAR_CTS3_CTS (0xC0)
/* Bit definitions and macros for MCF_PAD_PAR_PSC2 */
#define MCF_PAD_PAR_PSC2_PAR_TXD2 (0x4)
#define MCF_PAD_PAR_PSC2_PAR_RXD2 (0x8)
#define MCF_PAD_PAR_PSC2_PAR_RTS2(x) (((x)&0x3)<<0x4)
#define MCF_PAD_PAR_PSC2_PAR_RTS2_GPIO (0)
#define MCF_PAD_PAR_PSC2_PAR_RTS2_FSYNC (0x20)
#define MCF_PAD_PAR_PSC2_PAR_RTS2_RTS (0x30)
#define MCF_PAD_PAR_PSC2_PAR_CTS2(x) (((x)&0x3)<<0x6)
#define MCF_PAD_PAR_PSC2_PAR_CTS2_GPIO (0)
#define MCF_PAD_PAR_PSC2_PAR_CTS2_BCLK (0x80)
#define MCF_PAD_PAR_PSC2_PAR_CTS2_CTS (0xC0)
/* Bit definitions and macros for MCF_PAD_PAR_PSC1 */
#define MCF_PAD_PAR_PSC1_PAR_TXD1 (0x4)
#define MCF_PAD_PAR_PSC1_PAR_RXD1 (0x8)
#define MCF_PAD_PAR_PSC1_PAR_RTS1(x) (((x)&0x3)<<0x4)
#define MCF_PAD_PAR_PSC1_PAR_RTS1_GPIO (0)
#define MCF_PAD_PAR_PSC1_PAR_RTS1_FSYNC (0x20)
#define MCF_PAD_PAR_PSC1_PAR_RTS1_RTS (0x30)
#define MCF_PAD_PAR_PSC1_PAR_CTS1(x) (((x)&0x3)<<0x6)
#define MCF_PAD_PAR_PSC1_PAR_CTS1_GPIO (0)
#define MCF_PAD_PAR_PSC1_PAR_CTS1_BCLK (0x80)
#define MCF_PAD_PAR_PSC1_PAR_CTS1_CTS (0xC0)
/* Bit definitions and macros for MCF_PAD_PAR_PSC0 */
#define MCF_PAD_PAR_PSC0_PAR_TXD0 (0x4)
#define MCF_PAD_PAR_PSC0_PAR_RXD0 (0x8)
#define MCF_PAD_PAR_PSC0_PAR_RTS0(x) (((x)&0x3)<<0x4)
#define MCF_PAD_PAR_PSC0_PAR_RTS0_GPIO (0)
#define MCF_PAD_PAR_PSC0_PAR_RTS0_FSYNC (0x20)
#define MCF_PAD_PAR_PSC0_PAR_RTS0_RTS (0x30)
#define MCF_PAD_PAR_PSC0_PAR_CTS0(x) (((x)&0x3)<<0x6)
#define MCF_PAD_PAR_PSC0_PAR_CTS0_GPIO (0)
#define MCF_PAD_PAR_PSC0_PAR_CTS0_BCLK (0x80)
#define MCF_PAD_PAR_PSC0_PAR_CTS0_CTS (0xC0)
/* Bit definitions and macros for MCF_PAD_PAR_DSPI */
#define MCF_PAD_PAR_DSPI_PAR_SOUT(x) (((x)&0x3)<<0)
#define MCF_PAD_PAR_DSPI_PAR_SOUT_GPIO (0)
#define MCF_PAD_PAR_DSPI_PAR_SOUT_TXD (0x2)
#define MCF_PAD_PAR_DSPI_PAR_SOUT_SOUT (0x3)
#define MCF_PAD_PAR_DSPI_PAR_SIN(x) (((x)&0x3)<<0x2)
#define MCF_PAD_PAR_DSPI_PAR_SIN_GPIO (0)
#define MCF_PAD_PAR_DSPI_PAR_SIN_RXD (0x8)
#define MCF_PAD_PAR_DSPI_PAR_SIN_SIN (0xC)
#define MCF_PAD_PAR_DSPI_PAR_SCK(x) (((x)&0x3)<<0x4)
#define MCF_PAD_PAR_DSPI_PAR_SCK_GPIO (0)
#define MCF_PAD_PAR_DSPI_PAR_SCK_BCLK (0x10)
#define MCF_PAD_PAR_DSPI_PAR_SCK_CTS (0x20)
#define MCF_PAD_PAR_DSPI_PAR_SCK_SCK (0x30)
#define MCF_PAD_PAR_DSPI_PAR_CS0(x) (((x)&0x3)<<0x6)
#define MCF_PAD_PAR_DSPI_PAR_CS0_GPIO (0)
#define MCF_PAD_PAR_DSPI_PAR_CS0_FSYNC (0x40)
#define MCF_PAD_PAR_DSPI_PAR_CS0_RTS (0x80)
#define MCF_PAD_PAR_DSPI_PAR_CS0_DSPICS0 (0xC0)
#define MCF_PAD_PAR_DSPI_PAR_CS2(x) (((x)&0x3)<<0x8)
#define MCF_PAD_PAR_DSPI_PAR_CS2_GPIO (0)
#define MCF_PAD_PAR_DSPI_PAR_CS2_TOUT2 (0x200)
#define MCF_PAD_PAR_DSPI_PAR_CS2_DSPICS2 (0x300)
#define MCF_PAD_PAR_DSPI_PAR_CS3(x) (((x)&0x3)<<0xA)
#define MCF_PAD_PAR_DSPI_PAR_CS3_GPIO (0)
#define MCF_PAD_PAR_DSPI_PAR_CS3_TOUT3 (0x800)
#define MCF_PAD_PAR_DSPI_PAR_CS3_DSPICS3 (0xC00)
#define MCF_PAD_PAR_DSPI_PAR_CS5 (0x1000)
/* Bit definitions and macros for MCF_PAD_PAR_TIMER */
#define MCF_PAD_PAR_TIMER_PAR_TOUT2 (0x1)
#define MCF_PAD_PAR_TIMER_PAR_TIN2(x) (((x)&0x3)<<0x1)
#define MCF_PAD_PAR_TIMER_PAR_TIN2_IRQ2 (0x4)
#define MCF_PAD_PAR_TIMER_PAR_TIN2_TIN2 (0x6)
#define MCF_PAD_PAR_TIMER_PAR_TOUT3 (0x8)
#define MCF_PAD_PAR_TIMER_PAR_TIN3(x) (((x)&0x3)<<0x4)
#define MCF_PAD_PAR_TIMER_PAR_TIN3_IRQ3 (0x20)
#define MCF_PAD_PAR_TIMER_PAR_TIN3_TIN3 (0x30)
#endif /* __MCF5475_PAD_H__ */

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