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compare: Firebee:R_0_8_6
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Firebee:R_0_9_5 Firebee:R_0_9_4 Firebee:R_0_9_3 Firebee:R_0_9_1 Firebee:R_0_9 Firebee:R_0_8_8 Firebee:R_0_8_7 Firebee:R_0_8_6 Firebee:R_0_8_5 Firebee:R_0_8_3 Firebee:R_0_8 Firebee:r_0.1

20 Commits
R_0_8_5 ... R_0_8_6

Author SHA1 Message Date
Markus Fröschle
40162047d8 (hopefully) fixed a problem with hang when i2c communication to TFP410 fails 2014-12-28 22:47:43 +00:00
Markus Fröschle
f871794760 fixed bug that prevented proper detection of FPGA load skip request 2014-12-26 08:56:30 +00:00
Markus Fröschle
88c1bd2373 fixed errornous deactivation of FPGA load 2014-12-26 07:26:10 +00:00
Markus Fröschle
5163fd5813 file release to officially support m548x with EmuTOS 2014-08-06 06:25:41 +00:00
Markus Fröschle
1e471ec8cd bumped version for release 2014-08-06 06:23:30 +00:00
Markus Fröschle
e3e202a7cc added tos programs that are used to interface to BaS_gcc from TOS. These programs are currently not build by default (need to call make in their respective directory for now). They expect to find a libcmini copy on the same directory level than you have your BaS_gcc folder. 2014-08-02 08:25:07 +00:00
David Gálvez
8b8206cf97 Add format specifier to fix debug messages format 2014-07-13 15:18:23 +00:00
David Gálvez
77d134150a Make PCI memory space uncachable 2014-07-10 16:46:21 +00:00
David Gálvez
8d62eb705f Merge pci_BaS_gcc branch to trunk 2014-07-10 15:45:45 +00:00
Markus Fröschle
68aac6bf71 fixed formatting 2014-06-23 18:23:44 +00:00
Markus Fröschle
067b31c31d fixed formatting 2014-06-23 05:46:13 +00:00
Markus Fröschle
53644425ea fixed compiler warnings 2014-06-23 05:37:51 +00:00
Markus Fröschle
2ba3d52843 fixed a few compiler warnings 2014-06-23 05:32:49 +00:00
Markus Fröschle
7fd0c0c663 modified init_fpga() to honour JTAG configuration. Does not work 
currently and needs support from the TOS side (program not finished yet)
 2014-06-22 16:00:49 +00:00
Markus Fröschle
ae44abc952 added Doxyfile for doxygen documentation 2014-06-21 19:53:54 +00:00
Markus Fröschle
1dc12f4b05 added BaS includes 2014-06-21 19:52:23 +00:00
Markus Fröschle
49e3eb31e4 added ST fonts 2014-06-21 19:48:22 +00:00
David Gálvez
73f75895bc Add driver interface for PCI 2014-05-21 08:40:50 +00:00
David Gálvez
f0d0af7add Create new branch for PCI development 2014-05-21 07:38:47 +00:00
Markus Fröschle
a23abf0b5d corresponds to the equivalent file release. Contains networking code for EmuTOS, PCI bus scan and card configuration. X86emu included but deactivated. 2014-01-06 19:50:52 +00:00
36 changed files with 6167 additions and 2523 deletions
Expand all files Collapse all files

1689
Doxyfile Normal file
View File

File diff suppressed because it is too large Load Diff

4
Makefile
View File

@@ -124,6 +124,7 @@ CSRCS= \
radeon_accel.c \
radeon_cursor.c \
radeon_monitor.c \
fnt_st_8x16.c \
\
x86decode.c \
x86sys.c \
@@ -143,7 +144,8 @@ ASRCS= \
startcf.S \
printf_helper.S \
exceptions.S \
xhdi_vec.S
xhdi_vec.S \
pci_wrappers.S
SRCS=$(ASRCS) $(CSRCS)
COBJS=$(patsubst %.c,%.o,$(CSRCS))

386
bas.lk.in
View File

@@ -19,236 +19,244 @@ MEMORY
{
bas_rom (ROMFLAGS) : ORIGIN = TARGET_ADDRESS, LENGTH = 0x00100000
/*
* target to copy BaS data segment to. 1M should be enough for now
*/
* target to copy BaS data segment to. 1M should be enough for now
*/
bas_ram (WX) : ORIGIN = SDRAM_START + SDRAM_SIZE - 0x00200000, LENGTH = 0x00100000
/*
* driver_ram is an uncached, reserved memory area for drivers (e.g. USB) that need this type of memory
*/
* driver_ram is an uncached, reserved memory area for drivers (e.g. USB) that need this type of memory
*/
driver_ram (WX) : ORIGIN = SDRAM_START + SDRAM_SIZE - 0x00100000, LENGTH = 0x00100000
}
SECTIONS
{
/* BaS in ROM */
.text :
{
OBJDIR/startcf.o(.text) /* this one is the entry point so it must be the first */
/* BaS in ROM */
.text :
{
OBJDIR/startcf.o(.text) /* this one is the entry point so it must be the first */
OBJDIR/sysinit.o(.text)
OBJDIR/fault_vectors.o(.text)
OBJDIR/sysinit.o(.text)
OBJDIR/fault_vectors.o(.text)
#ifdef MACHINE_FIREBEE
OBJDIR/init_fpga.o(.text)
OBJDIR/init_fpga.o(.text)
#endif /* MACHINE_FIREBEE */
OBJDIR/wait.o(.text)
OBJDIR/exceptions.o(.text)
OBJDIR/driver_vec.o(.text)
OBJDIR/interrupts.o(.text)
OBJDIR/mmu.o(.text)
OBJDIR/BaS.o(.text)
OBJDIR/pci.o(.text)
OBJDIR/usb.o(.text)
OBJDIR/driver_mem.o(.text)
OBJDIR/usb_mouse.o(.text)
OBJDIR/ohci-hcd.o(.text)
OBJDIR/ehci-hcd.o(.text)
OBJDIR/wait.o(.text)
OBJDIR/wait.o(.text)
OBJDIR/exceptions.o(.text)
OBJDIR/driver_vec.o(.text)
OBJDIR/interrupts.o(.text)
OBJDIR/mmu.o(.text)
OBJDIR/nbuf.o(.text)
OBJDIR/net_timer.o(.text)
OBJDIR/queue.o(.text)
OBJDIR/nif.o(.text)
OBJDIR/fecbd.o(.text)
OBJDIR/fec.o(.text)
OBJDIR/am79c874.o(.text)
OBJDIR/bcm5222.o(.text)
OBJDIR/ip.o(.text)
OBJDIR/udp.o(text)
OBJDIR/bootp.o(text)
OBJDIR/tftp.o(text)
OBJDIR/arp.o(text)
OBJDIR/BaS.o(.text)
OBJDIR/pci.o(.text)
OBJDIR/pci_wrappers.o(.text)
OBJDIR/usb.o(.text)
OBJDIR/driver_mem.o(.text)
OBJDIR/usb_mouse.o(.text)
OBJDIR/ohci-hcd.o(.text)
OBJDIR/ehci-hcd.o(.text)
OBJDIR/wait.o(.text)
OBJDIR/unicode.o(.text)
OBJDIR/mmc.o(.text)
OBJDIR/ff.o(.text)
OBJDIR/sd_card.o(.text)
OBJDIR/s19reader.o(.text)
OBJDIR/bas_printf.o(.text)
OBJDIR/bas_string.o(.text)
OBJDIR/printf_helper.o(.text)
OBJDIR/cache.o(.text)
OBJDIR/dma.o(.text)
OBJDIR/MCD_dmaApi.o(.text)
OBJDIR/MCD_tasks.o(.text)
OBJDIR/MCD_tasksInit.o(.text)
OBJDIR/nbuf.o(.text)
OBJDIR/net_timer.o(.text)
OBJDIR/queue.o(.text)
OBJDIR/nif.o(.text)
OBJDIR/fecbd.o(.text)
OBJDIR/fec.o(.text)
OBJDIR/am79c874.o(.text)
OBJDIR/bcm5222.o(.text)
OBJDIR/ip.o(.text)
OBJDIR/udp.o(text)
OBJDIR/bootp.o(text)
OBJDIR/tftp.o(text)
OBJDIR/arp.o(text)
OBJDIR/video.o(.text)
OBJDIR/videl.o(.text)
OBJDIR/fbmem.o(.text)
OBJDIR/fbmon.o(.text)
OBJDIR/fbmodedb.o(.text)
OBJDIR/offscreen.o(.text)
OBJDIR/unicode.o(.text)
OBJDIR/mmc.o(.text)
OBJDIR/ff.o(.text)
OBJDIR/sd_card.o(.text)
OBJDIR/s19reader.o(.text)
OBJDIR/bas_printf.o(.text)
OBJDIR/bas_string.o(.text)
OBJDIR/printf_helper.o(.text)
OBJDIR/cache.o(.text)
OBJDIR/dma.o(.text)
OBJDIR/MCD_dmaApi.o(.text)
OBJDIR/MCD_tasks.o(.text)
OBJDIR/MCD_tasksInit.o(.text)
OBJDIR/x86decode.o(.text)
OBJDIR/x86ops.o(.text)
OBJDIR/x86ops2.o(.text)
OBJDIR/x86fpu.o(.text)
OBJDIR/x86sys.o(.text)
OBJDIR/x86biosemu.o(.text)
OBJDIR/x86debug.o(.text)
OBJDIR/x86prim_ops.o(.text)
OBJDIR/x86pcibios.o(.text)
OBJDIR/video.o(.text)
OBJDIR/videl.o(.text)
OBJDIR/fbmem.o(.text)
OBJDIR/fbmon.o(.text)
OBJDIR/fbmodedb.o(.text)
OBJDIR/offscreen.o(.text)
OBJDIR/radeon_base.o(.text)
OBJDIR/radeon_accel.o(.text)
OBJDIR/radeon_cursor.o(.text)
OBJDIR/radeon_monitor.o(.text)
OBJDIR/x86decode.o(.text)
OBJDIR/x86ops.o(.text)
OBJDIR/x86ops2.o(.text)
OBJDIR/x86fpu.o(.text)
OBJDIR/x86sys.o(.text)
OBJDIR/x86biosemu.o(.text)
OBJDIR/x86debug.o(.text)
OBJDIR/x86prim_ops.o(.text)
OBJDIR/x86pcibios.o(.text)
OBJDIR/radeon_base.o(.text)
OBJDIR/radeon_accel.o(.text)
OBJDIR/radeon_cursor.o(.text)
OBJDIR/radeon_monitor.o(.text)
OBJDIR/xhdi_sd.o(.text)
OBJDIR/xhdi_interface.o(.text)
OBJDIR/xhdi_vec.o(.text)
OBJDIR/xhdi_sd.o(.text)
OBJDIR/xhdi_interface.o(.text)
OBJDIR/xhdi_vec.o(.text)
#ifdef COMPILE_RAM
/*
* if we compile to RAM anyway, there is no need to copy anything
*/
. = ALIGN(4);
__BAS_DATA_START = .;
*(.data)
__BAS_DATA_END = .;
__BAS_BSS_START = .;
*(.bss)
__BAS_BSS_END = .;
/*
* if we compile to RAM anyway, there is no need to copy anything
*/
. = ALIGN(4);
__BAS_DATA_START = .;
*(.data)
__BAS_DATA_END = .;
__BAS_BSS_START = .;
*(.bss)
__BAS_BSS_END = .;
#endif /* COMPILE_RAM */
#if (FORMAT_ELF == 1)
*(.rodata)
*(.rodata.*)
*(.rodata)
*(.rodata.*)
#endif
} > bas_rom
} > bas_rom
#if (TARGET_ADDRESS == BOOTFLASH_BASE_ADDRESS)
/*
* put BaS .data and .bss segments to flash, but relocate it to RAM after initialize_hardware() ran
*/
.bas :
AT (ALIGN(ADDR(.text) + SIZEOF(.text), 4))
{
. = ALIGN(4); /* same alignment than AT() statement! */
__BAS_DATA_START = .;
*(.data)
__BAS_DATA_END = .;
__BAS_BSS_START = .;
*(.bss)
__BAS_BSS_END = .;
/*
* put BaS .data and .bss segments to flash, but relocate it to RAM after initialize_hardware() ran
*/
.bas :
AT (ALIGN(ADDR(.text) + SIZEOF(.text), 4))
{
. = ALIGN(4); /* same alignment than AT() statement! */
__BAS_DATA_START = .;
*(.data)
__BAS_DATA_END = .;
__BAS_BSS_START = .;
*(.bss)
__BAS_BSS_END = .;
. = ALIGN(16);
} > bas_ram
. = ALIGN(16);
} > bas_ram
#endif
.driver_memory :
{
. = ALIGN(4);
_driver_mem_buffer = .;
//. = . + DRIVER_MEM_BUFFER_SIZE;
} > driver_ram
/*
* Global memory map
*/
.driver_memory :
{
. = ALIGN(4);
_driver_mem_buffer = .;
//. = . + DRIVER_MEM_BUFFER_SIZE;
} > driver_ram
/* SDRAM Initialization */
___SDRAM = SDRAM_START;
___SDRAM_SIZE = SDRAM_SIZE;
_SDRAM_VECTOR_TABLE = ___SDRAM;
/* ST-RAM */
__STRAM = ___SDRAM;
__STRAM_END = __TOS;
/*
* Global memory map
*/
/* TOS */
__TOS = 0x00e00000;
/* SDRAM Initialization */
___SDRAM = SDRAM_START;
___SDRAM_SIZE = SDRAM_SIZE;
_SDRAM_VECTOR_TABLE = ___SDRAM;
/* FastRAM */
__FASTRAM = 0x10000000;
__TARGET_ADDRESS = TARGET_ADDRESS;
#if TARGET_ADDRESS == BOOTFLASH_BASE_ADDRESS
__FASTRAM_END = __BAS_IN_RAM;
#else
__FASTRAM_END = TARGET_ADDRESS;
#endif
__FASTRAM_SIZE = __FASTRAM_END - __FASTRAM;
/* ST-RAM */
__STRAM = ___SDRAM;
__STRAM_END = __TOS;
/* Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes) */
___BOOT_FLASH = BOOTFLASH_BASE_ADDRESS;
___BOOT_FLASH_SIZE = BOOTFLASH_SIZE;
/* TOS */
__TOS = 0x00e00000;
/* FastRAM */
__FASTRAM = 0x10000000;
__TARGET_ADDRESS = TARGET_ADDRESS;
#if TARGET_ADDRESS == BOOTFLASH_BASE_ADDRESS
/* BaS */
__BAS_LMA = LOADADDR(.bas);
__BAS_IN_RAM = ADDR(.bas);
__BAS_SIZE = SIZEOF(.bas);
__FASTRAM_END = __BAS_IN_RAM;
#else
/* BaS is already in RAM - no need to copy anything */
__BAS_IN_RAM = __FASTRAM_END;
__BAS_SIZE = 0;
__BAS_LMA = __BAS_IN_RAM;
__FASTRAM_END = TARGET_ADDRESS;
#endif
__FASTRAM_SIZE = __FASTRAM_END - __FASTRAM;
/* Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes) */
___BOOT_FLASH = BOOTFLASH_BASE_ADDRESS;
___BOOT_FLASH_SIZE = BOOTFLASH_SIZE;
#if TARGET_ADDRESS == BOOTFLASH_BASE_ADDRESS
/* BaS */
__BAS_LMA = LOADADDR(.bas);
__BAS_IN_RAM = ADDR(.bas);
__BAS_SIZE = SIZEOF(.bas);
#else
/* BaS is already in RAM - no need to copy anything */
__BAS_IN_RAM = __FASTRAM_END;
__BAS_SIZE = 0;
__BAS_LMA = __BAS_IN_RAM;
#endif
/* Other flash components */
__FIRETOS = 0xe0400000;
__EMUTOS = EMUTOS_BASE_ADDRESS;
__EMUTOS_SIZE = 0x00100000;
/* Other flash components */
__FIRETOS = 0xe0400000;
__EMUTOS = EMUTOS_BASE_ADDRESS;
__EMUTOS_SIZE = 0x00100000;
/* where FPGA data lives in flash */
__FPGA_FLASH_DATA = 0xe0700000;
__FPGA_FLASH_DATA_SIZE = 0x100000;
/* where FPGA data lives in flash */
__FPGA_CONFIG = 0xe0700000;
__FPGA_CONFIG_SIZE = 0x100000;
/* VIDEO RAM BASIS */
__VRAM = 0x60000000;
/* VIDEO RAM BASIS */
__VRAM = 0x60000000;
/* Memory mapped registers */
__MBAR = 0xFF000000;
/* 32KB on-chip System SRAM */
__SYS_SRAM = __MBAR + 0x10000;
__SYS_SRAM_SIZE = 0x00008000;
/* Memory mapped registers */
__MBAR = 0xFF000000;
/* MMU memory mapped registers */
__MMUBAR = 0xFF040000;
/* 32KB on-chip System SRAM */
__SYS_SRAM = __MBAR + 0x10000;
__SYS_SRAM_SIZE = 0x00008000;
/*
* 4KB on-chip Core SRAM0: -> exception table
*/
__RAMBAR0 = 0xFF100000;
__RAMBAR0_SIZE = 0x00001000;
/* MMU memory mapped registers */
__MMUBAR = 0xFF040000;
/* 4KB on-chip Core SRAM1 */
__RAMBAR1 = 0xFF101000;
__RAMBAR1_SIZE = 0x00001000;
__SUP_SP = __RAMBAR0 + __RAMBAR0_SIZE - 4;
/*
* 4KB on-chip Core SRAM0: -> exception table
*/
__RAMBAR0 = 0xFF100000;
__RAMBAR0_SIZE = 0x00001000;
/* system variables */
/* RAMBAR0 0 to 0x7FF -> exception vectors */
_rt_mod = __RAMBAR0 + 0x800;
_rt_ssp = __RAMBAR0 + 0x804;
_rt_usp = __RAMBAR0 + 0x808;
_rt_vbr = __RAMBAR0 + 0x80C; /* (8)01 */
_rt_cacr = __RAMBAR0 + 0x810; /* 002 */
_rt_asid = __RAMBAR0 + 0x814; /* 003 */
_rt_acr0 = __RAMBAR0 + 0x818; /* 004 */
_rt_acr1 = __RAMBAR0 + 0x81c; /* 005 */
_rt_acr2 = __RAMBAR0 + 0x820; /* 006 */
_rt_acr3 = __RAMBAR0 + 0x824; /* 007 */
_rt_mmubar = __RAMBAR0 + 0x828; /* 008 */
_rt_sr = __RAMBAR0 + 0x82c;
_d0_save = __RAMBAR0 + 0x830;
_a7_save = __RAMBAR0 + 0x834;
_video_tlb = __RAMBAR0 + 0x838;
_video_sbt = __RAMBAR0 + 0x83C;
_rt_mbar = __RAMBAR0 + 0x844; /* (c)0f */
/* 4KB on-chip Core SRAM1 */
__RAMBAR1 = 0xFF101000;
__RAMBAR1_SIZE = 0x00001000;
__SUP_SP = __RAMBAR1 + __RAMBAR1_SIZE - 4;
/*
* this flag (if 1) indicates that FPGA configuration has been loaded through JTAG
* and shouldn't be overwritten on boot
*/
__FPGA_JTAG_LOADED = __RAMBAR1;
__FPGA_JTAG_VALID = __FPGA_JTAG_LOADED + 4;
/* system variables */
/* RAMBAR0 0 to 0x7FF -> exception vectors */
_rt_mod = __RAMBAR0 + 0x800;
_rt_ssp = __RAMBAR0 + 0x804;
_rt_usp = __RAMBAR0 + 0x808;
_rt_vbr = __RAMBAR0 + 0x80C; /* (8)01 */
_rt_cacr = __RAMBAR0 + 0x810; /* 002 */
_rt_asid = __RAMBAR0 + 0x814; /* 003 */
_rt_acr0 = __RAMBAR0 + 0x818; /* 004 */
_rt_acr1 = __RAMBAR0 + 0x81c; /* 005 */
_rt_acr2 = __RAMBAR0 + 0x820; /* 006 */
_rt_acr3 = __RAMBAR0 + 0x824; /* 007 */
_rt_mmubar = __RAMBAR0 + 0x828; /* 008 */
_rt_sr = __RAMBAR0 + 0x82c;
_d0_save = __RAMBAR0 + 0x830;
_a7_save = __RAMBAR0 + 0x834;
_video_tlb = __RAMBAR0 + 0x838;
_video_sbt = __RAMBAR0 + 0x83C;
_rt_mbar = __RAMBAR0 + 0x844; /* (c)0f */
}

34
dma/dma.c
View File

@@ -39,7 +39,7 @@
#error "unknown machine!"
#endif /* MACHINE_FIREBEE */
#define DBG_DMA
// #define DBG_DMA
#ifdef DBG_DMA
#define dbg(format, arg...) do { xprintf("DEBUG: " format, ##arg); } while (0)
#else
@@ -58,13 +58,13 @@ struct dma_channel
static char used_reqs[32] =
{
DMA_ALWAYS, DMA_DSPI_RXFIFO, DMA_DSPI_TXFIFO, DMA_DREQ0,
DMA_PSC0_RX, DMA_PSC0_TX, DMA_USB_EP0, DMA_USB_EP1,
DMA_USB_EP2, DMA_USB_EP3, DMA_PCI_TX, DMA_PCI_RX,
DMA_PSC1_RX, DMA_PSC1_TX, DMA_I2C_RX, DMA_I2C_TX,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0
DMA_PSC0_RX, DMA_PSC0_TX, DMA_USB_EP0, DMA_USB_EP1,
DMA_USB_EP2, DMA_USB_EP3, DMA_PCI_TX, DMA_PCI_RX,
DMA_PSC1_RX, DMA_PSC1_TX, DMA_I2C_RX, DMA_I2C_TX,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0,
0, 0, 0, 0
};
static struct dma_channel dma_channel[NCHANNELS] =
@@ -225,7 +225,7 @@ int dma_set_initiator(int initiator)
else /* No empty slots */
{
dbg("%s: no free slot\r\n", __FUNCTION__);
return 1;
}
break;
@@ -530,7 +530,7 @@ int dma_get_channel(int requestor)
}
/*
* Remove the channel being initiated by the given requestor from
* Remove the channel being initiated by the given requestor from
* the active list
*
* Parameters:
@@ -551,8 +551,8 @@ void dma_free_channel(int requestor)
}
}
/*
* This is the catch-all interrupt handler for the mult-channel DMA
/*
* This is the catch-all interrupt handler for the mult-channel DMA
*/
int dma_interrupt_handler(void *arg1, void *arg2)
{
@@ -560,8 +560,8 @@ int dma_interrupt_handler(void *arg1, void *arg2)
(void) set_ipl(7);
/*
* Determine which interrupt(s) triggered by AND'ing the
/*
* Determine which interrupt(s) triggered by AND'ing the
* pending interrupts with those that aren't masked.
*/
interrupts = MCF_DMA_DIPR & ~MCF_DMA_DIMR;
@@ -598,9 +598,9 @@ void *dma_memcpy(void *dst, void *src, size_t n)
int ret;
#ifdef DBG_DMA
int32_t time;
int32_t start;
int32_t end;
int32_t time;
int32_t start;
int32_t end;
start = MCF_SLT0_SCNT;
#endif /* DBG_DMA */

89
flash_scripts/flash_firebee_bas.bdm
View File

@@ -1,4 +1,4 @@
#!/usr/local/bin/bdmctrl
#!/usr/local/bin/bdmctrl -D2
#
# firebee board initialization for bdmctrl
#
@@ -21,32 +21,32 @@ write 0xFF000508 0x00001180 4
write 0xFF000504 0x007F0001 4
# SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes
write 0xFF000004 0x000002AA 4 # SDRAMDS configuration
write 0xFF000020 0x0000001A 4 # SDRAM CS0 configuration (128Mbytes 0000_0000 - 07FF_FFFF)
write 0xFF000024 0x0800001A 4 # SDRAM CS1 configuration (128Mbytes 0800_0000 - 0FFF_FFFF)
write 0xFF000028 0x1000001A 4 # SDRAM CS2 configuration (128Mbytes 1000_0000 - 17FF_FFFF)
write 0xFF00002C 0x1800001A 4 # SDRAM CS3 configuration (128Mbytes 1800_0000 - 1FFF_FFFF)
write 0xFF000108 0x73622830 4 # SDCFG1
write 0xFF00010C 0x46770000 4 # SDCFG2
#write 0xFF000004 0x000002AA 4 # SDRAMDS configuration
#write 0xFF000020 0x0000001A 4 # SDRAM CS0 configuration (128Mbytes 0000_0000 - 07FF_FFFF)
#write 0xFF000024 0x0800001A 4 # SDRAM CS1 configuration (128Mbytes 0800_0000 - 0FFF_FFFF)
#write 0xFF000028 0x1000001A 4 # SDRAM CS2 configuration (128Mbytes 1000_0000 - 17FF_FFFF)
#write 0xFF00002C 0x1800001A 4 # SDRAM CS3 configuration (128Mbytes 1800_0000 - 1FFF_FFFF)
#write 0xFF000108 0x73622830 4 # SDCFG1
#write 0xFF00010C 0x46770000 4 # SDCFG2
write 0xFF000104 0xE10D0002 4 # SDCR + IPALL
write 0xFF000100 0x40010000 4 # SDMR (write to LEMR)
write 0xFF000100 0x048D0000 4 # SDMR (write to LMR)
sleep 100
write 0xFF000104 0xE10D0002 4 # SDCR + IPALL
write 0xFF000104 0xE10D0004 4 # SDCR + IREF (first refresh)
write 0xFF000104 0xE10D0004 4 # SDCR + IREF (first refresh)
write 0xFF000100 0x008D0000 4 # SDMR (write to LMR)
write 0xFF000104 0x710D0F00 4 # SDCR (lock SDMR and enable refresh)
sleep 10
#write 0xFF000104 0xE10D0002 4 # SDCR + IPALL
#write 0xFF000100 0x40010000 4 # SDMR (write to LEMR)
#write 0xFF000100 0x048D0000 4 # SDMR (write to LMR)
#sleep 100
#write 0xFF000104 0xE10D0002 4 # SDCR + IPALL
#write 0xFF000104 0xE10D0004 4 # SDCR + IREF (first refresh)
#write 0xFF000104 0xE10D0004 4 # SDCR + IREF (first refresh)
#write 0xFF000100 0x008D0000 4 # SDMR (write to LMR)
#write 0xFF000104 0x710D0F00 4 # SDCR (lock SDMR and enable refresh)
#sleep 10
# use system sdram as flashlib scratch area.
# TODO: plugin flashing seems to work o.k. now for smaller binaries, while it doesn't for larger ones (EmuTOS) yet.
# This seems to be related to large flash buffers and PC-relative adressing of the plugin
flash-plugin 0x1000 0xf000 flash29.plugin
#flash-plugin 0x1000 0xf000 flash29-5475.plugin
# notify flashlib that we have flash at address 0xE0000000, length 0x7FFFFF, plugin is flash29
flash 0xE0000000
flash 0xe0000000
# Erase flash from 0xE0000000 to 0xE00FFFFF (reserved space for BaS)
#
@@ -55,17 +55,44 @@ flash 0xE0000000
#
# contrary to documentation, it seems we need to erase-wait after each sector
erase 0xE0000000 0
erase 0xE0000000 1
erase 0xE0000000 2
erase 0xE0000000 3
erase 0xE0000000 4
erase 0xE0000000 5
erase 0xE0000000 7
erase 0xE0000000 8
erase 0xE0000000 9
erase 0xE0000000 10
erase-wait 0xE0000000
erase 0xe0000000 0
erase-wait 0xe0000000
erase 0xe0000000 0x1000
erase-wait 0xe0000000
erase 0xe0000000 0x2000
erase-wait 0xe0000000
erase 0xe0000000 0x3000
erase-wait 0xe0000000
erase 0xe0000000 0x4000
erase-wait 0xe0000000
erase 0xe0000000 0x5000
erase-wait 0xe0000000
erase 0xe0000000 0x6000
erase-wait 0xe0000000
erase 0xe0000000 0x7000
erase-wait 0xe0000000
erase 0xe0000000 0x8000
erase-wait 0xe0000000
erase 0xe0000000 0x10000
erase-wait 0xe0000000
erase 0xe0000000 0x18000
erase-wait 0xe0000000
erase 0xe0000000 0x20000
erase-wait 0xe0000000
erase 0xe0000000 0x28000
erase-wait 0xe0000000
erase 0xe0000000 0x30000
erase-wait 0xe0000000
erase 0xe0000000 0x38000
erase-wait 0xe0000000
erase 0xe0000000 0x40000
erase-wait 0xe0000000
erase 0xe0000000 0x48000
erase-wait 0xe0000000
erase 0xe0000000 0x50000
erase-wait 0xe0000000
erase 0xe0000000 0x58000
erase-wait 0xe0000000
load -v ../firebee/bas.elf
wait

235
if/driver_vec.c
View File

@@ -23,20 +23,21 @@
* Author: Markus Fröschle
*/
#include <stdint.h>
#include <stddef.h>
#include <bas_types.h>
#include "version.h"
#include "xhdi_sd.h"
#include "dma.h"
#include "driver_vec.h"
#include "driver_mem.h"
#include "pci.h"
#include "mmu.h"
/*
* driver interface struct for the SD card BaS driver
*/
static struct xhdi_driver_interface xhdi_call_interface =
static struct xhdi_driver_interface xhdi_call_interface =
{
xhdi_call
xhdi_call
};
/*
@@ -46,90 +47,194 @@ static struct xhdi_driver_interface xhdi_call_interface =
*/
static struct dma_driver_interface dma_interface =
{
.version = 0x0101,
.magic = 0x444d4143, /* 'DMAC' */
.dma_set_initiator = dma_set_initiator,
.dma_get_initiator = dma_get_initiator,
.dma_free_initiator = dma_free_initiator,
.dma_set_channel = dma_set_channel,
.dma_get_channel = dma_get_channel,
.dma_free_channel = dma_free_channel,
.dma_clear_channel = dma_clear_channel,
.MCD_startDma = MCD_startDma,
.MCD_dmaStatus = MCD_dmaStatus,
.MCD_XferProgrQuery = MCD_XferProgrQuery,
.MCD_killDma = MCD_killDma,
.MCD_continDma = MCD_continDma,
.MCD_pauseDma = MCD_pauseDma,
.MCD_resumeDma = MCD_resumeDma,
.MCD_csumQuery = MCD_csumQuery,
.dma_malloc = driver_mem_alloc,
.dma_free = driver_mem_free
.version = 0x0101,
.magic = 0x444d4143, /* 'DMAC' */
.dma_set_initiator = dma_set_initiator,
.dma_get_initiator = dma_get_initiator,
.dma_free_initiator = dma_free_initiator,
.dma_set_channel = dma_set_channel,
.dma_get_channel = dma_get_channel,
.dma_free_channel = dma_free_channel,
.dma_clear_channel = dma_clear_channel,
.MCD_startDma = (int (*)(long, int8_t *, unsigned int, int8_t *, unsigned int,
unsigned int, unsigned int, unsigned int, int,
unsigned int, unsigned int)) MCD_startDma,
.MCD_dmaStatus = (int32_t (*)(int32_t)) MCD_dmaStatus,
.MCD_XferProgrQuery = (int32_t (*)(int32_t, MCD_XferProg *)) MCD_XferProgrQuery,
.MCD_killDma = (int32_t (*)(int32_t)) MCD_killDma,
.MCD_continDma = (int32_t (*)(int32_t)) MCD_continDma,
.MCD_pauseDma = (int32_t (*)(int32_t)) MCD_pauseDma,
.MCD_resumeDma = (int32_t (*)(int32_t)) MCD_resumeDma,
.MCD_csumQuery = (int32_t (*)(int32_t, uint32_t *)) MCD_csumQuery,
.dma_malloc = driver_mem_alloc,
.dma_free = driver_mem_free
};
extern const struct fb_info *info_fb;
extern struct fb_info *info_fb;
/*
* driver interface struct for the PCI_BIOS BaS driver
*/
static struct pci_bios_interface pci_interface =
{
.subjar = 0,
.version = 0x00010000,
.find_pci_device = wrapper_find_pci_device,
.find_pci_classcode = wrapper_find_pci_classcode,
.read_config_byte = wrapper_read_config_byte,
.read_config_word = wrapper_read_config_word,
.read_config_longword = wrapper_read_config_longword,
.fast_read_config_byte = wrapper_fast_read_config_byte,
.fast_read_config_word = wrapper_fast_read_config_word,
.fast_read_config_longword = wrapper_fast_read_config_longword,
.write_config_byte = wrapper_write_config_byte,
.write_config_word = wrapper_write_config_word,
.write_config_longword = wrapper_write_config_longword,
.hook_interrupt = wrapper_hook_interrupt,
.unhook_interrupt = wrapper_unhook_interrupt,
.special_cycle = wrapper_special_cycle,
.get_routing = wrapper_get_routing,
.set_interrupt = wrapper_set_interrupt,
.get_resource = wrapper_get_resource,
.get_card_used = wrapper_get_card_used,
.set_card_used = wrapper_set_card_used,
.read_mem_byte = wrapper_read_mem_byte,
.read_mem_word = wrapper_read_mem_word,
.read_mem_longword = wrapper_read_mem_longword,
.fast_read_mem_byte = wrapper_fast_read_mem_byte,
.fast_read_mem_word = wrapper_fast_read_mem_word,
.fast_read_mem_longword = wrapper_fast_read_mem_longword,
.write_mem_byte = wrapper_write_mem_byte,
.write_mem_word = wrapper_write_mem_word,
.write_mem_longword = wrapper_write_mem_longword,
.read_io_byte = wrapper_read_io_byte,
.read_io_word = wrapper_read_io_word,
.read_io_longword = wrapper_read_io_longword,
.fast_read_io_byte = wrapper_fast_read_io_byte,
.fast_read_io_word = wrapper_fast_read_io_word,
.fast_read_io_longword = wrapper_fast_read_io_longword,
.write_io_byte = wrapper_write_io_byte,
.write_io_word = wrapper_write_io_word,
.write_io_longword = wrapper_write_io_longword,
.get_machine_id = wrapper_get_machine_id,
.get_pagesize = wrapper_get_pagesize,
.virt_to_bus = wrapper_virt_to_bus,
.bus_to_virt = wrapper_bus_to_virt,
.virt_to_phys = wrapper_virt_to_phys,
.phys_to_virt = wrapper_phys_to_virt,
};
/*
* driver interface struct for the BaS framebuffer video driver
*/
static struct framebuffer_driver_interface framebuffer_interface =
{
.framebuffer_info = &info_fb
.framebuffer_info = &info_fb
};
static struct generic_interface interfaces[] =
{
{
/* BaS SD-card driver interface */
{
/* BaS SD-card driver interface */
.type = XHDI_DRIVER,
.name = "SDCARD",
.description = "BaS SD Card driver",
.version = 0,
.revision = 1,
.interface.xhdi = &xhdi_call_interface
},
{
.type = MCD_DRIVER,
.name = "MCDDMA",
.description = "BaS Multichannel DMA driver",
.version = 0,
.revision = 1,
.interface.dma = &dma_interface,
},
{
.type = VIDEO_DRIVER,
.name = "RADEON",
.description = "BaS RADEON framebuffer driver",
.version = 0,
.revision = 1,
.interface.fb = &framebuffer_interface,
},
.type = XHDI_DRIVER,
.name = "SDCARD",
.description = "BaS SD Card driver",
.version = 0,
.revision = 1,
.interface.xhdi = &xhdi_call_interface
},
{
.type = MCD_DRIVER,
.name = "MCDDMA",
.description = "BaS Multichannel DMA driver",
.version = 0,
.revision = 1,
.interface.dma = &dma_interface,
},
{
.type = VIDEO_DRIVER,
.name = "RADEON",
.description = "BaS RADEON framebuffer driver",
.version = 0,
.revision = 1,
.interface.fb = &framebuffer_interface,
},
{
.type = PCI_DRIVER,
.name = "PCI",
.description = "BaS PCI_BIOS driver",
.version = 0,
.revision = 1,
.interface.pci = &pci_interface,
},
{
.type = MMU_DRIVER,
.name = "MMU",
.description = "BaS MMU driver",
.version = 0,
.revision = 1,
.interface.mmu = NULL,
},
/* insert new drivers here */
/* insert new drivers here */
{
.type = END_OF_DRIVERS
}
{
.type = END_OF_DRIVERS
}
};
extern void remove_handler(void); /* forward declaration */
/*
* this is the driver table we expose to the OS
*/
static struct driver_table bas_drivers =
{
.bas_version = MAJOR_VERSION,
.bas_revision = MINOR_VERSION,
.remove_handler = NULL,
.interfaces = { interfaces }
.bas_version = MAJOR_VERSION,
.bas_revision = MINOR_VERSION,
.remove_handler = remove_handler,
.interfaces = interfaces
};
void remove_handler(void)
{
extern void std_exc_vec(void);
uint32_t *trap_0_vector = (uint32_t *) 0x80;
*trap_0_vector = (uint32_t) std_exc_vec;
}
void __attribute__((interrupt)) get_bas_drivers(void)
{
__asm__ __volatile__(
"move.l #%[drivers],d0\n\t"
: /* no output */
: [drivers] "o" (bas_drivers) /* input */
: /* clobber */
);
__asm__ __volatile(
/*
* sp should now point to the next instruction after the trap
* The trap itself is 2 bytes, the four bytes before that must
* read '_BAS' or we are not meant by this call
*/
" move.l a0,-(sp) \n\t" // save registers
" move.l d0,-(sp) \n\t"
" move.l 12(sp),a0 \n\t" // get return address
" move.l -6(a0),d0 \n\t" //
" cmp.l #0x5f424153,d0 \n\t" // is it '_BAS'?
" beq fetch_drivers \n\t" // yes
/*
* This seems indeed a "normal" trap #0. Better pass control to "normal" trap #0 processing
* If trap #0 isn't set to something sensible, we'll probably crash here, but this must be
* prevented on the caller side.
*/
" move.l (sp)+,d0 \n\t" // restore registers
" move.l (sp)+,a0 \n\t"
" move.l 0x80,-(sp) \n\t" // fetch vector
" rts \n\t" // and jump through it
"fetch_drivers: \n\t"
" move.l #%[drivers],d0 \n\t" // return driver struct in d0
" addq.l #4,sp \n\t" // adjust stack
" move.l (sp)+,a0 \n\t" // restore register
: /* no output */
: [drivers] "o" (bas_drivers) /* input */
: /* clobber */
);
}

181
include/driver_vec.h
View File

@@ -27,54 +27,57 @@
#include "xhdi_sd.h"
#include "MCD_dma.h"
#include "pci.h"
enum driver_type
{
END_OF_DRIVERS, /* marks end of driver list */
BLOCKDEV_DRIVER,
CHARDEV_DRIVER,
VIDEO_DRIVER,
XHDI_DRIVER,
MCD_DRIVER,
BLOCKDEV_DRIVER,
CHARDEV_DRIVER,
XHDI_DRIVER,
MCD_DRIVER,
VIDEO_DRIVER,
PCI_DRIVER,
MMU_DRIVER,
END_OF_DRIVERS = 0xffffffff /* marks end of driver list */
};
struct generic_driver_interface
{
uint32_t (*init)(void);
uint32_t (*read)(void *buf, size_t count);
uint32_t (*write)(const void *buf, size_t count);
uint32_t (*ioctl)(uint32_t request, ...);
uint32_t (*init)(void);
uint32_t (*read)(void *buf, size_t count);
uint32_t (*write)(const void *buf, size_t count);
uint32_t (*ioctl)(uint32_t request, ...);
};
struct dma_driver_interface
{
int32_t version;
int32_t magic;
int (*dma_set_initiator)(int initiator);
uint32_t (*dma_get_initiator)(int requestor);
void (*dma_free_initiator)(int requestor);
int (*dma_set_channel)(int requestor, void (*handler)(void));
int (*dma_get_channel)(int requestor);
void (*dma_free_channel)(int requestor);
void (*dma_clear_channel)(int channel);
int (*MCD_startDma)(long channel,
int8_t *srcAddr, unsigned int srcIncr, int8_t *destAddr, unsigned int destIncr,
unsigned int dmaSize, unsigned int xferSize, unsigned int initiator, int priority,
unsigned int flags, unsigned int funcDesc);
int32_t (*MCD_dmaStatus)(int32_t channel);
int32_t (*MCD_XferProgrQuery)(int32_t channel, MCD_XferProg *progRep);
int32_t (*MCD_killDma)(int32_t channel);
int32_t (*MCD_continDma)(int32_t channel);
int32_t (*MCD_pauseDma)(int32_t channel);
int32_t (*MCD_resumeDma)(int32_t channel);
int32_t (*MCD_csumQuery)(int32_t channel, uint32_t *csum);
void *(*dma_malloc)(uint32_t amount);
int32_t (*dma_free)(void *addr);
int32_t version;
int32_t magic;
int (*dma_set_initiator)(int initiator);
uint32_t (*dma_get_initiator)(int requestor);
void (*dma_free_initiator)(int requestor);
int (*dma_set_channel)(int requestor, void (*handler)(void));
int (*dma_get_channel)(int requestor);
void (*dma_free_channel)(int requestor);
void (*dma_clear_channel)(int channel);
int (*MCD_startDma)(long channel,
int8_t *srcAddr, unsigned int srcIncr, int8_t *destAddr, unsigned int destIncr,
unsigned int dmaSize, unsigned int xferSize, unsigned int initiator, int priority,
unsigned int flags, unsigned int funcDesc);
int32_t (*MCD_dmaStatus)(int32_t channel);
int32_t (*MCD_XferProgrQuery)(int32_t channel, MCD_XferProg *progRep);
int32_t (*MCD_killDma)(int32_t channel);
int32_t (*MCD_continDma)(int32_t channel);
int32_t (*MCD_pauseDma)(int32_t channel);
int32_t (*MCD_resumeDma)(int32_t channel);
int32_t (*MCD_csumQuery)(int32_t channel, uint32_t *csum);
void *(*dma_malloc)(uint32_t amount);
int32_t (*dma_free)(void *addr);
};
struct xhdi_driver_interface
{
uint32_t (*xhdivec)();
uint32_t (*xhdivec)();
};
/* Interpretation of offset for color fields: All offsets are from the right,
@@ -88,7 +91,7 @@ struct fb_bitfield
unsigned long offset; /* beginning of bitfield */
unsigned long length; /* length of bitfield */
unsigned long msb_right; /* != 0 : Most significant bit is */
/* right */
/* right */
};
/*
@@ -101,19 +104,19 @@ struct fb_var_screeninfo
unsigned long xres_virtual; /* virtual resolution */
unsigned long yres_virtual;
unsigned long xoffset; /* offset from virtual to visible */
unsigned long yoffset; /* resolution */
unsigned long yoffset; /* resolution */
unsigned long bits_per_pixel; /* guess what */
unsigned long bits_per_pixel; /* guess what */
unsigned long grayscale; /* != 0 Graylevels instead of colors */
struct fb_bitfield red; /* bitfield in fb mem if true color, */
struct fb_bitfield green; /* else only length is significant */
struct fb_bitfield blue;
struct fb_bitfield transp; /* transparency */
struct fb_bitfield transp; /* transparency */
unsigned long nonstd; /* != 0 Non standard pixel format */
unsigned long activate; /* see FB_ACTIVATE_* */
unsigned long activate; /* see FB_ACTIVATE_* */
unsigned long height; /* height of picture in mm */
unsigned long width; /* width of picture in mm */
@@ -128,7 +131,7 @@ struct fb_var_screeninfo
unsigned long lower_margin;
unsigned long hsync_len; /* length of horizontal sync */
unsigned long vsync_len; /* length of vertical sync */
unsigned long sync; /* see FB_SYNC_* */
unsigned long sync; /* see FB_SYNC_* */
unsigned long vmode; /* see FB_VMODE_* */
unsigned long rotate; /* angle we rotate counter clockwise */
unsigned long refresh;
@@ -141,7 +144,7 @@ struct fb_fix_screeninfo
unsigned long smem_start; /* Start of frame buffer mem */
/* (physical address) */
unsigned long smem_len; /* Length of frame buffer mem */
unsigned long type; /* see FB_TYPE_* */
unsigned long type; /* see FB_TYPE_* */
unsigned long type_aux; /* Interleave for interleaved Planes */
unsigned long visual; /* see FB_VISUAL_* */
unsigned short xpanstep; /* zero if no hardware panning */
@@ -158,7 +161,7 @@ struct fb_fix_screeninfo
struct fb_chroma
{
unsigned long redx; /* in fraction of 1024 */
unsigned long redx; /* in fraction of 1024 */
unsigned long greenx;
unsigned long bluex;
unsigned long whitex;
@@ -201,33 +204,97 @@ struct fb_monspecs
struct framebuffer_driver_interface
{
struct fb_info **framebuffer_info; /* pointer to an fb_info struct (defined in include/fb.h) */
struct fb_info **framebuffer_info; /* pointer to an fb_info struct (defined in include/fb.h) */
};
struct pci_bios_interface
{
uint32_t subjar;
uint32_t version;
/* Although we declare this functions as standard gcc functions (cdecl),
* they expect paramenters inside registers (fastcall) unsupported by gcc m68k.
* Caller will take care of parameters passing convention.
*/
int32_t (*find_pci_device) (uint32_t id, uint16_t index);
int32_t (*find_pci_classcode) (uint32_t class, uint16_t index);
int32_t (*read_config_byte) (int32_t handle, uint16_t reg, uint8_t *address);
int32_t (*read_config_word) (int32_t handle, uint16_t reg, uint16_t *address);
int32_t (*read_config_longword) (int32_t handle, uint16_t reg, uint32_t *address);
uint8_t (*fast_read_config_byte) (int32_t handle, uint16_t reg);
uint16_t (*fast_read_config_word) (int32_t handle, uint16_t reg);
uint32_t (*fast_read_config_longword) (int32_t handle, uint16_t reg);
int32_t (*write_config_byte) (int32_t handle, uint16_t reg, uint16_t val);
int32_t (*write_config_word) (int32_t handle, uint16_t reg, uint16_t val);
int32_t (*write_config_longword) (int32_t handle, uint16_t reg, uint32_t val);
int32_t (*hook_interrupt) (int32_t handle, uint32_t *routine, uint32_t *parameter);
int32_t (*unhook_interrupt) (int32_t handle);
int32_t (*special_cycle) (uint16_t bus, uint32_t data);
int32_t (*get_routing) (int32_t handle);
int32_t (*set_interrupt) (int32_t handle);
int32_t (*get_resource) (int32_t handle);
int32_t (*get_card_used) (int32_t handle, uint32_t *address);
int32_t (*set_card_used) (int32_t handle, uint32_t *callback);
int32_t (*read_mem_byte) (int32_t handle, uint32_t offset, uint8_t *address);
int32_t (*read_mem_word) (int32_t handle, uint32_t offset, uint16_t *address);
int32_t (*read_mem_longword) (int32_t handle, uint32_t offset, uint32_t *address);
uint8_t (*fast_read_mem_byte) (int32_t handle, uint32_t offset);
uint16_t (*fast_read_mem_word) (int32_t handle, uint32_t offset);
uint32_t (*fast_read_mem_longword) (int32_t handle, uint32_t offset);
int32_t (*write_mem_byte) (int32_t handle, uint32_t offset, uint16_t val);
int32_t (*write_mem_word) (int32_t handle, uint32_t offset, uint16_t val);
int32_t (*write_mem_longword) (int32_t handle, uint32_t offset, uint32_t val);
int32_t (*read_io_byte) (int32_t handle, uint32_t offset, uint8_t *address);
int32_t (*read_io_word) (int32_t handle, uint32_t offset, uint16_t *address);
int32_t (*read_io_longword) (int32_t handle, uint32_t offset, uint32_t *address);
uint8_t (*fast_read_io_byte) (int32_t handle, uint32_t offset);
uint16_t (*fast_read_io_word) (int32_t handle, uint32_t offset);
uint32_t (*fast_read_io_longword) (int32_t handle, uint32_t offset);
int32_t (*write_io_byte) (int32_t handle, uint32_t offset, uint16_t val);
int32_t (*write_io_word) (int32_t handle, uint32_t offset, uint16_t val);
int32_t (*write_io_longword) (int32_t handle, uint32_t offset, uint32_t val);
int32_t (*get_machine_id) (void);
int32_t (*get_pagesize) (void);
int32_t (*virt_to_bus) (int32_t handle, uint32_t address, PCI_CONV_ADR *pointer);
int32_t (*bus_to_virt) (int32_t handle, uint32_t address, PCI_CONV_ADR *pointer);
int32_t (*virt_to_phys) (uint32_t address, PCI_CONV_ADR *pointer);
int32_t (*phys_to_virt) (uint32_t address, PCI_CONV_ADR *pointer);
// int32_t reserved[2];
};
struct mmu_driver_interface
{
int32_t (*map_page_locked)(uint32_t address, uint32_t length, int asid);
int32_t (*unlock_page)(uint32_t address, uint32_t length, int asid);
int32_t (*report_locked_pages)(uint32_t *num_itlb, uint32_t *num_dtlb);
uint32_t (*report_pagesize)(void);
};
union interface
{
struct generic_driver_interface *gdi;
struct xhdi_driver_interface *xhdi;
struct dma_driver_interface *dma;
struct framebuffer_driver_interface *fb;
struct generic_driver_interface *gdi;
struct xhdi_driver_interface *xhdi;
struct dma_driver_interface *dma;
struct framebuffer_driver_interface *fb;
struct pci_bios_interface *pci;
struct mmu_driver_interface *mmu;
};
struct generic_interface
{
enum driver_type type;
char name[16];
char description[64];
int version;
int revision;
union interface interface;
enum driver_type type;
char name[16];
char description[64];
int version;
int revision;
union interface interface;
};
struct driver_table
{
uint32_t bas_version;
uint32_t bas_revision;
uint32_t (*remove_handler)(); /* calling this will disable the BaS' hook into trap #0 */
struct generic_interface *interfaces[];
uint32_t bas_version;
uint32_t bas_revision;
void (*remove_handler)(void); /* calling this will disable the BaS' hook into trap #0 */
struct generic_interface *interfaces;
};

98
include/font.h Normal file
View File

@@ -0,0 +1,98 @@
/*
* font.h - font specific definitions
*
* Copyright (c) 2001 Lineo, Inc.
* Copyright (c) 2004 by Authors:
*
* Authors:
* MAD Martin Doering
*
* This file is distributed under the GPL, version 2 or at your
* option any later version. See doc/license.txt for details.
*/
#ifndef FONT_H
#define FONT_H
#include <stdint.h>
/* font header flags */
#define F_DEFAULT 1 /* this is the default font (face and size) */
#define F_HORZ_OFF 2 /* there are left and right offset tables */
#define F_STDFORM 4 /* is the font in standard format */
#define F_MONOSPACE 8 /* is the font monospaced */
/* font style bits */
#define F_THICKEN 1
#define F_LIGHT 2
#define F_SKEW 4
#define F_UNDER 8
#define F_OUTLINE 16
#define F_SHADOW 32
/* font specific linea variables */
extern const uint16_t *v_fnt_ad; /* address of current monospace font */
extern const uint16_t *v_off_ad; /* address of font offset table */
extern uint16_t v_fnt_nd; /* ascii code of last cell in font */
extern uint16_t v_fnt_st; /* ascii code of first cell in font */
extern uint16_t v_fnt_wr; /* font cell wrap */
/* character cell specific linea variables */
extern uint16_t v_cel_ht; /* cell height (width is 8) */
extern uint16_t v_cel_mx; /* needed by MiNT: columns on the screen minus 1 */
extern uint16_t v_cel_my; /* needed by MiNT: rows on the screen minus 1 */
extern uint16_t v_cel_wr; /* needed by MiNT: length (in int8_ts) of a line of characters */
/*
* font_ring is a struct of four pointers, each of which points to
* a list of font headers linked together to form a string.
*/
extern struct font_head *font_ring[4]; /* Ring of available fonts */
extern int16_t font_count; /* all three fonts and NULL */
/* the font header descibes a font */
struct font_head {
int16_t font_id;
int16_t point;
int8_t name[32];
uint16_t first_ade;
uint16_t last_ade;
uint16_t top;
uint16_t ascent;
uint16_t half;
uint16_t descent;
uint16_t bottom;
uint16_t max_char_width;
uint16_t max_cell_width;
uint16_t left_offset; /* amount character slants left when skewed */
uint16_t right_offset; /* amount character slants right */
uint16_t thicken; /* number of pixels to smear */
uint16_t ul_size; /* size of the underline */
uint16_t lighten; /* mask to and with to lighten */
uint16_t skew; /* mask for skewing */
uint16_t flags;
const uint8_t *hor_table; /* horizontal offsets */
const uint16_t *off_table; /* character offsets */
const uint16_t *dat_table; /* character definitions */
uint16_t form_width;
uint16_t form_height;
struct font_head *next_font;/* pointer to next font */
uint16_t font_seg;
};
/* prototypes */
void font_init(void); /* initialize BIOS font ring */
void font_set_default(void); /* choose the default font */
#endif /* FONT_H */

86
include/pci.h
View File

@@ -243,10 +243,94 @@ extern int32_t pci_write_config_longword(int32_t handle, int offset, uint32_t va
extern int32_t pci_write_config_word(int32_t handle, int offset, uint16_t value);
extern int32_t pci_write_config_byte(int32_t handle, int offset, uint8_t value);
extern struct pci_rd *pci_get_resource(int32_t handle);
extern int32_t pci_hook_interrupt(int32_t handle, void *interrupt_handler, void *parameter);
extern int32_t pci_unhook_interrupt(int32_t handle);
extern struct pci_rd *pci_get_resource(int32_t handle);
/*
* Not implemented PCI_BIOS functions
*/
extern uint8_t pci_fast_read_config_byte(int32_t handle, uint16_t reg);
extern uint16_t pci_fast_read_config_word(int32_t handle, uint16_t reg);
extern uint32_t pci_fast_read_config_longword(int32_t handle, uint16_t reg);
extern int32_t pci_special_cycle(uint16_t bus, uint32_t data);
extern int32_t pci_get_routing(int32_t handle);
extern int32_t pci_set_interrupt(int32_t handle);
extern int32_t pci_get_card_used(int32_t handle, uint32_t *address);
extern int32_t pci_set_card_used(int32_t handle, uint32_t *callback);
extern int32_t pci_read_mem_byte(int32_t handle, uint32_t offset, uint8_t *address);
extern int32_t pci_read_mem_word(int32_t handle, uint32_t offset, uint16_t *address);
extern int32_t pci_read_mem_longword(int32_t handle, uint32_t offset, uint32_t *address);
extern uint8_t pci_fast_read_mem_byte(int32_t handle, uint32_t offset);
extern uint16_t pci_fast_read_mem_word(int32_t handle, uint32_t offset);
extern uint32_t pci_fast_read_mem_longword(int32_t handle, uint32_t offset);
extern int32_t pci_write_mem_byte(int32_t handle, uint32_t offset, uint16_t val);
extern int32_t pci_write_mem_word(int32_t handle, uint32_t offset, uint16_t val);
extern int32_t pci_write_mem_longword(int32_t handle, uint32_t offset, uint32_t val);
extern int32_t pci_read_io_byte(int32_t handle, uint32_t offset, uint8_t *address);
extern int32_t pci_read_io_word(int32_t handle, uint32_t offset, uint16_t *address);
extern int32_t pci_read_io_longword(int32_t handle, uint32_t offset, uint32_t *address);
extern uint8_t pci_fast_read_io_byte(int32_t handle, uint32_t offset);
extern uint16_t pci_fast_read_io_word(int32_t handle, uint32_t offset);
extern uint32_t pci_fast_read_io_longword(int32_t handle, uint32_t offset);
extern int32_t pci_write_io_byte(int32_t handle, uint32_t offset, uint16_t val);
extern int32_t pci_write_io_word(int32_t handle, uint32_t offset, uint16_t val);
extern int32_t pci_write_io_longword(int32_t handle, uint32_t offset, uint32_t val);
extern int32_t pci_get_machine_id(void);
extern int32_t pci_get_pagesize(void);
extern int32_t pci_virt_to_bus(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer);
extern int32_t pci_bus_to_virt(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer);
extern int32_t pci_virt_to_phys(uint32_t address, PCI_CONV_ADR *pointer);
extern int32_t pci_phys_to_virt(uint32_t address, PCI_CONV_ADR *pointer);
/*
* prototypes for PCI wrapper routines
*/
extern int32_t wrapper_find_pci_device(uint32_t id, uint16_t index);
extern int32_t wrapper_find_pci_classcode(uint32_t class, uint16_t index);
extern int32_t wrapper_read_config_byte(int32_t handle, uint16_t reg, uint8_t *address);
extern int32_t wrapper_read_config_word(int32_t handle, uint16_t reg, uint16_t *address);
extern int32_t wrapper_read_config_longword(int32_t handle, uint16_t reg, uint32_t *address);
extern uint8_t wrapper_fast_read_config_byte(int32_t handle, uint16_t reg);
extern uint16_t wrapper_fast_read_config_word(int32_t handle, uint16_t reg);
extern uint32_t wrapper_fast_read_config_longword(int32_t handle, uint16_t reg);
extern int32_t wrapper_write_config_byte(int32_t handle, uint16_t reg, uint16_t val);
extern int32_t wrapper_write_config_word(int32_t handle, uint16_t reg, uint16_t val);
extern int32_t wrapper_write_config_longword(int32_t handle, uint16_t reg, uint32_t val);
extern int32_t wrapper_hook_interrupt(int32_t handle, uint32_t *routine, uint32_t *parameter);
extern int32_t wrapper_unhook_interrupt(int32_t handle);
extern int32_t wrapper_special_cycle(uint16_t bus, uint32_t data);
extern int32_t wrapper_get_routing(int32_t handle);
extern int32_t wrapper_set_interrupt(int32_t handle);
extern int32_t wrapper_get_resource(int32_t handle);
extern int32_t wrapper_get_card_used(int32_t handle, uint32_t *address);
extern int32_t wrapper_set_card_used(int32_t handle, uint32_t *callback);
extern int32_t wrapper_read_mem_byte(int32_t handle, uint32_t offset, uint8_t *address);
extern int32_t wrapper_read_mem_word(int32_t handle, uint32_t offset, uint16_t *address);
extern int32_t wrapper_read_mem_longword(int32_t handle, uint32_t offset, uint32_t *address);
extern uint8_t wrapper_fast_read_mem_byte(int32_t handle, uint32_t offset);
extern uint16_t wrapper_fast_read_mem_word(int32_t handle, uint32_t offset);
extern uint32_t wrapper_fast_read_mem_longword(int32_t handle, uint32_t offset);
extern int32_t wrapper_write_mem_byte(int32_t handle, uint32_t offset, uint16_t val);
extern int32_t wrapper_write_mem_word(int32_t handle, uint32_t offset, uint16_t val);
extern int32_t wrapper_write_mem_longword(int32_t handle, uint32_t offset, uint32_t val);
extern int32_t wrapper_read_io_byte(int32_t handle, uint32_t offset, uint8_t *address);
extern int32_t wrapper_read_io_word(int32_t handle, uint32_t offset, uint16_t *address);
extern int32_t wrapper_read_io_longword(int32_t handle, uint32_t offset, uint32_t *address);
extern uint8_t wrapper_fast_read_io_byte(int32_t handle, uint32_t offset);
extern uint16_t wrapper_fast_read_io_word(int32_t handle, uint32_t offset);
extern uint32_t wrapper_fast_read_io_longword(int32_t handle, uint32_t offset);
extern int32_t wrapper_write_io_byte(int32_t handle, uint32_t offset, uint16_t val);
extern int32_t wrapper_write_io_word(int32_t handle, uint32_t offset, uint16_t val);
extern int32_t wrapper_write_io_longword(int32_t handle, uint32_t offset, uint32_t val);
extern int32_t wrapper_get_machine_id(void);
extern int32_t wrapper_get_pagesize(void);
extern int32_t wrapper_virt_to_bus(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer);
extern int32_t wrapper_bus_to_virt(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer);
extern int32_t wrapper_virt_to_phys(uint32_t address, PCI_CONV_ADR *pointer);
extern int32_t wrapper_phys_to_virt(uint32_t address, PCI_CONV_ADR *pointer);
#define PCI_MK_CONF_ADDR(bus, device, function) (MCF_PCI_PCICAR_E | \
((bus) << 16) | \
((device << 8) | \

2
include/version.h
View File

@@ -29,7 +29,7 @@
*/
#define MAJOR_VERSION 0
#define MINOR_VERSION 85
#define MINOR_VERSION 86
#endif /* VERSION_H_ */

215
net/fec.c
View File

@@ -32,7 +32,7 @@
#error Unknown machine!
#endif
#define DBG_FEC
// #define DBG_FEC
#ifdef DBG_FEC
#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
#else
@@ -237,33 +237,33 @@ void fec_log_init(uint8_t ch)
*/
void fec_log_dump(uint8_t ch)
{
dbg("\r\n FEC%d Log\r\n", __FUNCTION__, ch);
dbg(" ---------------\r\n", __FUNCTION__);
dbg(" Total: %4d\r\n", fec_log[ch].total);
dbg(" hberr: %4d\r\n", fec_log[ch].hberr);
dbg(" babr: %4d\r\n", fec_log[ch].babr);
dbg(" babt: %4d\r\n", fec_log[ch].babt);
dbg(" gra: %4d\r\n", fec_log[ch].gra);
dbg(" txf: %4d\r\n", fec_log[ch].txf);
dbg(" mii: %4d\r\n", fec_log[ch].mii);
dbg(" lc: %4d\r\n", fec_log[ch].lc);
dbg(" rl: %4d\r\n", fec_log[ch].rl);
dbg(" xfun: %4d\r\n", fec_log[ch].xfun);
dbg(" xferr: %4d\r\n", fec_log[ch].xferr);
dbg(" rferr: %4d\r\n", fec_log[ch].rferr);
dbg(" dtxf: %4d\r\n", fec_log[ch].dtxf);
dbg(" drxf: %4d\r\n", fec_log[ch].drxf);
dbg(" \r\nRFSW:\r\n");
dbg(" inv: %4d\r\n", fec_log[ch].rfsw_inv);
dbg(" m: %4d\r\n", fec_log[ch].rfsw_m);
dbg(" bc: %4d\r\n", fec_log[ch].rfsw_bc);
dbg(" mc: %4d\r\n", fec_log[ch].rfsw_mc);
dbg(" lg: %4d\r\n", fec_log[ch].rfsw_lg);
dbg(" no: %4d\r\n", fec_log[ch].rfsw_no);
dbg(" cr: %4d\r\n", fec_log[ch].rfsw_cr);
dbg(" ov: %4d\r\n", fec_log[ch].rfsw_ov);
dbg(" tr: %4d\r\n", fec_log[ch].rfsw_tr);
dbg(" ---------------\r\n\r\n");
dbg("\r\n FEC%d Log\r\n", __FUNCTION__, ch);
dbg(" ---------------\r\n", __FUNCTION__);
dbg(" Total: %4d\r\n", fec_log[ch].total);
dbg(" hberr: %4d\r\n", fec_log[ch].hberr);
dbg(" babr: %4d\r\n", fec_log[ch].babr);
dbg(" babt: %4d\r\n", fec_log[ch].babt);
dbg(" gra: %4d\r\n", fec_log[ch].gra);
dbg(" txf: %4d\r\n", fec_log[ch].txf);
dbg(" mii: %4d\r\n", fec_log[ch].mii);
dbg(" lc: %4d\r\n", fec_log[ch].lc);
dbg(" rl: %4d\r\n", fec_log[ch].rl);
dbg(" xfun: %4d\r\n", fec_log[ch].xfun);
dbg(" xferr: %4d\r\n", fec_log[ch].xferr);
dbg(" rferr: %4d\r\n", fec_log[ch].rferr);
dbg(" dtxf: %4d\r\n", fec_log[ch].dtxf);
dbg(" drxf: %4d\r\n", fec_log[ch].drxf);
dbg(" \r\nRFSW:\r\n");
dbg(" inv: %4d\r\n", fec_log[ch].rfsw_inv);
dbg(" m: %4d\r\n", fec_log[ch].rfsw_m);
dbg(" bc: %4d\r\n", fec_log[ch].rfsw_bc);
dbg(" mc: %4d\r\n", fec_log[ch].rfsw_mc);
dbg(" lg: %4d\r\n", fec_log[ch].rfsw_lg);
dbg(" no: %4d\r\n", fec_log[ch].rfsw_no);
dbg(" cr: %4d\r\n", fec_log[ch].rfsw_cr);
dbg(" ov: %4d\r\n", fec_log[ch].rfsw_ov);
dbg(" tr: %4d\r\n", fec_log[ch].rfsw_tr);
dbg(" ---------------\r\n\r\n");
}
/*
@@ -538,19 +538,26 @@ void fec_rx_start(uint8_t ch, int8_t *rxbd)
{
uint32_t initiator;
int channel;
#ifdef DBG_FEC
int res;
#endif
/*
* Make the initiator assignment
*/
res = dma_set_initiator(DMA_FEC_RX(ch));
dbg("dma_set_initiator(DMA_FEC_RX(%d)): %d\r\n", ch, res);
#if defined(DBG_FEC)
res =
#else
(void)
#endif
dma_set_initiator(DMA_FEC_RX(ch));
dbg("dma_set_initiator(DMA_FEC_RX(%d)): %d\r\n", ch, res);
/*
* Grab the initiator number
*/
initiator = dma_get_initiator(DMA_FEC_RX(ch));
dbg("dma_get_initiator(DMA_FEC_RX(%d)) = %d\r\n", ch, initiator);
dbg("dma_get_initiator(DMA_FEC_RX(%d)) = %d\r\n", ch, initiator);
/*
* Determine the DMA channel running the task for the
@@ -558,7 +565,7 @@ void fec_rx_start(uint8_t ch, int8_t *rxbd)
*/
channel = dma_set_channel(DMA_FEC_RX(ch),
(ch == 0) ? fec0_rx_frame : fec1_rx_frame);
dbg("DMA channel for FEC%1d: %d\r\n", ch, channel);
dbg("DMA channel for FEC%1d: %d\r\n", ch, channel);
/*
* Start the Rx DMA task
@@ -572,18 +579,18 @@ void fec_rx_start(uint8_t ch, int8_t *rxbd)
0,
initiator,
FECRX_DMA_PRI(ch),
0
| MCD_FECRX_DMA
0
| MCD_FECRX_DMA
| MCD_INTERRUPT
| MCD_TT_FLAGS_CW
| MCD_TT_FLAGS_CW
| MCD_TT_FLAGS_RL
| MCD_TT_FLAGS_SP
,
0
0
| MCD_NO_CSUM
| MCD_NO_BYTE_SWAP
);
dbg("Rx DMA task for FEC%1d started\r\n", ch);
dbg("Rx DMA task for FEC%1d started\r\n", ch);
}
/*
@@ -607,13 +614,13 @@ void fec_rx_continue(uint8_t ch)
*/
channel = dma_get_channel(DMA_FEC_RX(ch));
dbg("RX DMA channel for FEC%1d is %d\r\n", ch, channel);
dbg("RX DMA channel for FEC%1d is %d\r\n", ch, channel);
/*
* Continue/restart the DMA task
*/
MCD_continDma(channel);
dbg("RX dma on channel %d continued\r\n", channel);
dbg("RX dma on channel %d continued\r\n", channel);
}
/*
@@ -642,9 +649,9 @@ void fec_rx_stop (uint8_t ch)
/* Kill the FEC Rx DMA task */
MCD_killDma(channel);
/*
* Free up the FEC requestor from the software maintained
* initiator list
/*
* Free up the FEC requestor from the software maintained
* initiator list
*/
dma_free_initiator(DMA_FEC_RX(ch));
@@ -656,7 +663,7 @@ void fec_rx_stop (uint8_t ch)
}
/*
* Receive Frame interrupt handler - this handler is called by the
* Receive Frame interrupt handler - this handler is called by the
* DMA interrupt handler indicating that a packet was successfully
* transferred out of the Rx FIFO.
*
@@ -671,7 +678,7 @@ void fec_rx_frame(uint8_t ch, NIF *nif)
NBUF *cur_nbuf, *new_nbuf;
int keep;
dbg("started\r\n");
dbg("started\r\n");
while ((pRxBD = fecbd_rx_alloc(ch)) != NULL)
{
@@ -684,7 +691,7 @@ void fec_rx_frame(uint8_t ch, NIF *nif)
* - No undefined bits should be set
* - The upper 5 bits of the length should be cleared
*/
if (!(pRxBD->status & RX_BD_L) || (pRxBD->status & 0x0608)
if (!(pRxBD->status & RX_BD_L) || (pRxBD->status & 0x0608)
|| (pRxBD->length & 0xF800))
{
keep = false;
@@ -716,8 +723,8 @@ void fec_rx_frame(uint8_t ch, NIF *nif)
if (keep)
{
/*
* Pull the network buffer off the Rx ring queue
/*
* Pull the network buffer off the Rx ring queue
*/
cur_nbuf = nbuf_remove(NBUF_RX_RING);
@@ -733,7 +740,7 @@ void fec_rx_frame(uint8_t ch, NIF *nif)
new_nbuf = nbuf_alloc();
if (new_nbuf == NULL)
{
dbg("nbuf_alloc() failed\n");
dbg("nbuf_alloc() failed\n");
/*
* Can't allocate a new network buffer, so we
@@ -767,7 +774,7 @@ void fec_rx_frame(uint8_t ch, NIF *nif)
/*
* Let the DMA know that there is a new Rx BD (in case the
* Let the DMA know that there is a new Rx BD (in case the
* ring was full and the DMA was waiting for an empty one)
*/
fec_rx_continue(ch);
@@ -778,7 +785,7 @@ void fec_rx_frame(uint8_t ch, NIF *nif)
eth_hdr = (ETH_HDR *) cur_nbuf->data;
/*
* Pass the received packet up the network stack if the
* Pass the received packet up the network stack if the
* protocol is supported in our network interface (NIF)
*/
if (nif_protocol_exist(nif, eth_hdr->type))
@@ -789,12 +796,12 @@ void fec_rx_frame(uint8_t ch, NIF *nif)
else
{
nbuf_free(cur_nbuf);
dbg("got unsupported packet %d, trashed it\r\n", eth_hdr->type);
dbg("got unsupported packet %d, trashed it\r\n", eth_hdr->type);
}
}
else
else
{
/*
/*
* This frame isn't a keeper
* Reset the status and length, but don't need to get another
* buffer since we are trashing the data in the current one
@@ -804,7 +811,7 @@ void fec_rx_frame(uint8_t ch, NIF *nif)
pRxBD->status |= RX_BD_E;
/*
* Move the current buffer from the beginning to the end of the
* Move the current buffer from the beginning to the end of the
* Rx ring queue
*/
cur_nbuf = nbuf_remove(NBUF_RX_RING);
@@ -844,22 +851,28 @@ void fec_tx_start(uint8_t ch, int8_t *txbd)
{
uint32_t initiator;
int channel;
int result;
void fec0_tx_frame(void);
void fec1_tx_frame(void);
#ifdef DBG_FEC
int res;
#endif
/*
* Make the initiator assignment
*/
res = dma_set_initiator(DMA_FEC_TX(ch));
dbg("dma_set_initiator(%d) = %d\r\n", ch, res);
#ifdef DBG_FEC
res =
#else
(void)
#endif
dma_set_initiator(DMA_FEC_TX(ch));
dbg("dma_set_initiator(%d) = %d\r\n", ch, res);
/*
* Grab the initiator number
*/
initiator = dma_get_initiator(DMA_FEC_TX(ch));
dbg("dma_get_initiator(%d) = %d\r\n", ch, initiator);
dbg("dma_get_initiator(%d) = %d\r\n", ch, initiator);
/*
@@ -868,7 +881,7 @@ void fec_tx_start(uint8_t ch, int8_t *txbd)
*/
channel = dma_set_channel(DMA_FEC_TX(ch),
(ch == 0) ? fec0_tx_frame : fec1_tx_frame);
dbg("dma_set_channel(%d, ...) = %d\r\n", ch, channel);
dbg("dma_set_channel(%d, ...) = %d\r\n", ch, channel);
/*
* Start the Tx DMA task
@@ -882,18 +895,18 @@ void fec_tx_start(uint8_t ch, int8_t *txbd)
0,
initiator,
FECTX_DMA_PRI(ch),
0
| MCD_FECTX_DMA
0
| MCD_FECTX_DMA
| MCD_INTERRUPT
| MCD_TT_FLAGS_CW
| MCD_TT_FLAGS_CW
| MCD_TT_FLAGS_RL
| MCD_TT_FLAGS_SP
,
0
0
| MCD_NO_CSUM
| MCD_NO_BYTE_SWAP
);
dbg("DMA tx task started\r\n");
dbg("DMA tx task started\r\n");
}
/*
@@ -916,13 +929,13 @@ void fec_tx_continue(uint8_t ch)
* selected FEC
*/
channel = dma_get_channel(DMA_FEC_TX(ch));
dbg("dma_get_channel(DMA_FEC_TX(%d)) = %d\r\n", ch, channel);
dbg("dma_get_channel(DMA_FEC_TX(%d)) = %d\r\n", ch, channel);
/*
* Continue/restart the DMA task
*/
MCD_continDma(channel);
dbg("DMA TX task continue\r\n");
dbg("DMA TX task continue\r\n");
}
/*
@@ -969,9 +982,9 @@ void fec_tx_stop(uint8_t ch)
/* Kill the FEC Tx DMA task */
MCD_killDma(channel);
/*
* Free up the FEC requestor from the software maintained
* initiator list
/*
* Free up the FEC requestor from the software maintained
* initiator list
*/
dma_free_initiator(DMA_FEC_TX(ch));
@@ -983,7 +996,7 @@ void fec_tx_stop(uint8_t ch)
}
/*
* Trasmit Frame interrupt handler - this handler is called by the
* Trasmit Frame interrupt handler - this handler is called by the
* DMA interrupt handler indicating that a packet was successfully
* transferred to the Tx FIFO.
*
@@ -996,7 +1009,7 @@ void fec_tx_frame(uint8_t ch)
NBUF *pNbuf;
bool is_empty = true;
dbg("\r\n");
dbg("\r\n");
while ((pTxBD = fecbd_tx_free(ch)) != NULL)
{
fec_log[ch].dtxf++;
@@ -1010,7 +1023,7 @@ void fec_tx_frame(uint8_t ch)
* Free up the network buffer that was just transmitted
*/
nbuf_free(pNbuf);
dbg("free buffer %p from TX ring\r\n", pNbuf);
dbg("free buffer %p from TX ring\r\n", pNbuf);
/*
* Re-initialize the Tx BD
@@ -1019,9 +1032,9 @@ void fec_tx_frame(uint8_t ch)
pTxBD->length = 0;
is_empty = false;
}
}
if (is_empty)
dbg("transmit queue was empty!\r\n");
dbg("transmit queue was empty!\r\n");
}
void fec0_tx_frame(void)
@@ -1044,7 +1057,7 @@ void fec1_tx_frame(void)
* dst Destination MAC Address
* src Source MAC Address
* type Ethernet Frame Type
* length Number of bytes to be transmitted (doesn't include type,
* length Number of bytes to be transmitted (doesn't include type,
* src, or dest byte count)
* pkt Pointer packet network buffer
*
@@ -1059,14 +1072,14 @@ int fec_send(uint8_t ch, NIF *nif, uint8_t *dst, uint8_t *src, uint16_t type, NB
/* Check the length */
if ((nbuf->length + ETH_HDR_LEN) > ETH_MTU)
{
dbg("nbuf->length (%d) + ETH_HDR_LEN (%d) exceeds ETH_MTU (%d)\r\n",
nbuf->length, ETH_HDR_LEN, ETH_MTU);
dbg("nbuf->length (%d) + ETH_HDR_LEN (%d) exceeds ETH_MTU (%d)\r\n",
nbuf->length, ETH_HDR_LEN, ETH_MTU);
return 0;
}
/*
* Copy the destination address, source address, and Ethernet
* type into the packet
/*
* Copy the destination address, source address, and Ethernet
* type into the packet
*/
memcpy(&nbuf->data[0], dst, 6);
memcpy(&nbuf->data[6], src, 6);
@@ -1082,7 +1095,7 @@ int fec_send(uint8_t ch, NIF *nif, uint8_t *dst, uint8_t *src, uint16_t type, NB
*/
nbuf_add(NBUF_TX_RING, nbuf);
/*
/*
* Setup the buffer descriptor for transmission
*/
pTxBD->data = nbuf->data;
@@ -1192,7 +1205,7 @@ static void fec_irq_handler(uint8_t ch)
event = eir & MCF_FEC_EIMR(ch);
if (event != eir)
dbg("pending but not enabled: 0x%08x\r\n", (event ^ eir));
dbg("pending but not enabled: 0x%08x\r\n", (event ^ eir));
/*
* Clear the event(s) in the EIR immediately
@@ -1203,8 +1216,8 @@ static void fec_irq_handler(uint8_t ch)
{
fec_log[ch].total++;
fec_log[ch].rferr++;
dbg("RFERR\r\n");
dbg("FECRFSR%d = 0x%08x\r\n", ch, MCF_FEC_FECRFSR(ch));
dbg("RFERR\r\n");
dbg("FECRFSR%d = 0x%08x\r\n", ch, MCF_FEC_FECRFSR(ch));
//fec_eth_stop(ch);
}
@@ -1212,14 +1225,14 @@ static void fec_irq_handler(uint8_t ch)
{
fec_log[ch].total++;
fec_log[ch].xferr++;
dbg("XFERR\r\n");
dbg("XFERR\r\n");
}
if (event & MCF_FEC_EIR_XFUN)
{
fec_log[ch].total++;
fec_log[ch].xfun++;
dbg("XFUN\r\n");
dbg("XFUN\r\n");
//fec_eth_stop(ch);
}
@@ -1227,54 +1240,54 @@ static void fec_irq_handler(uint8_t ch)
{
fec_log[ch].total++;
fec_log[ch].rl++;
dbg("RL\r\n");
dbg("RL\r\n");
}
if (event & MCF_FEC_EIR_LC)
{
fec_log[ch].total++;
fec_log[ch].lc++;
dbg("LC\r\n");
dbg("LC\r\n");
}
if (event & MCF_FEC_EIR_MII)
{
fec_log[ch].mii++;
dbg("MII\r\n");
dbg("MII\r\n");
}
if (event & MCF_FEC_EIR_TXF)
{
fec_log[ch].txf++;
dbg("TXF\r\n");
dbg("TXF\r\n");
fec_log_dump(0);
}
if (event & MCF_FEC_EIR_GRA)
{
fec_log[ch].gra++;
dbg("GRA\r\n");
dbg("GRA\r\n");
}
if (event & MCF_FEC_EIR_BABT)
{
fec_log[ch].total++;
fec_log[ch].babt++;
dbg("BABT\r\n");
dbg("BABT\r\n");
}
if (event & MCF_FEC_EIR_BABR)
{
fec_log[ch].total++;
fec_log[ch].babr++;
dbg("BABR\r\n");
dbg("BABR\r\n");
}
if (event & MCF_FEC_EIR_HBERR)
{
fec_log[ch].total++;
fec_log[ch].hberr++;
dbg("HBERR\r\n");
dbg("HBERR\r\n");
}
}
@@ -1284,7 +1297,7 @@ static void fec_irq_handler(uint8_t ch)
*/
int fec0_interrupt_handler(void* arg1, void* arg2)
{
(void) arg1;
(void) arg1; /* not used */
(void) arg2;
fec_irq_handler(0);
@@ -1294,7 +1307,7 @@ int fec0_interrupt_handler(void* arg1, void* arg2)
int fec1_interrupt_handler(void* arg1, void* arg2)
{
(void) arg1;
(void) arg1; /* not used */
(void) arg2;
fec_irq_handler(1);
@@ -1344,9 +1357,9 @@ void fec_eth_setup(uint8_t ch, uint8_t trcvr, uint8_t speed, uint8_t duplex, con
*/
#if defined(MACHINE_FIREBEE)
if (am79c874_init(0, 0, speed, duplex))
dbg("PHY init completed\r\n");
dbg("PHY init completed\r\n");
else
dbg("PHY init failed\r\n");
dbg("PHY init failed\r\n");
#elif defined(MACHINE_M548X)
bcm_5222_init(0, 0, speed, duplex);
#else
@@ -1399,7 +1412,7 @@ void fec_eth_stop(uint8_t ch)
*/
level = set_ipl(7);
dbg("fec %d stopped\r\n", ch);
dbg("fec %d stopped\r\n", ch);
/*
* Gracefully disable the receiver and transmitter
*/
@@ -1421,12 +1434,12 @@ void fec_eth_stop(uint8_t ch)
fec_log_dump(ch);
#endif
/*
/*
* Flush the network buffers
*/
nbuf_flush();
/*
/*
* Restore interrupt level
*/
set_ipl(level);

194
net/fecbd.c
View File

@@ -11,7 +11,7 @@
#include "bas_printf.h"
#include <stddef.h>
#define DBG_FECBD
//#define DBG_FECBD
#ifdef DBG_FECBD
#define dbg(format, arg...) do { xprintf("DEBUG: " format, ##arg); } while (0)
#else
@@ -62,94 +62,94 @@ static int iRxbd;
*/
void fecbd_init(uint8_t ch)
{
NBUF *nbuf;
int i;
NBUF *nbuf;
int i;
dbg("\r\n");
/*
* Align Buffer Descriptors to 4-byte boundary
*/
RxBD = (FECBD *)(((int) unaligned_bds + 3) & 0xFFFFFFFC);
TxBD = (FECBD *)((int) RxBD + (sizeof(FECBD) * 2 * NRXBD));
/*
* Align Buffer Descriptors to 4-byte boundary
*/
RxBD = (FECBD *)(((int) unaligned_bds + 3) & 0xFFFFFFFC);
TxBD = (FECBD *)((int) RxBD + (sizeof(FECBD) * 2 * NRXBD));
dbg("initialise RX buffer descriptor ring\r\n");
/*
* Initialize the Rx Buffer Descriptor ring
*/
for (i = 0; i < NRXBD; ++i)
{
/* Grab a network buffer from the free list */
nbuf = nbuf_alloc();
if (nbuf == NULL)
{
/*
* Initialize the Rx Buffer Descriptor ring
*/
for (i = 0; i < NRXBD; ++i)
{
/* Grab a network buffer from the free list */
nbuf = nbuf_alloc();
if (nbuf == NULL)
{
dbg("could not allocate network buffer\r\n");
return;
}
return;
}
/* Initialize the BD */
RxBD(ch,i).status = RX_BD_E | RX_BD_INTERRUPT;
RxBD(ch,i).length = RX_BUF_SZ;
RxBD(ch,i).data = nbuf->data;
/* Initialize the BD */
RxBD(ch,i).status = RX_BD_E | RX_BD_INTERRUPT;
RxBD(ch,i).length = RX_BUF_SZ;
RxBD(ch,i).data = nbuf->data;
/* Add the network buffer to the Rx queue */
nbuf_add(NBUF_RX_RING, nbuf);
}
/* Add the network buffer to the Rx queue */
nbuf_add(NBUF_RX_RING, nbuf);
}
/*
* Set the WRAP bit on the last one
*/
RxBD(ch, i - 1).status |= RX_BD_W;
/*
* Set the WRAP bit on the last one
*/
RxBD(ch, i - 1).status |= RX_BD_W;
dbg("initialise TX buffer descriptor ring\r\n");
/*
* Initialize the Tx Buffer Descriptor ring
*/
for (i = 0; i < NTXBD; ++i)
{
TxBD(ch, i).status = TX_BD_INTERRUPT;
TxBD(ch, i).length = 0;
TxBD(ch, i).data = NULL;
}
/*
* Initialize the Tx Buffer Descriptor ring
*/
for (i = 0; i < NTXBD; ++i)
{
TxBD(ch, i).status = TX_BD_INTERRUPT;
TxBD(ch, i).length = 0;
TxBD(ch, i).data = NULL;
}
/*
* Set the WRAP bit on the last one
*/
TxBD(ch, i - 1).status |= TX_BD_W;
/*
* Set the WRAP bit on the last one
*/
TxBD(ch, i - 1).status |= TX_BD_W;
/*
* Initialize the buffer descriptor indexes
*/
iTxbd_new = iTxbd_old = iRxbd = 0;
/*
* Initialize the buffer descriptor indexes
*/
iTxbd_new = iTxbd_old = iRxbd = 0;
}
void fecbd_dump(uint8_t ch)
{
#ifdef DBG_FECBD
int i;
int i;
xprintf("\n------------ FEC%d BDs -----------\n",ch);
xprintf("RxBD Ring\n");
for (i = 0; i < NRXBD; i++)
{
xprintf("%02d: BD Addr=0x%08x, Ctrl=0x%04x, Lgth=%04d, DataPtr=0x%08x\n",
i, &RxBD(ch, i),
RxBD(ch, i).status,
RxBD(ch, i).length,
RxBD(ch, i).data);
}
xprintf("TxBD Ring\n");
for (i = 0; i < NTXBD; i++)
{
xprintf("%02d: BD Addr=0x%08x, Ctrl=0x%04x, Lgth=%04d, DataPtr=0x%08x\n",
i, &TxBD(ch, i),
TxBD(ch, i).status,
TxBD(ch, i).length,
TxBD(ch, i).data);
}
xprintf("--------------------------------\n\n");
xprintf("\n------------ FEC%d BDs -----------\n",ch);
xprintf("RxBD Ring\n");
for (i = 0; i < NRXBD; i++)
{
xprintf("%02d: BD Addr=0x%08x, Ctrl=0x%04x, Lgth=%04d, DataPtr=0x%08x\n",
i, &RxBD(ch, i),
RxBD(ch, i).status,
RxBD(ch, i).length,
RxBD(ch, i).data);
}
xprintf("TxBD Ring\n");
for (i = 0; i < NTXBD; i++)
{
xprintf("%02d: BD Addr=0x%08x, Ctrl=0x%04x, Lgth=%04d, DataPtr=0x%08x\n",
i, &TxBD(ch, i),
TxBD(ch, i).status,
TxBD(ch, i).length,
TxBD(ch, i).data);
}
xprintf("--------------------------------\n\n");
#endif /* DBG_FECBD */
}
@@ -165,28 +165,28 @@ void fecbd_dump(uint8_t ch)
*/
uint32_t fecbd_get_start(uint8_t ch, uint8_t direction)
{
switch (direction)
{
case Rx:
return (uint32_t)((int)RxBD + (ch * sizeof(FECBD) * NRXBD));
case Tx:
default:
return (uint32_t)((int)TxBD + (ch * sizeof(FECBD) * NTXBD));
}
switch (direction)
{
case Rx:
return (uint32_t)((int)RxBD + (ch * sizeof(FECBD) * NRXBD));
case Tx:
default:
return (uint32_t)((int)TxBD + (ch * sizeof(FECBD) * NTXBD));
}
}
FECBD *fecbd_rx_alloc(uint8_t ch)
{
int i = iRxbd;
int i = iRxbd;
/* Check to see if the ring of BDs is full */
if (RxBD(ch, i).status & RX_BD_E)
return NULL;
/* Check to see if the ring of BDs is full */
if (RxBD(ch, i).status & RX_BD_E)
return NULL;
/* Increment the circular index */
iRxbd = (uint8_t)((iRxbd + 1) % NRXBD);
/* Increment the circular index */
iRxbd = (uint8_t)((iRxbd + 1) % NRXBD);
return &RxBD(ch, i);
return &RxBD(ch, i);
}
/*
@@ -201,16 +201,16 @@ FECBD *fecbd_rx_alloc(uint8_t ch)
*/
FECBD *fecbd_tx_alloc(uint8_t ch)
{
int i = iTxbd_new;
int i = iTxbd_new;
/* Check to see if the ring of BDs is full */
if (TxBD(ch, i).status & TX_BD_R)
return NULL;
/* Check to see if the ring of BDs is full */
if (TxBD(ch, i).status & TX_BD_R)
return NULL;
/* Increment the circular index */
iTxbd_new = (uint8_t)((iTxbd_new + 1) % NTXBD);
/* Increment the circular index */
iTxbd_new = (uint8_t)((iTxbd_new + 1) % NTXBD);
return &TxBD(ch, i);
return &TxBD(ch, i);
}
/*
@@ -226,14 +226,14 @@ FECBD *fecbd_tx_alloc(uint8_t ch)
*/
FECBD *fecbd_tx_free(uint8_t ch)
{
int i = iTxbd_old;
int i = iTxbd_old;
/* Check to see if the ring of BDs is empty */
if ((TxBD(ch, i).data == NULL) || (TxBD(ch, i).status & TX_BD_R))
return NULL;
/* Check to see if the ring of BDs is empty */
if ((TxBD(ch, i).data == NULL) || (TxBD(ch, i).status & TX_BD_R))
return NULL;
/* Increment the circular index */
iTxbd_old = (uint8_t)((iTxbd_old + 1) % NTXBD);
/* Increment the circular index */
iTxbd_old = (uint8_t)((iTxbd_old + 1) % NTXBD);
return &TxBD(ch, i);
return &TxBD(ch, i);
}

448
net/ip.c
View File

@@ -1,5 +1,5 @@
/*
* File: ip.c
* File: ip.c
* Purpose: Internet Protcol device driver
*
* Notes:
@@ -13,7 +13,7 @@
#include <stddef.h>
#define IP_DEBUG
//#define IP_DEBUG
#if defined(IP_DEBUG)
#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
#else
@@ -22,300 +22,300 @@
void ip_init(IP_INFO *info, IP_ADDR_P myip, IP_ADDR_P gateway, IP_ADDR_P netmask)
{
int index;
int index;
for (index = 0; index < sizeof(IP_ADDR); index++)
{
info->myip[index] = myip[index];
info->gateway[index] = gateway[index];
info->netmask[index] = netmask[index];
info->broadcast[index] = 0xFF;
}
for (index = 0; index < sizeof(IP_ADDR); index++)
{
info->myip[index] = myip[index];
info->gateway[index] = gateway[index];
info->netmask[index] = netmask[index];
info->broadcast[index] = 0xFF;
}
info->rx = 0;
info->rx_unsup = 0;
info->tx = 0;
info->err = 0;
info->rx = 0;
info->rx_unsup = 0;
info->tx = 0;
info->err = 0;
}
uint8_t *ip_get_myip(IP_INFO *info)
{
if (info != 0)
{
return (uint8_t *) &info->myip[0];
}
if (info != 0)
{
return (uint8_t *) &info->myip[0];
}
dbg("info is NULL!\n\t");
return 0;
return 0;
}
int ip_addr_compare(IP_ADDR_P addr1, IP_ADDR_P addr2)
{
int i;
int i;
for (i = 0; i < sizeof(IP_ADDR); i++)
{
if (addr1[i] != addr2[i])
return 0;
}
return 1;
for (i = 0; i < sizeof(IP_ADDR); i++)
{
if (addr1[i] != addr2[i])
return 0;
}
return 1;
}
uint8_t *ip_resolve_route(NIF *nif, IP_ADDR_P destip)
{
/*
* This function determines whether or not an outgoing IP
* packet needs to be transmitted on the local net or sent
* to the router for transmission.
*/
IP_INFO *info;
IP_ADDR mask, result;
IP_ADDR bc = { 255, 255, 255, 255 };
int i;
/*
* This function determines whether or not an outgoing IP
* packet needs to be transmitted on the local net or sent
* to the router for transmission.
*/
IP_INFO *info;
IP_ADDR mask, result;
IP_ADDR bc = { 255, 255, 255, 255 };
int i;
info = nif_get_protocol_info(nif, ETH_FRM_IP);
info = nif_get_protocol_info(nif, ETH_FRM_IP);
if (memcmp(destip, bc, 4) == 0)
{
dbg("destip is broadcast address, no gateway needed\r\n");
return destip;
}
{
dbg("destip is broadcast address, no gateway needed\r\n");
return destip;
}
/* create mask for local IP */
for (i = 0; i < sizeof(IP_ADDR); i++)
{
mask[i] = info->myip[i] & info->netmask[i];
}
/* create mask for local IP */
for (i = 0; i < sizeof(IP_ADDR); i++)
{
mask[i] = info->myip[i] & info->netmask[i];
}
/* apply mask to the destination IP */
for (i = 0; i < sizeof(IP_ADDR); i++)
{
result[i] = mask[i] & destip[i];
}
/* apply mask to the destination IP */
for (i = 0; i < sizeof(IP_ADDR); i++)
{
result[i] = mask[i] & destip[i];
}
/* See if destination IP is local or not */
if (ip_addr_compare(mask, result))
{
/* The destination IP is on the local net */
return arp_resolve(nif, ETH_FRM_IP, destip);
}
else
{
/* The destination IP is not on the local net */
return arp_resolve(nif, ETH_FRM_IP, info->gateway);
}
/* See if destination IP is local or not */
if (ip_addr_compare(mask, result))
{
/* The destination IP is on the local net */
return arp_resolve(nif, ETH_FRM_IP, destip);
}
else
{
/* The destination IP is not on the local net */
return arp_resolve(nif, ETH_FRM_IP, info->gateway);
}
}
int ip_send(NIF *nif, uint8_t *dest, uint8_t *src, uint8_t protocol, NBUF *pNbuf)
{
/*
* This function assembles an IP datagram and passes it
* onto the hardware to be sent over the network.
*/
uint8_t *route;
ip_frame_hdr *ipframe;
/*
* This function assembles an IP datagram and passes it
* onto the hardware to be sent over the network.
*/
uint8_t *route;
ip_frame_hdr *ipframe;
/*
* Construct the IP header
*/
ipframe = (ip_frame_hdr*) &pNbuf->data[IP_HDR_OFFSET];
/*
* Construct the IP header
*/
ipframe = (ip_frame_hdr*) &pNbuf->data[IP_HDR_OFFSET];
/* IP version 4, Internet Header Length of 5 32-bit words */
ipframe->version_ihl = 0x45;
/* IP version 4, Internet Header Length of 5 32-bit words */
ipframe->version_ihl = 0x45;
/* Type of Service == 0, normal and routine */
ipframe->service_type = 0x00;
/* Type of Service == 0, normal and routine */
ipframe->service_type = 0x00;
/* Total length of data */
ipframe->total_length = (uint16_t) (pNbuf->length + IP_HDR_SIZE);
/* Total length of data */
ipframe->total_length = (uint16_t) (pNbuf->length + IP_HDR_SIZE);
/* User defined identification */
ipframe->identification = 0x0000;
/* User defined identification */
ipframe->identification = 0x0000;
/* Fragment Flags and Offset -- Don't fragment, last frag */
ipframe->flags_frag_offset = 0x0000;
/* Fragment Flags and Offset -- Don't fragment, last frag */
ipframe->flags_frag_offset = 0x0000;
/* Time To Live */
ipframe->ttl = 0xFF;
/* Time To Live */
ipframe->ttl = 0xFF;
/* Protocol */
ipframe->protocol = protocol;
/* Protocol */
ipframe->protocol = protocol;
/* Checksum, computed later, zeroed for computation */
ipframe->checksum = 0x0000;
/* Checksum, computed later, zeroed for computation */
ipframe->checksum = 0x0000;
/* source IP address */
ipframe->source_addr[0] = src[0];
ipframe->source_addr[1] = src[1];
ipframe->source_addr[2] = src[2];
ipframe->source_addr[3] = src[3];
/* source IP address */
ipframe->source_addr[0] = src[0];
ipframe->source_addr[1] = src[1];
ipframe->source_addr[2] = src[2];
ipframe->source_addr[3] = src[3];
/* dest IP address */
ipframe->dest_addr[0] = dest[0];
ipframe->dest_addr[1] = dest[1];
ipframe->dest_addr[2] = dest[2];
ipframe->dest_addr[3] = dest[3];
/* dest IP address */
ipframe->dest_addr[0] = dest[0];
ipframe->dest_addr[1] = dest[1];
ipframe->dest_addr[2] = dest[2];
ipframe->dest_addr[3] = dest[3];
/* Compute checksum */
ipframe->checksum = ip_chksum((uint16_t *) ipframe, IP_HDR_SIZE);
/* Compute checksum */
ipframe->checksum = ip_chksum((uint16_t *) ipframe, IP_HDR_SIZE);
/* Increment the packet length by the size of the IP header */
pNbuf->length += IP_HDR_SIZE;
/* Increment the packet length by the size of the IP header */
pNbuf->length += IP_HDR_SIZE;
/*
* Determine the hardware address of the recipient
*/
IP_ADDR bc = { 255, 255, 255, 255};
if (memcmp(bc, dest, 4) != 0)
{
route = ip_resolve_route(nif, dest);
if (route == NULL)
{
dbg("Unable to locate %d.%d.%d.%d\r\n",
dest[0], dest[1], dest[2], dest[3]);
return 0;
}
}
else
{
route = bc;
dbg("route = broadcast\r\n");
dbg("nif = %p\r\n", nif);
dbg("nif->send = %p\r\n", nif->send);
}
/*
* Determine the hardware address of the recipient
*/
IP_ADDR bc = { 255, 255, 255, 255};
if (memcmp(bc, dest, 4) != 0)
{
route = ip_resolve_route(nif, dest);
if (route == NULL)
{
dbg("Unable to locate %d.%d.%d.%d\r\n",
dest[0], dest[1], dest[2], dest[3]);
return 0;
}
}
else
{
route = bc;
dbg("route = broadcast\r\n");
dbg("nif = %p\r\n", nif);
dbg("nif->send = %p\r\n", nif->send);
}
return nif->send(nif, route, &nif->hwa[0], ETH_FRM_IP, pNbuf);
return nif->send(nif, route, &nif->hwa[0], ETH_FRM_IP, pNbuf);
}
#if defined(DEBUG_PRINT)
void dump_ip_frame(ip_frame_hdr *ipframe)
{
xprintf("Version: %02X\n", ((ipframe->version_ihl & 0x00f0) >> 4));
xprintf("IHL: %02X\n", ipframe->version_ihl & 0x000f);
xprintf("Service: %02X\n", ipframe->service_type);
xprintf("Length: %04X\n", ipframe->total_length);
xprintf("Ident: %04X\n", ipframe->identification);
xprintf("Flags: %02X\n", ((ipframe->flags_frag_offset & 0xC000) >> 14));
xprintf("Frag: %04X\n", ipframe->flags_frag_offset & 0x3FFF);
xprintf("TTL: %02X\n", ipframe->ttl);
xprintf("Protocol: %02X\n", ipframe->protocol);
xprintf("Chksum: %04X\n", ipframe->checksum);
xprintf("Source : %d.%d.%d.%d\n",
ipframe->source_addr[0],
ipframe->source_addr[1],
ipframe->source_addr[2],
ipframe->source_addr[3]);
xprintf("Dest : %d.%d.%d.%d\n",
ipframe->dest_addr[0],
ipframe->dest_addr[1],
ipframe->dest_addr[2],
ipframe->dest_addr[3]);
xprintf("Options: %08X\n", ipframe->options);
xprintf("Version: %02X\n", ((ipframe->version_ihl & 0x00f0) >> 4));
xprintf("IHL: %02X\n", ipframe->version_ihl & 0x000f);
xprintf("Service: %02X\n", ipframe->service_type);
xprintf("Length: %04X\n", ipframe->total_length);
xprintf("Ident: %04X\n", ipframe->identification);
xprintf("Flags: %02X\n", ((ipframe->flags_frag_offset & 0xC000) >> 14));
xprintf("Frag: %04X\n", ipframe->flags_frag_offset & 0x3FFF);
xprintf("TTL: %02X\n", ipframe->ttl);
xprintf("Protocol: %02X\n", ipframe->protocol);
xprintf("Chksum: %04X\n", ipframe->checksum);
xprintf("Source : %d.%d.%d.%d\n",
ipframe->source_addr[0],
ipframe->source_addr[1],
ipframe->source_addr[2],
ipframe->source_addr[3]);
xprintf("Dest : %d.%d.%d.%d\n",
ipframe->dest_addr[0],
ipframe->dest_addr[1],
ipframe->dest_addr[2],
ipframe->dest_addr[3]);
xprintf("Options: %08X\n", ipframe->options);
}
#endif
uint16_t ip_chksum(uint16_t *data, int num)
{
int chksum, ichksum;
uint16_t temp;
int chksum, ichksum;
uint16_t temp;
chksum = 0;
num = num >> 1; /* from bytes to words */
for (; num; num--, data++)
{
temp = *data;
ichksum = chksum + temp;
ichksum = ichksum & 0x0000FFFF;
if ((ichksum < temp) || (ichksum < chksum))
{
ichksum += 1;
ichksum = ichksum & 0x0000FFFF;
}
chksum = ichksum;
}
return (uint16_t) ~chksum;
chksum = 0;
num = num >> 1; /* from bytes to words */
for (; num; num--, data++)
{
temp = *data;
ichksum = chksum + temp;
ichksum = ichksum & 0x0000FFFF;
if ((ichksum < temp) || (ichksum < chksum))
{
ichksum += 1;
ichksum = ichksum & 0x0000FFFF;
}
chksum = ichksum;
}
return (uint16_t) ~chksum;
}
static int validate_ip_hdr(NIF *nif, ip_frame_hdr *ipframe)
{
int index, chksum;
IP_INFO *info;
int index, chksum;
IP_INFO *info;
/*
* Check the IP Version
*/
if (IP_VERSION(ipframe) != 4)
return 0;
/*
* Check the IP Version
*/
if (IP_VERSION(ipframe) != 4)
return 0;
/*
* Check Internet Header Length
*/
if (IP_IHL(ipframe) < 5)
return 0;
/*
* Check Internet Header Length
*/
if (IP_IHL(ipframe) < 5)
return 0;
/*
* Check the destination IP address
*/
info = nif_get_protocol_info(nif,ETH_FRM_IP);
for (index = 0; index < sizeof(IP_ADDR); index++)
if (info->myip[index] != ipframe->dest_addr[index])
return 0;
/*
* Check the destination IP address
*/
info = nif_get_protocol_info(nif,ETH_FRM_IP);
for (index = 0; index < sizeof(IP_ADDR); index++)
if (info->myip[index] != ipframe->dest_addr[index])
return 0;
/*
* Check the checksum
*/
chksum = (int)((uint16_t) IP_CHKSUM(ipframe));
IP_CHKSUM(ipframe) = 0;
/*
* Check the checksum
*/
chksum = (int)((uint16_t) IP_CHKSUM(ipframe));
IP_CHKSUM(ipframe) = 0;
if (ip_chksum((uint16_t *) ipframe, IP_IHL(ipframe) * 4) != chksum)
return 0;
if (ip_chksum((uint16_t *) ipframe, IP_IHL(ipframe) * 4) != chksum)
return 0;
IP_CHKSUM(ipframe) = (uint16_t) chksum;
IP_CHKSUM(ipframe) = (uint16_t) chksum;
return 1;
return 1;
}
void ip_handler(NIF *nif, NBUF *pNbuf)
{
/*
* IP packet handler
*/
ip_frame_hdr *ipframe;
/*
* IP packet handler
*/
ip_frame_hdr *ipframe;
dbg("packet received\r\n");
ipframe = (ip_frame_hdr *) &pNbuf->data[pNbuf->offset];
ipframe = (ip_frame_hdr *) &pNbuf->data[pNbuf->offset];
/*
* Verify valid IP header and destination IP
*/
if (!validate_ip_hdr(nif, ipframe))
{
dbg("not a valid IP packet!\r\n");
nbuf_free(pNbuf);
return;
}
/*
* Verify valid IP header and destination IP
*/
if (!validate_ip_hdr(nif, ipframe))
{
dbg("not a valid IP packet!\r\n");
pNbuf->offset += (IP_IHL(ipframe) * 4);
pNbuf->length = (uint16_t)(IP_LENGTH(ipframe) - (IP_IHL(ipframe) * 4));
nbuf_free(pNbuf);
return;
}
/*
* Call the appriopriate handler
*/
switch (IP_PROTOCOL(ipframe))
{
case IP_PROTO_ICMP:
// FIXME: icmp_handler(nif, pNbuf);
break;
case IP_PROTO_UDP:
udp_handler(nif,pNbuf);
break;
default:
dbg("no protocol handler registered for protocol %d\r\n",
__FUNCTION__, IP_PROTOCOL(ipframe));
nbuf_free(pNbuf);
break;
}
return;
pNbuf->offset += (IP_IHL(ipframe) * 4);
pNbuf->length = (uint16_t)(IP_LENGTH(ipframe) - (IP_IHL(ipframe) * 4));
/*
* Call the appriopriate handler
*/
switch (IP_PROTOCOL(ipframe))
{
case IP_PROTO_ICMP:
// FIXME: icmp_handler(nif, pNbuf);
break;
case IP_PROTO_UDP:
udp_handler(nif,pNbuf);
break;
default:
dbg("no protocol handler registered for protocol %d\r\n",
__FUNCTION__, IP_PROTOCOL(ipframe));
nbuf_free(pNbuf);
break;
}
return;
}

190
net/udp.c
View File

@@ -21,8 +21,8 @@
typedef struct
{
uint16_t port;
void (*handler)(NIF *, NBUF *);
uint16_t port;
void (*handler)(NIF *, NBUF *);
} UDP_BOUND_PORT;
#define UDP_MAX_PORTS (5) /* plenty for this implementation */
@@ -34,151 +34,151 @@ static uint16_t udp_port;
void udp_init(void)
{
int index;
int index;
for (index = 0; index < UDP_MAX_PORTS; ++index)
{
udp_port_table[index].port = 0;
udp_port_table[index].handler = 0;
}
for (index = 0; index < UDP_MAX_PORTS; ++index)
{
udp_port_table[index].port = 0;
udp_port_table[index].handler = 0;
}
udp_port = DEFAULT_UDP_PORT; /* next free port */
udp_port = DEFAULT_UDP_PORT; /* next free port */
}
void udp_prime_port(uint16_t init_port)
{
udp_port = init_port;
udp_port = init_port;
}
void udp_bind_port(uint16_t port, void (*handler)(NIF *, NBUF *))
{
int index;
int index;
for (index = 0; index < UDP_MAX_PORTS; ++index)
{
if (udp_port_table[index].port == 0)
{
udp_port_table[index].port = port;
udp_port_table[index].handler = handler;
for (index = 0; index < UDP_MAX_PORTS; ++index)
{
if (udp_port_table[index].port == 0)
{
udp_port_table[index].port = port;
udp_port_table[index].handler = handler;
return;
}
}
return;
}
}
}
void udp_free_port(uint16_t port)
{
int index;
int index;
for (index = 0; index < UDP_MAX_PORTS; ++index)
{
if (udp_port_table[index].port == port)
{
udp_port_table[index].port = 0;
for (index = 0; index < UDP_MAX_PORTS; ++index)
{
if (udp_port_table[index].port == port)
{
udp_port_table[index].port = 0;
return;
}
}
return;
}
}
}
static void *udp_port_handler(uint16_t port)
{
int index;
int index;
for (index = 0; index < UDP_MAX_PORTS; ++index)
{
if (udp_port_table[index].port == port)
{
return (void *) udp_port_table[index].handler;
}
}
return NULL;
for (index = 0; index < UDP_MAX_PORTS; ++index)
{
if (udp_port_table[index].port == port)
{
return (void *) udp_port_table[index].handler;
}
}
return NULL;
}
uint16_t udp_obtain_free_port(void)
{
uint16_t port;
uint16_t port;
port = udp_port;
if (--udp_port <= 255)
udp_port = DEFAULT_UDP_PORT;
port = udp_port;
if (--udp_port <= 255)
udp_port = DEFAULT_UDP_PORT;
return port;
return port;
}
int udp_send(NIF *nif, uint8_t *dest, int sport, int dport, NBUF *pNbuf)
{
uint8_t *myip;
uint8_t *myip;
if (nif == NULL)
{
dbg("%s: nif is NULL\r\n", __FUNCTION__);
return 0;
}
if (nif == NULL)
{
dbg("%s: nif is NULL\r\n", __FUNCTION__);
return 0;
}
/*
* This function takes data, creates a UDP frame from it and
* passes it onto the IP layer
*/
udp_frame_hdr *udpframe;
/*
* This function takes data, creates a UDP frame from it and
* passes it onto the IP layer
*/
udp_frame_hdr *udpframe;
udpframe = (udp_frame_hdr *) &pNbuf->data[UDP_HDR_OFFSET];
udpframe = (udp_frame_hdr *) &pNbuf->data[UDP_HDR_OFFSET];
/* Set UDP source port */
udpframe->src_port = (uint16_t) sport;
/* Set UDP source port */
udpframe->src_port = (uint16_t) sport;
/* Set UDP destination port */
udpframe->dest_port = (uint16_t) dport;
/* Set UDP destination port */
udpframe->dest_port = (uint16_t) dport;
/* Set length */
udpframe->length = (uint16_t) (pNbuf->length + UDP_HDR_SIZE);
/* Set length */
udpframe->length = (uint16_t) (pNbuf->length + UDP_HDR_SIZE);
/* No checksum calcualation needed */
udpframe->chksum = (uint16_t) 0;
/* No checksum calcualation needed */
udpframe->chksum = (uint16_t) 0;
/* Add the length of the UDP packet to the total length of the packet */
pNbuf->length += 8;
/* Add the length of the UDP packet to the total length of the packet */
pNbuf->length += 8;
myip = ip_get_myip(nif_get_protocol_info(nif, ETH_FRM_IP));
myip = ip_get_myip(nif_get_protocol_info(nif, ETH_FRM_IP));
dbg("%s: sent UDP request to %d.%d.%d.%d from %d.%d.%d.%d\r\n", __FUNCTION__,
dest[0], dest[1], dest[2], dest[3],
myip[0], myip[1], myip[2], myip[3]);
dbg("%s: sent UDP request to %d.%d.%d.%d from %d.%d.%d.%d\r\n", __FUNCTION__,
dest[0], dest[1], dest[2], dest[3],
myip[0], myip[1], myip[2], myip[3]);
return (ip_send(nif, dest, myip, IP_PROTO_UDP, pNbuf));
return (ip_send(nif, dest, myip, IP_PROTO_UDP, pNbuf));
}
void udp_handler(NIF *nif, NBUF *pNbuf)
{
/*
* This function handles incoming UDP packets
*/
udp_frame_hdr *udpframe;
void (*handler)(NIF *, NBUF *);
/*
* This function handles incoming UDP packets
*/
udp_frame_hdr *udpframe;
void (*handler)(NIF *, NBUF *);
udpframe = (udp_frame_hdr *) &pNbuf->data[pNbuf->offset];
udpframe = (udp_frame_hdr *) &pNbuf->data[pNbuf->offset];
dbg("%s: packet received\r\n", __FUNCTION__);
dbg("%s: packet received\r\n", __FUNCTION__);
/*
* Adjust the length and valid data offset of the packet we are
* passing on
*/
pNbuf->length -= UDP_HDR_SIZE;
pNbuf->offset += UDP_HDR_SIZE;
/*
* Adjust the length and valid data offset of the packet we are
* passing on
*/
pNbuf->length -= UDP_HDR_SIZE;
pNbuf->offset += UDP_HDR_SIZE;
/*
* Traverse the list of bound ports to see if there is a higher
* level protocol to pass the packet on to
*/
if ((handler = (void(*)(NIF*, NBUF*)) udp_port_handler(UDP_DEST(udpframe))) != NULL)
handler(nif, pNbuf);
else
{
dbg("%s: received UDP packet for non-supported port\n", __FUNCTION__);
nbuf_free(pNbuf);
}
/*
* Traverse the list of bound ports to see if there is a higher
* level protocol to pass the packet on to
*/
if ((handler = (void(*)(NIF*, NBUF*)) udp_port_handler(UDP_DEST(udpframe))) != NULL)
handler(nif, pNbuf);
else
{
dbg("%s: received UDP packet for non-supported port\n", __FUNCTION__);
nbuf_free(pNbuf);
}
return;
return;
}

175
pci/pci.c
View File

@@ -35,7 +35,7 @@
//#define DEBUG_PCI
#ifdef DEBUG_PCI
#define dbg(format, arg...) do { xprintf("DEBUG: " format "", ##arg); } while (0)
#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
#else
#define dbg(format, arg...) do { ; } while (0)
#endif /* DEBUG_PCI */
@@ -162,7 +162,7 @@ static int32_t pci_get_interrupt_cause(int32_t *handles)
return handle;
}
}
dbg("%s: no interrupt cause found\r\n", __FUNCTION__);
dbg("%s: no interrupt cause found\r\n");
return -1;
}
@@ -189,7 +189,7 @@ void irq5_handler(void)
newvalue = pci_call_interrupt_chain(handle, value);
if (newvalue == value)
{
dbg("%s: interrupt not handled!\r\n", __FUNCTION__);
dbg("%s: interrupt not handled!\r\n");
}
}
}
@@ -211,7 +211,7 @@ void irq7_handler(void)
newvalue = pci_call_interrupt_chain(handle, value);
if (newvalue == value)
{
dbg("%s: interrupt not handled!\r\n", __FUNCTION__);
dbg("%s: interrupt not handled!\r\n");
}
}
}
@@ -587,7 +587,168 @@ int32_t pci_unhook_interrupt(int32_t handle)
return PCI_SUCCESSFUL;
}
/*
* Not implemented PCI_BIOS functions
*/
uint8_t pci_fast_read_config_byte(int32_t handle, uint16_t reg)
{
return PCI_FUNC_NOT_SUPPORTED;
}
uint16_t pci_fast_read_config_word(int32_t handle, uint16_t reg)
{
return PCI_FUNC_NOT_SUPPORTED;
}
uint32_t pci_fast_read_config_longword(int32_t handle, uint16_t reg)
{
return PCI_FUNC_NOT_SUPPORTED;
}
int32_t pci_special_cycle(uint16_t bus, uint32_t data)
{
return PCI_FUNC_NOT_SUPPORTED;
}
int32_t pci_get_routing(int32_t handle)
{
return PCI_FUNC_NOT_SUPPORTED;
}
int32_t pci_set_interrupt(int32_t handle)
{
return PCI_FUNC_NOT_SUPPORTED;
}
int32_t pci_get_card_used(int32_t handle, uint32_t *address)
{
return PCI_FUNC_NOT_SUPPORTED;
}
int32_t pci_set_card_used(int32_t handle, uint32_t *callback)
{
return PCI_FUNC_NOT_SUPPORTED;
}
int32_t pci_read_mem_byte(int32_t handle, uint32_t offset, uint8_t *address)
{
return PCI_FUNC_NOT_SUPPORTED;
}
int32_t pci_read_mem_word(int32_t handle, uint32_t offset, uint16_t *address)
{
return PCI_FUNC_NOT_SUPPORTED;
}
int32_t pci_read_mem_longword(int32_t handle, uint32_t offset, uint32_t *address)
{
return PCI_FUNC_NOT_SUPPORTED;
}
uint8_t pci_fast_read_mem_byte(int32_t handle, uint32_t offset)
{
return PCI_FUNC_NOT_SUPPORTED;
}
uint16_t pci_fast_read_mem_word(int32_t handle, uint32_t offset)
{
return PCI_FUNC_NOT_SUPPORTED;
}
uint32_t pci_fast_read_mem_longword(int32_t handle, uint32_t offset)
{
return PCI_FUNC_NOT_SUPPORTED;
}
int32_t pci_write_mem_byte(int32_t handle, uint32_t offset, uint16_t val)
{
return PCI_FUNC_NOT_SUPPORTED;
}
int32_t pci_write_mem_word(int32_t handle, uint32_t offset, uint16_t val)
{
return PCI_FUNC_NOT_SUPPORTED;
}
int32_t pci_write_mem_longword(int32_t handle, uint32_t offset, uint32_t val)
{
return PCI_FUNC_NOT_SUPPORTED;
}
int32_t pci_read_io_byte(int32_t handle, uint32_t offset, uint8_t *address)
{
return PCI_FUNC_NOT_SUPPORTED;
}
int32_t pci_read_io_word(int32_t handle, uint32_t offset, uint16_t *address)
{
return PCI_FUNC_NOT_SUPPORTED;
}
int32_t pci_read_io_longword(int32_t handle, uint32_t offset, uint32_t *address)
{
return PCI_FUNC_NOT_SUPPORTED;
}
uint8_t pci_fast_read_io_byte(int32_t handle, uint32_t offset)
{
return PCI_FUNC_NOT_SUPPORTED;
}
uint16_t pci_fast_read_io_word(int32_t handle, uint32_t offset)
{
return PCI_FUNC_NOT_SUPPORTED;
}
uint32_t pci_fast_read_io_longword(int32_t handle, uint32_t offset)
{
return PCI_FUNC_NOT_SUPPORTED;
}
int32_t pci_write_io_byte(int32_t handle, uint32_t offset, uint16_t val)
{
return PCI_FUNC_NOT_SUPPORTED;
}
int32_t pci_write_io_word(int32_t handle, uint32_t offset, uint16_t val)
{
return PCI_FUNC_NOT_SUPPORTED;
}
int32_t pci_write_io_longword(int32_t handle, uint32_t offset, uint32_t val)
{
return PCI_FUNC_NOT_SUPPORTED;
}
int32_t pci_get_machine_id(void)
{
return PCI_FUNC_NOT_SUPPORTED;
}
int32_t pci_get_pagesize(void)
{
return PCI_FUNC_NOT_SUPPORTED;
}
int32_t pci_virt_to_bus(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer)
{
return PCI_FUNC_NOT_SUPPORTED;
}
int32_t pci_bus_to_virt(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer)
{
return PCI_FUNC_NOT_SUPPORTED;
}
int32_t pci_virt_to_phys(uint32_t address, PCI_CONV_ADR *pointer)
{
return PCI_FUNC_NOT_SUPPORTED;
}
int32_t pci_phys_to_virt(uint32_t address, PCI_CONV_ADR *pointer)
{
return PCI_FUNC_NOT_SUPPORTED;
}
/*
* pci_device_config()
@@ -649,7 +810,7 @@ static void pci_device_config(uint16_t bus, uint16_t device, uint16_t function)
*/
struct pci_rd *rd = &descriptors[barnum];
dbg("%s: address = %08x\r\n", __FUNCTION__, address);
dbg("%s: address = %08x\r\n", address);
if (IS_PCI_MEM_BAR(address))
{
/* adjust base address to card's alignment requirements */
@@ -738,10 +899,10 @@ static void pci_device_config(uint16_t bus, uint16_t device, uint16_t function)
/* write it to PCIERBAR and enable ROM */
pci_write_config_longword(handle, PCIERBAR, swpl(address | 1));
dbg("%s: set PCIERBAR on device 0x%02x to 0x%08x\r\n", __FUNCTION__, handle, address | 1);
dbg("%s: set PCIERBAR on device 0x%02x to 0x%08x\r\n", handle, address | 1);
/* read value back just to be sure */
dbg("%s: PCIERBAR = %p\r\n", __FUNCTION__, swpl(pci_read_config_longword(handle, PCIERBAR)));
dbg("%s: PCIERBAR = %p\r\n", swpl(pci_read_config_longword(handle, PCIERBAR)));
rd->next = sizeof(struct pci_rd);

469
pci/pci_wrappers.S Normal file
View File

@@ -0,0 +1,469 @@
/*
* pci.S
*
* Purpose: PCI configuration for the Coldfire builtin PCI bridge.
*
* Notes:
*
* This file is part of BaS_gcc.
*
* BaS_gcc is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* BaS_gcc is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
*
* Created on: 08.05.2014
* Author: David Galvez
*/
.global _wrapper_find_pci_device
.global _wrapper_find_pci_classcode
.global _wrapper_read_config_longword
.global _wrapper_read_config_word
.global _wrapper_read_config_byte
.global _wrapper_fast_read_config_byte
.global _wrapper_fast_read_config_word
.global _wrapper_fast_read_config_longword
.global _wrapper_write_config_longword
.global _wrapper_write_config_word
.global _wrapper_write_config_byte
.global _wrapper_get_resource
.global _wrapper_hook_interrupt
.global _wrapper_unhook_interrupt
.global _wrapper_special_cycle
.global _wrapper_get_routing
.global _wrapper_set_interrupt
.global _wrapper_get_resource
.global _wrapper_get_card_used
.global _wrapper_set_card_used
.global _wrapper_read_mem_byte
.global _wrapper_read_mem_word
.global _wrapper_read_mem_longword
.global _wrapper_fast_read_mem_byte
.global _wrapper_fast_read_mem_word
.global _wrapper_fast_read_mem_longword
.global _wrapper_write_mem_byte
.global _wrapper_write_mem_word
.global _wrapper_write_mem_longword
.global _wrapper_read_io_byte
.global _wrapper_read_io_word
.global _wrapper_read_io_longword
.global _wrapper_fast_read_io_byte
.global _wrapper_fast_read_io_word
.global _wrapper_fast_read_io_longword
.global _wrapper_write_io_byte
.global _wrapper_write_io_word
.global _wrapper_write_io_longword
.global _wrapper_get_machine_id
.global _wrapper_get_pagesize
.global _wrapper_virt_to_bus
.global _wrapper_bus_to_virt
.global _wrapper_virt_to_phys
.global _wrapper_phys_to_virt
_wrapper_find_pci_device:
move.l D1,-(SP) // index
move.l D0,-(SP) // Vendor ID
move.l #16,D1
lsr.l D1,D0
move.l D0,-(SP) // Device ID
jsr _pci_find_device
add.l #12,SP
rts
_wrapper_find_pci_classcode:
move.l D1,-(SP) // index
move.l D0,-(SP) // ID
jsr _pci_find_classcode
addq.l #8,SP
rts
_wrapper_read_config_byte:
move.l A0,-(SP) // pointer to space for read data
move.l D1,-(SP) // PCI register
move.l D0,-(SP) // handle
jsr _pci_read_config_byte
move.l 8(SP),A0 // PCI_BIOS expects value in memory
move.l D0,(A0)
add.l #12,SP
move.l #0,D0
rts
_wrapper_read_config_word:
move.l A0,-(SP) // pointer to space for read data
move.l D1,-(SP) // PCI register
move.l D0,-(SP) // handle
jsr _pci_read_config_word
move.l 8(SP),A0 // little to big endian
move.l D0,(A0)
mvz.b 1(A0),D0
lsl.l #8,D0
move.b (A0),D0
move.l D0,(A0) // PCI_BIOS expects value in memory, not in D0
add.l #12,SP
move.l #0,D0
rts
_wrapper_read_config_longword:
move.l A0,-(SP) // pointer to space for read data
move.l D1,-(SP) // PCI register
move.l D0,-(SP) // handle
jsr _pci_read_config_longword
move.l 8(SP),A0 // little to big endian
move.l D0,(A0)
mvz.b 3(A0),D0
lsl.l #8,D0
move.b 2(A0),D0
lsl.l #8,D0
move.b 1(A0),D0
lsl.l #8,D0
move.b (A0),D0
move.l D0,(A0) // PCI_BIOS expects value in memory, not in D0
add.l #12,SP
move.l #0,D0
rts
/* Not implemented */
_wrapper_fast_read_config_byte:
move.l D1,-(SP) // PCI register
move.l D0,-(SP) // handle
jsr _pci_fast_read_config_byte
addq.l #8,SP
rts
/* Not implemented */
_wrapper_fast_read_config_word:
move.l D1,-(SP) // PCI register
move.l D0,-(SP) // handle
jsr _pci_fast_read_config_word
addq.l #8,SP
rts
/* Not implemented */
_wrapper_fast_read_config_longword:
move.l D1,-(SP) // PCI register
move.l D0,-(SP) // handle
jsr _pci_fast_read_config_longword
addq.l #8,SP
rts
_wrapper_write_config_byte:
move.l D2,-(SP) // data to write
move.l D1,-(SP) // PCI register
move.l D0,-(SP) // handle
jsr _pci_write_config_byte
add.l #12,SP
rts
_wrapper_write_config_word:
move.l D0,-(SP) // make data little endian
moveq #0,D1
move.w D2,D1
lsr.l #8,D1
asl.l #8,D2
or.l D1,D2
move.l (SP)+,D0
move.l D2,-(SP) // data to write
move.l D1,-(SP) // PCI register
move.l D0,-(SP) // handle
jsr _pci_write_config_word
add.l #12,SP
rts
_wrapper_write_config_longword:
move.l D0,-(SP)
move.l D2,D0 // make data little endian
lsr.l #8,D0
asl.l #8,D2
and.l #0x00FF00FF,D0
and.l #0xFF00FF00,D2
or.l D0,D2
swap D2
move.l (SP)+,D0
move.l D2,-(SP) // data to write
move.l D1,-(SP) // PCI register
move.l D0,-(SP) // handle
jsr _pci_write_config_longword
add.l #12,SP
rts
_wrapper_hook_interrupt:
move.l A1,-(SP) // parameter for interrupt handler
move.l A0,-(SP) // pointer to interrupt handler
move.l D0,-(SP) // handle
jsr _pci_hook_interrupt
add.l #12,SP
rts
_wrapper_unhook_interrupt:
move.l D0,-(SP) // handle
jsr _pci_unhook_interrupt
addq.l #4,SP
rts
/* Not implemented */
_wrapper_special_cycle:
move.l D1,-(SP) // special cycle data
move.l D0,-(SP) // bus number
jsr _pci_special_cycle
addq.l #8,SP
rts
/* Not implemented */
_wrapper_get_routing:
move.l D0,-(SP) // handle
jsr _pci_get_routing
addq.l #4,SP
rts
/* Not implemented */
_wrapper_set_interrupt:
move.l D1,-(SP) // mode
move.l D0,-(SP) // handle
jsr _pci_set_interrupt
addq.l #8,SP
rts
_wrapper_get_resource:
move.l D0,-(SP) // handle
jsr _pci_get_resource
addq.l #4,SP
rts
/* Not implemented */
_wrapper_get_card_used:
move.l D1,-(SP) // address
move.l D0,-(SP) // handle
jsr _pci_get_card_used
addq.l #8,SP
rts
/* Not implemented */
_wrapper_set_card_used:
move.l A0,-(SP) // callback
move.l D0,-(SP) // handle
jsr _pci_set_card_used
addq.l #8,SP
rts
/* Not implemented */
_wrapper_read_mem_byte:
move.l A0,-(SP) // pointer to data in memory
move.l D1,-(SP) // address to access (in PCI memory address space)
move.l D0,-(SP) // handle
jsr _pci_read_mem_byte
add.l #12,SP
rts
/* Not implemented */
_wrapper_read_mem_word:
move.l A0,-(SP) // pointer to data in memory
move.l D1,-(SP) // address to access (in PCI memory address space)
move.l D0,-(SP) // handle
jsr _pci_read_mem_word
add.l #12,SP
rts
/* Not implemented */
_wrapper_read_mem_longword:
move.l A0,-(SP) // pointer to data in memory
move.l D1,-(SP) // address to access (in PCI memory address space)
move.l D0,-(SP) // handle
jsr _pci_read_mem_longword
add.l #12,SP
rts
/* Not implemented */
_wrapper_fast_read_mem_byte:
move.l D1,-(SP) // address to access (in PCI memory address space)
move.l D0,-(SP) // handle
jsr _pci_read_mem_byte
addq.l #8,SP
rts
/* Not implemented */
_wrapper_fast_read_mem_word:
move.l D1,-(SP) // address to access (in PCI memory address space)
move.l D0,-(SP) // handle
jsr _pci_read_mem_word
addq.l #8,SP
rts
/* Not implemented */
_wrapper_fast_read_mem_longword:
move.l D1,-(SP) // address to access (in PCI memory address space)
move.l D0,-(SP) // handle
jsr _pci_read_mem_longword
addq.l #8,SP
rts
/* Not implemented */
_wrapper_write_mem_byte:
move.l D2,-(SP) // data to write
move.l D1,-(SP) // address to access (in PCI memory address space)
move.l D0,-(SP) // handle
jsr _pci_write_mem_byte
add.l #12,SP
rts
/* Not implemented */
_wrapper_write_mem_word:
move.l D2,-(SP) // data to write
move.l D1,-(SP) // address to access (in PCI memory address space)
move.l D0,-(SP) // handle
jsr _pci_write_mem_word
add.l #12,SP
rts
/* Not implemented */
_wrapper_write_mem_longword:
move.l D2,-(SP) // data to write
move.l D1,-(SP) // address to access (in PCI memory address space)
move.l D0,-(SP) // handle
jsr _pci_write_mem_longword
add.l #12,SP
rts
/* Not implemented */
_wrapper_read_io_byte:
move.l A0,-(SP) // pointer to data in memory
move.l D1,-(SP) // address to access (in PCI I/O address space)
move.l D0,-(SP) // handle
jsr _pci_read_io_byte
add.l #12,SP
rts
/* Not implemented */
_wrapper_read_io_word:
move.l A0,-(SP) // pointer to data in memory
move.l D1,-(SP) // address to access (in PCI I/O address space)
move.l D0,-(SP) // handle
jsr _pci_read_io_word
add.l #12,SP
rts
/* Not implemented */
_wrapper_read_io_longword:
move.l A0,-(SP) // pointer to data in memory
move.l D1,-(SP) // address to access (in PCI I/O address space)
move.l D0,-(SP) // handle
jsr _pci_read_io_longword
add.l #12,SP
rts
/* Not implemented */
_wrapper_fast_read_io_byte:
move.l D1,-(SP) // address to access (in PCI I/O address space)
move.l D0,-(SP) // handle
jsr _pci_read_io_byte
addq.l #8,SP
rts
/* Not implemented */
_wrapper_fast_read_io_word:
move.l D1,-(SP) // address to access (in PCI I/O address space)
move.l D0,-(SP) // handle
jsr _pci_read_io_word
addq.l #8,SP
rts
/* Not implemented */
_wrapper_fast_read_io_longword:
move.l D1,-(SP) // address to access (in PCI I/O address space)
move.l D0,-(SP) // handle
jsr _pci_read_io_longword
addq.l #8,SP
rts
/* Not implemented */
_wrapper_write_io_byte:
move.l D2,-(SP) // data to write
move.l D1,-(SP) // address to access (in PCI I/O address space)
move.l D0,-(SP) // handle
jsr _pci_write_io_byte
add.l #12,SP
rts
/* Not implemented */
_wrapper_write_io_word:
move.l D2,-(SP) // data to write
move.l D1,-(SP) // address to access (in PCI I/O address space)
move.l D0,-(SP) // handle
jsr _pci_write_io_word
add.l #12,SP
rts
/* Not implemented */
_wrapper_write_io_longword:
move.l D2,-(SP) // data to write
move.l D1,-(SP) // address to access (in PCI I/O address space)
move.l D0,-(SP) // handle
jsr _pci_write_io_longword
add.l #12,SP
rts
/* Not implemented */
_wrapper_get_machine_id:
jsr _pci_get_machine_id
rts
/* Not implemented */
_wrapper_get_pagesize:
jsr _pci_get_pagesize
rts
/* Not implemented */
_wrapper_virt_to_bus:
move.l A0,-(SP) // ptr
move.l D1,-(SP) // address in virtual CPU space
move.l D0,-(SP) // handle
jsr _pci_virt_to_bus
add.l #12,SP
rts
/* Not implemented */
_wrapper_bus_to_virt:
move.l A0,-(SP) // ptr
move.l D1,-(SP) // PCI bus address
move.l D0,-(SP) // handle
jsr _pci_bus_to_virt
add.l #12,SP
rts
/* Not implemented */
_wrapper_virt_to_phys:
move.l A0,-(SP) // ptr
move.l D0,-(SP) // address in virtual CPU space
jsr _pci_virt_to_phys
addq.l #8,SP
rts
/* Not implemented */
_wrapper_phys_to_virt:
move.l A0,-(SP) // ptr
move.l D0,-(SP) // physical CPU address
jsr _pci_phys_to_virt
addq.l #8,SP
rts

88
radeon/radeon_cursor.c
View File

@@ -44,11 +44,13 @@
*
*/
#include "bas_types.h"
#include "bas_printf.h"
#include "radeonfb.h"
#define DBG_RADEON
#ifdef DBG_RADEON
#define dbg(format, arg...) do { xprintf("DEBUG: " format, ##arg); } while (0)
#define dbg(format, arg...) do { xprintf("DEBUG %s(): " format, __FUNCTION__, ##arg); } while (0)
#else
#define dbg(format, arg...) do { ; } while (0)
#endif /* DBG_RADEON */
@@ -66,20 +68,20 @@
#define CURSOR_SWAPPING_DECL_MMIO
#define CURSOR_SWAPPING_DECL unsigned long __surface_cntl=0;
#define CURSOR_SWAPPING_START() \
if(rinfo->big_endian) \
if (rinfo->big_endian) \
OUTREG(SURFACE_CNTL, \
((__surface_cntl = INREG(SURFACE_CNTL)) | \
NONSURF_AP0_SWP_32BPP) & \
~NONSURF_AP0_SWP_16BPP);
#define CURSOR_SWAPPING_END() \
if(rinfo->big_endian) \
if (rinfo->big_endian) \
(OUTREG(SURFACE_CNTL, __surface_cntl));
/* Set cursor foreground and background colors */
void radeon_set_cursor_colors(struct fb_info *info, int bg, int fg)
{
struct radeonfb_info *rinfo = info->par;
unsigned long *pixels = (unsigned long *)((unsigned long) rinfo->fb_base+rinfo->cursor_start);
unsigned long *pixels = (unsigned long *)((unsigned long) rinfo->fb_base + rinfo->cursor_start);
int pixel, i;
CURSOR_SWAPPING_DECL_MMIO
CURSOR_SWAPPING_DECL
@@ -88,15 +90,17 @@ void radeon_set_cursor_colors(struct fb_info *info, int bg, int fg)
fg |= 0xff000000;
bg |= 0xff000000;
/* Don't recolour the image if we don't have to. */
if(fg == rinfo->cursor_fg && bg == rinfo->cursor_bg)
if (fg == rinfo->cursor_fg && bg == rinfo->cursor_bg)
return;
CURSOR_SWAPPING_START();
/* Note: We assume that the pixels are either fully opaque or fully
/*
* Note: We assume that the pixels are either fully opaque or fully
* transparent, so we won't premultiply them, and we can just
* check for non-zero pixel values; those are either fg or bg
*/
for(i = 0; i < CURSOR_WIDTH * CURSOR_HEIGHT; i++, pixels++)
if((pixel = *pixels))
for (i = 0; i < CURSOR_WIDTH * CURSOR_HEIGHT; i++, pixels++)
if ((pixel = *pixels))
*pixels = (pixel == rinfo->cursor_fg) ? fg : bg;
CURSOR_SWAPPING_END();
rinfo->cursor_fg = fg;
@@ -112,27 +116,30 @@ void radeon_set_cursor_position(struct fb_info *info, int x, int y)
struct fb_var_screeninfo *mode = &info->var;
int xorigin = 0;
int yorigin = 0;
if(mode->vmode & FB_VMODE_DOUBLE)
if (mode->vmode & FB_VMODE_DOUBLE)
y <<= 1;
if(x < 0)
if (x < 0)
xorigin = 1 - x;
if(y < 0)
if (y < 0)
yorigin = 1 - y;
// DPRINTVALHEX("radeonfb: RADEONSetCursorPosition: cursor_start ",rinfo->cursor_start);
// DPRINTVAL(" x ",x);
// DPRINTVAL(" y ",y);
// DPRINT("\r\n");
OUTREG(CUR_HORZ_VERT_OFF, (CUR_LOCK | (xorigin << 16) | yorigin));
OUTREG(CUR_HORZ_VERT_POSN, (CUR_LOCK | ((xorigin ? 0 : x) << 16) | (yorigin ? 0 : y)));
OUTREG(CUR_OFFSET, rinfo->cursor_start + yorigin * 256);
rinfo->cursor_x = (unsigned long)x;
if(mode->vmode & FB_VMODE_DOUBLE)
rinfo->cursor_y = (unsigned long)y >> 1;
if (mode->vmode & FB_VMODE_DOUBLE)
rinfo->cursor_y = (unsigned long) y >> 1;
else
rinfo->cursor_y = (unsigned long)y;
rinfo->cursor_y = (unsigned long) y;
}
/* Copy cursor image from `image' to video memory. RADEONSetCursorPosition
/*
* Copy cursor image from `image' to video memory. RADEONSetCursorPosition
* will be called after this, so we can ignore xorigin and yorigin.
*/
void radeon_load_cursor_image(struct fb_info *info, unsigned short *mask, unsigned short *data, int zoom)
@@ -143,11 +150,14 @@ void radeon_load_cursor_image(struct fb_info *info, unsigned short *mask, unsign
unsigned short chunk, mchunk;
unsigned long i, j, k;
CURSOR_SWAPPING_DECL
// DPRINTVALHEX("radeonfb: RADEONLoadCursorImage: cursor_start ",rinfo->cursor_start);
// DPRINT("\r\n");
// DPRINT("\r\n");
save = INREG(CRTC_GEN_CNTL) & ~(unsigned long) (3 << 20);
save |= (unsigned long) (2 << 20);
OUTREG(CRTC_GEN_CNTL, save & (unsigned long)~CRTC_CUR_EN);
/*
* Convert the bitmap to ARGB32.
*/
@@ -157,22 +167,22 @@ void radeon_load_cursor_image(struct fb_info *info, unsigned short *mask, unsign
{
case 1:
default:
for(i = 0; i < CURSOR_HEIGHT; i++)
for (i = 0; i < CURSOR_HEIGHT; i++)
{
if(i < 16)
if (i < 16)
{
mchunk = *mask++;
chunk = *data++;
}
else
mchunk = chunk = 0;
for(j = 0; j < CURSOR_WIDTH / ARGB_PER_CHUNK; j++)
for (j = 0; j < CURSOR_WIDTH / ARGB_PER_CHUNK; j++)
{
for(k = 0; k < ARGB_PER_CHUNK; k++, chunk <<= 1, mchunk <<= 1)
for (k = 0; k < ARGB_PER_CHUNK; k++, chunk <<= 1, mchunk <<= 1)
{
if(mchunk & 0x8000)
if (mchunk & 0x8000)
{
if(chunk & 0x8000)
if (chunk & 0x8000)
*d++ = 0xff000000; /* Black, fully opaque. */
else
*d++ = 0xffffffff; /* White, fully opaque. */
@@ -184,13 +194,13 @@ void radeon_load_cursor_image(struct fb_info *info, unsigned short *mask, unsign
}
break;
case 2:
for(i = 0; i < CURSOR_HEIGHT; i++)
for (i = 0; i < CURSOR_HEIGHT; i++)
{
if(i < 16*2)
if (i < 16*2)
{
mchunk = *mask;
chunk = *data;
if((i & 1) == 1)
if ((i & 1) == 1)
{
mask++;
data++;
@@ -198,13 +208,13 @@ void radeon_load_cursor_image(struct fb_info *info, unsigned short *mask, unsign
}
else
mchunk = chunk = 0;
for(j = 0; j < CURSOR_WIDTH / ARGB_PER_CHUNK; j+=2)
for (j = 0; j < CURSOR_WIDTH / ARGB_PER_CHUNK; j+=2)
{
for(k = 0; k < ARGB_PER_CHUNK; k++, chunk <<= 1, mchunk <<= 1)
for (k = 0; k < ARGB_PER_CHUNK; k++, chunk <<= 1, mchunk <<= 1)
{
if(mchunk & 0x8000)
if (mchunk & 0x8000)
{
if(chunk & 0x8000)
if (chunk & 0x8000)
{
*d++ = 0xff000000; /* Black, fully opaque. */
*d++ = 0xff000000;
@@ -225,13 +235,13 @@ void radeon_load_cursor_image(struct fb_info *info, unsigned short *mask, unsign
}
break;
case 4:
for(i = 0; i < CURSOR_HEIGHT; i++)
for (i = 0; i < CURSOR_HEIGHT; i++)
{
if(i < 16*4)
if (i < 16 * 4)
{
mchunk = *mask;
chunk = *data;
if((i & 3) == 3)
if ((i & 3) == 3)
{
mask++;
data++;
@@ -239,13 +249,13 @@ void radeon_load_cursor_image(struct fb_info *info, unsigned short *mask, unsign
}
else
mchunk = chunk = 0;
for(j = 0; j < CURSOR_WIDTH / ARGB_PER_CHUNK; j+=4)
for (j = 0; j < CURSOR_WIDTH / ARGB_PER_CHUNK; j+=4)
{
for(k = 0; k < ARGB_PER_CHUNK; k++, chunk <<= 1, mchunk <<= 1)
for (k = 0; k < ARGB_PER_CHUNK; k++, chunk <<= 1, mchunk <<= 1)
{
if(mchunk & 0x8000)
if (mchunk & 0x8000)
{
if(chunk & 0x8000)
if (chunk & 0x8000)
{
*d++ = 0xff000000; /* Black, fully opaque. */
*d++ = 0xff000000;
@@ -282,6 +292,7 @@ void radeon_load_cursor_image(struct fb_info *info, unsigned short *mask, unsign
void radeon_hide_cursor(struct fb_info *info)
{
struct radeonfb_info *rinfo = info->par;
// DPRINT("radeonfb: RADEONHideCursor\r\n");
OUTREGP(CRTC_GEN_CNTL, 0, ~CRTC_CUR_EN);
rinfo->cursor_show = 0;
@@ -291,6 +302,7 @@ void radeon_hide_cursor(struct fb_info *info)
void radeon_show_cursor(struct fb_info *info)
{
struct radeonfb_info *rinfo = info->par;
// DPRINT("radeonfb: RADEONShowCursor\r\n");
OUTREGP(CRTC_GEN_CNTL, CRTC_CUR_EN, ~CRTC_CUR_EN);
rinfo->cursor_show = 1;
@@ -303,9 +315,9 @@ long radeon_cursor_init(struct fb_info *info)
int size_bytes = CURSOR_WIDTH * 4 * CURSOR_HEIGHT;
unsigned long fbarea = offscreen_alloc(rinfo->info, size_bytes + 256);
dbg("radeonfb: %s: fbarea: %p\r\n", __FUNCTION__, fbarea);
dbg("radeonfb: %s: fbarea: %p\r\n", fbarea);
if(!fbarea)
if (!fbarea)
rinfo->cursor_start = 0;
else
{

1317
sys/exceptions.S
View File

File diff suppressed because it is too large Load Diff

214
sys/init_fpga.c
View File

@@ -33,40 +33,49 @@
#define FPGA_DATA0 (1 << 3)
#define FPGA_CONF_DONE (1 << 5)
extern uint8_t _FPGA_FLASH_DATA[];
#define FPGA_FLASH_DATA &_FPGA_FLASH_DATA[0]
extern uint8_t _FPGA_FLASH_DATA_SIZE[];
#define FPGA_FLASH_DATA_SIZE ((uint32_t) &_FPGA_FLASH_DATA_SIZE[0])
extern uint8_t _FPGA_CONFIG[];
#define FPGA_FLASH_DATA &_FPGA_CONFIG[0]
extern uint8_t _FPGA_CONFIG_SIZE[];
#define FPGA_FLASH_DATA_SIZE ((uint32_t) &_FPGA_CONFIG_SIZE[0])
/*
* flag located in processor SRAM1 that indicates that the FPGA configuration has
* been loaded through the onboard JTAG interface.
* init_fpga() will honour this and not overwrite config.
*/
extern int32_t _FPGA_JTAG_LOADED;
extern int32_t _FPGA_JTAG_VALID;
#define VALID_JTAG 0xaffeaffe
void config_gpio_for_fpga_config(void)
{
#if defined(MACHINE_FIREBEE)
/*
* Configure GPIO FEC1L port directions (needed to load FPGA configuration)
*/
MCF_GPIO_PDDR_FEC1L = 0 | /* bit 7 = input */
0 | /* bit 6 = input */
0 | /* bit 5 = input */
MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4 | /* bit 4 = LED => output */
MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L3 | /* bit 3 = PRG_DQ0 => output */
MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L2 | /* bit 2 = FPGA_CONFIG => output */
MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L1 | /* bit 1 = PRG_CLK (FPGA) => output */
0; /* bit 0 => input */
/*
* Configure GPIO FEC1L port directions (needed to load FPGA configuration)
*/
MCF_GPIO_PDDR_FEC1L = 0 | /* bit 7 = input */
0 | /* bit 6 = input */
0 | /* bit 5 = input */
MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4 | /* bit 4 = LED => output */
MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L3 | /* bit 3 = PRG_DQ0 => output */
MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L2 | /* bit 2 = FPGA_CONFIG => output */
MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L1 | /* bit 1 = PRG_CLK (FPGA) => output */
0; /* bit 0 => input */
#endif /* MACHINE_FIREBEE */
}
void config_gpio_for_jtag_config(void)
{
/*
* configure FEC1L port directions to enable external JTAG configuration download to FPGA
*/
MCF_GPIO_PDDR_FEC1L = 0 |
MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4; /* bit 4 = LED => output */
/* all other bits = input */
/*
* unfortunately, the GPIO module cannot trigger interrupts. That means FPGA_CONFIG needs to be polled to detect
* external FPGA (re)configuration and reset the system in that case. Could be done from the OS as well...
*/
/*
* configure FEC1L port directions to enable external JTAG configuration download to FPGA
*/
MCF_GPIO_PDDR_FEC1L = 0 |
MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4; /* bit 4 = LED => output */
/* all other bits = input */
/*
* unfortunately, the GPIO module cannot trigger interrupts. That means FPGA_CONFIG needs to be polled to detect
* external FPGA (re)configuration and reset the system in that case. Could be done from the OS as well...
*/
}
/*
@@ -74,88 +83,101 @@ void config_gpio_for_jtag_config(void)
*/
bool init_fpga(void)
{
uint8_t *fpga_data;
volatile int32_t time, start, end;
int i;
uint8_t *fpga_data;
volatile int32_t time, start, end;
int i;
xprintf("FPGA load config... ");
start = MCF_SLT0_SCNT;
xprintf("FPGA load config...\r\n");
xprintf("_FPGA_JTAG_LOADED = %x, _FPGA_JTAG_VALID = %x)\r\n", _FPGA_JTAG_LOADED, _FPGA_JTAG_VALID);
if (_FPGA_JTAG_LOADED == 1 && _FPGA_JTAG_VALID == VALID_JTAG)
{
xprintf("detected _FPGA_JTAG_LOADED flag. Not overwriting FPGA config.\r\n");
config_gpio_for_fpga_config();
MCF_GPIO_PODR_FEC1L &= ~FPGA_CLOCK; /* FPGA clock => low */
/* reset the flag so that next boot will load config again from flash */
_FPGA_JTAG_LOADED = 0;
_FPGA_JTAG_VALID = 0;
/* pulling FPGA_CONFIG to low resets the FPGA */
MCF_GPIO_PODR_FEC1L &= ~FPGA_CONFIG; /* FPGA config => low */
wait(10); /* give it some time to do its reset stuff */
return true;
}
start = MCF_SLT0_SCNT;
while ((MCF_GPIO_PPDSDR_FEC1L & FPGA_STATUS) && (MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE));
config_gpio_for_fpga_config();
MCF_GPIO_PODR_FEC1L &= ~FPGA_CLOCK; /* FPGA clock => low */
MCF_GPIO_PODR_FEC1L |= FPGA_CONFIG; /* pull FPGA_CONFIG high to start config cycle */
while (!(MCF_GPIO_PPDSDR_FEC1L & FPGA_STATUS)); /* wait until status becomes high */
/* pulling FPGA_CONFIG to low resets the FPGA */
MCF_GPIO_PODR_FEC1L &= ~FPGA_CONFIG; /* FPGA config => low */
wait(10); /* give it some time to do its reset stuff */
/*
* excerpt from an Altera configuration manual:
*
* The low-to-high transition of nCONFIG on the FPGA begins the configuration cycle. The
* configuration cycle consists of 3 stages<65>reset, configuration, and initialization.
* While nCONFIG is low, the device is in reset. When the device comes out of reset,
* nCONFIG must be at a logic high level in order for the device to release the open-drain
* nSTATUS pin. After nSTATUS is released, it is pulled high by a pull-up resistor and the FPGA
* is ready to receive configuration data. Before and during configuration, all user I/O pins
* are tri-stated. Stratix series, Arria series, and Cyclone series have weak pull-up resistors
* on the I/O pins which are on, before and during configuration.
*
* To begin configuration, nCONFIG and nSTATUS must be at a logic high level. You can delay
* configuration by holding the nCONFIG low. The device receives configuration data on its
* DATA0 pins. Configuration data is latched into the FPGA on the rising edge of DCLK. After
* the FPGA has received all configuration data successfully, it releases the CONF_DONE pin,
* which is pulled high by a pull-up resistor. A low to high transition on CONF_DONE indicates
* configuration is complete and initialization of the device can begin.
*/
while ((MCF_GPIO_PPDSDR_FEC1L & FPGA_STATUS) && (MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE));
const uint8_t *fpga_flash_data_end = FPGA_FLASH_DATA + FPGA_FLASH_DATA_SIZE;
MCF_GPIO_PODR_FEC1L |= FPGA_CONFIG; /* pull FPGA_CONFIG high to start config cycle */
while (!(MCF_GPIO_PPDSDR_FEC1L & FPGA_STATUS))
; /* wait until status becomes high */
fpga_data = (uint8_t *) FPGA_FLASH_DATA;
do
{
uint8_t value = *fpga_data++;
for (i = 0; i < 8; i++, value >>= 1)
{
/*
* excerpt from an Altera configuration manual:
*
* The low-to-high transition of nCONFIG on the FPGA begins the configuration cycle. The
* configuration cycle consists of 3 stages<65>reset, configuration, and initialization.
* While nCONFIG is low, the device is in reset. When the device comes out of reset,
* nCONFIG must be at a logic high level in order for the device to release the open-drain
* nSTATUS pin. After nSTATUS is released, it is pulled high by a pull-up resistor and the FPGA
* is ready to receive configuration data. Before and during configuration, all user I/O pins
* are tri-stated. Stratix series, Arria series, and Cyclone series have weak pull-up resistors
* on the I/O pins which are on, before and during configuration.
*
* To begin configuration, nCONFIG and nSTATUS must be at a logic high level. You can delay
* configuration by holding the nCONFIG low. The device receives configuration data on its
* DATA0 pins. Configuration data is latched into the FPGA on the rising edge of DCLK. After
* the FPGA has received all configuration data successfully, it releases the CONF_DONE pin,
* which is pulled high by a pull-up resistor. A low to high transition on CONF_DONE indicates
* configuration is complete and initialization of the device can begin.
*/
if (value & 1)
{
/* bit set -> toggle DATA0 to high */
MCF_GPIO_PODR_FEC1L |= FPGA_DATA0;
}
else
{
/* bit is cleared -> toggle DATA0 to low */
MCF_GPIO_PODR_FEC1L &= ~FPGA_DATA0;
}
/* toggle DCLK -> FPGA reads the bit */
MCF_GPIO_PODR_FEC1L |= FPGA_CLOCK;
MCF_GPIO_PODR_FEC1L &= ~FPGA_CLOCK;
}
} while ((!(MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE)) && (fpga_data < fpga_flash_data_end));
const uint8_t *fpga_flash_data_end = FPGA_FLASH_DATA + FPGA_FLASH_DATA_SIZE;
if (fpga_data < fpga_flash_data_end)
{
fpga_data = (uint8_t *) FPGA_FLASH_DATA;
do
{
uint8_t value = *fpga_data++;
for (i = 0; i < 8; i++, value >>= 1)
{
if (value & 1)
{
/* bit set -> toggle DATA0 to high */
MCF_GPIO_PODR_FEC1L |= FPGA_DATA0;
}
else
{
/* bit is cleared -> toggle DATA0 to low */
MCF_GPIO_PODR_FEC1L &= ~FPGA_DATA0;
}
/* toggle DCLK -> FPGA reads the bit */
MCF_GPIO_PODR_FEC1L |= FPGA_CLOCK;
MCF_GPIO_PODR_FEC1L &= ~FPGA_CLOCK;
}
} while ((!(MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE)) && (fpga_data < fpga_flash_data_end));
if (fpga_data < fpga_flash_data_end)
{
#ifdef _NOT_USED_
while (fpga_data++ < fpga_flash_data_end)
{
/* toggle a little more since it's fun ;) */
MCF_GPIO_PODR_FEC1L |= FPGA_CLOCK;
MCF_GPIO_PODR_FEC1L &= ~FPGA_CLOCK;
}
while (fpga_data++ < fpga_flash_data_end)
{
/* toggle a little more since it's fun ;) */
MCF_GPIO_PODR_FEC1L |= FPGA_CLOCK;
MCF_GPIO_PODR_FEC1L &= ~FPGA_CLOCK;
}
#endif /* _NOT_USED_ */
end = MCF_SLT0_SCNT;
time = (start - end) / (SYSCLK / 1000) / 1000;
end = MCF_SLT0_SCNT;
time = (start - end) / (SYSCLK / 1000) / 1000;
xprintf("finished (took %f seconds).\r\n", time / 1000.0);
config_gpio_for_jtag_config();
return true;
}
xprintf("FAILED!\r\n");
config_gpio_for_jtag_config();
return false;
xprintf("finished (took %f seconds).\r\n", time / 1000.0);
config_gpio_for_jtag_config();
return true;
}
xprintf("FAILED!\r\n");
config_gpio_for_jtag_config();
return false;
}

4
sys/mmu.c
View File

@@ -206,8 +206,8 @@ void mmu_init(void)
ACR_S(ACR_S_ALL) | /* match addresses in user and supervisor mode */
ACR_E(1) | /* enable ACR */
#if defined(MACHINE_FIREBEE)
ACR_ADMSK(0x3f) | /* cover 1GB area from 0xc0000000 to 0xffffffff */
ACR_BA(0xc0000000)); /* (equals area from 3 to 4 GB */
ACR_ADMSK(0x7f) | /* cover 2GB area from 0x80000000 to 0xffffffff */
ACR_BA(0x80000000)); /* (equals area from 3 to 4 GB */
#elif defined(MACHINE_M5484LITE)
ACR_ADMSK(0x7f) | /* cover 2 GB area from 0x80000000 to 0xffffffff */
ACR_BA(0x80000000));

1496
sys/sysinit.c
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File diff suppressed because it is too large Load Diff

97
tos/jtagwait/Makefile Executable file
View File

@@ -0,0 +1,97 @@
CROSS=Y
CROSSBINDIR_IS_Y=m68k-atari-mint-
CROSSBINDIR_IS_N=
CROSSBINDIR=$(CROSSBINDIR_IS_$(CROSS))
UNAME := $(shell uname)
ifeq ($(CROSS), Y)
ifeq ($(UNAME),Linux)
PREFIX=m68k-atari-mint
HATARI=hatari
else
PREFIX=m68k-atari-mint
HATARI=/usr/local/bin/hatari
endif
else
PREFIX=/usr
endif
DEPEND=depend
TOPDIR = ../..
INCLUDE=-I$(TOPDIR)/../libcmini/include -nostdlib
LIBS=-lcmini -nostdlib -lgcc
CC=$(PREFIX)/bin/gcc
CC=$(CROSSBINDIR)gcc
STRIP=$(CROSSBINDIR)strip
STACK=$(CROSSBINDIR)stack
APP=jtagwait.prg
TEST_APP=$(APP)
CFLAGS=\
-Os\
-g\
-Wl,-Map,mapfile\
-Wall
SRCDIR=sources
INCDIR=include
INCLUDE+=-I$(INCDIR)
CSRCS=\
$(SRCDIR)/jtagwait.c
ASRCS=
COBJS=$(patsubst $(SRCDIR)/%.o,%.o,$(patsubst %.c,%.o,$(CSRCS)))
AOBJS=$(patsubst $(SRCDIR)/%.o,%.o,$(patsubst %.S,%.o,$(ASRCS)))
OBJS=$(COBJS) $(AOBJS)
TRGTDIRS=./m5475 ./m5475/mshort
OBJDIRS=$(patsubst %,%/objs,$(TRGTDIRS))
#
# multilib flags. These must match m68k-atari-mint-gcc -print-multi-lib output
#
m5475/$(APP):CFLAGS += -mcpu=5475
m5475/mshort/$(APP): CFLAGS += -mcpu=5475 -mshort
all:$(patsubst %,%/$(APP),$(TRGTDIRS))
#
# generate pattern rules for multilib object files.
#
define CC_TEMPLATE
$(1)/objs/%.o:$(SRCDIR)/%.c
$(CC) $$(CFLAGS) $(INCLUDE) -c $$< -o $$@
$(1)/objs/%.o:$(SRCDIR)/%.S
$(CC) $$(CFLAGS) $(INCLUDE) -c $$< -o $$@
$(1)_OBJS=$(patsubst %,$(1)/objs/%,$(OBJS))
$(1)/$(APP): $$($(1)_OBJS)
$(CC) $$(CFLAGS) -o $$@ $(TOPDIR)/../libcmini/$(1)/startup.o $$($(1)_OBJS) -L$(TOPDIR)/../libcmini/$(1) $(LIBS)
$(STRIP) $$@
endef
$(foreach DIR,$(TRGTDIRS),$(eval $(call CC_TEMPLATE,$(DIR))))
$(DEPEND): $(ASRCS) $(CSRCS)
-rm -f $(DEPEND)
for d in $(TRGTDIRS);\
do $(CC) $(CFLAGS) $(INCLUDE) -M $(ASRCS) $(CSRCS) | sed -e "s#^\(.*\).o:#$$d/objs/\1.o:#" >> $(DEPEND); \
done
clean:
@rm -f $(patsubst %,%/objs/*.o,$(TRGTDIRS)) $(patsubst %,%/$(APP),$(TRGTDIRS))
@rm -f $(DEPEND) mapfile
.PHONY: printvars
printvars:
@$(foreach V,$(.VARIABLES), $(if $(filter-out environment% default automatic, $(origin $V)),$(warning $V=$($V))))
ifneq (clean,$(MAKECMDGOALS))
-include $(DEPEND)
endif

125
tos/jtagwait/include/driver_vec.h Normal file
View File

@@ -0,0 +1,125 @@
/*
* driver_vec.h
*
* Interface for exposure of BaS drivers to the OS
*
* This file is part of BaS_gcc.
*
* BaS_gcc is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* BaS_gcc is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
*
* Created on: 24.10.2013
* Author: Markus Fröschle
*/
#ifndef _DRIVER_VEC_H_
#define _DRIVER_VEC_H_
enum driver_type
{
END_OF_DRIVERS, /* marks end of driver list */
BLOCKDEV_DRIVER,
CHARDEV_DRIVER,
VIDEO_DRIVER,
XHDI_DRIVER,
MCD_DRIVER,
};
struct generic_driver_interface
{
uint32_t (*init)(void);
uint32_t (*read)(void *buf, size_t count);
uint32_t (*write)(const void *buf, size_t count);
uint32_t (*ioctl)(uint32_t request, ...);
};
/* Chained buffer descriptor */
typedef volatile struct MCD_bufDesc_struct MCD_bufDesc;
struct MCD_bufDesc_struct {
uint32_t flags; /* flags describing the DMA */
uint32_t csumResult; /* checksum from checksumming performed since last checksum reset */
int8_t *srcAddr; /* the address to move data from */
int8_t *destAddr; /* the address to move data to */
int8_t *lastDestAddr; /* the last address written to */
uint32_t dmaSize; /* the number of bytes to transfer independent of the transfer size */
MCD_bufDesc *next; /* next buffer descriptor in chain */
uint32_t info; /* private information about this descriptor; DMA does not affect it */
};
/* Progress Query struct */
typedef volatile struct MCD_XferProg_struct {
int8_t *lastSrcAddr; /* the most-recent or last, post-increment source address */
int8_t *lastDestAddr; /* the most-recent or last, post-increment destination address */
uint32_t dmaSize; /* the amount of data transferred for the current buffer */
MCD_bufDesc *currBufDesc;/* pointer to the current buffer descriptor being DMAed */
} MCD_XferProg;
struct dma_driver_interface
{
int32_t version;
int32_t magic;
int32_t (*dma_set_initiator)(int initiator);
uint32_t (*dma_get_initiator)(int requestor);
void (*dma_free_initiator)(int requestor);
int32_t (*dma_set_channel)(int requestor, void (*handler)(void));
int (*dma_get_channel)(int requestor);
void (*dma_free_channel)(int requestor);
void (*dma_clear_channel)(int channel);
int (*MCD_startDma)(int channel, int8_t *srcAddr, int16_t srcIncr, int8_t *destAddr, int16_t destIncr,
uint32_t dmaSize, uint32_t xferSize, uint32_t initiator, int32_t priority, uint32_t flags,
uint32_t funcDesc);
int (*MCD_dmaStatus)(int channel);
int (*MCD_XferProgrQuery)(int channel, MCD_XferProg *progRep);
int (*MCD_killDma)(int channel);
int (*MCD_continDma)(int channel);
int (*MCD_pauseDma)(int channel);
int (*MCD_resumeDma)(int channel);
int (*MCD_csumQuery)(int channel, uint32_t *csum);
void *(*dma_malloc)(long amount);
int (*dma_free)(void *addr);
};
struct xhdi_driver_interface
{
uint32_t (*xhdivec)();
};
union interface
{
struct generic_driver_interface *gdi;
struct xhdi_driver_interface *xhdi;
struct dma_driver_interface *dma;
};
struct generic_interface
{
enum driver_type type;
char name[16];
char description[64];
int version;
int revision;
union interface interface;
};
struct driver_table
{
uint32_t bas_version;
uint32_t bas_revision;
uint32_t (*remove_handler)(); /* calling this will disable the BaS' hook into trap #0 */
struct generic_interface *interfaces;
};
#endif /* _DRIVER_VEC_H_ */

1
tos/jtagwait/jtagwait.config Normal file
View File

@@ -0,0 +1 @@
// ADD PREDEFINED MACROS HERE!

1
tos/jtagwait/jtagwait.creator Normal file
View File

@@ -0,0 +1 @@
[General]

186
tos/jtagwait/jtagwait.creator.user Normal file
View File

@@ -0,0 +1,186 @@
<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE QtCreatorProject>
<!-- Written by QtCreator 3.0.1, 2014-08-04T18:51:58. -->
<qtcreator>
<data>
<variable>ProjectExplorer.Project.ActiveTarget</variable>
<value type="int">0</value>
</data>
<data>
<variable>ProjectExplorer.Project.EditorSettings</variable>
<valuemap type="QVariantMap">
<value type="bool" key="EditorConfiguration.AutoIndent">true</value>
<value type="bool" key="EditorConfiguration.AutoSpacesForTabs">false</value>
<value type="bool" key="EditorConfiguration.CamelCaseNavigation">true</value>
<valuemap type="QVariantMap" key="EditorConfiguration.CodeStyle.0">
<value type="QString" key="language">Cpp</value>
<valuemap type="QVariantMap" key="value">
<value type="QByteArray" key="CurrentPreferences">CppGlobal</value>
</valuemap>
</valuemap>
<valuemap type="QVariantMap" key="EditorConfiguration.CodeStyle.1">
<value type="QString" key="language">QmlJS</value>
<valuemap type="QVariantMap" key="value">
<value type="QByteArray" key="CurrentPreferences">QmlJSGlobal</value>
</valuemap>
</valuemap>
<value type="int" key="EditorConfiguration.CodeStyle.Count">2</value>
<value type="QByteArray" key="EditorConfiguration.Codec">UTF-8</value>
<value type="bool" key="EditorConfiguration.ConstrainTooltips">false</value>
<value type="int" key="EditorConfiguration.IndentSize">4</value>
<value type="bool" key="EditorConfiguration.KeyboardTooltips">false</value>
<value type="bool" key="EditorConfiguration.MouseNavigation">true</value>
<value type="int" key="EditorConfiguration.PaddingMode">1</value>
<value type="bool" key="EditorConfiguration.ScrollWheelZooming">true</value>
<value type="int" key="EditorConfiguration.SmartBackspaceBehavior">0</value>
<value type="bool" key="EditorConfiguration.SpacesForTabs">true</value>
<value type="int" key="EditorConfiguration.TabKeyBehavior">0</value>
<value type="int" key="EditorConfiguration.TabSize">8</value>
<value type="bool" key="EditorConfiguration.UseGlobal">true</value>
<value type="int" key="EditorConfiguration.Utf8BomBehavior">1</value>
<value type="bool" key="EditorConfiguration.addFinalNewLine">true</value>
<value type="bool" key="EditorConfiguration.cleanIndentation">true</value>
<value type="bool" key="EditorConfiguration.cleanWhitespace">true</value>
<value type="bool" key="EditorConfiguration.inEntireDocument">true</value>
</valuemap>
</data>
<data>
<variable>ProjectExplorer.Project.PluginSettings</variable>
<valuemap type="QVariantMap"/>
</data>
<data>
<variable>ProjectExplorer.Project.Target.0</variable>
<valuemap type="QVariantMap">
<value type="QString" key="ProjectExplorer.ProjectConfiguration.DefaultDisplayName">Desktop</value>
<value type="QString" key="ProjectExplorer.ProjectConfiguration.DisplayName">Desktop</value>
<value type="QString" key="ProjectExplorer.ProjectConfiguration.Id">{8a828d48-5359-4872-acb6-81070c6b7c12}</value>
<value type="int" key="ProjectExplorer.Target.ActiveBuildConfiguration">0</value>
<value type="int" key="ProjectExplorer.Target.ActiveDeployConfiguration">0</value>
<value type="int" key="ProjectExplorer.Target.ActiveRunConfiguration">0</value>
<valuemap type="QVariantMap" key="ProjectExplorer.Target.BuildConfiguration.0">
<value type="QString" key="ProjectExplorer.BuildConfiguration.BuildDirectory">/home/mfro/Dokumente/Development/workspace/jtagwait</value>
<valuemap type="QVariantMap" key="ProjectExplorer.BuildConfiguration.BuildStepList.0">
<valuemap type="QVariantMap" key="ProjectExplorer.BuildStepList.Step.0">
<valuelist type="QVariantList" key="GenericProjectManager.GenericMakeStep.BuildTargets">
<value type="QString">all</value>
</valuelist>
<value type="bool" key="GenericProjectManager.GenericMakeStep.Clean">false</value>
<value type="QString" key="GenericProjectManager.GenericMakeStep.MakeArguments"></value>
<value type="QString" key="GenericProjectManager.GenericMakeStep.MakeCommand"></value>
<value type="bool" key="ProjectExplorer.BuildStep.Enabled">true</value>
<value type="QString" key="ProjectExplorer.ProjectConfiguration.DefaultDisplayName">Make</value>
<value type="QString" key="ProjectExplorer.ProjectConfiguration.DisplayName"></value>
<value type="QString" key="ProjectExplorer.ProjectConfiguration.Id">GenericProjectManager.GenericMakeStep</value>
</valuemap>
<value type="int" key="ProjectExplorer.BuildStepList.StepsCount">1</value>
<value type="QString" key="ProjectExplorer.ProjectConfiguration.DefaultDisplayName">Build</value>
<value type="QString" key="ProjectExplorer.ProjectConfiguration.DisplayName"></value>
<value type="QString" key="ProjectExplorer.ProjectConfiguration.Id">ProjectExplorer.BuildSteps.Build</value>
</valuemap>
<valuemap type="QVariantMap" key="ProjectExplorer.BuildConfiguration.BuildStepList.1">
<valuemap type="QVariantMap" key="ProjectExplorer.BuildStepList.Step.0">
<valuelist type="QVariantList" key="GenericProjectManager.GenericMakeStep.BuildTargets">
<value type="QString">clean</value>
</valuelist>
<value type="bool" key="GenericProjectManager.GenericMakeStep.Clean">true</value>
<value type="QString" key="GenericProjectManager.GenericMakeStep.MakeArguments"></value>
<value type="QString" key="GenericProjectManager.GenericMakeStep.MakeCommand"></value>
<value type="bool" key="ProjectExplorer.BuildStep.Enabled">true</value>
<value type="QString" key="ProjectExplorer.ProjectConfiguration.DefaultDisplayName">Make</value>
<value type="QString" key="ProjectExplorer.ProjectConfiguration.DisplayName"></value>
<value type="QString" key="ProjectExplorer.ProjectConfiguration.Id">GenericProjectManager.GenericMakeStep</value>
</valuemap>
<value type="int" key="ProjectExplorer.BuildStepList.StepsCount">1</value>
<value type="QString" key="ProjectExplorer.ProjectConfiguration.DefaultDisplayName">Clean</value>
<value type="QString" key="ProjectExplorer.ProjectConfiguration.DisplayName"></value>
<value type="QString" key="ProjectExplorer.ProjectConfiguration.Id">ProjectExplorer.BuildSteps.Clean</value>
</valuemap>
<value type="int" key="ProjectExplorer.BuildConfiguration.BuildStepListCount">2</value>
<value type="bool" key="ProjectExplorer.BuildConfiguration.ClearSystemEnvironment">false</value>
<valuelist type="QVariantList" key="ProjectExplorer.BuildConfiguration.UserEnvironmentChanges"/>
<value type="QString" key="ProjectExplorer.ProjectConfiguration.DefaultDisplayName">Default</value>
<value type="QString" key="ProjectExplorer.ProjectConfiguration.DisplayName">Default</value>
<value type="QString" key="ProjectExplorer.ProjectConfiguration.Id">GenericProjectManager.GenericBuildConfiguration</value>
</valuemap>
<value type="int" key="ProjectExplorer.Target.BuildConfigurationCount">1</value>
<valuemap type="QVariantMap" key="ProjectExplorer.Target.DeployConfiguration.0">
<valuemap type="QVariantMap" key="ProjectExplorer.BuildConfiguration.BuildStepList.0">
<value type="int" key="ProjectExplorer.BuildStepList.StepsCount">0</value>
<value type="QString" key="ProjectExplorer.ProjectConfiguration.DefaultDisplayName">Deploy</value>
<value type="QString" key="ProjectExplorer.ProjectConfiguration.DisplayName"></value>
<value type="QString" key="ProjectExplorer.ProjectConfiguration.Id">ProjectExplorer.BuildSteps.Deploy</value>
</valuemap>
<value type="int" key="ProjectExplorer.BuildConfiguration.BuildStepListCount">1</value>
<value type="QString" key="ProjectExplorer.ProjectConfiguration.DefaultDisplayName">Deploy locally</value>
<value type="QString" key="ProjectExplorer.ProjectConfiguration.DisplayName"></value>
<value type="QString" key="ProjectExplorer.ProjectConfiguration.Id">ProjectExplorer.DefaultDeployConfiguration</value>
</valuemap>
<value type="int" key="ProjectExplorer.Target.DeployConfigurationCount">1</value>
<valuemap type="QVariantMap" key="ProjectExplorer.Target.PluginSettings"/>
<valuemap type="QVariantMap" key="ProjectExplorer.Target.RunConfiguration.0">
<valuelist type="QVariantList" key="Analyzer.Valgrind.AddedSuppressionFiles"/>
<value type="bool" key="Analyzer.Valgrind.Callgrind.CollectBusEvents">false</value>
<value type="bool" key="Analyzer.Valgrind.Callgrind.CollectSystime">false</value>
<value type="bool" key="Analyzer.Valgrind.Callgrind.EnableBranchSim">false</value>
<value type="bool" key="Analyzer.Valgrind.Callgrind.EnableCacheSim">false</value>
<value type="bool" key="Analyzer.Valgrind.Callgrind.EnableEventToolTips">true</value>
<value type="double" key="Analyzer.Valgrind.Callgrind.MinimumCostRatio">0.01</value>
<value type="double" key="Analyzer.Valgrind.Callgrind.VisualisationMinimumCostRatio">10</value>
<value type="bool" key="Analyzer.Valgrind.FilterExternalIssues">true</value>
<value type="int" key="Analyzer.Valgrind.LeakCheckOnFinish">1</value>
<value type="int" key="Analyzer.Valgrind.NumCallers">25</value>
<valuelist type="QVariantList" key="Analyzer.Valgrind.RemovedSuppressionFiles"/>
<value type="int" key="Analyzer.Valgrind.SelfModifyingCodeDetection">1</value>
<value type="bool" key="Analyzer.Valgrind.Settings.UseGlobalSettings">true</value>
<value type="bool" key="Analyzer.Valgrind.ShowReachable">false</value>
<value type="bool" key="Analyzer.Valgrind.TrackOrigins">true</value>
<value type="QString" key="Analyzer.Valgrind.ValgrindExecutable">valgrind</value>
<valuelist type="QVariantList" key="Analyzer.Valgrind.VisibleErrorKinds">
<value type="int">0</value>
<value type="int">1</value>
<value type="int">2</value>
<value type="int">3</value>
<value type="int">4</value>
<value type="int">5</value>
<value type="int">6</value>
<value type="int">7</value>
<value type="int">8</value>
<value type="int">9</value>
<value type="int">10</value>
<value type="int">11</value>
<value type="int">12</value>
<value type="int">13</value>
<value type="int">14</value>
</valuelist>
<value type="int" key="PE.EnvironmentAspect.Base">2</value>
<valuelist type="QVariantList" key="PE.EnvironmentAspect.Changes"/>
<value type="QString" key="ProjectExplorer.CustomExecutableRunConfiguration.Arguments"></value>
<value type="QString" key="ProjectExplorer.CustomExecutableRunConfiguration.Executable"></value>
<value type="bool" key="ProjectExplorer.CustomExecutableRunConfiguration.UseTerminal">false</value>
<value type="QString" key="ProjectExplorer.CustomExecutableRunConfiguration.WorkingDirectory">%{buildDir}</value>
<value type="QString" key="ProjectExplorer.ProjectConfiguration.DefaultDisplayName">Custom Executable</value>
<value type="QString" key="ProjectExplorer.ProjectConfiguration.DisplayName"></value>
<value type="QString" key="ProjectExplorer.ProjectConfiguration.Id">ProjectExplorer.CustomExecutableRunConfiguration</value>
<value type="uint" key="RunConfiguration.QmlDebugServerPort">3768</value>
<value type="bool" key="RunConfiguration.UseCppDebugger">true</value>
<value type="bool" key="RunConfiguration.UseCppDebuggerAuto">false</value>
<value type="bool" key="RunConfiguration.UseMultiProcess">false</value>
<value type="bool" key="RunConfiguration.UseQmlDebugger">false</value>
<value type="bool" key="RunConfiguration.UseQmlDebuggerAuto">true</value>
</valuemap>
<value type="int" key="ProjectExplorer.Target.RunConfigurationCount">1</value>
</valuemap>
</data>
<data>
<variable>ProjectExplorer.Project.TargetCount</variable>
<value type="int">1</value>
</data>
<data>
<variable>ProjectExplorer.Project.Updater.EnvironmentId</variable>
<value type="QByteArray">{d01d0a15-4efd-4fa2-8e2c-f26845794427}</value>
</data>
<data>
<variable>ProjectExplorer.Project.Updater.FileVersion</variable>
<value type="int">15</value>
</data>
</qtcreator>

3
tos/jtagwait/jtagwait.files Normal file
View File

@@ -0,0 +1,3 @@
include/driver_vec.h
sources/jtagwait.c
Makefile

1
tos/jtagwait/jtagwait.includes Normal file
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@@ -0,0 +1 @@
include

75
tos/jtagwait/sources/jtagwait.c Normal file
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@@ -0,0 +1,75 @@
#include <stdio.h>
#include <mint/osbind.h>
#include <stdint.h>
#include <stdbool.h>
#include "driver_vec.h"
#define FPGA_JTAG_LOADED_FLAG ((volatile bool *) 0xFF101000)
#define _MBAR ((volatile uint8_t *) 0xFF000000)
#define MCF_GPIO_PDDR_FEC1L ((volatile uint8_t *)(&_MBAR[0xA17]))
#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4 (0x10)
#define MCF_GPIO_PPDSDR_FEC1L ((volatile uint8_t *)(&_MBAR[0xA27]))
#define FPGA_CONFIG (1 << 2)
#define FPGA_CONF_DONE (1 << 5)
static inline uint32_t set_ipl(uint32_t ipl)
{
uint32_t ret;
__asm__ __volatile__(
" move.w sr,%[ret]\r\n" /* retrieve status register */
" andi.l #0x07,%[ipl]\n\t" /* mask out ipl bits on new value */
" lsl.l #8,%[ipl]\n\t" /* shift them to position */
" move.l %[ret],d0\n\t" /* retrieve original value */
" andi.l #0x0000f8ff,d0\n\t" /* clear ipl part */
" or.l %[ipl],d0\n\t" /* or in new value */
" move.w d0,sr\n\t" /* put it in place */
" andi.l #0x0700,%[ret]\r\n" /* mask out ipl bits */
" lsr.l #8,%[ret]\r\n" /* shift them to position */
: [ret] "=&d" (ret) /* output */
: [ipl] "d" (ipl) /* input */
: "d0", "cc" /* clobber */
);
return ret;
}
void wait_for_jtag(void)
{
set_ipl(7); /* disable interrupts */
/*
* configure FEC1L port directions to enable external JTAG configuration download to FPGA
*/
*MCF_GPIO_PDDR_FEC1L = 0 |
MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4; /* bit 4 = LED => output */
/* all other bits = input */
/*
* now that this GPIO ports have been switched to input, we can poll for FPGA config
* started from the JTAG interface (CONFIGn goes high) and finish (CONF_DONE goes high)
*/
while (*MCF_GPIO_PPDSDR_FEC1L & FPGA_CONFIG); /* wait for JTAG reset */
while (!(*MCF_GPIO_PPDSDR_FEC1L & FPGA_CONFIG)); /* wait for JTAG config load starting */
while (!(*MCF_GPIO_PPDSDR_FEC1L & FPGA_CONF_DONE)); /* wait for JTAG config load finished */
*FPGA_JTAG_LOADED_FLAG = true; /* indicate jtag loaded FPGA config to BaS */
/*
* reboot after configuration finished
*/
__asm__ __volatile__(
"jmp 0xE0000000\n\t"
);
}
int main(int argc, char *argv[])
{
printf("\033E\r\nFPGA JTAG configuration support\r\n");
printf("You may now savely load a new FPGA configuration through the JTAG interface\r\n"
"and your Firebee will reboot once finished using that new configuration.\r\n");
Supexec(wait_for_jtag);
return 0; /* just to make the compiler happy, we will never return */
}

117
tos/mcdcook/Makefile Executable file
View File

@@ -0,0 +1,117 @@
CROSS=Y
CROSSBINDIR_IS_Y=m68k-atari-mint-
CROSSBINDIR_IS_N=
CROSSBINDIR=$(CROSSBINDIR_IS_$(CROSS))
UNAME := $(shell uname)
ifeq ($(CROSS), Y)
ifeq ($(UNAME),Linux)
PREFIX=m68k-atari-mint
HATARI=hatari
else
PREFIX=m68k-atari-mint
HATARI=/usr/local/bin/hatari
endif
else
PREFIX=/usr
endif
DEPEND=depend
TOPDIR= ../..
INCLUDE=-I$(TOPDIR)/../libcmini/include -nostdlib
LIBS=-lcmini -nostdlib -lgcc
CC=$(PREFIX)/bin/gcc
CC=$(CROSSBINDIR)gcc
STRIP=$(CROSSBINDIR)strip
STACK=$(CROSSBINDIR)stack
APP=mcdcook.prg
TEST_APP=$(APP)
CFLAGS=\
-Os\
-g\
-Wl,-Map,mapfile\
-Wall
SRCDIR=sources
INCDIR=include
INCLUDE+=-I$(INCDIR)
CSRCS=\
$(SRCDIR)/mcdcook.c
ASRCS=
COBJS=$(patsubst $(SRCDIR)/%.o,%.o,$(patsubst %.c,%.o,$(CSRCS)))
AOBJS=$(patsubst $(SRCDIR)/%.o,%.o,$(patsubst %.S,%.o,$(ASRCS)))
OBJS=$(COBJS) $(AOBJS)
TRGTDIRS=. ./m68020-60 ./m5475 ./mshort ./m68020-60/mshort ./m5475/mshort
OBJDIRS=$(patsubst %,%/objs,$(TRGTDIRS))
#
# multilib flags. These must match m68k-atari-mint-gcc -print-multi-lib output
#
m68020-60/$(APP):CFLAGS += -m68020-60
m5475/$(APP):CFLAGS += -mcpu=5475
mshort/$(APP):CFLAGS += -mshort
m68020-60/mshort/$(APP): CFLAGS += -m68020-60 -mshort
m5475/mshort/$(APP): CFLAGS += -mcpu=5475 -mshort
ctest: $(TEST_APP)
all:$(patsubst %,%/$(APP),$(TRGTDIRS))
#
# generate pattern rules for multilib object files.
#
define CC_TEMPLATE
$(1)/objs/%.o:$(SRCDIR)/%.c
$(CC) $$(CFLAGS) $(INCLUDE) -c $$< -o $$@
$(1)/objs/%.o:$(SRCDIR)/%.S
$(CC) $$(CFLAGS) $(INCLUDE) -c $$< -o $$@
$(1)_OBJS=$(patsubst %,$(1)/objs/%,$(OBJS))
$(1)/$(APP): $$($(1)_OBJS)
$(CC) $$(CFLAGS) -o $$@ $(TOPDIR)/../libcmini/$(1)/startup.o $$($(1)_OBJS) -L$(TOPDIR)/../libcmini/$(1) $(LIBS)
$(STRIP) $$@
endef
$(foreach DIR,$(TRGTDIRS),$(eval $(call CC_TEMPLATE,$(DIR))))
$(DEPEND): $(ASRCS) $(CSRCS)
-rm -f $(DEPEND)
for d in $(TRGTDIRS);\
do $(CC) $(CFLAGS) $(INCLUDE) -M $(ASRCS) $(CSRCS) | sed -e "s#^\(.*\).o:#$$d/objs/\1.o:#" >> $(DEPEND); \
done
clean:
@rm -f $(patsubst %,%/objs/*.o,$(TRGTDIRS)) $(patsubst %,%/$(APP),$(TRGTDIRS))
@rm -f $(DEPEND) mapfile
.PHONY: printvars
printvars:
@$(foreach V,$(.VARIABLES), $(if $(filter-out environment% default automatic, $(origin $V)),$(warning $V=$($V))))
ifneq (clean,$(MAKECMDGOALS))
-include $(DEPEND)
endif
test: $(TEST_APP)
$(HATARI) --grab -w --tos $(TOPDIR)/../emutos/etos512k.img \
--machine falcon -s 14 --cpuclock 32 --cpulevel 3 --vdi true --vdi-planes 4 \
--vdi-width 640 --vdi-height 480 -d . $(APP)
ftest: $(TEST_APP)
$(HATARI) --grab -w --tos /usr/share/hatari/TOS404.IMG \
--machine falcon --cpuclock 32 --cpulevel 3 \
-d . $(APP)
sttest: $(TEST_APP)
$(HATARI) --grab -w --tos "/usr/share/hatari/tos106de.img" \
--machine st --cpuclock 32 --cpulevel 3 --vdi true --vdi-planes 4 \
--vdi-width 640 --vdi-height 480 \
-d . $(APP)

125
tos/mcdcook/include/driver_vec.h Normal file
View File

@@ -0,0 +1,125 @@
/*
* driver_vec.h
*
* Interface for exposure of BaS drivers to the OS
*
* This file is part of BaS_gcc.
*
* BaS_gcc is free software: you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* BaS_gcc is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
*
* Created on: 24.10.2013
* Author: Markus Fröschle
*/
#ifndef _DRIVER_VEC_H_
#define _DRIVER_VEC_H_
enum driver_type
{
END_OF_DRIVERS, /* marks end of driver list */
BLOCKDEV_DRIVER,
CHARDEV_DRIVER,
VIDEO_DRIVER,
XHDI_DRIVER,
MCD_DRIVER,
};
struct generic_driver_interface
{
uint32_t (*init)(void);
uint32_t (*read)(void *buf, size_t count);
uint32_t (*write)(const void *buf, size_t count);
uint32_t (*ioctl)(uint32_t request, ...);
};
/* Chained buffer descriptor */
typedef volatile struct MCD_bufDesc_struct MCD_bufDesc;
struct MCD_bufDesc_struct {
uint32_t flags; /* flags describing the DMA */
uint32_t csumResult; /* checksum from checksumming performed since last checksum reset */
int8_t *srcAddr; /* the address to move data from */
int8_t *destAddr; /* the address to move data to */
int8_t *lastDestAddr; /* the last address written to */
uint32_t dmaSize; /* the number of bytes to transfer independent of the transfer size */
MCD_bufDesc *next; /* next buffer descriptor in chain */
uint32_t info; /* private information about this descriptor; DMA does not affect it */
};
/* Progress Query struct */
typedef volatile struct MCD_XferProg_struct {
int8_t *lastSrcAddr; /* the most-recent or last, post-increment source address */
int8_t *lastDestAddr; /* the most-recent or last, post-increment destination address */
uint32_t dmaSize; /* the amount of data transferred for the current buffer */
MCD_bufDesc *currBufDesc;/* pointer to the current buffer descriptor being DMAed */
} MCD_XferProg;
struct dma_driver_interface
{
int32_t version;
int32_t magic;
int32_t (*dma_set_initiator)(int initiator);
uint32_t (*dma_get_initiator)(int requestor);
void (*dma_free_initiator)(int requestor);
int32_t (*dma_set_channel)(int requestor, void (*handler)(void));
int (*dma_get_channel)(int requestor);
void (*dma_free_channel)(int requestor);
void (*dma_clear_channel)(int channel);
int (*MCD_startDma)(int channel, int8_t *srcAddr, int16_t srcIncr, int8_t *destAddr, int16_t destIncr,
uint32_t dmaSize, uint32_t xferSize, uint32_t initiator, int32_t priority, uint32_t flags,
uint32_t funcDesc);
int (*MCD_dmaStatus)(int channel);
int (*MCD_XferProgrQuery)(int channel, MCD_XferProg *progRep);
int (*MCD_killDma)(int channel);
int (*MCD_continDma)(int channel);
int (*MCD_pauseDma)(int channel);
int (*MCD_resumeDma)(int channel);
int (*MCD_csumQuery)(int channel, uint32_t *csum);
void *(*dma_malloc)(long amount);
int (*dma_free)(void *addr);
};
struct xhdi_driver_interface
{
uint32_t (*xhdivec)();
};
union interface
{
struct generic_driver_interface *gdi;
struct xhdi_driver_interface *xhdi;
struct dma_driver_interface *dma;
};
struct generic_interface
{
enum driver_type type;
char name[16];
char description[64];
int version;
int revision;
union interface interface;
};
struct driver_table
{
uint32_t bas_version;
uint32_t bas_revision;
uint32_t (*remove_handler)(); /* calling this will disable the BaS' hook into trap #0 */
struct generic_interface *interfaces;
};
#endif /* _DRIVER_VEC_H_ */

121
tos/mcdcook/sources/mcdcook.c Normal file
View File

@@ -0,0 +1,121 @@
#include <stdio.h>
#include <mint/osbind.h>
#include <stdint.h>
#include <stdbool.h>
#include "driver_vec.h"
struct driver_table *get_bas_drivers(void)
{
struct driver_table *ret = NULL;
__asm__ __volatile(
" trap #0\n\t"
" move.l d0,%[ret]\n\t"
: [ret] "=m" (ret) /* output */
: /* no inputs */
: /* clobbered */
);
return ret;
}
static uint32_t cookieptr(void)
{
return * (uint32_t *) 0x5a0L;
}
void setcookie(uint32_t cookie, uint32_t value)
{
uint32_t *cookiejar = (uint32_t *) Supexec(cookieptr);
int num_slots;
int max_slots;
num_slots = max_slots = 0;
do
{
if (cookiejar[0] == cookie)
{
cookiejar[1] = value;
return;
}
cookiejar = &(cookiejar[2]);
num_slots++;
} while (cookiejar[-2]);
/*
* Here we are at the end of the list and did not find our cookie.
* Let's check if there is any space left and append our value to the
* list if so. If not, we are lost (extending the cookie jar does only
* work from TSRs)
*/
if (cookiejar[-1])
max_slots = cookiejar[-1];
if (max_slots > num_slots)
{
/* relief, there is space left, extend the list */
cookiejar[0] = cookiejar[-2];
cookiejar[1] = cookiejar[-1];
/* add the new element */
cookiejar[-2] = cookie;
cookiejar[-1] = value;
}
else
printf("cannot set cookie, cookie jar is full!\r\n");
}
# define COOKIE_DMAC 0x444D4143L /* FireTOS DMA API */
static char *dt_to_str(enum driver_type dt)
{
switch (dt)
{
case BLOCKDEV_DRIVER: return "generic block device driver";
case CHARDEV_DRIVER: return "generic character device driver";
case VIDEO_DRIVER: return "video/framebuffer driver";
case XHDI_DRIVER: return "XHDI compatible hard disk driver";
case MCD_DRIVER: return "multichannel DMA driver";
default: return "unknown driver type";
}
}
int main(int argc, char *argv[])
{
struct driver_table *dt;
void *ssp;
(void) Cconws("retrieve BaS driver interface\r\n");
ssp = (void *) Super(0L);
dt = get_bas_drivers();
if (dt)
{
struct generic_interface *ifc = &dt->interfaces[0];
printf("BaS driver table found at %p, BaS version is %d.%d\r\n", dt,
dt->bas_version, dt->bas_revision);
while (ifc->type != END_OF_DRIVERS)
{
printf("driver \"%s (%s)\" found,\r\n"
"interface type is %d (%s),\r\n"
"version %d.%d\r\n\r\n",
ifc->name, ifc->description, ifc->type, dt_to_str(ifc->type),
ifc->version, ifc->revision);
if (ifc->type == MCD_DRIVER)
{
setcookie(COOKIE_DMAC, ifc->interface.dma);
printf("\r\nDMAC cookie set to %p\r\n", ifc->interface.dma);
}
ifc++;
}
}
Super(ssp);
while (Cconis()) Cconin(); /* eat keys */
printf("press any key to continue\n\r");
// while (! Cconis());
return 0;
}

6
util/wait.c
View File

@@ -33,6 +33,7 @@ uint32_t get_timer(void)
{
return MCF_SLT_SCNT(0);
}
/*
* wait for the specified number of us on slice timer 0. Replaces the original routines that had
* the number of useconds to wait for hardcoded in their name.
@@ -52,8 +53,8 @@ void wait_ms(uint32_t ms)
wait(ms * 1000);
}
/*
* the same as above, with a checker function which gets called while
* busy waiting and allows for an early return if it returns true
* wait for the specified number of us (same as above), but with a checker function
* which gets called while busy waiting and allows for an early return if it returns true
*/
bool waitfor(uint32_t us, checker_func condition)
{
@@ -65,5 +66,6 @@ bool waitfor(uint32_t us, checker_func condition)
if ((res = (*condition)()))
return res;
} while (MCF_SLT_SCNT(0) - target > 0);
return false;
}

2
video/fbmodedb.c
View File

@@ -18,7 +18,7 @@
#define DBG_MODES
#ifdef DBG_MODES
#define dbg(format, arg...) do { xprintf("DEBUG: " format, ##arg); } while (0)
#define dbg(format, arg...) do { xprintf("DEBUG: " format, __FUNCTION__, ##arg); } while (0)
#else
#define dbg(format, arg...) do { ; } while (0)
#endif /* DBG_MODES */

7
video/fnt_st_8x16.c
View File

@@ -7,11 +7,10 @@
* option any later version. See doc/license.txt for details.
*/
#include "config.h"
#include "portab.h"
#include "bas_types.h"
#include "font.h"
static const UWORD off_table[] =
static const uint16_t off_table[] =
{
0x0000, 0x0008, 0x0010, 0x0018, 0x0020, 0x0028, 0x0030, 0x0038,
0x0040, 0x0048, 0x0050, 0x0058, 0x0060, 0x0068, 0x0070, 0x0078,
@@ -48,7 +47,7 @@ static const UWORD off_table[] =
0x0800,
};
static const UWORD dat_table[] =
static const uint16_t dat_table[] =
{
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x1104,

209
video/videl.c
View File

@@ -11,7 +11,12 @@
* option any later version. See doc/license.txt for details.
*/
#define DBG_VIDEL 0
#define DBG_VIDEL
#ifdef DBG_VIDEL
#define dbg(format, arg...) do { xprintf("DEBUG: %s(): " format, __FUNCTION__, ##arg); } while (0)
#else
#define dbg(format, arg...) do { ; } while (0)
#endif /* DBG_VIDEL */
#include <stdint.h>
#include <stdbool.h>
@@ -300,14 +305,14 @@ static uint16_t get_videl_bpp(void)
static uint16_t get_videl_width(void)
{
return (*(volatile uint16_t *)0xffff8210) * 16 / get_videl_bpp();
return ( * (volatile uint16_t *) 0xffff8210) * 16 / get_videl_bpp();
}
static uint16_t get_videl_height(void)
{
uint16_t vdb = *(volatile uint16_t *)0xffff82a8;
uint16_t vde = *(volatile uint16_t *)0xffff82aa;
uint16_t vmode = *(volatile uint16_t *)0xffff82c2;
uint16_t vdb = * (volatile uint16_t *) 0xffff82a8;
uint16_t vde = * (volatile uint16_t *) 0xffff82aa;
uint16_t vmode = * (volatile uint16_t *) 0xffff82c2;
/* visible y resolution:
* Graphics display starts at line VDB and ends at line
@@ -332,11 +337,14 @@ const VMODE_ENTRY *lookup_videl_mode(int16_t mode,int16_t monitor)
{
const VMODE_ENTRY *vmode_init_table, *p;
if (mode&VIDEL_VGA) {
if (mode&VIDEL_VGA)
{
vmode_init_table = vga_init_table;
/* ignore bits that don't affect initialisation data */
mode &= ~(VIDEL_VERTICAL|VIDEL_PAL);
} else {
}
else
{
vmode_init_table = nonvga_init_table;
}
@@ -368,34 +376,38 @@ static int16_t determine_width(int16_t mode)
/*
* determine vctl based on video mode and monitor type
*/
static int16_t determine_vctl(int16_t mode,int16_t monitor)
static int16_t determine_vctl(int16_t mode, int16_t monitor)
{
int16_t vctl;
if (mode&VIDEL_VGA) {
vctl = (mode&VIDEL_80COL) ? 0x08 : 0x04;
if (mode&VIDEL_VERTICAL)
if (mode & VIDEL_VGA)
{
vctl = (mode & VIDEL_80COL) ? 0x08 : 0x04;
if (mode & VIDEL_VERTICAL)
vctl |= 0x01;
} else {
vctl = (mode&VIDEL_80COL) ? 0x04 : 0x00;
if (mode&VIDEL_VERTICAL)
}
else
{
vctl = (mode & VIDEL_80COL) ? 0x04 : 0x00;
if (mode & VIDEL_VERTICAL)
vctl |= 0x02;
}
if (!(mode&VIDEL_COMPAT))
if (!(mode & VIDEL_COMPAT))
return vctl;
switch(mode&VIDEL_BPPMASK) {
case VIDEL_1BPP:
if (!(mode&VIDEL_VGA) && (monitor == MON_MONO))
vctl = 0x08;
break;
case VIDEL_2BPP:
vctl = (mode&VIDEL_VGA)? 0x09 : 0x04;
break;
case VIDEL_4BPP:
vctl = (mode&VIDEL_VGA)? 0x05 : 0x00;
break;
switch (mode & VIDEL_BPPMASK)
{
case VIDEL_1BPP:
if (!(mode & VIDEL_VGA) && (monitor == MON_MONO))
vctl = 0x08;
break;
case VIDEL_2BPP:
vctl = (mode & VIDEL_VGA)? 0x09 : 0x04;
break;
case VIDEL_4BPP:
vctl = (mode & VIDEL_VGA)? 0x05 : 0x00;
break;
}
return vctl;
@@ -407,25 +419,28 @@ static int16_t determine_vctl(int16_t mode,int16_t monitor)
*/
static int16_t determine_regc0(int16_t mode,int16_t monitor)
{
if (mode&VIDEL_VGA)
if (mode & VIDEL_VGA)
return 0x0186;
if (!(mode&VIDEL_COMPAT))
return (monitor==MON_TV)?0x0183:0x0181;
if (!(mode & VIDEL_COMPAT))
return (monitor == MON_TV) ? 0x0183 : 0x0181;
/* handle ST-compatible modes */
if ((mode&(VIDEL_80COL|VIDEL_BPPMASK)) == (VIDEL_80COL|VIDEL_1BPP)) { /* 80-column, 2-colour */
switch(monitor) {
case MON_MONO:
return 0x0080;
case MON_TV:
return 0x0183;
default:
return 0x0181;
if ((mode & (VIDEL_80COL | VIDEL_BPPMASK)) == (VIDEL_80COL | VIDEL_1BPP))
{
/* 80-column, 2-colour */
switch(monitor)
{
case MON_MONO:
return 0x0080;
case MON_TV:
return 0x0183;
default:
return 0x0181;
}
}
return (monitor==MON_TV)?0x0083:0x0081;
return (monitor == MON_TV) ? 0x0083 : 0x0081;
}
@@ -445,7 +460,7 @@ static int set_videl_vga(int16_t mode)
if (!p)
return -1;
videlregs[0x0a] = (mode&VIDEL_PAL) ? 2 : 0; /* video sync to 50Hz if PAL */
videlregs[0x0a] = (mode & VIDEL_PAL) ? 2 : 0; /* video sync to 50Hz if PAL */
// FIXME: vsync() can't work if the screen is initially turned off
//vsync(); /* wait for vbl so we're not interrupted :-) */
@@ -476,28 +491,30 @@ static int set_videl_vga(int16_t mode)
videlword(0xc0) = determine_regc0(mode,monitor);
videlword(0x66) = 0x0000; /* clear SPSHIFT */
switch(mode&VIDEL_BPPMASK) { /* set SPSHIFT / ST shift */
case VIDEL_1BPP: /* 2 colours (mono) */
if (monitor == MON_MONO)
videlregs[0x60] = 0x02;
else videlword(0x66) = 0x0400;
break;
case VIDEL_2BPP: /* 4 colours */
videlregs[0x60] = 0x01;
videlword(0x10) = linewidth; /* writing to the ST shifter has */
videlword(0xc2) = vctl; /* just overwritten these registers */
break;
case VIDEL_4BPP: /* 16 colours */
/* if not ST-compatible, SPSHIFT was already set correctly above */
if (mode&VIDEL_COMPAT)
videlregs[0x60] = 0x00; /* else set ST shifter */
break;
case VIDEL_8BPP: /* 256 colours */
videlword(0x66) = 0x0010;
break;
case VIDEL_TRUECOLOR: /* 65536 colours (Truecolor) */
videlword(0x66) = 0x0100;
break;
switch(mode & VIDEL_BPPMASK)
{
/* set SPSHIFT / ST shift */
case VIDEL_1BPP: /* 2 colours (mono) */
if (monitor == MON_MONO)
videlregs[0x60] = 0x02;
else videlword(0x66) = 0x0400;
break;
case VIDEL_2BPP: /* 4 colours */
videlregs[0x60] = 0x01;
videlword(0x10) = linewidth; /* writing to the ST shifter has */
videlword(0xc2) = vctl; /* just overwritten these registers */
break;
case VIDEL_4BPP: /* 16 colours */
/* if not ST-compatible, SPSHIFT was already set correctly above */
if (mode & VIDEL_COMPAT)
videlregs[0x60] = 0x00; /* else set ST shifter */
break;
case VIDEL_8BPP: /* 256 colours */
videlword(0x66) = 0x0010;
break;
case VIDEL_TRUECOLOR: /* 65536 colours (Truecolor) */
videlword(0x66) = 0x0100;
break;
}
return 0;
@@ -518,8 +535,8 @@ int16_t vsetmode(int16_t mode)
if (mode == -1)
return current_video_mode;
#if DBG_VIDEL
kprintf("vsetmode(0x%04x)\n", mode);
#ifdef DBG_VIDEL
xprintf("vsetmode(0x%04x)\n", mode);
#endif
if (set_videl_vga(mode) < 0) /* invalid mode */
@@ -577,26 +594,30 @@ int32_t vgetsize(int16_t mode)
monitor = vmontype();
mode &= VIDEL_VALID; /* ignore invalid bits */
if ((mode&VIDEL_BPPMASK) > VIDEL_TRUECOLOR) { /* fixup invalid bpp */
if ((mode & VIDEL_BPPMASK) > VIDEL_TRUECOLOR)
{
/* fixup invalid bpp */
mode &= ~VIDEL_BPPMASK;
mode |= VIDEL_TRUECOLOR;
}
p = lookup_videl_mode(mode,monitor);
if (!p) { /* invalid mode */
if (mode&VIDEL_COMPAT)
p = lookup_videl_mode(mode, monitor);
if (!p)
{
/* invalid mode */
if (mode & VIDEL_COMPAT)
return ST_VRAM_SIZE;
mode &= ~(VIDEL_OVERSCAN|VIDEL_PAL);/* ignore less-important bits */
p = lookup_videl_mode(mode,monitor);/* & try again */
p = lookup_videl_mode(mode, monitor);/* & try again */
if (!p) /* "can't happen" */
return FALCON_VRAM_SIZE;
}
vctl = determine_vctl(mode,monitor);
vctl = determine_vctl(mode, monitor);
height = p->vde - p->vdb;
if (!(vctl&0x02))
if (!(vctl & 0x02))
height >>= 1;
if (vctl&0x01)
if (vctl & 0x01)
height >>= 1;
return (int32_t)determine_width(mode) * 2 * height;
@@ -605,18 +626,21 @@ int32_t vgetsize(int16_t mode)
/*
* convert from Falcon palette format to STe palette format
*/
#define falc2ste(a) ((((a)>>1)&0x08)|(((a)>>5)&0x07))
#define falc2ste(a) ((((a) >> 1) & 0x08) | (((a) >> 5) & 0x07))
static void convert2ste(int16_t *ste,int32_t *falcon)
{
union {
union
{
int32_t l;
uint8_t b[4];
} u;
int i;
for (i = 0; i < 16; i++) {
for (i = 0; i < 16; i++)
{
u.l = *falcon++;
*ste++ = (falc2ste(u.b[0])<<8) | (falc2ste(u.b[1])<<4) | falc2ste(u.b[3]);
*ste++ = (falc2ste(u.b[0]) << 8) | (falc2ste(u.b[1]) << 4) | falc2ste(u.b[3]);
}
}
@@ -629,10 +653,10 @@ static int use_ste_palette(int16_t videomode)
if (vmontype() == MON_MONO) /* always for ST mono monitor */
return true;
if ((videomode&VIDEL_BPPMASK) == VIDEL_2BPP) /* always for 4-colour modes */
if ((videomode & VIDEL_BPPMASK) == VIDEL_2BPP) /* always for 4-colour modes */
return true;
if ((videomode&VIDEL_COMPAT) && ((videomode&VIDEL_BPPMASK) == VIDEL_4BPP))
if ((videomode & VIDEL_COMPAT) && ((videomode & VIDEL_BPPMASK) == VIDEL_4BPP))
return true; /* and for ST low */
return false;
@@ -652,10 +676,11 @@ static int use_ste_palette(int16_t videomode)
* address | 0x01 load first 16 Falcon palette regs from address
* 0 | 0x01 load 256 Falcon palette regs from falcon_shadow_palette[]
*/
int16_t vsetrgb(int16_t index,int16_t count,int32_t *rgb)
int16_t vsetrgb(int16_t index,int16_t count, int32_t *rgb)
{
int32_t *shadow, *source;
union {
union
{
int32_t l;
uint8_t b[4];
} u;
@@ -664,8 +689,8 @@ int16_t vsetrgb(int16_t index,int16_t count,int32_t *rgb)
if ((index < 0) || (count <= 0))
return -1; /* Generic error */
limit = (get_videl_bpp()<=4) ? 16 : 256;
if ((index+count) > limit)
limit = (get_videl_bpp() <= 4) ? 16 : 256;
if ((index + count) > limit)
return -1; /* Generic error */
/*
@@ -674,7 +699,7 @@ int16_t vsetrgb(int16_t index,int16_t count,int32_t *rgb)
*/
shadow = falcon_shadow_palette + index;
source = rgb;
while(count--) {
while (count--) {
u.l = *source++;
u.b[0] = u.b[1]; /* shift R & G */
u.b[1] = u.b[2];
@@ -696,7 +721,7 @@ int16_t vsetrgb(int16_t index,int16_t count,int32_t *rgb)
return 0; /* OK */
}
colorptr = (limit==256) ? (int16_t *) 0x01L : (int16_t *) ((int32_t) falcon_shadow_palette|0x01L);
colorptr = (limit == 256) ? (int16_t *) 0x01L : (int16_t *) ((int32_t) falcon_shadow_palette|0x01L);
set_palette(colorptr);
return 0; /* OK */
@@ -708,7 +733,8 @@ int16_t vsetrgb(int16_t index,int16_t count,int32_t *rgb)
int16_t vgetrgb(int16_t index,int16_t count,int32_t *rgb)
{
int32_t *shadow;
union {
union
{
int32_t l;
uint8_t b[4];
} u;
@@ -717,12 +743,13 @@ int16_t vgetrgb(int16_t index,int16_t count,int32_t *rgb)
if ((index < 0) || (count <= 0))
return -1; /* Generic error */
limit = (get_videl_bpp()<=4) ? 16 : 256;
if ((index+count) > limit)
limit = (get_videl_bpp() <= 4) ? 16 : 256;
if ((index + count) > limit)
return -1; /* Generic error */
shadow = falcon_shadow_palette + index;
while(count--) {
while (count--)
{
u.l = *shadow++;
u.b[2] = u.b[1]; /* shift R & G right*/
u.b[1] = u.b[0];
@@ -769,7 +796,7 @@ int16_t vfixmode(int16_t mode)
if (mode & VIDEL_VGA) /* if mode has VGA set, */
mode ^= (VIDEL_VERTICAL | VIDEL_VGA); /* clear it & flip vertical */
if (mode & VIDEL_COMPAT) {
if ((mode&VIDEL_BPPMASK) == VIDEL_1BPP)
if ((mode & VIDEL_BPPMASK) == VIDEL_1BPP)
mode |= VIDEL_VERTICAL; /* set vertical for ST high */
else mode &= ~VIDEL_VERTICAL; /* clear it for ST medium, low */
}
@@ -786,7 +813,7 @@ int16_t videl_check_moderez(int16_t moderez)
current_mode = get_videl_mode();
return_mode = vfixmode(moderez);/* adjust */
return (return_mode==current_mode)?0:return_mode;
return (return_mode == current_mode) ? 0 : return_mode;
}
uint32_t videl_vram_size(void)
@@ -832,7 +859,7 @@ void initialise_falcon_palette(int16_t mode)
* although it is probably not important since we don't use those
* registers.
*/
limit = ((mode&VIDEL_BPPMASK)==VIDEL_8BPP) ? 256 : 16;
limit = ((mode & VIDEL_BPPMASK) == VIDEL_8BPP) ? 256 : 16;
for (i = 0; i < limit; i++)
fcol_regs[i] = falcon_shadow_palette[i];
@@ -840,7 +867,7 @@ void initialise_falcon_palette(int16_t mode)
* if appropriate, set up the STe shadow & real palette registers
*/
if (use_ste_palette(mode)) {
convert2ste(ste_shadow_palette,falcon_shadow_palette);
convert2ste(ste_shadow_palette, falcon_shadow_palette);
for (i = 0; i < 16; i++)
col_regs[i] = ste_shadow_palette[i];
}