Clean up CACR initialization.
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@@ -81,9 +81,6 @@ void clear_caches(void)
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" move.l d0,a0\n\t"
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" cmpi.w #4,d0 | all ways?\n\t"
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" bne cfa_setloop | no->\n\t"
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" nop\n\t"
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" move.l _rt_cacr,d0 | get cacr shadow register\n\t"
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" movec d0,cacr | set old value\n\t"
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" move.l (sp)+,d2\n\t"
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" move.w d2,sr | restore previous interrupt mask\n\t"
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/* input */ :
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@@ -82,9 +82,6 @@ _mmu_init:
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clr.l d0
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movec d0,ASID // ASID allways 0
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move.l d0,_rt_asid // sichern
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movec d0,cacr // cache aus
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move.l d0,_rt_cacr // sichern
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nop
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move.l #0xC03FC040,d0 // data r/w precise c000'0000-ffff'ffff
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movec d0,ACR0
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@@ -171,10 +168,6 @@ _mmu_init:
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move.l d1,MCF_MMU_MMUDR
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move.l d3,MCF_MMU_MMUOR // setzen instr
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*/
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move.l #0xa10ca120,d0
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move.l d0,_rt_cacr // sichern
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movec d0,cacr
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nop
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rts
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/*
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@@ -33,10 +33,14 @@ warmstart:
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/* set stack pointer to end of SRAM1 */
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lea __SUP_SP,a7
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/* instruction cache on */
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move.l #0x000C8100,d0
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/* Initialize the processor caches.
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* The instruction cache is fully enabled.
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* The data cache is enabled, but cache-inhibited by default.
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* Later, the MMU will fully activate the data cache for specific areas.
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* It is important to enable both caches now, otherwise cpushl would hang.
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*/
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move.l #0xa50c8120,d0
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movec d0,cacr
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nop
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/* initialize any hardware specific issues */
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bra _initialize_hardware
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@@ -573,9 +573,6 @@ cfa_setloop:
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move.l d0,a0
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cmpi.w #4,d0 // all ways?
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bne cfa_setloop // nein->
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nop
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move.l _rt_cacr,d0 // holen
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movec d0,cacr // setzen
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move.w d2,sr // alte interrupt maske
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movem.l (a7),d0-d2/a0 // register zur<EFBFBD>ck
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lea 16(a7),a7
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@@ -675,14 +675,6 @@ void initialize_hardware(void) {
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uint32_t *dst; /* destination address to copy to */
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uint32_t *jmp; /* address of BaS() routine to jmp at after copy */
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__asm__ __volatile__(
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"move.l #0x000C8120,D0\n\t"
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"move.l D0,_rt_cacr\n\t"
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"movec D0,CACR\n\t"
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"nop\n\t"
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: : : "d0", "memory"
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);
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init_gpio();
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init_serial();
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init_slt();
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