Show FPGA date after config loading
FPGA have now a register(0xf0040100) where the date is stored
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@@ -45,6 +45,8 @@ extern uint8_t _FPGA_CONFIG[];
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extern uint8_t _FPGA_CONFIG_SIZE[];
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extern uint8_t _FPGA_CONFIG_SIZE[];
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#define FPGA_FLASH_DATA_SIZE ((uint32_t) &_FPGA_CONFIG_SIZE[0])
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#define FPGA_FLASH_DATA_SIZE ((uint32_t) &_FPGA_CONFIG_SIZE[0])
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#define ACP_FPGA_DATE_REG *(volatile uint32_t *)(0xF0040100)
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/*
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/*
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* flag located in processor SRAM1 that indicates that the FPGA configuration has
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* flag located in processor SRAM1 that indicates that the FPGA configuration has
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* been loaded through the onboard JTAG interface.
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* been loaded through the onboard JTAG interface.
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@@ -85,6 +87,16 @@ void config_gpio_for_jtag_config(void)
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*/
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*/
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}
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}
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void show_fpga_date(void)
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{
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uint32_t date = ACP_FPGA_DATE_REG;
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uint8_t day = (uint8_t)(date >> 24 & 0xffL);
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uint8_t month = (uint8_t)(date >> 16 & 0xffL);
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uint16_t year = (uint16_t)(date & 0xffffL);
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xprintf("FPGA date: %02x/%02x/%04x (dd/mm/yyyy) \r\n", day, month, year);
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}
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/*
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/*
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* load FPGA
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* load FPGA
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*/
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*/
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@@ -105,6 +117,8 @@ bool init_fpga(void)
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// _FPGA_JTAG_LOADED = 0;
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// _FPGA_JTAG_LOADED = 0;
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// _FPGA_JTAG_VALID = 0;
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// _FPGA_JTAG_VALID = 0;
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show_fpga_date();
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return true;
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return true;
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}
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}
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start = MCF_SLT0_SCNT;
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start = MCF_SLT0_SCNT;
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@@ -192,6 +206,8 @@ bool init_fpga(void)
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xprintf("SRAM now set to FPGA load skip\r\n");
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xprintf("SRAM now set to FPGA load skip\r\n");
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show_fpga_date();
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return true;
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return true;
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}
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}
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xprintf("FAILED!\r\n");
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xprintf("FAILED!\r\n");
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