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362
include/MCD_dma.h
Normal file
362
include/MCD_dma.h
Normal file
@@ -0,0 +1,362 @@
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/*
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* File: MCD_dma.h
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* Purpose: Main header file for multi-channel DMA API.
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*
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* Notes:
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*/
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#ifndef _MCD_API_H
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#define _MCD_API_H
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/*
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* Turn Execution Unit tasks ON (#define) or OFF (#undef)
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*/
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#undef MCD_INCLUDE_EU
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//#define MCD_INCLUDE_EU
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/*
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* Number of DMA channels
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*/
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#define NCHANNELS 16
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/*
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* Total number of variants
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*/
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#ifdef MCD_INCLUDE_EU
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#define NUMOFVARIANTS 6
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#else
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#define NUMOFVARIANTS 4
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#endif
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/*
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* Define sizes of the various tables
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*/
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#define TASK_TABLE_SIZE (NCHANNELS*32)
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#define VAR_TAB_SIZE (128)
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#define CONTEXT_SAVE_SIZE (128)
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#define FUNCDESC_TAB_SIZE (256)
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#ifdef MCD_INCLUDE_EU
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#define FUNCDESC_TAB_NUM 16
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#else
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#define FUNCDESC_TAB_NUM 1
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#endif
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#ifndef DEFINESONLY
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/*
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* Portability typedefs
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*/
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typedef int s32;
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typedef unsigned int u32;
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typedef short s16;
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typedef unsigned short u16;
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typedef char s8;
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typedef unsigned char u8;
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/*
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* These structures represent the internal registers of the
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* multi-channel DMA
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*/
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struct dmaRegs_s {
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u32 taskbar; /* task table base address register */
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u32 currPtr;
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u32 endPtr;
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u32 varTablePtr;
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u16 dma_rsvd0;
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u16 ptdControl; /* ptd control */
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u32 intPending; /* interrupt pending register */
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u32 intMask; /* interrupt mask register */
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u16 taskControl[16]; /* task control registers */
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u8 priority[32]; /* priority registers */
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u32 initiatorMux; /* initiator mux control */
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u32 taskSize0; /* task size control register 0. */
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u32 taskSize1; /* task size control register 1. */
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u32 dma_rsvd1; /* reserved */
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u32 dma_rsvd2; /* reserved */
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u32 debugComp1; /* debug comparator 1 */
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u32 debugComp2; /* debug comparator 2 */
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u32 debugControl; /* debug control */
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u32 debugStatus; /* debug status */
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u32 ptdDebug; /* priority task decode debug */
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u32 dma_rsvd3[31]; /* reserved */
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};
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typedef volatile struct dmaRegs_s dmaRegs;
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#endif
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/*
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* PTD contrl reg bits
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*/
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#define PTD_CTL_TSK_PRI 0x8000
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#define PTD_CTL_COMM_PREFETCH 0x0001
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/*
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* Task Control reg bits and field masks
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*/
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#define TASK_CTL_EN 0x8000
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#define TASK_CTL_VALID 0x4000
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#define TASK_CTL_ALWAYS 0x2000
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#define TASK_CTL_INIT_MASK 0x1f00
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#define TASK_CTL_ASTRT 0x0080
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#define TASK_CTL_HIPRITSKEN 0x0040
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#define TASK_CTL_HLDINITNUM 0x0020
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#define TASK_CTL_ASTSKNUM_MASK 0x000f
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/*
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* Priority reg bits and field masks
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*/
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#define PRIORITY_HLD 0x80
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#define PRIORITY_PRI_MASK 0x07
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/*
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* Debug Control reg bits and field masks
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*/
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#define DBG_CTL_BLOCK_TASKS_MASK 0xffff0000
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#define DBG_CTL_AUTO_ARM 0x00008000
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#define DBG_CTL_BREAK 0x00004000
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#define DBG_CTL_COMP1_TYP_MASK 0x00003800
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#define DBG_CTL_COMP2_TYP_MASK 0x00000070
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#define DBG_CTL_EXT_BREAK 0x00000004
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#define DBG_CTL_INT_BREAK 0x00000002
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/*
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* PTD Debug reg selector addresses
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* This reg must be written with a value to show the contents of
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* one of the desired internal register.
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*/
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#define PTD_DBG_REQ 0x00 /* shows the state of 31 initiators */
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#define PTD_DBG_TSK_VLD_INIT 0x01 /* shows which 16 tasks are valid and
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have initiators asserted */
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/*
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* General return values
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*/
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#define MCD_OK 0
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#define MCD_ERROR -1
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#define MCD_TABLE_UNALIGNED -2
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#define MCD_CHANNEL_INVALID -3
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/*
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* MCD_initDma input flags
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*/
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#define MCD_RELOC_TASKS 0x00000001
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#define MCD_NO_RELOC_TASKS 0x00000000
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#define MCD_COMM_PREFETCH_EN 0x00000002 /* Commbus Prefetching - MCF547x/548x ONLY */
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/*
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* MCD_dmaStatus Status Values for each channel
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*/
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#define MCD_NO_DMA 1 /* No DMA has been requested since reset */
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#define MCD_IDLE 2 /* DMA active, but the initiator is currently inactive */
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#define MCD_RUNNING 3 /* DMA active, and the initiator is currently active */
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#define MCD_PAUSED 4 /* DMA active but it is currently paused */
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#define MCD_HALTED 5 /* the most recent DMA has been killed with MCD_killTask() */
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#define MCD_DONE 6 /* the most recent DMA has completed. */
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/*
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* MCD_startDma parameter defines
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*/
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/*
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* Constants for the funcDesc parameter
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*/
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/* Byte swapping: */
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#define MCD_NO_BYTE_SWAP 0x00045670 /* to disable byte swapping. */
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#define MCD_BYTE_REVERSE 0x00076540 /* to reverse the bytes of each u32 of the DMAed data. */
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#define MCD_U16_REVERSE 0x00067450 /* to reverse the 16-bit halves of
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each 32-bit data value being DMAed.*/
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#define MCD_U16_BYTE_REVERSE 0x00054760 /* to reverse the byte halves of each
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16-bit half of each 32-bit data value DMAed */
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#define MCD_NO_BIT_REV 0x00000000 /* do not reverse the bits of each byte DMAed. */
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#define MCD_BIT_REV 0x00088880 /* reverse the bits of each byte DMAed */
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/* CRCing: */
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#define MCD_CRC16 0xc0100000 /* to perform CRC-16 on DMAed data. */
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#define MCD_CRCCCITT 0xc0200000 /* to perform CRC-CCITT on DMAed data. */
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#define MCD_CRC32 0xc0300000 /* to perform CRC-32 on DMAed data. */
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#define MCD_CSUMINET 0xc0400000 /* to perform internet checksums on DMAed data.*/
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#define MCD_NO_CSUM 0xa0000000 /* to perform no checksumming. */
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#define MCD_FUNC_NOEU1 (MCD_NO_BYTE_SWAP | MCD_NO_BIT_REV | MCD_NO_CSUM)
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#define MCD_FUNC_NOEU2 (MCD_NO_BYTE_SWAP | MCD_NO_CSUM)
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/*
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* Constants for the flags parameter
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*/
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#define MCD_TT_FLAGS_RL 0x00000001 /* Read line */
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#define MCD_TT_FLAGS_CW 0x00000002 /* Combine Writes */
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#define MCD_TT_FLAGS_SP 0x00000004 /* Speculative prefetch(XLB) MCF547x/548x ONLY */
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#define MCD_TT_FLAGS_MASK 0x000000ff
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#define MCD_TT_FLAGS_DEF (MCD_TT_FLAGS_RL | MCD_TT_FLAGS_CW)
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#define MCD_SINGLE_DMA 0x00000100 /* Unchained DMA */
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#define MCD_CHAIN_DMA /* TBD */
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#define MCD_EU_DMA /* TBD */
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#define MCD_FECTX_DMA 0x00001000 /* FEC TX ring DMA */
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#define MCD_FECRX_DMA 0x00002000 /* FEC RX ring DMA */
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/* these flags are valid for MCD_startDma and the chained buffer descriptors */
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#define MCD_BUF_READY 0x80000000 /* indicates that this buffer is now under the DMA's control */
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#define MCD_WRAP 0x20000000 /* to tell the FEC Dmas to wrap to the first BD */
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#define MCD_INTERRUPT 0x10000000 /* to generate an interrupt after completion of the DMA. */
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#define MCD_END_FRAME 0x08000000 /* tell the DMA to end the frame when transferring
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last byte of data in buffer */
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#define MCD_CRC_RESTART 0x40000000 /* to empty out the accumulated checksum
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prior to performing the DMA. */
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/* Defines for the FEC buffer descriptor control/status word*/
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#define MCD_FEC_BUF_READY 0x8000
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#define MCD_FEC_WRAP 0x2000
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#define MCD_FEC_INTERRUPT 0x1000
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#define MCD_FEC_END_FRAME 0x0800
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/*
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* Defines for general intuitiveness
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*/
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#define MCD_TRUE 1
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#define MCD_FALSE 0
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/*
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* Three different cases for destination and source.
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*/
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#define MINUS1 -1
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#define ZERO 0
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#define PLUS1 1
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#ifndef DEFINESONLY
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/* Task Table Entry struct*/
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typedef struct {
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u32 TDTstart; /* task descriptor table start */
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u32 TDTend; /* task descriptor table end */
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u32 varTab; /* variable table start */
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u32 FDTandFlags; /* function descriptor table start and flags */
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volatile u32 descAddrAndStatus;
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volatile u32 modifiedVarTab;
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u32 contextSaveSpace; /* context save space start */
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u32 literalBases;
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} TaskTableEntry;
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/* Chained buffer descriptor */
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typedef volatile struct MCD_bufDesc_struct MCD_bufDesc;
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struct MCD_bufDesc_struct {
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u32 flags; /* flags describing the DMA */
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u32 csumResult; /* checksum from checksumming performed since last checksum reset */
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s8 *srcAddr; /* the address to move data from */
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s8 *destAddr; /* the address to move data to */
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s8 *lastDestAddr; /* the last address written to */
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u32 dmaSize; /* the number of bytes to transfer independent of the transfer size */
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MCD_bufDesc *next; /* next buffer descriptor in chain */
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u32 info; /* private information about this descriptor; DMA does not affect it */
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};
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/* Progress Query struct */
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typedef volatile struct MCD_XferProg_struct {
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s8 *lastSrcAddr; /* the most-recent or last, post-increment source address */
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s8 *lastDestAddr; /* the most-recent or last, post-increment destination address */
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u32 dmaSize; /* the amount of data transferred for the current buffer */
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MCD_bufDesc *currBufDesc;/* pointer to the current buffer descriptor being DMAed */
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} MCD_XferProg;
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/* FEC buffer descriptor */
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typedef volatile struct MCD_bufDescFec_struct {
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u16 statCtrl;
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u16 length;
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u32 dataPointer;
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} MCD_bufDescFec;
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/*************************************************************************/
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/*
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* API function Prototypes - see MCD_dmaApi.c for further notes
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*/
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/*
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* MCD_startDma starts a particular kind of DMA .
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*/
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int MCD_startDma (
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int channel, /* the channel on which to run the DMA */
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s8 *srcAddr, /* the address to move data from, or buffer-descriptor address */
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s16 srcIncr, /* the amount to increment the source address per transfer */
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s8 *destAddr, /* the address to move data to */
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s16 destIncr, /* the amount to increment the destination address per transfer */
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u32 dmaSize, /* the number of bytes to transfer independent of the transfer size */
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u32 xferSize, /* the number bytes in of each data movement (1, 2, or 4) */
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u32 initiator, /* what device initiates the DMA */
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int priority, /* priority of the DMA */
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u32 flags, /* flags describing the DMA */
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u32 funcDesc /* a description of byte swapping, bit swapping, and CRC actions */
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);
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/*
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* MCD_initDma() initializes the DMA API by setting up a pointer to the DMA
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* registers, relocating and creating the appropriate task structures, and
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* setting up some global settings
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*/
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int MCD_initDma (dmaRegs *sDmaBarAddr, void *taskTableDest, u32 flags);
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/*
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* MCD_dmaStatus() returns the status of the DMA on the requested channel.
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*/
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int MCD_dmaStatus (int channel);
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/*
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* MCD_XferProgrQuery() returns progress of DMA on requested channel
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*/
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int MCD_XferProgrQuery (int channel, MCD_XferProg *progRep);
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/*
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* MCD_killDma() halts the DMA on the requested channel, without any
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* intention of resuming the DMA.
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*/
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int MCD_killDma (int channel);
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/*
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* MCD_continDma() continues a DMA which as stopped due to encountering an
|
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* unready buffer descriptor.
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*/
|
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int MCD_continDma (int channel);
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||||
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||||
/*
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* MCD_pauseDma() pauses the DMA on the given channel ( if any DMA is
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* running on that channel).
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*/
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int MCD_pauseDma (int channel);
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||||
|
||||
/*
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* MCD_resumeDma() resumes the DMA on a given channel (if any DMA is
|
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* running on that channel).
|
||||
*/
|
||||
int MCD_resumeDma (int channel);
|
||||
|
||||
/*
|
||||
* MCD_csumQuery provides the checksum/CRC after performing a non-chained DMA
|
||||
*/
|
||||
int MCD_csumQuery (int channel, u32 *csum);
|
||||
|
||||
/*
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||||
* MCD_getCodeSize provides the packed size required by the microcoded task
|
||||
* and structures.
|
||||
*/
|
||||
int MCD_getCodeSize(void);
|
||||
|
||||
/*
|
||||
* MCD_getVersion provides a pointer to a version string and returns a
|
||||
* version number.
|
||||
*/
|
||||
int MCD_getVersion(char **longVersion);
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||||
|
||||
/* macro for setting a location in the variable table */
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#define MCD_SET_VAR(taskTab,idx,value) ((u32 *)(taskTab)->varTab)[idx] = value
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||||
/* Note that MCD_SET_VAR() is invoked many times in firing up a DMA function,
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so I'm avoiding surrounding it with "do {} while(0)" */
|
||||
|
||||
#endif /* DEFINESONLY */
|
||||
|
||||
#endif /* _MCD_API_H */
|
||||
5
include/MCD_progCheck.h
Normal file
5
include/MCD_progCheck.h
Normal file
@@ -0,0 +1,5 @@
|
||||
/* This file is autogenerated. Do not change */
|
||||
#define CURRBD 4
|
||||
#define DCOUNT 6
|
||||
#define DESTPTR 5
|
||||
#define SRCPTR 7
|
||||
44
include/MCD_tasksInit.h
Normal file
44
include/MCD_tasksInit.h
Normal file
@@ -0,0 +1,44 @@
|
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#ifndef MCD_TSK_INIT_H
|
||||
#define MCD_TSK_INIT_H 1
|
||||
|
||||
/*
|
||||
* Do not edit!
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
* Task 0
|
||||
*/
|
||||
void MCD_startDmaChainNoEu(int *currBD, short srcIncr, short destIncr, int xferSize, short xferSizeIncr, int *cSave, volatile TaskTableEntry *taskTable, int channel);
|
||||
|
||||
|
||||
/*
|
||||
* Task 1
|
||||
*/
|
||||
void MCD_startDmaSingleNoEu(char *srcAddr, short srcIncr, char *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel);
|
||||
|
||||
|
||||
/*
|
||||
* Task 2
|
||||
*/
|
||||
void MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr, int xferSize, short xferSizeIncr, int *cSave, volatile TaskTableEntry *taskTable, int channel);
|
||||
|
||||
|
||||
/*
|
||||
* Task 3
|
||||
*/
|
||||
void MCD_startDmaSingleEu(char *srcAddr, short srcIncr, char *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel);
|
||||
|
||||
|
||||
/*
|
||||
* Task 4
|
||||
*/
|
||||
void MCD_startDmaENetRcv(char *bDBase, char *currBD, char *rcvFifoPtr, volatile TaskTableEntry *taskTable, int channel);
|
||||
|
||||
|
||||
/*
|
||||
* Task 5
|
||||
*/
|
||||
void MCD_startDmaENetXmit(char *bDBase, char *currBD, char *xmitFifoPtr, volatile TaskTableEntry *taskTable, int channel);
|
||||
|
||||
#endif /* MCD_TSK_INIT_H */
|
||||
67
include/MCF5475.h
Normal file
67
include/MCF5475.h
Normal file
@@ -0,0 +1,67 @@
|
||||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.81
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF5475_H__
|
||||
#define __MCF5475_H__
|
||||
|
||||
#include <bas_types.h>
|
||||
/***
|
||||
* MCF5475 Derivative Memory map definitions from linker command files:
|
||||
* __MBAR, __MMUBAR, __RAMBAR0, __RAMBAR0_SIZE, __RAMBAR1, __RAMBAR1_SIZE
|
||||
* linker symbols must be defined in the linker command file.
|
||||
*/
|
||||
|
||||
typedef uint32_t __attribute__((__may_alias__)) uint32_t_a; /* a type to avoid gcc's complaints about pointer aliasing */
|
||||
|
||||
extern uint8_t _MBAR[];
|
||||
extern uint8_t _MMUBAR[];
|
||||
extern uint8_t _RAMBAR0[];
|
||||
extern uint8_t _RAMBAR0_SIZE[];
|
||||
extern uint8_t _RAMBAR1[];
|
||||
extern uint8_t _RAMBAR1_SIZE[];
|
||||
|
||||
#define MBAR_ADDRESS (uint32_t)_MBAR
|
||||
#define MMUBAR_ADDRESS (uint32_t)_MMUBAR
|
||||
#define RAMBAR0_ADDRESS (uint32_t)_RAMBAR0
|
||||
#define RAMBAR0_SIZE (uint32_t)_RAMBAR0_SIZE
|
||||
#define RAMBAR1_ADDRESS (uint32_t)_RAMBAR1
|
||||
#define RAMBAR1_SIZE (uint32_t)_RAMBAR1_SIZE
|
||||
|
||||
|
||||
#include "MCF5475_SIU.h"
|
||||
#include "MCF5475_MMU.h"
|
||||
#include "MCF5475_SDRAMC.h"
|
||||
#include "MCF5475_XLB.h"
|
||||
#include "MCF5475_CLOCK.h"
|
||||
#include "MCF5475_FBCS.h"
|
||||
#include "MCF5475_INTC.h"
|
||||
#include "MCF5475_GPT.h"
|
||||
#include "MCF5475_SLT.h"
|
||||
#include "MCF5475_GPIO.h"
|
||||
#include "MCF5475_PAD.h"
|
||||
#include "MCF5475_PCI.h"
|
||||
#include "MCF5475_PCIARB.h"
|
||||
#include "MCF5475_EPORT.h"
|
||||
#include "MCF5475_CTM.h"
|
||||
#include "MCF5475_DMA.h"
|
||||
#include "MCF5475_PSC.h"
|
||||
#include "MCF5475_DSPI.h"
|
||||
#include "MCF5475_I2C.h"
|
||||
#include "MCF5475_FEC.h"
|
||||
#include "MCF5475_USB.h"
|
||||
#include "MCF5475_SRAM.h"
|
||||
#include "MCF5475_SEC.h"
|
||||
|
||||
#endif /* __MCF5475_H__ */
|
||||
47
include/MCF5475_CLOCK.h
Normal file
47
include/MCF5475_CLOCK.h
Normal file
@@ -0,0 +1,47 @@
|
||||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.81
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF5475_CLOCK_H__
|
||||
#define __MCF5475_CLOCK_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Clock Module (CLOCK)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_CLOCK_SPCR (*(volatile uint32_t*)(&_MBAR[0x300]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_CLOCK_SPCR */
|
||||
#define MCF_CLOCK_SPCR_MEMEN (0x1)
|
||||
#define MCF_CLOCK_SPCR_PCIEN (0x2)
|
||||
#define MCF_CLOCK_SPCR_FBEN (0x4)
|
||||
#define MCF_CLOCK_SPCR_CAN0EN (0x8)
|
||||
#define MCF_CLOCK_SPCR_DMAEN (0x10)
|
||||
#define MCF_CLOCK_SPCR_FEC0EN (0x20)
|
||||
#define MCF_CLOCK_SPCR_FEC1EN (0x40)
|
||||
#define MCF_CLOCK_SPCR_USBEN (0x80)
|
||||
#define MCF_CLOCK_SPCR_PSCEN (0x200)
|
||||
#define MCF_CLOCK_SPCR_CAN1EN (0x800)
|
||||
#define MCF_CLOCK_SPCR_CRYENA (0x1000)
|
||||
#define MCF_CLOCK_SPCR_CRYENB (0x2000)
|
||||
#define MCF_CLOCK_SPCR_COREN (0x4000)
|
||||
#define MCF_CLOCK_SPCR_PLLK (0x80000000)
|
||||
|
||||
|
||||
#endif /* __MCF5475_CLOCK_H__ */
|
||||
76
include/MCF5475_CTM.h
Normal file
76
include/MCF5475_CTM.h
Normal file
@@ -0,0 +1,76 @@
|
||||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.81
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF5475_CTM_H__
|
||||
#define __MCF5475_CTM_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Comm Timer Module (CTM)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_CTM_CTCR0 (*(volatile uint32_t*)(&_MBAR[0x7F00]))
|
||||
#define MCF_CTM_CTCR1 (*(volatile uint32_t*)(&_MBAR[0x7F04]))
|
||||
#define MCF_CTM_CTCR2 (*(volatile uint32_t*)(&_MBAR[0x7F08]))
|
||||
#define MCF_CTM_CTCR3 (*(volatile uint32_t*)(&_MBAR[0x7F0C]))
|
||||
#define MCF_CTM_CTCR4 (*(volatile uint32_t*)(&_MBAR[0x7F10]))
|
||||
#define MCF_CTM_CTCR5 (*(volatile uint32_t*)(&_MBAR[0x7F14]))
|
||||
#define MCF_CTM_CTCR6 (*(volatile uint32_t*)(&_MBAR[0x7F18]))
|
||||
#define MCF_CTM_CTCR7 (*(volatile uint32_t*)(&_MBAR[0x7F1C]))
|
||||
#define MCF_CTM_CTCRF(x) (*(volatile uint32_t*)(&_MBAR[0x7F00 + ((x)*0x4)]))
|
||||
#define MCF_CTM_CTCRV(x) (*(volatile uint32_t*)(&_MBAR[0x7F10 + ((x-4)*0x4)]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_CTM_CTCRF */
|
||||
#define MCF_CTM_CTCRF_CRV(x) (((x)&0xFFFF)<<0)
|
||||
#define MCF_CTM_CTCRF_S(x) (((x)&0xF)<<0x10)
|
||||
#define MCF_CTM_CTCRF_S_CLK_1 (0)
|
||||
#define MCF_CTM_CTCRF_S_CLK_2 (0x10000)
|
||||
#define MCF_CTM_CTCRF_S_CLK_4 (0x20000)
|
||||
#define MCF_CTM_CTCRF_S_CLK_8 (0x30000)
|
||||
#define MCF_CTM_CTCRF_S_CLK_16 (0x40000)
|
||||
#define MCF_CTM_CTCRF_S_CLK_32 (0x50000)
|
||||
#define MCF_CTM_CTCRF_S_CLK_64 (0x60000)
|
||||
#define MCF_CTM_CTCRF_S_CLK_128 (0x70000)
|
||||
#define MCF_CTM_CTCRF_S_CLK_256 (0x80000)
|
||||
#define MCF_CTM_CTCRF_S_CLK_EXT (0x90000)
|
||||
#define MCF_CTM_CTCRF_PCT(x) (((x)&0x7)<<0x14)
|
||||
#define MCF_CTM_CTCRF_PCT_100 (0)
|
||||
#define MCF_CTM_CTCRF_PCT_50 (0x100000)
|
||||
#define MCF_CTM_CTCRF_PCT_25 (0x200000)
|
||||
#define MCF_CTM_CTCRF_PCT_12p5 (0x300000)
|
||||
#define MCF_CTM_CTCRF_PCT_6p25 (0x400000)
|
||||
#define MCF_CTM_CTCRF_PCT_OFF (0x500000)
|
||||
#define MCF_CTM_CTCRF_M (0x800000)
|
||||
#define MCF_CTM_CTCRF_IM (0x1000000)
|
||||
#define MCF_CTM_CTCRF_I (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_CTM_CTCRV */
|
||||
#define MCF_CTM_CTCRV_CRV(x) (((x)&0xFFFFFF)<<0)
|
||||
#define MCF_CTM_CTCRV_PCT(x) (((x)&0x7)<<0x18)
|
||||
#define MCF_CTM_CTCRV_PCT_100 (0)
|
||||
#define MCF_CTM_CTCRV_PCT_50 (0x1000000)
|
||||
#define MCF_CTM_CTCRV_PCT_25 (0x2000000)
|
||||
#define MCF_CTM_CTCRV_PCT_12p5 (0x3000000)
|
||||
#define MCF_CTM_CTCRV_PCT_6p25 (0x4000000)
|
||||
#define MCF_CTM_CTCRV_PCT_OFF (0x5000000)
|
||||
#define MCF_CTM_CTCRV_M (0x8000000)
|
||||
#define MCF_CTM_CTCRV_S (0x10000000)
|
||||
|
||||
|
||||
#endif /* __MCF5475_CTM_H__ */
|
||||
234
include/MCF5475_DMA.h
Normal file
234
include/MCF5475_DMA.h
Normal file
@@ -0,0 +1,234 @@
|
||||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.81
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF5475_DMA_H__
|
||||
#define __MCF5475_DMA_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Multichannel DMA (DMA)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_DMA_TASKBAR (*(volatile uint32_t*)(&_MBAR[0x8000]))
|
||||
#define MCF_DMA_CP (*(volatile uint32_t*)(&_MBAR[0x8004]))
|
||||
#define MCF_DMA_EP (*(volatile uint32_t*)(&_MBAR[0x8008]))
|
||||
#define MCF_DMA_VP (*(volatile uint32_t*)(&_MBAR[0x800C]))
|
||||
#define MCF_DMA_PTD (*(volatile uint32_t*)(&_MBAR[0x8010]))
|
||||
#define MCF_DMA_DIPR (*(volatile uint32_t*)(&_MBAR[0x8014]))
|
||||
#define MCF_DMA_DIMR (*(volatile uint32_t*)(&_MBAR[0x8018]))
|
||||
#define MCF_DMA_TCR0 (*(volatile uint16_t*)(&_MBAR[0x801C]))
|
||||
#define MCF_DMA_TCR1 (*(volatile uint16_t*)(&_MBAR[0x801E]))
|
||||
#define MCF_DMA_TCR2 (*(volatile uint16_t*)(&_MBAR[0x8020]))
|
||||
#define MCF_DMA_TCR3 (*(volatile uint16_t*)(&_MBAR[0x8022]))
|
||||
#define MCF_DMA_TCR4 (*(volatile uint16_t*)(&_MBAR[0x8024]))
|
||||
#define MCF_DMA_TCR5 (*(volatile uint16_t*)(&_MBAR[0x8026]))
|
||||
#define MCF_DMA_TCR6 (*(volatile uint16_t*)(&_MBAR[0x8028]))
|
||||
#define MCF_DMA_TCR7 (*(volatile uint16_t*)(&_MBAR[0x802A]))
|
||||
#define MCF_DMA_TCR8 (*(volatile uint16_t*)(&_MBAR[0x802C]))
|
||||
#define MCF_DMA_TCR9 (*(volatile uint16_t*)(&_MBAR[0x802E]))
|
||||
#define MCF_DMA_TCR10 (*(volatile uint16_t*)(&_MBAR[0x8030]))
|
||||
#define MCF_DMA_TCR11 (*(volatile uint16_t*)(&_MBAR[0x8032]))
|
||||
#define MCF_DMA_TCR12 (*(volatile uint16_t*)(&_MBAR[0x8034]))
|
||||
#define MCF_DMA_TCR13 (*(volatile uint16_t*)(&_MBAR[0x8036]))
|
||||
#define MCF_DMA_TCR14 (*(volatile uint16_t*)(&_MBAR[0x8038]))
|
||||
#define MCF_DMA_TCR15 (*(volatile uint16_t*)(&_MBAR[0x803A]))
|
||||
#define MCF_DMA_PRIOR0 (*(volatile uint8_t *)(&_MBAR[0x803C]))
|
||||
#define MCF_DMA_PRIOR1 (*(volatile uint8_t *)(&_MBAR[0x803D]))
|
||||
#define MCF_DMA_PRIOR2 (*(volatile uint8_t *)(&_MBAR[0x803E]))
|
||||
#define MCF_DMA_PRIOR3 (*(volatile uint8_t *)(&_MBAR[0x803F]))
|
||||
#define MCF_DMA_PRIOR4 (*(volatile uint8_t *)(&_MBAR[0x8040]))
|
||||
#define MCF_DMA_PRIOR5 (*(volatile uint8_t *)(&_MBAR[0x8041]))
|
||||
#define MCF_DMA_PRIOR6 (*(volatile uint8_t *)(&_MBAR[0x8042]))
|
||||
#define MCF_DMA_PRIOR7 (*(volatile uint8_t *)(&_MBAR[0x8043]))
|
||||
#define MCF_DMA_PRIOR8 (*(volatile uint8_t *)(&_MBAR[0x8044]))
|
||||
#define MCF_DMA_PRIOR9 (*(volatile uint8_t *)(&_MBAR[0x8045]))
|
||||
#define MCF_DMA_PRIOR10 (*(volatile uint8_t *)(&_MBAR[0x8046]))
|
||||
#define MCF_DMA_PRIOR11 (*(volatile uint8_t *)(&_MBAR[0x8047]))
|
||||
#define MCF_DMA_PRIOR12 (*(volatile uint8_t *)(&_MBAR[0x8048]))
|
||||
#define MCF_DMA_PRIOR13 (*(volatile uint8_t *)(&_MBAR[0x8049]))
|
||||
#define MCF_DMA_PRIOR14 (*(volatile uint8_t *)(&_MBAR[0x804A]))
|
||||
#define MCF_DMA_PRIOR15 (*(volatile uint8_t *)(&_MBAR[0x804B]))
|
||||
#define MCF_DMA_PRIOR16 (*(volatile uint8_t *)(&_MBAR[0x804C]))
|
||||
#define MCF_DMA_PRIOR17 (*(volatile uint8_t *)(&_MBAR[0x804D]))
|
||||
#define MCF_DMA_PRIOR18 (*(volatile uint8_t *)(&_MBAR[0x804E]))
|
||||
#define MCF_DMA_PRIOR19 (*(volatile uint8_t *)(&_MBAR[0x804F]))
|
||||
#define MCF_DMA_PRIOR20 (*(volatile uint8_t *)(&_MBAR[0x8050]))
|
||||
#define MCF_DMA_PRIOR21 (*(volatile uint8_t *)(&_MBAR[0x8051]))
|
||||
#define MCF_DMA_PRIOR22 (*(volatile uint8_t *)(&_MBAR[0x8052]))
|
||||
#define MCF_DMA_PRIOR23 (*(volatile uint8_t *)(&_MBAR[0x8053]))
|
||||
#define MCF_DMA_PRIOR24 (*(volatile uint8_t *)(&_MBAR[0x8054]))
|
||||
#define MCF_DMA_PRIOR25 (*(volatile uint8_t *)(&_MBAR[0x8055]))
|
||||
#define MCF_DMA_PRIOR26 (*(volatile uint8_t *)(&_MBAR[0x8056]))
|
||||
#define MCF_DMA_PRIOR27 (*(volatile uint8_t *)(&_MBAR[0x8057]))
|
||||
#define MCF_DMA_PRIOR28 (*(volatile uint8_t *)(&_MBAR[0x8058]))
|
||||
#define MCF_DMA_PRIOR29 (*(volatile uint8_t *)(&_MBAR[0x8059]))
|
||||
#define MCF_DMA_PRIOR30 (*(volatile uint8_t *)(&_MBAR[0x805A]))
|
||||
#define MCF_DMA_PRIOR31 (*(volatile uint8_t *)(&_MBAR[0x805B]))
|
||||
#define MCF_DMA_IMCR (*(volatile uint32_t*)(&_MBAR[0x805C]))
|
||||
#define MCF_DMA_TSKSZ0 (*(volatile uint32_t*)(&_MBAR[0x8060]))
|
||||
#define MCF_DMA_TSKSZ1 (*(volatile uint32_t*)(&_MBAR[0x8064]))
|
||||
#define MCF_DMA_DBGCOMP0 (*(volatile uint32_t*)(&_MBAR[0x8070]))
|
||||
#define MCF_DMA_DBGCOMP2 (*(volatile uint32_t*)(&_MBAR[0x8074]))
|
||||
#define MCF_DMA_DBGCTL (*(volatile uint32_t*)(&_MBAR[0x8078]))
|
||||
#define MCF_DMA_TCR(x) (*(volatile uint16_t*)(&_MBAR[0x801C + ((x)*0x2)]))
|
||||
#define MCF_DMA_PRIOR(x) (*(volatile uint8_t *)(&_MBAR[0x803C + ((x)*0x1)]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_DMA_TASKBAR */
|
||||
#define MCF_DMA_TASKBAR_TASK_BASE_ADDRESS(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_DMA_CP */
|
||||
#define MCF_DMA_CP_DESCRIPTOR_POINTER(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_DMA_EP */
|
||||
#define MCF_DMA_EP_DESCRIPTOR_POINTER(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_DMA_VP */
|
||||
#define MCF_DMA_VP_VARIABLE_POINTER(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_DMA_PTD */
|
||||
#define MCF_DMA_PTD_PCTL0 (0x1)
|
||||
#define MCF_DMA_PTD_PCTL1 (0x2)
|
||||
#define MCF_DMA_PTD_PCTL13 (0x2000)
|
||||
#define MCF_DMA_PTD_PCTL14 (0x4000)
|
||||
#define MCF_DMA_PTD_PCTL15 (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_DMA_DIPR */
|
||||
#define MCF_DMA_DIPR_TASK(x) (((x)&0xFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_DMA_DIMR */
|
||||
#define MCF_DMA_DIMR_TASK(x) (((x)&0xFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_DMA_TCR */
|
||||
#define MCF_DMA_TCR_ASTSKNUM(x) (((x)&0xF)<<0)
|
||||
#define MCF_DMA_TCR_HLDINITNUM (0x20)
|
||||
#define MCF_DMA_TCR_HIPRITSKEN (0x40)
|
||||
#define MCF_DMA_TCR_ASTRT (0x80)
|
||||
#define MCF_DMA_TCR_INITNUM(x) (((x)&0x1F)<<0x8)
|
||||
#define MCF_DMA_TCR_ALWINIT (0x2000)
|
||||
#define MCF_DMA_TCR_V (0x4000)
|
||||
#define MCF_DMA_TCR_EN (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_DMA_PRIOR */
|
||||
#define MCF_DMA_PRIOR_PRI(x) (((x)&0x7)<<0)
|
||||
#define MCF_DMA_PRIOR_HLD (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_DMA_IMCR */
|
||||
#define MCF_DMA_IMCR_IMC16(x) (((x)&0x3)<<0)
|
||||
#define MCF_DMA_IMCR_IMC17(x) (((x)&0x3)<<0x2)
|
||||
#define MCF_DMA_IMCR_IMC18(x) (((x)&0x3)<<0x4)
|
||||
#define MCF_DMA_IMCR_IMC19(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_DMA_IMCR_IMC20(x) (((x)&0x3)<<0x8)
|
||||
#define MCF_DMA_IMCR_IMC21(x) (((x)&0x3)<<0xA)
|
||||
#define MCF_DMA_IMCR_IMC22(x) (((x)&0x3)<<0xC)
|
||||
#define MCF_DMA_IMCR_IMC23(x) (((x)&0x3)<<0xE)
|
||||
#define MCF_DMA_IMCR_IMC24(x) (((x)&0x3)<<0x10)
|
||||
#define MCF_DMA_IMCR_IMC25(x) (((x)&0x3)<<0x12)
|
||||
#define MCF_DMA_IMCR_IMC26(x) (((x)&0x3)<<0x14)
|
||||
#define MCF_DMA_IMCR_IMC27(x) (((x)&0x3)<<0x16)
|
||||
#define MCF_DMA_IMCR_IMC28(x) (((x)&0x3)<<0x18)
|
||||
#define MCF_DMA_IMCR_IMC29(x) (((x)&0x3)<<0x1A)
|
||||
#define MCF_DMA_IMCR_IMC30(x) (((x)&0x3)<<0x1C)
|
||||
#define MCF_DMA_IMCR_IMC31(x) (((x)&0x3)<<0x1E)
|
||||
|
||||
|
||||
#define MCF_DMA_IMCR_IMC16_FEC0RX (0x00000000)
|
||||
#define MCF_DMA_IMCR_IMC17_FEC0TX (0x00000000)
|
||||
#define MCF_DMA_IMCR_IMC18_FEC0RX (0x00000020)
|
||||
#define MCF_DMA_IMCR_IMC19_FEC0TX (0x00000080)
|
||||
#define MCF_DMA_IMCR_IMC20_FEC1RX (0x00000100)
|
||||
#define MCF_DMA_IMCR_IMC21_DREQ1 (0x00000000)
|
||||
#define MCF_DMA_IMCR_IMC21_FEC1TX (0x00000400)
|
||||
#define MCF_DMA_IMCR_IMC22_FEC0RX (0x00001000)
|
||||
#define MCF_DMA_IMCR_IMC23_FEC0TX (0x00004000)
|
||||
#define MCF_DMA_IMCR_IMC24_CTM0 (0x00010000)
|
||||
#define MCF_DMA_IMCR_IMC24_FEC1RX (0x00020000)
|
||||
#define MCF_DMA_IMCR_IMC25_CTM1 (0x00040000)
|
||||
#define MCF_DMA_IMCR_IMC25_FEC1TX (0x00080000)
|
||||
#define MCF_DMA_IMCR_IMC26_USBEP4 (0x00000000)
|
||||
#define MCF_DMA_IMCR_IMC26_CTM2 (0x00200000)
|
||||
#define MCF_DMA_IMCR_IMC27_USBEP5 (0x00000000)
|
||||
#define MCF_DMA_IMCR_IMC27_CTM3 (0x00800000)
|
||||
#define MCF_DMA_IMCR_IMC28_USBEP6 (0x00000000)
|
||||
#define MCF_DMA_IMCR_IMC28_CTM4 (0x01000000)
|
||||
#define MCF_DMA_IMCR_IMC28_DREQ1 (0x02000000)
|
||||
#define MCF_DMA_IMCR_IMC28_PSC2RX (0x03000000)
|
||||
#define MCF_DMA_IMCR_IMC29_DREQ1 (0x04000000)
|
||||
#define MCF_DMA_IMCR_IMC29_CTM5 (0x08000000)
|
||||
#define MCF_DMA_IMCR_IMC29_PSC2TX (0x0C000000)
|
||||
#define MCF_DMA_IMCR_IMC30_FEC1RX (0x00000000)
|
||||
#define MCF_DMA_IMCR_IMC30_CTM6 (0x10000000)
|
||||
#define MCF_DMA_IMCR_IMC30_PSC3RX (0x30000000)
|
||||
#define MCF_DMA_IMCR_IMC31_FEC1TX (0x00000000)
|
||||
#define MCF_DMA_IMCR_IMC31_CTM7 (0x80000000)
|
||||
#define MCF_DMA_IMCR_IMC31_PSC3TX (0xC0000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_DMA_TSKSZ0 */
|
||||
#define MCF_DMA_TSKSZ0_DSTSZ7(x) (((x)&0x3)<<0)
|
||||
#define MCF_DMA_TSKSZ0_SRCSZ7(x) (((x)&0x3)<<0x2)
|
||||
#define MCF_DMA_TSKSZ0_DSTSZ6(x) (((x)&0x3)<<0x4)
|
||||
#define MCF_DMA_TSKSZ0_SRCSZ6(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_DMA_TSKSZ0_DSTSZ5(x) (((x)&0x3)<<0x8)
|
||||
#define MCF_DMA_TSKSZ0_SRCSZ5(x) (((x)&0x3)<<0xA)
|
||||
#define MCF_DMA_TSKSZ0_DSTSZ4(x) (((x)&0x3)<<0xC)
|
||||
#define MCF_DMA_TSKSZ0_SRCSZ4(x) (((x)&0x3)<<0xE)
|
||||
#define MCF_DMA_TSKSZ0_DSTSZ3(x) (((x)&0x3)<<0x10)
|
||||
#define MCF_DMA_TSKSZ0_SRCSZ3(x) (((x)&0x3)<<0x12)
|
||||
#define MCF_DMA_TSKSZ0_DSTSZ2(x) (((x)&0x3)<<0x14)
|
||||
#define MCF_DMA_TSKSZ0_SRCSZ2(x) (((x)&0x3)<<0x16)
|
||||
#define MCF_DMA_TSKSZ0_DSTSZ1(x) (((x)&0x3)<<0x18)
|
||||
#define MCF_DMA_TSKSZ0_SRCSZ1(x) (((x)&0x3)<<0x1A)
|
||||
#define MCF_DMA_TSKSZ0_DSTSZ0(x) (((x)&0x3)<<0x1C)
|
||||
#define MCF_DMA_TSKSZ0_SRCSZ0(x) (((x)&0x3)<<0x1E)
|
||||
|
||||
/* Bit definitions and macros for MCF_DMA_TSKSZ1 */
|
||||
#define MCF_DMA_TSKSZ1_DSTSZ15(x) (((x)&0x3)<<0)
|
||||
#define MCF_DMA_TSKSZ1_SRCSZ15(x) (((x)&0x3)<<0x2)
|
||||
#define MCF_DMA_TSKSZ1_DSTSZ14(x) (((x)&0x3)<<0x4)
|
||||
#define MCF_DMA_TSKSZ1_SRCSZ14(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_DMA_TSKSZ1_DSTSZ13(x) (((x)&0x3)<<0x8)
|
||||
#define MCF_DMA_TSKSZ1_SRCSZ13(x) (((x)&0x3)<<0xA)
|
||||
#define MCF_DMA_TSKSZ1_DSTSZ12(x) (((x)&0x3)<<0xC)
|
||||
#define MCF_DMA_TSKSZ1_SRCSZ12(x) (((x)&0x3)<<0xE)
|
||||
#define MCF_DMA_TSKSZ1_DSTSZ11(x) (((x)&0x3)<<0x10)
|
||||
#define MCF_DMA_TSKSZ1_SRCSZ11(x) (((x)&0x3)<<0x12)
|
||||
#define MCF_DMA_TSKSZ1_DSTSZ10(x) (((x)&0x3)<<0x14)
|
||||
#define MCF_DMA_TSKSZ1_SRCSZ10(x) (((x)&0x3)<<0x16)
|
||||
#define MCF_DMA_TSKSZ1_DSTSZ9(x) (((x)&0x3)<<0x18)
|
||||
#define MCF_DMA_TSKSZ1_SRCSZ9(x) (((x)&0x3)<<0x1A)
|
||||
#define MCF_DMA_TSKSZ1_DSTSZ8(x) (((x)&0x3)<<0x1C)
|
||||
#define MCF_DMA_TSKSZ1_SRCSZ8(x) (((x)&0x3)<<0x1E)
|
||||
|
||||
/* Bit definitions and macros for MCF_DMA_DBGCOMP0 */
|
||||
#define MCF_DMA_DBGCOMP0_COMPARATOR_VALUE(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_DMA_DBGCOMP2 */
|
||||
#define MCF_DMA_DBGCOMP2_COMPARATOR_VALUE(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_DMA_DBGCTL */
|
||||
#define MCF_DMA_DBGCTL_I (0x2)
|
||||
#define MCF_DMA_DBGCTL_E (0x4)
|
||||
#define MCF_DMA_DBGCTL_AND_OR (0x80)
|
||||
#define MCF_DMA_DBGCTL_COMPARATOR_TYPE_2(x) (((x)&0x7)<<0x8)
|
||||
#define MCF_DMA_DBGCTL_COMPARATOR_TYPE_1(x) (((x)&0x7)<<0xB)
|
||||
#define MCF_DMA_DBGCTL_B (0x4000)
|
||||
#define MCF_DMA_DBGCTL_AA (0x8000)
|
||||
#define MCF_DMA_DBGCTL_BLOCK_TASKS(x) (((x)&0xFFFF)<<0x10)
|
||||
|
||||
|
||||
#endif /* __MCF5475_DMA_H__ */
|
||||
123
include/MCF5475_EPORT.h
Normal file
123
include/MCF5475_EPORT.h
Normal file
@@ -0,0 +1,123 @@
|
||||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.81
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF5475_EPORT_H__
|
||||
#define __MCF5475_EPORT_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Edge Port Module (EPORT)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_EPORT_EPPAR (*(volatile uint16_t*)(&_MBAR[0xF00]))
|
||||
#define MCF_EPORT_EPDDR (*(volatile uint8_t *)(&_MBAR[0xF04]))
|
||||
#define MCF_EPORT_EPIER (*(volatile uint8_t *)(&_MBAR[0xF05]))
|
||||
#define MCF_EPORT_EPDR (*(volatile uint8_t *)(&_MBAR[0xF08]))
|
||||
#define MCF_EPORT_EPPDR (*(volatile uint8_t *)(&_MBAR[0xF09]))
|
||||
#define MCF_EPORT_EPFR (*(volatile uint8_t *)(&_MBAR[0xF0C]))
|
||||
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_EPORT_EPPAR */
|
||||
#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x3)<<0x2)
|
||||
#define MCF_EPORT_EPPAR_EPPA1_LEVEL (0)
|
||||
#define MCF_EPORT_EPPAR_EPPA1_RISING (0x4)
|
||||
#define MCF_EPORT_EPPAR_EPPA1_FALLING (0x8)
|
||||
#define MCF_EPORT_EPPAR_EPPA1_BOTH (0xC)
|
||||
#define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x3)<<0x4)
|
||||
#define MCF_EPORT_EPPAR_EPPA2_LEVEL (0)
|
||||
#define MCF_EPORT_EPPAR_EPPA2_RISING (0x10)
|
||||
#define MCF_EPORT_EPPAR_EPPA2_FALLING (0x20)
|
||||
#define MCF_EPORT_EPPAR_EPPA2_BOTH (0x30)
|
||||
#define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_EPORT_EPPAR_EPPA3_LEVEL (0)
|
||||
#define MCF_EPORT_EPPAR_EPPA3_RISING (0x40)
|
||||
#define MCF_EPORT_EPPAR_EPPA3_FALLING (0x80)
|
||||
#define MCF_EPORT_EPPAR_EPPA3_BOTH (0xC0)
|
||||
#define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x3)<<0x8)
|
||||
#define MCF_EPORT_EPPAR_EPPA4_LEVEL (0)
|
||||
#define MCF_EPORT_EPPAR_EPPA4_RISING (0x100)
|
||||
#define MCF_EPORT_EPPAR_EPPA4_FALLING (0x200)
|
||||
#define MCF_EPORT_EPPAR_EPPA4_BOTH (0x300)
|
||||
#define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x3)<<0xA)
|
||||
#define MCF_EPORT_EPPAR_EPPA5_LEVEL (0)
|
||||
#define MCF_EPORT_EPPAR_EPPA5_RISING (0x400)
|
||||
#define MCF_EPORT_EPPAR_EPPA5_FALLING (0x800)
|
||||
#define MCF_EPORT_EPPAR_EPPA5_BOTH (0xC00)
|
||||
#define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x3)<<0xC)
|
||||
#define MCF_EPORT_EPPAR_EPPA6_LEVEL (0)
|
||||
#define MCF_EPORT_EPPAR_EPPA6_RISING (0x1000)
|
||||
#define MCF_EPORT_EPPAR_EPPA6_FALLING (0x2000)
|
||||
#define MCF_EPORT_EPPAR_EPPA6_BOTH (0x3000)
|
||||
#define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x3)<<0xE)
|
||||
#define MCF_EPORT_EPPAR_EPPA7_LEVEL (0)
|
||||
#define MCF_EPORT_EPPAR_EPPA7_RISING (0x4000)
|
||||
#define MCF_EPORT_EPPAR_EPPA7_FALLING (0x8000)
|
||||
#define MCF_EPORT_EPPAR_EPPA7_BOTH (0xC000)
|
||||
#define MCF_EPORT_EPPAR_LEVEL (0)
|
||||
#define MCF_EPORT_EPPAR_RISING (0x1)
|
||||
#define MCF_EPORT_EPPAR_FALLING (0x2)
|
||||
#define MCF_EPORT_EPPAR_BOTH (0x3)
|
||||
|
||||
/* Bit definitions and macros for MCF_EPORT_EPDDR */
|
||||
#define MCF_EPORT_EPDDR_EPDD1 (0x2)
|
||||
#define MCF_EPORT_EPDDR_EPDD2 (0x4)
|
||||
#define MCF_EPORT_EPDDR_EPDD3 (0x8)
|
||||
#define MCF_EPORT_EPDDR_EPDD4 (0x10)
|
||||
#define MCF_EPORT_EPDDR_EPDD5 (0x20)
|
||||
#define MCF_EPORT_EPDDR_EPDD6 (0x40)
|
||||
#define MCF_EPORT_EPDDR_EPDD7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_EPORT_EPIER */
|
||||
#define MCF_EPORT_EPIER_EPIE1 (0x2)
|
||||
#define MCF_EPORT_EPIER_EPIE2 (0x4)
|
||||
#define MCF_EPORT_EPIER_EPIE3 (0x8)
|
||||
#define MCF_EPORT_EPIER_EPIE4 (0x10)
|
||||
#define MCF_EPORT_EPIER_EPIE5 (0x20)
|
||||
#define MCF_EPORT_EPIER_EPIE6 (0x40)
|
||||
#define MCF_EPORT_EPIER_EPIE7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_EPORT_EPDR */
|
||||
#define MCF_EPORT_EPDR_EPD1 (0x2)
|
||||
#define MCF_EPORT_EPDR_EPD2 (0x4)
|
||||
#define MCF_EPORT_EPDR_EPD3 (0x8)
|
||||
#define MCF_EPORT_EPDR_EPD4 (0x10)
|
||||
#define MCF_EPORT_EPDR_EPD5 (0x20)
|
||||
#define MCF_EPORT_EPDR_EPD6 (0x40)
|
||||
#define MCF_EPORT_EPDR_EPD7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_EPORT_EPPDR */
|
||||
#define MCF_EPORT_EPPDR_EPPD1 (0x2)
|
||||
#define MCF_EPORT_EPPDR_EPPD2 (0x4)
|
||||
#define MCF_EPORT_EPPDR_EPPD3 (0x8)
|
||||
#define MCF_EPORT_EPPDR_EPPD4 (0x10)
|
||||
#define MCF_EPORT_EPPDR_EPPD5 (0x20)
|
||||
#define MCF_EPORT_EPPDR_EPPD6 (0x40)
|
||||
#define MCF_EPORT_EPPDR_EPPD7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_EPORT_EPFR */
|
||||
#define MCF_EPORT_EPFR_EPF1 (0x2)
|
||||
#define MCF_EPORT_EPFR_EPF2 (0x4)
|
||||
#define MCF_EPORT_EPFR_EPF3 (0x8)
|
||||
#define MCF_EPORT_EPFR_EPF4 (0x10)
|
||||
#define MCF_EPORT_EPFR_EPF5 (0x20)
|
||||
#define MCF_EPORT_EPFR_EPF6 (0x40)
|
||||
#define MCF_EPORT_EPFR_EPF7 (0x80)
|
||||
|
||||
|
||||
#endif /* __MCF5475_EPORT_H__ */
|
||||
100
include/MCF5475_FBCS.h
Normal file
100
include/MCF5475_FBCS.h
Normal file
@@ -0,0 +1,100 @@
|
||||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.81
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF5475_FBCS_H__
|
||||
#define __MCF5475_FBCS_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* FlexBus Chip Select Module (FBCS)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_FBCS0_CSAR (*(volatile uint32_t*)(&_MBAR[0x500]))
|
||||
#define MCF_FBCS0_CSMR (*(volatile uint32_t*)(&_MBAR[0x504]))
|
||||
#define MCF_FBCS0_CSCR (*(volatile uint32_t*)(&_MBAR[0x508]))
|
||||
|
||||
#define MCF_FBCS1_CSAR (*(volatile uint32_t*)(&_MBAR[0x50C]))
|
||||
#define MCF_FBCS1_CSMR (*(volatile uint32_t*)(&_MBAR[0x510]))
|
||||
#define MCF_FBCS1_CSCR (*(volatile uint32_t*)(&_MBAR[0x514]))
|
||||
|
||||
#define MCF_FBCS2_CSAR (*(volatile uint32_t*)(&_MBAR[0x518]))
|
||||
#define MCF_FBCS2_CSMR (*(volatile uint32_t*)(&_MBAR[0x51C]))
|
||||
#define MCF_FBCS2_CSCR (*(volatile uint32_t*)(&_MBAR[0x520]))
|
||||
|
||||
#define MCF_FBCS3_CSAR (*(volatile uint32_t*)(&_MBAR[0x524]))
|
||||
#define MCF_FBCS3_CSMR (*(volatile uint32_t*)(&_MBAR[0x528]))
|
||||
#define MCF_FBCS3_CSCR (*(volatile uint32_t*)(&_MBAR[0x52C]))
|
||||
|
||||
#define MCF_FBCS4_CSAR (*(volatile uint32_t*)(&_MBAR[0x530]))
|
||||
#define MCF_FBCS4_CSMR (*(volatile uint32_t*)(&_MBAR[0x534]))
|
||||
#define MCF_FBCS4_CSCR (*(volatile uint32_t*)(&_MBAR[0x538]))
|
||||
|
||||
#define MCF_FBCS5_CSAR (*(volatile uint32_t*)(&_MBAR[0x53C]))
|
||||
#define MCF_FBCS5_CSMR (*(volatile uint32_t*)(&_MBAR[0x540]))
|
||||
#define MCF_FBCS5_CSCR (*(volatile uint32_t*)(&_MBAR[0x544]))
|
||||
|
||||
#define MCF_FBCS_CSAR(x) (*(volatile uint32_t*)(&_MBAR[0x500 + ((x)*0xC)]))
|
||||
#define MCF_FBCS_CSMR(x) (*(volatile uint32_t*)(&_MBAR[0x504 + ((x)*0xC)]))
|
||||
#define MCF_FBCS_CSCR(x) (*(volatile uint32_t*)(&_MBAR[0x508 + ((x)*0xC)]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_FBCS_CSAR */
|
||||
#define MCF_FBCS_CSAR_BA(x) ((x)&0xFFFF0000)
|
||||
|
||||
/* Bit definitions and macros for MCF_FBCS_CSMR */
|
||||
#define MCF_FBCS_CSMR_V (0x1)
|
||||
#define MCF_FBCS_CSMR_WP (0x100)
|
||||
#define MCF_FBCS_CSMR_BAM(x) (((x)&0xFFFF)<<0x10)
|
||||
#define MCF_FBCS_CSMR_BAM_4G (0xFFFF0000)
|
||||
#define MCF_FBCS_CSMR_BAM_2G (0x7FFF0000)
|
||||
#define MCF_FBCS_CSMR_BAM_1G (0x3FFF0000)
|
||||
#define MCF_FBCS_CSMR_BAM_1024M (0x3FFF0000)
|
||||
#define MCF_FBCS_CSMR_BAM_512M (0x1FFF0000)
|
||||
#define MCF_FBCS_CSMR_BAM_256M (0xFFF0000)
|
||||
#define MCF_FBCS_CSMR_BAM_128M (0x7FF0000)
|
||||
#define MCF_FBCS_CSMR_BAM_64M (0x3FF0000)
|
||||
#define MCF_FBCS_CSMR_BAM_32M (0x1FF0000)
|
||||
#define MCF_FBCS_CSMR_BAM_16M (0xFF0000)
|
||||
#define MCF_FBCS_CSMR_BAM_8M (0x7F0000)
|
||||
#define MCF_FBCS_CSMR_BAM_4M (0x3F0000)
|
||||
#define MCF_FBCS_CSMR_BAM_2M (0x1F0000)
|
||||
#define MCF_FBCS_CSMR_BAM_1M (0xF0000)
|
||||
#define MCF_FBCS_CSMR_BAM_1024K (0xF0000)
|
||||
#define MCF_FBCS_CSMR_BAM_512K (0x70000)
|
||||
#define MCF_FBCS_CSMR_BAM_256K (0x30000)
|
||||
#define MCF_FBCS_CSMR_BAM_128K (0x10000)
|
||||
#define MCF_FBCS_CSMR_BAM_64K (0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FBCS_CSCR */
|
||||
#define MCF_FBCS_CSCR_BSTW (0x8)
|
||||
#define MCF_FBCS_CSCR_BSTR (0x10)
|
||||
#define MCF_FBCS_CSCR_BEM (0x20)
|
||||
#define MCF_FBCS_CSCR_PS(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_FBCS_CSCR_PS_32 (0)
|
||||
#define MCF_FBCS_CSCR_PS_8 (0x40)
|
||||
#define MCF_FBCS_CSCR_PS_16 (0x80)
|
||||
#define MCF_FBCS_CSCR_AA (0x100)
|
||||
#define MCF_FBCS_CSCR_WS(x) (((x)&0x3F)<<0xA)
|
||||
#define MCF_FBCS_CSCR_WRAH(x) (((x)&0x3)<<0x10)
|
||||
#define MCF_FBCS_CSCR_RDAH(x) (((x)&0x3)<<0x12)
|
||||
#define MCF_FBCS_CSCR_ASET(x) (((x)&0x3)<<0x14)
|
||||
#define MCF_FBCS_CSCR_SWSEN (0x800000)
|
||||
#define MCF_FBCS_CSCR_SWS(x) (((x)&0x3F)<<0x1A)
|
||||
|
||||
|
||||
#endif /* __MCF5475_FBCS_H__ */
|
||||
680
include/MCF5475_FEC.h
Normal file
680
include/MCF5475_FEC.h
Normal file
@@ -0,0 +1,680 @@
|
||||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.81
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF5475_FEC_H__
|
||||
#define __MCF5475_FEC_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Fast Ethernet Controller(FEC)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_FEC0_EIR (*(volatile uint32_t*)(&_MBAR[0x9004]))
|
||||
#define MCF_FEC0_EIMR (*(volatile uint32_t*)(&_MBAR[0x9008]))
|
||||
#define MCF_FEC0_ECR (*(volatile uint32_t*)(&_MBAR[0x9024]))
|
||||
#define MCF_FEC0_MMFR (*(volatile uint32_t*)(&_MBAR[0x9040]))
|
||||
#define MCF_FEC0_MSCR (*(volatile uint32_t*)(&_MBAR[0x9044]))
|
||||
#define MCF_FEC0_MIBC (*(volatile uint32_t*)(&_MBAR[0x9064]))
|
||||
#define MCF_FEC0_RCR (*(volatile uint32_t*)(&_MBAR[0x9084]))
|
||||
#define MCF_FEC0_RHR (*(volatile uint32_t*)(&_MBAR[0x9088]))
|
||||
#define MCF_FEC0_TCR (*(volatile uint32_t*)(&_MBAR[0x90C4]))
|
||||
#define MCF_FEC0_PALR (*(volatile uint32_t*)(&_MBAR[0x90E4]))
|
||||
#define MCF_FEC0_PAHR (*(volatile uint32_t*)(&_MBAR[0x90E8]))
|
||||
#define MCF_FEC0_OPD (*(volatile uint32_t*)(&_MBAR[0x90EC]))
|
||||
#define MCF_FEC0_IAUR (*(volatile uint32_t*)(&_MBAR[0x9118]))
|
||||
#define MCF_FEC0_IALR (*(volatile uint32_t*)(&_MBAR[0x911C]))
|
||||
#define MCF_FEC0_GAUR (*(volatile uint32_t*)(&_MBAR[0x9120]))
|
||||
#define MCF_FEC0_GALR (*(volatile uint32_t*)(&_MBAR[0x9124]))
|
||||
#define MCF_FEC0_FECTFWR (*(volatile uint32_t*)(&_MBAR[0x9144]))
|
||||
#define MCF_FEC0_FECRFDR (*(volatile uint32_t*)(&_MBAR[0x9184]))
|
||||
#define MCF_FEC0_FECRFSR (*(volatile uint32_t*)(&_MBAR[0x9188]))
|
||||
#define MCF_FEC0_FECRFCR (*(volatile uint32_t*)(&_MBAR[0x918C]))
|
||||
#define MCF_FEC0_FECRLRFP (*(volatile uint32_t*)(&_MBAR[0x9190]))
|
||||
#define MCF_FEC0_FECRLWFP (*(volatile uint32_t*)(&_MBAR[0x9194]))
|
||||
#define MCF_FEC0_FECRFAR (*(volatile uint32_t*)(&_MBAR[0x9198]))
|
||||
#define MCF_FEC0_FECRFRP (*(volatile uint32_t*)(&_MBAR[0x919C]))
|
||||
#define MCF_FEC0_FECRFWP (*(volatile uint32_t*)(&_MBAR[0x91A0]))
|
||||
#define MCF_FEC0_FECTFDR (*(volatile uint32_t*)(&_MBAR[0x91A4]))
|
||||
#define MCF_FEC0_FECTFSR (*(volatile uint32_t*)(&_MBAR[0x91A8]))
|
||||
#define MCF_FEC0_FECTFCR (*(volatile uint32_t*)(&_MBAR[0x91AC]))
|
||||
#define MCF_FEC0_FECTLRFP (*(volatile uint32_t*)(&_MBAR[0x91B0]))
|
||||
#define MCF_FEC0_FECTLWFP (*(volatile uint32_t*)(&_MBAR[0x91B4]))
|
||||
#define MCF_FEC0_FECTFAR (*(volatile uint32_t*)(&_MBAR[0x91B8]))
|
||||
#define MCF_FEC0_FECTFRP (*(volatile uint32_t*)(&_MBAR[0x91BC]))
|
||||
#define MCF_FEC0_FECTFWP (*(volatile uint32_t*)(&_MBAR[0x91C0]))
|
||||
#define MCF_FEC0_FECFRST (*(volatile uint32_t*)(&_MBAR[0x91C4]))
|
||||
#define MCF_FEC0_FECCTCWR (*(volatile uint32_t*)(&_MBAR[0x91C8]))
|
||||
#define MCF_FEC0_RMON_T_DROP (*(volatile uint32_t*)(&_MBAR[0x9200]))
|
||||
#define MCF_FEC0_RMON_T_PACKETS (*(volatile uint32_t*)(&_MBAR[0x9204]))
|
||||
#define MCF_FEC0_RMON_T_BC_PKT (*(volatile uint32_t*)(&_MBAR[0x9208]))
|
||||
#define MCF_FEC0_RMON_T_MC_PKT (*(volatile uint32_t*)(&_MBAR[0x920C]))
|
||||
#define MCF_FEC0_RMON_T_CRC_ALIGN (*(volatile uint32_t*)(&_MBAR[0x9210]))
|
||||
#define MCF_FEC0_RMON_T_UNDERSIZE (*(volatile uint32_t*)(&_MBAR[0x9214]))
|
||||
#define MCF_FEC0_RMON_T_OVERSIZE (*(volatile uint32_t*)(&_MBAR[0x9218]))
|
||||
#define MCF_FEC0_RMON_T_FRAG (*(volatile uint32_t*)(&_MBAR[0x921C]))
|
||||
#define MCF_FEC0_RMON_T_JAB (*(volatile uint32_t*)(&_MBAR[0x9220]))
|
||||
#define MCF_FEC0_RMON_T_COL (*(volatile uint32_t*)(&_MBAR[0x9224]))
|
||||
#define MCF_FEC0_RMON_T_P64 (*(volatile uint32_t*)(&_MBAR[0x9228]))
|
||||
#define MCF_FEC0_RMON_T_P65TO127 (*(volatile uint32_t*)(&_MBAR[0x922C]))
|
||||
#define MCF_FEC0_RMON_T_P128TO255 (*(volatile uint32_t*)(&_MBAR[0x9230]))
|
||||
#define MCF_FEC0_RMON_T_P256TO511 (*(volatile uint32_t*)(&_MBAR[0x9234]))
|
||||
#define MCF_FEC0_RMON_T_P512TO1023 (*(volatile uint32_t*)(&_MBAR[0x9238]))
|
||||
#define MCF_FEC0_RMON_T_P1024TO2047 (*(volatile uint32_t*)(&_MBAR[0x923C]))
|
||||
#define MCF_FEC0_RMON_T_P_GTE2048 (*(volatile uint32_t*)(&_MBAR[0x9240]))
|
||||
#define MCF_FEC0_RMON_T_OCTETS (*(volatile uint32_t*)(&_MBAR[0x9244]))
|
||||
#define MCF_FEC0_IEEE_T_DROP (*(volatile uint32_t*)(&_MBAR[0x9248]))
|
||||
#define MCF_FEC0_IEEE_T_FRAME_OK (*(volatile uint32_t*)(&_MBAR[0x924C]))
|
||||
#define MCF_FEC0_IEEE_T_1COL (*(volatile uint32_t*)(&_MBAR[0x9250]))
|
||||
#define MCF_FEC0_IEEE_T_MCOL (*(volatile uint32_t*)(&_MBAR[0x9254]))
|
||||
#define MCF_FEC0_IEEE_T_DEF (*(volatile uint32_t*)(&_MBAR[0x9258]))
|
||||
#define MCF_FEC0_IEEE_T_LCOL (*(volatile uint32_t*)(&_MBAR[0x925C]))
|
||||
#define MCF_FEC0_IEEE_T_EXCOL (*(volatile uint32_t*)(&_MBAR[0x9260]))
|
||||
#define MCF_FEC0_IEEE_T_MACERR (*(volatile uint32_t*)(&_MBAR[0x9264]))
|
||||
#define MCF_FEC0_IEEE_T_CSERR (*(volatile uint32_t*)(&_MBAR[0x9268]))
|
||||
#define MCF_FEC0_IEEE_T_SQE (*(volatile uint32_t*)(&_MBAR[0x926C]))
|
||||
#define MCF_FEC0_IEEE_T_FDXFC (*(volatile uint32_t*)(&_MBAR[0x9270]))
|
||||
#define MCF_FEC0_IEEE_T_OCTETS_OK (*(volatile uint32_t*)(&_MBAR[0x9274]))
|
||||
#define MCF_FEC0_RMON_R_DROP (*(volatile uint32_t*)(&_MBAR[0x9280]))
|
||||
#define MCF_FEC0_RMON_R_PACKETS (*(volatile uint32_t*)(&_MBAR[0x9284]))
|
||||
#define MCF_FEC0_RMON_R_BC_PKT (*(volatile uint32_t*)(&_MBAR[0x9288]))
|
||||
#define MCF_FEC0_RMON_R_MC_PKT (*(volatile uint32_t*)(&_MBAR[0x928C]))
|
||||
#define MCF_FEC0_RMON_R_CRC_ALIGN (*(volatile uint32_t*)(&_MBAR[0x9290]))
|
||||
#define MCF_FEC0_RMON_R_UNDERSIZE (*(volatile uint32_t*)(&_MBAR[0x9294]))
|
||||
#define MCF_FEC0_RMON_R_OVERSIZE (*(volatile uint32_t*)(&_MBAR[0x9298]))
|
||||
#define MCF_FEC0_RMON_R_FRAG (*(volatile uint32_t*)(&_MBAR[0x929C]))
|
||||
#define MCF_FEC0_RMON_R_JAB (*(volatile uint32_t*)(&_MBAR[0x92A0]))
|
||||
#define MCF_FEC0_RMON_R_RESVD_0 (*(volatile uint32_t*)(&_MBAR[0x92A4]))
|
||||
#define MCF_FEC0_RMON_R_P64 (*(volatile uint32_t*)(&_MBAR[0x92A8]))
|
||||
#define MCF_FEC0_RMON_R_P65TO127 (*(volatile uint32_t*)(&_MBAR[0x92AC]))
|
||||
#define MCF_FEC0_RMON_R_P128TO255 (*(volatile uint32_t*)(&_MBAR[0x92B0]))
|
||||
#define MCF_FEC0_RMON_R_P256TO511 (*(volatile uint32_t*)(&_MBAR[0x92B4]))
|
||||
#define MCF_FEC0_RMON_R_P512TO1023 (*(volatile uint32_t*)(&_MBAR[0x92B8]))
|
||||
#define MCF_FEC0_RMON_R_P1024TO2047 (*(volatile uint32_t*)(&_MBAR[0x92BC]))
|
||||
#define MCF_FEC0_RMON_R_P_GTE2048 (*(volatile uint32_t*)(&_MBAR[0x92C0]))
|
||||
#define MCF_FEC0_RMON_R_OCTETS (*(volatile uint32_t*)(&_MBAR[0x92C4]))
|
||||
#define MCF_FEC0_IEEE_R_DROP (*(volatile uint32_t*)(&_MBAR[0x92C8]))
|
||||
#define MCF_FEC0_IEEE_R_FRAME_OK (*(volatile uint32_t*)(&_MBAR[0x92CC]))
|
||||
#define MCF_FEC0_IEEE_R_CRC (*(volatile uint32_t*)(&_MBAR[0x92D0]))
|
||||
#define MCF_FEC0_IEEE_R_ALIGN (*(volatile uint32_t*)(&_MBAR[0x92D4]))
|
||||
#define MCF_FEC0_IEEE_R_MACERR (*(volatile uint32_t*)(&_MBAR[0x92D8]))
|
||||
#define MCF_FEC0_IEEE_R_FDXFC (*(volatile uint32_t*)(&_MBAR[0x92DC]))
|
||||
#define MCF_FEC0_IEEE_R_OCTETS_OK (*(volatile uint32_t*)(&_MBAR[0x92E0]))
|
||||
|
||||
#define MCF_FEC1_EIR (*(volatile uint32_t*)(&_MBAR[0x9804]))
|
||||
#define MCF_FEC1_EIMR (*(volatile uint32_t*)(&_MBAR[0x9808]))
|
||||
#define MCF_FEC1_ECR (*(volatile uint32_t*)(&_MBAR[0x9824]))
|
||||
#define MCF_FEC1_MMFR (*(volatile uint32_t*)(&_MBAR[0x9840]))
|
||||
#define MCF_FEC1_MSCR (*(volatile uint32_t*)(&_MBAR[0x9844]))
|
||||
#define MCF_FEC1_MIBC (*(volatile uint32_t*)(&_MBAR[0x9864]))
|
||||
#define MCF_FEC1_RCR (*(volatile uint32_t*)(&_MBAR[0x9884]))
|
||||
#define MCF_FEC1_RHR (*(volatile uint32_t*)(&_MBAR[0x9888]))
|
||||
#define MCF_FEC1_TCR (*(volatile uint32_t*)(&_MBAR[0x98C4]))
|
||||
#define MCF_FEC1_PALR (*(volatile uint32_t*)(&_MBAR[0x98E4]))
|
||||
#define MCF_FEC1_PAHR (*(volatile uint32_t*)(&_MBAR[0x98E8]))
|
||||
#define MCF_FEC1_OPD (*(volatile uint32_t*)(&_MBAR[0x98EC]))
|
||||
#define MCF_FEC1_IAUR (*(volatile uint32_t*)(&_MBAR[0x9918]))
|
||||
#define MCF_FEC1_IALR (*(volatile uint32_t*)(&_MBAR[0x991C]))
|
||||
#define MCF_FEC1_GAUR (*(volatile uint32_t*)(&_MBAR[0x9920]))
|
||||
#define MCF_FEC1_GALR (*(volatile uint32_t*)(&_MBAR[0x9924]))
|
||||
#define MCF_FEC1_FECTFWR (*(volatile uint32_t*)(&_MBAR[0x9944]))
|
||||
#define MCF_FEC1_FECRFDR (*(volatile uint32_t*)(&_MBAR[0x9984]))
|
||||
#define MCF_FEC1_FECRFSR (*(volatile uint32_t*)(&_MBAR[0x9988]))
|
||||
#define MCF_FEC1_FECRFCR (*(volatile uint32_t*)(&_MBAR[0x998C]))
|
||||
#define MCF_FEC1_FECRLRFP (*(volatile uint32_t*)(&_MBAR[0x9990]))
|
||||
#define MCF_FEC1_FECRLWFP (*(volatile uint32_t*)(&_MBAR[0x9994]))
|
||||
#define MCF_FEC1_FECRFAR (*(volatile uint32_t*)(&_MBAR[0x9998]))
|
||||
#define MCF_FEC1_FECRFRP (*(volatile uint32_t*)(&_MBAR[0x999C]))
|
||||
#define MCF_FEC1_FECRFWP (*(volatile uint32_t*)(&_MBAR[0x99A0]))
|
||||
#define MCF_FEC1_FECTFDR (*(volatile uint32_t*)(&_MBAR[0x99A4]))
|
||||
#define MCF_FEC1_FECTFSR (*(volatile uint32_t*)(&_MBAR[0x99A8]))
|
||||
#define MCF_FEC1_FECTFCR (*(volatile uint32_t*)(&_MBAR[0x99AC]))
|
||||
#define MCF_FEC1_FECTLRFP (*(volatile uint32_t*)(&_MBAR[0x99B0]))
|
||||
#define MCF_FEC1_FECTLWFP (*(volatile uint32_t*)(&_MBAR[0x99B4]))
|
||||
#define MCF_FEC1_FECTFAR (*(volatile uint32_t*)(&_MBAR[0x99B8]))
|
||||
#define MCF_FEC1_FECTFRP (*(volatile uint32_t*)(&_MBAR[0x99BC]))
|
||||
#define MCF_FEC1_FECTFWP (*(volatile uint32_t*)(&_MBAR[0x99C0]))
|
||||
#define MCF_FEC1_FECFRST (*(volatile uint32_t*)(&_MBAR[0x99C4]))
|
||||
#define MCF_FEC1_FECCTCWR (*(volatile uint32_t*)(&_MBAR[0x99C8]))
|
||||
#define MCF_FEC1_RMON_T_DROP (*(volatile uint32_t*)(&_MBAR[0x9A00]))
|
||||
#define MCF_FEC1_RMON_T_PACKETS (*(volatile uint32_t*)(&_MBAR[0x9A04]))
|
||||
#define MCF_FEC1_RMON_T_BC_PKT (*(volatile uint32_t*)(&_MBAR[0x9A08]))
|
||||
#define MCF_FEC1_RMON_T_MC_PKT (*(volatile uint32_t*)(&_MBAR[0x9A0C]))
|
||||
#define MCF_FEC1_RMON_T_CRC_ALIGN (*(volatile uint32_t*)(&_MBAR[0x9A10]))
|
||||
#define MCF_FEC1_RMON_T_UNDERSIZE (*(volatile uint32_t*)(&_MBAR[0x9A14]))
|
||||
#define MCF_FEC1_RMON_T_OVERSIZE (*(volatile uint32_t*)(&_MBAR[0x9A18]))
|
||||
#define MCF_FEC1_RMON_T_FRAG (*(volatile uint32_t*)(&_MBAR[0x9A1C]))
|
||||
#define MCF_FEC1_RMON_T_JAB (*(volatile uint32_t*)(&_MBAR[0x9A20]))
|
||||
#define MCF_FEC1_RMON_T_COL (*(volatile uint32_t*)(&_MBAR[0x9A24]))
|
||||
#define MCF_FEC1_RMON_T_P64 (*(volatile uint32_t*)(&_MBAR[0x9A28]))
|
||||
#define MCF_FEC1_RMON_T_P65TO127 (*(volatile uint32_t*)(&_MBAR[0x9A2C]))
|
||||
#define MCF_FEC1_RMON_T_P128TO255 (*(volatile uint32_t*)(&_MBAR[0x9A30]))
|
||||
#define MCF_FEC1_RMON_T_P256TO511 (*(volatile uint32_t*)(&_MBAR[0x9A34]))
|
||||
#define MCF_FEC1_RMON_T_P512TO1023 (*(volatile uint32_t*)(&_MBAR[0x9A38]))
|
||||
#define MCF_FEC1_RMON_T_P1024TO2047 (*(volatile uint32_t*)(&_MBAR[0x9A3C]))
|
||||
#define MCF_FEC1_RMON_T_P_GTE2048 (*(volatile uint32_t*)(&_MBAR[0x9A40]))
|
||||
#define MCF_FEC1_RMON_T_OCTETS (*(volatile uint32_t*)(&_MBAR[0x9A44]))
|
||||
#define MCF_FEC1_IEEE_T_DROP (*(volatile uint32_t*)(&_MBAR[0x9A48]))
|
||||
#define MCF_FEC1_IEEE_T_FRAME_OK (*(volatile uint32_t*)(&_MBAR[0x9A4C]))
|
||||
#define MCF_FEC1_IEEE_T_1COL (*(volatile uint32_t*)(&_MBAR[0x9A50]))
|
||||
#define MCF_FEC1_IEEE_T_MCOL (*(volatile uint32_t*)(&_MBAR[0x9A54]))
|
||||
#define MCF_FEC1_IEEE_T_DEF (*(volatile uint32_t*)(&_MBAR[0x9A58]))
|
||||
#define MCF_FEC1_IEEE_T_LCOL (*(volatile uint32_t*)(&_MBAR[0x9A5C]))
|
||||
#define MCF_FEC1_IEEE_T_EXCOL (*(volatile uint32_t*)(&_MBAR[0x9A60]))
|
||||
#define MCF_FEC1_IEEE_T_MACERR (*(volatile uint32_t*)(&_MBAR[0x9A64]))
|
||||
#define MCF_FEC1_IEEE_T_CSERR (*(volatile uint32_t*)(&_MBAR[0x9A68]))
|
||||
#define MCF_FEC1_IEEE_T_SQE (*(volatile uint32_t*)(&_MBAR[0x9A6C]))
|
||||
#define MCF_FEC1_IEEE_T_FDXFC (*(volatile uint32_t*)(&_MBAR[0x9A70]))
|
||||
#define MCF_FEC1_IEEE_T_OCTETS_OK (*(volatile uint32_t*)(&_MBAR[0x9A74]))
|
||||
#define MCF_FEC1_RMON_R_DROP (*(volatile uint32_t*)(&_MBAR[0x9A80]))
|
||||
#define MCF_FEC1_RMON_R_PACKETS (*(volatile uint32_t*)(&_MBAR[0x9A84]))
|
||||
#define MCF_FEC1_RMON_R_BC_PKT (*(volatile uint32_t*)(&_MBAR[0x9A88]))
|
||||
#define MCF_FEC1_RMON_R_MC_PKT (*(volatile uint32_t*)(&_MBAR[0x9A8C]))
|
||||
#define MCF_FEC1_RMON_R_CRC_ALIGN (*(volatile uint32_t*)(&_MBAR[0x9A90]))
|
||||
#define MCF_FEC1_RMON_R_UNDERSIZE (*(volatile uint32_t*)(&_MBAR[0x9A94]))
|
||||
#define MCF_FEC1_RMON_R_OVERSIZE (*(volatile uint32_t*)(&_MBAR[0x9A98]))
|
||||
#define MCF_FEC1_RMON_R_FRAG (*(volatile uint32_t*)(&_MBAR[0x9A9C]))
|
||||
#define MCF_FEC1_RMON_R_JAB (*(volatile uint32_t*)(&_MBAR[0x9AA0]))
|
||||
#define MCF_FEC1_RMON_R_RESVD_0 (*(volatile uint32_t*)(&_MBAR[0x9AA4]))
|
||||
#define MCF_FEC1_RMON_R_P64 (*(volatile uint32_t*)(&_MBAR[0x9AA8]))
|
||||
#define MCF_FEC1_RMON_R_P65TO127 (*(volatile uint32_t*)(&_MBAR[0x9AAC]))
|
||||
#define MCF_FEC1_RMON_R_P128TO255 (*(volatile uint32_t*)(&_MBAR[0x9AB0]))
|
||||
#define MCF_FEC1_RMON_R_P256TO511 (*(volatile uint32_t*)(&_MBAR[0x9AB4]))
|
||||
#define MCF_FEC1_RMON_R_P512TO1023 (*(volatile uint32_t*)(&_MBAR[0x9AB8]))
|
||||
#define MCF_FEC1_RMON_R_P1024TO2047 (*(volatile uint32_t*)(&_MBAR[0x9ABC]))
|
||||
#define MCF_FEC1_RMON_R_P_GTE2048 (*(volatile uint32_t*)(&_MBAR[0x9AC0]))
|
||||
#define MCF_FEC1_RMON_R_OCTETS (*(volatile uint32_t*)(&_MBAR[0x9AC4]))
|
||||
#define MCF_FEC1_IEEE_R_DROP (*(volatile uint32_t*)(&_MBAR[0x9AC8]))
|
||||
#define MCF_FEC1_IEEE_R_FRAME_OK (*(volatile uint32_t*)(&_MBAR[0x9ACC]))
|
||||
#define MCF_FEC1_IEEE_R_CRC (*(volatile uint32_t*)(&_MBAR[0x9AD0]))
|
||||
#define MCF_FEC1_IEEE_R_ALIGN (*(volatile uint32_t*)(&_MBAR[0x9AD4]))
|
||||
#define MCF_FEC1_IEEE_R_MACERR (*(volatile uint32_t*)(&_MBAR[0x9AD8]))
|
||||
#define MCF_FEC1_IEEE_R_FDXFC (*(volatile uint32_t*)(&_MBAR[0x9ADC]))
|
||||
#define MCF_FEC1_IEEE_R_OCTETS_OK (*(volatile uint32_t*)(&_MBAR[0x9AE0]))
|
||||
|
||||
#define MCF_FEC_EIR(x) (*(volatile uint32_t*)(&_MBAR[0x9004 + ((x)*0x800)]))
|
||||
#define MCF_FEC_EIMR(x) (*(volatile uint32_t*)(&_MBAR[0x9008 + ((x)*0x800)]))
|
||||
#define MCF_FEC_ECR(x) (*(volatile uint32_t*)(&_MBAR[0x9024 + ((x)*0x800)]))
|
||||
#define MCF_FEC_MMFR(x) (*(volatile uint32_t*)(&_MBAR[0x9040 + ((x)*0x800)]))
|
||||
#define MCF_FEC_MSCR(x) (*(volatile uint32_t*)(&_MBAR[0x9044 + ((x)*0x800)]))
|
||||
#define MCF_FEC_MIBC(x) (*(volatile uint32_t*)(&_MBAR[0x9064 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RCR(x) (*(volatile uint32_t*)(&_MBAR[0x9084 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RHR(x) (*(volatile uint32_t*)(&_MBAR[0x9088 + ((x)*0x800)]))
|
||||
#define MCF_FEC_TCR(x) (*(volatile uint32_t*)(&_MBAR[0x90C4 + ((x)*0x800)]))
|
||||
#define MCF_FEC_PALR(x) (*(volatile uint32_t*)(&_MBAR[0x90E4 + ((x)*0x800)]))
|
||||
#define MCF_FEC_PAHR(x) (*(volatile uint32_t*)(&_MBAR[0x90E8 + ((x)*0x800)]))
|
||||
#define MCF_FEC_OPD(x) (*(volatile uint32_t*)(&_MBAR[0x90EC + ((x)*0x800)]))
|
||||
#define MCF_FEC_IAUR(x) (*(volatile uint32_t*)(&_MBAR[0x9118 + ((x)*0x800)]))
|
||||
#define MCF_FEC_IALR(x) (*(volatile uint32_t*)(&_MBAR[0x911C + ((x)*0x800)]))
|
||||
#define MCF_FEC_GAUR(x) (*(volatile uint32_t*)(&_MBAR[0x9120 + ((x)*0x800)]))
|
||||
#define MCF_FEC_GALR(x) (*(volatile uint32_t*)(&_MBAR[0x9124 + ((x)*0x800)]))
|
||||
#define MCF_FEC_FECTFWR(x) (*(volatile uint32_t*)(&_MBAR[0x9144 + ((x)*0x800)]))
|
||||
#define MCF_FEC_FECRFDR(x) (*(volatile uint32_t*)(&_MBAR[0x9184 + ((x)*0x800)]))
|
||||
#define MCF_FEC_FECRFSR(x) (*(volatile uint32_t*)(&_MBAR[0x9188 + ((x)*0x800)]))
|
||||
#define MCF_FEC_FECRFCR(x) (*(volatile uint32_t*)(&_MBAR[0x918C + ((x)*0x800)]))
|
||||
#define MCF_FEC_FECRLRFP(x) (*(volatile uint32_t*)(&_MBAR[0x9190 + ((x)*0x800)]))
|
||||
#define MCF_FEC_FECRLWFP(x) (*(volatile uint32_t*)(&_MBAR[0x9194 + ((x)*0x800)]))
|
||||
#define MCF_FEC_FECRFAR(x) (*(volatile uint32_t*)(&_MBAR[0x9198 + ((x)*0x800)]))
|
||||
#define MCF_FEC_FECRFRP(x) (*(volatile uint32_t*)(&_MBAR[0x919C + ((x)*0x800)]))
|
||||
#define MCF_FEC_FECRFWP(x) (*(volatile uint32_t*)(&_MBAR[0x91A0 + ((x)*0x800)]))
|
||||
#define MCF_FEC_FECTFDR(x) (*(volatile uint32_t*)(&_MBAR[0x91A4 + ((x)*0x800)]))
|
||||
#define MCF_FEC_FECTFSR(x) (*(volatile uint32_t*)(&_MBAR[0x91A8 + ((x)*0x800)]))
|
||||
#define MCF_FEC_FECTFCR(x) (*(volatile uint32_t*)(&_MBAR[0x91AC + ((x)*0x800)]))
|
||||
#define MCF_FEC_FECTLRFP(x) (*(volatile uint32_t*)(&_MBAR[0x91B0 + ((x)*0x800)]))
|
||||
#define MCF_FEC_FECTLWFP(x) (*(volatile uint32_t*)(&_MBAR[0x91B4 + ((x)*0x800)]))
|
||||
#define MCF_FEC_FECTFAR(x) (*(volatile uint32_t*)(&_MBAR[0x91B8 + ((x)*0x800)]))
|
||||
#define MCF_FEC_FECTFRP(x) (*(volatile uint32_t*)(&_MBAR[0x91BC + ((x)*0x800)]))
|
||||
#define MCF_FEC_FECTFWP(x) (*(volatile uint32_t*)(&_MBAR[0x91C0 + ((x)*0x800)]))
|
||||
#define MCF_FEC_FECFRST(x) (*(volatile uint32_t*)(&_MBAR[0x91C4 + ((x)*0x800)]))
|
||||
#define MCF_FEC_FECCTCWR(x) (*(volatile uint32_t*)(&_MBAR[0x91C8 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_T_DROP(x) (*(volatile uint32_t*)(&_MBAR[0x9200 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_T_PACKETS(x) (*(volatile uint32_t*)(&_MBAR[0x9204 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_T_BC_PKT(x) (*(volatile uint32_t*)(&_MBAR[0x9208 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_T_MC_PKT(x) (*(volatile uint32_t*)(&_MBAR[0x920C + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_T_CRC_ALIGN(x) (*(volatile uint32_t*)(&_MBAR[0x9210 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_T_UNDERSIZE(x) (*(volatile uint32_t*)(&_MBAR[0x9214 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_T_OVERSIZE(x) (*(volatile uint32_t*)(&_MBAR[0x9218 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_T_FRAG(x) (*(volatile uint32_t*)(&_MBAR[0x921C + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_T_JAB(x) (*(volatile uint32_t*)(&_MBAR[0x9220 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_T_COL(x) (*(volatile uint32_t*)(&_MBAR[0x9224 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_T_P64(x) (*(volatile uint32_t*)(&_MBAR[0x9228 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_T_P65TO127(x) (*(volatile uint32_t*)(&_MBAR[0x922C + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_T_P128TO255(x) (*(volatile uint32_t*)(&_MBAR[0x9230 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_T_P256TO511(x) (*(volatile uint32_t*)(&_MBAR[0x9234 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_T_P512TO1023(x) (*(volatile uint32_t*)(&_MBAR[0x9238 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_T_P1024TO2047(x) (*(volatile uint32_t*)(&_MBAR[0x923C + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_T_P_GTE2048(x) (*(volatile uint32_t*)(&_MBAR[0x9240 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_T_OCTETS(x) (*(volatile uint32_t*)(&_MBAR[0x9244 + ((x)*0x800)]))
|
||||
#define MCF_FEC_IEEE_T_DROP(x) (*(volatile uint32_t*)(&_MBAR[0x9248 + ((x)*0x800)]))
|
||||
#define MCF_FEC_IEEE_T_FRAME_OK(x) (*(volatile uint32_t*)(&_MBAR[0x924C + ((x)*0x800)]))
|
||||
#define MCF_FEC_IEEE_T_1COL(x) (*(volatile uint32_t*)(&_MBAR[0x9250 + ((x)*0x800)]))
|
||||
#define MCF_FEC_IEEE_T_MCOL(x) (*(volatile uint32_t*)(&_MBAR[0x9254 + ((x)*0x800)]))
|
||||
#define MCF_FEC_IEEE_T_DEF(x) (*(volatile uint32_t*)(&_MBAR[0x9258 + ((x)*0x800)]))
|
||||
#define MCF_FEC_IEEE_T_LCOL(x) (*(volatile uint32_t*)(&_MBAR[0x925C + ((x)*0x800)]))
|
||||
#define MCF_FEC_IEEE_T_EXCOL(x) (*(volatile uint32_t*)(&_MBAR[0x9260 + ((x)*0x800)]))
|
||||
#define MCF_FEC_IEEE_T_MACERR(x) (*(volatile uint32_t*)(&_MBAR[0x9264 + ((x)*0x800)]))
|
||||
#define MCF_FEC_IEEE_T_CSERR(x) (*(volatile uint32_t*)(&_MBAR[0x9268 + ((x)*0x800)]))
|
||||
#define MCF_FEC_IEEE_T_SQE(x) (*(volatile uint32_t*)(&_MBAR[0x926C + ((x)*0x800)]))
|
||||
#define MCF_FEC_IEEE_T_FDXFC(x) (*(volatile uint32_t*)(&_MBAR[0x9270 + ((x)*0x800)]))
|
||||
#define MCF_FEC_IEEE_T_OCTETS_OK(x) (*(volatile uint32_t*)(&_MBAR[0x9274 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_R_DROP(x) (*(volatile uint32_t*)(&_MBAR[0x9280 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_R_PACKETS(x) (*(volatile uint32_t*)(&_MBAR[0x9284 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_R_BC_PKT(x) (*(volatile uint32_t*)(&_MBAR[0x9288 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_R_MC_PKT(x) (*(volatile uint32_t*)(&_MBAR[0x928C + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_R_CRC_ALIGN(x) (*(volatile uint32_t*)(&_MBAR[0x9290 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_R_UNDERSIZE(x) (*(volatile uint32_t*)(&_MBAR[0x9294 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_R_OVERSIZE(x) (*(volatile uint32_t*)(&_MBAR[0x9298 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_R_FRAG(x) (*(volatile uint32_t*)(&_MBAR[0x929C + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_R_JAB(x) (*(volatile uint32_t*)(&_MBAR[0x92A0 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_R_RESVD_0(x) (*(volatile uint32_t*)(&_MBAR[0x92A4 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_R_P64(x) (*(volatile uint32_t*)(&_MBAR[0x92A8 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_R_P65TO127(x) (*(volatile uint32_t*)(&_MBAR[0x92AC + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_R_P128TO255(x) (*(volatile uint32_t*)(&_MBAR[0x92B0 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_R_P256TO511(x) (*(volatile uint32_t*)(&_MBAR[0x92B4 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_R_P512TO1023(x) (*(volatile uint32_t*)(&_MBAR[0x92B8 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_R_P1024TO2047(x) (*(volatile uint32_t*)(&_MBAR[0x92BC + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_R_P_GTE2048(x) (*(volatile uint32_t*)(&_MBAR[0x92C0 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_R_OCTETS(x) (*(volatile uint32_t*)(&_MBAR[0x92C4 + ((x)*0x800)]))
|
||||
#define MCF_FEC_IEEE_R_DROP(x) (*(volatile uint32_t*)(&_MBAR[0x92C8 + ((x)*0x800)]))
|
||||
#define MCF_FEC_IEEE_R_FRAME_OK(x) (*(volatile uint32_t*)(&_MBAR[0x92CC + ((x)*0x800)]))
|
||||
#define MCF_FEC_IEEE_R_CRC(x) (*(volatile uint32_t*)(&_MBAR[0x92D0 + ((x)*0x800)]))
|
||||
#define MCF_FEC_IEEE_R_ALIGN(x) (*(volatile uint32_t*)(&_MBAR[0x92D4 + ((x)*0x800)]))
|
||||
#define MCF_FEC_IEEE_R_MACERR(x) (*(volatile uint32_t*)(&_MBAR[0x92D8 + ((x)*0x800)]))
|
||||
#define MCF_FEC_IEEE_R_FDXFC(x) (*(volatile uint32_t*)(&_MBAR[0x92DC + ((x)*0x800)]))
|
||||
#define MCF_FEC_IEEE_R_OCTETS_OK(x) (*(volatile uint32_t*)(&_MBAR[0x92E0 + ((x)*0x800)]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_EIR */
|
||||
#define MCF_FEC_EIR_RFERR (0x20000)
|
||||
#define MCF_FEC_EIR_XFERR (0x40000)
|
||||
#define MCF_FEC_EIR_XFUN (0x80000)
|
||||
#define MCF_FEC_EIR_RL (0x100000)
|
||||
#define MCF_FEC_EIR_LC (0x200000)
|
||||
#define MCF_FEC_EIR_MII (0x800000)
|
||||
#define MCF_FEC_EIR_TXF (0x8000000)
|
||||
#define MCF_FEC_EIR_GRA (0x10000000)
|
||||
#define MCF_FEC_EIR_BABT (0x20000000)
|
||||
#define MCF_FEC_EIR_BABR (0x40000000)
|
||||
#define MCF_FEC_EIR_HBERR (0x80000000)
|
||||
#define MCF_FEC_EIR_CLEAR_ALL (0xFFFFFFFF)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_EIMR */
|
||||
#define MCF_FEC_EIMR_RFERR (0x20000)
|
||||
#define MCF_FEC_EIMR_XFERR (0x40000)
|
||||
#define MCF_FEC_EIMR_XFUN (0x80000)
|
||||
#define MCF_FEC_EIMR_RL (0x100000)
|
||||
#define MCF_FEC_EIMR_LC (0x200000)
|
||||
#define MCF_FEC_EIMR_MII (0x800000)
|
||||
#define MCF_FEC_EIMR_TXF (0x8000000)
|
||||
#define MCF_FEC_EIMR_GRA (0x10000000)
|
||||
#define MCF_FEC_EIMR_BABT (0x20000000)
|
||||
#define MCF_FEC_EIMR_BABR (0x40000000)
|
||||
#define MCF_FEC_EIMR_HBERR (0x80000000)
|
||||
#define MCF_FEC_EIMR_MASK_ALL (0)
|
||||
#define MCF_FEC_EIMR_UNMASK_ALL (0xFFFFFFFF)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_ECR */
|
||||
#define MCF_FEC_ECR_RESET (0x1)
|
||||
#define MCF_FEC_ECR_ETHER_EN (0x2)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_MMFR */
|
||||
#define MCF_FEC_MMFR_DATA(x) (((x)&0xFFFF)<<0)
|
||||
#define MCF_FEC_MMFR_TA(x) (((x)&0x3)<<0x10)
|
||||
#define MCF_FEC_MMFR_TA_10 (0x20000)
|
||||
#define MCF_FEC_MMFR_RA(x) (((x)&0x1F)<<0x12)
|
||||
#define MCF_FEC_MMFR_PA(x) (((x)&0x1F)<<0x17)
|
||||
#define MCF_FEC_MMFR_OP(x) (((x)&0x3)<<0x1C)
|
||||
#define MCF_FEC_MMFR_OP_READ (0x20000000)
|
||||
#define MCF_FEC_MMFR_OP_WRITE (0x10000000)
|
||||
#define MCF_FEC_MMFR_ST(x) (((x)&0x3)<<0x1E)
|
||||
#define MCF_FEC_MMFR_ST_01 (0x40000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_MSCR */
|
||||
#define MCF_FEC_MSCR_MII_SPEED(x) (((x)&0x3F)<<0x1)
|
||||
#define MCF_FEC_MSCR_DIS_PREAMBLE (0x80)
|
||||
#define MCF_FEC_MSCR_MII_SPEED_133 (0x1B<<0x1)
|
||||
#define MCF_FEC_MSCR_MII_SPEED_120 (0x18<<0x1)
|
||||
#define MCF_FEC_MSCR_MII_SPEED_66 (0xE<<0x1)
|
||||
#define MCF_FEC_MSCR_MII_SPEED_60 (0xC<<0x1)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_MIBC */
|
||||
#define MCF_FEC_MIBC_MIB_IDLE (0x40000000)
|
||||
#define MCF_FEC_MIBC_MIB_DISABLE (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RCR */
|
||||
#define MCF_FEC_RCR_LOOP (0x1)
|
||||
#define MCF_FEC_RCR_DRT (0x2)
|
||||
#define MCF_FEC_RCR_MII_MODE (0x4)
|
||||
#define MCF_FEC_RCR_PROM (0x8)
|
||||
#define MCF_FEC_RCR_BC_REJ (0x10)
|
||||
#define MCF_FEC_RCR_FCE (0x20)
|
||||
#define MCF_FEC_RCR_MAX_FL(x) (((x)&0x7FF)<<0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RHR */
|
||||
#define MCF_FEC_RHR_HASH(x) (((x)&0x3F)<<0x18)
|
||||
#define MCF_FEC_RHR_MULTCAST (0x40000000)
|
||||
#define MCF_FEC_RHR_FCE (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_TCR */
|
||||
#define MCF_FEC_TCR_GTS (0x1)
|
||||
#define MCF_FEC_TCR_HBC (0x2)
|
||||
#define MCF_FEC_TCR_FDEN (0x4)
|
||||
#define MCF_FEC_TCR_TFC_PAUSE (0x8)
|
||||
#define MCF_FEC_TCR_RFC_PAUSE (0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_PALR */
|
||||
#define MCF_FEC_PALR_PADDR1(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_PAHR */
|
||||
#define MCF_FEC_PAHR_TYPE(x) (((x)&0xFFFF)<<0)
|
||||
#define MCF_FEC_PAHR_PADDR2(x) (((x)&0xFFFF)<<0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_OPD */
|
||||
#define MCF_FEC_OPD_PAUSE_DUR(x) (((x)&0xFFFF)<<0)
|
||||
#define MCF_FEC_OPD_OPCODE(x) (((x)&0xFFFF)<<0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IAUR */
|
||||
#define MCF_FEC_IAUR_IADDR1(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IALR */
|
||||
#define MCF_FEC_IALR_IADDR2(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_GAUR */
|
||||
#define MCF_FEC_GAUR_GADDR1(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_GALR */
|
||||
#define MCF_FEC_GALR_GADDR2(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FECTFWR */
|
||||
#define MCF_FEC_FECTFWR_X_WMRK(x) (((x)&0xF)<<0)
|
||||
#define MCF_FEC_FECTFWR_X_WMRK_64 (0)
|
||||
#define MCF_FEC_FECTFWR_X_WMRK_128 (0x1)
|
||||
#define MCF_FEC_FECTFWR_X_WMRK_192 (0x2)
|
||||
#define MCF_FEC_FECTFWR_X_WMRK_256 (0x3)
|
||||
#define MCF_FEC_FECTFWR_X_WMRK_320 (0x4)
|
||||
#define MCF_FEC_FECTFWR_X_WMRK_384 (0x5)
|
||||
#define MCF_FEC_FECTFWR_X_WMRK_448 (0x6)
|
||||
#define MCF_FEC_FECTFWR_X_WMRK_512 (0x7)
|
||||
#define MCF_FEC_FECTFWR_X_WMRK_576 (0x8)
|
||||
#define MCF_FEC_FECTFWR_X_WMRK_640 (0x9)
|
||||
#define MCF_FEC_FECTFWR_X_WMRK_704 (0xA)
|
||||
#define MCF_FEC_FECTFWR_X_WMRK_768 (0xB)
|
||||
#define MCF_FEC_FECTFWR_X_WMRK_832 (0xC)
|
||||
#define MCF_FEC_FECTFWR_X_WMRK_896 (0xD)
|
||||
#define MCF_FEC_FECTFWR_X_WMRK_960 (0xE)
|
||||
#define MCF_FEC_FECTFWR_X_WMRK_1024 (0xF)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FECRFDR */
|
||||
#define MCF_FEC_FECRFDR_FIFO_DATA(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FECRFSR */
|
||||
#define MCF_FEC_FECRFSR_EMT (0x10000)
|
||||
#define MCF_FEC_FECRFSR_ALARM (0x20000)
|
||||
#define MCF_FEC_FECRFSR_FU (0x40000)
|
||||
#define MCF_FEC_FECRFSR_FRMRDY (0x80000)
|
||||
#define MCF_FEC_FECRFSR_OF (0x100000)
|
||||
#define MCF_FEC_FECRFSR_UF (0x200000)
|
||||
#define MCF_FEC_FECRFSR_RXW (0x400000)
|
||||
#define MCF_FEC_FECRFSR_FAE (0x800000)
|
||||
#define MCF_FEC_FECRFSR_FRM(x) (((x)&0xF)<<0x18)
|
||||
#define MCF_FEC_FECRFSR_IP (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FECRFCR */
|
||||
#define MCF_FEC_FECRFCR_COUNTER(x) (((x)&0xFFFF)<<0)
|
||||
#define MCF_FEC_FECRFCR_OF_MSK (0x80000)
|
||||
#define MCF_FEC_FECRFCR_UF_MSK (0x100000)
|
||||
#define MCF_FEC_FECRFCR_RXW_MSK (0x200000)
|
||||
#define MCF_FEC_FECRFCR_FAE_MSK (0x400000)
|
||||
#define MCF_FEC_FECRFCR_IP_MSK (0x800000)
|
||||
#define MCF_FEC_FECRFCR_GR(x) (((x)&0x7)<<0x18)
|
||||
#define MCF_FEC_FECRFCR_FRMEN (0x8000000)
|
||||
#define MCF_FEC_FECRFCR_TIMER (0x10000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FECRLRFP */
|
||||
#define MCF_FEC_FECRLRFP_LRFP(x) (((x)&0x3FF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FECRLWFP */
|
||||
#define MCF_FEC_FECRLWFP_LWFP(x) (((x)&0x3FF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FECRFAR */
|
||||
#define MCF_FEC_FECRFAR_ALARM(x) (((x)&0x3FF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FECRFRP */
|
||||
#define MCF_FEC_FECRFRP_READ(x) (((x)&0x3FF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FECRFWP */
|
||||
#define MCF_FEC_FECRFWP_WRITE(x) (((x)&0x3FF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FECTFDR */
|
||||
#define MCF_FEC_FECTFDR_FIFO_DATA(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FECTFSR */
|
||||
#define MCF_FEC_FECTFSR_EMT (0x10000)
|
||||
#define MCF_FEC_FECTFSR_ALARM (0x20000)
|
||||
#define MCF_FEC_FECTFSR_FU (0x40000)
|
||||
#define MCF_FEC_FECTFSR_FRMRDY (0x80000)
|
||||
#define MCF_FEC_FECTFSR_OF (0x100000)
|
||||
#define MCF_FEC_FECTFSR_UF (0x200000)
|
||||
#define MCF_FEC_FECTFSR_FAE (0x800000)
|
||||
#define MCF_FEC_FECTFSR_FRM(x) (((x)&0xF)<<0x18)
|
||||
#define MCF_FEC_FECTFSR_TXW (0x40000000)
|
||||
#define MCF_FEC_FECTFSR_IP (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FECTFCR */
|
||||
#define MCF_FEC_FECTFCR_RESERVED (0x200000)
|
||||
#define MCF_FEC_FECTFCR_COUNTER(x) (((x)&0xFFFF)<<0|0x200000)
|
||||
#define MCF_FEC_FECTFCR_TXW_MASK (0x240000)
|
||||
#define MCF_FEC_FECTFCR_OF_MSK (0x280000)
|
||||
#define MCF_FEC_FECTFCR_UF_MSK (0x300000)
|
||||
#define MCF_FEC_FECTFCR_FAE_MSK (0x600000)
|
||||
#define MCF_FEC_FECTFCR_IP_MSK (0xA00000)
|
||||
#define MCF_FEC_FECTFCR_GR(x) (((x)&0x7)<<0x18|0x200000)
|
||||
#define MCF_FEC_FECTFCR_FRMEN (0x8200000)
|
||||
#define MCF_FEC_FECTFCR_TIMER (0x10200000)
|
||||
#define MCF_FEC_FECTFCR_WFR (0x20200000)
|
||||
#define MCF_FEC_FECTFCR_WCTL (0x40200000)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FECTLRFP */
|
||||
#define MCF_FEC_FECTLRFP_LRFP(x) (((x)&0x3FF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FECTLWFP */
|
||||
#define MCF_FEC_FECTLWFP_LWFP(x) (((x)&0x3FF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FECTFAR */
|
||||
#define MCF_FEC_FECTFAR_ALARM(x) (((x)&0x3FF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FECTFRP */
|
||||
#define MCF_FEC_FECTFRP_READ(x) (((x)&0x3FF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FECTFWP */
|
||||
#define MCF_FEC_FECTFWP_WRITE(x) (((x)&0x3FF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FECFRST */
|
||||
#define MCF_FEC_FECFRST_RST_CTL (0x1000000)
|
||||
#define MCF_FEC_FECFRST_SW_RST (0x2000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FECCTCWR */
|
||||
#define MCF_FEC_FECCTCWR_TFCW (0x1000000)
|
||||
#define MCF_FEC_FECCTCWR_CRC (0x2000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_DROP */
|
||||
#define MCF_FEC_RMON_T_DROP_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_PACKETS */
|
||||
#define MCF_FEC_RMON_T_PACKETS_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_BC_PKT */
|
||||
#define MCF_FEC_RMON_T_BC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_MC_PKT */
|
||||
#define MCF_FEC_RMON_T_MC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_CRC_ALIGN */
|
||||
#define MCF_FEC_RMON_T_CRC_ALIGN_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_UNDERSIZE */
|
||||
#define MCF_FEC_RMON_T_UNDERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_OVERSIZE */
|
||||
#define MCF_FEC_RMON_T_OVERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_FRAG */
|
||||
#define MCF_FEC_RMON_T_FRAG_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_JAB */
|
||||
#define MCF_FEC_RMON_T_JAB_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_COL */
|
||||
#define MCF_FEC_RMON_T_COL_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_P64 */
|
||||
#define MCF_FEC_RMON_T_P64_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_P65TO127 */
|
||||
#define MCF_FEC_RMON_T_P65TO127_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_P128TO255 */
|
||||
#define MCF_FEC_RMON_T_P128TO255_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_P256TO511 */
|
||||
#define MCF_FEC_RMON_T_P256TO511_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_P512TO1023 */
|
||||
#define MCF_FEC_RMON_T_P512TO1023_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_P1024TO2047 */
|
||||
#define MCF_FEC_RMON_T_P1024TO2047_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_P_GTE2048 */
|
||||
#define MCF_FEC_RMON_T_P_GTE2048_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_OCTETS */
|
||||
#define MCF_FEC_RMON_T_OCTETS_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_T_DROP */
|
||||
#define MCF_FEC_IEEE_T_DROP_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_T_FRAME_OK */
|
||||
#define MCF_FEC_IEEE_T_FRAME_OK_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_T_1COL */
|
||||
#define MCF_FEC_IEEE_T_1COL_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_T_MCOL */
|
||||
#define MCF_FEC_IEEE_T_MCOL_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_T_DEF */
|
||||
#define MCF_FEC_IEEE_T_DEF_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_T_LCOL */
|
||||
#define MCF_FEC_IEEE_T_LCOL_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_T_EXCOL */
|
||||
#define MCF_FEC_IEEE_T_EXCOL_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_T_MACERR */
|
||||
#define MCF_FEC_IEEE_T_MACERR_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_T_CSERR */
|
||||
#define MCF_FEC_IEEE_T_CSERR_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_T_SQE */
|
||||
#define MCF_FEC_IEEE_T_SQE_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_T_FDXFC */
|
||||
#define MCF_FEC_IEEE_T_FDXFC_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_T_OCTETS_OK */
|
||||
#define MCF_FEC_IEEE_T_OCTETS_OK_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_DROP */
|
||||
#define MCF_FEC_RMON_R_DROP_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_PACKETS */
|
||||
#define MCF_FEC_RMON_R_PACKETS_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_BC_PKT */
|
||||
#define MCF_FEC_RMON_R_BC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_MC_PKT */
|
||||
#define MCF_FEC_RMON_R_MC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_CRC_ALIGN */
|
||||
#define MCF_FEC_RMON_R_CRC_ALIGN_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_UNDERSIZE */
|
||||
#define MCF_FEC_RMON_R_UNDERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_OVERSIZE */
|
||||
#define MCF_FEC_RMON_R_OVERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_FRAG */
|
||||
#define MCF_FEC_RMON_R_FRAG_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_JAB */
|
||||
#define MCF_FEC_RMON_R_JAB_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_RESVD_0 */
|
||||
#define MCF_FEC_RMON_R_RESVD_0_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_P64 */
|
||||
#define MCF_FEC_RMON_R_P64_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_P65TO127 */
|
||||
#define MCF_FEC_RMON_R_P65TO127_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_P128TO255 */
|
||||
#define MCF_FEC_RMON_R_P128TO255_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_P256TO511 */
|
||||
#define MCF_FEC_RMON_R_P256TO511_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_P512TO1023 */
|
||||
#define MCF_FEC_RMON_R_P512TO1023_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_P1024TO2047 */
|
||||
#define MCF_FEC_RMON_R_P1024TO2047_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_P_GTE2048 */
|
||||
#define MCF_FEC_RMON_R_P_GTE2048_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_OCTETS */
|
||||
#define MCF_FEC_RMON_R_OCTETS_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_R_DROP */
|
||||
#define MCF_FEC_IEEE_R_DROP_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_R_FRAME_OK */
|
||||
#define MCF_FEC_IEEE_R_FRAME_OK_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_R_CRC */
|
||||
#define MCF_FEC_IEEE_R_CRC_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_R_ALIGN */
|
||||
#define MCF_FEC_IEEE_R_ALIGN_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_R_MACERR */
|
||||
#define MCF_FEC_IEEE_R_MACERR_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_R_FDXFC */
|
||||
#define MCF_FEC_IEEE_R_FDXFC_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_R_OCTETS_OK */
|
||||
#define MCF_FEC_IEEE_R_OCTETS_OK_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
|
||||
#endif /* __MCF5475_FEC_H__ */
|
||||
69
include/MCF5475_I2C.h
Normal file
69
include/MCF5475_I2C.h
Normal file
@@ -0,0 +1,69 @@
|
||||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.81
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF5475_I2C_H__
|
||||
#define __MCF5475_I2C_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* I2C Module (I2C)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_I2C_I2ADR (*(volatile uint8_t *)(&_MBAR[0x8F00]))
|
||||
#define MCF_I2C_I2FDR (*(volatile uint8_t *)(&_MBAR[0x8F04]))
|
||||
#define MCF_I2C_I2CR (*(volatile uint8_t *)(&_MBAR[0x8F08]))
|
||||
#define MCF_I2C_I2SR (*(volatile uint8_t *)(&_MBAR[0x8F0C]))
|
||||
#define MCF_I2C_I2DR (*(volatile uint8_t *)(&_MBAR[0x8F10]))
|
||||
#define MCF_I2C_I2ICR (*(volatile uint8_t *)(&_MBAR[0x8F20]))
|
||||
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_I2C_I2ADR */
|
||||
#define MCF_I2C_I2ADR_ADR(x) (((x)&0x7F)<<0x1)
|
||||
|
||||
/* Bit definitions and macros for MCF_I2C_I2FDR */
|
||||
#define MCF_I2C_I2FDR_IC(x) (((x)&0x3F)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_I2C_I2CR */
|
||||
#define MCF_I2C_I2CR_RSTA (0x4)
|
||||
#define MCF_I2C_I2CR_TXAK (0x8)
|
||||
#define MCF_I2C_I2CR_MTX (0x10)
|
||||
#define MCF_I2C_I2CR_MSTA (0x20)
|
||||
#define MCF_I2C_I2CR_IIEN (0x40)
|
||||
#define MCF_I2C_I2CR_IEN (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_I2C_I2SR */
|
||||
#define MCF_I2C_I2SR_RXAK (0x1)
|
||||
#define MCF_I2C_I2SR_IIF (0x2)
|
||||
#define MCF_I2C_I2SR_SRW (0x4)
|
||||
#define MCF_I2C_I2SR_IAL (0x10)
|
||||
#define MCF_I2C_I2SR_IBB (0x20)
|
||||
#define MCF_I2C_I2SR_IAAS (0x40)
|
||||
#define MCF_I2C_I2SR_ICF (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_I2C_I2DR */
|
||||
#define MCF_I2C_I2DR_DATA(x) (((x)&0xFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_I2C_I2ICR */
|
||||
#define MCF_I2C_I2ICR_IE (0x1)
|
||||
#define MCF_I2C_I2ICR_RE (0x2)
|
||||
#define MCF_I2C_I2ICR_TE (0x4)
|
||||
#define MCF_I2C_I2ICR_BNBE (0x8)
|
||||
|
||||
|
||||
#endif /* __MCF5475_I2C_H__ */
|
||||
79
include/MCF5475_MMU.h
Normal file
79
include/MCF5475_MMU.h
Normal file
@@ -0,0 +1,79 @@
|
||||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.81
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF5475_MMU_H__
|
||||
#define __MCF5475_MMU_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Memory Management Unit (MMU)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
|
||||
/* note the uint32_t_a - this is to avoid gcc warnings about pointer aliasing */
|
||||
#define MCF_MMU_MMUCR (*(volatile uint32_t_a*)(&_MMUBAR[0]))
|
||||
#define MCF_MMU_MMUOR (*(volatile uint32_t_a*)(&_MMUBAR[0x4]))
|
||||
#define MCF_MMU_MMUSR (*(volatile uint32_t_a*)(&_MMUBAR[0x8]))
|
||||
#define MCF_MMU_MMUAR (*(volatile uint32_t_a*)(&_MMUBAR[0x10]))
|
||||
#define MCF_MMU_MMUTR (*(volatile uint32_t_a*)(&_MMUBAR[0x14]))
|
||||
#define MCF_MMU_MMUDR (*(volatile uint32_t_a*)(&_MMUBAR[0x18]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_MMU_MMUCR */
|
||||
#define MCF_MMU_MMUCR_EN (0x1)
|
||||
#define MCF_MMU_MMUCR_ASM (0x2)
|
||||
|
||||
/* Bit definitions and macros for MCF_MMU_MMUOR */
|
||||
#define MCF_MMU_MMUOR_UAA (0x1)
|
||||
#define MCF_MMU_MMUOR_ACC (0x2)
|
||||
#define MCF_MMU_MMUOR_RW (0x4)
|
||||
#define MCF_MMU_MMUOR_ADR (0x8)
|
||||
#define MCF_MMU_MMUOR_ITLB (0x10)
|
||||
#define MCF_MMU_MMUOR_CAS (0x20)
|
||||
#define MCF_MMU_MMUOR_CNL (0x40)
|
||||
#define MCF_MMU_MMUOR_CA (0x80)
|
||||
#define MCF_MMU_MMUOR_STLB (0x100)
|
||||
#define MCF_MMU_MMUOR_AA(x) (((x)&0xFFFF)<<0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_MMU_MMUSR */
|
||||
#define MCF_MMU_MMUSR_HIT (0x2)
|
||||
#define MCF_MMU_MMUSR_WF (0x8)
|
||||
#define MCF_MMU_MMUSR_RF (0x10)
|
||||
#define MCF_MMU_MMUSR_SPF (0x20)
|
||||
|
||||
/* Bit definitions and macros for MCF_MMU_MMUAR */
|
||||
#define MCF_MMU_MMUAR_FA(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_MMU_MMUTR */
|
||||
#define MCF_MMU_MMUTR_V (0x1)
|
||||
#define MCF_MMU_MMUTR_SG (0x2)
|
||||
#define MCF_MMU_MMUTR_ID(x) (((x) & 0xFF) << 0x2)
|
||||
#define MCF_MMU_MMUTR_VA(x) (((x)&0x3FFFFF)<<0xA)
|
||||
|
||||
/* Bit definitions and macros for MCF_MMU_MMUDR */
|
||||
#define MCF_MMU_MMUDR_LK (0x2)
|
||||
#define MCF_MMU_MMUDR_X (0x4)
|
||||
#define MCF_MMU_MMUDR_W (0x8)
|
||||
#define MCF_MMU_MMUDR_R (0x10)
|
||||
#define MCF_MMU_MMUDR_SP (0x20)
|
||||
#define MCF_MMU_MMUDR_CM(x) (((x) & 0x3) << 0x6)
|
||||
#define MCF_MMU_MMUDR_SZ(x) (((x) & 0x3) << 0x8)
|
||||
#define MCF_MMU_MMUDR_PA(x) (((x) & 0x3FFFFF) << 0xA)
|
||||
|
||||
|
||||
#endif /* __MCF5475_MMU_H__ */
|
||||
233
include/MCF5475_PAD.h
Normal file
233
include/MCF5475_PAD.h
Normal file
@@ -0,0 +1,233 @@
|
||||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.81
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF5475_PAD_H__
|
||||
#define __MCF5475_PAD_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Common GPIO
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_PAD_PAR_FBCTL (*(volatile uint16_t*)(&_MBAR[0xA40]))
|
||||
#define MCF_PAD_PAR_FBCS (*(volatile uint8_t *)(&_MBAR[0xA42]))
|
||||
#define MCF_PAD_PAR_DMA (*(volatile uint8_t *)(&_MBAR[0xA43]))
|
||||
#define MCF_PAD_PAR_FECI2CIRQ (*(volatile uint16_t*)(&_MBAR[0xA44]))
|
||||
#define MCF_PAD_PAR_PCIBG (*(volatile uint16_t*)(&_MBAR[0xA48]))
|
||||
#define MCF_PAD_PAR_PCIBR (*(volatile uint16_t*)(&_MBAR[0xA4A]))
|
||||
#define MCF_PAD_PAR_PSC3 (*(volatile uint8_t *)(&_MBAR[0xA4C]))
|
||||
#define MCF_PAD_PAR_PSC2 (*(volatile uint8_t *)(&_MBAR[0xA4D]))
|
||||
#define MCF_PAD_PAR_PSC1 (*(volatile uint8_t *)(&_MBAR[0xA4E]))
|
||||
#define MCF_PAD_PAR_PSC0 (*(volatile uint8_t *)(&_MBAR[0xA4F]))
|
||||
#define MCF_PAD_PAR_DSPI (*(volatile uint16_t*)(&_MBAR[0xA50]))
|
||||
#define MCF_PAD_PAR_TIMER (*(volatile uint8_t *)(&_MBAR[0xA52]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_PAD_PAR_FBCTL */
|
||||
#define MCF_PAD_PAR_FBCTL_PAR_ALE(x) (((x)&0x3)<<0)
|
||||
#define MCF_PAD_PAR_FBCTL_PAR_ALE_GPIO (0)
|
||||
#define MCF_PAD_PAR_FBCTL_PAR_ALE_TBST (0x2)
|
||||
#define MCF_PAD_PAR_FBCTL_PAR_ALE_ALE (0x3)
|
||||
#define MCF_PAD_PAR_FBCTL_PAR_TA (0x4)
|
||||
#define MCF_PAD_PAR_FBCTL_PAR_RWB(x) (((x)&0x3)<<0x4)
|
||||
#define MCF_PAD_PAR_FBCTL_PAR_RWB_GPIO (0)
|
||||
#define MCF_PAD_PAR_FBCTL_PAR_RWB_TBST (0x20)
|
||||
#define MCF_PAD_PAR_FBCTL_PAR_RWB_RW (0x30)
|
||||
#define MCF_PAD_PAR_FBCTL_PAR_OE (0x40)
|
||||
#define MCF_PAD_PAR_FBCTL_PAR_BWE0 (0x100)
|
||||
#define MCF_PAD_PAR_FBCTL_PAR_BWE1 (0x400)
|
||||
#define MCF_PAD_PAR_FBCTL_PAR_BWE2 (0x1000)
|
||||
#define MCF_PAD_PAR_FBCTL_PAR_BWE3 (0x4000)
|
||||
|
||||
/* Bit definitions and macros for MCF_PAD_PAR_FBCS */
|
||||
#define MCF_PAD_PAR_FBCS_PAR_CS1 (0x2)
|
||||
#define MCF_PAD_PAR_FBCS_PAR_CS2 (0x4)
|
||||
#define MCF_PAD_PAR_FBCS_PAR_CS3 (0x8)
|
||||
#define MCF_PAD_PAR_FBCS_PAR_CS4 (0x10)
|
||||
#define MCF_PAD_PAR_FBCS_PAR_CS5 (0x20)
|
||||
|
||||
/* Bit definitions and macros for MCF_PAD_PAR_DMA */
|
||||
#define MCF_PAD_PAR_DMA_PAR_DREQ0(x) (((x)&0x3)<<0)
|
||||
#define MCF_PAD_PAR_DMA_PAR_DREQ0_GPIO (0)
|
||||
#define MCF_PAD_PAR_DMA_PAR_DREQ0_TIN0 (0x2)
|
||||
#define MCF_PAD_PAR_DMA_PAR_DREQ0_DREQ0 (0x3)
|
||||
#define MCF_PAD_PAR_DMA_PAR_DREQ1(x) (((x)&0x3)<<0x2)
|
||||
#define MCF_PAD_PAR_DMA_PAR_DREQ1_GPIO (0)
|
||||
#define MCF_PAD_PAR_DMA_PAR_DREQ1_IRQ1 (0x4)
|
||||
#define MCF_PAD_PAR_DMA_PAR_DREQ1_TIN1 (0x8)
|
||||
#define MCF_PAD_PAR_DMA_PAR_DREQ1_DREQ1 (0xC)
|
||||
#define MCF_PAD_PAR_DMA_PAR_DACK0(x) (((x)&0x3)<<0x4)
|
||||
#define MCF_PAD_PAR_DMA_PAR_DACK0_GPIO (0)
|
||||
#define MCF_PAD_PAR_DMA_PAR_DACK0_TOUT0 (0x20)
|
||||
#define MCF_PAD_PAR_DMA_PAR_DACK0_DACK0 (0x30)
|
||||
#define MCF_PAD_PAR_DMA_PAR_DACK1(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_PAD_PAR_DMA_PAR_DACK1_GPIO (0)
|
||||
#define MCF_PAD_PAR_DMA_PAR_DACK1_TOUT1 (0x80)
|
||||
#define MCF_PAD_PAR_DMA_PAR_DACK1_DACK1 (0xC0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PAD_PAR_FECI2CIRQ */
|
||||
#define MCF_PAD_PAR_FECI2CIRQ_PAR_IRQ5 (0x1)
|
||||
#define MCF_PAD_PAR_FECI2CIRQ_PAR_IRQ6 (0x2)
|
||||
#define MCF_PAD_PAR_FECI2CIRQ_PAR_SCL (0x4)
|
||||
#define MCF_PAD_PAR_FECI2CIRQ_PAR_SDA (0x8)
|
||||
#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDC(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDC_SCL (0x80)
|
||||
#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDC_E1MDC (0xC0)
|
||||
#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDIO(x) (((x)&0x3)<<0x8)
|
||||
#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDIO_SDA (0x200)
|
||||
#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDIO_E1MDIO (0x300)
|
||||
#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MII (0x400)
|
||||
#define MCF_PAD_PAR_FECI2CIRQ_PAR_E17 (0x800)
|
||||
#define MCF_PAD_PAR_FECI2CIRQ_PAR_E0MDC (0x1000)
|
||||
#define MCF_PAD_PAR_FECI2CIRQ_PAR_E0MDIO (0x2000)
|
||||
#define MCF_PAD_PAR_FECI2CIRQ_PAR_E0MII (0x4000)
|
||||
#define MCF_PAD_PAR_FECI2CIRQ_PAR_E07 (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_PAD_PAR_PCIBG */
|
||||
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0(x) (((x)&0x3)<<0)
|
||||
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0_GPIO (0)
|
||||
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0_TOUT0 (0x2)
|
||||
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0_PCIBG0 (0x3)
|
||||
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1(x) (((x)&0x3)<<0x2)
|
||||
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1_GPIO (0)
|
||||
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1_TOUT1 (0x8)
|
||||
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1_PCIBG1 (0xC)
|
||||
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2(x) (((x)&0x3)<<0x4)
|
||||
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2_GPIO (0)
|
||||
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2_TOUT2 (0x20)
|
||||
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2_PCIBG2 (0x30)
|
||||
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3_GPIO (0)
|
||||
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3_TOUT3 (0x80)
|
||||
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3_PCIBG3 (0xC0)
|
||||
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4(x) (((x)&0x3)<<0x8)
|
||||
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4_GPIO (0)
|
||||
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4_TBST (0x200)
|
||||
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4_PCIBG4 (0x300)
|
||||
|
||||
/* Bit definitions and macros for MCF_PAD_PAR_PCIBR */
|
||||
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0(x) (((x)&0x3)<<0)
|
||||
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0_GPIO (0)
|
||||
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0_TIN0 (0x2)
|
||||
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0_PCIBR0 (0x3)
|
||||
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1(x) (((x)&0x3)<<0x2)
|
||||
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1_GPIO (0)
|
||||
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1_TIN1 (0x8)
|
||||
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1_PCIBR1 (0xC)
|
||||
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2(x) (((x)&0x3)<<0x4)
|
||||
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2_GPIO (0)
|
||||
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2_TIN2 (0x20)
|
||||
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2_PCIBR2 (0x30)
|
||||
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3_GPIO (0)
|
||||
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3_TIN3 (0x80)
|
||||
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3_PCIBR3 (0xC0)
|
||||
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4(x) (((x)&0x3)<<0x8)
|
||||
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4_GPIO (0)
|
||||
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4_IRQ4 (0x200)
|
||||
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4_PCIBR4 (0x300)
|
||||
|
||||
/* Bit definitions and macros for MCF_PAD_PAR_PSC3 */
|
||||
#define MCF_PAD_PAR_PSC3_PAR_TXD3 (0x4)
|
||||
#define MCF_PAD_PAR_PSC3_PAR_RXD3 (0x8)
|
||||
#define MCF_PAD_PAR_PSC3_PAR_RTS3(x) (((x)&0x3)<<0x4)
|
||||
#define MCF_PAD_PAR_PSC3_PAR_RTS3_GPIO (0)
|
||||
#define MCF_PAD_PAR_PSC3_PAR_RTS3_FSYNC (0x20)
|
||||
#define MCF_PAD_PAR_PSC3_PAR_RTS3_RTS (0x30)
|
||||
#define MCF_PAD_PAR_PSC3_PAR_CTS3(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_PAD_PAR_PSC3_PAR_CTS3_GPIO (0)
|
||||
#define MCF_PAD_PAR_PSC3_PAR_CTS3_BCLK (0x80)
|
||||
#define MCF_PAD_PAR_PSC3_PAR_CTS3_CTS (0xC0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PAD_PAR_PSC2 */
|
||||
#define MCF_PAD_PAR_PSC2_PAR_TXD2 (0x4)
|
||||
#define MCF_PAD_PAR_PSC2_PAR_RXD2 (0x8)
|
||||
#define MCF_PAD_PAR_PSC2_PAR_RTS2(x) (((x)&0x3)<<0x4)
|
||||
#define MCF_PAD_PAR_PSC2_PAR_RTS2_GPIO (0)
|
||||
#define MCF_PAD_PAR_PSC2_PAR_RTS2_FSYNC (0x20)
|
||||
#define MCF_PAD_PAR_PSC2_PAR_RTS2_RTS (0x30)
|
||||
#define MCF_PAD_PAR_PSC2_PAR_CTS2(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_PAD_PAR_PSC2_PAR_CTS2_GPIO (0)
|
||||
#define MCF_PAD_PAR_PSC2_PAR_CTS2_BCLK (0x80)
|
||||
#define MCF_PAD_PAR_PSC2_PAR_CTS2_CTS (0xC0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PAD_PAR_PSC1 */
|
||||
#define MCF_PAD_PAR_PSC1_PAR_TXD1 (0x4)
|
||||
#define MCF_PAD_PAR_PSC1_PAR_RXD1 (0x8)
|
||||
#define MCF_PAD_PAR_PSC1_PAR_RTS1(x) (((x)&0x3)<<0x4)
|
||||
#define MCF_PAD_PAR_PSC1_PAR_RTS1_GPIO (0)
|
||||
#define MCF_PAD_PAR_PSC1_PAR_RTS1_FSYNC (0x20)
|
||||
#define MCF_PAD_PAR_PSC1_PAR_RTS1_RTS (0x30)
|
||||
#define MCF_PAD_PAR_PSC1_PAR_CTS1(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_PAD_PAR_PSC1_PAR_CTS1_GPIO (0)
|
||||
#define MCF_PAD_PAR_PSC1_PAR_CTS1_BCLK (0x80)
|
||||
#define MCF_PAD_PAR_PSC1_PAR_CTS1_CTS (0xC0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PAD_PAR_PSC0 */
|
||||
#define MCF_PAD_PAR_PSC0_PAR_TXD0 (0x4)
|
||||
#define MCF_PAD_PAR_PSC0_PAR_RXD0 (0x8)
|
||||
#define MCF_PAD_PAR_PSC0_PAR_RTS0(x) (((x)&0x3)<<0x4)
|
||||
#define MCF_PAD_PAR_PSC0_PAR_RTS0_GPIO (0)
|
||||
#define MCF_PAD_PAR_PSC0_PAR_RTS0_FSYNC (0x20)
|
||||
#define MCF_PAD_PAR_PSC0_PAR_RTS0_RTS (0x30)
|
||||
#define MCF_PAD_PAR_PSC0_PAR_CTS0(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_PAD_PAR_PSC0_PAR_CTS0_GPIO (0)
|
||||
#define MCF_PAD_PAR_PSC0_PAR_CTS0_BCLK (0x80)
|
||||
#define MCF_PAD_PAR_PSC0_PAR_CTS0_CTS (0xC0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PAD_PAR_DSPI */
|
||||
#define MCF_PAD_PAR_DSPI_PAR_SOUT(x) (((x)&0x3)<<0)
|
||||
#define MCF_PAD_PAR_DSPI_PAR_SOUT_GPIO (0)
|
||||
#define MCF_PAD_PAR_DSPI_PAR_SOUT_TXD (0x2)
|
||||
#define MCF_PAD_PAR_DSPI_PAR_SOUT_SOUT (0x3)
|
||||
#define MCF_PAD_PAR_DSPI_PAR_SIN(x) (((x)&0x3)<<0x2)
|
||||
#define MCF_PAD_PAR_DSPI_PAR_SIN_GPIO (0)
|
||||
#define MCF_PAD_PAR_DSPI_PAR_SIN_RXD (0x8)
|
||||
#define MCF_PAD_PAR_DSPI_PAR_SIN_SIN (0xC)
|
||||
#define MCF_PAD_PAR_DSPI_PAR_SCK(x) (((x)&0x3)<<0x4)
|
||||
#define MCF_PAD_PAR_DSPI_PAR_SCK_GPIO (0)
|
||||
#define MCF_PAD_PAR_DSPI_PAR_SCK_BCLK (0x10)
|
||||
#define MCF_PAD_PAR_DSPI_PAR_SCK_CTS (0x20)
|
||||
#define MCF_PAD_PAR_DSPI_PAR_SCK_SCK (0x30)
|
||||
#define MCF_PAD_PAR_DSPI_PAR_CS0(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_PAD_PAR_DSPI_PAR_CS0_GPIO (0)
|
||||
#define MCF_PAD_PAR_DSPI_PAR_CS0_FSYNC (0x40)
|
||||
#define MCF_PAD_PAR_DSPI_PAR_CS0_RTS (0x80)
|
||||
#define MCF_PAD_PAR_DSPI_PAR_CS0_DSPICS0 (0xC0)
|
||||
#define MCF_PAD_PAR_DSPI_PAR_CS2(x) (((x)&0x3)<<0x8)
|
||||
#define MCF_PAD_PAR_DSPI_PAR_CS2_GPIO (0)
|
||||
#define MCF_PAD_PAR_DSPI_PAR_CS2_TOUT2 (0x200)
|
||||
#define MCF_PAD_PAR_DSPI_PAR_CS2_DSPICS2 (0x300)
|
||||
#define MCF_PAD_PAR_DSPI_PAR_CS3(x) (((x)&0x3)<<0xA)
|
||||
#define MCF_PAD_PAR_DSPI_PAR_CS3_GPIO (0)
|
||||
#define MCF_PAD_PAR_DSPI_PAR_CS3_TOUT3 (0x800)
|
||||
#define MCF_PAD_PAR_DSPI_PAR_CS3_DSPICS3 (0xC00)
|
||||
#define MCF_PAD_PAR_DSPI_PAR_CS5 (0x1000)
|
||||
|
||||
/* Bit definitions and macros for MCF_PAD_PAR_TIMER */
|
||||
#define MCF_PAD_PAR_TIMER_PAR_TOUT2 (0x1)
|
||||
#define MCF_PAD_PAR_TIMER_PAR_TIN2(x) (((x)&0x3)<<0x1)
|
||||
#define MCF_PAD_PAR_TIMER_PAR_TIN2_IRQ2 (0x4)
|
||||
#define MCF_PAD_PAR_TIMER_PAR_TIN2_TIN2 (0x6)
|
||||
#define MCF_PAD_PAR_TIMER_PAR_TOUT3 (0x8)
|
||||
#define MCF_PAD_PAR_TIMER_PAR_TIN3(x) (((x)&0x3)<<0x4)
|
||||
#define MCF_PAD_PAR_TIMER_PAR_TIN3_IRQ3 (0x20)
|
||||
#define MCF_PAD_PAR_TIMER_PAR_TIN3_TIN3 (0x30)
|
||||
|
||||
|
||||
#endif /* __MCF5475_PAD_H__ */
|
||||
43
include/MCF5475_PCIARB.h
Normal file
43
include/MCF5475_PCIARB.h
Normal file
@@ -0,0 +1,43 @@
|
||||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.81
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF5475_PCIARB_H__
|
||||
#define __MCF5475_PCIARB_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* PCI Bus Arbiter Module (PCIARB)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_PCIARB_PACR (*(volatile uint32_t*)(&_MBAR[0xC00]))
|
||||
#define MCF_PCIARB_PASR (*(volatile uint32_t*)(&_MBAR[0xC04]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_PCIARB_PACR */
|
||||
#define MCF_PCIARB_PACR_INTMPRI (0x1)
|
||||
#define MCF_PCIARB_PACR_EXTMPRI(x) (((x)&0x1F)<<0x1)
|
||||
#define MCF_PCIARB_PACR_INTMINTEN (0x10000)
|
||||
#define MCF_PCIARB_PACR_EXTMINTEN(x) (((x)&0x1F)<<0x11)
|
||||
#define MCF_PCIARB_PACR_DS (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCIARB_PASR */
|
||||
#define MCF_PCIARB_PASR_ITLMBK (0x10000)
|
||||
#define MCF_PCIARB_PASR_EXTMBK(x) (((x)&0x1F)<<0x11)
|
||||
|
||||
|
||||
#endif /* __MCF5475_PCIARB_H__ */
|
||||
527
include/MCF5475_PSC.h
Normal file
527
include/MCF5475_PSC.h
Normal file
@@ -0,0 +1,527 @@
|
||||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.81
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF5475_PSC_H__
|
||||
#define __MCF5475_PSC_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Programmable Serial Controller (PSC)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_PSC0_PSCMR2 (*(volatile uint8_t *)(&_MBAR[0x8600]))
|
||||
#define MCF_PSC0_PSCMR1 (*(volatile uint8_t *)(&_MBAR[0x8600]))
|
||||
#define MCF_PSC0_PSCCSR (*(volatile uint8_t *)(&_MBAR[0x8604]))
|
||||
#define MCF_PSC0_PSCSR (*(volatile uint16_t*)(&_MBAR[0x8604]))
|
||||
#define MCF_PSC0_PSCCR (*(volatile uint8_t *)(&_MBAR[0x8608]))
|
||||
#define MCF_PSC0_PSCRB_8BIT (*(volatile uint32_t*)(&_MBAR[0x860C]))
|
||||
#define MCF_PSC0_PSCTB_8BIT (*(volatile uint32_t*)(&_MBAR[0x860C]))
|
||||
#define MCF_PSC0_PSCRB_16BIT (*(volatile uint32_t*)(&_MBAR[0x860C]))
|
||||
#define MCF_PSC0_PSCTB_16BIT (*(volatile uint32_t*)(&_MBAR[0x860C]))
|
||||
#define MCF_PSC0_PSCRB_AC97 (*(volatile uint32_t*)(&_MBAR[0x860C]))
|
||||
#define MCF_PSC0_PSCTB_AC97 (*(volatile uint32_t*)(&_MBAR[0x860C]))
|
||||
#define MCF_PSC0_PSCIPCR (*(volatile uint8_t *)(&_MBAR[0x8610]))
|
||||
#define MCF_PSC0_PSCACR (*(volatile uint8_t *)(&_MBAR[0x8610]))
|
||||
#define MCF_PSC0_PSCIMR (*(volatile uint16_t*)(&_MBAR[0x8614]))
|
||||
#define MCF_PSC0_PSCISR (*(volatile uint16_t*)(&_MBAR[0x8614]))
|
||||
#define MCF_PSC0_PSCCTUR (*(volatile uint8_t *)(&_MBAR[0x8618]))
|
||||
#define MCF_PSC0_PSCCTLR (*(volatile uint8_t *)(&_MBAR[0x861C]))
|
||||
#define MCF_PSC0_PSCIP (*(volatile uint8_t *)(&_MBAR[0x8634]))
|
||||
#define MCF_PSC0_PSCOPSET (*(volatile uint8_t *)(&_MBAR[0x8638]))
|
||||
#define MCF_PSC0_PSCOPRESET (*(volatile uint8_t *)(&_MBAR[0x863C]))
|
||||
#define MCF_PSC0_PSCSICR (*(volatile uint8_t *)(&_MBAR[0x8640]))
|
||||
#define MCF_PSC0_PSCIRCR1 (*(volatile uint8_t *)(&_MBAR[0x8644]))
|
||||
#define MCF_PSC0_PSCIRCR2 (*(volatile uint8_t *)(&_MBAR[0x8648]))
|
||||
#define MCF_PSC0_PSCIRSDR (*(volatile uint8_t *)(&_MBAR[0x864C]))
|
||||
#define MCF_PSC0_PSCIRMDR (*(volatile uint8_t *)(&_MBAR[0x8650]))
|
||||
#define MCF_PSC0_PSCIRFDR (*(volatile uint8_t *)(&_MBAR[0x8654]))
|
||||
#define MCF_PSC0_PSCRFCNT (*(volatile uint16_t*)(&_MBAR[0x8658]))
|
||||
#define MCF_PSC0_PSCTFCNT (*(volatile uint16_t*)(&_MBAR[0x865C]))
|
||||
#define MCF_PSC0_PSCRFDR (*(volatile uint32_t*)(&_MBAR[0x8660]))
|
||||
#define MCF_PSC0_PSCRFSR (*(volatile uint16_t*)(&_MBAR[0x8664]))
|
||||
#define MCF_PSC0_PSCRFCR (*(volatile uint32_t*)(&_MBAR[0x8668]))
|
||||
#define MCF_PSC0_PSCRFAR (*(volatile uint16_t*)(&_MBAR[0x866E]))
|
||||
#define MCF_PSC0_PSCRFRP (*(volatile uint16_t*)(&_MBAR[0x8672]))
|
||||
#define MCF_PSC0_PSCRFWP (*(volatile uint16_t*)(&_MBAR[0x8676]))
|
||||
#define MCF_PSC0_PSCRLRFP (*(volatile uint16_t*)(&_MBAR[0x867A]))
|
||||
#define MCF_PSC0_PSCRLWFP (*(volatile uint16_t*)(&_MBAR[0x867E]))
|
||||
#define MCF_PSC0_PSCTFDR (*(volatile uint32_t*)(&_MBAR[0x8680]))
|
||||
#define MCF_PSC0_PSCTFSR (*(volatile uint16_t*)(&_MBAR[0x8684]))
|
||||
#define MCF_PSC0_PSCTFCR (*(volatile uint32_t*)(&_MBAR[0x8688]))
|
||||
#define MCF_PSC0_PSCTFAR (*(volatile uint16_t*)(&_MBAR[0x868E]))
|
||||
#define MCF_PSC0_PSCTFRP (*(volatile uint16_t*)(&_MBAR[0x8692]))
|
||||
#define MCF_PSC0_PSCTFWP (*(volatile uint16_t*)(&_MBAR[0x8696]))
|
||||
#define MCF_PSC0_PSCTLRFP (*(volatile uint16_t*)(&_MBAR[0x869A]))
|
||||
#define MCF_PSC0_PSCTLWFP (*(volatile uint16_t*)(&_MBAR[0x869E]))
|
||||
|
||||
#define MCF_PSC1_PSCMR2 (*(volatile uint8_t *)(&_MBAR[0x8700]))
|
||||
#define MCF_PSC1_PSCMR1 (*(volatile uint8_t *)(&_MBAR[0x8700]))
|
||||
#define MCF_PSC1_PSCCSR (*(volatile uint8_t *)(&_MBAR[0x8704]))
|
||||
#define MCF_PSC1_PSCSR (*(volatile uint16_t*)(&_MBAR[0x8704]))
|
||||
#define MCF_PSC1_PSCCR (*(volatile uint8_t *)(&_MBAR[0x8708]))
|
||||
#define MCF_PSC1_PSCRB_8BIT (*(volatile uint32_t*)(&_MBAR[0x870C]))
|
||||
#define MCF_PSC1_PSCTB_8BIT (*(volatile uint32_t*)(&_MBAR[0x870C]))
|
||||
#define MCF_PSC1_PSCRB_16BIT (*(volatile uint32_t*)(&_MBAR[0x870C]))
|
||||
#define MCF_PSC1_PSCTB_16BIT (*(volatile uint32_t*)(&_MBAR[0x870C]))
|
||||
#define MCF_PSC1_PSCRB_AC97 (*(volatile uint32_t*)(&_MBAR[0x870C]))
|
||||
#define MCF_PSC1_PSCTB_AC97 (*(volatile uint32_t*)(&_MBAR[0x870C]))
|
||||
#define MCF_PSC1_PSCIPCR (*(volatile uint8_t *)(&_MBAR[0x8710]))
|
||||
#define MCF_PSC1_PSCACR (*(volatile uint8_t *)(&_MBAR[0x8710]))
|
||||
#define MCF_PSC1_PSCIMR (*(volatile uint16_t*)(&_MBAR[0x8714]))
|
||||
#define MCF_PSC1_PSCISR (*(volatile uint16_t*)(&_MBAR[0x8714]))
|
||||
#define MCF_PSC1_PSCCTUR (*(volatile uint8_t *)(&_MBAR[0x8718]))
|
||||
#define MCF_PSC1_PSCCTLR (*(volatile uint8_t *)(&_MBAR[0x871C]))
|
||||
#define MCF_PSC1_PSCIP (*(volatile uint8_t *)(&_MBAR[0x8734]))
|
||||
#define MCF_PSC1_PSCOPSET (*(volatile uint8_t *)(&_MBAR[0x8738]))
|
||||
#define MCF_PSC1_PSCOPRESET (*(volatile uint8_t *)(&_MBAR[0x873C]))
|
||||
#define MCF_PSC1_PSCSICR (*(volatile uint8_t *)(&_MBAR[0x8740]))
|
||||
#define MCF_PSC1_PSCIRCR1 (*(volatile uint8_t *)(&_MBAR[0x8744]))
|
||||
#define MCF_PSC1_PSCIRCR2 (*(volatile uint8_t *)(&_MBAR[0x8748]))
|
||||
#define MCF_PSC1_PSCIRSDR (*(volatile uint8_t *)(&_MBAR[0x874C]))
|
||||
#define MCF_PSC1_PSCIRMDR (*(volatile uint8_t *)(&_MBAR[0x8750]))
|
||||
#define MCF_PSC1_PSCIRFDR (*(volatile uint8_t *)(&_MBAR[0x8754]))
|
||||
#define MCF_PSC1_PSCRFCNT (*(volatile uint16_t*)(&_MBAR[0x8758]))
|
||||
#define MCF_PSC1_PSCTFCNT (*(volatile uint16_t*)(&_MBAR[0x875C]))
|
||||
#define MCF_PSC1_PSCRFDR (*(volatile uint32_t*)(&_MBAR[0x8760]))
|
||||
#define MCF_PSC1_PSCRFSR (*(volatile uint16_t*)(&_MBAR[0x8764]))
|
||||
#define MCF_PSC1_PSCRFCR (*(volatile uint32_t*)(&_MBAR[0x8768]))
|
||||
#define MCF_PSC1_PSCRFAR (*(volatile uint16_t*)(&_MBAR[0x876E]))
|
||||
#define MCF_PSC1_PSCRFRP (*(volatile uint16_t*)(&_MBAR[0x8772]))
|
||||
#define MCF_PSC1_PSCRFWP (*(volatile uint16_t*)(&_MBAR[0x8776]))
|
||||
#define MCF_PSC1_PSCRLRFP (*(volatile uint16_t*)(&_MBAR[0x877A]))
|
||||
#define MCF_PSC1_PSCRLWFP (*(volatile uint16_t*)(&_MBAR[0x877E]))
|
||||
#define MCF_PSC1_PSCTFDR (*(volatile uint32_t*)(&_MBAR[0x8780]))
|
||||
#define MCF_PSC1_PSCTFSR (*(volatile uint16_t*)(&_MBAR[0x8784]))
|
||||
#define MCF_PSC1_PSCTFCR (*(volatile uint32_t*)(&_MBAR[0x8788]))
|
||||
#define MCF_PSC1_PSCTFAR (*(volatile uint16_t*)(&_MBAR[0x878E]))
|
||||
#define MCF_PSC1_PSCTFRP (*(volatile uint16_t*)(&_MBAR[0x8792]))
|
||||
#define MCF_PSC1_PSCTFWP (*(volatile uint16_t*)(&_MBAR[0x8796]))
|
||||
#define MCF_PSC1_PSCTLRFP (*(volatile uint16_t*)(&_MBAR[0x879A]))
|
||||
#define MCF_PSC1_PSCTLWFP (*(volatile uint16_t*)(&_MBAR[0x879E]))
|
||||
|
||||
#define MCF_PSC2_PSCMR2 (*(volatile uint8_t *)(&_MBAR[0x8800]))
|
||||
#define MCF_PSC2_PSCMR1 (*(volatile uint8_t *)(&_MBAR[0x8800]))
|
||||
#define MCF_PSC2_PSCCSR (*(volatile uint8_t *)(&_MBAR[0x8804]))
|
||||
#define MCF_PSC2_PSCSR (*(volatile uint16_t*)(&_MBAR[0x8804]))
|
||||
#define MCF_PSC2_PSCCR (*(volatile uint8_t *)(&_MBAR[0x8808]))
|
||||
#define MCF_PSC2_PSCRB_8BIT (*(volatile uint32_t*)(&_MBAR[0x880C]))
|
||||
#define MCF_PSC2_PSCTB_8BIT (*(volatile uint32_t*)(&_MBAR[0x880C]))
|
||||
#define MCF_PSC2_PSCRB_16BIT (*(volatile uint32_t*)(&_MBAR[0x880C]))
|
||||
#define MCF_PSC2_PSCTB_16BIT (*(volatile uint32_t*)(&_MBAR[0x880C]))
|
||||
#define MCF_PSC2_PSCRB_AC97 (*(volatile uint32_t*)(&_MBAR[0x880C]))
|
||||
#define MCF_PSC2_PSCTB_AC97 (*(volatile uint32_t*)(&_MBAR[0x880C]))
|
||||
#define MCF_PSC2_PSCIPCR (*(volatile uint8_t *)(&_MBAR[0x8810]))
|
||||
#define MCF_PSC2_PSCACR (*(volatile uint8_t *)(&_MBAR[0x8810]))
|
||||
#define MCF_PSC2_PSCIMR (*(volatile uint16_t*)(&_MBAR[0x8814]))
|
||||
#define MCF_PSC2_PSCISR (*(volatile uint16_t*)(&_MBAR[0x8814]))
|
||||
#define MCF_PSC2_PSCCTUR (*(volatile uint8_t *)(&_MBAR[0x8818]))
|
||||
#define MCF_PSC2_PSCCTLR (*(volatile uint8_t *)(&_MBAR[0x881C]))
|
||||
#define MCF_PSC2_PSCIP (*(volatile uint8_t *)(&_MBAR[0x8834]))
|
||||
#define MCF_PSC2_PSCOPSET (*(volatile uint8_t *)(&_MBAR[0x8838]))
|
||||
#define MCF_PSC2_PSCOPRESET (*(volatile uint8_t *)(&_MBAR[0x883C]))
|
||||
#define MCF_PSC2_PSCSICR (*(volatile uint8_t *)(&_MBAR[0x8840]))
|
||||
#define MCF_PSC2_PSCIRCR1 (*(volatile uint8_t *)(&_MBAR[0x8844]))
|
||||
#define MCF_PSC2_PSCIRCR2 (*(volatile uint8_t *)(&_MBAR[0x8848]))
|
||||
#define MCF_PSC2_PSCIRSDR (*(volatile uint8_t *)(&_MBAR[0x884C]))
|
||||
#define MCF_PSC2_PSCIRMDR (*(volatile uint8_t *)(&_MBAR[0x8850]))
|
||||
#define MCF_PSC2_PSCIRFDR (*(volatile uint8_t *)(&_MBAR[0x8854]))
|
||||
#define MCF_PSC2_PSCRFCNT (*(volatile uint16_t*)(&_MBAR[0x8858]))
|
||||
#define MCF_PSC2_PSCTFCNT (*(volatile uint16_t*)(&_MBAR[0x885C]))
|
||||
#define MCF_PSC2_PSCRFDR (*(volatile uint32_t*)(&_MBAR[0x8860]))
|
||||
#define MCF_PSC2_PSCRFSR (*(volatile uint16_t*)(&_MBAR[0x8864]))
|
||||
#define MCF_PSC2_PSCRFCR (*(volatile uint32_t*)(&_MBAR[0x8868]))
|
||||
#define MCF_PSC2_PSCRFAR (*(volatile uint16_t*)(&_MBAR[0x886E]))
|
||||
#define MCF_PSC2_PSCRFRP (*(volatile uint16_t*)(&_MBAR[0x8872]))
|
||||
#define MCF_PSC2_PSCRFWP (*(volatile uint16_t*)(&_MBAR[0x8876]))
|
||||
#define MCF_PSC2_PSCRLRFP (*(volatile uint16_t*)(&_MBAR[0x887A]))
|
||||
#define MCF_PSC2_PSCRLWFP (*(volatile uint16_t*)(&_MBAR[0x887E]))
|
||||
#define MCF_PSC2_PSCTFDR (*(volatile uint32_t*)(&_MBAR[0x8880]))
|
||||
#define MCF_PSC2_PSCTFSR (*(volatile uint16_t*)(&_MBAR[0x8884]))
|
||||
#define MCF_PSC2_PSCTFCR (*(volatile uint32_t*)(&_MBAR[0x8888]))
|
||||
#define MCF_PSC2_PSCTFAR (*(volatile uint16_t*)(&_MBAR[0x888E]))
|
||||
#define MCF_PSC2_PSCTFRP (*(volatile uint16_t*)(&_MBAR[0x8892]))
|
||||
#define MCF_PSC2_PSCTFWP (*(volatile uint16_t*)(&_MBAR[0x8896]))
|
||||
#define MCF_PSC2_PSCTLRFP (*(volatile uint16_t*)(&_MBAR[0x889A]))
|
||||
#define MCF_PSC2_PSCTLWFP (*(volatile uint16_t*)(&_MBAR[0x889E]))
|
||||
|
||||
#define MCF_PSC3_PSCMR2 (*(volatile uint8_t *)(&_MBAR[0x8900]))
|
||||
#define MCF_PSC3_PSCMR1 (*(volatile uint8_t *)(&_MBAR[0x8900]))
|
||||
#define MCF_PSC3_PSCCSR (*(volatile uint8_t *)(&_MBAR[0x8904]))
|
||||
#define MCF_PSC3_PSCSR (*(volatile uint16_t*)(&_MBAR[0x8904]))
|
||||
#define MCF_PSC3_PSCCR (*(volatile uint8_t *)(&_MBAR[0x8908]))
|
||||
#define MCF_PSC3_PSCRB_8BIT (*(volatile uint32_t*)(&_MBAR[0x890C]))
|
||||
#define MCF_PSC3_PSCTB_8BIT (*(volatile uint32_t*)(&_MBAR[0x890C]))
|
||||
#define MCF_PSC3_PSCRB_16BIT (*(volatile uint32_t*)(&_MBAR[0x890C]))
|
||||
#define MCF_PSC3_PSCTB_16BIT (*(volatile uint32_t*)(&_MBAR[0x890C]))
|
||||
#define MCF_PSC3_PSCRB_AC97 (*(volatile uint32_t*)(&_MBAR[0x890C]))
|
||||
#define MCF_PSC3_PSCTB_AC97 (*(volatile uint32_t*)(&_MBAR[0x890C]))
|
||||
#define MCF_PSC3_PSCIPCR (*(volatile uint8_t *)(&_MBAR[0x8910]))
|
||||
#define MCF_PSC3_PSCACR (*(volatile uint8_t *)(&_MBAR[0x8910]))
|
||||
#define MCF_PSC3_PSCIMR (*(volatile uint16_t*)(&_MBAR[0x8914]))
|
||||
#define MCF_PSC3_PSCISR (*(volatile uint16_t*)(&_MBAR[0x8914]))
|
||||
#define MCF_PSC3_PSCCTUR (*(volatile uint8_t *)(&_MBAR[0x8918]))
|
||||
#define MCF_PSC3_PSCCTLR (*(volatile uint8_t *)(&_MBAR[0x891C]))
|
||||
#define MCF_PSC3_PSCIP (*(volatile uint8_t *)(&_MBAR[0x8934]))
|
||||
#define MCF_PSC3_PSCOPSET (*(volatile uint8_t *)(&_MBAR[0x8938]))
|
||||
#define MCF_PSC3_PSCOPRESET (*(volatile uint8_t *)(&_MBAR[0x893C]))
|
||||
#define MCF_PSC3_PSCSICR (*(volatile uint8_t *)(&_MBAR[0x8940]))
|
||||
#define MCF_PSC3_PSCIRCR1 (*(volatile uint8_t *)(&_MBAR[0x8944]))
|
||||
#define MCF_PSC3_PSCIRCR2 (*(volatile uint8_t *)(&_MBAR[0x8948]))
|
||||
#define MCF_PSC3_PSCIRSDR (*(volatile uint8_t *)(&_MBAR[0x894C]))
|
||||
#define MCF_PSC3_PSCIRMDR (*(volatile uint8_t *)(&_MBAR[0x8950]))
|
||||
#define MCF_PSC3_PSCIRFDR (*(volatile uint8_t *)(&_MBAR[0x8954]))
|
||||
#define MCF_PSC3_PSCRFCNT (*(volatile uint16_t*)(&_MBAR[0x8958]))
|
||||
#define MCF_PSC3_PSCTFCNT (*(volatile uint16_t*)(&_MBAR[0x895C]))
|
||||
#define MCF_PSC3_PSCRFDR (*(volatile uint32_t*)(&_MBAR[0x8960]))
|
||||
#define MCF_PSC3_PSCRFSR (*(volatile uint16_t*)(&_MBAR[0x8964]))
|
||||
#define MCF_PSC3_PSCRFCR (*(volatile uint32_t*)(&_MBAR[0x8968]))
|
||||
#define MCF_PSC3_PSCRFAR (*(volatile uint16_t*)(&_MBAR[0x896E]))
|
||||
#define MCF_PSC3_PSCRFRP (*(volatile uint16_t*)(&_MBAR[0x8972]))
|
||||
#define MCF_PSC3_PSCRFWP (*(volatile uint16_t*)(&_MBAR[0x8976]))
|
||||
#define MCF_PSC3_PSCRLRFP (*(volatile uint16_t*)(&_MBAR[0x897A]))
|
||||
#define MCF_PSC3_PSCRLWFP (*(volatile uint16_t*)(&_MBAR[0x897E]))
|
||||
#define MCF_PSC3_PSCTFDR (*(volatile uint32_t*)(&_MBAR[0x8980]))
|
||||
#define MCF_PSC3_PSCTFSR (*(volatile uint16_t*)(&_MBAR[0x8984]))
|
||||
#define MCF_PSC3_PSCTFCR (*(volatile uint32_t*)(&_MBAR[0x8988]))
|
||||
#define MCF_PSC3_PSCTFAR (*(volatile uint16_t*)(&_MBAR[0x898E]))
|
||||
#define MCF_PSC3_PSCTFRP (*(volatile uint16_t*)(&_MBAR[0x8992]))
|
||||
#define MCF_PSC3_PSCTFWP (*(volatile uint16_t*)(&_MBAR[0x8996]))
|
||||
#define MCF_PSC3_PSCTLRFP (*(volatile uint16_t*)(&_MBAR[0x899A]))
|
||||
#define MCF_PSC3_PSCTLWFP (*(volatile uint16_t*)(&_MBAR[0x899E]))
|
||||
|
||||
#define MCF_PSC_PSCMR(x) (*(volatile uint8_t *)(&_MBAR[0x8600 + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCCSR(x) (*(volatile uint8_t *)(&_MBAR[0x8604 + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCSR(x) (*(volatile uint16_t*)(&_MBAR[0x8604 + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCCR(x) (*(volatile uint8_t *)(&_MBAR[0x8608 + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCRB_8BIT(x) (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCTB_8BIT(x) (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCRB_16BIT(x) (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCTB_16BIT(x) (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCRB_AC97(x) (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCTB_AC97(x) (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCIPCR(x) (*(volatile uint8_t *)(&_MBAR[0x8610 + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCACR(x) (*(volatile uint8_t *)(&_MBAR[0x8610 + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCIMR(x) (*(volatile uint16_t*)(&_MBAR[0x8614 + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCISR(x) (*(volatile uint16_t*)(&_MBAR[0x8614 + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCCTUR(x) (*(volatile uint8_t *)(&_MBAR[0x8618 + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCCTLR(x) (*(volatile uint8_t *)(&_MBAR[0x861C + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCIP(x) (*(volatile uint8_t *)(&_MBAR[0x8634 + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCOPSET(x) (*(volatile uint8_t *)(&_MBAR[0x8638 + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCOPRESET(x) (*(volatile uint8_t *)(&_MBAR[0x863C + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCSICR(x) (*(volatile uint8_t *)(&_MBAR[0x8640 + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCIRCR1(x) (*(volatile uint8_t *)(&_MBAR[0x8644 + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCIRCR2(x) (*(volatile uint8_t *)(&_MBAR[0x8648 + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCIRSDR(x) (*(volatile uint8_t *)(&_MBAR[0x864C + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCIRMDR(x) (*(volatile uint8_t *)(&_MBAR[0x8650 + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCIRFDR(x) (*(volatile uint8_t *)(&_MBAR[0x8654 + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCRFCNT(x) (*(volatile uint16_t*)(&_MBAR[0x8658 + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCTFCNT(x) (*(volatile uint16_t*)(&_MBAR[0x865C + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCRFDR(x) (*(volatile uint32_t*)(&_MBAR[0x8660 + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCRFSR(x) (*(volatile uint16_t*)(&_MBAR[0x8664 + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCRFCR(x) (*(volatile uint32_t*)(&_MBAR[0x8668 + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCRFAR(x) (*(volatile uint16_t*)(&_MBAR[0x866E + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCRFRP(x) (*(volatile uint16_t*)(&_MBAR[0x8672 + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCRFWP(x) (*(volatile uint16_t*)(&_MBAR[0x8676 + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCRLRFP(x) (*(volatile uint16_t*)(&_MBAR[0x867A + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCRLWFP(x) (*(volatile uint16_t*)(&_MBAR[0x867E + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCTFDR(x) (*(volatile uint32_t*)(&_MBAR[0x8680 + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCTFSR(x) (*(volatile uint16_t*)(&_MBAR[0x8684 + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCTFCR(x) (*(volatile uint32_t*)(&_MBAR[0x8688 + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCTFAR(x) (*(volatile uint16_t*)(&_MBAR[0x868E + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCTFRP(x) (*(volatile uint16_t*)(&_MBAR[0x8692 + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCTFWP(x) (*(volatile uint16_t*)(&_MBAR[0x8696 + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCTLRFP(x) (*(volatile uint16_t*)(&_MBAR[0x869A + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCTLWFP(x) (*(volatile uint16_t*)(&_MBAR[0x869E + ((x)*0x100)]))
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCMR */
|
||||
#define MCF_PSC_PSCMR_SB(x) (((x)&0xF)<<0)
|
||||
#define MCF_PSC_PSCMR_TXCTS (0x10)
|
||||
#define MCF_PSC_PSCMR_TXRTS (0x20)
|
||||
#define MCF_PSC_PSCMR_CM(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_PSC_PSCMR_CM_NORMAL (0)
|
||||
#define MCF_PSC_PSCMR_CM_ECHO (0x40)
|
||||
#define MCF_PSC_PSCMR_CM_LOCAL_LOOP (0x80)
|
||||
#define MCF_PSC_PSCMR_CM_REMOTE_LOOP (0xC0)
|
||||
#define MCF_PSC_PSCMR_SB_STOP_BITS_1 (0x7)
|
||||
#define MCF_PSC_PSCMR_SB_STOP_BITS_15 (0x8)
|
||||
#define MCF_PSC_PSCMR_SB_STOP_BITS_2 (0xF)
|
||||
#define MCF_PSC_PSCMR_PM_MULTI_ADDR (0x1C)
|
||||
#define MCF_PSC_PSCMR_PM_MULTI_DATA (0x18)
|
||||
#define MCF_PSC_PSCMR_PM_NONE (0x10)
|
||||
#define MCF_PSC_PSCMR_PM_FORCE_HI (0xC)
|
||||
#define MCF_PSC_PSCMR_PM_FORCE_LO (0x8)
|
||||
#define MCF_PSC_PSCMR_PM_ODD (0x4)
|
||||
#define MCF_PSC_PSCMR_PM_EVEN (0)
|
||||
#define MCF_PSC_PSCMR_BC(x) (((x)&0x3)<<0)
|
||||
#define MCF_PSC_PSCMR_BC_5 (0)
|
||||
#define MCF_PSC_PSCMR_BC_6 (0x1)
|
||||
#define MCF_PSC_PSCMR_BC_7 (0x2)
|
||||
#define MCF_PSC_PSCMR_BC_8 (0x3)
|
||||
#define MCF_PSC_PSCMR_PT (0x4)
|
||||
#define MCF_PSC_PSCMR_PM(x) (((x)&0x3)<<0x3)
|
||||
#define MCF_PSC_PSCMR_ERR (0x20)
|
||||
#define MCF_PSC_PSCMR_RXIRQ_FU (0x40)
|
||||
#define MCF_PSC_PSCMR_RXRTS (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCCSR */
|
||||
#define MCF_PSC_PSCCSR_TCSEL(x) (((x)&0xF)<<0)
|
||||
#define MCF_PSC_PSCCSR_RCSEL(x) (((x)&0xF)<<0x4)
|
||||
#define MCF_PSC_PSCCSR_TCSEL_SYS_CLK (0x0D)
|
||||
#define MCF_PSC_PSCCSR_TCSEL_CTM16 (0x0E)
|
||||
#define MCF_PSC_PSCCSR_TCSEL_CTM (0x0F)
|
||||
#define MCF_PSC_PSCCSR_RCSEL_SYS_CLK (0xD0)
|
||||
#define MCF_PSC_PSCCSR_RCSEL_CTM16 (0xE0)
|
||||
#define MCF_PSC_PSCCSR_RCSEL_CTM (0xF0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCSR */
|
||||
#define MCF_PSC_PSCSR_ERR (0x40)
|
||||
#define MCF_PSC_PSCSR_CDE_DEOF (0x80)
|
||||
#define MCF_PSC_PSCSR_RXRDY (0x100)
|
||||
#define MCF_PSC_PSCSR_FU (0x200)
|
||||
#define MCF_PSC_PSCSR_TXRDY (0x400)
|
||||
#define MCF_PSC_PSCSR_TXEMP_URERR (0x800)
|
||||
#define MCF_PSC_PSCSR_OE (0x1000)
|
||||
#define MCF_PSC_PSCSR_PE_CRCERR (0x2000)
|
||||
#define MCF_PSC_PSCSR_FE_PHYERR (0x4000)
|
||||
#define MCF_PSC_PSCSR_RB_NEOF (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCCR */
|
||||
#define MCF_PSC_PSCCR_RXC(x) (((x)&0x3)<<0)
|
||||
#define MCF_PSC_PSCCR_RX_ENABLED (0x1)
|
||||
#define MCF_PSC_PSCCR_RX_DISABLED (0x2)
|
||||
#define MCF_PSC_PSCCR_TXC(x) (((x)&0x3)<<0x2)
|
||||
#define MCF_PSC_PSCCR_TX_ENABLED (0x4)
|
||||
#define MCF_PSC_PSCCR_TX_DISABLED (0x8)
|
||||
#define MCF_PSC_PSCCR_MISC(x) (((x)&0x7)<<0x4)
|
||||
#define MCF_PSC_PSCCR_NONE (0)
|
||||
#define MCF_PSC_PSCCR_RESET_MR (0x10)
|
||||
#define MCF_PSC_PSCCR_RESET_RX (0x20)
|
||||
#define MCF_PSC_PSCCR_RESET_TX (0x30)
|
||||
#define MCF_PSC_PSCCR_RESET_ERROR (0x40)
|
||||
#define MCF_PSC_PSCCR_RESET_BKCHGINT (0x50)
|
||||
#define MCF_PSC_PSCCR_START_BREAK (0x60)
|
||||
#define MCF_PSC_PSCCR_STOP_BREAK (0x70)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCRB_8BIT */
|
||||
#define MCF_PSC_PSCRB_8BIT_RB3(x) (((x)&0xFF)<<0)
|
||||
#define MCF_PSC_PSCRB_8BIT_RB2(x) (((x)&0xFF)<<0x8)
|
||||
#define MCF_PSC_PSCRB_8BIT_RB1(x) (((x)&0xFF)<<0x10)
|
||||
#define MCF_PSC_PSCRB_8BIT_RB0(x) (((x)&0xFF)<<0x18)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCTB_8BIT */
|
||||
#define MCF_PSC_PSCTB_8BIT_TB3(x) (((x)&0xFF)<<0)
|
||||
#define MCF_PSC_PSCTB_8BIT_TB2(x) (((x)&0xFF)<<0x8)
|
||||
#define MCF_PSC_PSCTB_8BIT_TB1(x) (((x)&0xFF)<<0x10)
|
||||
#define MCF_PSC_PSCTB_8BIT_TB0(x) (((x)&0xFF)<<0x18)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCRB_16BIT */
|
||||
#define MCF_PSC_PSCRB_16BIT_RB1(x) (((x)&0xFFFF)<<0)
|
||||
#define MCF_PSC_PSCRB_16BIT_RB0(x) (((x)&0xFFFF)<<0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCTB_16BIT */
|
||||
#define MCF_PSC_PSCTB_16BIT_TB1(x) (((x)&0xFFFF)<<0)
|
||||
#define MCF_PSC_PSCTB_16BIT_TB0(x) (((x)&0xFFFF)<<0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCRB_AC97 */
|
||||
#define MCF_PSC_PSCRB_AC97_SOF (0x800)
|
||||
#define MCF_PSC_PSCRB_AC97_RB(x) (((x)&0xFFFFF)<<0xC)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCTB_AC97 */
|
||||
#define MCF_PSC_PSCTB_AC97_TB(x) (((x)&0xFFFFF)<<0xC)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCIPCR */
|
||||
#define MCF_PSC_PSCIPCR_RESERVED (0xC)
|
||||
#define MCF_PSC_PSCIPCR_CTS (0xD)
|
||||
#define MCF_PSC_PSCIPCR_D_CTS (0x1C)
|
||||
#define MCF_PSC_PSCIPCR_SYNC (0x8C)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCACR */
|
||||
#define MCF_PSC_PSCACR_IEC0 (0x1)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCIMR */
|
||||
#define MCF_PSC_PSCIMR_ERR (0x40)
|
||||
#define MCF_PSC_PSCIMR_DEOF (0x80)
|
||||
#define MCF_PSC_PSCIMR_TXRDY (0x100)
|
||||
#define MCF_PSC_PSCIMR_RXRDY_FU (0x200)
|
||||
#define MCF_PSC_PSCIMR_DB (0x400)
|
||||
#define MCF_PSC_PSCIMR_IPC (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCISR */
|
||||
#define MCF_PSC_PSCISR_ERR (0x40)
|
||||
#define MCF_PSC_PSCISR_DEOF (0x80)
|
||||
#define MCF_PSC_PSCISR_TXRDY (0x100)
|
||||
#define MCF_PSC_PSCISR_RXRDY_FU (0x200)
|
||||
#define MCF_PSC_PSCISR_DB (0x400)
|
||||
#define MCF_PSC_PSCISR_IPC (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCCTUR */
|
||||
#define MCF_PSC_PSCCTUR_CT(x) (((x)&0xFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCCTLR */
|
||||
#define MCF_PSC_PSCCTLR_CT(x) (((x)&0xFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCIP */
|
||||
#define MCF_PSC_PSCIP_CTS (0x1)
|
||||
#define MCF_PSC_PSCIP_TGL (0x40)
|
||||
#define MCF_PSC_PSCIP_LPWR_B (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCOPSET */
|
||||
#define MCF_PSC_PSCOPSET_RTS (0x1)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCOPRESET */
|
||||
#define MCF_PSC_PSCOPRESET_RTS (0x1)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCSICR */
|
||||
#define MCF_PSC_PSCSICR_SIM(x) (((x)&0x7)<<0)
|
||||
#define MCF_PSC_PSCSICR_SIM_UART (0)
|
||||
#define MCF_PSC_PSCSICR_SIM_MODEM8 (0x1)
|
||||
#define MCF_PSC_PSCSICR_SIM_MODEM16 (0x2)
|
||||
#define MCF_PSC_PSCSICR_SIM_AC97 (0x3)
|
||||
#define MCF_PSC_PSCSICR_SIM_SIR (0x4)
|
||||
#define MCF_PSC_PSCSICR_SIM_MIR (0x5)
|
||||
#define MCF_PSC_PSCSICR_SIM_FIR (0x6)
|
||||
#define MCF_PSC_PSCSICR_SHDIR (0x10)
|
||||
#define MCF_PSC_PSCSICR_DTS1 (0x20)
|
||||
#define MCF_PSC_PSCSICR_AWR (0x40)
|
||||
#define MCF_PSC_PSCSICR_ACRB (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCIRCR1 */
|
||||
#define MCF_PSC_PSCIRCR1_SPUL (0x1)
|
||||
#define MCF_PSC_PSCIRCR1_SIPEN (0x2)
|
||||
#define MCF_PSC_PSCIRCR1_FD (0x4)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCIRCR2 */
|
||||
#define MCF_PSC_PSCIRCR2_NXTEOF (0x1)
|
||||
#define MCF_PSC_PSCIRCR2_ABORT (0x2)
|
||||
#define MCF_PSC_PSCIRCR2_SIPREQ (0x4)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCIRSDR */
|
||||
#define MCF_PSC_PSCIRSDR_IRSTIM(x) (((x)&0xFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCIRMDR */
|
||||
#define MCF_PSC_PSCIRMDR_M_FDIV(x) (((x)&0x7F)<<0)
|
||||
#define MCF_PSC_PSCIRMDR_FREQ (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCIRFDR */
|
||||
#define MCF_PSC_PSCIRFDR_F_FDIV(x) (((x)&0xF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCRFCNT */
|
||||
#define MCF_PSC_PSCRFCNT_CNT(x) (((x)&0x1FF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCTFCNT */
|
||||
#define MCF_PSC_PSCTFCNT_CNT(x) (((x)&0x1FF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCRFDR */
|
||||
#define MCF_PSC_PSCRFDR_DATA(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCRFSR */
|
||||
#define MCF_PSC_PSCRFSR_EMT (0x1)
|
||||
#define MCF_PSC_PSCRFSR_ALARM (0x2)
|
||||
#define MCF_PSC_PSCRFSR_FU (0x4)
|
||||
#define MCF_PSC_PSCRFSR_FRMRDY (0x8)
|
||||
#define MCF_PSC_PSCRFSR_OF (0x10)
|
||||
#define MCF_PSC_PSCRFSR_UF (0x20)
|
||||
#define MCF_PSC_PSCRFSR_RXW (0x40)
|
||||
#define MCF_PSC_PSCRFSR_FAE (0x80)
|
||||
#define MCF_PSC_PSCRFSR_FRM(x) (((x)&0xF)<<0x8)
|
||||
#define MCF_PSC_PSCRFSR_FRM_BYTE0 (0x800)
|
||||
#define MCF_PSC_PSCRFSR_FRM_BYTE1 (0x400)
|
||||
#define MCF_PSC_PSCRFSR_FRM_BYTE2 (0x200)
|
||||
#define MCF_PSC_PSCRFSR_FRM_BYTE3 (0x100)
|
||||
#define MCF_PSC_PSCRFSR_TAG(x) (((x)&0x3)<<0xC)
|
||||
#define MCF_PSC_PSCRFSR_TXW (0x4000)
|
||||
#define MCF_PSC_PSCRFSR_IP (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCRFCR */
|
||||
#define MCF_PSC_PSCRFCR_CNTR(x) (((x)&0xFFFF)<<0)
|
||||
#define MCF_PSC_PSCRFCR_TXW_MSK (0x40000)
|
||||
#define MCF_PSC_PSCRFCR_OF_MSK (0x80000)
|
||||
#define MCF_PSC_PSCRFCR_UF_MSK (0x100000)
|
||||
#define MCF_PSC_PSCRFCR_RXW_MSK (0x200000)
|
||||
#define MCF_PSC_PSCRFCR_FAE_MSK (0x400000)
|
||||
#define MCF_PSC_PSCRFCR_IP_MSK (0x800000)
|
||||
#define MCF_PSC_PSCRFCR_GR(x) (((x)&0x7)<<0x18)
|
||||
#define MCF_PSC_PSCRFCR_FRMEN (0x8000000)
|
||||
#define MCF_PSC_PSCRFCR_TIMER (0x10000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCRFAR */
|
||||
#define MCF_PSC_PSCRFAR_ALARM(x) (((x)&0x1FF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCRFRP */
|
||||
#define MCF_PSC_PSCRFRP_READ(x) (((x)&0x1FF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCRFWP */
|
||||
#define MCF_PSC_PSCRFWP_WRITE(x) (((x)&0x1FF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCRLRFP */
|
||||
#define MCF_PSC_PSCRLRFP_LRFP(x) (((x)&0x1FF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCRLWFP */
|
||||
#define MCF_PSC_PSCRLWFP_LWFP(x) (((x)&0x1FF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCTFDR */
|
||||
#define MCF_PSC_PSCTFDR_DATA(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCTFSR */
|
||||
#define MCF_PSC_PSCTFSR_EMT (0x1)
|
||||
#define MCF_PSC_PSCTFSR_ALARM (0x2)
|
||||
#define MCF_PSC_PSCTFSR_FU (0x4)
|
||||
#define MCF_PSC_PSCTFSR_FRMRDY (0x8)
|
||||
#define MCF_PSC_PSCTFSR_OF (0x10)
|
||||
#define MCF_PSC_PSCTFSR_UF (0x20)
|
||||
#define MCF_PSC_PSCTFSR_RXW (0x40)
|
||||
#define MCF_PSC_PSCTFSR_FAE (0x80)
|
||||
#define MCF_PSC_PSCTFSR_FRM(x) (((x)&0xF)<<0x8)
|
||||
#define MCF_PSC_PSCTFSR_FRM_BYTE0 (0x800)
|
||||
#define MCF_PSC_PSCTFSR_FRM_BYTE1 (0x400)
|
||||
#define MCF_PSC_PSCTFSR_FRM_BYTE2 (0x200)
|
||||
#define MCF_PSC_PSCTFSR_FRM_BYTE3 (0x100)
|
||||
#define MCF_PSC_PSCTFSR_TAG(x) (((x)&0x3)<<0xC)
|
||||
#define MCF_PSC_PSCTFSR_TXW (0x4000)
|
||||
#define MCF_PSC_PSCTFSR_IP (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCTFCR */
|
||||
#define MCF_PSC_PSCTFCR_CNTR(x) (((x)&0xFFFF)<<0)
|
||||
#define MCF_PSC_PSCTFCR_TXW_MSK (0x40000)
|
||||
#define MCF_PSC_PSCTFCR_OF_MSK (0x80000)
|
||||
#define MCF_PSC_PSCTFCR_UF_MSK (0x100000)
|
||||
#define MCF_PSC_PSCTFCR_RXW_MSK (0x200000)
|
||||
#define MCF_PSC_PSCTFCR_FAE_MSK (0x400000)
|
||||
#define MCF_PSC_PSCTFCR_IP_MSK (0x800000)
|
||||
#define MCF_PSC_PSCTFCR_GR(x) (((x)&0x7)<<0x18)
|
||||
#define MCF_PSC_PSCTFCR_FRMEN (0x8000000)
|
||||
#define MCF_PSC_PSCTFCR_TIMER (0x10000000)
|
||||
#define MCF_PSC_PSCTFCR_WFR (0x20000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCTFAR */
|
||||
#define MCF_PSC_PSCTFAR_ALARM(x) (((x)&0x1FF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCTFRP */
|
||||
#define MCF_PSC_PSCTFRP_READ(x) (((x)&0x1FF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCTFWP */
|
||||
#define MCF_PSC_PSCTFWP_WRITE(x) (((x)&0x1FF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCTLRFP */
|
||||
#define MCF_PSC_PSCTLRFP_LRFP(x) (((x)&0x1FF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCTLWFP */
|
||||
#define MCF_PSC_PSCTLWFP_LWFP(x) (((x)&0x1FF)<<0)
|
||||
|
||||
|
||||
#endif /* __MCF5475_PSC_H__ */
|
||||
106
include/MCF5475_SDRAMC.h
Normal file
106
include/MCF5475_SDRAMC.h
Normal file
@@ -0,0 +1,106 @@
|
||||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.81
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF5475_SDRAMC_H__
|
||||
#define __MCF5475_SDRAMC_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Synchronous DRAM Controller (SDRAMC)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_SDRAMC_SDRAMDS (*(volatile uint32_t*)(&_MBAR[0x4]))
|
||||
#define MCF_SDRAMC_CS0CFG (*(volatile uint32_t*)(&_MBAR[0x20]))
|
||||
#define MCF_SDRAMC_CS1CFG (*(volatile uint32_t*)(&_MBAR[0x24]))
|
||||
#define MCF_SDRAMC_CS2CFG (*(volatile uint32_t*)(&_MBAR[0x28]))
|
||||
#define MCF_SDRAMC_CS3CFG (*(volatile uint32_t*)(&_MBAR[0x2C]))
|
||||
#define MCF_SDRAMC_SDMR (*(volatile uint32_t*)(&_MBAR[0x100]))
|
||||
#define MCF_SDRAMC_SDCR (*(volatile uint32_t*)(&_MBAR[0x104]))
|
||||
#define MCF_SDRAMC_SDCFG1 (*(volatile uint32_t*)(&_MBAR[0x108]))
|
||||
#define MCF_SDRAMC_SDCFG2 (*(volatile uint32_t*)(&_MBAR[0x10C]))
|
||||
#define MCF_SDRAMC_CSCFG(x) (*(volatile uint32_t*)(&_MBAR[0x20 + ((x)*0x4)]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_SDRAMC_SDRAMDS */
|
||||
#define MCF_SDRAMC_SDRAMDS_SB_D(x) (((x)&0x3)<<0)
|
||||
#define MCF_SDRAMC_SDRAMDS_SB_S(x) (((x)&0x3)<<0x2)
|
||||
#define MCF_SDRAMC_SDRAMDS_SB_A(x) (((x)&0x3)<<0x4)
|
||||
#define MCF_SDRAMC_SDRAMDS_SB_C(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_SDRAMC_SDRAMDS_SB_E(x) (((x)&0x3)<<0x8)
|
||||
#define MCF_SDRAMC_SDRAMDS_DRIVE_24MA (0)
|
||||
#define MCF_SDRAMC_SDRAMDS_DRIVE_16MA (0x1)
|
||||
#define MCF_SDRAMC_SDRAMDS_DRIVE_8MA (0x2)
|
||||
#define MCF_SDRAMC_SDRAMDS_DRIVE_NONE (0x3)
|
||||
|
||||
/* Bit definitions and macros for MCF_SDRAMC_CSCFG */
|
||||
#define MCF_SDRAMC_CSCFG_CSSZ(x) (((x)&0x1F)<<0)
|
||||
#define MCF_SDRAMC_CSCFG_CSSZ_DISABLED (0)
|
||||
#define MCF_SDRAMC_CSCFG_CSSZ_1MBYTE (0x13)
|
||||
#define MCF_SDRAMC_CSCFG_CSSZ_2MBYTE (0x14)
|
||||
#define MCF_SDRAMC_CSCFG_CSSZ_4MBYTE (0x15)
|
||||
#define MCF_SDRAMC_CSCFG_CSSZ_8MBYTE (0x16)
|
||||
#define MCF_SDRAMC_CSCFG_CSSZ_16MBYTE (0x17)
|
||||
#define MCF_SDRAMC_CSCFG_CSSZ_32MBYTE (0x18)
|
||||
#define MCF_SDRAMC_CSCFG_CSSZ_64MBYTE (0x19)
|
||||
#define MCF_SDRAMC_CSCFG_CSSZ_128MBYTE (0x1A)
|
||||
#define MCF_SDRAMC_CSCFG_CSSZ_256MBYTE (0x1B)
|
||||
#define MCF_SDRAMC_CSCFG_CSSZ_512MBYTE (0x1C)
|
||||
#define MCF_SDRAMC_CSCFG_CSSZ_1GBYTE (0x1D)
|
||||
#define MCF_SDRAMC_CSCFG_CSSZ_2GBYTE (0x1E)
|
||||
#define MCF_SDRAMC_CSCFG_CSSZ_4GBYTE (0x1F)
|
||||
#define MCF_SDRAMC_CSCFG_CSBA(x) (((x)&0xFFF)<<0x14)
|
||||
#define MCF_SDRAMC_CSCFG_BA(x) ((x)&0xFFF00000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SDRAMC_SDMR */
|
||||
#define MCF_SDRAMC_SDMR_CMD (0x10000)
|
||||
#define MCF_SDRAMC_SDMR_AD(x) (((x)&0xFFF)<<0x12)
|
||||
#define MCF_SDRAMC_SDMR_BNKAD(x) (((x)&0x3)<<0x1E)
|
||||
#define MCF_SDRAMC_SDMR_BK_LMR (0)
|
||||
#define MCF_SDRAMC_SDMR_BK_LEMR (0x40000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SDRAMC_SDCR */
|
||||
#define MCF_SDRAMC_SDCR_IPALL (0x2)
|
||||
#define MCF_SDRAMC_SDCR_IREF (0x4)
|
||||
#define MCF_SDRAMC_SDCR_BUFF (0x10)
|
||||
#define MCF_SDRAMC_SDCR_DQS_OE(x) (((x)&0xF)<<0x8)
|
||||
#define MCF_SDRAMC_SDCR_RCNT(x) (((x)&0x3F)<<0x10)
|
||||
#define MCF_SDRAMC_SDCR_DRIVE (0x400000)
|
||||
#define MCF_SDRAMC_SDCR_AP (0x800000)
|
||||
#define MCF_SDRAMC_SDCR_MUX(x) (((x)&0x3)<<0x18)
|
||||
#define MCF_SDRAMC_SDCR_REF (0x10000000)
|
||||
#define MCF_SDRAMC_SDCR_DDR (0x20000000)
|
||||
#define MCF_SDRAMC_SDCR_CKE (0x40000000)
|
||||
#define MCF_SDRAMC_SDCR_MODE_EN (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SDRAMC_SDCFG1 */
|
||||
#define MCF_SDRAMC_SDCFG1_WTLAT(x) (((x)&0x7)<<0x4)
|
||||
#define MCF_SDRAMC_SDCFG1_REF2ACT(x) (((x)&0xF)<<0x8)
|
||||
#define MCF_SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x7)<<0xC)
|
||||
#define MCF_SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x7)<<0x10)
|
||||
#define MCF_SDRAMC_SDCFG1_RDLAT(x) (((x)&0xF)<<0x14)
|
||||
#define MCF_SDRAMC_SDCFG1_SWT2RD(x) (((x)&0x7)<<0x18)
|
||||
#define MCF_SDRAMC_SDCFG1_SRD2RW(x) (((x)&0xF)<<0x1C)
|
||||
|
||||
/* Bit definitions and macros for MCF_SDRAMC_SDCFG2 */
|
||||
#define MCF_SDRAMC_SDCFG2_BL(x) (((x)&0xF)<<0x10)
|
||||
#define MCF_SDRAMC_SDCFG2_BRD2WT(x) (((x)&0xF)<<0x14)
|
||||
#define MCF_SDRAMC_SDCFG2_BWT2RW(x) (((x)&0xF)<<0x18)
|
||||
#define MCF_SDRAMC_SDCFG2_BRD2PRE(x) (((x)&0xF)<<0x1C)
|
||||
|
||||
|
||||
#endif /* __MCF5475_SDRAMC_H__ */
|
||||
398
include/MCF5475_SEC.h
Normal file
398
include/MCF5475_SEC.h
Normal file
@@ -0,0 +1,398 @@
|
||||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.81
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF5475_SEC_H__
|
||||
#define __MCF5475_SEC_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Integrated Security Engine (SEC)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_SEC_EUACRH (*(volatile uint32_t*)(&_MBAR[0x21000]))
|
||||
#define MCF_SEC_EUACRL (*(volatile uint32_t*)(&_MBAR[0x21004]))
|
||||
#define MCF_SEC_SIMRH (*(volatile uint32_t*)(&_MBAR[0x21008]))
|
||||
#define MCF_SEC_SIMRL (*(volatile uint32_t*)(&_MBAR[0x2100C]))
|
||||
#define MCF_SEC_SISRH (*(volatile uint32_t*)(&_MBAR[0x21010]))
|
||||
#define MCF_SEC_SISRL (*(volatile uint32_t*)(&_MBAR[0x21014]))
|
||||
#define MCF_SEC_SICRH (*(volatile uint32_t*)(&_MBAR[0x21018]))
|
||||
#define MCF_SEC_SICRL (*(volatile uint32_t*)(&_MBAR[0x2101C]))
|
||||
#define MCF_SEC_SIDR (*(volatile uint32_t*)(&_MBAR[0x21020]))
|
||||
#define MCF_SEC_EUASRH (*(volatile uint32_t*)(&_MBAR[0x21028]))
|
||||
#define MCF_SEC_EUASRL (*(volatile uint32_t*)(&_MBAR[0x2102C]))
|
||||
#define MCF_SEC_SMCR (*(volatile uint32_t*)(&_MBAR[0x21030]))
|
||||
#define MCF_SEC_MEAR (*(volatile uint32_t*)(&_MBAR[0x21038]))
|
||||
#define MCF_SEC_CCCR0 (*(volatile uint32_t*)(&_MBAR[0x2200C]))
|
||||
#define MCF_SEC_CCPSRH0 (*(volatile uint32_t*)(&_MBAR[0x22010]))
|
||||
#define MCF_SEC_CCPSRL0 (*(volatile uint32_t*)(&_MBAR[0x22014]))
|
||||
#define MCF_SEC_CDPR0 (*(volatile uint32_t*)(&_MBAR[0x22044]))
|
||||
#define MCF_SEC_FR0 (*(volatile uint32_t*)(&_MBAR[0x2204C]))
|
||||
#define MCF_SEC_CCCR1 (*(volatile uint32_t*)(&_MBAR[0x2300C]))
|
||||
#define MCF_SEC_CCPSRH1 (*(volatile uint32_t*)(&_MBAR[0x23010]))
|
||||
#define MCF_SEC_CCPSRL1 (*(volatile uint32_t*)(&_MBAR[0x23014]))
|
||||
#define MCF_SEC_CDPR1 (*(volatile uint32_t*)(&_MBAR[0x23044]))
|
||||
#define MCF_SEC_FR1 (*(volatile uint32_t*)(&_MBAR[0x2304C]))
|
||||
#define MCF_SEC_AFRCR (*(volatile uint32_t*)(&_MBAR[0x28018]))
|
||||
#define MCF_SEC_AFSR (*(volatile uint32_t*)(&_MBAR[0x28028]))
|
||||
#define MCF_SEC_AFISR (*(volatile uint32_t*)(&_MBAR[0x28030]))
|
||||
#define MCF_SEC_AFIMR (*(volatile uint32_t*)(&_MBAR[0x28038]))
|
||||
#define MCF_SEC_DRCR (*(volatile uint32_t*)(&_MBAR[0x2A018]))
|
||||
#define MCF_SEC_DSR (*(volatile uint32_t*)(&_MBAR[0x2A028]))
|
||||
#define MCF_SEC_DISR (*(volatile uint32_t*)(&_MBAR[0x2A030]))
|
||||
#define MCF_SEC_DIMR (*(volatile uint32_t*)(&_MBAR[0x2A038]))
|
||||
#define MCF_SEC_MDRCR (*(volatile uint32_t*)(&_MBAR[0x2C018]))
|
||||
#define MCF_SEC_MDSR (*(volatile uint32_t*)(&_MBAR[0x2C028]))
|
||||
#define MCF_SEC_MDISR (*(volatile uint32_t*)(&_MBAR[0x2C030]))
|
||||
#define MCF_SEC_MDIMR (*(volatile uint32_t*)(&_MBAR[0x2C038]))
|
||||
#define MCF_SEC_RNGRCR (*(volatile uint32_t*)(&_MBAR[0x2E018]))
|
||||
#define MCF_SEC_RNGSR (*(volatile uint32_t*)(&_MBAR[0x2E028]))
|
||||
#define MCF_SEC_RNGISR (*(volatile uint32_t*)(&_MBAR[0x2E030]))
|
||||
#define MCF_SEC_RNGIMR (*(volatile uint32_t*)(&_MBAR[0x2E038]))
|
||||
#define MCF_SEC_AESRCR (*(volatile uint32_t*)(&_MBAR[0x32018]))
|
||||
#define MCF_SEC_AESSR (*(volatile uint32_t*)(&_MBAR[0x32028]))
|
||||
#define MCF_SEC_AESISR (*(volatile uint32_t*)(&_MBAR[0x32030]))
|
||||
#define MCF_SEC_AESIMR (*(volatile uint32_t*)(&_MBAR[0x32038]))
|
||||
#define MCF_SEC_CCCRn(x) (*(volatile uint32_t*)(&_MBAR[0x2200C + ((x)*0x1000)]))
|
||||
#define MCF_SEC_CCPSRHn(x) (*(volatile uint32_t*)(&_MBAR[0x22010 + ((x)*0x1000)]))
|
||||
#define MCF_SEC_CCPSRLn(x) (*(volatile uint32_t*)(&_MBAR[0x22014 + ((x)*0x1000)]))
|
||||
#define MCF_SEC_CDPRn(x) (*(volatile uint32_t*)(&_MBAR[0x22044 + ((x)*0x1000)]))
|
||||
#define MCF_SEC_FRn(x) (*(volatile uint32_t*)(&_MBAR[0x2204C + ((x)*0x1000)]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_EUACRH */
|
||||
#define MCF_SEC_EUACRH_AFEU(x) (((x)&0xF)<<0)
|
||||
#define MCF_SEC_EUACRH_AFFEU_NOASSIGN (0)
|
||||
#define MCF_SEC_EUACRH_AFFEU_CHA0 (0x1)
|
||||
#define MCF_SEC_EUACRH_AFFEU_CHA1 (0x2)
|
||||
#define MCF_SEC_EUACRH_MDEU(x) (((x)&0xF)<<0x8)
|
||||
#define MCF_SEC_EUACRH_MDEU_NOASSIGN (0)
|
||||
#define MCF_SEC_EUACRH_MDEU_CHA0 (0x100)
|
||||
#define MCF_SEC_EUACRH_MDEU_CHA1 (0x200)
|
||||
#define MCF_SEC_EUACRH_RNG(x) (((x)&0xF)<<0x18)
|
||||
#define MCF_SEC_EUACRH_RNG_NOASSIGN (0)
|
||||
#define MCF_SEC_EUACRH_RNG_CHA0 (0x1000000)
|
||||
#define MCF_SEC_EUACRH_RNG_CHA1 (0x2000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_EUACRL */
|
||||
#define MCF_SEC_EUACRL_AESU(x) (((x)&0xF)<<0x10)
|
||||
#define MCF_SEC_EUACRL_AESU_NOASSIGN (0)
|
||||
#define MCF_SEC_EUACRL_AESU_CHA0 (0x10000)
|
||||
#define MCF_SEC_EUACRL_AESU_CHA1 (0x20000)
|
||||
#define MCF_SEC_EUACRL_DEU(x) (((x)&0xF)<<0x18)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_SIMRH */
|
||||
#define MCF_SEC_SIMRH_AERR (0x8000000)
|
||||
#define MCF_SEC_SIMRH_CHA_0_DN (0x10000000)
|
||||
#define MCF_SEC_SIMRH_CHA_0_ERR (0x20000000)
|
||||
#define MCF_SEC_SIMRH_CHA_1_DN (0x40000000)
|
||||
#define MCF_SEC_SIMRH_CHA_1_ERR (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_SIMRL */
|
||||
#define MCF_SEC_SIMRL_TEA (0x40)
|
||||
#define MCF_SEC_SIMRL_DEU_DN (0x100)
|
||||
#define MCF_SEC_SIMRL_DEU_ERR (0x200)
|
||||
#define MCF_SEC_SIMRL_AESU_DN (0x1000)
|
||||
#define MCF_SEC_SIMRL_AESU_ERR (0x2000)
|
||||
#define MCF_SEC_SIMRL_MDEU_DN (0x10000)
|
||||
#define MCF_SEC_SIMRL_MDEU_ERR (0x20000)
|
||||
#define MCF_SEC_SIMRL_AFEU_DN (0x100000)
|
||||
#define MCF_SEC_SIMRL_AFEU_ERR (0x200000)
|
||||
#define MCF_SEC_SIMRL_RNG_DN (0x1000000)
|
||||
#define MCF_SEC_SIMRL_RNG_ERR (0x2000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_SISRH */
|
||||
#define MCF_SEC_SISRH_AERR (0x8000000)
|
||||
#define MCF_SEC_SISRH_CHA_0_DN (0x10000000)
|
||||
#define MCF_SEC_SISRH_CHA_0_ERR (0x20000000)
|
||||
#define MCF_SEC_SISRH_CHA_1_DN (0x40000000)
|
||||
#define MCF_SEC_SISRH_CHA_1_ERR (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_SISRL */
|
||||
#define MCF_SEC_SISRL_TEA (0x40)
|
||||
#define MCF_SEC_SISRL_DEU_DN (0x100)
|
||||
#define MCF_SEC_SISRL_DEU_ERR (0x200)
|
||||
#define MCF_SEC_SISRL_AESU_DN (0x1000)
|
||||
#define MCF_SEC_SISRL_AESU_ERR (0x2000)
|
||||
#define MCF_SEC_SISRL_MDEU_DN (0x10000)
|
||||
#define MCF_SEC_SISRL_MDEU_ERR (0x20000)
|
||||
#define MCF_SEC_SISRL_AFEU_DN (0x100000)
|
||||
#define MCF_SEC_SISRL_AFEU_ERR (0x200000)
|
||||
#define MCF_SEC_SISRL_RNG_DN (0x1000000)
|
||||
#define MCF_SEC_SISRL_RNG_ERR (0x2000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_SICRH */
|
||||
#define MCF_SEC_SICRH_AERR (0x8000000)
|
||||
#define MCF_SEC_SICRH_CHA_0_DN (0x10000000)
|
||||
#define MCF_SEC_SICRH_CHA_0_ERR (0x20000000)
|
||||
#define MCF_SEC_SICRH_CHA_1_DN (0x40000000)
|
||||
#define MCF_SEC_SICRH_CHA_1_ERR (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_SICRL */
|
||||
#define MCF_SEC_SICRL_TEA (0x40)
|
||||
#define MCF_SEC_SICRL_DEU_DN (0x100)
|
||||
#define MCF_SEC_SICRL_DEU_ERR (0x200)
|
||||
#define MCF_SEC_SICRL_AESU_DN (0x1000)
|
||||
#define MCF_SEC_SICRL_AESU_ERR (0x2000)
|
||||
#define MCF_SEC_SICRL_MDEU_DN (0x10000)
|
||||
#define MCF_SEC_SICRL_MDEU_ERR (0x20000)
|
||||
#define MCF_SEC_SICRL_AFEU_DN (0x100000)
|
||||
#define MCF_SEC_SICRL_AFEU_ERR (0x200000)
|
||||
#define MCF_SEC_SICRL_RNG_DN (0x1000000)
|
||||
#define MCF_SEC_SICRL_RNG_ERR (0x2000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_SIDR */
|
||||
#define MCF_SEC_SIDR_VERSION(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_EUASRH */
|
||||
#define MCF_SEC_EUASRH_AFEU(x) (((x)&0xF)<<0)
|
||||
#define MCF_SEC_EUASRH_MDEU(x) (((x)&0xF)<<0x8)
|
||||
#define MCF_SEC_EUASRH_RNG(x) (((x)&0xF)<<0x18)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_EUASRL */
|
||||
#define MCF_SEC_EUASRL_AESU(x) (((x)&0xF)<<0x10)
|
||||
#define MCF_SEC_EUASRL_DEU(x) (((x)&0xF)<<0x18)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_SMCR */
|
||||
#define MCF_SEC_SMCR_CURR_CHAN(x) (((x)&0xF)<<0x4)
|
||||
#define MCF_SEC_SMCR_CURR_CHAN_1 (0x10)
|
||||
#define MCF_SEC_SMCR_CURR_CHAN_2 (0x20)
|
||||
#define MCF_SEC_SMCR_SWR (0x1000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_MEAR */
|
||||
#define MCF_SEC_MEAR_ADDRESS(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_CCCRn */
|
||||
#define MCF_SEC_CCCRn_RST (0x1)
|
||||
#define MCF_SEC_CCCRn_CDIE (0x2)
|
||||
#define MCF_SEC_CCCRn_NT (0x4)
|
||||
#define MCF_SEC_CCCRn_NE (0x8)
|
||||
#define MCF_SEC_CCCRn_WE (0x10)
|
||||
#define MCF_SEC_CCCRn_BURST_SIZE(x) (((x)&0x7)<<0x8)
|
||||
#define MCF_SEC_CCCRn_BURST_SIZE_2 (0)
|
||||
#define MCF_SEC_CCCRn_BURST_SIZE_8 (0x100)
|
||||
#define MCF_SEC_CCCRn_BURST_SIZE_16 (0x200)
|
||||
#define MCF_SEC_CCCRn_BURST_SIZE_24 (0x300)
|
||||
#define MCF_SEC_CCCRn_BURST_SIZE_32 (0x400)
|
||||
#define MCF_SEC_CCCRn_BURST_SIZE_40 (0x500)
|
||||
#define MCF_SEC_CCCRn_BURST_SIZE_48 (0x600)
|
||||
#define MCF_SEC_CCCRn_BURST_SIZE_56 (0x700)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_CCPSRHn */
|
||||
#define MCF_SEC_CCPSRHn_STATE(x) (((x)&0xFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_CCPSRLn */
|
||||
#define MCF_SEC_CCPSRLn_PAIR_PTR(x) (((x)&0xFF)<<0)
|
||||
#define MCF_SEC_CCPSRLn_EUERR (0x100)
|
||||
#define MCF_SEC_CCPSRLn_SERR (0x200)
|
||||
#define MCF_SEC_CCPSRLn_DERR (0x400)
|
||||
#define MCF_SEC_CCPSRLn_PERR (0x1000)
|
||||
#define MCF_SEC_CCPSRLn_TEA (0x2000)
|
||||
#define MCF_SEC_CCPSRLn_SD (0x10000)
|
||||
#define MCF_SEC_CCPSRLn_PD (0x20000)
|
||||
#define MCF_SEC_CCPSRLn_SRD (0x40000)
|
||||
#define MCF_SEC_CCPSRLn_PRD (0x80000)
|
||||
#define MCF_SEC_CCPSRLn_SG (0x100000)
|
||||
#define MCF_SEC_CCPSRLn_PG (0x200000)
|
||||
#define MCF_SEC_CCPSRLn_SR (0x400000)
|
||||
#define MCF_SEC_CCPSRLn_PR (0x800000)
|
||||
#define MCF_SEC_CCPSRLn_MO (0x1000000)
|
||||
#define MCF_SEC_CCPSRLn_MI (0x2000000)
|
||||
#define MCF_SEC_CCPSRLn_STAT (0x4000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_CDPRn */
|
||||
#define MCF_SEC_CDPRn_CDP(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_FRn */
|
||||
#define MCF_SEC_FRn_FETCH_ADDR(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_AFRCR */
|
||||
#define MCF_SEC_AFRCR_SR (0x1000000)
|
||||
#define MCF_SEC_AFRCR_MI (0x2000000)
|
||||
#define MCF_SEC_AFRCR_RI (0x4000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_AFSR */
|
||||
#define MCF_SEC_AFSR_RD (0x1000000)
|
||||
#define MCF_SEC_AFSR_ID (0x2000000)
|
||||
#define MCF_SEC_AFSR_IE (0x4000000)
|
||||
#define MCF_SEC_AFSR_OFR (0x8000000)
|
||||
#define MCF_SEC_AFSR_IFW (0x10000000)
|
||||
#define MCF_SEC_AFSR_HALT (0x20000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_AFISR */
|
||||
#define MCF_SEC_AFISR_DSE (0x10000)
|
||||
#define MCF_SEC_AFISR_KSE (0x20000)
|
||||
#define MCF_SEC_AFISR_CE (0x40000)
|
||||
#define MCF_SEC_AFISR_ERE (0x80000)
|
||||
#define MCF_SEC_AFISR_IE (0x100000)
|
||||
#define MCF_SEC_AFISR_OFU (0x2000000)
|
||||
#define MCF_SEC_AFISR_IFO (0x4000000)
|
||||
#define MCF_SEC_AFISR_IFE (0x10000000)
|
||||
#define MCF_SEC_AFISR_OFE (0x20000000)
|
||||
#define MCF_SEC_AFISR_AE (0x40000000)
|
||||
#define MCF_SEC_AFISR_ME (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_AFIMR */
|
||||
#define MCF_SEC_AFIMR_DSE (0x10000)
|
||||
#define MCF_SEC_AFIMR_KSE (0x20000)
|
||||
#define MCF_SEC_AFIMR_CE (0x40000)
|
||||
#define MCF_SEC_AFIMR_ERE (0x80000)
|
||||
#define MCF_SEC_AFIMR_IE (0x100000)
|
||||
#define MCF_SEC_AFIMR_OFU (0x2000000)
|
||||
#define MCF_SEC_AFIMR_IFO (0x4000000)
|
||||
#define MCF_SEC_AFIMR_IFE (0x10000000)
|
||||
#define MCF_SEC_AFIMR_OFE (0x20000000)
|
||||
#define MCF_SEC_AFIMR_AE (0x40000000)
|
||||
#define MCF_SEC_AFIMR_ME (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_DRCR */
|
||||
#define MCF_SEC_DRCR_SR (0x1000000)
|
||||
#define MCF_SEC_DRCR_MI (0x2000000)
|
||||
#define MCF_SEC_DRCR_RI (0x4000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_DSR */
|
||||
#define MCF_SEC_DSR_RD (0x1000000)
|
||||
#define MCF_SEC_DSR_ID (0x2000000)
|
||||
#define MCF_SEC_DSR_IE (0x4000000)
|
||||
#define MCF_SEC_DSR_OFR (0x8000000)
|
||||
#define MCF_SEC_DSR_IFW (0x10000000)
|
||||
#define MCF_SEC_DSR_HALT (0x20000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_DISR */
|
||||
#define MCF_SEC_DISR_DSE (0x10000)
|
||||
#define MCF_SEC_DISR_KSE (0x20000)
|
||||
#define MCF_SEC_DISR_CE (0x40000)
|
||||
#define MCF_SEC_DISR_ERE (0x80000)
|
||||
#define MCF_SEC_DISR_IE (0x100000)
|
||||
#define MCF_SEC_DISR_KPE (0x200000)
|
||||
#define MCF_SEC_DISR_OFU (0x2000000)
|
||||
#define MCF_SEC_DISR_IFO (0x4000000)
|
||||
#define MCF_SEC_DISR_IFE (0x10000000)
|
||||
#define MCF_SEC_DISR_OFE (0x20000000)
|
||||
#define MCF_SEC_DISR_AE (0x40000000)
|
||||
#define MCF_SEC_DISR_ME (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_DIMR */
|
||||
#define MCF_SEC_DIMR_DSE (0x10000)
|
||||
#define MCF_SEC_DIMR_KSE (0x20000)
|
||||
#define MCF_SEC_DIMR_CE (0x40000)
|
||||
#define MCF_SEC_DIMR_ERE (0x80000)
|
||||
#define MCF_SEC_DIMR_IE (0x100000)
|
||||
#define MCF_SEC_DIMR_KPE (0x200000)
|
||||
#define MCF_SEC_DIMR_OFU (0x2000000)
|
||||
#define MCF_SEC_DIMR_IFO (0x4000000)
|
||||
#define MCF_SEC_DIMR_IFE (0x10000000)
|
||||
#define MCF_SEC_DIMR_OFE (0x20000000)
|
||||
#define MCF_SEC_DIMR_AE (0x40000000)
|
||||
#define MCF_SEC_DIMR_ME (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_MDRCR */
|
||||
#define MCF_SEC_MDRCR_SR (0x1000000)
|
||||
#define MCF_SEC_MDRCR_MI (0x2000000)
|
||||
#define MCF_SEC_MDRCR_RI (0x4000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_MDSR */
|
||||
#define MCF_SEC_MDSR_RD (0x1000000)
|
||||
#define MCF_SEC_MDSR_ID (0x2000000)
|
||||
#define MCF_SEC_MDSR_IE (0x4000000)
|
||||
#define MCF_SEC_MDSR_IFW (0x10000000)
|
||||
#define MCF_SEC_MDSR_HALT (0x20000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_MDISR */
|
||||
#define MCF_SEC_MDISR_DSE (0x10000)
|
||||
#define MCF_SEC_MDISR_KSE (0x20000)
|
||||
#define MCF_SEC_MDISR_CE (0x40000)
|
||||
#define MCF_SEC_MDISR_ERE (0x80000)
|
||||
#define MCF_SEC_MDISR_IE (0x100000)
|
||||
#define MCF_SEC_MDISR_IFO (0x4000000)
|
||||
#define MCF_SEC_MDISR_AE (0x40000000)
|
||||
#define MCF_SEC_MDISR_ME (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_MDIMR */
|
||||
#define MCF_SEC_MDIMR_DSE (0x10000)
|
||||
#define MCF_SEC_MDIMR_KSE (0x20000)
|
||||
#define MCF_SEC_MDIMR_CE (0x40000)
|
||||
#define MCF_SEC_MDIMR_ERE (0x80000)
|
||||
#define MCF_SEC_MDIMR_IE (0x100000)
|
||||
#define MCF_SEC_MDIMR_IFO (0x4000000)
|
||||
#define MCF_SEC_MDIMR_AE (0x40000000)
|
||||
#define MCF_SEC_MDIMR_ME (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_RNGRCR */
|
||||
#define MCF_SEC_RNGRCR_SR (0x1000000)
|
||||
#define MCF_SEC_RNGRCR_MI (0x2000000)
|
||||
#define MCF_SEC_RNGRCR_RI (0x4000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_RNGSR */
|
||||
#define MCF_SEC_RNGSR_RD (0x1000000)
|
||||
#define MCF_SEC_RNGSR_IE (0x4000000)
|
||||
#define MCF_SEC_RNGSR_OFR (0x8000000)
|
||||
#define MCF_SEC_RNGSR_HALT (0x20000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_RNGISR */
|
||||
#define MCF_SEC_RNGISR_IE (0x100000)
|
||||
#define MCF_SEC_RNGISR_OFU (0x2000000)
|
||||
#define MCF_SEC_RNGISR_AE (0x40000000)
|
||||
#define MCF_SEC_RNGISR_ME (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_RNGIMR */
|
||||
#define MCF_SEC_RNGIMR_IE (0x100000)
|
||||
#define MCF_SEC_RNGIMR_OFU (0x2000000)
|
||||
#define MCF_SEC_RNGIMR_AE (0x40000000)
|
||||
#define MCF_SEC_RNGIMR_ME (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_AESRCR */
|
||||
#define MCF_SEC_AESRCR_SR (0x1000000)
|
||||
#define MCF_SEC_AESRCR_MI (0x2000000)
|
||||
#define MCF_SEC_AESRCR_RI (0x4000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_AESSR */
|
||||
#define MCF_SEC_AESSR_RD (0x1000000)
|
||||
#define MCF_SEC_AESSR_ID (0x2000000)
|
||||
#define MCF_SEC_AESSR_IE (0x4000000)
|
||||
#define MCF_SEC_AESSR_OFR (0x8000000)
|
||||
#define MCF_SEC_AESSR_IFW (0x10000000)
|
||||
#define MCF_SEC_AESSR_HALT (0x20000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_AESISR */
|
||||
#define MCF_SEC_AESISR_DSE (0x10000)
|
||||
#define MCF_SEC_AESISR_KSE (0x20000)
|
||||
#define MCF_SEC_AESISR_CE (0x40000)
|
||||
#define MCF_SEC_AESISR_ERE (0x80000)
|
||||
#define MCF_SEC_AESISR_IE (0x100000)
|
||||
#define MCF_SEC_AESISR_OFU (0x2000000)
|
||||
#define MCF_SEC_AESISR_IFO (0x4000000)
|
||||
#define MCF_SEC_AESISR_IFE (0x10000000)
|
||||
#define MCF_SEC_AESISR_OFE (0x20000000)
|
||||
#define MCF_SEC_AESISR_AE (0x40000000)
|
||||
#define MCF_SEC_AESISR_ME (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_AESIMR */
|
||||
#define MCF_SEC_AESIMR_DSE (0x10000)
|
||||
#define MCF_SEC_AESIMR_KSE (0x20000)
|
||||
#define MCF_SEC_AESIMR_CE (0x40000)
|
||||
#define MCF_SEC_AESIMR_ERE (0x80000)
|
||||
#define MCF_SEC_AESIMR_IE (0x100000)
|
||||
#define MCF_SEC_AESIMR_OFU (0x2000000)
|
||||
#define MCF_SEC_AESIMR_IFO (0x4000000)
|
||||
#define MCF_SEC_AESIMR_IFE (0x10000000)
|
||||
#define MCF_SEC_AESIMR_OFE (0x20000000)
|
||||
#define MCF_SEC_AESIMR_AE (0x40000000)
|
||||
#define MCF_SEC_AESIMR_ME (0x80000000)
|
||||
|
||||
|
||||
#endif /* __MCF5475_SEC_H__ */
|
||||
67
include/MCF5475_SIU.h
Normal file
67
include/MCF5475_SIU.h
Normal file
@@ -0,0 +1,67 @@
|
||||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.81
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF5475_SIU_H__
|
||||
#define __MCF5475_SIU_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* System Integration Unit (SIU)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_SIU_SBCR (*(volatile uint32_t*)(&_MBAR[0x10]))
|
||||
#define MCF_SIU_SECSACR (*(volatile uint32_t*)(&_MBAR[0x38]))
|
||||
#define MCF_SIU_RSR (*(volatile uint32_t*)(&_MBAR[0x44]))
|
||||
#define MCF_SIU_JTAGID (*(volatile uint32_t*)(&_MBAR[0x50]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_SIU_SBCR */
|
||||
#define MCF_SIU_SBCR_PIN2DSPI (0x8000000)
|
||||
#define MCF_SIU_SBCR_DMA2CPU (0x10000000)
|
||||
#define MCF_SIU_SBCR_CPU2DMA (0x20000000)
|
||||
#define MCF_SIU_SBCR_PIN2DMA (0x40000000)
|
||||
#define MCF_SIU_SBCR_PIN2CPU (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SIU_SECSACR */
|
||||
#define MCF_SIU_SECSACR_SEQEN (0x1)
|
||||
|
||||
/* Bit definitions and macros for MCF_SIU_RSR */
|
||||
#define MCF_SIU_RSR_RST (0x1)
|
||||
#define MCF_SIU_RSR_RSTWD (0x2)
|
||||
#define MCF_SIU_RSR_RSTJTG (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_SIU_JTAGID */
|
||||
#define MCF_SIU_JTAGID_JTAGID(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_SIU_JTAGID */
|
||||
#define MCF_SIU_JTAGID_REV (0xF0000000)
|
||||
#define MCF_SIU_JTAGID_PROCESSOR (0x0FFFFFFF)
|
||||
#define MCF_SIU_JTAGID_MCF5485 (0x0800C01D)
|
||||
#define MCF_SIU_JTAGID_MCF5484 (0x0800D01D)
|
||||
#define MCF_SIU_JTAGID_MCF5483 (0x0800E01D)
|
||||
#define MCF_SIU_JTAGID_MCF5482 (0x0800F01D)
|
||||
#define MCF_SIU_JTAGID_MCF5481 (0x0801001D)
|
||||
#define MCF_SIU_JTAGID_MCF5480 (0x0801101D)
|
||||
#define MCF_SIU_JTAGID_MCF5475 (0x0801201D)
|
||||
#define MCF_SIU_JTAGID_MCF5474 (0x0801301D)
|
||||
#define MCF_SIU_JTAGID_MCF5473 (0x0801401D)
|
||||
#define MCF_SIU_JTAGID_MCF5472 (0x0801501D)
|
||||
#define MCF_SIU_JTAGID_MCF5471 (0x0801601D)
|
||||
#define MCF_SIU_JTAGID_MCF5470 (0x0801701D)
|
||||
|
||||
#endif /* __MCF5475_SIU_H__ */
|
||||
59
include/MCF5475_SLT.h
Normal file
59
include/MCF5475_SLT.h
Normal file
@@ -0,0 +1,59 @@
|
||||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.81
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF5475_SLT_H__
|
||||
#define __MCF5475_SLT_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Slice Timers (SLT)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_SLT0_STCNT (*(volatile uint32_t*)(&_MBAR[0x900]))
|
||||
#define MCF_SLT0_SCR (*(volatile uint32_t*)(&_MBAR[0x904]))
|
||||
#define MCF_SLT0_SCNT (*(volatile uint32_t*)(&_MBAR[0x908]))
|
||||
#define MCF_SLT0_SSR (*(volatile uint32_t*)(&_MBAR[0x90C]))
|
||||
|
||||
#define MCF_SLT1_STCNT (*(volatile uint32_t*)(&_MBAR[0x910]))
|
||||
#define MCF_SLT1_SCR (*(volatile uint32_t*)(&_MBAR[0x914]))
|
||||
#define MCF_SLT1_SCNT (*(volatile uint32_t*)(&_MBAR[0x918]))
|
||||
#define MCF_SLT1_SSR (*(volatile uint32_t*)(&_MBAR[0x91C]))
|
||||
|
||||
#define MCF_SLT_STCNT(x) (*(volatile uint32_t*)(&_MBAR[0x900 + ((x)*0x10)]))
|
||||
#define MCF_SLT_SCR(x) (*(volatile uint32_t*)(&_MBAR[0x904 + ((x)*0x10)]))
|
||||
#define MCF_SLT_SCNT(x) (*(volatile int32_t*)(&_MBAR[0x908 + ((x)*0x10)]))
|
||||
#define MCF_SLT_SSR(x) (*(volatile uint32_t*)(&_MBAR[0x90C + ((x)*0x10)]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_SLT_STCNT */
|
||||
#define MCF_SLT_STCNT_TC(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_SLT_SCR */
|
||||
#define MCF_SLT_SCR_TEN (0x1000000)
|
||||
#define MCF_SLT_SCR_IEN (0x2000000)
|
||||
#define MCF_SLT_SCR_RUN (0x4000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SLT_SCNT */
|
||||
#define MCF_SLT_SCNT_CNT(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_SLT_SSR */
|
||||
#define MCF_SLT_SSR_ST (0x1000000)
|
||||
#define MCF_SLT_SSR_BE (0x2000000)
|
||||
|
||||
|
||||
#endif /* __MCF5475_SLT_H__ */
|
||||
62
include/MCF5475_SRAM.h
Normal file
62
include/MCF5475_SRAM.h
Normal file
@@ -0,0 +1,62 @@
|
||||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.81
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF5475_SRAM_H__
|
||||
#define __MCF5475_SRAM_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* System SRAM Module (SRAM)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_SRAM_SSCR (*(volatile uint32_t*)(&__MBAR[0x1FFC0]))
|
||||
#define MCF_SRAM_TCCR (*(volatile uint32_t*)(&__MBAR[0x1FFC4]))
|
||||
#define MCF_SRAM_TCCRDR (*(volatile uint32_t*)(&__MBAR[0x1FFC8]))
|
||||
#define MCF_SRAM_TCCRDW (*(volatile uint32_t*)(&__MBAR[0x1FFCC]))
|
||||
#define MCF_SRAM_TCCRSEC (*(volatile uint32_t*)(&__MBAR[0x1FFD0]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_SRAM_SSCR */
|
||||
#define MCF_SRAM_SSCR_INLV (0x10000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SRAM_TCCR */
|
||||
#define MCF_SRAM_TCCR_BANK0_TC(x) (((x)&0xF)<<0)
|
||||
#define MCF_SRAM_TCCR_BANK1_TC(x) (((x)&0xF)<<0x8)
|
||||
#define MCF_SRAM_TCCR_BANK2_TC(x) (((x)&0xF)<<0x10)
|
||||
#define MCF_SRAM_TCCR_BANK3_TC(x) (((x)&0xF)<<0x18)
|
||||
|
||||
/* Bit definitions and macros for MCF_SRAM_TCCRDR */
|
||||
#define MCF_SRAM_TCCRDR_BANK0_TC(x) (((x)&0xF)<<0)
|
||||
#define MCF_SRAM_TCCRDR_BANK1_TC(x) (((x)&0xF)<<0x8)
|
||||
#define MCF_SRAM_TCCRDR_BANK2_TC(x) (((x)&0xF)<<0x10)
|
||||
#define MCF_SRAM_TCCRDR_BANK3_TC(x) (((x)&0xF)<<0x18)
|
||||
|
||||
/* Bit definitions and macros for MCF_SRAM_TCCRDW */
|
||||
#define MCF_SRAM_TCCRDW_BANK0_TC(x) (((x)&0xF)<<0)
|
||||
#define MCF_SRAM_TCCRDW_BANK1_TC(x) (((x)&0xF)<<0x8)
|
||||
#define MCF_SRAM_TCCRDW_BANK2_TC(x) (((x)&0xF)<<0x10)
|
||||
#define MCF_SRAM_TCCRDW_BANK3_TC(x) (((x)&0xF)<<0x18)
|
||||
|
||||
/* Bit definitions and macros for MCF_SRAM_TCCRSEC */
|
||||
#define MCF_SRAM_TCCRSEC_BANK0_TC(x) (((x)&0xF)<<0)
|
||||
#define MCF_SRAM_TCCRSEC_BANK1_TC(x) (((x)&0xF)<<0x8)
|
||||
#define MCF_SRAM_TCCRSEC_BANK2_TC(x) (((x)&0xF)<<0x10)
|
||||
#define MCF_SRAM_TCCRSEC_BANK3_TC(x) (((x)&0xF)<<0x18)
|
||||
|
||||
|
||||
#endif /* __MCF5475_SRAM_H__ */
|
||||
554
include/MCF5475_USB.h
Normal file
554
include/MCF5475_USB.h
Normal file
@@ -0,0 +1,554 @@
|
||||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.81
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF5475_USB_H__
|
||||
#define __MCF5475_USB_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Universal Serial Bus Interface (USB)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_USB_USBAISR (*(volatile uint8_t *)(&__MBAR[0xB000]))
|
||||
#define MCF_USB_USBAIMR (*(volatile uint8_t *)(&__MBAR[0xB001]))
|
||||
#define MCF_USB_EPINFO (*(volatile uint8_t *)(&__MBAR[0xB003]))
|
||||
#define MCF_USB_CFGR (*(volatile uint8_t *)(&__MBAR[0xB004]))
|
||||
#define MCF_USB_CFGAR (*(volatile uint8_t *)(&__MBAR[0xB005]))
|
||||
#define MCF_USB_SPEEDR (*(volatile uint8_t *)(&__MBAR[0xB006]))
|
||||
#define MCF_USB_FRMNUMR (*(volatile uint16_t*)(&__MBAR[0xB00E]))
|
||||
#define MCF_USB_EPTNR (*(volatile uint16_t*)(&__MBAR[0xB010]))
|
||||
#define MCF_USB_IFUR (*(volatile uint16_t*)(&__MBAR[0xB014]))
|
||||
#define MCF_USB_IFR0 (*(volatile uint16_t*)(&__MBAR[0xB040]))
|
||||
#define MCF_USB_IFR1 (*(volatile uint16_t*)(&__MBAR[0xB042]))
|
||||
#define MCF_USB_IFR2 (*(volatile uint16_t*)(&__MBAR[0xB044]))
|
||||
#define MCF_USB_IFR3 (*(volatile uint16_t*)(&__MBAR[0xB046]))
|
||||
#define MCF_USB_IFR4 (*(volatile uint16_t*)(&__MBAR[0xB048]))
|
||||
#define MCF_USB_IFR5 (*(volatile uint16_t*)(&__MBAR[0xB04A]))
|
||||
#define MCF_USB_IFR6 (*(volatile uint16_t*)(&__MBAR[0xB04C]))
|
||||
#define MCF_USB_IFR7 (*(volatile uint16_t*)(&__MBAR[0xB04E]))
|
||||
#define MCF_USB_IFR8 (*(volatile uint16_t*)(&__MBAR[0xB050]))
|
||||
#define MCF_USB_IFR9 (*(volatile uint16_t*)(&__MBAR[0xB052]))
|
||||
#define MCF_USB_IFR10 (*(volatile uint16_t*)(&__MBAR[0xB054]))
|
||||
#define MCF_USB_IFR11 (*(volatile uint16_t*)(&__MBAR[0xB056]))
|
||||
#define MCF_USB_IFR12 (*(volatile uint16_t*)(&__MBAR[0xB058]))
|
||||
#define MCF_USB_IFR13 (*(volatile uint16_t*)(&__MBAR[0xB05A]))
|
||||
#define MCF_USB_IFR14 (*(volatile uint16_t*)(&__MBAR[0xB05C]))
|
||||
#define MCF_USB_IFR15 (*(volatile uint16_t*)(&__MBAR[0xB05E]))
|
||||
#define MCF_USB_IFR16 (*(volatile uint16_t*)(&__MBAR[0xB060]))
|
||||
#define MCF_USB_IFR17 (*(volatile uint16_t*)(&__MBAR[0xB062]))
|
||||
#define MCF_USB_IFR18 (*(volatile uint16_t*)(&__MBAR[0xB064]))
|
||||
#define MCF_USB_IFR19 (*(volatile uint16_t*)(&__MBAR[0xB066]))
|
||||
#define MCF_USB_IFR20 (*(volatile uint16_t*)(&__MBAR[0xB068]))
|
||||
#define MCF_USB_IFR21 (*(volatile uint16_t*)(&__MBAR[0xB06A]))
|
||||
#define MCF_USB_IFR22 (*(volatile uint16_t*)(&__MBAR[0xB06C]))
|
||||
#define MCF_USB_IFR23 (*(volatile uint16_t*)(&__MBAR[0xB06E]))
|
||||
#define MCF_USB_IFR24 (*(volatile uint16_t*)(&__MBAR[0xB070]))
|
||||
#define MCF_USB_IFR25 (*(volatile uint16_t*)(&__MBAR[0xB072]))
|
||||
#define MCF_USB_IFR26 (*(volatile uint16_t*)(&__MBAR[0xB074]))
|
||||
#define MCF_USB_IFR27 (*(volatile uint16_t*)(&__MBAR[0xB076]))
|
||||
#define MCF_USB_IFR28 (*(volatile uint16_t*)(&__MBAR[0xB078]))
|
||||
#define MCF_USB_IFR29 (*(volatile uint16_t*)(&__MBAR[0xB07A]))
|
||||
#define MCF_USB_IFR30 (*(volatile uint16_t*)(&__MBAR[0xB07C]))
|
||||
#define MCF_USB_IFR31 (*(volatile uint16_t*)(&__MBAR[0xB07E]))
|
||||
#define MCF_USB_PPCNT (*(volatile uint16_t*)(&__MBAR[0xB080]))
|
||||
#define MCF_USB_DPCNT (*(volatile uint16_t*)(&__MBAR[0xB082]))
|
||||
#define MCF_USB_CRCECNT (*(volatile uint16_t*)(&__MBAR[0xB084]))
|
||||
#define MCF_USB_BSECNT (*(volatile uint16_t*)(&__MBAR[0xB086]))
|
||||
#define MCF_USB_PIDECNT (*(volatile uint16_t*)(&__MBAR[0xB088]))
|
||||
#define MCF_USB_FRMECNT (*(volatile uint16_t*)(&__MBAR[0xB08A]))
|
||||
#define MCF_USB_TXPCNT (*(volatile uint16_t*)(&__MBAR[0xB08C]))
|
||||
#define MCF_USB_CNTOVR (*(volatile uint8_t *)(&__MBAR[0xB08E]))
|
||||
#define MCF_USB_EP0ACR (*(volatile uint8_t *)(&__MBAR[0xB101]))
|
||||
#define MCF_USB_EP0MPSR (*(volatile uint16_t*)(&__MBAR[0xB102]))
|
||||
#define MCF_USB_EP0IFR (*(volatile uint8_t *)(&__MBAR[0xB104]))
|
||||
#define MCF_USB_EP0SR (*(volatile uint8_t *)(&__MBAR[0xB105]))
|
||||
#define MCF_USB_BMRTR (*(volatile uint8_t *)(&__MBAR[0xB106]))
|
||||
#define MCF_USB_BRTR (*(volatile uint8_t *)(&__MBAR[0xB107]))
|
||||
#define MCF_USB_WVALUER (*(volatile uint16_t*)(&__MBAR[0xB108]))
|
||||
#define MCF_USB_WINDEXR (*(volatile uint16_t*)(&__MBAR[0xB10A]))
|
||||
#define MCF_USB_WLENGTHR (*(volatile uint16_t*)(&__MBAR[0xB10C]))
|
||||
#define MCF_USB_EP1OUTACR (*(volatile uint8_t *)(&__MBAR[0xB131]))
|
||||
#define MCF_USB_EP1OUTMPSR (*(volatile uint16_t*)(&__MBAR[0xB132]))
|
||||
#define MCF_USB_EP1OUTIFR (*(volatile uint8_t *)(&__MBAR[0xB134]))
|
||||
#define MCF_USB_EP1OUTSR (*(volatile uint8_t *)(&__MBAR[0xB135]))
|
||||
#define MCF_USB_EP1OUTSFR (*(volatile uint16_t*)(&__MBAR[0xB13E]))
|
||||
#define MCF_USB_EP1INACR (*(volatile uint8_t *)(&__MBAR[0xB149]))
|
||||
#define MCF_USB_EP1INMPSR (*(volatile uint16_t*)(&__MBAR[0xB14A]))
|
||||
#define MCF_USB_EP1INIFR (*(volatile uint8_t *)(&__MBAR[0xB14C]))
|
||||
#define MCF_USB_EP1INSR (*(volatile uint8_t *)(&__MBAR[0xB14D]))
|
||||
#define MCF_USB_EP1INSFR (*(volatile uint16_t*)(&__MBAR[0xB156]))
|
||||
#define MCF_USB_EP2OUTACR (*(volatile uint8_t *)(&__MBAR[0xB161]))
|
||||
#define MCF_USB_EP2OUTMPSR (*(volatile uint16_t*)(&__MBAR[0xB162]))
|
||||
#define MCF_USB_EP2OUTIFR (*(volatile uint8_t *)(&__MBAR[0xB164]))
|
||||
#define MCF_USB_EP2OUTSR (*(volatile uint8_t *)(&__MBAR[0xB165]))
|
||||
#define MCF_USB_EP2OUTSFR (*(volatile uint16_t*)(&__MBAR[0xB16E]))
|
||||
#define MCF_USB_EP2INACR (*(volatile uint8_t *)(&__MBAR[0xB179]))
|
||||
#define MCF_USB_EP2INMPSR (*(volatile uint16_t*)(&__MBAR[0xB17A]))
|
||||
#define MCF_USB_EP2INIFR (*(volatile uint8_t *)(&__MBAR[0xB17C]))
|
||||
#define MCF_USB_EP2INSR (*(volatile uint8_t *)(&__MBAR[0xB17D]))
|
||||
#define MCF_USB_EP2INSFR (*(volatile uint16_t*)(&__MBAR[0xB186]))
|
||||
#define MCF_USB_EP3OUTACR (*(volatile uint8_t *)(&__MBAR[0xB191]))
|
||||
#define MCF_USB_EP3OUTMPSR (*(volatile uint16_t*)(&__MBAR[0xB192]))
|
||||
#define MCF_USB_EP3OUTIFR (*(volatile uint8_t *)(&__MBAR[0xB194]))
|
||||
#define MCF_USB_EP3OUTSR (*(volatile uint8_t *)(&__MBAR[0xB195]))
|
||||
#define MCF_USB_EP3OUTSFR (*(volatile uint16_t*)(&__MBAR[0xB19E]))
|
||||
#define MCF_USB_EP3INACR (*(volatile uint8_t *)(&__MBAR[0xB1A9]))
|
||||
#define MCF_USB_EP3INMPSR (*(volatile uint16_t*)(&__MBAR[0xB1AA]))
|
||||
#define MCF_USB_EP3INIFR (*(volatile uint8_t *)(&__MBAR[0xB1AC]))
|
||||
#define MCF_USB_EP3INSR (*(volatile uint8_t *)(&__MBAR[0xB1AD]))
|
||||
#define MCF_USB_EP3INSFR (*(volatile uint16_t*)(&__MBAR[0xB1B6]))
|
||||
#define MCF_USB_EP4OUTACR (*(volatile uint8_t *)(&__MBAR[0xB1C1]))
|
||||
#define MCF_USB_EP4OUTMPSR (*(volatile uint16_t*)(&__MBAR[0xB1C2]))
|
||||
#define MCF_USB_EP4OUTIFR (*(volatile uint8_t *)(&__MBAR[0xB1C4]))
|
||||
#define MCF_USB_EP4OUTSR (*(volatile uint8_t *)(&__MBAR[0xB1C5]))
|
||||
#define MCF_USB_EP4OUTSFR (*(volatile uint16_t*)(&__MBAR[0xB1CE]))
|
||||
#define MCF_USB_EP4INACR (*(volatile uint8_t *)(&__MBAR[0xB1D9]))
|
||||
#define MCF_USB_EP4INMPSR (*(volatile uint16_t*)(&__MBAR[0xB1DA]))
|
||||
#define MCF_USB_EP4INIFR (*(volatile uint8_t *)(&__MBAR[0xB1DC]))
|
||||
#define MCF_USB_EP4INSR (*(volatile uint8_t *)(&__MBAR[0xB1DD]))
|
||||
#define MCF_USB_EP4INSFR (*(volatile uint16_t*)(&__MBAR[0xB1E6]))
|
||||
#define MCF_USB_EP5OUTACR (*(volatile uint8_t *)(&__MBAR[0xB1F1]))
|
||||
#define MCF_USB_EP5OUTMPSR (*(volatile uint16_t*)(&__MBAR[0xB1F2]))
|
||||
#define MCF_USB_EP5OUTIFR (*(volatile uint8_t *)(&__MBAR[0xB1F4]))
|
||||
#define MCF_USB_EP5OUTSR (*(volatile uint8_t *)(&__MBAR[0xB1F5]))
|
||||
#define MCF_USB_EP5OUTSFR (*(volatile uint16_t*)(&__MBAR[0xB1FE]))
|
||||
#define MCF_USB_EP5INACR (*(volatile uint8_t *)(&__MBAR[0xB209]))
|
||||
#define MCF_USB_EP5INMPSR (*(volatile uint16_t*)(&__MBAR[0xB20A]))
|
||||
#define MCF_USB_EP5INIFR (*(volatile uint8_t *)(&__MBAR[0xB20C]))
|
||||
#define MCF_USB_EP5INSR (*(volatile uint8_t *)(&__MBAR[0xB20D]))
|
||||
#define MCF_USB_EP5INSFR (*(volatile uint16_t*)(&__MBAR[0xB216]))
|
||||
#define MCF_USB_EP6OUTACR (*(volatile uint8_t *)(&__MBAR[0xB221]))
|
||||
#define MCF_USB_EP6OUTMPSR (*(volatile uint16_t*)(&__MBAR[0xB222]))
|
||||
#define MCF_USB_EP6OUTIFR (*(volatile uint8_t *)(&__MBAR[0xB224]))
|
||||
#define MCF_USB_EP6OUTSR (*(volatile uint8_t *)(&__MBAR[0xB225]))
|
||||
#define MCF_USB_EP6OUTSFR (*(volatile uint16_t*)(&__MBAR[0xB22E]))
|
||||
#define MCF_USB_EP6INACR (*(volatile uint8_t *)(&__MBAR[0xB239]))
|
||||
#define MCF_USB_EP6INMPSR (*(volatile uint16_t*)(&__MBAR[0xB23A]))
|
||||
#define MCF_USB_EP6INIFR (*(volatile uint8_t *)(&__MBAR[0xB23C]))
|
||||
#define MCF_USB_EP6INSR (*(volatile uint8_t *)(&__MBAR[0xB23D]))
|
||||
#define MCF_USB_EP6INSFR (*(volatile uint16_t*)(&__MBAR[0xB246]))
|
||||
#define MCF_USB_USBSR (*(volatile uint32_t*)(&__MBAR[0xB400]))
|
||||
#define MCF_USB_USBCR (*(volatile uint32_t*)(&__MBAR[0xB404]))
|
||||
#define MCF_USB_DRAMCR (*(volatile uint32_t*)(&__MBAR[0xB408]))
|
||||
#define MCF_USB_DRAMDR (*(volatile uint32_t*)(&__MBAR[0xB40C]))
|
||||
#define MCF_USB_USBISR (*(volatile uint32_t*)(&__MBAR[0xB410]))
|
||||
#define MCF_USB_USBIMR (*(volatile uint32_t*)(&__MBAR[0xB414]))
|
||||
#define MCF_USB_EP0STAT (*(volatile uint32_t*)(&__MBAR[0xB440]))
|
||||
#define MCF_USB_EP0ISR (*(volatile uint32_t*)(&__MBAR[0xB444]))
|
||||
#define MCF_USB_EP0IMR (*(volatile uint32_t*)(&__MBAR[0xB448]))
|
||||
#define MCF_USB_EP0FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB44C]))
|
||||
#define MCF_USB_EP0FDR (*(volatile uint32_t*)(&__MBAR[0xB450]))
|
||||
#define MCF_USB_EP0FSR (*(volatile uint32_t*)(&__MBAR[0xB454]))
|
||||
#define MCF_USB_EP0FCR (*(volatile uint32_t*)(&__MBAR[0xB458]))
|
||||
#define MCF_USB_EP0FAR (*(volatile uint32_t*)(&__MBAR[0xB45C]))
|
||||
#define MCF_USB_EP0FRP (*(volatile uint32_t*)(&__MBAR[0xB460]))
|
||||
#define MCF_USB_EP0FWP (*(volatile uint32_t*)(&__MBAR[0xB464]))
|
||||
#define MCF_USB_EP0LRFP (*(volatile uint32_t*)(&__MBAR[0xB468]))
|
||||
#define MCF_USB_EP0LWFP (*(volatile uint32_t*)(&__MBAR[0xB46C]))
|
||||
#define MCF_USB_EP1STAT (*(volatile uint32_t*)(&__MBAR[0xB470]))
|
||||
#define MCF_USB_EP1ISR (*(volatile uint32_t*)(&__MBAR[0xB474]))
|
||||
#define MCF_USB_EP1IMR (*(volatile uint32_t*)(&__MBAR[0xB478]))
|
||||
#define MCF_USB_EP1FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB47C]))
|
||||
#define MCF_USB_EP1FDR (*(volatile uint32_t*)(&__MBAR[0xB480]))
|
||||
#define MCF_USB_EP1FSR (*(volatile uint32_t*)(&__MBAR[0xB484]))
|
||||
#define MCF_USB_EP1FCR (*(volatile uint32_t*)(&__MBAR[0xB488]))
|
||||
#define MCF_USB_EP1FAR (*(volatile uint32_t*)(&__MBAR[0xB48C]))
|
||||
#define MCF_USB_EP1FRP (*(volatile uint32_t*)(&__MBAR[0xB490]))
|
||||
#define MCF_USB_EP1FWP (*(volatile uint32_t*)(&__MBAR[0xB494]))
|
||||
#define MCF_USB_EP1LRFP (*(volatile uint32_t*)(&__MBAR[0xB498]))
|
||||
#define MCF_USB_EP1LWFP (*(volatile uint32_t*)(&__MBAR[0xB49C]))
|
||||
#define MCF_USB_EP2STAT (*(volatile uint32_t*)(&__MBAR[0xB4A0]))
|
||||
#define MCF_USB_EP2ISR (*(volatile uint32_t*)(&__MBAR[0xB4A4]))
|
||||
#define MCF_USB_EP2IMR (*(volatile uint32_t*)(&__MBAR[0xB4A8]))
|
||||
#define MCF_USB_EP2FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB4AC]))
|
||||
#define MCF_USB_EP2FDR (*(volatile uint32_t*)(&__MBAR[0xB4B0]))
|
||||
#define MCF_USB_EP2FSR (*(volatile uint32_t*)(&__MBAR[0xB4B4]))
|
||||
#define MCF_USB_EP2FCR (*(volatile uint32_t*)(&__MBAR[0xB4B8]))
|
||||
#define MCF_USB_EP2FAR (*(volatile uint32_t*)(&__MBAR[0xB4BC]))
|
||||
#define MCF_USB_EP2FRP (*(volatile uint32_t*)(&__MBAR[0xB4C0]))
|
||||
#define MCF_USB_EP2FWP (*(volatile uint32_t*)(&__MBAR[0xB4C4]))
|
||||
#define MCF_USB_EP2LRFP (*(volatile uint32_t*)(&__MBAR[0xB4C8]))
|
||||
#define MCF_USB_EP2LWFP (*(volatile uint32_t*)(&__MBAR[0xB4CC]))
|
||||
#define MCF_USB_EP3STAT (*(volatile uint32_t*)(&__MBAR[0xB4D0]))
|
||||
#define MCF_USB_EP3ISR (*(volatile uint32_t*)(&__MBAR[0xB4D4]))
|
||||
#define MCF_USB_EP3IMR (*(volatile uint32_t*)(&__MBAR[0xB4D8]))
|
||||
#define MCF_USB_EP3FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB4DC]))
|
||||
#define MCF_USB_EP3FDR (*(volatile uint32_t*)(&__MBAR[0xB4E0]))
|
||||
#define MCF_USB_EP3FSR (*(volatile uint32_t*)(&__MBAR[0xB4E4]))
|
||||
#define MCF_USB_EP3FCR (*(volatile uint32_t*)(&__MBAR[0xB4E8]))
|
||||
#define MCF_USB_EP3FAR (*(volatile uint32_t*)(&__MBAR[0xB4EC]))
|
||||
#define MCF_USB_EP3FRP (*(volatile uint32_t*)(&__MBAR[0xB4F0]))
|
||||
#define MCF_USB_EP3FWP (*(volatile uint32_t*)(&__MBAR[0xB4F4]))
|
||||
#define MCF_USB_EP3LRFP (*(volatile uint32_t*)(&__MBAR[0xB4F8]))
|
||||
#define MCF_USB_EP3LWFP (*(volatile uint32_t*)(&__MBAR[0xB4FC]))
|
||||
#define MCF_USB_EP4STAT (*(volatile uint32_t*)(&__MBAR[0xB500]))
|
||||
#define MCF_USB_EP4ISR (*(volatile uint32_t*)(&__MBAR[0xB504]))
|
||||
#define MCF_USB_EP4IMR (*(volatile uint32_t*)(&__MBAR[0xB508]))
|
||||
#define MCF_USB_EP4FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB50C]))
|
||||
#define MCF_USB_EP4FDR (*(volatile uint32_t*)(&__MBAR[0xB510]))
|
||||
#define MCF_USB_EP4FSR (*(volatile uint32_t*)(&__MBAR[0xB514]))
|
||||
#define MCF_USB_EP4FCR (*(volatile uint32_t*)(&__MBAR[0xB518]))
|
||||
#define MCF_USB_EP4FAR (*(volatile uint32_t*)(&__MBAR[0xB51C]))
|
||||
#define MCF_USB_EP4FRP (*(volatile uint32_t*)(&__MBAR[0xB520]))
|
||||
#define MCF_USB_EP4FWP (*(volatile uint32_t*)(&__MBAR[0xB524]))
|
||||
#define MCF_USB_EP4LRFP (*(volatile uint32_t*)(&__MBAR[0xB528]))
|
||||
#define MCF_USB_EP4LWFP (*(volatile uint32_t*)(&__MBAR[0xB52C]))
|
||||
#define MCF_USB_EP5STAT (*(volatile uint32_t*)(&__MBAR[0xB530]))
|
||||
#define MCF_USB_EP5ISR (*(volatile uint32_t*)(&__MBAR[0xB534]))
|
||||
#define MCF_USB_EP5IMR (*(volatile uint32_t*)(&__MBAR[0xB538]))
|
||||
#define MCF_USB_EP5FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB53C]))
|
||||
#define MCF_USB_EP5FDR (*(volatile uint32_t*)(&__MBAR[0xB540]))
|
||||
#define MCF_USB_EP5FSR (*(volatile uint32_t*)(&__MBAR[0xB544]))
|
||||
#define MCF_USB_EP5FCR (*(volatile uint32_t*)(&__MBAR[0xB548]))
|
||||
#define MCF_USB_EP5FAR (*(volatile uint32_t*)(&__MBAR[0xB54C]))
|
||||
#define MCF_USB_EP5FRP (*(volatile uint32_t*)(&__MBAR[0xB550]))
|
||||
#define MCF_USB_EP5FWP (*(volatile uint32_t*)(&__MBAR[0xB554]))
|
||||
#define MCF_USB_EP5LRFP (*(volatile uint32_t*)(&__MBAR[0xB558]))
|
||||
#define MCF_USB_EP5LWFP (*(volatile uint32_t*)(&__MBAR[0xB55C]))
|
||||
#define MCF_USB_EP6STAT (*(volatile uint32_t*)(&__MBAR[0xB560]))
|
||||
#define MCF_USB_EP6ISR (*(volatile uint32_t*)(&__MBAR[0xB564]))
|
||||
#define MCF_USB_EP6IMR (*(volatile uint32_t*)(&__MBAR[0xB568]))
|
||||
#define MCF_USB_EP6FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB56C]))
|
||||
#define MCF_USB_EP6FDR (*(volatile uint32_t*)(&__MBAR[0xB570]))
|
||||
#define MCF_USB_EP6FSR (*(volatile uint32_t*)(&__MBAR[0xB574]))
|
||||
#define MCF_USB_EP6FCR (*(volatile uint32_t*)(&__MBAR[0xB578]))
|
||||
#define MCF_USB_EP6FAR (*(volatile uint32_t*)(&__MBAR[0xB57C]))
|
||||
#define MCF_USB_EP6FRP (*(volatile uint32_t*)(&__MBAR[0xB580]))
|
||||
#define MCF_USB_EP6FWP (*(volatile uint32_t*)(&__MBAR[0xB584]))
|
||||
#define MCF_USB_EP6LRFP (*(volatile uint32_t*)(&__MBAR[0xB588]))
|
||||
#define MCF_USB_EP6LWFP (*(volatile uint32_t*)(&__MBAR[0xB58C]))
|
||||
#define MCF_USB_IFR(x) (*(volatile uint16_t*)(&__MBAR[0xB040 + ((x)*0x2)]))
|
||||
#define MCF_USB_EPOUTACR(x) (*(volatile uint8_t *)(&__MBAR[0xB131 + ((x-1)*0x30)]))
|
||||
#define MCF_USB_EPOUTMPSR(x) (*(volatile uint16_t*)(&__MBAR[0xB132 + ((x-1)*0x30)]))
|
||||
#define MCF_USB_EPOUTIFR(x) (*(volatile uint8_t *)(&__MBAR[0xB134 + ((x-1)*0x30)]))
|
||||
#define MCF_USB_EPOUTSR(x) (*(volatile uint8_t *)(&__MBAR[0xB135 + ((x-1)*0x30)]))
|
||||
#define MCF_USB_EPOUTSFR(x) (*(volatile uint16_t*)(&__MBAR[0xB13E + ((x-1)*0x30)]))
|
||||
#define MCF_USB_EPINACR(x) (*(volatile uint8_t *)(&__MBAR[0xB149 + ((x-1)*0x30)]))
|
||||
#define MCF_USB_EPINMPSR(x) (*(volatile uint16_t*)(&__MBAR[0xB14A + ((x-1)*0x30)]))
|
||||
#define MCF_USB_EPINIFR(x) (*(volatile uint8_t *)(&__MBAR[0xB14C + ((x-1)*0x30)]))
|
||||
#define MCF_USB_EPINSR(x) (*(volatile uint8_t *)(&__MBAR[0xB14D + ((x-1)*0x30)]))
|
||||
#define MCF_USB_EPINSFR(x) (*(volatile uint16_t*)(&__MBAR[0xB156 + ((x-1)*0x30)]))
|
||||
#define MCF_USB_EPSTAT(x) (*(volatile uint32_t*)(&__MBAR[0xB440 + ((x)*0x30)]))
|
||||
#define MCF_USB_EPISR(x) (*(volatile uint32_t*)(&__MBAR[0xB444 + ((x)*0x30)]))
|
||||
#define MCF_USB_EPIMR(x) (*(volatile uint32_t*)(&__MBAR[0xB448 + ((x)*0x30)]))
|
||||
#define MCF_USB_EPFRCFGR(x) (*(volatile uint32_t*)(&__MBAR[0xB44C + ((x)*0x30)]))
|
||||
#define MCF_USB_EPFDR(x) (*(volatile uint32_t*)(&__MBAR[0xB450 + ((x)*0x30)]))
|
||||
#define MCF_USB_EPFSR(x) (*(volatile uint32_t*)(&__MBAR[0xB454 + ((x)*0x30)]))
|
||||
#define MCF_USB_EPFCR(x) (*(volatile uint32_t*)(&__MBAR[0xB458 + ((x)*0x30)]))
|
||||
#define MCF_USB_EPFAR(x) (*(volatile uint32_t*)(&__MBAR[0xB45C + ((x)*0x30)]))
|
||||
#define MCF_USB_EPFRP(x) (*(volatile uint32_t*)(&__MBAR[0xB460 + ((x)*0x30)]))
|
||||
#define MCF_USB_EPFWP(x) (*(volatile uint32_t*)(&__MBAR[0xB464 + ((x)*0x30)]))
|
||||
#define MCF_USB_EPLRFP(x) (*(volatile uint32_t*)(&__MBAR[0xB468 + ((x)*0x30)]))
|
||||
#define MCF_USB_EPLWFP(x) (*(volatile uint32_t*)(&__MBAR[0xB46C + ((x)*0x30)]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_USBAISR */
|
||||
#define MCF_USB_USBAISR_SETUP (0x1)
|
||||
#define MCF_USB_USBAISR_IN (0x2)
|
||||
#define MCF_USB_USBAISR_OUT (0x4)
|
||||
#define MCF_USB_USBAISR_EPHALT (0x8)
|
||||
#define MCF_USB_USBAISR_TRANSERR (0x10)
|
||||
#define MCF_USB_USBAISR_ACK (0x20)
|
||||
#define MCF_USB_USBAISR_CTROVFL (0x40)
|
||||
#define MCF_USB_USBAISR_EPSTALL (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_USBAIMR */
|
||||
#define MCF_USB_USBAIMR_SETUPEN (0x1)
|
||||
#define MCF_USB_USBAIMR_INEN (0x2)
|
||||
#define MCF_USB_USBAIMR_OUTEN (0x4)
|
||||
#define MCF_USB_USBAIMR_EPHALTEN (0x8)
|
||||
#define MCF_USB_USBAIMR_TRANSERREN (0x10)
|
||||
#define MCF_USB_USBAIMR_ACKEN (0x20)
|
||||
#define MCF_USB_USBAIMR_CTROVFLEN (0x40)
|
||||
#define MCF_USB_USBAIMR_EPSTALLEN (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_EPINFO */
|
||||
#define MCF_USB_EPINFO_EPDIR (0x1)
|
||||
#define MCF_USB_EPINFO_EPNUM(x) (((x)&0x7)<<0x1)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_CFGR */
|
||||
#define MCF_USB_CFGR_Configuration_Value(x) (((x)&0xFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_CFGAR */
|
||||
#define MCF_USB_CFGAR_RESERVED (0xA0)
|
||||
#define MCF_USB_CFGAR_RMTWKEUP (0xE0)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_SPEEDR */
|
||||
#define MCF_USB_SPEEDR_SPEED(x) (((x)&0x3)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_FRMNUMR */
|
||||
#define MCF_USB_FRMNUMR_FRMNUM(x) (((x)&0xFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_EPTNR */
|
||||
#define MCF_USB_EPTNR_EP1T(x) (((x)&0x3)<<0)
|
||||
#define MCF_USB_EPTNR_EP2T(x) (((x)&0x3)<<0x2)
|
||||
#define MCF_USB_EPTNR_EP3T(x) (((x)&0x3)<<0x4)
|
||||
#define MCF_USB_EPTNR_EP4T(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_USB_EPTNR_EP5T(x) (((x)&0x3)<<0x8)
|
||||
#define MCF_USB_EPTNR_EP6T(x) (((x)&0x3)<<0xA)
|
||||
#define MCF_USB_EPTNR_EPnT1 (0)
|
||||
#define MCF_USB_EPTNR_EPnT2 (0x1)
|
||||
#define MCF_USB_EPTNR_EPnT3 (0x2)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_IFUR */
|
||||
#define MCF_USB_IFUR_ALTSET(x) (((x)&0xFF)<<0)
|
||||
#define MCF_USB_IFUR_IFNUM(x) (((x)&0xFF)<<0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_IFR */
|
||||
#define MCF_USB_IFR_ALTSET(x) (((x)&0xFF)<<0)
|
||||
#define MCF_USB_IFR_IFNUM(x) (((x)&0xFF)<<0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_PPCNT */
|
||||
#define MCF_USB_PPCNT_PPCNT(x) (((x)&0xFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_DPCNT */
|
||||
#define MCF_USB_DPCNT_DPCNT(x) (((x)&0xFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_CRCECNT */
|
||||
#define MCF_USB_CRCECNT_CRCECNT(x) (((x)&0xFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_BSECNT */
|
||||
#define MCF_USB_BSECNT_BSECNT(x) (((x)&0xFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_PIDECNT */
|
||||
#define MCF_USB_PIDECNT_PIDECNT(x) (((x)&0xFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_FRMECNT */
|
||||
#define MCF_USB_FRMECNT_FRMECNT(x) (((x)&0xFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_TXPCNT */
|
||||
#define MCF_USB_TXPCNT_TXPCNT(x) (((x)&0xFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_CNTOVR */
|
||||
#define MCF_USB_CNTOVR_PPCNT (0x1)
|
||||
#define MCF_USB_CNTOVR_DPCNT (0x2)
|
||||
#define MCF_USB_CNTOVR_CRCECNT (0x4)
|
||||
#define MCF_USB_CNTOVR_BSECNT (0x8)
|
||||
#define MCF_USB_CNTOVR_PIDECNT (0x10)
|
||||
#define MCF_USB_CNTOVR_FRMECNT (0x20)
|
||||
#define MCF_USB_CNTOVR_TXPCNT (0x40)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_EP0ACR */
|
||||
#define MCF_USB_EP0ACR_TTYPE(x) (((x)&0x3)<<0)
|
||||
#define MCF_USB_EP0ACR_TTYPE_CTRL (0)
|
||||
#define MCF_USB_EP0ACR_TTYPE_ISOC (0x1)
|
||||
#define MCF_USB_EP0ACR_TTYPE_BULK (0x2)
|
||||
#define MCF_USB_EP0ACR_TTYPE_INT (0x3)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_EP0MPSR */
|
||||
#define MCF_USB_EP0MPSR_MAXPKTSZ(x) (((x)&0x7FF)<<0)
|
||||
#define MCF_USB_EP0MPSR_ADDTRANS(x) (((x)&0x3)<<0xB)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_EP0IFR */
|
||||
#define MCF_USB_EP0IFR_IFNUM(x) (((x)&0xFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_EP0SR */
|
||||
#define MCF_USB_EP0SR_HALT (0x1)
|
||||
#define MCF_USB_EP0SR_ACTIVE (0x2)
|
||||
#define MCF_USB_EP0SR_PSTALL (0x4)
|
||||
#define MCF_USB_EP0SR_CCOMP (0x8)
|
||||
#define MCF_USB_EP0SR_TXZERO (0x20)
|
||||
#define MCF_USB_EP0SR_INT (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_BMRTR */
|
||||
#define MCF_USB_BMRTR_REC(x) (((x)&0x1F)<<0)
|
||||
#define MCF_USB_BMRTR_REC_DEVICE (0)
|
||||
#define MCF_USB_BMRTR_REC_INTERFACE (0x1)
|
||||
#define MCF_USB_BMRTR_REC_ENDPOINT (0x2)
|
||||
#define MCF_USB_BMRTR_REC_OTHER (0x3)
|
||||
#define MCF_USB_BMRTR_TYPE(x) (((x)&0x3)<<0x5)
|
||||
#define MCF_USB_BMRTR_TYPE_STANDARD (0)
|
||||
#define MCF_USB_BMRTR_TYPE_CLASS (0x20)
|
||||
#define MCF_USB_BMRTR_TYPE_VENDOR (0x40)
|
||||
#define MCF_USB_BMRTR_DIR (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_BRTR */
|
||||
#define MCF_USB_BRTR_BREQ(x) (((x)&0xFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_WVALUER */
|
||||
#define MCF_USB_WVALUER_WVALUE(x) (((x)&0xFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_WINDEXR */
|
||||
#define MCF_USB_WINDEXR_WINDEX(x) (((x)&0xFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_WLENGTHR */
|
||||
#define MCF_USB_WLENGTHR_WLENGTH(x) (((x)&0xFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_EPOUTACR */
|
||||
#define MCF_USB_EPOUTACR_TTYPE(x) (((x)&0x3)<<0)
|
||||
#define MCF_USB_EPOUTACR_TTYPE_ISOC (0x1)
|
||||
#define MCF_USB_EPOUTACR_TTYPE_BULK (0x2)
|
||||
#define MCF_USB_EPOUTACR_TTYPE_INT (0x3)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_EPOUTMPSR */
|
||||
#define MCF_USB_EPOUTMPSR_MAXPKTSZ(x) (((x)&0x7FF)<<0)
|
||||
#define MCF_USB_EPOUTMPSR_ADDTRANS(x) (((x)&0x3)<<0xB)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_EPOUTIFR */
|
||||
#define MCF_USB_EPOUTIFR_IFNUM(x) (((x)&0xFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_EPOUTSR */
|
||||
#define MCF_USB_EPOUTSR_HALT (0x1)
|
||||
#define MCF_USB_EPOUTSR_ACTIVE (0x2)
|
||||
#define MCF_USB_EPOUTSR_PSTALL (0x4)
|
||||
#define MCF_USB_EPOUTSR_CCOMP (0x8)
|
||||
#define MCF_USB_EPOUTSR_TXZERO (0x20)
|
||||
#define MCF_USB_EPOUTSR_INT (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_EPOUTSFR */
|
||||
#define MCF_USB_EPOUTSFR_FRMNUM(x) (((x)&0x7FF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_EPINACR */
|
||||
#define MCF_USB_EPINACR_TTYPE(x) (((x)&0x3)<<0)
|
||||
#define MCF_USB_EPINACR_TTYPE_ISOC (0x1)
|
||||
#define MCF_USB_EPINACR_TTYPE_BULK (0x2)
|
||||
#define MCF_USB_EPINACR_TTYPE_INT (0x3)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_EPINMPSR */
|
||||
#define MCF_USB_EPINMPSR_MAXPKTSZ(x) (((x)&0x7FF)<<0)
|
||||
#define MCF_USB_EPINMPSR_ADDTRANS(x) (((x)&0x3)<<0xB)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_EPINIFR */
|
||||
#define MCF_USB_EPINIFR_IFNUM(x) (((x)&0xFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_EPINSR */
|
||||
#define MCF_USB_EPINSR_HALT (0x1)
|
||||
#define MCF_USB_EPINSR_ACTIVE (0x2)
|
||||
#define MCF_USB_EPINSR_PSTALL (0x4)
|
||||
#define MCF_USB_EPINSR_CCOMP (0x8)
|
||||
#define MCF_USB_EPINSR_TXZERO (0x20)
|
||||
#define MCF_USB_EPINSR_INT (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_EPINSFR */
|
||||
#define MCF_USB_EPINSFR_FRMNUM(x) (((x)&0x7FF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_USBSR */
|
||||
#define MCF_USB_USBSR_ISOERREP(x) (((x)&0xF)<<0)
|
||||
#define MCF_USB_USBSR_SUSP (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_USBCR */
|
||||
#define MCF_USB_USBCR_RESUME (0x1)
|
||||
#define MCF_USB_USBCR_APPLOCK (0x2)
|
||||
#define MCF_USB_USBCR_RST (0x4)
|
||||
#define MCF_USB_USBCR_RAMEN (0x8)
|
||||
#define MCF_USB_USBCR_RAMSPLIT (0x20)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_DRAMCR */
|
||||
#define MCF_USB_DRAMCR_DADR(x) (((x)&0x3FF)<<0)
|
||||
#define MCF_USB_DRAMCR_DSIZE(x) (((x)&0x7FF)<<0x10)
|
||||
#define MCF_USB_DRAMCR_BSY (0x40000000)
|
||||
#define MCF_USB_DRAMCR_START (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_DRAMDR */
|
||||
#define MCF_USB_DRAMDR_DDAT(x) (((x)&0xFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_USBISR */
|
||||
#define MCF_USB_USBISR_ISOERR (0x1)
|
||||
#define MCF_USB_USBISR_FTUNLCK (0x2)
|
||||
#define MCF_USB_USBISR_SUSP (0x4)
|
||||
#define MCF_USB_USBISR_RES (0x8)
|
||||
#define MCF_USB_USBISR_UPDSOF (0x10)
|
||||
#define MCF_USB_USBISR_RSTSTOP (0x20)
|
||||
#define MCF_USB_USBISR_SOF (0x40)
|
||||
#define MCF_USB_USBISR_MSOF (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_USBIMR */
|
||||
#define MCF_USB_USBIMR_ISOERR (0x1)
|
||||
#define MCF_USB_USBIMR_FTUNLCK (0x2)
|
||||
#define MCF_USB_USBIMR_SUSP (0x4)
|
||||
#define MCF_USB_USBIMR_RES (0x8)
|
||||
#define MCF_USB_USBIMR_UPDSOF (0x10)
|
||||
#define MCF_USB_USBIMR_RSTSTOP (0x20)
|
||||
#define MCF_USB_USBIMR_SOF (0x40)
|
||||
#define MCF_USB_USBIMR_MSOF (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_EPSTAT */
|
||||
#define MCF_USB_EPSTAT_RST (0x1)
|
||||
#define MCF_USB_EPSTAT_FLUSH (0x2)
|
||||
#define MCF_USB_EPSTAT_DIR (0x80)
|
||||
#define MCF_USB_EPSTAT_BYTECNT(x) (((x)&0xFFF)<<0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_EPISR */
|
||||
#define MCF_USB_EPISR_EOF (0x1)
|
||||
#define MCF_USB_EPISR_EOT (0x4)
|
||||
#define MCF_USB_EPISR_FIFOLO (0x10)
|
||||
#define MCF_USB_EPISR_FIFOHI (0x20)
|
||||
#define MCF_USB_EPISR_ERR (0x40)
|
||||
#define MCF_USB_EPISR_EMT (0x80)
|
||||
#define MCF_USB_EPISR_FU (0x100)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_EPIMR */
|
||||
#define MCF_USB_EPIMR_EOF (0x1)
|
||||
#define MCF_USB_EPIMR_EOT (0x4)
|
||||
#define MCF_USB_EPIMR_FIFOLO (0x10)
|
||||
#define MCF_USB_EPIMR_FIFOHI (0x20)
|
||||
#define MCF_USB_EPIMR_ERR (0x40)
|
||||
#define MCF_USB_EPIMR_EMT (0x80)
|
||||
#define MCF_USB_EPIMR_FU (0x100)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_EPFRCFGR */
|
||||
#define MCF_USB_EPFRCFGR_DEPTH(x) (((x)&0x1FFF)<<0)
|
||||
#define MCF_USB_EPFRCFGR_BASE(x) (((x)&0xFFF)<<0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_EPFDR */
|
||||
#define MCF_USB_EPFDR_RX_TXDATA(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_EPFSR */
|
||||
#define MCF_USB_EPFSR_EMT (0x10000)
|
||||
#define MCF_USB_EPFSR_ALRM (0x20000)
|
||||
#define MCF_USB_EPFSR_FU (0x40000)
|
||||
#define MCF_USB_EPFSR_FR (0x80000)
|
||||
#define MCF_USB_EPFSR_OF (0x100000)
|
||||
#define MCF_USB_EPFSR_UF (0x200000)
|
||||
#define MCF_USB_EPFSR_RXW (0x400000)
|
||||
#define MCF_USB_EPFSR_FAE (0x800000)
|
||||
#define MCF_USB_EPFSR_FRM(x) (((x)&0xF)<<0x18)
|
||||
#define MCF_USB_EPFSR_TXW (0x40000000)
|
||||
#define MCF_USB_EPFSR_IP (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_EPFCR */
|
||||
#define MCF_USB_EPFCR_COUNTER(x) (((x)&0xFFFF)<<0)
|
||||
#define MCF_USB_EPFCR_TXWMSK (0x40000)
|
||||
#define MCF_USB_EPFCR_OFMSK (0x80000)
|
||||
#define MCF_USB_EPFCR_UFMSK (0x100000)
|
||||
#define MCF_USB_EPFCR_RXWMSK (0x200000)
|
||||
#define MCF_USB_EPFCR_FAEMSK (0x400000)
|
||||
#define MCF_USB_EPFCR_IPMSK (0x800000)
|
||||
#define MCF_USB_EPFCR_GR(x) (((x)&0x7)<<0x18)
|
||||
#define MCF_USB_EPFCR_FRM (0x8000000)
|
||||
#define MCF_USB_EPFCR_TMR (0x10000000)
|
||||
#define MCF_USB_EPFCR_WFR (0x20000000)
|
||||
#define MCF_USB_EPFCR_SHAD (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_EPFAR */
|
||||
#define MCF_USB_EPFAR_ALRMP(x) (((x)&0xFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_EPFRP */
|
||||
#define MCF_USB_EPFRP_RP(x) (((x)&0xFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_EPFWP */
|
||||
#define MCF_USB_EPFWP_WP(x) (((x)&0xFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_EPLRFP */
|
||||
#define MCF_USB_EPLRFP_LRFP(x) (((x)&0xFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_EPLWFP */
|
||||
#define MCF_USB_EPLWFP_LWFP(x) (((x)&0xFFF)<<0)
|
||||
|
||||
|
||||
#endif /* __MCF5475_USB_H__ */
|
||||
101
include/MCF5475_XLB.h
Normal file
101
include/MCF5475_XLB.h
Normal file
@@ -0,0 +1,101 @@
|
||||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.81
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF5475_XLB_H__
|
||||
#define __MCF5475_XLB_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* XL Bus Arbiter (XLB)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_XLB_XARB_CFG (*(volatile uint32_t*)(&_MBAR[0x240]))
|
||||
#define MCF_XLB_XARB_VER (*(volatile uint32_t*)(&_MBAR[0x244]))
|
||||
#define MCF_XLB_XARB_SR (*(volatile uint32_t*)(&_MBAR[0x248]))
|
||||
#define MCF_XLB_XARB_IMR (*(volatile uint32_t*)(&_MBAR[0x24C]))
|
||||
#define MCF_XLB_XARB_ADRCAP (*(volatile uint32_t*)(&_MBAR[0x250]))
|
||||
#define MCF_XLB_XARB_SIGCAP (*(volatile uint32_t*)(&_MBAR[0x254]))
|
||||
#define MCF_XLB_XARB_ADRTO (*(volatile uint32_t*)(&_MBAR[0x258]))
|
||||
#define MCF_XLB_XARB_DATTO (*(volatile uint32_t*)(&_MBAR[0x25C]))
|
||||
#define MCF_XLB_XARB_BUSTO (*(volatile uint32_t*)(&_MBAR[0x260]))
|
||||
#define MCF_XLB_XARB_PRIEN (*(volatile uint32_t*)(&_MBAR[0x264]))
|
||||
#define MCF_XLB_XARB_PRI (*(volatile uint32_t*)(&_MBAR[0x268]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_XLB_XARB_CFG */
|
||||
#define MCF_XLB_XARB_CFG_AT (0x2)
|
||||
#define MCF_XLB_XARB_CFG_DT (0x4)
|
||||
#define MCF_XLB_XARB_CFG_BA (0x8)
|
||||
#define MCF_XLB_XARB_CFG_PM(x) (((x)&0x3)<<0x5)
|
||||
#define MCF_XLB_XARB_CFG_SP(x) (((x)&0x7)<<0x8)
|
||||
#define MCF_XLB_XARB_CFG_PLDIS (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_XLB_XARB_VER */
|
||||
#define MCF_XLB_XARB_VER_VER(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_XLB_XARB_SR */
|
||||
#define MCF_XLB_XARB_SR_AT (0x1)
|
||||
#define MCF_XLB_XARB_SR_DT (0x2)
|
||||
#define MCF_XLB_XARB_SR_BA (0x4)
|
||||
#define MCF_XLB_XARB_SR_TTM (0x8)
|
||||
#define MCF_XLB_XARB_SR_ECW (0x10)
|
||||
#define MCF_XLB_XARB_SR_TTR (0x20)
|
||||
#define MCF_XLB_XARB_SR_TTA (0x40)
|
||||
#define MCF_XLB_XARB_SR_MM (0x80)
|
||||
#define MCF_XLB_XARB_SR_SEA (0x100)
|
||||
|
||||
/* Bit definitions and macros for MCF_XLB_XARB_IMR */
|
||||
#define MCF_XLB_XARB_IMR_ATE (0x1)
|
||||
#define MCF_XLB_XARB_IMR_DTE (0x2)
|
||||
#define MCF_XLB_XARB_IMR_BAE (0x4)
|
||||
#define MCF_XLB_XARB_IMR_TTME (0x8)
|
||||
#define MCF_XLB_XARB_IMR_ECWE (0x10)
|
||||
#define MCF_XLB_XARB_IMR_TTRE (0x20)
|
||||
#define MCF_XLB_XARB_IMR_TTAE (0x40)
|
||||
#define MCF_XLB_XARB_IMR_MME (0x80)
|
||||
#define MCF_XLB_XARB_IMR_SEAE (0x100)
|
||||
|
||||
/* Bit definitions and macros for MCF_XLB_XARB_ADRCAP */
|
||||
#define MCF_XLB_XARB_ADRCAP_ADRCAP(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_XLB_XARB_SIGCAP */
|
||||
#define MCF_XLB_XARB_SIGCAP_TT(x) (((x)&0x1F)<<0)
|
||||
#define MCF_XLB_XARB_SIGCAP_TBST (0x20)
|
||||
#define MCF_XLB_XARB_SIGCAP_TSIZ(x) (((x)&0x7)<<0x7)
|
||||
|
||||
/* Bit definitions and macros for MCF_XLB_XARB_ADRTO */
|
||||
#define MCF_XLB_XARB_ADRTO_ADRTO(x) (((x)&0xFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_XLB_XARB_DATTO */
|
||||
#define MCF_XLB_XARB_DATTO_DATTO(x) (((x)&0xFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_XLB_XARB_BUSTO */
|
||||
#define MCF_XLB_XARB_BUSTO_BUSTO(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_XLB_XARB_PRIEN */
|
||||
#define MCF_XLB_XARB_PRIEN_M0 (0x1)
|
||||
#define MCF_XLB_XARB_PRIEN_M2 (0x4)
|
||||
#define MCF_XLB_XARB_PRIEN_M3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_XLB_XARB_PRI */
|
||||
#define MCF_XLB_XARB_PRI_M0P(x) (((x)&0x7)<<0)
|
||||
#define MCF_XLB_XARB_PRI_M2P(x) (((x)&0x7)<<0x8)
|
||||
#define MCF_XLB_XARB_PRI_M3P(x) (((x)&0x7)<<0xC)
|
||||
|
||||
|
||||
#endif /* __MCF5475_XLB_H__ */
|
||||
12
include/acia.h
Normal file
12
include/acia.h
Normal file
@@ -0,0 +1,12 @@
|
||||
#ifndef _ACIA_H_
|
||||
#define _ACIA_H_
|
||||
|
||||
/*
|
||||
* ACIA registers
|
||||
*/
|
||||
#define keyctl 0xfffc00
|
||||
#define keybd 0xfffc02
|
||||
#define midictl 0xfffc04
|
||||
#define midi 0xfffc06
|
||||
|
||||
#endif /* _ACIA_H_ */
|
||||
85
include/am79c874.h
Normal file
85
include/am79c874.h
Normal file
@@ -0,0 +1,85 @@
|
||||
/*
|
||||
* File: am79c874.h
|
||||
* Purpose: Driver for the AM79C874 10/100 Ethernet PHY
|
||||
*
|
||||
* Notes:
|
||||
*/
|
||||
|
||||
#ifndef _AM79C874_H_
|
||||
#define _AM79C874_H_
|
||||
|
||||
|
||||
extern int am79c874_init(uint8_t fec_ch, uint8_t phy_addr, uint8_t speed, uint8_t duplex);
|
||||
|
||||
|
||||
/* MII Register Addresses */
|
||||
#define MII_AM79C874_CR 0 /* MII Management Control Register */
|
||||
#define MII_AM79C874_SR 1 /* MII Management Status Register */
|
||||
#define MII_AM79C874_PHYIDR1 2 /* PHY Identifier 1 Register */
|
||||
#define MII_AM79C874_PHYIDR2 3 /* PHY Identifier 2 Register */
|
||||
#define MII_AM79C874_ANAR 4 /* Auto-Negociation Advertissement Register */
|
||||
#define MII_AM79C874_ANLPAR 5 /* Auto-Negociation Link Partner Register */
|
||||
#define MII_AM79C874_ANER 6 /* Auto-Negociation Expansion Register */
|
||||
#define MII_AM79C874_ANNPTR 7 /* Next Page Advertisement Register */
|
||||
#define MII_AM79C874_MFR 16 /* Miscellaneous Feature Register */
|
||||
#define MII_AM79C874_ICSR 17 /* Interrupt/Status Register */
|
||||
#define MII_AM79C874_DR 18 /* Diagnostic Register */
|
||||
#define MII_AM79C874_PMLR 19 /* Power and Loopback Register */
|
||||
#define MII_AM79C874_MCR 21 /* ModeControl Register */
|
||||
#define MII_AM79C874_DC 23 /* Disconnect Counter */
|
||||
#define MII_AM79C874_REC 24 /* Recieve Error Counter */
|
||||
|
||||
/* Bit definitions and macros for MII_AM79C874_CR */
|
||||
#define MII_AM79C874_CR_RESET (0x8000)
|
||||
#define MII_AM79C874_CR_LOOP (0x4000)
|
||||
#define MII_AM79C874_CR_100MB (0x2000)
|
||||
#define MII_AM79C874_CR_AUTON (0x1000)
|
||||
#define MII_AM79C874_CR_POWD (0x0800)
|
||||
#define MII_AM79C874_CR_ISO (0x0400)
|
||||
#define MII_AM79C874_CR_RST_NEG (0x0200)
|
||||
#define MII_AM79C874_CR_DPLX (0x0100)
|
||||
#define MII_AM79C874_CR_COL_TST (0x0080)
|
||||
#define MII_AM79C874_CR_SPEED_MASK (0x2040)
|
||||
#define MII_AM79C874_CR_1000_MPS (0x0040)
|
||||
#define MII_AM79C874_CR_100_MPS (0x2000)
|
||||
#define MII_AM79C874_CR_10_MPS (0x0000)
|
||||
|
||||
/* Bit definitions and macros for MII_AM79C874_SR */
|
||||
#define MII_AM79C874_SR_100T4 (0x8000)
|
||||
#define MII_AM79C874_SR_100TXF (0x4000)
|
||||
#define MII_AM79C874_SR_100TXH (0x2000)
|
||||
#define MII_AM79C874_SR_10TF (0x1000)
|
||||
#define MII_AM79C874_SR_10TH (0x0800)
|
||||
#define MII_AM79C874_SR_PRE_SUP (0x0040)
|
||||
#define MII_AM79C874_SR_AUTN_COMP (0x0020)
|
||||
#define MII_AM79C874_SR_RF (0x0010)
|
||||
#define MII_AM79C874_SR_AUTN_ABLE (0x0008)
|
||||
#define MII_AM79C874_SR_LS (0x0004)
|
||||
#define MII_AM79C874_SR_JD (0x0002)
|
||||
#define MII_AM79C874_SR_EXT (0x0001)
|
||||
|
||||
/* Bit definitions and macros for MII_AM79C874_ANLPAR */
|
||||
#define MII_AM79C874_ANLPAR_NP (0x8000)
|
||||
#define MII_AM79C874_ANLPAR_ACK (0x4000)
|
||||
#define MII_AM79C874_ANLPAR_RF (0x2000)
|
||||
#define MII_AM79C874_ANLPAR_T4 (0x0200)
|
||||
#define MII_AM79C874_ANLPAR_TXFD (0x0100)
|
||||
#define MII_AM79C874_ANLPAR_TX (0x0080)
|
||||
#define MII_AM79C874_ANLPAR_10FD (0x0040)
|
||||
#define MII_AM79C874_ANLPAR_10 (0x0020)
|
||||
#define MII_AM79C874_ANLPAR_100 (0x0380)
|
||||
#define MII_AM79C874_ANLPAR_PSB_MASK (0x001F)
|
||||
#define MII_AM79C874_ANLPAR_PSB_802_3 (0x0001)
|
||||
#define MII_AM79C874_ANLPAR_PSB_802_9 (0x0002)
|
||||
|
||||
/* Bit definitions and macros for MII_AM79C874_DR */
|
||||
#define MII_AM79C874_DR_DPLX (0x0800)
|
||||
#define MII_AM79C874_DR_DATA_RATE (0x0400)
|
||||
#define MII_AM79C874_DR_RX_PASS (0x0200)
|
||||
#define MII_AM79C874_DR_RX_LOCK (0x0100)
|
||||
|
||||
#define AUTONEGLINK (MII_AM79C874_SR_AUTN_COMP | MII_AM79C874_SR_LS)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* _AM79C874_H_ */
|
||||
211
include/ati_ids.h
Normal file
211
include/ati_ids.h
Normal file
@@ -0,0 +1,211 @@
|
||||
/*
|
||||
* ATI PCI IDs from XFree86, kept here to make sync'ing with
|
||||
* XFree much simpler. Currently, this list is only used by
|
||||
* radeonfb
|
||||
*/
|
||||
|
||||
#define PCI_CHIP_RV380_3150 0x3150
|
||||
#define PCI_CHIP_RV380_3151 0x3151
|
||||
#define PCI_CHIP_RV380_3152 0x3152
|
||||
#define PCI_CHIP_RV380_3153 0x3153
|
||||
#define PCI_CHIP_RV380_3154 0x3154
|
||||
#define PCI_CHIP_RV380_3156 0x3156
|
||||
#define PCI_CHIP_RV380_3E50 0x3E50
|
||||
#define PCI_CHIP_RV380_3E51 0x3E51
|
||||
#define PCI_CHIP_RV380_3E52 0x3E52
|
||||
#define PCI_CHIP_RV380_3E53 0x3E53
|
||||
#define PCI_CHIP_RV380_3E54 0x3E54
|
||||
#define PCI_CHIP_RV380_3E56 0x3E56
|
||||
#define PCI_CHIP_RS100_4136 0x4136
|
||||
#define PCI_CHIP_RS200_4137 0x4137
|
||||
#define PCI_CHIP_R300_AD 0x4144
|
||||
#define PCI_CHIP_R300_AE 0x4145
|
||||
#define PCI_CHIP_R300_AF 0x4146
|
||||
#define PCI_CHIP_R300_AG 0x4147
|
||||
#define PCI_CHIP_R350_AH 0x4148
|
||||
#define PCI_CHIP_R350_AI 0x4149
|
||||
#define PCI_CHIP_R350_AJ 0x414A
|
||||
#define PCI_CHIP_R350_AK 0x414B
|
||||
#define PCI_CHIP_RV350_AP 0x4150
|
||||
#define PCI_CHIP_RV350_AQ 0x4151
|
||||
#define PCI_CHIP_RV360_AR 0x4152
|
||||
#define PCI_CHIP_RV350_AS 0x4153
|
||||
#define PCI_CHIP_RV350_AT 0x4154
|
||||
#define PCI_CHIP_RV350_AV 0x4156
|
||||
#define PCI_CHIP_MACH32 0x4158
|
||||
#define PCI_CHIP_RS250_4237 0x4237
|
||||
#define PCI_CHIP_R200_BB 0x4242
|
||||
#define PCI_CHIP_R200_BC 0x4243
|
||||
#define PCI_CHIP_RS100_4336 0x4336
|
||||
#define PCI_CHIP_RS200_4337 0x4337
|
||||
#define PCI_CHIP_MACH64CT 0x4354
|
||||
#define PCI_CHIP_MACH64CX 0x4358
|
||||
#define PCI_CHIP_RS250_4437 0x4437
|
||||
#define PCI_CHIP_MACH64ET 0x4554
|
||||
#define PCI_CHIP_MACH64GB 0x4742
|
||||
#define PCI_CHIP_MACH64GD 0x4744
|
||||
#define PCI_CHIP_MACH64GI 0x4749
|
||||
#define PCI_CHIP_MACH64GL 0x474C
|
||||
#define PCI_CHIP_MACH64GM 0x474D
|
||||
#define PCI_CHIP_MACH64GN 0x474E
|
||||
#define PCI_CHIP_MACH64GO 0x474F
|
||||
#define PCI_CHIP_MACH64GP 0x4750
|
||||
#define PCI_CHIP_MACH64GQ 0x4751
|
||||
#define PCI_CHIP_MACH64GR 0x4752
|
||||
#define PCI_CHIP_MACH64GS 0x4753
|
||||
#define PCI_CHIP_MACH64GT 0x4754
|
||||
#define PCI_CHIP_MACH64GU 0x4755
|
||||
#define PCI_CHIP_MACH64GV 0x4756
|
||||
#define PCI_CHIP_MACH64GW 0x4757
|
||||
#define PCI_CHIP_MACH64GX 0x4758
|
||||
#define PCI_CHIP_MACH64GY 0x4759
|
||||
#define PCI_CHIP_MACH64GZ 0x475A
|
||||
#define PCI_CHIP_RV250_Id 0x4964
|
||||
#define PCI_CHIP_RV250_Ie 0x4965
|
||||
#define PCI_CHIP_RV250_If 0x4966
|
||||
#define PCI_CHIP_RV250_Ig 0x4967
|
||||
#define PCI_CHIP_R420_JH 0x4A48
|
||||
#define PCI_CHIP_R420_JI 0x4A49
|
||||
#define PCI_CHIP_R420_JJ 0x4A4A
|
||||
#define PCI_CHIP_R420_JK 0x4A4B
|
||||
#define PCI_CHIP_R420_JL 0x4A4C
|
||||
#define PCI_CHIP_R420_JM 0x4A4D
|
||||
#define PCI_CHIP_R420_JN 0x4A4E
|
||||
#define PCI_CHIP_R420_JP 0x4A50
|
||||
#define PCI_CHIP_MACH64LB 0x4C42
|
||||
#define PCI_CHIP_MACH64LD 0x4C44
|
||||
#define PCI_CHIP_RAGE128LE 0x4C45
|
||||
#define PCI_CHIP_RAGE128LF 0x4C46
|
||||
#define PCI_CHIP_MACH64LG 0x4C47
|
||||
#define PCI_CHIP_MACH64LI 0x4C49
|
||||
#define PCI_CHIP_MACH64LM 0x4C4D
|
||||
#define PCI_CHIP_MACH64LN 0x4C4E
|
||||
#define PCI_CHIP_MACH64LP 0x4C50
|
||||
#define PCI_CHIP_MACH64LQ 0x4C51
|
||||
#define PCI_CHIP_MACH64LR 0x4C52
|
||||
#define PCI_CHIP_MACH64LS 0x4C53
|
||||
#define PCI_CHIP_MACH64LT 0x4C54
|
||||
#define PCI_CHIP_RADEON_LW 0x4C57
|
||||
#define PCI_CHIP_RADEON_LX 0x4C58
|
||||
#define PCI_CHIP_RADEON_LY 0x4C59
|
||||
#define PCI_CHIP_RADEON_LZ 0x4C5A
|
||||
#define PCI_CHIP_RV250_Ld 0x4C64
|
||||
#define PCI_CHIP_RV250_Le 0x4C65
|
||||
#define PCI_CHIP_RV250_Lf 0x4C66
|
||||
#define PCI_CHIP_RV250_Lg 0x4C67
|
||||
#define PCI_CHIP_RV250_Ln 0x4C6E
|
||||
#define PCI_CHIP_RAGE128MF 0x4D46
|
||||
#define PCI_CHIP_RAGE128ML 0x4D4C
|
||||
#define PCI_CHIP_R300_ND 0x4E44
|
||||
#define PCI_CHIP_R300_NE 0x4E45
|
||||
#define PCI_CHIP_R300_NF 0x4E46
|
||||
#define PCI_CHIP_R300_NG 0x4E47
|
||||
#define PCI_CHIP_R350_NH 0x4E48
|
||||
#define PCI_CHIP_R350_NI 0x4E49
|
||||
#define PCI_CHIP_R360_NJ 0x4E4A
|
||||
#define PCI_CHIP_R350_NK 0x4E4B
|
||||
#define PCI_CHIP_RV350_NP 0x4E50
|
||||
#define PCI_CHIP_RV350_NQ 0x4E51
|
||||
#define PCI_CHIP_RV350_NR 0x4E52
|
||||
#define PCI_CHIP_RV350_NS 0x4E53
|
||||
#define PCI_CHIP_RV350_NT 0x4E54
|
||||
#define PCI_CHIP_RV350_NV 0x4E56
|
||||
#define PCI_CHIP_RAGE128PA 0x5041
|
||||
#define PCI_CHIP_RAGE128PB 0x5042
|
||||
#define PCI_CHIP_RAGE128PC 0x5043
|
||||
#define PCI_CHIP_RAGE128PD 0x5044
|
||||
#define PCI_CHIP_RAGE128PE 0x5045
|
||||
#define PCI_CHIP_RAGE128PF 0x5046
|
||||
#define PCI_CHIP_RAGE128PG 0x5047
|
||||
#define PCI_CHIP_RAGE128PH 0x5048
|
||||
#define PCI_CHIP_RAGE128PI 0x5049
|
||||
#define PCI_CHIP_RAGE128PJ 0x504A
|
||||
#define PCI_CHIP_RAGE128PK 0x504B
|
||||
#define PCI_CHIP_RAGE128PL 0x504C
|
||||
#define PCI_CHIP_RAGE128PM 0x504D
|
||||
#define PCI_CHIP_RAGE128PN 0x504E
|
||||
#define PCI_CHIP_RAGE128PO 0x504F
|
||||
#define PCI_CHIP_RAGE128PP 0x5050
|
||||
#define PCI_CHIP_RAGE128PQ 0x5051
|
||||
#define PCI_CHIP_RAGE128PR 0x5052
|
||||
#define PCI_CHIP_RAGE128PS 0x5053
|
||||
#define PCI_CHIP_RAGE128PT 0x5054
|
||||
#define PCI_CHIP_RAGE128PU 0x5055
|
||||
#define PCI_CHIP_RAGE128PV 0x5056
|
||||
#define PCI_CHIP_RAGE128PW 0x5057
|
||||
#define PCI_CHIP_RAGE128PX 0x5058
|
||||
#define PCI_CHIP_RADEON_QD 0x5144
|
||||
#define PCI_CHIP_RADEON_QE 0x5145
|
||||
#define PCI_CHIP_RADEON_QF 0x5146
|
||||
#define PCI_CHIP_RADEON_QG 0x5147
|
||||
#define PCI_CHIP_R200_QH 0x5148
|
||||
#define PCI_CHIP_R200_QI 0x5149
|
||||
#define PCI_CHIP_R200_QJ 0x514A
|
||||
#define PCI_CHIP_R200_QK 0x514B
|
||||
#define PCI_CHIP_R200_QL 0x514C
|
||||
#define PCI_CHIP_R200_QM 0x514D
|
||||
#define PCI_CHIP_R200_QN 0x514E
|
||||
#define PCI_CHIP_R200_QO 0x514F
|
||||
#define PCI_CHIP_RV200_QW 0x5157
|
||||
#define PCI_CHIP_RV200_QX 0x5158
|
||||
#define PCI_CHIP_RV100_QY 0x5159
|
||||
#define PCI_CHIP_RV100_QZ 0x515A
|
||||
#define PCI_CHIP_RAGE128RE 0x5245
|
||||
#define PCI_CHIP_RAGE128RF 0x5246
|
||||
#define PCI_CHIP_RAGE128RG 0x5247
|
||||
#define PCI_CHIP_RAGE128RK 0x524B
|
||||
#define PCI_CHIP_RAGE128RL 0x524C
|
||||
#define PCI_CHIP_RAGE128SE 0x5345
|
||||
#define PCI_CHIP_RAGE128SF 0x5346
|
||||
#define PCI_CHIP_RAGE128SG 0x5347
|
||||
#define PCI_CHIP_RAGE128SH 0x5348
|
||||
#define PCI_CHIP_RAGE128SK 0x534B
|
||||
#define PCI_CHIP_RAGE128SL 0x534C
|
||||
#define PCI_CHIP_RAGE128SM 0x534D
|
||||
#define PCI_CHIP_RAGE128SN 0x534E
|
||||
#define PCI_CHIP_RAGE128TF 0x5446
|
||||
#define PCI_CHIP_RAGE128TL 0x544C
|
||||
#define PCI_CHIP_RAGE128TR 0x5452
|
||||
#define PCI_CHIP_RAGE128TS 0x5453
|
||||
#define PCI_CHIP_RAGE128TT 0x5454
|
||||
#define PCI_CHIP_RAGE128TU 0x5455
|
||||
#define PCI_CHIP_RV370_5460 0x5460
|
||||
#define PCI_CHIP_RV370_5461 0x5461
|
||||
#define PCI_CHIP_RV370_5462 0x5462
|
||||
#define PCI_CHIP_RV370_5463 0x5463
|
||||
#define PCI_CHIP_RV370_5464 0x5464
|
||||
#define PCI_CHIP_RV370_5465 0x5465
|
||||
#define PCI_CHIP_RV370_5466 0x5466
|
||||
#define PCI_CHIP_RV370_5467 0x5467
|
||||
#define PCI_CHIP_R423_UH 0x5548
|
||||
#define PCI_CHIP_R423_UI 0x5549
|
||||
#define PCI_CHIP_R423_UJ 0x554A
|
||||
#define PCI_CHIP_R423_UK 0x554B
|
||||
#define PCI_CHIP_R423_UQ 0x5551
|
||||
#define PCI_CHIP_R423_UR 0x5552
|
||||
#define PCI_CHIP_R423_UT 0x5554
|
||||
#define PCI_CHIP_MACH64VT 0x5654
|
||||
#define PCI_CHIP_MACH64VU 0x5655
|
||||
#define PCI_CHIP_MACH64VV 0x5656
|
||||
#define PCI_CHIP_RS300_5834 0x5834
|
||||
#define PCI_CHIP_RS300_5835 0x5835
|
||||
#define PCI_CHIP_RS300_5836 0x5836
|
||||
#define PCI_CHIP_RS300_5837 0x5837
|
||||
#define PCI_CHIP_RV370_5B60 0x5B60
|
||||
#define PCI_CHIP_RV370_5B61 0x5B61
|
||||
#define PCI_CHIP_RV370_5B62 0x5B62
|
||||
#define PCI_CHIP_RV370_5B63 0x5B63
|
||||
#define PCI_CHIP_RV370_5B64 0x5B64
|
||||
#define PCI_CHIP_RV370_5B65 0x5B65
|
||||
#define PCI_CHIP_RV370_5B66 0x5B66
|
||||
#define PCI_CHIP_RV370_5B67 0x5B67
|
||||
#define PCI_CHIP_RV280_5960 0x5960
|
||||
#define PCI_CHIP_RV280_5961 0x5961
|
||||
#define PCI_CHIP_RV280_5962 0x5962
|
||||
#define PCI_CHIP_RV280_5964 0x5964
|
||||
#define PCI_CHIP_RV280_5C61 0x5C61
|
||||
#define PCI_CHIP_RV280_5C63 0x5C63
|
||||
#define PCI_CHIP_R423_5D57 0x5D57
|
||||
#define PCI_CHIP_RS350_7834 0x7834
|
||||
#define PCI_CHIP_RS350_7835 0x7835
|
||||
|
||||
48
include/bas_string.h
Normal file
48
include/bas_string.h
Normal file
@@ -0,0 +1,48 @@
|
||||
/*
|
||||
* bas_string.h
|
||||
*
|
||||
* This file is part of BaS_gcc.
|
||||
*
|
||||
* BaS_gcc is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* BaS_gcc is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* Created on: 26.02.2013
|
||||
* Author: Markus Fröschle
|
||||
*/
|
||||
|
||||
#ifndef BAS_STRING_H_
|
||||
#define BAS_STRING_H_
|
||||
|
||||
#include <stddef.h>
|
||||
|
||||
extern int strncmp(const char *s1, const char *s2, size_t max);
|
||||
extern char *strcpy(char *dst, const char *src);
|
||||
char *strncpy(char *dst, const char *src, size_t max);
|
||||
extern int strcmp(const char *s1, const char *s2);
|
||||
extern size_t strlen(const char *str);
|
||||
extern char *strcat(char *dst, const char *src);
|
||||
extern char *strncat(char *dst, const char *src, size_t max);
|
||||
extern int atoi(const char *c);
|
||||
extern void *memcpy(void *dst, const void *src, size_t n);
|
||||
extern void *memmove(void *dst, const void *src, size_t n);
|
||||
extern void *memset(void *s, int c, size_t n);
|
||||
extern int memcmp(const void *s1, const void *s2, size_t max);
|
||||
extern void bzero(void *s, size_t n);
|
||||
|
||||
#define isdigit(c) (((c) >= '0') && ((c) <= '9'))
|
||||
#define isupper(c) ((c) >= 'A' && ((c) <= 'Z'))
|
||||
#define islower(c) ((c) >= 'a' && ((c) <= 'z'))
|
||||
#define isalpha(c) (isupper((c)) || islower(c))
|
||||
#define tolower(c) (isupper(c) ? ((c) + 'a' - 'A') : (c))
|
||||
|
||||
#endif /* BAS_STRING_H_ */
|
||||
35
include/bas_types.h
Normal file
35
include/bas_types.h
Normal file
@@ -0,0 +1,35 @@
|
||||
/*
|
||||
* bas_types.h
|
||||
*
|
||||
* Created on: 17.11.2012
|
||||
* Author: mfro
|
||||
*
|
||||
* This file is part of BaS_gcc.
|
||||
*
|
||||
* BaS_gcc is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* BaS_gcc is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* Copyright 2010 - 2012 F. Aschwanden
|
||||
* Copyright 2011 - 2012 V. Riviere
|
||||
* Copyright 2012 M. Froeschle
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef BAS_TYPES_H_
|
||||
#define BAS_TYPES_H_
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include <stddef.h> /* for sizeof() etc. */
|
||||
|
||||
#endif /* BAS_TYPES_H_ */
|
||||
32
include/bas_utils.h
Normal file
32
include/bas_utils.h
Normal file
@@ -0,0 +1,32 @@
|
||||
/*
|
||||
* bas_utils.h
|
||||
*
|
||||
* This file is part of BaS_gcc.
|
||||
*
|
||||
* BaS_gcc is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* BaS_gcc is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* Created on: 26.02.2013
|
||||
* Author: Markus Fröschle
|
||||
*/
|
||||
|
||||
#ifndef _BAS_UTILS_H_
|
||||
#define _BAS_UTILS_H_
|
||||
|
||||
#define CLEAR_BIT(p,bit) p &= ~(bit)
|
||||
#define CLEAR_BIT_NO(p,nr) CLEAR_BIT(p, (1 << (nr)))
|
||||
|
||||
extern void write_pic_byte(uint8_t value);
|
||||
extern uint8_t read_pic_byte(void);
|
||||
|
||||
#endif /* _BAS_UTILS_H_ */
|
||||
71
include/bcm5222.h
Normal file
71
include/bcm5222.h
Normal file
@@ -0,0 +1,71 @@
|
||||
/*
|
||||
* File: bcm5222.h
|
||||
* Purpose: Driver for the BCM5222 10/100 Ethernet PHY
|
||||
*
|
||||
* Notes:
|
||||
*/
|
||||
|
||||
#ifndef _BCM5222_H_
|
||||
#define _BCM5222_H_
|
||||
|
||||
extern int bcm5222_init(uint8_t, uint8_t, uint8_t, uint8_t);
|
||||
extern void bcm5222_get_reg(uint16_t*, uint16_t*);
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
/* MII Register Addresses */
|
||||
#define BCM5222_CTRL (0x00)
|
||||
#define BCM5222_STAT (0x01)
|
||||
#define BCM5222_PHY_ID1 (0x02)
|
||||
#define BCM5222_PHY_ID2 (0x03)
|
||||
#define BCM5222_AN_ADV (0x04)
|
||||
#define BCM5222_AN_LINK_PAR (0x05)
|
||||
#define BCM5222_AN_EXP (0x06)
|
||||
#define BCM5222_AN_NPR (0x07)
|
||||
#define BCM5222_LINK_NPA (0x08)
|
||||
#define BCM5222_ACSR (0x18)
|
||||
|
||||
/* Bit definitions and macros for BCM5222_CTRL */
|
||||
#define BCM5222_CTRL_RESET (0x8000)
|
||||
#define BCM5222_CTRL_LOOP (0x4000)
|
||||
#define BCM5222_CTRL_SPEED (0x2000)
|
||||
#define BCM5222_CTRL_ANE (0x1000)
|
||||
#define BCM5222_CTRL_PD (0x0800)
|
||||
#define BCM5222_CTRL_ISOLATE (0x0400)
|
||||
#define BCM5222_CTRL_RESTART_AN (0x0200)
|
||||
#define BCM5222_CTRL_FDX (0x0100)
|
||||
#define BCM5222_CTRL_COL_TEST (0x0080)
|
||||
|
||||
|
||||
/* Bit definitions and macros for BCM5222_STAT */
|
||||
#define BCM5222_STAT_100BT4 (0x8000)
|
||||
#define BCM5222_STAT_100BTX_FDX (0x4000)
|
||||
#define BCM5222_STAT_100BTX (0x2000)
|
||||
#define BCM5222_STAT_10BT_FDX (0x1000)
|
||||
#define BCM5222_STAT_10BT (0x0800)
|
||||
#define BCM5222_STAT_NO_PREAMBLE (0x0040)
|
||||
#define BCM5222_STAT_AN_COMPLETE (0x0020)
|
||||
#define BCM5222_STAT_REMOTE_FAULT (0x0010)
|
||||
#define BCM5222_STAT_AN_ABILITY (0x0008)
|
||||
#define BCM5222_STAT_LINK (0x0004)
|
||||
#define BCM5222_STAT_JABBER (0x0002)
|
||||
#define BCM5222_STAT_EXTENDED (0x0001)
|
||||
|
||||
/* Bit definitions and macros for BCM5222_AN_ADV */
|
||||
#define BCM5222_AN_ADV_NEXT_PAGE (0x8001)
|
||||
#define BCM5222_AN_ADV_REM_FAULT (0x2001)
|
||||
#define BCM5222_AN_ADV_PAUSE (0x0401)
|
||||
#define BCM5222_AN_ADV_100BT4 (0x0201)
|
||||
#define BCM5222_AN_ADV_100BTX_FDX (0x0101)
|
||||
#define BCM5222_AN_ADV_100BTX (0x0081)
|
||||
#define BCM5222_AN_ADV_10BT_FDX (0x0041)
|
||||
#define BCM5222_AN_ADV_10BT (0x0021)
|
||||
#define BCM5222_AN_ADV_802_3 (0x0001)
|
||||
|
||||
/* Bit definitions and macros for BCM5222_ACSR */
|
||||
#define BCM5222_ACSR_100BTX (0x0002)
|
||||
#define BCM5222_ACSR_FDX (0x0001)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* _BCM5222_H_ */
|
||||
69
include/bootp.h
Normal file
69
include/bootp.h
Normal file
@@ -0,0 +1,69 @@
|
||||
/*
|
||||
* File: bootp.h
|
||||
* Purpose: BOOTP definitions.
|
||||
*
|
||||
* Notes:
|
||||
*/
|
||||
|
||||
#ifndef _BOOTP_H_
|
||||
#define _BOOTP_H_
|
||||
|
||||
#define BOOTP_SERVER_PORT 67
|
||||
#define BOOTP_CLIENT_PORT 68
|
||||
|
||||
/* protocol header information */
|
||||
#define BOOTP_HDR_OFFSET (ETH_HDR_LEN + IP_HDR_SIZE + UDP_HDR_SIZE)
|
||||
|
||||
/* timeout in seconds */
|
||||
#define BOOTP_TIMEOUT 2
|
||||
|
||||
/* BOOTP connection status */
|
||||
|
||||
struct bootp_connection
|
||||
{
|
||||
bool open; /* connection established flag */
|
||||
NIF *nif; /* pointer to network interface */
|
||||
IP_ADDR server_ip; /* server IP address */
|
||||
};
|
||||
|
||||
/*
|
||||
* This data definition is defined for Ethernet only!
|
||||
*/
|
||||
struct bootp_packet
|
||||
{
|
||||
uint8_t type; /* bootp operation type */
|
||||
uint8_t htype; /* hardware type */
|
||||
uint8_t hlen; /* hardware address length */
|
||||
uint8_t hops; /* hops */
|
||||
uint32_t xid; /* transaction identifier */
|
||||
uint16_t secs; /* seconds since trying to boot */
|
||||
uint16_t flags; /* only broadcast flag in use */
|
||||
uint32_t cl_addr; /* client ip address. Set to all 0 on request */
|
||||
uint32_t yi_addr; /* this field contains the new IP */
|
||||
uint32_t gi_addr; /* gateway address */
|
||||
uint8_t ch_addr[16]; /* client hw address */
|
||||
uint8_t sname[64]; /* server name */
|
||||
uint8_t file[128]; /* name of bootfile */
|
||||
uint8_t vend[64]; /* vendor specific (see below) */
|
||||
};
|
||||
|
||||
#define BOOTP_PACKET_LEN (BOOTP_HDR_OFFSET + sizeof(struct bootp_packet))
|
||||
|
||||
/* possible values for type field */
|
||||
#define BOOTP_TYPE_BOOTREQUEST 1
|
||||
#define BOOTP_TYPE_BOOTREPLY 2
|
||||
|
||||
/* values for hardware type - we only use ethernet */
|
||||
#define BOOTP_HTYPE_ETHERNET 1
|
||||
|
||||
/* values for hlen - again only ethernet defined */
|
||||
#define BOOTP_HLEN_ETHERNET 6
|
||||
|
||||
/* values for flags - only broadcast flag in use */
|
||||
#define BOOTP_FLAGS_BROADCAST 1
|
||||
|
||||
extern void bootp_request(NIF *, uint8_t *);
|
||||
extern void bootp_handler(NIF *, NBUF *);
|
||||
//extern void bootp_init(BOOTP_INFO *);
|
||||
|
||||
#endif /* _BOOTP_H_ */
|
||||
89
include/cache.h
Normal file
89
include/cache.h
Normal file
@@ -0,0 +1,89 @@
|
||||
#ifndef _CACHE_H_
|
||||
#define _CACHE_H_
|
||||
|
||||
/*
|
||||
* cache.h
|
||||
*
|
||||
* This file is part of BaS_gcc.
|
||||
*
|
||||
* BaS_gcc is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* BaS_gcc is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* Copyright 2010 - 2012 F. Aschwanden
|
||||
* Copyright 2011 - 2012 V. Riviere
|
||||
* Copyright 2012 M. Froeschle
|
||||
*
|
||||
*/
|
||||
|
||||
#include <bas_types.h>
|
||||
|
||||
/*
|
||||
* CACR Cache Control Register
|
||||
*/
|
||||
#define CF_CACR_DEC (0x80000000) /* Data Cache Enable */
|
||||
#define CF_CACR_DW (0x40000000) /* Data default Write-protect */
|
||||
#define CF_CACR_DESB (0x20000000) /* Data Enable Store Buffer */
|
||||
#define CF_CACR_DPI (0x10000000) /* Data Disable CPUSHL Invalidate */
|
||||
#define CF_CACR_DHLCK (0x08000000) /* 1/2 Data Cache Lock Mode */
|
||||
#define CF_CACR_DDCM_00 (0x00000000) /* Cacheable writethrough imprecise */
|
||||
#define CF_CACR_DDCM_01 (0x02000000) /* Cacheable copyback */
|
||||
#define CF_CACR_DDCM_10 (0x04000000) /* Noncacheable precise */
|
||||
#define CF_CACR_DDCM_11 (0x06000000) /* Noncacheable imprecise */
|
||||
#define CF_CACR_DCINVA (0x01000000) /* Data Cache Invalidate All */
|
||||
#define CF_CACR_DDSP (0x00800000) /* Data default supervisor-protect */
|
||||
#define CF_CACR_IVO (0x00100000) /* Invalidate only */
|
||||
#define CF_CACR_BEC (0x00080000) /* Branch Cache Enable */
|
||||
#define CF_CACR_BCINVA (0x00040000) /* Branch Cache Invalidate All */
|
||||
#define CF_CACR_IEC (0x00008000) /* Instruction Cache Enable */
|
||||
#define CF_CACR_SPA (0x00004000) /* Search by Physical Address */
|
||||
#define CF_CACR_DNFB (0x00002000) /* Default cache-inhibited fill buf */
|
||||
#define CF_CACR_IDPI (0x00001000) /* Instr Disable CPUSHL Invalidate */
|
||||
#define CF_CACR_IHLCK (0x00000800) /* 1/2 Instruction Cache Lock Mode */
|
||||
#define CF_CACR_IDCM (0x00000400) /* Noncacheable Instr default mode */
|
||||
#define CF_CACR_ICINVA (0x00000100) /* Instr Cache Invalidate All */
|
||||
#define CF_CACR_IDSP (0x00000080) /* Ins default supervisor-protect */
|
||||
#define CF_CACR_EUSP (0x00000020) /* Switch stacks in user mode */
|
||||
#define CF_CACR_DF (0x00000010) /* Disable FPU */
|
||||
|
||||
#define _DCACHE_SET_MASK ((DCACHE_SIZE / 64 - 1) << CACHE_WAYS)
|
||||
#define _ICACHE_SET_MASK ((ICACHE_SIZE / 64 - 1) << CACHE_WAYS)
|
||||
#define LAST_DCACHE_ADDR _DCACHE_SET_MASK
|
||||
#define LAST_ICACHE_ADDR _ICACHE_SET_MASK
|
||||
|
||||
#define ICACHE_SIZE 0x8000 /* instruction - 32k */
|
||||
#define DCACHE_SIZE 0x8000 /* data - 32k */
|
||||
|
||||
#define CACHE_LINE_SIZE 0x0010 /* 16 bytes */
|
||||
#define CACHE_SETS 0x0200 /* 512 sets */
|
||||
#define CACHE_WAYS 0x0004 /* 4 way */
|
||||
|
||||
|
||||
#define CACHE_DISABLE_MODE (CF_CACR_DCINVA + \
|
||||
CF_CACR_BCINVA + \
|
||||
CF_CACR_ICINVA)
|
||||
|
||||
#define CACHE_INITIAL_MODE (CF_CACR_DEC + \
|
||||
CF_CACR_BEC + \
|
||||
CF_CACR_IEC + \
|
||||
CF_CACR_DESB + \
|
||||
CF_CACR_EUSP)
|
||||
|
||||
extern void flush_and_invalidate_caches(void);
|
||||
extern uint32_t cacr_get(void);
|
||||
extern void cacr_set(uint32_t);
|
||||
extern void flush_icache_range(void *address, size_t size);
|
||||
extern void flush_dcache_range(void *address, size_t size);
|
||||
extern void flush_cache_range(void *address, size_t size);
|
||||
|
||||
|
||||
#endif /* _CACHE_H_ */
|
||||
16
include/debug.h
Normal file
16
include/debug.h
Normal file
@@ -0,0 +1,16 @@
|
||||
#ifndef DEBUG_H
|
||||
// #define DEBUG_H
|
||||
|
||||
#ifdef DEBUG
|
||||
#include "bas_types.h"
|
||||
#include "bas_printf.h"
|
||||
|
||||
#define dbg(format, arg...) do { xprintf("DEBUG (%s()): " format, __FUNCTION__, ##arg);} while(0)
|
||||
#else
|
||||
#define dbg(format, arg...) do {;} while (0)
|
||||
#endif /* DEBUG */
|
||||
#define err(format, arg...) do { xprintf("ERROR (%s()): " format, __FUNCTION__, ##arg); } while(0)
|
||||
#define inf(format, arg...) do { xprintf("" format, ##arg); } while(0)
|
||||
|
||||
#endif // DEBUG_H
|
||||
|
||||
15
include/driver_mem.h
Normal file
15
include/driver_mem.h
Normal file
@@ -0,0 +1,15 @@
|
||||
#ifndef _DRIVER_MEM_H_
|
||||
#define _DRIVER_MEM_H_
|
||||
|
||||
#include "bas_types.h"
|
||||
|
||||
/*
|
||||
* the driver_mem module provides a block of _uncached_ memory for USB and other drivers as
|
||||
* well as some memory handling functions for it
|
||||
*/
|
||||
extern int driver_mem_init(void);
|
||||
extern void *driver_mem_alloc(uint32_t amount);
|
||||
extern int32_t driver_mem_free(void *addr);
|
||||
extern void driver_mem_release(void);
|
||||
|
||||
#endif /* _DRIVER_MEM_H_ */
|
||||
216
include/driver_vec.h
Normal file
216
include/driver_vec.h
Normal file
@@ -0,0 +1,216 @@
|
||||
/*
|
||||
* driver_vec.h
|
||||
*
|
||||
* Interface for exposure of BaS drivers to the OS
|
||||
*
|
||||
* This file is part of BaS_gcc.
|
||||
*
|
||||
* BaS_gcc is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* BaS_gcc is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* Created on: 24.10.2013
|
||||
* Author: Markus Fröschle
|
||||
*/
|
||||
|
||||
#ifndef _DRIVER_VEC_H_
|
||||
#define _DRIVER_VEC_H_
|
||||
|
||||
#include "xhdi_sd.h"
|
||||
#include "MCD_dma.h"
|
||||
#include "pci.h"
|
||||
#include "fb.h"
|
||||
|
||||
enum driver_type
|
||||
{
|
||||
BLOCKDEV_DRIVER,
|
||||
CHARDEV_DRIVER,
|
||||
XHDI_DRIVER,
|
||||
MCD_DRIVER,
|
||||
VIDEO_DRIVER,
|
||||
PCI_DRIVER,
|
||||
MMU_DRIVER,
|
||||
PCI_NATIVE_DRIVER,
|
||||
END_OF_DRIVERS = 0xffffffffL, /* marks end of driver list */
|
||||
};
|
||||
|
||||
struct generic_driver_interface
|
||||
{
|
||||
uint32_t (*init)(void);
|
||||
uint32_t (*read)(void *buf, size_t count);
|
||||
uint32_t (*write)(const void *buf, size_t count);
|
||||
uint32_t (*ioctl)(uint32_t request, ...);
|
||||
};
|
||||
|
||||
struct dma_driver_interface
|
||||
{
|
||||
int32_t version;
|
||||
int32_t magic;
|
||||
int (*dma_set_initiator)(int initiator);
|
||||
uint32_t (*dma_get_initiator)(int requestor);
|
||||
void (*dma_free_initiator)(int requestor);
|
||||
int (*dma_set_channel)(int requestor, void (*handler)(void));
|
||||
int (*dma_get_channel)(int requestor);
|
||||
void (*dma_free_channel)(int requestor);
|
||||
void (*dma_clear_channel)(int channel);
|
||||
int (*MCD_startDma)(long channel,
|
||||
int8_t *srcAddr, unsigned int srcIncr, int8_t *destAddr, unsigned int destIncr,
|
||||
unsigned int dmaSize, unsigned int xferSize, unsigned int initiator, int priority,
|
||||
unsigned int flags, unsigned int funcDesc);
|
||||
int32_t (*MCD_dmaStatus)(int32_t channel);
|
||||
int32_t (*MCD_XferProgrQuery)(int32_t channel, MCD_XferProg *progRep);
|
||||
int32_t (*MCD_killDma)(int32_t channel);
|
||||
int32_t (*MCD_continDma)(int32_t channel);
|
||||
int32_t (*MCD_pauseDma)(int32_t channel);
|
||||
int32_t (*MCD_resumeDma)(int32_t channel);
|
||||
int32_t (*MCD_csumQuery)(int32_t channel, uint32_t *csum);
|
||||
void *(*dma_malloc)(uint32_t amount);
|
||||
int32_t (*dma_free)(void *addr);
|
||||
};
|
||||
|
||||
struct xhdi_driver_interface
|
||||
{
|
||||
uint32_t (*xhdivec)();
|
||||
};
|
||||
|
||||
|
||||
|
||||
struct framebuffer_driver_interface
|
||||
{
|
||||
struct fb_info **framebuffer_info; /* pointer to an fb_info struct (defined in include/fb.h) */
|
||||
};
|
||||
|
||||
struct pci_bios_interface
|
||||
{
|
||||
uint32_t subjar;
|
||||
uint32_t version;
|
||||
/* Although we declare this functions as standard gcc functions (cdecl),
|
||||
* they expect parameters inside registers (fastcall) unsupported by gcc m68k.
|
||||
* Caller will take care of parameters passing convention.
|
||||
*/
|
||||
int32_t (*find_pci_device)(uint32_t id, uint16_t index);
|
||||
int32_t (*find_pci_classcode)(uint32_t class, uint16_t index);
|
||||
int32_t (*read_config_byte)(int32_t handle, uint16_t reg, uint8_t *address);
|
||||
int32_t (*read_config_word)(int32_t handle, uint16_t reg, uint16_t *address);
|
||||
int32_t (*read_config_longword)(int32_t handle, uint16_t reg, uint32_t *address);
|
||||
uint8_t (*fast_read_config_byte)(int32_t handle, uint16_t reg);
|
||||
uint16_t (*fast_read_config_word)(int32_t handle, uint16_t reg);
|
||||
uint32_t (*fast_read_config_longword)(int32_t handle, uint16_t reg);
|
||||
int32_t (*write_config_byte)(int32_t handle, uint16_t reg, uint16_t val);
|
||||
int32_t (*write_config_word)(int32_t handle, uint16_t reg, uint16_t val);
|
||||
int32_t (*write_config_longword)(int32_t handle, uint16_t reg, uint32_t val);
|
||||
int32_t (*hook_interrupt)(int32_t handle, uint32_t *routine, uint32_t *parameter);
|
||||
int32_t (*unhook_interrupt)(int32_t handle);
|
||||
int32_t (*special_cycle)(uint16_t bus, uint32_t data);
|
||||
int32_t (*get_routing)(int32_t handle);
|
||||
int32_t (*set_interrupt)(int32_t handle);
|
||||
int32_t (*get_resource)(int32_t handle);
|
||||
int32_t (*get_card_used)(int32_t handle, uint32_t *address);
|
||||
int32_t (*set_card_used)(int32_t handle, uint32_t *callback);
|
||||
int32_t (*read_mem_byte)(int32_t handle, uint32_t offset, uint8_t *address);
|
||||
int32_t (*read_mem_word)(int32_t handle, uint32_t offset, uint16_t *address);
|
||||
int32_t (*read_mem_longword)(int32_t handle, uint32_t offset, uint32_t *address);
|
||||
uint8_t (*fast_read_mem_byte)(int32_t handle, uint32_t offset);
|
||||
uint16_t (*fast_read_mem_word)(int32_t handle, uint32_t offset);
|
||||
uint32_t (*fast_read_mem_longword)(int32_t handle, uint32_t offset);
|
||||
int32_t (*write_mem_byte)(int32_t handle, uint32_t offset, uint16_t val);
|
||||
int32_t (*write_mem_word)(int32_t handle, uint32_t offset, uint16_t val);
|
||||
int32_t (*write_mem_longword)(int32_t handle, uint32_t offset, uint32_t val);
|
||||
int32_t (*read_io_byte)(int32_t handle, uint32_t offset, uint8_t *address);
|
||||
int32_t (*read_io_word)(int32_t handle, uint32_t offset, uint16_t *address);
|
||||
int32_t (*read_io_longword)(int32_t handle, uint32_t offset, uint32_t *address);
|
||||
uint8_t (*fast_read_io_byte)(int32_t handle, uint32_t offset);
|
||||
uint16_t (*fast_read_io_word)(int32_t handle, uint32_t offset);
|
||||
uint32_t (*fast_read_io_longword)(int32_t handle, uint32_t offset);
|
||||
int32_t (*write_io_byte)(int32_t handle, uint32_t offset, uint16_t val);
|
||||
int32_t (*write_io_word)(int32_t handle, uint32_t offset, uint16_t val);
|
||||
int32_t (*write_io_longword)(int32_t handle, uint32_t offset, uint32_t val);
|
||||
int32_t (*get_machine_id)(void);
|
||||
int32_t (*get_pagesize)(void);
|
||||
int32_t (*virt_to_bus)(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer);
|
||||
int32_t (*bus_to_virt)(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer);
|
||||
int32_t (*virt_to_phys)(uint32_t address, PCI_CONV_ADR *pointer);
|
||||
int32_t (*phys_to_virt)(uint32_t address, PCI_CONV_ADR *pointer);
|
||||
// int32_t reserved[2];
|
||||
};
|
||||
|
||||
struct mmu_driver_interface
|
||||
{
|
||||
uint32_t (*map_page_locked)(uint32_t address, uint32_t length, int asid);
|
||||
uint32_t (*unlock_page)(uint32_t address, uint32_t length, int asid);
|
||||
uint32_t (*report_locked_pages)(uint32_t *num_itlb, uint32_t *num_dtlb);
|
||||
uint32_t (*report_pagesize)(void);
|
||||
};
|
||||
|
||||
struct pci_native_driver_interface_0_1
|
||||
{
|
||||
uint32_t (*pci_read_config_longword)(int32_t handle, int offset);
|
||||
uint16_t (*pci_read_config_word)(int32_t handle, int offset);
|
||||
uint8_t (*pci_read_config_byte)(int32_t handle, int offset);
|
||||
|
||||
int32_t (*pci_write_config_longword)(int32_t handle, int offset, uint32_t value);
|
||||
int32_t (*pci_write_config_word)(int32_t handle, int offset, uint16_t value);
|
||||
int32_t (*pci_write_config_byte)(int32_t handle, int offset, uint8_t value);
|
||||
int32_t (*pci_hook_interrupt)(int32_t handle, void *handler, void *parameter);
|
||||
int32_t (*pci_unhook_interrupt)(int32_t handle);
|
||||
|
||||
struct pci_rd * (*pci_get_resource)(int32_t handle);
|
||||
};
|
||||
|
||||
struct pci_native_driver_interface
|
||||
{
|
||||
uint32_t (*pci_read_config_longword)(int32_t handle, int offset);
|
||||
uint16_t (*pci_read_config_word)(int32_t handle, int offset);
|
||||
uint8_t (*pci_read_config_byte)(int32_t handle, int offset);
|
||||
|
||||
int32_t (*pci_write_config_longword)(int32_t handle, int offset, uint32_t value);
|
||||
int32_t (*pci_write_config_word)(int32_t handle, int offset, uint16_t value);
|
||||
int32_t (*pci_write_config_byte)(int32_t handle, int offset, uint8_t value);
|
||||
int32_t (*pci_hook_interrupt)(int32_t handle, void *handler, void *parameter);
|
||||
int32_t (*pci_unhook_interrupt)(int32_t handle);
|
||||
int32_t (*pci_find_device)(uint16_t device_id, uint16_t vendor_id, int index);
|
||||
int32_t (*pci_find_classcode)(uint32_t classcode, int index);
|
||||
struct pci_rd * (*pci_get_resource)(int32_t handle);
|
||||
};
|
||||
|
||||
union interface
|
||||
{
|
||||
struct generic_driver_interface *gdi;
|
||||
struct xhdi_driver_interface *xhdi;
|
||||
struct dma_driver_interface *dma;
|
||||
struct framebuffer_driver_interface *fb;
|
||||
struct pci_bios_interface *pci;
|
||||
struct mmu_driver_interface *mmu;
|
||||
struct pci_native_driver_interface_0_1 *pci_native_0_1;
|
||||
struct pci_native_driver_interface *pci_native;
|
||||
};
|
||||
|
||||
struct generic_interface
|
||||
{
|
||||
enum driver_type type;
|
||||
char name[16];
|
||||
char description[64];
|
||||
int version;
|
||||
int revision;
|
||||
union interface interface;
|
||||
};
|
||||
|
||||
struct driver_table
|
||||
{
|
||||
uint32_t bas_version;
|
||||
uint32_t bas_revision;
|
||||
void (*remove_handler)(void); /* calling this will disable the BaS' hook into trap #0 */
|
||||
struct generic_interface *interfaces;
|
||||
};
|
||||
|
||||
|
||||
#endif /* _DRIVER_VEC_H_ */
|
||||
138
include/edid.h
Normal file
138
include/edid.h
Normal file
@@ -0,0 +1,138 @@
|
||||
/*
|
||||
* edid.h - EDID/DDC Header
|
||||
*
|
||||
* Based on:
|
||||
* 1. XFree86 4.3.0, edid.h
|
||||
* Copyright 1998 by Egbert Eich <Egbert.Eich@Physik.TU-Darmstadt.DE>
|
||||
*
|
||||
* 2. John Fremlin <vii@users.sourceforge.net> and
|
||||
* Ani Joshi <ajoshi@unixbox.com>
|
||||
*
|
||||
* DDC is a Trademark of VESA (Video Electronics Standard Association).
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file COPYING in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
|
||||
#ifndef __EDID_H__
|
||||
#define __EDID_H__
|
||||
|
||||
#define EDID_LENGTH 0x80
|
||||
#define EDID_HEADER 0x00
|
||||
#define EDID_HEADER_END 0x07
|
||||
|
||||
#define ID_MANUFACTURER_NAME 0x08
|
||||
#define ID_MANUFACTURER_NAME_END 0x09
|
||||
#define ID_MODEL 0x0a
|
||||
|
||||
#define ID_SERIAL_NUMBER 0x0c
|
||||
|
||||
#define MANUFACTURE_WEEK 0x10
|
||||
#define MANUFACTURE_YEAR 0x11
|
||||
|
||||
#define EDID_STRUCT_VERSION 0x12
|
||||
#define EDID_STRUCT_REVISION 0x13
|
||||
|
||||
#define EDID_STRUCT_DISPLAY 0x14
|
||||
|
||||
#define DPMS_FLAGS 0x18
|
||||
#define ESTABLISHED_TIMING_1 0x23
|
||||
#define ESTABLISHED_TIMING_2 0x24
|
||||
#define MANUFACTURERS_TIMINGS 0x25
|
||||
|
||||
/* standard timings supported */
|
||||
#define STD_TIMING 8
|
||||
#define STD_TIMING_DESCRIPTION_SIZE 2
|
||||
#define STD_TIMING_DESCRIPTIONS_START 0x26
|
||||
|
||||
#define DETAILED_TIMING_DESCRIPTIONS_START 0x36
|
||||
#define DETAILED_TIMING_DESCRIPTION_SIZE 18
|
||||
#define NO_DETAILED_TIMING_DESCRIPTIONS 4
|
||||
|
||||
#define DETAILED_TIMING_DESCRIPTION_1 0x36
|
||||
#define DETAILED_TIMING_DESCRIPTION_2 0x48
|
||||
#define DETAILED_TIMING_DESCRIPTION_3 0x5a
|
||||
#define DETAILED_TIMING_DESCRIPTION_4 0x6c
|
||||
|
||||
#define DESCRIPTOR_DATA 5
|
||||
|
||||
#define UPPER_NIBBLE( x ) \
|
||||
(((128|64|32|16) & (x)) >> 4)
|
||||
|
||||
#define LOWER_NIBBLE( x ) \
|
||||
((1|2|4|8) & (x))
|
||||
|
||||
#define COMBINE_HI_8LO( hi, lo ) \
|
||||
( (((unsigned)hi) << 8) | (unsigned)lo )
|
||||
|
||||
#define COMBINE_HI_4LO( hi, lo ) \
|
||||
( (((unsigned)hi) << 4) | (unsigned)lo )
|
||||
|
||||
#define PIXEL_CLOCK_LO (unsigned)block[ 0 ]
|
||||
#define PIXEL_CLOCK_HI (unsigned)block[ 1 ]
|
||||
#define PIXEL_CLOCK (COMBINE_HI_8LO( PIXEL_CLOCK_HI,PIXEL_CLOCK_LO )*10000)
|
||||
#define H_ACTIVE_LO (unsigned)block[ 2 ]
|
||||
#define H_BLANKING_LO (unsigned)block[ 3 ]
|
||||
#define H_ACTIVE_HI UPPER_NIBBLE( (unsigned)block[ 4 ] )
|
||||
#define H_ACTIVE COMBINE_HI_8LO( H_ACTIVE_HI, H_ACTIVE_LO )
|
||||
#define H_BLANKING_HI LOWER_NIBBLE( (unsigned)block[ 4 ] )
|
||||
#define H_BLANKING COMBINE_HI_8LO( H_BLANKING_HI, H_BLANKING_LO )
|
||||
|
||||
#define V_ACTIVE_LO (unsigned)block[ 5 ]
|
||||
#define V_BLANKING_LO (unsigned)block[ 6 ]
|
||||
#define V_ACTIVE_HI UPPER_NIBBLE( (unsigned)block[ 7 ] )
|
||||
#define V_ACTIVE COMBINE_HI_8LO( V_ACTIVE_HI, V_ACTIVE_LO )
|
||||
#define V_BLANKING_HI LOWER_NIBBLE( (unsigned)block[ 7 ] )
|
||||
#define V_BLANKING COMBINE_HI_8LO( V_BLANKING_HI, V_BLANKING_LO )
|
||||
|
||||
#define H_SYNC_OFFSET_LO (unsigned)block[ 8 ]
|
||||
#define H_SYNC_WIDTH_LO (unsigned)block[ 9 ]
|
||||
|
||||
#define V_SYNC_OFFSET_LO UPPER_NIBBLE( (unsigned)block[ 10 ] )
|
||||
#define V_SYNC_WIDTH_LO LOWER_NIBBLE( (unsigned)block[ 10 ] )
|
||||
|
||||
#define V_SYNC_WIDTH_HI ((unsigned)block[ 11 ] & (1|2))
|
||||
#define V_SYNC_OFFSET_HI (((unsigned)block[ 11 ] & (4|8)) >> 2)
|
||||
|
||||
#define H_SYNC_WIDTH_HI (((unsigned)block[ 11 ] & (16|32)) >> 4)
|
||||
#define H_SYNC_OFFSET_HI (((unsigned)block[ 11 ] & (64|128)) >> 6)
|
||||
|
||||
#define V_SYNC_WIDTH COMBINE_HI_4LO( V_SYNC_WIDTH_HI, V_SYNC_WIDTH_LO )
|
||||
#define V_SYNC_OFFSET COMBINE_HI_4LO( V_SYNC_OFFSET_HI, V_SYNC_OFFSET_LO )
|
||||
|
||||
#define H_SYNC_WIDTH COMBINE_HI_4LO( H_SYNC_WIDTH_HI, H_SYNC_WIDTH_LO )
|
||||
#define H_SYNC_OFFSET COMBINE_HI_4LO( H_SYNC_OFFSET_HI, H_SYNC_OFFSET_LO )
|
||||
|
||||
#define H_SIZE_LO (unsigned)block[ 12 ]
|
||||
#define V_SIZE_LO (unsigned)block[ 13 ]
|
||||
|
||||
#define H_SIZE_HI UPPER_NIBBLE( (unsigned)block[ 14 ] )
|
||||
#define V_SIZE_HI LOWER_NIBBLE( (unsigned)block[ 14 ] )
|
||||
|
||||
#define H_SIZE COMBINE_HI_8LO( H_SIZE_HI, H_SIZE_LO )
|
||||
#define V_SIZE COMBINE_HI_8LO( V_SIZE_HI, V_SIZE_LO )
|
||||
|
||||
#define H_BORDER (unsigned)block[ 15 ]
|
||||
#define V_BORDER (unsigned)block[ 16 ]
|
||||
|
||||
#define FLAGS (unsigned)block[ 17 ]
|
||||
|
||||
#define INTERLACED (FLAGS&128)
|
||||
#define SYNC_TYPE (FLAGS&3<<3) /* bits 4,3 */
|
||||
#define SYNC_SEPARATE (3<<3)
|
||||
#define HSYNC_POSITIVE (FLAGS & 4)
|
||||
#define VSYNC_POSITIVE (FLAGS & 2)
|
||||
|
||||
#define V_MIN_RATE block[ 5 ]
|
||||
#define V_MAX_RATE block[ 6 ]
|
||||
#define H_MIN_RATE block[ 7 ]
|
||||
#define H_MAX_RATE block[ 8 ]
|
||||
#define MAX_PIXEL_CLOCK (((int)block[ 9 ]) * 10)
|
||||
#define GTF_SUPPORT block[10]
|
||||
|
||||
#define DPMS_ACTIVE_OFF (1 << 5)
|
||||
#define DPMS_SUSPEND (1 << 6)
|
||||
#define DPMS_STANDBY (1 << 7)
|
||||
|
||||
#endif /* __EDID_H__ */
|
||||
211
include/ehci.h
Normal file
211
include/ehci.h
Normal file
@@ -0,0 +1,211 @@
|
||||
/*-
|
||||
* Copyright (c) 2007-2008, Juniper Networks, Inc.
|
||||
* Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
|
||||
* All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2 of
|
||||
* the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef USB_EHCI_H
|
||||
#define USB_EHCI_H
|
||||
|
||||
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 5
|
||||
|
||||
/* (shifted) direction/type/recipient from the USB 2.0 spec, table 9.2 */
|
||||
#define DeviceRequest \
|
||||
((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8)
|
||||
|
||||
#define DeviceOutRequest \
|
||||
((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8)
|
||||
|
||||
#define InterfaceRequest \
|
||||
((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
|
||||
|
||||
#define EndpointRequest \
|
||||
((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
|
||||
|
||||
#define EndpointOutRequest \
|
||||
((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
|
||||
|
||||
/*
|
||||
* Register Space.
|
||||
*/
|
||||
struct ehci_hccr
|
||||
{
|
||||
uint32_t cr_capbase;
|
||||
#define HC_LENGTH(p) (((p) >> 0) & 0x00ff)
|
||||
#define HC_VERSION(p) (((p) >> 16) & 0xffff)
|
||||
uint32_t cr_hcsparams;
|
||||
#define HCS_PPC(p) ((p) & (1 << 4))
|
||||
#define HCS_INDICATOR(p) ((p) & (1 << 16)) /* Port indicators */
|
||||
#define HCS_N_PORTS(p) (((p) >> 0) & 0xf)
|
||||
uint32_t cr_hccparams;
|
||||
uint8_t cr_hcsp_portrt[8];
|
||||
} __attribute__ ((packed));
|
||||
|
||||
struct ehci_hcor
|
||||
{
|
||||
uint32_t or_usbcmd;
|
||||
#define CMD_PARK (1 << 11) /* enable "park" */
|
||||
#define CMD_PARK_CNT(c) (((c) >> 8) & 3) /* how many transfers to park */
|
||||
#define CMD_ASE (1 << 5) /* async schedule enable */
|
||||
#define CMD_LRESET (1 << 7) /* partial reset */
|
||||
#define CMD_IAAD (1 << 5) /* "doorbell" interrupt */
|
||||
#define CMD_PSE (1 << 4) /* periodic schedule enable */
|
||||
#define CMD_RESET (1 << 1) /* reset HC not bus */
|
||||
#define CMD_RUN (1 << 0) /* start/stop HC */
|
||||
uint32_t or_usbsts;
|
||||
#define STD_ASS (1 << 15)
|
||||
#define STS_PSSTAT (1 << 14)
|
||||
#define STS_RECL (1 << 13)
|
||||
#define STS_HALT (1 << 12)
|
||||
#define STS_IAA (1 << 5)
|
||||
#define STS_HSE (1 << 4)
|
||||
#define STS_FLR (1 << 3)
|
||||
#define STS_PCD (1 << 2)
|
||||
#define STS_USBERRINT (1 << 1)
|
||||
#define STS_USBINT (1 << 0)
|
||||
uint32_t or_usbintr;
|
||||
#define INTR_IAAE (1 << 5)
|
||||
#define INTR_HSEE (1 << 4)
|
||||
#define INTR_FLRE (1 << 3)
|
||||
#define INTR_PCDE (1 << 2)
|
||||
#define INTR_USBERRINTE (1 << 1)
|
||||
#define INTR_USBINTE (1 << 0)
|
||||
uint32_t or_frindex;
|
||||
uint32_t or_ctrldssegment;
|
||||
uint32_t or_periodiclistbase;
|
||||
uint32_t or_asynclistaddr;
|
||||
uint32_t _reserved_[9];
|
||||
uint32_t or_configflag;
|
||||
#define FLAG_CF (1 << 0) /* true: we'll support "high speed" */
|
||||
uint32_t or_portsc[CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS];
|
||||
uint32_t or_systune;
|
||||
} __attribute__ ((packed));
|
||||
|
||||
#define USBMODE 0x68 /* USB Device mode */
|
||||
#define USBMODE_SDIS (1 << 3) /* Stream disable */
|
||||
#define USBMODE_BE (1 << 2) /* BE/LE endiannes select */
|
||||
#define USBMODE_CM_HC (3 << 0) /* host controller mode */
|
||||
#define USBMODE_CM_IDLE (0 << 0) /* idle state */
|
||||
|
||||
/* Interface descriptor */
|
||||
struct usb_linux_interface_descriptor
|
||||
{
|
||||
unsigned char bLength;
|
||||
unsigned char bDescriptorType;
|
||||
unsigned char bInterfaceNumber;
|
||||
unsigned char bAlternateSetting;
|
||||
unsigned char bNumEndpoints;
|
||||
unsigned char bInterfaceClass;
|
||||
unsigned char bInterfaceSubClass;
|
||||
unsigned char bInterfaceProtocol;
|
||||
unsigned char iInterface;
|
||||
} __attribute__ ((packed));
|
||||
|
||||
/* Configuration descriptor information.. */
|
||||
struct usb_linux_config_descriptor
|
||||
{
|
||||
unsigned char bLength;
|
||||
unsigned char bDescriptorType;
|
||||
unsigned short wTotalLength;
|
||||
unsigned char bNumInterfaces;
|
||||
unsigned char bConfigurationValue;
|
||||
unsigned char iConfiguration;
|
||||
unsigned char bmAttributes;
|
||||
unsigned char MaxPower;
|
||||
} __attribute__ ((packed));
|
||||
|
||||
#if defined CONFIG_EHCI_DESC_BIG_ENDIAN
|
||||
#define ehci_readl(x) (*((volatile uint32_t *)(x)))
|
||||
#define ehci_writel(a, b) (*((volatile uint32_t *)(a)) = ((volatile uint32_t) b))
|
||||
#else
|
||||
#define ehci_readl(x) swpl((*((volatile uint32_t *)(x))))
|
||||
#define ehci_writel(a, b) (*((volatile uint32_t *)(a)) = swpl(((volatile uint32_t) b)))
|
||||
#endif
|
||||
|
||||
#if defined CONFIG_EHCI_MMIO_BIG_ENDIAN
|
||||
#define hc32_to_cpu(x) be32_to_cpu((x))
|
||||
#define cpu_to_hc32(x) cpu_to_be32((x))
|
||||
#else
|
||||
#define hc32_to_cpu(x) swpl((x))
|
||||
#define cpu_to_hc32(x) swpl((x))
|
||||
#endif
|
||||
|
||||
#define EHCI_PS_WKOC_E (1 << 22) /* RW wake on over current */
|
||||
#define EHCI_PS_WKDSCNNT_E (1 << 21) /* RW wake on disconnect */
|
||||
#define EHCI_PS_WKCNNT_E (1 << 20) /* RW wake on connect */
|
||||
#define EHCI_PS_PO (1 << 13) /* RW port owner */
|
||||
#define EHCI_PS_PP (1 << 12) /* RW,RO port power */
|
||||
#define EHCI_PS_LS (3 << 10) /* RO line status */
|
||||
#define EHCI_PS_PR (1 << 8) /* RW port reset */
|
||||
#define EHCI_PS_SUSP (1 << 7) /* RW suspend */
|
||||
#define EHCI_PS_FPR (1 << 6) /* RW force port resume */
|
||||
#define EHCI_PS_OCC (1 << 5) /* RWC over current change */
|
||||
#define EHCI_PS_OCA (1 << 4) /* RO over current active */
|
||||
#define EHCI_PS_PEC (1 << 3) /* RWC port enable change */
|
||||
#define EHCI_PS_PE (1 << 2) /* RW port enable */
|
||||
#define EHCI_PS_CSC (1 << 1) /* RWC connect status change */
|
||||
#define EHCI_PS_CS (1 << 0) /* RO connect status */
|
||||
#define EHCI_PS_CLEAR (EHCI_PS_OCC | EHCI_PS_PEC | EHCI_PS_CSC)
|
||||
|
||||
#define EHCI_PS_IS_LOWSPEED(x) (((x) & EHCI_PS_LS) == (1 << 10))
|
||||
|
||||
/*
|
||||
* Schedule Interface Space.
|
||||
*
|
||||
* IMPORTANT: Software must ensure that no interface data structure
|
||||
* reachable by the EHCI host controller spans a 4K page boundary!
|
||||
*
|
||||
* Periodic transfers (i.e. isochronous and interrupt transfers) are
|
||||
* not supported.
|
||||
*/
|
||||
|
||||
/* Queue Element Transfer Descriptor (qTD). */
|
||||
struct qTD
|
||||
{
|
||||
uint32_t qt_next;
|
||||
#define QT_NEXT_TERMINATE 1
|
||||
uint32_t qt_altnext;
|
||||
uint32_t qt_token;
|
||||
uint32_t qt_buffer[5];
|
||||
};
|
||||
|
||||
/* Queue Head (QH). */
|
||||
struct QH
|
||||
{
|
||||
uint32_t qh_link;
|
||||
#define QH_LINK_TERMINATE 1
|
||||
#define QH_LINK_TYPE_ITD 0
|
||||
#define QH_LINK_TYPE_QH 2
|
||||
#define QH_LINK_TYPE_SITD 4
|
||||
#define QH_LINK_TYPE_FSTN 6
|
||||
uint32_t qh_endpt1;
|
||||
uint32_t qh_endpt2;
|
||||
uint32_t qh_curtd;
|
||||
struct qTD qh_overlay;
|
||||
/*
|
||||
* Add dummy fill value to make the size of this struct
|
||||
* aligned to 32 bytes
|
||||
*/
|
||||
uint8_t fill[16];
|
||||
};
|
||||
|
||||
/* Low level init functions */
|
||||
int ehci_hcd_init(void);
|
||||
int ehci_hcd_stop(void);
|
||||
|
||||
#endif /* USB_EHCI_H */
|
||||
57
include/eth.h
Normal file
57
include/eth.h
Normal file
@@ -0,0 +1,57 @@
|
||||
/*
|
||||
* File: eth.h
|
||||
* Purpose: Definitions for Ethernet Frames.
|
||||
*
|
||||
* Modifications:
|
||||
*/
|
||||
|
||||
#ifndef _ETH_H
|
||||
#define _ETH_H
|
||||
|
||||
#include "bas_types.h"
|
||||
|
||||
/*******************************************************************/
|
||||
|
||||
/* Ethernet standard lengths in bytes*/
|
||||
#define ETH_ADDR_LEN (6)
|
||||
#define ETH_TYPE_LEN (2)
|
||||
#define ETH_CRC_LEN (4)
|
||||
#define ETH_MAX_DATA (1500)
|
||||
#define ETH_MIN_DATA (46)
|
||||
#define ETH_HDR_LEN (ETH_ADDR_LEN * 2 + ETH_TYPE_LEN)
|
||||
|
||||
/* Defined Ethernet Frame Types */
|
||||
#define ETH_FRM_IP (0x0800)
|
||||
#define ETH_FRM_ARP (0x0806)
|
||||
#define ETH_FRM_RARP (0x8035)
|
||||
#define ETH_FRM_TEST (0xA5A5)
|
||||
|
||||
/* Maximum and Minimum Ethernet Frame Sizes */
|
||||
#define ETH_MAX_FRM (ETH_HDR_LEN + ETH_MAX_DATA + ETH_CRC_LEN)
|
||||
#define ETH_MIN_FRM (ETH_HDR_LEN + ETH_MIN_DATA + ETH_CRC_LEN)
|
||||
#define ETH_MTU (ETH_HDR_LEN + ETH_MAX_DATA)
|
||||
|
||||
/* Ethernet Addresses */
|
||||
typedef uint8_t ETH_ADDR[ETH_ADDR_LEN];
|
||||
|
||||
/* 16-bit Ethernet Frame Type, ie. Protocol */
|
||||
typedef uint16_t ETH_FRM_TYPE;
|
||||
|
||||
/* Ethernet Frame Header definition */
|
||||
typedef struct
|
||||
{
|
||||
ETH_ADDR dest;
|
||||
ETH_ADDR src;
|
||||
ETH_FRM_TYPE type;
|
||||
} ETH_HDR;
|
||||
|
||||
/* Ethernet Frame definition */
|
||||
typedef struct
|
||||
{
|
||||
ETH_HDR head;
|
||||
uint8_t* data;
|
||||
} ETH_FRAME;
|
||||
|
||||
/*******************************************************************/
|
||||
|
||||
#endif /* _ETH_H */
|
||||
8
include/exceptions.h
Normal file
8
include/exceptions.h
Normal file
@@ -0,0 +1,8 @@
|
||||
#ifndef _EXCEPTIONS_H_
|
||||
#define _EXCEPTIONS_H_
|
||||
|
||||
#include <bas_types.h>
|
||||
|
||||
extern uint32_t set_ipl(uint32_t ipl);
|
||||
|
||||
#endif /* _EXCEPTIONS_H_ */
|
||||
569
include/fb.h
Normal file
569
include/fb.h
Normal file
@@ -0,0 +1,569 @@
|
||||
#ifndef _FB_H
|
||||
#define _FB_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/* Definitions of frame buffers */
|
||||
|
||||
#define FB_MAJOR 29
|
||||
#define FB_MAX 32 /* sufficient for now */
|
||||
|
||||
/* ioctls 0x46 is 'F' */
|
||||
#define FBIOGET_VSCREENINFO 0x4600
|
||||
#define FBIOPUT_VSCREENINFO 0x4601
|
||||
#define FBIOGET_FSCREENINFO 0x4602
|
||||
#define FBIOPAN_DISPLAY 0x4606
|
||||
#define FBIOBLANK 0x4611 /* arg: 0 or vesa level + 1 */
|
||||
#define FBIO_ALLOC 0x4613
|
||||
#define FBIO_FREE 0x4614
|
||||
|
||||
/* picture format */
|
||||
#define PICT_FORMAT(bpp, type, a, r, g, b) (((bpp) << 24) | ((type) << 16) | ((a) << 12) | ((r) << 8) | ((g) << 4) | ((b)))
|
||||
|
||||
/* gray/color formats use a visual index instead of argb */
|
||||
#define PICT_VISFORMAT(bpp, type, vi) (((bpp) << 24) | ((type) << 16) | ((vi)))
|
||||
#define PICT_FORMAT_BPP(f) (((f) >> 24) )
|
||||
#define PICT_FORMAT_TYPE(f) (((f) >> 16) & 0xff)
|
||||
#define PICT_FORMAT_A(f) (((f) >> 12) & 0x0f)
|
||||
#define PICT_FORMAT_R(f) (((f) >> 8) & 0x0f)
|
||||
#define PICT_FORMAT_G(f) (((f) >> 4) & 0x0f)
|
||||
#define PICT_FORMAT_B(f) (((f) ) & 0x0f)
|
||||
#define PICT_FORMAT_RGB(f) (((f) ) & 0xfff)
|
||||
#define PICT_FORMAT_VIS(f) (((f) ) & 0xffff)
|
||||
|
||||
#define PICT_TYPE_OTHER 0
|
||||
#define PICT_TYPE_A 1
|
||||
#define PICT_TYPE_ARGB 2
|
||||
#define PICT_TYPE_ABGR 3
|
||||
#define PICT_TYPE_COLOR 4
|
||||
#define PICT_TYPE_GRAY 5
|
||||
#define PICT_FORMAT_COLOR(f) (PICT_FORMAT_TYPE(f) & 2)
|
||||
|
||||
/* 32bpp formats */
|
||||
#define PICT_a8r8g8b8 PICT_FORMAT(32, PICT_TYPE_ARGB, 8, 8, 8, 8)
|
||||
#define PICT_x8r8g8b8 PICT_FORMAT(32, PICT_TYPE_ARGB, 0, 8, 8, 8)
|
||||
#define PICT_a8b8g8r8 PICT_FORMAT(32, PICT_TYPE_ABGR, 8, 8, 8, 8)
|
||||
#define PICT_x8b8g8r8 PICT_FORMAT(32, PICT_TYPE_ABGR, 0, 8, 8, 8)
|
||||
|
||||
/* 24bpp formats */
|
||||
#define PICT_r8g8b8 PICT_FORMAT(24, PICT_TYPE_ARGB, 0, 8, 8, 8)
|
||||
#define PICT_b8g8r8 PICT_FORMAT(24, PICT_TYPE_ABGR, 0, 8, 8, 8)
|
||||
|
||||
/* 16bpp formats */
|
||||
#define PICT_r5g6b5 PICT_FORMAT(16, PICT_TYPE_ARGB, 0, 5, 6, 5)
|
||||
#define PICT_b5g6r5 PICT_FORMAT(16, PICT_TYPE_ABGR, 0, 5, 6, 5)
|
||||
#define PICT_a1r5g5b5 PICT_FORMAT(16, PICT_TYPE_ARGB, 1, 5, 5, 5)
|
||||
#define PICT_x1r5g5b5 PICT_FORMAT(16, PICT_TYPE_ARGB, 0, 5, 5, 5)
|
||||
#define PICT_a1b5g5r5 PICT_FORMAT(16, PICT_TYPE_ABGR, 1, 5, 5, 5)
|
||||
#define PICT_x1b5g5r5 PICT_FORMAT(16, PICT_TYPE_ABGR, 0, 5, 5, 5)
|
||||
#define PICT_a4r4g4b4 PICT_FORMAT(16, PICT_TYPE_ARGB, 4, 4, 4, 4)
|
||||
#define PICT_x4r4g4b4 PICT_FORMAT(16, PICT_TYPE_ARGB, 4, 4, 4, 4)
|
||||
#define PICT_a4b4g4r4 PICT_FORMAT(16, PICT_TYPE_ARGB, 4, 4, 4, 4)
|
||||
#define PICT_x4b4g4r4 PICT_FORMAT(16, PICT_TYPE_ARGB, 4, 4, 4, 4)
|
||||
|
||||
/* 8bpp formats */
|
||||
#define PICT_a8 PICT_FORMAT(8, PICT_TYPE_A, 8, 0, 0, 0)
|
||||
#define PICT_r3g3b2 PICT_FORMAT(8, PICT_TYPE_ARGB, 0, 3, 3, 2)
|
||||
#define PICT_b2g3r3 PICT_FORMAT(8, PICT_TYPE_ABGR, 0, 3, 3, 2)
|
||||
#define PICT_a2r2g2b2 PICT_FORMAT(8, PICT_TYPE_ARGB, 2, 2, 2, 2)
|
||||
#define PICT_a2b2g2r2 PICT_FORMAT(8, PICT_TYPE_ABGR, 2, 2, 2, 2)
|
||||
#define PICT_c8 PICT_FORMAT(8, PICT_TYPE_COLOR, 0, 0, 0, 0)
|
||||
#define PICT_g8 PICT_FORMAT(8, PICT_TYPE_GRAY, 0, 0, 0, 0)
|
||||
|
||||
/* fVDI */
|
||||
#define MODE_EMUL_MONO_FLAG 1
|
||||
#define MODE_VESA_FLAG 2 /* for modedb.c */
|
||||
|
||||
struct mode_option
|
||||
{
|
||||
short used; /* Whether the mode option was used or not. */
|
||||
short width;
|
||||
short height;
|
||||
short bpp;
|
||||
short freq;
|
||||
short flags;
|
||||
};
|
||||
|
||||
extern struct mode_option resolution; /* fVDI */
|
||||
|
||||
#define FB_TYPE_PACKED_PIXELS 0 /* Packed Pixels */
|
||||
#define FB_TYPE_PLANES 1 /* Non interleaved planes */
|
||||
#define FB_TYPE_INTERLEAVED_PLANES 2 /* Interleaved planes */
|
||||
#define FB_TYPE_TEXT 3 /* Text/attributes */
|
||||
#define FB_TYPE_VGA_PLANES 4 /* EGA/VGA planes */
|
||||
|
||||
#define FB_AUX_TEXT_MDA 0 /* Monochrome text */
|
||||
#define FB_AUX_TEXT_CGA 1 /* CGA/EGA/VGA Color text */
|
||||
#define FB_AUX_TEXT_S3_MMIO 2 /* S3 MMIO fasttext */
|
||||
#define FB_AUX_TEXT_MGA_STEP16 3 /* MGA Millenium I: text, attr, 14 reserved bytes */
|
||||
#define FB_AUX_TEXT_MGA_STEP8 4 /* other MGAs: text, attr, 6 reserved bytes */
|
||||
|
||||
#define FB_AUX_VGA_PLANES_VGA4 0 /* 16 color planes (EGA/VGA) */
|
||||
#define FB_AUX_VGA_PLANES_CFB4 1 /* CFB4 in planes (VGA) */
|
||||
#define FB_AUX_VGA_PLANES_CFB8 2 /* CFB8 in planes (VGA) */
|
||||
|
||||
#define FB_VISUAL_MONO01 0 /* Monochr. 1=Black 0=White */
|
||||
#define FB_VISUAL_MONO10 1 /* Monochr. 1=White 0=Black */
|
||||
#define FB_VISUAL_TRUECOLOR 2 /* True color */
|
||||
#define FB_VISUAL_PSEUDOCOLOR 3 /* Pseudo color (like atari) */
|
||||
#define FB_VISUAL_DIRECTCOLOR 4 /* Direct color */
|
||||
#define FB_VISUAL_STATIC_PSEUDOCOLOR 5 /* Pseudo color readonly */
|
||||
|
||||
#define FB_ACCEL_NONE 0 /* no hardware accelerator */
|
||||
#define FB_ACCEL_ATARIBLITT 1 /* Atari Blitter */
|
||||
#define FB_ACCEL_AMIGABLITT 2 /* Amiga Blitter */
|
||||
#define FB_ACCEL_S3_TRIO64 3 /* Cybervision64 (S3 Trio64) */
|
||||
#define FB_ACCEL_NCR_77C32BLT 4 /* RetinaZ3 (NCR 77C32BLT) */
|
||||
#define FB_ACCEL_S3_VIRGE 5 /* Cybervision64/3D (S3 ViRGE) */
|
||||
#define FB_ACCEL_ATI_MACH64GX 6 /* ATI Mach 64GX family */
|
||||
#define FB_ACCEL_DEC_TGA 7 /* DEC 21030 TGA */
|
||||
#define FB_ACCEL_ATI_MACH64CT 8 /* ATI Mach 64CT family */
|
||||
#define FB_ACCEL_ATI_MACH64VT 9 /* ATI Mach 64CT family VT class */
|
||||
#define FB_ACCEL_ATI_MACH64GT 10 /* ATI Mach 64CT family GT class */
|
||||
#define FB_ACCEL_SUN_CREATOR 11 /* Sun Creator/Creator3D */
|
||||
#define FB_ACCEL_SUN_CGSIX 12 /* Sun cg6 */
|
||||
#define FB_ACCEL_SUN_LEO 13 /* Sun leo/zx */
|
||||
#define FB_ACCEL_IMS_TWINTURBO 14 /* IMS Twin Turbo */
|
||||
#define FB_ACCEL_3DLABS_PERMEDIA2 15 /* 3Dlabs Permedia 2 */
|
||||
#define FB_ACCEL_MATROX_MGA2064W 16 /* Matrox MGA2064W (Millenium) */
|
||||
#define FB_ACCEL_MATROX_MGA1064SG 17 /* Matrox MGA1064SG (Mystique) */
|
||||
#define FB_ACCEL_MATROX_MGA2164W 18 /* Matrox MGA2164W (Millenium II) */
|
||||
#define FB_ACCEL_MATROX_MGA2164W_AGP 19 /* Matrox MGA2164W (Millenium II) */
|
||||
#define FB_ACCEL_MATROX_MGAG100 20 /* Matrox G100 (Productiva G100) */
|
||||
#define FB_ACCEL_MATROX_MGAG200 21 /* Matrox G200 (Myst, Mill, ...) */
|
||||
#define FB_ACCEL_SUN_CG14 22 /* Sun cgfourteen */
|
||||
#define FB_ACCEL_SUN_BWTWO 23 /* Sun bwtwo */
|
||||
#define FB_ACCEL_SUN_CGTHREE 24 /* Sun cgthree */
|
||||
#define FB_ACCEL_SUN_TCX 25 /* Sun tcx */
|
||||
#define FB_ACCEL_MATROX_MGAG400 26 /* Matrox G400 */
|
||||
#define FB_ACCEL_NV3 27 /* nVidia RIVA 128 */
|
||||
#define FB_ACCEL_NV4 28 /* nVidia RIVA TNT */
|
||||
#define FB_ACCEL_NV5 29 /* nVidia RIVA TNT2 */
|
||||
#define FB_ACCEL_CT_6555x 30 /* C&T 6555x */
|
||||
#define FB_ACCEL_3DFX_BANSHEE 31 /* 3Dfx Banshee */
|
||||
#define FB_ACCEL_ATI_RAGE128 32 /* ATI Rage128 family */
|
||||
#define FB_ACCEL_IGS_CYBER2000 33 /* CyberPro 2000 */
|
||||
#define FB_ACCEL_IGS_CYBER2010 34 /* CyberPro 2010 */
|
||||
#define FB_ACCEL_IGS_CYBER5000 35 /* CyberPro 5000 */
|
||||
#define FB_ACCEL_SIS_GLAMOUR 36 /* SiS 300/630/540 */
|
||||
#define FB_ACCEL_3DLABS_PERMEDIA3 37 /* 3Dlabs Permedia 3 */
|
||||
#define FB_ACCEL_ATI_RADEON 38 /* ATI Radeon family */
|
||||
#define FB_ACCEL_I810 39 /* Intel 810/815 */
|
||||
#define FB_ACCEL_SIS_GLAMOUR_2 40 /* SiS 315, 650, 740 */
|
||||
#define FB_ACCEL_SIS_XABRE 41 /* SiS 330 ("Xabre") */
|
||||
#define FB_ACCEL_I830 42 /* Intel 830M/845G/85x/865G */
|
||||
#define FB_ACCEL_NV_10 43 /* nVidia Arch 10 */
|
||||
#define FB_ACCEL_NV_20 44 /* nVidia Arch 20 */
|
||||
#define FB_ACCEL_NV_30 45 /* nVidia Arch 30 */
|
||||
#define FB_ACCEL_NV_40 46 /* nVidia Arch 40 */
|
||||
#define FB_ACCEL_NEOMAGIC_NM2070 90 /* NeoMagic NM2070 */
|
||||
#define FB_ACCEL_NEOMAGIC_NM2090 91 /* NeoMagic NM2090 */
|
||||
#define FB_ACCEL_NEOMAGIC_NM2093 92 /* NeoMagic NM2093 */
|
||||
#define FB_ACCEL_NEOMAGIC_NM2097 93 /* NeoMagic NM2097 */
|
||||
#define FB_ACCEL_NEOMAGIC_NM2160 94 /* NeoMagic NM2160 */
|
||||
#define FB_ACCEL_NEOMAGIC_NM2200 95 /* NeoMagic NM2200 */
|
||||
#define FB_ACCEL_NEOMAGIC_NM2230 96 /* NeoMagic NM2230 */
|
||||
#define FB_ACCEL_NEOMAGIC_NM2360 97 /* NeoMagic NM2360 */
|
||||
#define FB_ACCEL_NEOMAGIC_NM2380 98 /* NeoMagic NM2380 */
|
||||
|
||||
#define FB_ACCEL_SAVAGE4 0x80 /* S3 Savage4 */
|
||||
#define FB_ACCEL_SAVAGE3D 0x81 /* S3 Savage3D */
|
||||
#define FB_ACCEL_SAVAGE3D_MV 0x82 /* S3 Savage3D-MV */
|
||||
#define FB_ACCEL_SAVAGE2000 0x83 /* S3 Savage2000 */
|
||||
#define FB_ACCEL_SAVAGE_MX_MV 0x84 /* S3 Savage/MX-MV */
|
||||
#define FB_ACCEL_SAVAGE_MX 0x85 /* S3 Savage/MX */
|
||||
#define FB_ACCEL_SAVAGE_IX_MV 0x86 /* S3 Savage/IX-MV */
|
||||
#define FB_ACCEL_SAVAGE_IX 0x87 /* S3 Savage/IX */
|
||||
#define FB_ACCEL_PROSAVAGE_PM 0x88 /* S3 ProSavage PM133 */
|
||||
#define FB_ACCEL_PROSAVAGE_KM 0x89 /* S3 ProSavage KM133 */
|
||||
#define FB_ACCEL_S3TWISTER_P 0x8a /* S3 Twister */
|
||||
#define FB_ACCEL_S3TWISTER_K 0x8b /* S3 TwisterK */
|
||||
#define FB_ACCEL_SUPERSAVAGE 0x8c /* S3 Supersavage */
|
||||
#define FB_ACCEL_PROSAVAGE_DDR 0x8d /* S3 ProSavage DDR */
|
||||
#define FB_ACCEL_PROSAVAGE_DDRK 0x8e /* S3 ProSavage DDR-K */
|
||||
|
||||
struct fb_fix_screeninfo
|
||||
{
|
||||
char id[16]; /* identification string eg "TT Builtin" */
|
||||
uint32_t smem_start; /* Start of frame buffer mem */
|
||||
/* (physical address) */
|
||||
uint32_t smem_len; /* Length of frame buffer mem */
|
||||
uint32_t type; /* see FB_TYPE_* */
|
||||
uint32_t type_aux; /* Interleave for interleaved Planes */
|
||||
uint32_t visual; /* see FB_VISUAL_* */
|
||||
uint16_t xpanstep; /* zero if no hardware panning */
|
||||
uint16_t ypanstep; /* zero if no hardware panning */
|
||||
uint16_t ywrapstep; /* zero if no hardware ywrap */
|
||||
uint32_t line_length; /* length of a line in bytes */
|
||||
uint32_t mmio_start; /* Start of Memory Mapped I/O */
|
||||
/* (physical address) */
|
||||
uint32_t mmio_len; /* Length of Memory Mapped I/O */
|
||||
uint32_t accel; /* Indicate to driver which */
|
||||
/* specific chip/card we have */
|
||||
uint16_t reserved[3]; /* Reserved for future compatibility */
|
||||
};
|
||||
|
||||
/* Interpretation of offset for color fields: All offsets are from the right,
|
||||
* inside a "pixel" value, which is exactly 'bits_per_pixel' wide (means: you
|
||||
* can use the offset as right argument to <<). A pixel afterwards is a bit
|
||||
* stream and is written to video memory as that unmodified. This implies
|
||||
* big-endian byte order if bits_per_pixel is greater than 8.
|
||||
*/
|
||||
struct fb_bitfield
|
||||
{
|
||||
uint32_t offset; /* beginning of bitfield */
|
||||
uint32_t length; /* length of bitfield */
|
||||
uint32_t msb_right; /* != 0 : Most significant bit is */
|
||||
/* right */
|
||||
};
|
||||
|
||||
#define FB_NONSTD_HAM 1 /* Hold-And-Modify (HAM) */
|
||||
|
||||
#define FB_ACTIVATE_NOW 0 /* set values immediately (or vbl)*/
|
||||
#define FB_ACTIVATE_NXTOPEN 1 /* activate on next open */
|
||||
#define FB_ACTIVATE_TEST 2 /* don't set, round up impossible */
|
||||
#define FB_ACTIVATE_MASK 15
|
||||
/* values */
|
||||
#define FB_ACTIVATE_VBL 16 /* activate values on next vbl */
|
||||
#define FB_CHANGE_CMAP_VBL 32 /* change colormap on vbl */
|
||||
#define FB_ACTIVATE_ALL 64 /* change all VCs on this fb */
|
||||
#define FB_ACTIVATE_FORCE 128 /* force apply even when no change*/
|
||||
#define FB_ACTIVATE_INV_MODE 256 /* invalidate videomode */
|
||||
|
||||
#define FB_ACCELF_TEXT 1 /* (OBSOLETE) see fb_info.flags and vc_mode */
|
||||
|
||||
#define FB_SYNC_HOR_HIGH_ACT 1 /* horizontal sync high active */
|
||||
#define FB_SYNC_VERT_HIGH_ACT 2 /* vertical sync high active */
|
||||
#define FB_SYNC_EXT 4 /* external sync */
|
||||
#define FB_SYNC_COMP_HIGH_ACT 8 /* composite sync high active */
|
||||
#define FB_SYNC_BROADCAST 16 /* broadcast video timings */
|
||||
/* vtotal = 144d/288n/576i => PAL */
|
||||
/* vtotal = 121d/242n/484i => NTSC */
|
||||
#define FB_SYNC_ON_GREEN 32 /* sync on green */
|
||||
|
||||
#define FB_VMODE_NONINTERLACED 0 /* non interlaced */
|
||||
#define FB_VMODE_INTERLACED 1 /* interlaced */
|
||||
#define FB_VMODE_DOUBLE 2 /* double scan */
|
||||
#define FB_VMODE_MASK 255
|
||||
|
||||
#define FB_VMODE_YWRAP 256 /* ywrap instead of panning */
|
||||
#define FB_VMODE_SMOOTH_XPAN 512 /* smooth xpan possible (internally used) */
|
||||
#define FB_VMODE_CONUPDATE 512 /* don't update x/yoffset */
|
||||
|
||||
#define PICOS2KHZ(a) (1000000000UL / (a))
|
||||
#define KHZ2PICOS(a) (1000000000UL / (a))
|
||||
|
||||
struct fb_var_screeninfo
|
||||
{
|
||||
uint32_t xres; /* visible resolution */
|
||||
uint32_t yres;
|
||||
uint32_t xres_virtual; /* virtual resolution */
|
||||
uint32_t yres_virtual;
|
||||
uint32_t xoffset; /* offset from virtual to visible */
|
||||
uint32_t yoffset; /* resolution */
|
||||
|
||||
uint32_t bits_per_pixel; /* guess what */
|
||||
uint32_t grayscale; /* != 0 Graylevels instead of colors */
|
||||
|
||||
struct fb_bitfield red; /* bitfield in fb mem if true color, */
|
||||
struct fb_bitfield green; /* else only length is significant */
|
||||
struct fb_bitfield blue;
|
||||
struct fb_bitfield transp; /* transparency */
|
||||
|
||||
uint32_t nonstd; /* != 0 Non standard pixel format */
|
||||
|
||||
uint32_t activate; /* see FB_ACTIVATE_* */
|
||||
|
||||
uint32_t height; /* height of picture in mm */
|
||||
uint32_t width; /* width of picture in mm */
|
||||
|
||||
uint32_t accel_flags; /* (OBSOLETE) see fb_info.flags */
|
||||
|
||||
/* Timing: All values in pixclocks, except pixclock (of course) */
|
||||
uint32_t pixclock; /* pixel clock in ps (pico seconds) */
|
||||
uint32_t left_margin; /* time from sync to picture */
|
||||
uint32_t right_margin; /* time from picture to sync */
|
||||
uint32_t upper_margin; /* time from sync to picture */
|
||||
uint32_t lower_margin;
|
||||
uint32_t hsync_len; /* length of horizontal sync */
|
||||
uint32_t vsync_len; /* length of vertical sync */
|
||||
uint32_t sync; /* see FB_SYNC_* */
|
||||
uint32_t vmode; /* see FB_VMODE_* */
|
||||
uint32_t rotate; /* angle we rotate counter clockwise */
|
||||
uint32_t refresh;
|
||||
uint32_t reserved[4]; /* Reserved for future compatibility */
|
||||
};
|
||||
|
||||
/* VESA Blanking Levels */
|
||||
#define VESA_NO_BLANKING 0
|
||||
#define VESA_VSYNC_SUSPEND 1
|
||||
#define VESA_HSYNC_SUSPEND 2
|
||||
#define VESA_POWERDOWN 3
|
||||
|
||||
enum
|
||||
{
|
||||
/* screen: unblanked, hsync: on, vsync: on */
|
||||
FB_BLANK_UNBLANK = VESA_NO_BLANKING,
|
||||
/* screen: blanked, hsync: on, vsync: on */
|
||||
FB_BLANK_NORMAL = VESA_NO_BLANKING + 1,
|
||||
/* screen: blanked, hsync: on, vsync: off */
|
||||
FB_BLANK_VSYNC_SUSPEND = VESA_VSYNC_SUSPEND + 1,
|
||||
/* screen: blanked, hsync: off, vsync: on */
|
||||
FB_BLANK_HSYNC_SUSPEND = VESA_HSYNC_SUSPEND + 1,
|
||||
/* screen: blanked, hsync: off, vsync: off */
|
||||
FB_BLANK_POWERDOWN = VESA_POWERDOWN + 1
|
||||
};
|
||||
|
||||
#define FB_VBLANK_VBLANKING 0x001 /* currently in a vertical blank */
|
||||
#define FB_VBLANK_HBLANKING 0x002 /* currently in a horizontal blank */
|
||||
#define FB_VBLANK_HAVE_VBLANK 0x004 /* vertical blanks can be detected */
|
||||
#define FB_VBLANK_HAVE_HBLANK 0x008 /* horizontal blanks can be detected */
|
||||
#define FB_VBLANK_HAVE_COUNT 0x010 /* global retrace counter is available */
|
||||
#define FB_VBLANK_HAVE_VCOUNT 0x020 /* the vcount field is valid */
|
||||
#define FB_VBLANK_HAVE_HCOUNT 0x040 /* the hcount field is valid */
|
||||
#define FB_VBLANK_VSYNCING 0x080 /* currently in a vsync */
|
||||
#define FB_VBLANK_HAVE_VSYNC 0x100 /* verical syncs can be detected */
|
||||
|
||||
struct fb_vblank
|
||||
{
|
||||
uint32_t flags; /* FB_VBLANK flags */
|
||||
uint32_t count; /* counter of retraces since boot */
|
||||
uint32_t vcount; /* current scanline position */
|
||||
uint32_t hcount; /* current scandot position */
|
||||
uint32_t reserved[4]; /* reserved for future compatibility */
|
||||
};
|
||||
|
||||
struct vm_area_struct;
|
||||
struct fb_info;
|
||||
struct device;
|
||||
struct file;
|
||||
|
||||
/* Definitions below are used in the parsed monitor specs */
|
||||
#define FB_DPMS_ACTIVE_OFF 1
|
||||
#define FB_DPMS_SUSPEND 2
|
||||
#define FB_DPMS_STANDBY 4
|
||||
|
||||
#define FB_DISP_DDI 1
|
||||
#define FB_DISP_ANA_700_300 2
|
||||
#define FB_DISP_ANA_714_286 4
|
||||
#define FB_DISP_ANA_1000_400 8
|
||||
#define FB_DISP_ANA_700_000 16
|
||||
|
||||
#define FB_DISP_MONO 32
|
||||
#define FB_DISP_RGB 64
|
||||
#define FB_DISP_MULTI 128
|
||||
#define FB_DISP_UNKNOWN 256
|
||||
|
||||
#define FB_SIGNAL_NONE 0
|
||||
#define FB_SIGNAL_BLANK_BLANK 1
|
||||
#define FB_SIGNAL_SEPARATE 2
|
||||
#define FB_SIGNAL_COMPOSITE 4
|
||||
#define FB_SIGNAL_SYNC_ON_GREEN 8
|
||||
#define FB_SIGNAL_SERRATION_ON 16
|
||||
|
||||
#define FB_MISC_PRIM_COLOR 1
|
||||
#define FB_MISC_1ST_DETAIL 2 /* First Detailed Timing is preferred */
|
||||
|
||||
struct fb_chroma
|
||||
{
|
||||
uint32_t redx; /* in fraction of 1024 */
|
||||
uint32_t greenx;
|
||||
uint32_t bluex;
|
||||
uint32_t whitex;
|
||||
uint32_t redy;
|
||||
uint32_t greeny;
|
||||
uint32_t bluey;
|
||||
uint32_t whitey;
|
||||
};
|
||||
|
||||
struct fb_monspecs
|
||||
{
|
||||
struct fb_chroma chroma;
|
||||
struct fb_videomode *modedb; /* mode database */
|
||||
uint8_t manufacturer[4]; /* Manufacturer */
|
||||
uint8_t monitor[14]; /* Monitor String */
|
||||
uint8_t serial_no[14]; /* Serial Number */
|
||||
uint8_t ascii[14]; /* ? */
|
||||
uint32_t modedb_len; /* mode database length */
|
||||
uint32_t model; /* Monitor Model */
|
||||
uint32_t serial; /* Serial Number - Integer */
|
||||
uint32_t year; /* Year manufactured */
|
||||
uint32_t week; /* Week Manufactured */
|
||||
uint32_t hfmin; /* hfreq lower limit (Hz) */
|
||||
uint32_t hfmax; /* hfreq upper limit (Hz) */
|
||||
uint32_t dclkmin; /* pixelclock lower limit (Hz) */
|
||||
uint32_t dclkmax; /* pixelclock upper limit (Hz) */
|
||||
uint16_t input; /* display type - see FB_DISP_* */
|
||||
uint16_t dpms; /* DPMS support - see FB_DPMS_ */
|
||||
uint16_t signal; /* Signal Type - see FB_SIGNAL_* */
|
||||
uint16_t vfmin; /* vfreq lower limit (Hz) */
|
||||
uint16_t vfmax; /* vfreq upper limit (Hz) */
|
||||
uint16_t gamma; /* Gamma - in fractions of 100 */
|
||||
uint16_t gtf : 1; /* supports GTF */
|
||||
uint16_t misc; /* Misc flags - see FB_MISC_* */
|
||||
uint8_t version; /* EDID version... */
|
||||
uint8_t revision; /* ...and revision */
|
||||
uint8_t max_x; /* Maximum horizontal size (cm) */
|
||||
uint8_t max_y; /* Maximum vertical size (cm) */
|
||||
};
|
||||
|
||||
struct fb_ops
|
||||
{
|
||||
/* checks var and eventually tweaks if to something supported,
|
||||
* DO NOT MODIFY PAR */
|
||||
int32_t (*fb_check_var)(struct fb_var_screeninfo *var, struct fb_info *info);
|
||||
|
||||
/* set the video mode according to info->var */
|
||||
int32_t (*fb_set_par)(struct fb_info *info);
|
||||
|
||||
/* set color register */
|
||||
int32_t (*fb_setcolreg)(uint32_t regno, uint32_t red, uint32_t green,
|
||||
uint32_t blue, uint32_t transp, struct fb_info *info);
|
||||
|
||||
/* pan display */
|
||||
int32_t (*fb_pan_display)(struct fb_var_screeninfo *var, struct fb_info *info);
|
||||
|
||||
/* blank display */
|
||||
int32_t (*fb_blank)(int32_t blank, struct fb_info *info);
|
||||
|
||||
/* wait for blit idle */
|
||||
int32_t (*fb_sync)(struct fb_info *info);
|
||||
|
||||
/* perform fb specific ioctl */
|
||||
int32_t (*fb_ioctl)(uint32_t cmd, uint32_t arg, struct fb_info *info);
|
||||
|
||||
/*
|
||||
* Build the modedb for head 1 (head 2 will come later), check panel infos
|
||||
* from either BIOS or EDID, and pick up the default mode
|
||||
*/
|
||||
void (*fb_check_modes)(struct fb_info *info, struct mode_option *resolution);
|
||||
|
||||
/* Accel functions */
|
||||
#define DEGREES_0 0
|
||||
#define DEGREES_90 1
|
||||
#define DEGREES_180 2
|
||||
#define DEGREES_270 3
|
||||
#define OMIT_LAST 1
|
||||
void (*SetupForSolidFill)(struct fb_info *info, int32_t color, int32_t rop, uint32_t planemask);
|
||||
void (*SubsequentSolidFillRect)(struct fb_info *info, int32_t x, int32_t y, int32_t w, int32_t h);
|
||||
void (*SetupForSolidLine)(struct fb_info *info, int32_t color, int32_t rop, uint32_t planemask);
|
||||
void (*SubsequentSolidHorVertLine)(struct fb_info *info, int32_t x, int32_t y, int32_t len, int32_t dir);
|
||||
void (*SubsequentSolidTwoPointLine)(struct fb_info *info, int32_t xa, int32_t ya, int32_t xb, int32_t yb, int32_t flags);
|
||||
void (*SetupForDashedLine)(struct fb_info *info, int32_t fg, int32_t bg, int32_t rop, uint32_t planemask, int32_t length, uint8_t *pattern);
|
||||
void (*SubsequentDashedTwoPointLine)(struct fb_info *info, int32_t xa, int32_t ya, int32_t xb, int32_t yb, int32_t flags, int32_t phase);
|
||||
void (*SetupForScreenToScreenCopy)(struct fb_info *info, int32_t xdir, int32_t ydir, int32_t rop, uint32_t planemask, int32_t trans_color);
|
||||
void (*SubsequentScreenToScreenCopy)(struct fb_info *info, int32_t xa, int32_t ya, int32_t xb, int32_t yb, int32_t w, int32_t h);
|
||||
void (*ScreenToScreenCopy)(struct fb_info *info, int32_t xa, int32_t ya, int32_t xb, int32_t yb, int32_t w, int32_t h, int32_t rop);
|
||||
void (*SetupForMono8x8PatternFill)(struct fb_info *info, int32_t patternx, int32_t patterny, int32_t fg, int32_t bg, int32_t rop, uint32_t planemask);
|
||||
void (*SubsequentMono8x8PatternFillRect)(struct fb_info *info, int32_t patternx, int32_t patterny, int32_t x, int32_t y, int32_t w, int32_t h);
|
||||
void (*SetupForScanlineCPUToScreenColorExpandFill)(struct fb_info *info, int32_t fg, int32_t bg, int32_t rop, uint32_t planemask);
|
||||
void (*SubsequentScanlineCPUToScreenColorExpandFill)(struct fb_info *info, int32_t x, int32_t y, int32_t w, int32_t h, int32_t skipleft);
|
||||
void (*SubsequentScanline)(struct fb_info *info, uint32_t *buf);
|
||||
void (*SetupForScanlineImageWrite)(struct fb_info *info, int32_t rop, uint32_t planemask, int32_t trans_color, int32_t bpp);
|
||||
void (*SubsequentScanlineImageWriteRect)(struct fb_info *info, int32_t x, int32_t y, int32_t w, int32_t h, int32_t skipleft);
|
||||
void (*SetClippingRectangle)(struct fb_info *info, int32_t xa, int32_t ya, int32_t xb, int32_t yb);
|
||||
void (*DisableClipping)(struct fb_info *info);
|
||||
int (*SetupForCPUToScreenAlphaTexture)(struct fb_info *info,
|
||||
int32_t op, uint16_t red, uint16_t green, uint16_t blue, uint16_t alpha,
|
||||
uint32_t maskFormat, uint32_t dstFormat, uint8_t *alphaPtr, int32_t alphaPitch,
|
||||
int32_t width, int32_t height, int32_t flags);
|
||||
int32_t (*SetupForCPUToScreenTexture)(struct fb_info *info, int32_t op, uint32_t srcFormat, uint32_t dstFormat, uint8_t *texPtr, int32_t texPitch, int32_t width, int32_t height, int32_t flags);
|
||||
void (*SubsequentCPUToScreenTexture)(struct fb_info *info, int32_t dstx, int32_t dsty, int32_t srcx, int32_t srcy, int32_t width, int32_t height);
|
||||
/* Cursor functions */
|
||||
void (*SetCursorColors)(struct fb_info *info, int32_t bg, int32_t fg);
|
||||
void (*SetCursorPosition)(struct fb_info *info, int32_t x, int32_t y);
|
||||
void (*LoadCursorImage)(struct fb_info *info, uint16_t *mask, uint16_t *data, int32_t zoom);
|
||||
void (*HideCursor)(struct fb_info *info);
|
||||
void (*ShowCursor)(struct fb_info *info);
|
||||
long (*CursorInit)(struct fb_info *info);
|
||||
void (*WaitVbl)(struct fb_info *info);
|
||||
};
|
||||
|
||||
struct fb_info
|
||||
{
|
||||
struct fb_var_screeninfo var; /* Current var */
|
||||
struct fb_fix_screeninfo fix; /* Current fix */
|
||||
struct fb_monspecs monspecs; /* Current Monitor specs */
|
||||
struct fb_videomode *mode; /* current mode */
|
||||
char *screen_base; /* virtual address */
|
||||
uint32_t screen_size;
|
||||
char *ram_base; /* base vram */
|
||||
uint32_t ram_size; /* vram size */
|
||||
char *screen_mono;
|
||||
long update_mono;
|
||||
struct fb_ops *fbops;
|
||||
void *par; /* device dependent */
|
||||
};
|
||||
|
||||
/* fbmem.c */
|
||||
extern int fb_pan_display(struct fb_info *info, struct fb_var_screeninfo *var);
|
||||
extern int fb_set_var(struct fb_info *info, struct fb_var_screeninfo *var);
|
||||
extern int fb_blank(struct fb_info *info, int blank);
|
||||
extern int fb_ioctl(struct fb_info *info, uint32_t cmd, uint32_t arg);
|
||||
extern struct fb_info *framebuffer_alloc(uint32_t size);
|
||||
extern void framebuffer_release(struct fb_info *info);
|
||||
|
||||
/* offscreen.c */
|
||||
extern long offscreen_free(struct fb_info *info, void *addr);
|
||||
extern long offscreen_alloc(struct fb_info *info, long amount);
|
||||
extern long offscren_reserved(struct fb_info *info);
|
||||
extern void offscreen_init(struct fb_info *info);
|
||||
|
||||
/* fbmon.c */
|
||||
#define FB_MAXTIMINGS 0
|
||||
#define FB_VSYNCTIMINGS 1
|
||||
#define FB_HSYNCTIMINGS 2
|
||||
#define FB_DCLKTIMINGS 3
|
||||
#define FB_IGNOREMON 0x100
|
||||
|
||||
#define FB_MODE_IS_UNKNOWN 0
|
||||
#define FB_MODE_IS_DETAILED 1
|
||||
#define FB_MODE_IS_STANDARD 2
|
||||
#define FB_MODE_IS_VESA 4
|
||||
#define FB_MODE_IS_CALCULATED 8
|
||||
#define FB_MODE_IS_FIRST 16
|
||||
#define FB_MODE_IS_FROM_VAR 32
|
||||
|
||||
extern void fb_destroy_modedb(struct fb_videomode *modedb);
|
||||
extern int fb_parse_edid(uint8_t *edid, struct fb_var_screeninfo *var);
|
||||
extern void fb_edid_to_monspecs(uint8_t *edid, struct fb_monspecs *specs);
|
||||
extern int32_t fb_get_mode(int32_t flags, uint32_t val, struct fb_var_screeninfo *var, struct fb_info *info);
|
||||
extern int32_t fb_validate_mode(const struct fb_var_screeninfo *var, struct fb_info *info);
|
||||
|
||||
/* modedb.c */
|
||||
#define VESA_MODEDB_SIZE 34
|
||||
extern int fb_find_mode(struct fb_var_screeninfo *var,
|
||||
struct fb_info *info, struct mode_option *resolution ,
|
||||
const struct fb_videomode *db, unsigned int dbsize,
|
||||
const struct fb_videomode *default_mode, unsigned int default_bpp);
|
||||
extern void fb_var_to_videomode(struct fb_videomode *mode, struct fb_var_screeninfo *var);
|
||||
extern void fb_videomode_to_var(struct fb_var_screeninfo *var, struct fb_videomode *mode);
|
||||
extern int fb_mode_is_equal(struct fb_videomode *mode1, struct fb_videomode *mode2);
|
||||
|
||||
struct fb_videomode
|
||||
{
|
||||
uint16_t refresh; /* optional */
|
||||
uint16_t xres;
|
||||
uint16_t yres;
|
||||
uint32_t pixclock;
|
||||
uint16_t left_margin;
|
||||
uint16_t right_margin;
|
||||
uint16_t upper_margin;
|
||||
uint16_t lower_margin;
|
||||
uint16_t hsync_len;
|
||||
uint16_t vsync_len;
|
||||
uint16_t sync;
|
||||
uint16_t vmode;
|
||||
uint16_t flag;
|
||||
};
|
||||
|
||||
extern const struct fb_videomode vesa_modes[];
|
||||
|
||||
extern void start_timeout(void);
|
||||
extern int32_t end_timeout(long msec);
|
||||
extern void mdelay(long msec);
|
||||
extern void install_vbl_timer(void *func, int32_t remove);
|
||||
extern void uninstall_vbl_timer(void *func);
|
||||
|
||||
extern struct fb_info *info_fvdi;
|
||||
#endif /* _FB_H */
|
||||
93
include/fecbd.h
Normal file
93
include/fecbd.h
Normal file
@@ -0,0 +1,93 @@
|
||||
/*
|
||||
* File: fecbd.h
|
||||
* Purpose:
|
||||
*
|
||||
* Purpose: Provide a simple buffer management driver
|
||||
*/
|
||||
|
||||
#ifndef _FECBD_H_
|
||||
#define _FECBD_H_
|
||||
|
||||
#include "bas_types.h"
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#define Rx 1
|
||||
#define Tx 0
|
||||
|
||||
/*
|
||||
* Buffer sizes in bytes
|
||||
*/
|
||||
#ifndef RX_BUF_SZ
|
||||
#define RX_BUF_SZ NBUF_SZ
|
||||
#endif
|
||||
#ifndef TX_BUF_SZ
|
||||
#define TX_BUF_SZ NBUF_SZ
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Number of Rx and Tx Buffers and Buffer Descriptors
|
||||
*/
|
||||
#ifndef NRXBD
|
||||
#define NRXBD 20
|
||||
#endif
|
||||
#ifndef NTXBD
|
||||
#define NTXBD 20
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Buffer Descriptor Format
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t status; /* control and status */
|
||||
uint16_t length; /* transfer length */
|
||||
uint8_t *data; /* buffer address */
|
||||
} FECBD;
|
||||
|
||||
/*
|
||||
* Bit level definitions for status field of buffer descriptors
|
||||
*/
|
||||
#define TX_BD_R 0x8000
|
||||
#define TX_BD_TO1 0x4000
|
||||
#define TX_BD_W 0x2000
|
||||
#define TX_BD_TO2 0x1000
|
||||
#define TX_BD_INTERRUPT 0x1000 /* MCF547x/8x Only */
|
||||
#define TX_BD_L 0x0800
|
||||
#define TX_BD_TC 0x0400
|
||||
#define TX_BD_DEF 0x0200 /* MCF5272 Only */
|
||||
#define TX_BD_ABC 0x0200
|
||||
#define TX_BD_HB 0x0100 /* MCF5272 Only */
|
||||
#define TX_BD_LC 0x0080 /* MCF5272 Only */
|
||||
#define TX_BD_RL 0x0040 /* MCF5272 Only */
|
||||
#define TX_BD_UN 0x0002 /* MCF5272 Only */
|
||||
#define TX_BD_CSL 0x0001 /* MCF5272 Only */
|
||||
|
||||
#define RX_BD_E 0x8000
|
||||
#define RX_BD_R01 0x4000
|
||||
#define RX_BD_W 0x2000
|
||||
#define RX_BD_R02 0x1000
|
||||
#define RX_BD_INTERRUPT 0x1000 /* MCF547x/8x Only */
|
||||
#define RX_BD_L 0x0800
|
||||
#define RX_BD_M 0x0100
|
||||
#define RX_BD_BC 0x0080
|
||||
#define RX_BD_MC 0x0040
|
||||
#define RX_BD_LG 0x0020
|
||||
#define RX_BD_NO 0x0010
|
||||
#define RX_BD_CR 0x0004
|
||||
#define RX_BD_OV 0x0002
|
||||
#define RX_BD_TR 0x0001
|
||||
#define RX_BD_ERROR (RX_BD_NO | RX_BD_CR | RX_BD_OV | RX_BD_TR)
|
||||
|
||||
/*
|
||||
* Functions provided in fec_bd.c
|
||||
*/
|
||||
extern void fecbd_init(uint8_t);
|
||||
extern uint32_t fecbd_get_start(uint8_t, uint8_t);
|
||||
extern FECBD *fecbd_rx_alloc(uint8_t);
|
||||
extern FECBD *fecbd_tx_alloc(uint8_t);
|
||||
extern FECBD *fecbd_tx_free(uint8_t);
|
||||
|
||||
/*******************************************************************/
|
||||
|
||||
#endif /* _FECBD_H_ */
|
||||
337
include/ff.h
Normal file
337
include/ff.h
Normal file
@@ -0,0 +1,337 @@
|
||||
/*---------------------------------------------------------------------------/
|
||||
/ FatFs - FAT file system module include file R0.09a (C)ChaN, 2012
|
||||
/----------------------------------------------------------------------------/
|
||||
/ FatFs module is a generic FAT file system module for small embedded systems.
|
||||
/ This is a free software that opened for education, research and commercial
|
||||
/ developments under license policy of following terms.
|
||||
/
|
||||
/ Copyright (C) 2012, ChaN, all right reserved.
|
||||
/
|
||||
/ * The FatFs module is a free software and there is NO WARRANTY.
|
||||
/ * No restriction on use. You can use, modify and redistribute it for
|
||||
/ personal, non-profit or commercial product UNDER YOUR RESPONSIBILITY.
|
||||
/ * Redistributions of source code must retain the above copyright notice.
|
||||
/
|
||||
/----------------------------------------------------------------------------*/
|
||||
|
||||
#ifndef _FATFS
|
||||
#define _FATFS 4004 /* Revision ID */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <bas_types.h>
|
||||
#include <ffconf.h> /* FatFs configuration options */
|
||||
|
||||
#if _FATFS != _FFCONF
|
||||
#error Wrong configuration file (ffconf.h).
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
/* Definitions of volume management */
|
||||
|
||||
#if _MULTI_PARTITION /* Multiple partition configuration */
|
||||
typedef struct {
|
||||
uint8_t pd; /* Physical drive number */
|
||||
uint8_t pt; /* Partition: 0:Auto detect, 1-4:Forced partition) */
|
||||
} PARTITION;
|
||||
extern PARTITION VolToPart[]; /* Volume - Partition resolution table */
|
||||
#define LD2PD(vol) (VolToPart[vol].pd) /* Get physical drive number */
|
||||
#define LD2PT(vol) (VolToPart[vol].pt) /* Get partition index */
|
||||
|
||||
#else /* Single partition configuration */
|
||||
#define LD2PD(vol) (uint8_t)(vol) /* Each logical drive is bound to the same physical drive number */
|
||||
#define LD2PT(vol) 0 /* Always mounts the 1st partition or in SFD */
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
/* Type of path name strings on FatFs API */
|
||||
|
||||
#if _LFN_UNICODE /* Unicode string */
|
||||
#if !_USE_LFN
|
||||
#error _LFN_UNICODE must be 0 in non-LFN cfg.
|
||||
#endif
|
||||
#ifndef _INC_TCHAR
|
||||
typedef uint16_t TCHAR;
|
||||
#define _T(x) L ## x
|
||||
#define _TEXT(x) L ## x
|
||||
#endif
|
||||
|
||||
#else /* ANSI/OEM string */
|
||||
#ifndef _INC_TCHAR
|
||||
typedef char TCHAR;
|
||||
#define _T(x) x
|
||||
#define _TEXT(x) x
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
/* File system object structure (FATFS) */
|
||||
|
||||
typedef struct {
|
||||
uint8_t fs_type; /* FAT sub-type (0:Not mounted) */
|
||||
uint8_t drv; /* Physical drive number */
|
||||
uint8_t csize; /* Sectors per cluster (1,2,4...128) */
|
||||
uint8_t n_fats; /* Number of FAT copies (1,2) */
|
||||
uint8_t wflag; /* win[] dirty flag (1:must be written back) */
|
||||
uint8_t fsi_flag; /* fsinfo dirty flag (1:must be written back) */
|
||||
uint16_t id; /* File system mount ID */
|
||||
uint16_t n_rootdir; /* Number of root directory entries (FAT12/16) */
|
||||
#if _MAX_SS != 512
|
||||
uint16_t ssize; /* Bytes per sector (512, 1024, 2048 or 4096) */
|
||||
#endif
|
||||
#if _FS_REENTRANT
|
||||
_SYNC_t sobj; /* Identifier of sync object */
|
||||
#endif
|
||||
#if !_FS_READONLY
|
||||
uint32_t last_clust; /* Last allocated cluster */
|
||||
uint32_t free_clust; /* Number of free clusters */
|
||||
uint32_t fsi_sector; /* fsinfo sector (FAT32) */
|
||||
#endif
|
||||
#if _FS_RPATH
|
||||
uint32_t cdir; /* Current directory start cluster (0:root) */
|
||||
#endif
|
||||
uint32_t n_fatent; /* Number of FAT entries (= number of clusters + 2) */
|
||||
uint32_t fsize; /* Sectors per FAT */
|
||||
uint32_t fatbase; /* FAT start sector */
|
||||
uint32_t dirbase; /* Root directory start sector (FAT32:Cluster#) */
|
||||
uint32_t database; /* Data start sector */
|
||||
uint32_t winsect; /* Current sector appearing in the win[] */
|
||||
uint8_t win[_MAX_SS]; /* Disk access window for Directory, FAT (and Data on tiny cfg) */
|
||||
} FATFS;
|
||||
|
||||
|
||||
|
||||
/* File object structure (FIL) */
|
||||
|
||||
typedef struct {
|
||||
FATFS* fs; /* Pointer to the related file system object */
|
||||
uint16_t id; /* File system mount ID of the related file system object */
|
||||
uint8_t flag; /* File status flags */
|
||||
uint8_t pad1;
|
||||
uint32_t fptr; /* File read/write pointer (0ed on file open) */
|
||||
uint32_t fsize; /* File size */
|
||||
uint32_t sclust; /* File data start cluster (0:no data cluster, always 0 when fsize is 0) */
|
||||
uint32_t clust; /* Current cluster of fpter */
|
||||
uint32_t dsect; /* Current data sector of fpter */
|
||||
#if !_FS_READONLY
|
||||
uint32_t dir_sect; /* Sector containing the directory entry */
|
||||
uint8_t* dir_ptr; /* Pointer to the directory entry in the window */
|
||||
#endif
|
||||
#if _USE_FASTSEEK
|
||||
uint32_t* cltbl; /* Pointer to the cluster link map table (null on file open) */
|
||||
#endif
|
||||
#if _FS_LOCK
|
||||
uint32_t lockid; /* File lock ID (index of file semaphore table Files[]) */
|
||||
#endif
|
||||
#if !_FS_TINY
|
||||
uint8_t buf[_MAX_SS]; /* File data read/write buffer */
|
||||
#endif
|
||||
} FIL;
|
||||
|
||||
|
||||
|
||||
/* Directory object structure (DIR) */
|
||||
|
||||
typedef struct {
|
||||
FATFS* fs; /* Pointer to the owner file system object */
|
||||
uint16_t id; /* Owner file system mount ID */
|
||||
uint16_t index; /* Current read/write index number */
|
||||
uint32_t sclust; /* Table start cluster (0:Root dir) */
|
||||
uint32_t clust; /* Current cluster */
|
||||
uint32_t sect; /* Current sector */
|
||||
uint8_t* dir; /* Pointer to the current SFN entry in the win[] */
|
||||
uint8_t* fn; /* Pointer to the SFN (in/out) {file[8],ext[3],status[1]} */
|
||||
#if _USE_LFN
|
||||
uint16_t* lfn; /* Pointer to the LFN working buffer */
|
||||
uint16_t lfn_idx; /* Last matched LFN index number (0xFFFF:No LFN) */
|
||||
#endif
|
||||
} DIR;
|
||||
|
||||
|
||||
|
||||
/* File status structure (FILINFO) */
|
||||
|
||||
typedef struct {
|
||||
uint32_t fsize; /* File size */
|
||||
uint16_t fdate; /* Last modified date */
|
||||
uint16_t ftime; /* Last modified time */
|
||||
uint8_t fattrib; /* Attribute */
|
||||
TCHAR fname[13]; /* Short file name (8.3 format) */
|
||||
#if _USE_LFN
|
||||
TCHAR* lfname; /* Pointer to the LFN buffer */
|
||||
uint32_t lfsize; /* Size of LFN buffer in TCHAR */
|
||||
#endif
|
||||
} FILINFO;
|
||||
|
||||
|
||||
|
||||
/* File function return code (FRESULT) */
|
||||
|
||||
typedef enum {
|
||||
FR_OK = 0, /* (0) Succeeded */
|
||||
FR_DISK_ERR, /* (1) A hard error occurred in the low level disk I/O layer */
|
||||
FR_INT_ERR, /* (2) Assertion failed */
|
||||
FR_NOT_READY, /* (3) The physical drive cannot work */
|
||||
FR_NO_FILE, /* (4) Could not find the file */
|
||||
FR_NO_PATH, /* (5) Could not find the path */
|
||||
FR_INVALID_NAME, /* (6) The path name format is invalid */
|
||||
FR_DENIED, /* (7) Access denied due to prohibited access or directory full */
|
||||
FR_EXIST, /* (8) Access denied due to prohibited access */
|
||||
FR_INVALID_OBJECT, /* (9) The file/directory object is invalid */
|
||||
FR_WRITE_PROTECTED, /* (10) The physical drive is write protected */
|
||||
FR_INVALID_DRIVE, /* (11) The logical drive number is invalid */
|
||||
FR_NOT_ENABLED, /* (12) The volume has no work area */
|
||||
FR_NO_FILESYSTEM, /* (13) There is no valid FAT volume */
|
||||
FR_MKFS_ABORTED, /* (14) The f_mkfs() aborted due to any parameter error */
|
||||
FR_TIMEOUT, /* (15) Could not get a grant to access the volume within defined period */
|
||||
FR_LOCKED, /* (16) The operation is rejected according to the file sharing policy */
|
||||
FR_NOT_ENOUGH_CORE, /* (17) LFN working buffer could not be allocated */
|
||||
FR_TOO_MANY_OPEN_FILES, /* (18) Number of open files > _FS_SHARE */
|
||||
FR_INVALID_PARAMETER /* (19) Given parameter is invalid */
|
||||
} FRESULT;
|
||||
|
||||
|
||||
|
||||
/*--------------------------------------------------------------*/
|
||||
/* FatFs module application interface */
|
||||
|
||||
FRESULT f_mount (uint8_t, FATFS*); /* Mount/Unmount a logical drive */
|
||||
FRESULT f_open (FIL*, const TCHAR*, uint8_t); /* Open or create a file */
|
||||
FRESULT f_read (FIL*, void*, uint32_t, uint32_t*); /* Read data from a file */
|
||||
FRESULT f_lseek (FIL*, uint32_t); /* Move file pointer of a file object */
|
||||
FRESULT f_close (FIL*); /* Close an open file object */
|
||||
FRESULT f_opendir (DIR*, const char*); /* Open an existing directory */
|
||||
FRESULT f_readdir (DIR*, FILINFO*); /* Read a directory item */
|
||||
FRESULT f_stat (const TCHAR*, FILINFO*); /* Get file status */
|
||||
FRESULT f_write (FIL*, const void*, uint32_t, uint32_t*); /* Write data to a file */
|
||||
FRESULT f_getfree (const TCHAR*, uint32_t*, FATFS**); /* Get number of free clusters on the drive */
|
||||
FRESULT f_truncate (FIL*); /* Truncate file */
|
||||
FRESULT f_sync (FIL*); /* Flush cached data of a writing file */
|
||||
FRESULT f_unlink (const TCHAR*); /* Delete an existing file or directory */
|
||||
FRESULT f_mkdir (const TCHAR*); /* Create a new directory */
|
||||
FRESULT f_chmod (const TCHAR*, uint8_t, uint8_t); /* Change attribute of the file/dir */
|
||||
FRESULT f_utime (const TCHAR*, const FILINFO*); /* Change times-tamp of the file/dir */
|
||||
FRESULT f_rename (const TCHAR*, const TCHAR*); /* Rename/Move a file or directory */
|
||||
FRESULT f_chdrive (uint8_t); /* Change current drive */
|
||||
FRESULT f_chdir (const TCHAR*); /* Change current directory */
|
||||
FRESULT f_getcwd (TCHAR*, uint32_t); /* Get current directory */
|
||||
FRESULT f_forward (FIL*, uint32_t(*)(const uint8_t*,uint32_t), uint32_t, uint32_t*); /* Forward data to the stream */
|
||||
FRESULT f_mkfs (uint8_t, uint8_t, uint32_t); /* Create a file system on the drive */
|
||||
FRESULT f_fdisk (uint8_t, const uint32_t[], void*); /* Divide a physical drive into some partitions */
|
||||
int f_putc (TCHAR, FIL*); /* Put a character to the file */
|
||||
int f_puts (const TCHAR*, FIL*); /* Put a string to the file */
|
||||
int f_printf (FIL*, const TCHAR*, ...); /* Put a formatted string to the file */
|
||||
TCHAR* f_gets (TCHAR*, int, FIL*); /* Get a string from the file */
|
||||
|
||||
#define f_eof(fp) (((fp)->fptr == (fp)->fsize) ? 1 : 0)
|
||||
#define f_error(fp) (((fp)->flag & FA__ERROR) ? 1 : 0)
|
||||
#define f_tell(fp) ((fp)->fptr)
|
||||
#define f_size(fp) ((fp)->fsize)
|
||||
|
||||
#ifndef EOF
|
||||
#define EOF (-1)
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
/*--------------------------------------------------------------*/
|
||||
/* Additional user defined functions */
|
||||
|
||||
/* RTC function */
|
||||
#if !_FS_READONLY
|
||||
uint32_t get_fattime (void);
|
||||
#endif
|
||||
|
||||
/* Unicode support functions */
|
||||
#if _USE_LFN /* Unicode - OEM code conversion */
|
||||
uint16_t ff_convert (uint16_t, uint32_t); /* OEM-Unicode bidirectional conversion */
|
||||
uint16_t ff_wtoupper (uint16_t); /* Unicode upper-case conversion */
|
||||
#if _USE_LFN == 3 /* Memory functions */
|
||||
void* ff_memalloc (uint32_t); /* Allocate memory block */
|
||||
void ff_memfree (void*); /* Free memory block */
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Sync functions */
|
||||
#if _FS_REENTRANT
|
||||
int ff_cre_syncobj (uint8_t, _SYNC_t*);/* Create a sync object */
|
||||
int ff_req_grant (_SYNC_t); /* Lock sync object */
|
||||
void ff_rel_grant (_SYNC_t); /* Unlock sync object */
|
||||
int ff_del_syncobj (_SYNC_t); /* Delete a sync object */
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
/*--------------------------------------------------------------*/
|
||||
/* Flags and offset address */
|
||||
|
||||
|
||||
/* File access control and file status flags (FIL.flag) */
|
||||
|
||||
#define FA_READ 0x01
|
||||
#define FA_OPEN_EXISTING 0x00
|
||||
#define FA__ERROR 0x80
|
||||
|
||||
#if !_FS_READONLY
|
||||
#define FA_WRITE 0x02
|
||||
#define FA_CREATE_NEW 0x04
|
||||
#define FA_CREATE_ALWAYS 0x08
|
||||
#define FA_OPEN_ALWAYS 0x10
|
||||
#define FA__WRITTEN 0x20
|
||||
#define FA__DIRTY 0x40
|
||||
#endif
|
||||
|
||||
|
||||
/* FAT sub type (FATFS.fs_type) */
|
||||
|
||||
#define FS_FAT12 1
|
||||
#define FS_FAT16 2
|
||||
#define FS_FAT32 3
|
||||
|
||||
|
||||
/* File attribute bits for directory entry */
|
||||
|
||||
#define AM_RDO 0x01 /* Read only */
|
||||
#define AM_HID 0x02 /* Hidden */
|
||||
#define AM_SYS 0x04 /* System */
|
||||
#define AM_VOL 0x08 /* Volume label */
|
||||
#define AM_LFN 0x0F /* LFN entry */
|
||||
#define AM_DIR 0x10 /* Directory */
|
||||
#define AM_ARC 0x20 /* Archive */
|
||||
#define AM_MASK 0x3F /* Mask of defined bits */
|
||||
|
||||
|
||||
/* Fast seek feature */
|
||||
#define CREATE_LINKMAP 0xFFFFFFFF
|
||||
|
||||
|
||||
|
||||
/*--------------------------------*/
|
||||
/* Multi-byte word access macros */
|
||||
|
||||
#if _WORD_ACCESS == 1 /* Enable word access to the FAT structure */
|
||||
#define LD_WORD(ptr) (uint16_t)(* (uint16_t *)(uint8_t *)(ptr))
|
||||
#define LD_DWORD(ptr) (uint32_t)(* (uint32_t *)(uint8_t *)(ptr))
|
||||
#define ST_WORD(ptr,val) *(uint16_t *) (uint8_t *)(ptr) = (uint16_t)(val)
|
||||
#define ST_DWORD(ptr,val) *(uint32_t *) (uint8_t *)(ptr) = (uint32_t)(val)
|
||||
#else /* Use byte-by-byte access to the FAT structure */
|
||||
#define LD_WORD(ptr) (uint16_t)(((uint16_t)*((uint8_t *)(ptr) + 1) << 8) | (uint16_t) *(uint8_t *)(ptr))
|
||||
#define LD_DWORD(ptr) (uint32_t)(((uint32_t)*((uint8_t *)(ptr) + 3) << 24) | ((uint32_t)*((uint8_t*)(ptr) + 2) << 16) | ((uint16_t) *((uint8_t*)(ptr) + 1) << 8) | *(uint8_t*)(ptr))
|
||||
#define ST_WORD(ptr,val) *(uint8_t *)(ptr) = (uint8_t)(val); *((uint8_t *)(ptr) + 1) = (uint8_t)((uint16_t)(val) >> 8)
|
||||
#define ST_DWORD(ptr,val) *(uint8_t *)(ptr) = (uint8_t)(val); *((uint8_t *)(ptr) + 1) = (uint8_t)((uint16_t)(val) >> 8); *((uint8_t*)(ptr) + 2) = (uint8_t)((uint32_t)(val) >> 16); *((uint8_t *)(ptr) + 3) = (uint8_t)((uint32_t)(val) >> 24)
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _FATFS */
|
||||
190
include/ffconf.h
Normal file
190
include/ffconf.h
Normal file
@@ -0,0 +1,190 @@
|
||||
/*---------------------------------------------------------------------------/
|
||||
/ FatFs - FAT file system module configuration file R0.09a (C)ChaN, 2012
|
||||
/----------------------------------------------------------------------------/
|
||||
/
|
||||
/ CAUTION! Do not forget to make clean the project after any changes to
|
||||
/ the configuration options.
|
||||
/
|
||||
/----------------------------------------------------------------------------*/
|
||||
#ifndef _FFCONF
|
||||
#define _FFCONF 4004 /* Revision ID */
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------/
|
||||
/ Functions and Buffer Configurations
|
||||
/----------------------------------------------------------------------------*/
|
||||
|
||||
#define _FS_TINY 0 /* 0:Normal or 1:Tiny */
|
||||
/* When _FS_TINY is set to 1, FatFs uses the sector buffer in the file system
|
||||
/ object instead of the sector buffer in the individual file object for file
|
||||
/ data transfer. This reduces memory consumption 512 bytes each file object. */
|
||||
|
||||
|
||||
#define _FS_READONLY 0 /* 0:Read/Write or 1:Read only */
|
||||
/* Setting _FS_READONLY to 1 defines read only configuration. This removes
|
||||
/ writing functions, f_write, f_sync, f_unlink, f_mkdir, f_chmod, f_rename,
|
||||
/ f_truncate and useless f_getfree. */
|
||||
|
||||
|
||||
#define _FS_MINIMIZE 0 /* 0 to 3 */
|
||||
/* The _FS_MINIMIZE option defines minimization level to remove some functions.
|
||||
/
|
||||
/ 0: Full function.
|
||||
/ 1: f_stat, f_getfree, f_unlink, f_mkdir, f_chmod, f_truncate and f_rename
|
||||
/ are removed.
|
||||
/ 2: f_opendir and f_readdir are removed in addition to 1.
|
||||
/ 3: f_lseek is removed in addition to 2. */
|
||||
|
||||
|
||||
#define _USE_STRFUNC 1 /* 0:Disable or 1-2:Enable */
|
||||
/* To enable string functions, set _USE_STRFUNC to 1 or 2. */
|
||||
|
||||
|
||||
#define _USE_MKFS 0 /* 0:Disable or 1:Enable */
|
||||
/* To enable f_mkfs function, set _USE_MKFS to 1 and set _FS_READONLY to 0 */
|
||||
|
||||
|
||||
#define _USE_FORWARD 0 /* 0:Disable or 1:Enable */
|
||||
/* To enable f_forward function, set _USE_FORWARD to 1 and set _FS_TINY to 1. */
|
||||
|
||||
|
||||
#define _USE_FASTSEEK 0 /* 0:Disable or 1:Enable */
|
||||
/* To enable fast seek feature, set _USE_FASTSEEK to 1. */
|
||||
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------/
|
||||
/ Locale and Namespace Configurations
|
||||
/----------------------------------------------------------------------------*/
|
||||
|
||||
#define _CODE_PAGE 858
|
||||
/* The _CODE_PAGE specifies the OEM code page to be used on the target system.
|
||||
/ Incorrect setting of the code page can cause a file open failure.
|
||||
/
|
||||
/ 932 - Japanese Shift-JIS (DBCS, OEM, Windows)
|
||||
/ 936 - Simplified Chinese GBK (DBCS, OEM, Windows)
|
||||
/ 949 - Korean (DBCS, OEM, Windows)
|
||||
/ 950 - Traditional Chinese Big5 (DBCS, OEM, Windows)
|
||||
/ 1250 - Central Europe (Windows)
|
||||
/ 1251 - Cyrillic (Windows)
|
||||
/ 1252 - Latin 1 (Windows)
|
||||
/ 1253 - Greek (Windows)
|
||||
/ 1254 - Turkish (Windows)
|
||||
/ 1255 - Hebrew (Windows)
|
||||
/ 1256 - Arabic (Windows)
|
||||
/ 1257 - Baltic (Windows)
|
||||
/ 1258 - Vietnam (OEM, Windows)
|
||||
/ 437 - U.S. (OEM)
|
||||
/ 720 - Arabic (OEM)
|
||||
/ 737 - Greek (OEM)
|
||||
/ 775 - Baltic (OEM)
|
||||
/ 850 - Multilingual Latin 1 (OEM)
|
||||
/ 858 - Multilingual Latin 1 + Euro (OEM)
|
||||
/ 852 - Latin 2 (OEM)
|
||||
/ 855 - Cyrillic (OEM)
|
||||
/ 866 - Russian (OEM)
|
||||
/ 857 - Turkish (OEM)
|
||||
/ 862 - Hebrew (OEM)
|
||||
/ 874 - Thai (OEM, Windows)
|
||||
/ 1 - ASCII only (Valid for non LFN cfg.)
|
||||
*/
|
||||
|
||||
|
||||
#define _USE_LFN 0 /* 0 to 3 */
|
||||
#define _MAX_LFN 255 /* Maximum LFN length to handle (12 to 255) */
|
||||
/* The _USE_LFN option switches the LFN support.
|
||||
/
|
||||
/ 0: Disable LFN feature. _MAX_LFN and _LFN_UNICODE have no effect.
|
||||
/ 1: Enable LFN with static working buffer on the BSS. Always NOT reentrant.
|
||||
/ 2: Enable LFN with dynamic working buffer on the STACK.
|
||||
/ 3: Enable LFN with dynamic working buffer on the HEAP.
|
||||
/
|
||||
/ The LFN working buffer occupies (_MAX_LFN + 1) * 2 bytes. To enable LFN,
|
||||
/ Unicode handling functions ff_convert() and ff_wtoupper() must be added
|
||||
/ to the project. When enable to use heap, memory control functions
|
||||
/ ff_memalloc() and ff_memfree() must be added to the project. */
|
||||
|
||||
|
||||
#define _LFN_UNICODE 0 /* 0:ANSI/OEM or 1:Unicode */
|
||||
/* To switch the character code set on FatFs API to Unicode,
|
||||
/ enable LFN feature and set _LFN_UNICODE to 1. */
|
||||
|
||||
|
||||
#define _FS_RPATH 0 /* 0 to 2 */
|
||||
/* The _FS_RPATH option configures relative path feature.
|
||||
/
|
||||
/ 0: Disable relative path feature and remove related functions.
|
||||
/ 1: Enable relative path. f_chdrive() and f_chdir() are available.
|
||||
/ 2: f_getcwd() is available in addition to 1.
|
||||
/
|
||||
/ Note that output of the f_readdir fnction is affected by this option. */
|
||||
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------/
|
||||
/ Physical Drive Configurations
|
||||
/----------------------------------------------------------------------------*/
|
||||
|
||||
#define _VOLUMES 1
|
||||
/* Number of volumes (logical drives) to be used. */
|
||||
|
||||
|
||||
#define _MAX_SS 512 /* 512, 1024, 2048 or 4096 */
|
||||
/* Maximum sector size to be handled.
|
||||
/ Always set 512 for memory card and hard disk but a larger value may be
|
||||
/ required for on-board flash memory, floppy disk and optical disk.
|
||||
/ When _MAX_SS is larger than 512, it configures FatFs to variable sector size
|
||||
/ and GET_SECTOR_SIZE command must be implememted to the disk_ioctl function. */
|
||||
|
||||
|
||||
#define _MULTI_PARTITION 0 /* 0:Single partition, 1/2:Enable multiple partition */
|
||||
/* When set to 0, each volume is bound to the same physical drive number and
|
||||
/ it can mount only first primaly partition. When it is set to 1, each volume
|
||||
/ is tied to the partitions listed in VolToPart[]. */
|
||||
|
||||
|
||||
#define _USE_ERASE 0 /* 0:Disable or 1:Enable */
|
||||
/* To enable sector erase feature, set _USE_ERASE to 1. CTRL_ERASE_SECTOR command
|
||||
/ should be added to the disk_ioctl functio. */
|
||||
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------/
|
||||
/ System Configurations
|
||||
/----------------------------------------------------------------------------*/
|
||||
|
||||
#define _WORD_ACCESS 0 /* 0 or 1 */
|
||||
/* Set 0 first and it is always compatible with all platforms. The _WORD_ACCESS
|
||||
/ option defines which access method is used to the word data on the FAT volume.
|
||||
/
|
||||
/ 0: Byte-by-byte access.
|
||||
/ 1: Word access. Do not choose this unless following condition is met.
|
||||
/
|
||||
/ When the byte order on the memory is big-endian or address miss-aligned word
|
||||
/ access results incorrect behavior, the _WORD_ACCESS must be set to 0.
|
||||
/ If it is not the case, the value can also be set to 1 to improve the
|
||||
/ performance and code size.
|
||||
*/
|
||||
|
||||
|
||||
/* A header file that defines sync object types on the O/S, such as
|
||||
/ windows.h, ucos_ii.h and semphr.h, must be included prior to ff.h. */
|
||||
|
||||
#define _FS_REENTRANT 0 /* 0:Disable or 1:Enable */
|
||||
#define _FS_TIMEOUT 1000 /* Timeout period in unit of time ticks */
|
||||
#define _SYNC_t HANDLE /* O/S dependent type of sync object. e.g. HANDLE, OS_EVENT*, ID and etc.. */
|
||||
|
||||
/* The _FS_REENTRANT option switches the reentrancy (thread safe) of the FatFs module.
|
||||
/
|
||||
/ 0: Disable reentrancy. _SYNC_t and _FS_TIMEOUT have no effect.
|
||||
/ 1: Enable reentrancy. Also user provided synchronization handlers,
|
||||
/ ff_req_grant, ff_rel_grant, ff_del_syncobj and ff_cre_syncobj
|
||||
/ function must be added to the project. */
|
||||
|
||||
|
||||
#define _FS_LOCK 0 /* 0:Disable or >=1:Enable */
|
||||
/* To enable file lock control feature, set _FS_LOCK to 1 or greater.
|
||||
The value defines how many files can be opened simultaneously. */
|
||||
|
||||
|
||||
#endif /* _FFCONFIG */
|
||||
51
include/firebee.h
Normal file
51
include/firebee.h
Normal file
@@ -0,0 +1,51 @@
|
||||
#ifndef _FIREBEE_H_
|
||||
#define _FIREBEE_H_
|
||||
|
||||
/*
|
||||
* firebee.h
|
||||
*
|
||||
* preprocessor definitions for the Firebee machine. This file should contain nothing but preprocessor
|
||||
* definition that evaluate to numbers. It is intended for use in C sources as well as in linker control
|
||||
* files, so care must be taken to not break the syntax of either one.
|
||||
*
|
||||
* This file is part of BaS_gcc.
|
||||
*
|
||||
* BaS_gcc is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* BaS_gcc is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* Created on: 26.02.2013
|
||||
* Author: Markus Fröschle
|
||||
*/
|
||||
|
||||
#define SYSCLK 132000 /* NOTE: 132 _is_ correct. 133 _is_ wrong. Do not change! */
|
||||
|
||||
#define BOOTFLASH_BASE_ADDRESS 0xE0000000
|
||||
#define BOOTFLASH_SIZE 0x800000 /* FireBee has 8 MByte Flash */
|
||||
#define BOOTFLASH_BAM (BOOTFLASH_SIZE - 1)
|
||||
|
||||
#define SDRAM_START 0x00000000 /* start at address 0 */
|
||||
#define SDRAM_SIZE 0x20000000 /* 512 MB on the Firebee */
|
||||
|
||||
#ifdef COMPILE_RAM
|
||||
#define TARGET_ADDRESS (SDRAM_START + SDRAM_SIZE - 0x200000)
|
||||
#else
|
||||
#define TARGET_ADDRESS BOOTFLASH_BASE_ADDRESS
|
||||
#define BFL_TARGET_ADDRESS 0x0100000 /* load address for basflash */
|
||||
|
||||
#endif /* COMPILE_RAM */
|
||||
|
||||
#define DRIVER_MEM_BUFFER_SIZE 0x100000
|
||||
|
||||
#define EMUTOS_BASE_ADDRESS 0xe0600000
|
||||
|
||||
#endif /* _FIREBEE_H_ */
|
||||
11
include/ikbd.h
Normal file
11
include/ikbd.h
Normal file
@@ -0,0 +1,11 @@
|
||||
#ifndef _IKBD_H_
|
||||
#define _IKBD_H_
|
||||
|
||||
extern void ikbd_init(void);
|
||||
extern void ikbd_poll(void);
|
||||
extern void ikbd_joystick(uint8_t joy, uint8_t map);
|
||||
extern void ikbd_mouse(uint8_t buttons, int8_t x, int8_t y);
|
||||
extern void ikbd_keyboard(uint8_t code);
|
||||
|
||||
#endif /* _IKBD_H_ */
|
||||
|
||||
150
include/interrupts.h
Normal file
150
include/interrupts.h
Normal file
@@ -0,0 +1,150 @@
|
||||
/*
|
||||
* interrupts.h
|
||||
*
|
||||
* This file is part of BaS_gcc.
|
||||
*
|
||||
* BaS_gcc is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* BaS_gcc is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
*
|
||||
* Created on: 08.08.2013
|
||||
* Author: Markus Fröschle
|
||||
*/
|
||||
|
||||
#ifndef _INTERRUPTS_H_
|
||||
#define _INTERRUPTS_H_
|
||||
|
||||
#include <stdbool.h>
|
||||
|
||||
/* interrupt sources */
|
||||
#define INT_SOURCE_EPORT_EPF1 1 // edge port flag 1
|
||||
#define INT_SOURCE_EPORT_EPF2 2 // edge port flag 2
|
||||
#define INT_SOURCE_EPORT_EPF3 3 // edge port flag 3
|
||||
#define INT_SOURCE_EPORT_EPF4 4 // edge port flag 4
|
||||
#define INT_SOURCE_EPORT_EPF5 5 // edge port flag 5
|
||||
#define INT_SOURCE_EPORT_EPF6 6 // edge port flag 6
|
||||
#define INT_SOURCE_EPORT_EPF7 7 // edge port flag 7
|
||||
#define INT_SOURCE_USB_EP0ISR 15 // USB endpoint 0 interrupt
|
||||
#define INT_SOURCE_USB_EP1ISR 16 // USB endpoint 1 interrupt
|
||||
#define INT_SOURCE_USB_EP2ISR 17 // USB endpoint 2 interrupt
|
||||
#define INT_SOURCE_USB_EP3ISR 18 // USB endpoint 3 interrupt
|
||||
#define INT_SOURCE_USB_EP4ISR 19 // USB endpoint 4 interrupt
|
||||
#define INT_SOURCE_USB_EP5ISR 20 // USB endpoint 5 interrupt
|
||||
#define INT_SOURCE_USB_EP6ISR 21 // USB endpoint 6 interrupt
|
||||
#define INT_SOURCE_USB_USBISR 22 // USB general interrupt
|
||||
#define INT_SOURCE_USB_USBAISR 23 // USB core interrupt
|
||||
#define INT_SOURCE_USB_ANY 24 // OR of all USB interrupts
|
||||
#define INT_SOURCE_USB_DSPI_OVF 25 // DSPI overflow or underflow
|
||||
#define INT_SOURCE_USB_DSPI_RFOF 26 // receive FIFO overflow interrupt
|
||||
#define INT_SOURCE_USB_DSPI_RFDF 27 // receive FIFO drain interrupt
|
||||
#define INT_SOURCE_USB_DSPI_TFUF 28 // transmit FIFO underflow interrupt
|
||||
#define INT_SOURCE_USB_DSPI_TCF 29 // transfer complete interrupt
|
||||
#define INT_SOURCE_USB_DSPI_TFFF 30 // transfer FIFO fill interrupt
|
||||
#define INT_SOURCE_USB_DSPI_EOQF 31 // end of queue interrupt
|
||||
#define INT_SOURCE_PSC3 32 // PSC3 interrupt
|
||||
#define INT_SOURCE_PSC2 33 // PSC2 interrupt
|
||||
#define INT_SOURCE_PSC1 34 // PSC1 interrupt
|
||||
#define INT_SOURCE_PSC0 35 // PSC0 interrupt
|
||||
#define INT_SOURCE_CTIMERS 36 // combined source for comm timers
|
||||
#define INT_SOURCE_SEC 37 // SEC interrupt
|
||||
#define INT_SOURCE_FEC1 38 // FEC1 interrupt
|
||||
#define INT_SOURCE_FEC0 39 // FEC0 interrupt
|
||||
#define INT_SOURCE_I2C 40 // I2C interrupt
|
||||
#define INT_SOURCE_PCIARB 41 // PCI arbiter interrupt
|
||||
#define INT_SOURCE_CBPCI 42 // COMM bus PCI interrupt
|
||||
#define INT_SOURCE_XLBPCI 43 // XLB PCI interrupt
|
||||
#define INT_SOURCE_XLBARB 47 // XLBARB to PCI interrupt
|
||||
#define INT_SOURCE_DMA 48 // multichannel DMA interrupt
|
||||
#define INT_SOURCE_CAN0_ERROR 49 // FlexCAN error interrupt
|
||||
#define INT_SOURCE_CAN0_BUSOFF 50 // FlexCAN bus off interrupt
|
||||
#define INT_SOURCE_CAN0_MBOR 51 // message buffer ORed interrupt
|
||||
#define INT_SOURCE_SLT1 53 // slice timer 1 interrupt
|
||||
#define INT_SOURCE_SLT0 54 // slice timer 0 interrupt
|
||||
#define INT_SOURCE_CAN1_ERROR 55 // FlexCAN error interrupt
|
||||
#define INT_SOURCE_CAN1_BUSOFF 56 // FlexCAN bus off interrupt
|
||||
#define INT_SOURCE_CAN1_MBOR 57 // message buffer ORed interrupt
|
||||
#define INT_SOURCE_GPT3 59 // GPT3 timer interrupt
|
||||
#define INT_SOURCE_GPT2 60 // GPT2 timer interrupt
|
||||
#define INT_SOURCE_GPT1 61 // GPT1 timer interrupt
|
||||
#define INT_SOURCE_GPT0 62 // GPT0 timer interrupt
|
||||
|
||||
|
||||
#define FEC0_INTC_LVL 6 /* interrupt level for FEC0 */
|
||||
#define FEC0_INTC_PRI 7 /* interrupt priority for FEC0 */
|
||||
|
||||
#define FEC1_INTC_LVL 6 /* interrupt level for FEC1 */
|
||||
#define FEC1_INTC_PRI 6 /* interrupt priority for FEC1 */
|
||||
|
||||
#define FEC_INTC_LVL(x) ((x == 0) ? FEC0_INTC_LVL : FEC1_INTC_LVL)
|
||||
#define FEC_INTC_PRI(x) ((x == 0) ? FEC0_INTC_PRI : FEC1_INTC_PRI)
|
||||
|
||||
#define FEC0RX_DMA_PRI 5
|
||||
#define FEC1RX_DMA_PRI 4
|
||||
#define FECRX_DMA_PRI(x) ((x == 0) ? FEC0RX_DMA_PRI : FEC1RX_DMA_PRI)
|
||||
#define FEC0TX_DMA_PRI 2
|
||||
#define FEC1TX_DMA_PRI 1
|
||||
#define FECTX_DMA_PRI(x) ((x == 0) ? FEC0TX_DMA_PRI : FEC1TX_DMA_PRI)
|
||||
|
||||
#if defined(MACHINE_FIREBEE)
|
||||
|
||||
/* Firebee FPGA interrupt controller */
|
||||
#define FBEE_INTR_CONTROL * ((volatile uint32_t *) 0xf0010000)
|
||||
#define FBEE_INTR_ENABLE * ((volatile uint32_t *) 0xf0010004)
|
||||
#define FBEE_INTR_CLEAR * ((volatile uint32_t *) 0xf0010008)
|
||||
#define FBEE_INTR_PENDING * ((volatile uint32_t *) 0xff01000c)
|
||||
|
||||
/* register bits for Firebee FPGA-based interrupt controller */
|
||||
#define FBEE_INTR_PIC (1 << 0) /* PIC interrupt enable/pending/clear bit */
|
||||
#define FBEE_INTR_ETHERNET (1 << 1) /* ethernet PHY interrupt enable/pending/clear bit */
|
||||
#define FBEE_INTR_DVI (1 << 2) /* TFP410 monitor sense interrupt enable/pending/clear bit */
|
||||
#define FBEE_INTR_PCI_INTA (1 << 3) /* /PCIINTA enable/pending clear bit */
|
||||
#define FBEE_INTR_PCI_INTB (1 << 4) /* /PCIINTB enable/pending clear bit */
|
||||
#define FBEE_INTR_PCI_INTC (1 << 5) /* /PCIINTC enable/pending clear bit */
|
||||
#define FBEE_INTR_PCI_INTD (1 << 6) /* /PCIINTD enable/pending clear bit */
|
||||
#define FBEE_INTR_DSP (1 << 7) /* DSP interrupt enable/pending/clear bit */
|
||||
#define FBEE_INTR_VSYNC (1 << 8) /* VSYNC interrupt enable/pending/clear bit */
|
||||
#define FBEE_INTR_HSYNC (1 << 9) /* HSYNC interrupt enable/pending/clear bit */
|
||||
|
||||
#define FBEE_INTR_INT_HSYNC_IRQ2 (1 << 26) /* these bits are only meaningful for the FBEE_INTR_ENABLE register */
|
||||
#define FBEE_INTR_INT_CTR0_IRQ3 (1 << 27)
|
||||
#define FBEE_INTR_INT_VSYNC_IRQ4 (1 << 28)
|
||||
#define FBEE_INTR_INT_FPGA_IRQ5 (1 << 29)
|
||||
#define FBEE_INTR_INT_MFP_IRQ6 (1 << 30)
|
||||
#define FBEE_INTR_INT_IRQ7 (1 << 31)
|
||||
|
||||
/*
|
||||
* Atari MFP interrupt registers.
|
||||
*/
|
||||
|
||||
#define FALCON_MFP_IERA *((volatile uint8_t *) 0xfffffa07)
|
||||
#define FALCON_MFP_IERB *((volatile uint8_t *) 0xfffffa09)
|
||||
#define FALCON_MFP_IPRA *((volatile uint8_t *) 0xfffffa0b)
|
||||
#define FALCON_MFP_IPRB *((volatile uint8_t *) 0xfffffa0d)
|
||||
#define FALCON_MFP_IMRA *((volatile uint8_t *) 0xfffffa13)
|
||||
#define FALCON_MFP_IMRB *((volatile uint8_t *) 0xfffffa15)
|
||||
|
||||
#endif /* MACHINE_FIREBEE */
|
||||
|
||||
extern void isr_init(void);
|
||||
extern bool isr_set_prio_and_level(int int_source, int priority, int level);
|
||||
extern bool isr_enable_int_source(int int_source);
|
||||
extern bool isr_register_handler(int vector, int level, int priority, bool (*handler)(void *, void *), void *hdev, void *harg);
|
||||
extern void isr_remove_handler(bool (*handler)(void *, void *));
|
||||
extern bool isr_execute_handler(int vector);
|
||||
extern bool pic_interrupt_handler(void *arg1, void *arg2);
|
||||
extern bool xlbpci_interrupt_handler(void *arg1, void *arg2);
|
||||
extern bool pciarb_interrupt_handler(void *arg1, void *arg2);
|
||||
extern bool xlbarb_interrupt_handler(void *arg1, void *arg2);
|
||||
extern bool gpt0_interrupt_handler(void *arg1, void *arg2);
|
||||
extern bool irq5_handler(void *arg1, void *arg2);
|
||||
#endif /* _INTERRUPTS_H_ */
|
||||
80
include/ip.h
Normal file
80
include/ip.h
Normal file
@@ -0,0 +1,80 @@
|
||||
/*
|
||||
* File: ip.h
|
||||
* Purpose: Definitions for the Internet Protocol, IP.
|
||||
*
|
||||
* Notes: See RFC 791 "DARPA Internet Program Protocol
|
||||
* Specification" for more details.
|
||||
*/
|
||||
|
||||
#ifndef _IP_H
|
||||
#define _IP_H
|
||||
|
||||
|
||||
/* 32-bit IP Addresses */
|
||||
typedef uint8_t IP_ADDR[4];
|
||||
|
||||
/* Pointer to an IP Address */
|
||||
typedef uint8_t IP_ADDR_P[];
|
||||
|
||||
/* Definition of an IP packet header */
|
||||
typedef struct
|
||||
{
|
||||
uint8_t version_ihl;
|
||||
uint8_t service_type;
|
||||
uint16_t total_length;
|
||||
uint16_t identification;
|
||||
uint16_t flags_frag_offset;
|
||||
uint8_t ttl;
|
||||
uint8_t protocol;
|
||||
uint16_t checksum;
|
||||
IP_ADDR source_addr;
|
||||
IP_ADDR dest_addr;
|
||||
uint8_t options; /* actually an array of undetermined length */
|
||||
} ip_frame_hdr;
|
||||
|
||||
/* Macros for accessing an IP datagram. */
|
||||
#define IP_VERSION(a) ((a->version_ihl & 0x00F0) >> 4)
|
||||
#define IP_IHL(a) ((a->version_ihl & 0x000F))
|
||||
#define IP_SERVICE(a) (a->service_type)
|
||||
#define IP_LENGTH(a) (a->total_length)
|
||||
#define IP_IDENT(a) (a->identification)
|
||||
#define IP_FLAGS(a) ((a->flags_frag_offset & 0x0000E000) >> 13)
|
||||
#define IP_FRAGMENT(a) ((a->flags_frag_offset & 0x00001FFF))
|
||||
#define IP_TTL(a) (a->ttl)
|
||||
#define IP_PROTOCOL(a) (a->protocol)
|
||||
#define IP_CHKSUM(a) (a->checksum)
|
||||
#define IP_SRC(a) (&a->source_addr[0])
|
||||
#define IP_DEST(a) (&a->dest_addr[0])
|
||||
#define IP_OPTIONS(a) (&a->options)
|
||||
#define IP_DATA(a) (&((uint8_t *)a)[IP_IHL(a) * 4])
|
||||
|
||||
/* Defined IP protocols */
|
||||
#define IP_PROTO_ICMP (1)
|
||||
#define IP_PROTO_UDP (17)
|
||||
|
||||
/* Protocol Header information */
|
||||
#define IP_HDR_OFFSET ETH_HDR_LEN
|
||||
#define IP_HDR_SIZE 20 /* no options */
|
||||
|
||||
|
||||
typedef struct
|
||||
{
|
||||
IP_ADDR myip;
|
||||
IP_ADDR gateway;
|
||||
IP_ADDR netmask;
|
||||
IP_ADDR broadcast;
|
||||
unsigned int rx;
|
||||
unsigned int rx_unsup;
|
||||
unsigned int tx;
|
||||
unsigned int err;
|
||||
} IP_INFO;
|
||||
|
||||
|
||||
extern void ip_handler(NIF *nif, NBUF *nbf);
|
||||
uint16_t ip_chksum(uint16_t *data, int num);
|
||||
extern int ip_send(NIF *nif, uint8_t *dest_addr, uint8_t *src_addr, uint8_t protocol, NBUF *nbf);
|
||||
extern void ip_init(IP_INFO *, IP_ADDR_P, IP_ADDR_P, IP_ADDR_P);
|
||||
extern uint8_t *ip_get_myip(IP_INFO *);
|
||||
extern uint8_t *ip_resolve_route(NIF *, IP_ADDR_P);
|
||||
|
||||
#endif /* _IP_H */
|
||||
50
include/m5484l.h
Normal file
50
include/m5484l.h
Normal file
@@ -0,0 +1,50 @@
|
||||
#ifndef _M5484L_H_
|
||||
#define _M5484L_H_
|
||||
|
||||
/*
|
||||
* m5484l.h
|
||||
*
|
||||
* preprocessor definitions for the M5484LITE machine. This file should contain nothing but preprocessor
|
||||
* definition that evaluate to numbers. It is intended for use in C sources as well as in linker control
|
||||
* files, so care must be taken to not break the syntax of either one.
|
||||
*
|
||||
* This file is part of BaS_gcc.
|
||||
*
|
||||
* BaS_gcc is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* BaS_gcc is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* Created on: 26.02.2013
|
||||
* Author: Markus Fröschle
|
||||
*/
|
||||
|
||||
#define SYSCLK 100000UL
|
||||
|
||||
#define BOOTFLASH_BASE_ADDRESS 0xe0000000
|
||||
#define BOOTFLASH_SIZE 0x400000 /* LITEKIT has 4MB flash */
|
||||
#define BOOTFLASH_BAM (BOOTFLASH_SIZE - 1)
|
||||
|
||||
#define SDRAM_START 0x00000000 /* start at address 0 */
|
||||
#define SDRAM_SIZE 0x4000000 /* 64 MB on the LITEKIT */
|
||||
|
||||
#ifdef COMPILE_RAM
|
||||
#define TARGET_ADDRESS (SDRAM_START + SDRAM_SIZE - 0x200000)
|
||||
#else
|
||||
#define TARGET_ADDRESS BOOTFLASH_BASE_ADDRESS
|
||||
#endif /* COMPILE_RAM */
|
||||
#define BFL_TARGET_ADDRESS 0x0100000 /* load address for basflash */
|
||||
|
||||
#define DRIVER_MEM_BUFFER_SIZE 0x100000
|
||||
|
||||
#define EMUTOS_BASE_ADDRESS 0xe0100000
|
||||
|
||||
#endif /* _M5484L_H_ */
|
||||
48
include/mcd_initiators.h
Normal file
48
include/mcd_initiators.h
Normal file
@@ -0,0 +1,48 @@
|
||||
#ifndef _MCD_INITIATORS_H_
|
||||
#define _MCD_INITIATORS_H_
|
||||
|
||||
/* initiators */
|
||||
|
||||
/* direct connected initiators */
|
||||
#define DMA_ALWAYS (0)
|
||||
#define DMA_DSPI_RXFIFO (1)
|
||||
#define DMA_DSPI_TXFIFO (2)
|
||||
#define DMA_DREQ0 (3)
|
||||
#define DMA_PSC0_RX (4)
|
||||
#define DMA_PSC0_TX (5)
|
||||
#define DMA_USB_EP0 (6)
|
||||
#define DMA_USB_EP1 (7)
|
||||
#define DMA_USB_EP2 (8)
|
||||
#define DMA_USB_EP3 (9)
|
||||
#define DMA_PCI_TX (10)
|
||||
#define DMA_PCI_RX (11)
|
||||
#define DMA_PSC1_RX (12)
|
||||
#define DMA_PSC1_TX (13)
|
||||
#define DMA_I2C_RX (14)
|
||||
#define DMA_I2C_TX (15)
|
||||
|
||||
/* multiplexed initiators */
|
||||
#define DMA_FEC0_RX (16)
|
||||
#define DMA_FEC0_TX (17)
|
||||
#define DMA_FEC1_RX (18)
|
||||
#define DMA_FEC1_TX (19)
|
||||
#define DMA_DREQ1 (20)
|
||||
#define DMA_CTM0 (21)
|
||||
#define DMA_CTM1 (22)
|
||||
#define DMA_CTM2 (23)
|
||||
#define DMA_CTM3 (24)
|
||||
#define DMA_CTM4 (25)
|
||||
#define DMA_CTM5 (26)
|
||||
#define DMA_CTM6 (27)
|
||||
#define DMA_CTM7 (28)
|
||||
#define DMA_USBEP4 (29)
|
||||
#define DMA_USBEP5 (30)
|
||||
#define DMA_USBEP6 (31)
|
||||
#define DMA_PSC2_RX (32)
|
||||
#define DMA_PSC2_TX (33)
|
||||
#define DMA_PSC3_RX (34)
|
||||
#define DMA_PSC3_TX (35)
|
||||
#define DMA_FEC_RX(x) ((x == 0) ? DMA_FEC0_RX : DMA_FEC1_RX)
|
||||
#define DMA_FEC_TX(x) ((x == 0) ? DMA_FEC0_TX : DMA_FEC1_TX)
|
||||
|
||||
#endif /* _MCD_INITIATORS_H_ */
|
||||
133
include/mmu.h
Normal file
133
include/mmu.h
Normal file
@@ -0,0 +1,133 @@
|
||||
/*
|
||||
* mmu.h
|
||||
*
|
||||
* This file is part of BaS_gcc.
|
||||
*
|
||||
* BaS_gcc is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* BaS_gcc is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* Created on: 26.02.2013
|
||||
* Author: Markus Fröschle
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _MMU_H_
|
||||
#define _MMU_H_
|
||||
|
||||
#include <stddef.h>
|
||||
#include "bas_types.h"
|
||||
|
||||
/*
|
||||
* ACR register handling macros
|
||||
*/
|
||||
#define ACR_BA(x) ((x) & 0xff000000)
|
||||
#define ACR_ADMSK(x) (((x) & 0xff) << 16)
|
||||
#define ACR_E(x) (((x) & 1) << 15)
|
||||
|
||||
#define ACR_S(x) (((x) & 3) << 13)
|
||||
#define ACR_S_USERMODE 0
|
||||
#define ACR_S_SUPERVISOR_MODE 1
|
||||
#define ACR_S_ALL 2
|
||||
|
||||
#define ACR_ADDRESS_MASK_MODE(x) (((x) & 1) << 10)
|
||||
|
||||
#define ACR_CACHE_MODE(x) (((x) & 3) << 5)
|
||||
#define ACR_SUPERVISOR_PROTECT(x) (((x) & 1) << 3)
|
||||
#define ACR_WRITE_PROTECT(x) (((x) & 1) << 2)
|
||||
|
||||
#define ACR_AMM(x) (((x) & 1) << 10)
|
||||
|
||||
#define ACR_CM(x) (((x) & 3) << 5)
|
||||
#define ACR_CM_CACHEABLE_WT 0x0
|
||||
#define ACR_CM_CACHEABLE_CB 0x1
|
||||
#define ACR_CM_CACHE_INH_PRECISE 0x2
|
||||
#define ACR_CM_CACHE_INH_IMPRECISE 0x3
|
||||
|
||||
#define ACR_SP(x) (((x) & 1) << 3)
|
||||
#define ACR_W(x) (((x) & 1) << 2)
|
||||
|
||||
|
||||
/*
|
||||
* MMU register handling macros
|
||||
*/
|
||||
|
||||
#define SCA_PAGE_ID 6 /* indicates video memory page */
|
||||
|
||||
/*
|
||||
* MMU page sizes
|
||||
*/
|
||||
|
||||
enum mmu_page_size
|
||||
{
|
||||
MMU_PAGE_SIZE_1M = 0,
|
||||
MMU_PAGE_SIZE_4K = 1,
|
||||
MMU_PAGE_SIZE_8K = 2,
|
||||
MMU_PAGE_SIZE_1K = 3
|
||||
};
|
||||
|
||||
#define MMU_PAGE_SIZE_DEFAULT MMU_PAGE_SIZE_1M /* note: if this changes, SIZE_DEFAULT below _must_ also change */
|
||||
|
||||
#define SIZE_1M 0x100000 /* 1 Megabyte */
|
||||
#define SIZE_4K 0x1000 /* 4 KB */
|
||||
#define SIZE_8K 0x2000 /* 8 KB */
|
||||
#define SIZE_1K 0x400 /* 1 KB */
|
||||
|
||||
#define SIZE_DEFAULT SIZE_1M
|
||||
/*
|
||||
* cache modes
|
||||
*/
|
||||
#define CACHE_WRITETHROUGH 0
|
||||
#define CACHE_COPYBACK 1
|
||||
#define CACHE_NOCACHE_PRECISE 2
|
||||
#define CACHE_NOCACHE_IMPRECISE 3
|
||||
|
||||
|
||||
/*
|
||||
* page flags
|
||||
*/
|
||||
#define SV_PROTECT 1
|
||||
#define SV_USER 0
|
||||
|
||||
#define ACCESS_READ (1 << 0)
|
||||
#define ACCESS_WRITE (1 << 1)
|
||||
#define ACCESS_EXECUTE (1 << 2)
|
||||
|
||||
|
||||
/*
|
||||
* global variables from linker script
|
||||
*/
|
||||
extern long video_tlb;
|
||||
extern long video_sbt;
|
||||
|
||||
struct mmu_page_descriptor_ram
|
||||
{
|
||||
uint8_t cache_mode : 2;
|
||||
uint8_t supervisor_protect : 1;
|
||||
uint8_t read : 1;
|
||||
uint8_t write : 1;
|
||||
uint8_t execute : 1;
|
||||
uint8_t global : 1;
|
||||
uint8_t locked : 1;
|
||||
};
|
||||
|
||||
extern void mmu_init(void);
|
||||
extern uint32_t mmu_map_page(uint32_t virt, uint32_t phys, enum mmu_page_size sz, uint8_t page_id, const struct mmu_page_descriptor_ram *flags);
|
||||
|
||||
/*
|
||||
* API functions for the BaS driver interface
|
||||
*/
|
||||
extern uint32_t mmu_map_data_page_locked(uint32_t address, uint32_t length, int asid);
|
||||
extern uint32_t mmu_unlock_data_page(uint32_t address, uint32_t length, int asid);
|
||||
extern uint32_t mmu_report_locked_pages(uint32_t *num_itlb, uint32_t *num_dtlb);
|
||||
extern uint32_t mmu_report_pagesize(void);
|
||||
#endif /* _MMU_H_ */
|
||||
176
include/mod_devicetable.h
Normal file
176
include/mod_devicetable.h
Normal file
@@ -0,0 +1,176 @@
|
||||
#ifndef MOD_DEVICETABLE_H
|
||||
#define MOD_DEVICETABLE_H
|
||||
|
||||
#define PCI_ANY_ID (~0)
|
||||
|
||||
struct pci_device_id
|
||||
{
|
||||
unsigned long vendor; /* Vendor and device ID or PCI_ANY_ID*/
|
||||
unsigned long device;
|
||||
unsigned long subvendor; /* Subsystem ID's or PCI_ANY_ID */
|
||||
unsigned long subdevice;
|
||||
unsigned long class; /* (class,subclass,prog-if) triplet */
|
||||
unsigned long class_mask;
|
||||
unsigned long driver_data; /* Data private to the driver */
|
||||
};
|
||||
|
||||
#define IEEE1394_MATCH_VENDOR_ID 0x0001
|
||||
#define IEEE1394_MATCH_MODEL_ID 0x0002
|
||||
#define IEEE1394_MATCH_SPECIFIER_ID 0x0004
|
||||
#define IEEE1394_MATCH_VERSION 0x0008
|
||||
|
||||
struct ieee1394_device_id
|
||||
{
|
||||
unsigned long match_flags;
|
||||
unsigned long vendor_id;
|
||||
unsigned long model_id;
|
||||
unsigned long specifier_id;
|
||||
unsigned long version;
|
||||
unsigned long driver_data;
|
||||
};
|
||||
|
||||
/*
|
||||
* Device table entry for "new style" table-driven USB drivers.
|
||||
* User mode code can read these tables to choose which modules to load.
|
||||
* Declare the table as a MODULE_DEVICE_TABLE.
|
||||
*
|
||||
* A probe() parameter will point to a matching entry from this table.
|
||||
* Use the driver_info field for each match to hold information tied
|
||||
* to that match: device quirks, etc.
|
||||
*
|
||||
* Terminate the driver's table with an all-zeroes entry.
|
||||
* Use the flag values to control which fields are compared.
|
||||
*/
|
||||
|
||||
/**
|
||||
* struct usb_device_id - identifies USB devices for probing and hotplugging
|
||||
* @match_flags: Bit mask controlling of the other fields are used to match
|
||||
* against new devices. Any field except for driver_info may be used,
|
||||
* although some only make sense in conjunction with other fields.
|
||||
* This is usually set by a USB_DEVICE_*() macro, which sets all
|
||||
* other fields in this structure except for driver_info.
|
||||
* @idVendor: USB vendor ID for a device; numbers are assigned
|
||||
* by the USB forum to its members.
|
||||
* @idProduct: Vendor-assigned product ID.
|
||||
* @bcdDevice_lo: Low end of range of vendor-assigned product version numbers.
|
||||
* This is also used to identify individual product versions, for
|
||||
* a range consisting of a single device.
|
||||
* @bcdDevice_hi: High end of version number range. The range of product
|
||||
* versions is inclusive.
|
||||
* @bDeviceClass: Class of device; numbers are assigned
|
||||
* by the USB forum. Products may choose to implement classes,
|
||||
* or be vendor-specific. Device classes specify behavior of all
|
||||
* the interfaces on a devices.
|
||||
* @bDeviceSubClass: Subclass of device; associated with bDeviceClass.
|
||||
* @bDeviceProtocol: Protocol of device; associated with bDeviceClass.
|
||||
* @bInterfaceClass: Class of interface; numbers are assigned
|
||||
* by the USB forum. Products may choose to implement classes,
|
||||
* or be vendor-specific. Interface classes specify behavior only
|
||||
* of a given interface; other interfaces may support other classes.
|
||||
* @bInterfaceSubClass: Subclass of interface; associated with bInterfaceClass.
|
||||
* @bInterfaceProtocol: Protocol of interface; associated with bInterfaceClass.
|
||||
* @driver_info: Holds information used by the driver. Usually it holds
|
||||
* a pointer to a descriptor understood by the driver, or perhaps
|
||||
* device flags.
|
||||
*
|
||||
* In most cases, drivers will create a table of device IDs by using
|
||||
* USB_DEVICE(), or similar macros designed for that purpose.
|
||||
* They will then export it to userspace using MODULE_DEVICE_TABLE(),
|
||||
* and provide it to the USB core through their usb_driver structure.
|
||||
*
|
||||
* See the usb_match_id() function for information about how matches are
|
||||
* performed. Briefly, you will normally use one of several macros to help
|
||||
* construct these entries. Each entry you provide will either identify
|
||||
* one or more specific products, or will identify a class of products
|
||||
* which have agreed to behave the same. You should put the more specific
|
||||
* matches towards the beginning of your table, so that driver_info can
|
||||
* record quirks of specific products.
|
||||
*/
|
||||
struct usb_device_id
|
||||
{
|
||||
/* which fields to match against? */
|
||||
unsigned short match_flags;
|
||||
|
||||
/* Used for product specific matches; range is inclusive */
|
||||
unsigned short idVendor;
|
||||
unsigned short idProduct;
|
||||
unsigned short bcdDevice_lo;
|
||||
unsigned short bcdDevice_hi;
|
||||
|
||||
/* Used for device class matches */
|
||||
unsigned char bDeviceClass;
|
||||
unsigned char bDeviceSubClass;
|
||||
unsigned char bDeviceProtocol;
|
||||
|
||||
/* Used for interface class matches */
|
||||
unsigned char bInterfaceClass;
|
||||
unsigned char bInterfaceSubClass;
|
||||
unsigned char bInterfaceProtocol;
|
||||
|
||||
/* not matched against */
|
||||
unsigned long driver_info;
|
||||
};
|
||||
|
||||
/* Some useful macros to use to create struct usb_device_id */
|
||||
#define USB_DEVICE_ID_MATCH_VENDOR 0x0001
|
||||
#define USB_DEVICE_ID_MATCH_PRODUCT 0x0002
|
||||
#define USB_DEVICE_ID_MATCH_DEV_LO 0x0004
|
||||
#define USB_DEVICE_ID_MATCH_DEV_HI 0x0008
|
||||
#define USB_DEVICE_ID_MATCH_DEV_CLASS 0x0010
|
||||
#define USB_DEVICE_ID_MATCH_DEV_SUBCLASS 0x0020
|
||||
#define USB_DEVICE_ID_MATCH_DEV_PROTOCOL 0x0040
|
||||
#define USB_DEVICE_ID_MATCH_INT_CLASS 0x0080
|
||||
#define USB_DEVICE_ID_MATCH_INT_SUBCLASS 0x0100
|
||||
#define USB_DEVICE_ID_MATCH_INT_PROTOCOL 0x0200
|
||||
|
||||
/* s390 CCW devices */
|
||||
struct ccw_device_id
|
||||
{
|
||||
unsigned short match_flags; /* which fields to match against */
|
||||
|
||||
unsigned short cu_type; /* control unit type */
|
||||
unsigned short dev_type; /* device type */
|
||||
unsigned char cu_model; /* control unit model */
|
||||
unsigned char dev_model; /* device model */
|
||||
|
||||
unsigned long driver_info;
|
||||
};
|
||||
|
||||
#define CCW_DEVICE_ID_MATCH_CU_TYPE 0x01
|
||||
#define CCW_DEVICE_ID_MATCH_CU_MODEL 0x02
|
||||
#define CCW_DEVICE_ID_MATCH_DEVICE_TYPE 0x04
|
||||
#define CCW_DEVICE_ID_MATCH_DEVICE_MODEL 0x08
|
||||
|
||||
|
||||
#define PNP_ID_LEN 8
|
||||
#define PNP_MAX_DEVICES 8
|
||||
|
||||
struct pnp_device_id
|
||||
{
|
||||
unsigned char id[PNP_ID_LEN];
|
||||
unsigned long driver_data;
|
||||
};
|
||||
|
||||
struct pnp_card_device_id
|
||||
{
|
||||
unsigned char id[PNP_ID_LEN];
|
||||
unsigned long driver_data;
|
||||
struct
|
||||
{
|
||||
unsigned char id[PNP_ID_LEN];
|
||||
} devs[PNP_MAX_DEVICES];
|
||||
};
|
||||
|
||||
|
||||
#define SERIO_ANY 0xff
|
||||
|
||||
struct serio_device_id
|
||||
{
|
||||
unsigned char type;
|
||||
unsigned char extra;
|
||||
unsigned char id;
|
||||
unsigned char proto;
|
||||
};
|
||||
|
||||
|
||||
#endif /* MOD_DEVICETABLE_H */
|
||||
70
include/nbuf.h
Normal file
70
include/nbuf.h
Normal file
@@ -0,0 +1,70 @@
|
||||
/*
|
||||
* File: nbuf.h
|
||||
* Purpose: Definitions for network buffer management
|
||||
*
|
||||
* Notes: These routines implement a network buffer scheme
|
||||
*/
|
||||
|
||||
#ifndef _NBUF_H_
|
||||
#define _NBUF_H_
|
||||
|
||||
#include "bas_types.h"
|
||||
|
||||
/*
|
||||
* Include the Queue structure definitions
|
||||
*/
|
||||
#include "queue.h"
|
||||
|
||||
/*
|
||||
* Number of network buffers to use
|
||||
*/
|
||||
#define NBUF_MAX 30
|
||||
|
||||
/*
|
||||
* Size of each buffer in bytes
|
||||
*/
|
||||
#ifndef NBUF_SZ
|
||||
#define NBUF_SZ 2048
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Defines to identify all the buffer queues
|
||||
* - FREE must always be defined as 0
|
||||
*/
|
||||
#define NBUF_FREE 0 /* available buffers */
|
||||
#define NBUF_TX_RING 1 /* buffers in the Tx BD ring */
|
||||
#define NBUF_RX_RING 2 /* buffers in the Rx BD ring */
|
||||
#define NBUF_SCRATCH 3 /* misc */
|
||||
#define NBUF_MAXQ 4 /* total number of queueus */
|
||||
|
||||
/*
|
||||
* Buffer Descriptor Format
|
||||
*
|
||||
* Fields:
|
||||
* next Pointer to next node in the queue
|
||||
* data Pointer to the data buffer
|
||||
* offset Index into buffer
|
||||
* length Remaining bytes in buffer from (data + offset)
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
QNODE node;
|
||||
uint8_t *data;
|
||||
uint16_t offset;
|
||||
uint16_t length;
|
||||
} NBUF;
|
||||
|
||||
/*
|
||||
* Functions to manipulate the network buffers.
|
||||
*/
|
||||
extern int nbuf_init(void);
|
||||
extern void nbuf_flush(void);
|
||||
extern NBUF *nbuf_alloc (void);
|
||||
extern void nbuf_free(NBUF *);
|
||||
extern NBUF *nbuf_remove(int);
|
||||
extern void nbuf_add(int, NBUF *);
|
||||
extern void nbuf_reset(void);
|
||||
extern void nbuf_debug_dump(void);
|
||||
|
||||
|
||||
#endif /* _NBUF_H_ */
|
||||
32
include/net.h
Normal file
32
include/net.h
Normal file
@@ -0,0 +1,32 @@
|
||||
/*
|
||||
* File: net.h
|
||||
* Purpose: Network definitions and prototypes for BaS.
|
||||
*
|
||||
* Notes:
|
||||
*/
|
||||
|
||||
#ifndef _NET_H
|
||||
#define _NET_H
|
||||
|
||||
|
||||
/*
|
||||
* Include information and prototypes for all protocols
|
||||
*/
|
||||
#include "eth.h"
|
||||
#include "nbuf.h"
|
||||
#include "nif.h"
|
||||
#include "ip.h"
|
||||
#include "icmp.h"
|
||||
#include "arp.h"
|
||||
#include "udp.h"
|
||||
#include "tftp.h"
|
||||
|
||||
#define TIMER_NETWORK 3 /* use GPT3 for network timers */
|
||||
#define TMR_INTC_LVL 3 /* interrupt level for network timer */
|
||||
#define TMR_INTC_PRI 0 /* interrupt priority for network timer */
|
||||
|
||||
extern int net_init(void);
|
||||
|
||||
|
||||
#endif /* _NET_H */
|
||||
|
||||
32
include/net_timer.h
Normal file
32
include/net_timer.h
Normal file
@@ -0,0 +1,32 @@
|
||||
/*
|
||||
* File: net_timer.h
|
||||
* Purpose: Provide a timer use by the BaS network as a timeout
|
||||
* indicator
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _TIMER_H_
|
||||
#define _TIMER_H_
|
||||
|
||||
#include <bas_types.h>
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint8_t ch; /* which channel is this structure for? */
|
||||
uint8_t lvl; /* Interrupt level for this channel */
|
||||
uint8_t pri; /* Interrupt priority for this channel */
|
||||
uint8_t reference; /* timeout indicator */
|
||||
uint32_t gms; /* mode select register value */
|
||||
uint16_t pre; /* prescale value */
|
||||
uint16_t cnt; /* prescaled clocks for timeout */
|
||||
} NET_TIMER;
|
||||
|
||||
|
||||
extern bool timer_init(uint8_t, uint8_t, uint8_t);
|
||||
extern bool timer_set_secs(uint8_t ch, uint32_t secs);
|
||||
extern uint32_t timer_get_reference(uint8_t ch);
|
||||
|
||||
/* Vector numbers for all the timer channels */
|
||||
#define TIMER_VECTOR(x) (126-x)
|
||||
|
||||
#endif /* _TIMER_H_ */
|
||||
90
include/part.h
Normal file
90
include/part.h
Normal file
@@ -0,0 +1,90 @@
|
||||
/*
|
||||
* (C) Copyright 2000-2004
|
||||
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
#ifndef _PART_H
|
||||
#define _PART_H
|
||||
|
||||
typedef unsigned long long uint64_t;
|
||||
typedef unsigned long lbaint_t;
|
||||
|
||||
typedef struct block_dev_desc
|
||||
{
|
||||
int if_type; /* type of the interface */
|
||||
int dev; /* device number */
|
||||
unsigned char part_type; /* partition type */
|
||||
unsigned char target; /* target SCSI ID */
|
||||
unsigned char lun; /* target LUN */
|
||||
unsigned char type; /* device type */
|
||||
unsigned char removable; /* removable device */
|
||||
#ifdef CONFIG_LBA48
|
||||
unsigned char lba48; /* device can use 48bit addr (ATA/ATAPI v7) */
|
||||
#endif
|
||||
lbaint_t lba; /* number of blocks */
|
||||
unsigned long blksz; /* block size */
|
||||
char vendor [40+1]; /* IDE model, SCSI Vendor */
|
||||
char product[20+1]; /* IDE Serial no, SCSI product */
|
||||
char revision[8+1]; /* firmware revision */
|
||||
long (*block_read)(int dev, unsigned long start, lbaint_t blkcnt, void *buffer);
|
||||
long (*block_write)(int dev, unsigned long start, lbaint_t blkcnt, const void *buffer);
|
||||
void *priv; /* driver private struct pointer */
|
||||
}block_dev_desc_t;
|
||||
|
||||
/* Interface types: */
|
||||
#define IF_TYPE_UNKNOWN 0
|
||||
#define IF_TYPE_IDE 1
|
||||
#define IF_TYPE_SCSI 2
|
||||
#define IF_TYPE_ATAPI 3
|
||||
#define IF_TYPE_USB 4
|
||||
#define IF_TYPE_DOC 5
|
||||
#define IF_TYPE_MMC 6
|
||||
#define IF_TYPE_SD 7
|
||||
#define IF_TYPE_SATA 8
|
||||
|
||||
/* Part types */
|
||||
#define PART_TYPE_UNKNOWN 0x00
|
||||
#define PART_TYPE_MAC 0x01
|
||||
#define PART_TYPE_DOS 0x02
|
||||
#define PART_TYPE_ISO 0x03
|
||||
#define PART_TYPE_AMIGA 0x04
|
||||
#define PART_TYPE_EFI 0x05
|
||||
#define PART_TYPE_GEMDOS 0x06
|
||||
|
||||
/*
|
||||
* Type string for U-Boot bootable partitions
|
||||
*/
|
||||
#define BOOT_PART_TYPE "U-Boot" /* primary boot partition type */
|
||||
#define BOOT_PART_COMP "PPCBoot" /* PPCBoot compatibility type */
|
||||
|
||||
/* device types */
|
||||
#define DEV_TYPE_UNKNOWN 0xff /* not connected */
|
||||
#define DEV_TYPE_HARDDISK 0x00 /* harddisk */
|
||||
#define DEV_TYPE_TAPE 0x01 /* Tape */
|
||||
#define DEV_TYPE_CDROM 0x05 /* CD-ROM */
|
||||
#define DEV_TYPE_OPDISK 0x07 /* optical disk */
|
||||
|
||||
void print_part(block_dev_desc_t *dev_desc);
|
||||
void init_part(block_dev_desc_t *dev_desc);
|
||||
void dev_print(block_dev_desc_t *dev_desc);
|
||||
|
||||
int fat_register_device(block_dev_desc_t *dev_desc, int part_no, unsigned long *part_type, unsigned long *part_offset, unsigned long *part_size);
|
||||
|
||||
#endif /* _PART_H */
|
||||
360
include/pci.h
Normal file
360
include/pci.h
Normal file
@@ -0,0 +1,360 @@
|
||||
#ifndef _PCI_H_
|
||||
#define _PCI_H_
|
||||
|
||||
/*
|
||||
* This file is part of BaS_gcc.
|
||||
*
|
||||
* BaS_gcc is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* BaS_gcc is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* Created on: 26.02.2013
|
||||
* Author: Markus Fröschle
|
||||
*/
|
||||
|
||||
#include <bas_types.h>
|
||||
#include "util.h" /* for swpX() */
|
||||
|
||||
#define PCI_MEMORY_OFFSET 0x80000000
|
||||
#define PCI_MEMORY_SIZE 0x40000000 /* 1 GByte PCI memory window */
|
||||
#define PCI_IO_OFFSET 0xD0000000
|
||||
#define PCI_IO_SIZE 0x10000000 /* 256 MByte PCI I/O window */
|
||||
|
||||
#define PCI_LANESWAP_B(x) (x ^ 3)
|
||||
#define PCI_LANESWAP_W(x) (x ^ 2)
|
||||
#define PCI_LANESWAP_L(x) (x) /* for completeness only */
|
||||
/*
|
||||
* Note: the byte offsets are in little endian format, so for pci_xxx_config_byte()
|
||||
* accesses to hit the right offset, you'll need to wrap them into PCI_LANESWAP_B()
|
||||
* and for pci_xxx_config_word() into PCI_LANESWAP_W()
|
||||
*/
|
||||
#define PCIIDR 0x00 /* PCI Configuration ID Register */
|
||||
#define PCICSR 0x04 /* PCI Command/Status Register */
|
||||
#define PCICR 0x06 /* PCI Command Register */
|
||||
#define PCISR 0x04 /* PCI Status Register */
|
||||
#define PCIREV 0x0B /* PCI Revision ID Register */
|
||||
#define PCICCR 0x08 /* PCI Class Code Register */
|
||||
#define PCICLSR 0x0F /* PCI Cache Line Size Register */
|
||||
#define PCILTR 0x0E /* PCI Latency Timer Register */
|
||||
#define PCIHTR 0x0D /* PCI Header Type Register */
|
||||
#define PCIBISTR 0x0C /* PCI Build-In Self Test Register */
|
||||
|
||||
#define PCIBAR0 0x10 /* PCI Base Address Register for Memory
|
||||
Accesses to Local, Runtime, and DMA */
|
||||
#define PCIBAR1 0x14 /* PCI Base Address Register for I/O
|
||||
Accesses to Local, Runtime, and DMA */
|
||||
#define PCIBAR2 0x18 /* PCI Base Address Register for Memory
|
||||
Accesses to Local Address Space 0 */
|
||||
#define PCIBAR3 0x1C /* PCI Base Address Register for Memory
|
||||
Accesses to Local Address Space 1 */
|
||||
#define PCIBAR4 0x20 /* PCI Base Address Register, reserved */
|
||||
#define PCIBAR5 0x24 /* PCI Base Address Register, reserved */
|
||||
#define PCICIS 0x28 /* PCI Cardbus CIS Pointer, not support*/
|
||||
#define PCISVID 0x2E /* PCI Subsystem Vendor ID */
|
||||
#define PCISID 0x2D /* PCI Subsystem ID */
|
||||
#define PCIERBAR 0x30 /* PCI Expansion ROM Base Register */
|
||||
#define CAP_PTR 0x34 /* New Capability Pointer */
|
||||
#define PCIILR 0x3F /* PCI Interrupt Line Register */
|
||||
#define PCIIPR 0x3E /* PCI Interrupt Pin Register */
|
||||
#define PCIMGR 0x3D /* PCI Min_Gnt Register */
|
||||
#define PCIMLR 0x3C /* PCI Max_Lat Register */
|
||||
#define PMCAPID 0x40 /* Power Management Capability ID */
|
||||
#define PMNEXT 0x41 /* Power Management Next Capability
|
||||
Pointer */
|
||||
#define PMC 0x42 /* Power Management Capabilities */
|
||||
#define PMCSR 0x44 /* Power Management Control/Status */
|
||||
#define PMCSR_BSE 0x46 /* PMCSR Bridge Support Extensions */
|
||||
#define PMDATA 0x47 /* Power Management Data */
|
||||
#define HS_CNTL 0x48 /* Hot Swap Control */
|
||||
#define HS_NEXT 0x49 /* Hot Swap Next Capability Pointer */
|
||||
#define HS_CSR 0x4A /* Hot Swap Control/Status */
|
||||
#define PVPDCNTL 0x4C /* PCI Vital Product Data Control */
|
||||
#define PVPD_NEXT 0x4D /* PCI Vital Product Data Next
|
||||
Capability Pointer */
|
||||
#define PVPDAD 0x4E /* PCI Vital Product Data Address */
|
||||
#define PVPDATA 0x50 /* PCI VPD Data */
|
||||
|
||||
/*
|
||||
* bit definitions for PCICSR lower half (Command Register)
|
||||
*/
|
||||
#define PCICR_IO (1 << 0) /* if set: device responds to I/O space accesses */
|
||||
#define PCICR_MEMORY (1 << 1) /* if set: device responds to memory space accesses */
|
||||
#define PCICR_MASTER (1 << 2) /* if set: device is master */
|
||||
#define PCICR_SPECIAL (1 << 3) /* if set: device reacts on special cycles */
|
||||
#define PCICR_MEMWI (1 << 4) /* if set: device deals with memory write and invalidate */
|
||||
#define PCICR_VGA_SNOOP (1 << 5) /* if set: capable of palette snoop */
|
||||
#define PCICR_PERR (1 << 6) /* if set: reacts to parity errors */
|
||||
#define PCICR_STEPPING (1 << 7) /* if set: stepping enabled */
|
||||
#define PCICR_SERR (1 << 8) /* if set: SERR pin enabled */
|
||||
#define PCICR_FAST_BTOB_E (1 << 9) /* if set: fast back-to-back enabled */
|
||||
#define PCICR_INT_DISABLE (1 << 10) /* if set: disable interrupts from this device */
|
||||
/*
|
||||
* bit definitions for PCICSR upper half (Status Register)
|
||||
*/
|
||||
#define PCISR_INTERRUPT (1 << 3) /* device requested interrupt */
|
||||
#define PCISR_CAPABILITIES (1 << 4) /* if set, capabilities pointer is valid */
|
||||
#define PCISR_66MHZ (1 << 5) /* 66 MHz capable */
|
||||
#define PCISR_UDF (1 << 6) /* UDF supported */
|
||||
#define PCISR_FAST_BTOB (1 << 7) /* Fast back-to-back enabled */
|
||||
#define PCISR_DPARITY_ERROR (1 << 8) /* data parity error detected */
|
||||
|
||||
#define PCISR_T_ABORT_S (1 << 11) /* target abort signaled */
|
||||
#define PCISR_T_ABORT_R (1 << 12) /* target abort received */
|
||||
#define PCISR_M_ABORT_R (1 << 13) /* master abort received */
|
||||
#define PCISR_S_ERROR_S (1 << 14) /* system error signaled */
|
||||
#define PCISR_PARITY_ERR (1 << 15) /* data parity error */
|
||||
|
||||
/* Header type 1 (PCI-to-PCI bridges) */
|
||||
#define PCI_PRIMARY_BUS 0x1B /* Primary bus number */
|
||||
#define PCI_SECONDARY_BUS 0x1A /* Secondary bus number */
|
||||
#define PCI_SUBORDINATE_BUS 0x19 /* Highest bus number behind the bridge */
|
||||
#define PCI_SEC_LATENCY_TIMER 0x18 /* Latency timer for secondary interface */
|
||||
#define PCI_IO_BASE 0x1C /* I/O range behind the bridge */
|
||||
#define PCI_IO_LIMIT 0x1D
|
||||
#define PCI_SEC_STATUS 0x1C /* Secondary status register, only bit 14 used */
|
||||
#define PCI_MEMORY_BASE 0x20 /* Memory range behind */
|
||||
#define PCI_MEMORY_LIMIT 0x22
|
||||
#define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
|
||||
#define PCI_PREF_MEMORY_LIMIT 0x26
|
||||
#define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */
|
||||
#define PCI_PREF_LIMIT_UPPER32 0x2C
|
||||
#define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */
|
||||
#define PCI_IO_LIMIT_UPPER16 0x32
|
||||
#define PCI_BRIDGE_CONTROL 0x3E /* Bridge Control */
|
||||
|
||||
struct pci_rd /* structure of resource descriptor */
|
||||
{
|
||||
unsigned short next; /* length of the following structure */
|
||||
unsigned short flags; /* type of resource and misc. flags */
|
||||
unsigned long start; /* start-address of resource */
|
||||
unsigned long length; /* length of resource */
|
||||
unsigned long offset; /* offset PCI to phys. CPU Address */
|
||||
unsigned long dmaoffset; /* offset for DMA-transfers */
|
||||
};
|
||||
|
||||
typedef struct /* structure of address conversion */
|
||||
{
|
||||
unsigned long adr; /* calculated address (CPU<->PCI) */
|
||||
unsigned long len; /* length of memory range */
|
||||
} PCI_CONV_ADR;
|
||||
|
||||
/******************************************************************************/
|
||||
/* PCI-BIOS Error Codes */
|
||||
/******************************************************************************/
|
||||
#define PCI_SUCCESSFUL 0 /* everything's fine */
|
||||
#define PCI_FUNC_NOT_SUPPORTED -2 /* function not supported */
|
||||
#define PCI_BAD_VENDOR_ID -3 /* wrong Vendor ID */
|
||||
#define PCI_DEVICE_NOT_FOUND -4 /* PCI-Device not found */
|
||||
#define PCI_BAD_REGISTER_NUMBER -5 /* wrong register number */
|
||||
#define PCI_SET_FAILED -6 /* reserved for later use */
|
||||
#define PCI_BUFFER_TOO_SMALL -7 /* reserved for later use */
|
||||
#define PCI_GENERAL_ERROR -8 /* general BIOS error code */
|
||||
#define PCI_BAD_HANDLE -9 /* wrong/unknown PCI-handle */
|
||||
|
||||
/******************************************************************************/
|
||||
/* Flags used in Resource-Descriptor */
|
||||
/******************************************************************************/
|
||||
#define FLG_IO 0x4000 /* Ressource in IO range */
|
||||
#define FLG_ROM 0x2000 /* Expansion ROM */
|
||||
#define FLG_LAST 0x8000 /* last ressource */
|
||||
#define FLG_8BIT 0x0100 /* 8 bit accesses allowed */
|
||||
#define FLG_16BIT 0x0200 /* 16 bit accesses allowed */
|
||||
#define FLG_32BIT 0x0400 /* 32 bit accesses allowed */
|
||||
#define FLG_ENDMASK 0x000F /* mask for byte ordering */
|
||||
|
||||
/******************************************************************************/
|
||||
/* Values used in FLG_ENDMASK for Byte Ordering */
|
||||
/******************************************************************************/
|
||||
#define ORD_MOTOROLA 0 /* Motorola (big endian) */
|
||||
#define ORD_INTEL_AS 1 /* Intel (little endian), addr.swapped */
|
||||
#define ORD_INTEL_LS 2 /* Intel (little endian), lane swapped */
|
||||
#define ORD_UNKNOWN 15 /* unknown (BIOS-calls allowed only) */
|
||||
|
||||
/******************************************************************************/
|
||||
/* Status Info used in Device-Descriptor */
|
||||
/******************************************************************************/
|
||||
#define DEVICE_FREE 0 /* Device is not used */
|
||||
#define DEVICE_USED 1 /* Device is used by another driver */
|
||||
#define DEVICE_CALLBACK 2 /* used, but driver can be cancelled */
|
||||
#define DEVICE_AVAILABLE 3 /* used, not available */
|
||||
#define NO_DEVICE -1 /* no device detected */
|
||||
|
||||
/* PCI configuration space macros */
|
||||
|
||||
/* register 0x00 macros */
|
||||
#define PCI_DEVICE_ID(i) (uint16_t)(((i) & 0xffff0000) >> 16)
|
||||
#define PCI_VENDOR_ID(i) (uint16_t) ((i) & 0xffff)
|
||||
|
||||
/* register 0x04 macros */
|
||||
#define PCI_STATUS(i) ((i) & 0xffff)
|
||||
#define PCI_COMMAND(i) (((i) >> 16) & 0xffff)
|
||||
|
||||
/* register 0x08 macros (use on little endian value!) */
|
||||
#define PCI_CLASS_CODE(i) (((i) & 0x00ff0000) >> 16)
|
||||
#define PCI_SUBCLASS(i) (((i) & 0x0000ff00) >> 8)
|
||||
#define PCI_PROG_IF(i) (((i) & 0x000000ff) >> 0)
|
||||
#define PCI_REVISION_ID(i) (((i) & 0xff000000) >> 24)
|
||||
|
||||
/* register 0x0c macros */
|
||||
#define PCI_BIST(i) (((i) & 0xff000000) >> 24)
|
||||
#define PCI_HEADER_TYPE(i) (((i) & 0x00ff0000) >> 16)
|
||||
#define PCI_LAT_TIMER(i) (((i) & 0x0000ff00) >> 8)
|
||||
#define PCI_CACHELINE_SIZE(i) (((i) & 0x000000ff))
|
||||
|
||||
/* register 0x2c macros */
|
||||
#define PCI_SUBSYS_ID(i) ((i) & 0xffff0000) >> 16)
|
||||
#define PCI_SUBSYS_VID(i) ((i) & 0xffff))
|
||||
|
||||
/* register 0x34 macros */
|
||||
#define PCI_CAPABILITIES(i) ((i) & 0xff)
|
||||
|
||||
/* register 0x3c macros */
|
||||
#define PCI_MAX_LATENCY(i) (((i) & 0xff000000) >> 24)
|
||||
#define PCI_MIN_GRANT(i) (((i) & 0xff0000) >> 16)
|
||||
#define PCI_INTERRUPT_PIN(i) (((i) & 0xff00) >> 8)
|
||||
#define PCI_INTERRUPT_LINE(i) (((i)) & 0xff)
|
||||
|
||||
#define IS_PCI_MEM_BAR(i) ((i) & 1) == 0
|
||||
#define IS_PCI_IO_BAR(i) ((i) & 1) == 1
|
||||
#define PCI_MEMBAR_TYPE(i) (((i) & 0x6) >> 1)
|
||||
#define PCI_IOBAR_ADR(i) (((i) & 0xfffffffc))
|
||||
#define PCI_MEMBAR_ADR(i) (((i) & 0xfffffff0))
|
||||
|
||||
extern void init_eport(void);
|
||||
extern void init_xlbus_arbiter(void);
|
||||
extern void init_pci(void);
|
||||
extern int pci_handle2index(int32_t handle);
|
||||
|
||||
extern int32_t pci_find_device(uint16_t device_id, uint16_t vendor_id, int index);
|
||||
extern int32_t pci_find_classcode(uint32_t classcode, int index);
|
||||
|
||||
extern int32_t pci_get_interrupt_cause(void);
|
||||
extern int32_t pci_call_interrupt_chain(int32_t handle, int32_t data);
|
||||
|
||||
/*
|
||||
* match bits for pci_find_classcode()
|
||||
*/
|
||||
#define PCI_FIND_BASE_CLASS (1 << 26)
|
||||
#define PCI_FIND_SUB_CLASS (1 << 25)
|
||||
#define PCI_FIND_PROG_IF (1 << 24)
|
||||
|
||||
extern uint32_t pci_read_config_longword(int32_t handle, int offset);
|
||||
extern uint16_t pci_read_config_word(int32_t handle, int offset);
|
||||
extern uint8_t pci_read_config_byte(int32_t handle, int offset);
|
||||
|
||||
extern int32_t pci_write_config_longword(int32_t handle, int offset, uint32_t value);
|
||||
extern int32_t pci_write_config_word(int32_t handle, int offset, uint16_t value);
|
||||
extern int32_t pci_write_config_byte(int32_t handle, int offset, uint8_t value);
|
||||
|
||||
typedef int (*pci_interrupt_handler)(int param);
|
||||
|
||||
extern int32_t pci_hook_interrupt(int32_t handle, void *handler, void *parameter);
|
||||
extern int32_t pci_unhook_interrupt(int32_t handle);
|
||||
|
||||
extern struct pci_rd *pci_get_resource(int32_t handle);
|
||||
|
||||
/*
|
||||
* Not implemented PCI_BIOS functions
|
||||
*/
|
||||
extern uint8_t pci_fast_read_config_byte(int32_t handle, uint16_t reg);
|
||||
extern uint16_t pci_fast_read_config_word(int32_t handle, uint16_t reg);
|
||||
extern uint32_t pci_fast_read_config_longword(int32_t handle, uint16_t reg);
|
||||
extern int32_t pci_special_cycle(uint16_t bus, uint32_t data);
|
||||
extern int32_t pci_get_routing(int32_t handle);
|
||||
extern int32_t pci_set_interrupt(int32_t handle);
|
||||
extern int32_t pci_get_card_used(int32_t handle, uint32_t *address);
|
||||
extern int32_t pci_set_card_used(int32_t handle, uint32_t *callback);
|
||||
extern int32_t pci_read_mem_byte(int32_t handle, uint32_t offset, uint8_t *address);
|
||||
extern int32_t pci_read_mem_word(int32_t handle, uint32_t offset, uint16_t *address);
|
||||
extern int32_t pci_read_mem_longword(int32_t handle, uint32_t offset, uint32_t *address);
|
||||
extern uint8_t pci_fast_read_mem_byte(int32_t handle, uint32_t offset);
|
||||
extern uint16_t pci_fast_read_mem_word(int32_t handle, uint32_t offset);
|
||||
extern uint32_t pci_fast_read_mem_longword(int32_t handle, uint32_t offset);
|
||||
extern int32_t pci_write_mem_byte(int32_t handle, uint32_t offset, uint16_t val);
|
||||
extern int32_t pci_write_mem_word(int32_t handle, uint32_t offset, uint16_t val);
|
||||
extern int32_t pci_write_mem_longword(int32_t handle, uint32_t offset, uint32_t val);
|
||||
extern int32_t pci_read_io_byte(int32_t handle, uint32_t offset, uint8_t *address);
|
||||
extern int32_t pci_read_io_word(int32_t handle, uint32_t offset, uint16_t *address);
|
||||
extern int32_t pci_read_io_longword(int32_t handle, uint32_t offset, uint32_t *address);
|
||||
extern uint8_t pci_fast_read_io_byte(int32_t handle, uint32_t offset);
|
||||
extern uint16_t pci_fast_read_io_word(int32_t handle, uint32_t offset);
|
||||
extern uint32_t pci_fast_read_io_longword(int32_t handle, uint32_t offset);
|
||||
extern int32_t pci_write_io_byte(int32_t handle, uint32_t offset, uint16_t val);
|
||||
extern int32_t pci_write_io_word(int32_t handle, uint32_t offset, uint16_t val);
|
||||
extern int32_t pci_write_io_longword(int32_t handle, uint32_t offset, uint32_t val);
|
||||
extern int32_t pci_get_machine_id(void);
|
||||
extern int32_t pci_get_pagesize(void);
|
||||
extern int32_t pci_virt_to_bus(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer);
|
||||
extern int32_t pci_bus_to_virt(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer);
|
||||
extern int32_t pci_virt_to_phys(uint32_t address, PCI_CONV_ADR *pointer);
|
||||
extern int32_t pci_phys_to_virt(uint32_t address, PCI_CONV_ADR *pointer);
|
||||
|
||||
/*
|
||||
* prototypes for PCI wrapper routines
|
||||
*/
|
||||
extern int32_t wrapper_find_pci_device(uint32_t id, uint16_t index);
|
||||
extern int32_t wrapper_find_pci_classcode(uint32_t class, uint16_t index);
|
||||
extern int32_t wrapper_read_config_byte(int32_t handle, uint16_t reg, uint8_t *address);
|
||||
extern int32_t wrapper_read_config_word(int32_t handle, uint16_t reg, uint16_t *address);
|
||||
extern int32_t wrapper_read_config_longword(int32_t handle, uint16_t reg, uint32_t *address);
|
||||
extern uint8_t wrapper_fast_read_config_byte(int32_t handle, uint16_t reg);
|
||||
extern uint16_t wrapper_fast_read_config_word(int32_t handle, uint16_t reg);
|
||||
extern uint32_t wrapper_fast_read_config_longword(int32_t handle, uint16_t reg);
|
||||
extern int32_t wrapper_write_config_byte(int32_t handle, uint16_t reg, uint16_t val);
|
||||
extern int32_t wrapper_write_config_word(int32_t handle, uint16_t reg, uint16_t val);
|
||||
extern int32_t wrapper_write_config_longword(int32_t handle, uint16_t reg, uint32_t val);
|
||||
extern int32_t wrapper_hook_interrupt(int32_t handle, uint32_t *routine, uint32_t *parameter);
|
||||
extern int32_t wrapper_unhook_interrupt(int32_t handle);
|
||||
extern int32_t wrapper_special_cycle(uint16_t bus, uint32_t data);
|
||||
extern int32_t wrapper_get_routing(int32_t handle);
|
||||
extern int32_t wrapper_set_interrupt(int32_t handle);
|
||||
extern int32_t wrapper_get_resource(int32_t handle);
|
||||
extern int32_t wrapper_get_card_used(int32_t handle, uint32_t *address);
|
||||
extern int32_t wrapper_set_card_used(int32_t handle, uint32_t *callback);
|
||||
extern int32_t wrapper_read_mem_byte(int32_t handle, uint32_t offset, uint8_t *address);
|
||||
extern int32_t wrapper_read_mem_word(int32_t handle, uint32_t offset, uint16_t *address);
|
||||
extern int32_t wrapper_read_mem_longword(int32_t handle, uint32_t offset, uint32_t *address);
|
||||
extern uint8_t wrapper_fast_read_mem_byte(int32_t handle, uint32_t offset);
|
||||
extern uint16_t wrapper_fast_read_mem_word(int32_t handle, uint32_t offset);
|
||||
extern uint32_t wrapper_fast_read_mem_longword(int32_t handle, uint32_t offset);
|
||||
extern int32_t wrapper_write_mem_byte(int32_t handle, uint32_t offset, uint16_t val);
|
||||
extern int32_t wrapper_write_mem_word(int32_t handle, uint32_t offset, uint16_t val);
|
||||
extern int32_t wrapper_write_mem_longword(int32_t handle, uint32_t offset, uint32_t val);
|
||||
extern int32_t wrapper_read_io_byte(int32_t handle, uint32_t offset, uint8_t *address);
|
||||
extern int32_t wrapper_read_io_word(int32_t handle, uint32_t offset, uint16_t *address);
|
||||
extern int32_t wrapper_read_io_longword(int32_t handle, uint32_t offset, uint32_t *address);
|
||||
extern uint8_t wrapper_fast_read_io_byte(int32_t handle, uint32_t offset);
|
||||
extern uint16_t wrapper_fast_read_io_word(int32_t handle, uint32_t offset);
|
||||
extern uint32_t wrapper_fast_read_io_longword(int32_t handle, uint32_t offset);
|
||||
extern int32_t wrapper_write_io_byte(int32_t handle, uint32_t offset, uint16_t val);
|
||||
extern int32_t wrapper_write_io_word(int32_t handle, uint32_t offset, uint16_t val);
|
||||
extern int32_t wrapper_write_io_longword(int32_t handle, uint32_t offset, uint32_t val);
|
||||
extern int32_t wrapper_get_machine_id(void);
|
||||
extern int32_t wrapper_get_pagesize(void);
|
||||
extern int32_t wrapper_virt_to_bus(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer);
|
||||
extern int32_t wrapper_bus_to_virt(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer);
|
||||
extern int32_t wrapper_virt_to_phys(uint32_t address, PCI_CONV_ADR *pointer);
|
||||
extern int32_t wrapper_phys_to_virt(uint32_t address, PCI_CONV_ADR *pointer);
|
||||
|
||||
#define PCI_MK_CONF_ADDR(bus, device, function) (MCF_PCI_PCICAR_E | \
|
||||
((bus) << 16) | \
|
||||
((device << 8) | \
|
||||
(function))
|
||||
|
||||
#define PCI_HANDLE(bus, slot, function) (0 | ((bus & 0xff) << 10 | (slot & 0x1f) << 3 | (function & 7)))
|
||||
#define PCI_BUS_FROM_HANDLE(h) (((h) & 0xff00) >> 10)
|
||||
#define PCI_DEVICE_FROM_HANDLE(h) (((h) & 0xf8) >> 3)
|
||||
#define PCI_FUNCTION_FROM_HANDLE(h) (((h) & 0x7))
|
||||
|
||||
extern void pci_dump_registers(int32_t handle);
|
||||
|
||||
#endif /* _PCI_H_ */
|
||||
2626
include/pci_ids.h
Normal file
2626
include/pci_ids.h
Normal file
File diff suppressed because it is too large
Load Diff
5648
include/radeon_reg.h
Normal file
5648
include/radeon_reg.h
Normal file
File diff suppressed because it is too large
Load Diff
676
include/radeonfb.h
Normal file
676
include/radeonfb.h
Normal file
@@ -0,0 +1,676 @@
|
||||
#ifndef __RADEONFB_H__
|
||||
#define __RADEONFB_H__
|
||||
|
||||
#include <bas_string.h>
|
||||
#include "pci.h"
|
||||
#include "mod_devicetable.h"
|
||||
#include "pci_ids.h"
|
||||
#include "fb.h"
|
||||
#include "i2c.h"
|
||||
#include "i2c-algo-bit.h"
|
||||
#include "util.h" /* for swpX() */
|
||||
#include "wait.h"
|
||||
#include "video.h"
|
||||
|
||||
// #define RADEON_TILING
|
||||
|
||||
//#include "radeon_theatre.h"
|
||||
|
||||
#include "radeon_reg.h"
|
||||
|
||||
/* Buffer are aligned on 4096 byte boundaries */
|
||||
#define RADEON_BUFFER_ALIGN 0x00000fff
|
||||
|
||||
#define RADEON_IDLE_RETRY 16 /* Fall out of idle loops after this count */
|
||||
#define RADEON_TIMEOUT 2000000 /* Fall out of wait loops after this count */
|
||||
#define RADEON_MMIOSIZE 0x80000
|
||||
|
||||
#define RADEON_ALIGN(x,bytes) (((x) + ((bytes) - 1)) & ~((bytes) - 1))
|
||||
|
||||
#define ATY_RADEON_LCD_ON 0x00000001
|
||||
#define ATY_RADEON_CRT_ON 0x00000002
|
||||
|
||||
#define FBIO_RADEON_GET_MIRROR 0x80044003
|
||||
#define FBIO_RADEON_SET_MIRROR 0xC0044004
|
||||
|
||||
/***************************************************************
|
||||
* Most of the definitions here are adapted right from XFree86 *
|
||||
***************************************************************/
|
||||
|
||||
/*
|
||||
* Chip families. Must fit in the low 16 bits of a int32_t word
|
||||
*/
|
||||
enum radeon_family
|
||||
{
|
||||
CHIP_FAMILY_UNKNOW,
|
||||
CHIP_FAMILY_LEGACY,
|
||||
CHIP_FAMILY_RADEON,
|
||||
CHIP_FAMILY_RV100,
|
||||
CHIP_FAMILY_RS100, /* U1 (IGP320M) or A3 (IGP320)*/
|
||||
CHIP_FAMILY_RV200,
|
||||
CHIP_FAMILY_RS200, /* U2 (IGP330M/340M/350M) or A4 (IGP330/340/345/350), RS250 (IGP 7000) */
|
||||
CHIP_FAMILY_R200,
|
||||
CHIP_FAMILY_RV250,
|
||||
CHIP_FAMILY_RS300, /* Radeon 9000 IGP */
|
||||
CHIP_FAMILY_RV280,
|
||||
CHIP_FAMILY_R300,
|
||||
CHIP_FAMILY_R350,
|
||||
CHIP_FAMILY_RV350,
|
||||
CHIP_FAMILY_RV380, /* RV370/RV380/M22/M24 */
|
||||
CHIP_FAMILY_R420, /* R420/R423/M18 */
|
||||
CHIP_FAMILY_LAST,
|
||||
};
|
||||
|
||||
#define IS_RV100_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_RV100) || \
|
||||
((rinfo)->family == CHIP_FAMILY_RV200) || \
|
||||
((rinfo)->family == CHIP_FAMILY_RS100) || \
|
||||
((rinfo)->family == CHIP_FAMILY_RS200) || \
|
||||
((rinfo)->family == CHIP_FAMILY_RV250) || \
|
||||
((rinfo)->family == CHIP_FAMILY_RV280) || \
|
||||
((rinfo)->family == CHIP_FAMILY_RS300))
|
||||
|
||||
|
||||
#define IS_R300_VARIANT(rinfo) (((rinfo)->family == CHIP_FAMILY_R300) || \
|
||||
((rinfo)->family == CHIP_FAMILY_RV350) || \
|
||||
((rinfo)->family == CHIP_FAMILY_R350) || \
|
||||
((rinfo)->family == CHIP_FAMILY_RV380) || \
|
||||
((rinfo)->family == CHIP_FAMILY_R420))
|
||||
|
||||
/*
|
||||
* Chip flags
|
||||
*/
|
||||
enum radeon_chip_flags
|
||||
{
|
||||
CHIP_FAMILY_MASK = 0x0000ffffUL,
|
||||
CHIP_FLAGS_MASK = 0xffff0000UL,
|
||||
CHIP_IS_MOBILITY = 0x00010000UL,
|
||||
CHIP_IS_IGP = 0x00020000UL,
|
||||
CHIP_HAS_CRTC2 = 0x00040000UL,
|
||||
};
|
||||
|
||||
/*
|
||||
* Errata workarounds
|
||||
*/
|
||||
enum radeon_errata
|
||||
{
|
||||
CHIP_ERRATA_R300_CG = 0x00000001,
|
||||
CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
|
||||
CHIP_ERRATA_PLL_DELAY = 0x00000004,
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* Monitor types
|
||||
*/
|
||||
enum radeon_montype
|
||||
{
|
||||
MT_NONE = 0,
|
||||
MT_CRT, /* CRT */
|
||||
MT_LCD, /* LCD */
|
||||
MT_DFP, /* DVI */
|
||||
MT_CTV, /* composite TV */
|
||||
MT_STV /* S-Video out */
|
||||
};
|
||||
|
||||
/*
|
||||
* DDC i2c ports
|
||||
*/
|
||||
enum ddc_type
|
||||
{
|
||||
ddc_none,
|
||||
ddc_monid,
|
||||
ddc_dvi,
|
||||
ddc_vga,
|
||||
ddc_crt2,
|
||||
};
|
||||
|
||||
/*
|
||||
* Connector types
|
||||
*/
|
||||
enum conn_type
|
||||
{
|
||||
conn_none,
|
||||
conn_proprietary,
|
||||
conn_crt,
|
||||
conn_DVI_I,
|
||||
conn_DVI_D,
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* PLL infos
|
||||
*/
|
||||
struct pll_info
|
||||
{
|
||||
int32_t ppll_max;
|
||||
int32_t ppll_min;
|
||||
int32_t sclk, mclk;
|
||||
int32_t ref_div;
|
||||
int32_t ref_clk;
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* This structure contains the various registers manipulated by this
|
||||
* driver for setting or restoring a mode. It's mostly copied from
|
||||
* XFree's RADEONSaveRec structure. A few chip settings might still be
|
||||
* tweaked without beeing reflected or saved in these registers though
|
||||
*/
|
||||
struct radeon_regs
|
||||
{
|
||||
/* Common registers */
|
||||
uint32_t ovr_clr;
|
||||
uint32_t ovr_wid_left_right;
|
||||
uint32_t ovr_wid_top_bottom;
|
||||
uint32_t ov0_scale_cntl;
|
||||
uint32_t mpp_tb_config;
|
||||
uint32_t mpp_gp_config;
|
||||
uint32_t subpic_cntl;
|
||||
uint32_t viph_control;
|
||||
uint32_t i2c_cntl_1;
|
||||
uint32_t gen_int_cntl;
|
||||
uint32_t cap0_trig_cntl;
|
||||
uint32_t cap1_trig_cntl;
|
||||
uint32_t bus_cntl;
|
||||
uint32_t surface_cntl;
|
||||
uint32_t bios_5_scratch;
|
||||
|
||||
/* Other registers to save for VT switches or driver load/unload */
|
||||
uint32_t dp_datatype;
|
||||
uint32_t rbbm_soft_reset;
|
||||
uint32_t clock_cntl_index;
|
||||
uint32_t amcgpio_en_reg;
|
||||
uint32_t amcgpio_mask;
|
||||
|
||||
/* Surface/tiling registers */
|
||||
uint32_t surf_lower_bound[8];
|
||||
uint32_t surf_upper_bound[8];
|
||||
uint32_t surf_info[8];
|
||||
|
||||
/* CRTC registers */
|
||||
uint32_t crtc_gen_cntl;
|
||||
uint32_t crtc_ext_cntl;
|
||||
uint32_t dac_cntl;
|
||||
uint32_t crtc_h_total_disp;
|
||||
uint32_t crtc_h_sync_strt_wid;
|
||||
uint32_t crtc_v_total_disp;
|
||||
uint32_t crtc_v_sync_strt_wid;
|
||||
uint32_t crtc_offset;
|
||||
uint32_t crtc_offset_cntl;
|
||||
uint32_t crtc_pitch;
|
||||
uint32_t disp_merge_cntl;
|
||||
uint32_t grph_buffer_cntl;
|
||||
uint32_t crtc_more_cntl;
|
||||
|
||||
/* CRTC2 registers */
|
||||
uint32_t crtc2_gen_cntl;
|
||||
uint32_t dac2_cntl;
|
||||
uint32_t disp_output_cntl;
|
||||
uint32_t disp_hw_debug;
|
||||
uint32_t disp2_merge_cntl;
|
||||
uint32_t grph2_buffer_cntl;
|
||||
uint32_t crtc2_h_total_disp;
|
||||
uint32_t crtc2_h_sync_strt_wid;
|
||||
uint32_t crtc2_v_total_disp;
|
||||
uint32_t crtc2_v_sync_strt_wid;
|
||||
uint32_t crtc2_offset;
|
||||
uint32_t crtc2_offset_cntl;
|
||||
uint32_t crtc2_pitch;
|
||||
|
||||
/* Flat panel regs */
|
||||
uint32_t fp_crtc_h_total_disp;
|
||||
uint32_t fp_crtc_v_total_disp;
|
||||
uint32_t fp_gen_cntl;
|
||||
uint32_t fp2_gen_cntl;
|
||||
uint32_t fp_h_sync_strt_wid;
|
||||
uint32_t fp2_h_sync_strt_wid;
|
||||
uint32_t fp_horz_stretch;
|
||||
uint32_t fp_panel_cntl;
|
||||
uint32_t fp_v_sync_strt_wid;
|
||||
uint32_t fp2_v_sync_strt_wid;
|
||||
uint32_t fp_vert_stretch;
|
||||
uint32_t lvds_gen_cntl;
|
||||
uint32_t lvds_pll_cntl;
|
||||
uint32_t tmds_crc;
|
||||
uint32_t tmds_transmitter_cntl;
|
||||
|
||||
/* Computed values for PLL */
|
||||
uint32_t dot_clock_freq;
|
||||
uint32_t pll_output_freq;
|
||||
int32_t feedback_div;
|
||||
int32_t post_div;
|
||||
|
||||
/* PLL registers */
|
||||
uint32_t ppll_div_3;
|
||||
uint32_t ppll_ref_div;
|
||||
uint32_t vclk_ecp_cntl;
|
||||
uint32_t clk_cntl_index;
|
||||
uint32_t htotal_cntl;
|
||||
|
||||
/* Computed values for PLL2 */
|
||||
uint32_t dot_clock_freq_2;
|
||||
uint32_t pll_output_freq_2;
|
||||
int32_t feedback_div_2;
|
||||
int32_t post_div_2;
|
||||
|
||||
/* PLL2 registers */
|
||||
uint32_t p2pll_ref_div;
|
||||
uint32_t p2pll_div_0;
|
||||
uint32_t htotal_cntl2;
|
||||
};
|
||||
|
||||
struct panel_info
|
||||
{
|
||||
int32_t xres, yres;
|
||||
int32_t valid;
|
||||
int32_t clock;
|
||||
int32_t hOver_plus, hSync_width, hblank;
|
||||
int32_t vOver_plus, vSync_width, vblank;
|
||||
int32_t hAct_high, vAct_high, int32_terlaced;
|
||||
int32_t pwr_delay;
|
||||
int32_t use_bios_dividers;
|
||||
int32_t ref_divider;
|
||||
int32_t post_divider;
|
||||
int32_t fbk_divider;
|
||||
};
|
||||
|
||||
struct radeonfb_info;
|
||||
|
||||
#ifdef CONFIG_FB_RADEON_I2C
|
||||
struct radeon_i2c_chan
|
||||
{
|
||||
struct radeonfb_info *rinfo;
|
||||
uint32_t ddc_reg;
|
||||
struct i2c_adapter adapter;
|
||||
struct i2c_algo_bit_data algo;
|
||||
};
|
||||
#endif
|
||||
|
||||
enum radeon_pm_mode
|
||||
{
|
||||
radeon_pm_none = 0, /* Nothing supported */
|
||||
radeon_pm_d2 = 0x00000001, /* Can do D2 state */
|
||||
radeon_pm_off = 0x00000002, /* Can resume from D3 cold */
|
||||
};
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint8_t table_revision;
|
||||
uint8_t table_size;
|
||||
uint8_t tuner_type;
|
||||
uint8_t audio_chip;
|
||||
uint8_t product_id;
|
||||
uint8_t tuner_voltage_teletext_fm;
|
||||
uint8_t i2s_config; /* configuration of the sound chip */
|
||||
uint8_t video_decoder_type;
|
||||
uint8_t video_decoder_host_config;
|
||||
uint8_t input[5];
|
||||
} _MM_TABLE;
|
||||
|
||||
struct radeonfb_info
|
||||
{
|
||||
int32_t handle; /* PCI BIOS, must be 1st place */
|
||||
int32_t big_endian; /* PCI BIOS */
|
||||
|
||||
uint32_t cursor_x;
|
||||
uint32_t cursor_y;
|
||||
int32_t cursor_show;
|
||||
uint32_t cursor_start;
|
||||
uint32_t cursor_end;
|
||||
int32_t cursor_fg;
|
||||
int32_t cursor_bg;
|
||||
|
||||
int32_t fifo_slots; /* Free slots in the FIFO (64 max) */
|
||||
|
||||
/* Computed values for Radeon */
|
||||
uint32_t dp_gui_master_cntl_clip;
|
||||
uint32_t trans_color;
|
||||
|
||||
/* Saved values for ScreenToScreenCopy */
|
||||
int32_t xdir;
|
||||
int32_t ydir;
|
||||
|
||||
/* ScanlineScreenToScreenColorExpand support */
|
||||
int32_t scanline_h;
|
||||
int32_t scanline_words;
|
||||
int32_t scanline_bpp; /* Only used for ImageWrite */
|
||||
|
||||
/* Saved values for DashedTwoPoint32_tLine */
|
||||
int32_t dashLen;
|
||||
uint32_t dashPattern;
|
||||
int32_t dash_fg;
|
||||
int32_t dash_bg;
|
||||
|
||||
struct fb_info *info;
|
||||
|
||||
struct radeon_regs state;
|
||||
struct radeon_regs init_state;
|
||||
|
||||
uint8_t name[50];
|
||||
|
||||
uint32_t io_base_phys;
|
||||
uint32_t mmio_base_phys;
|
||||
uint32_t fb_base_phys;
|
||||
|
||||
void *io_base;
|
||||
void *mmio_base;
|
||||
void *fb_base;
|
||||
|
||||
uint32_t fb_local_base;
|
||||
uint32_t fb_offset;
|
||||
|
||||
uint32_t bios_seg_phys;
|
||||
void *bios_seg;
|
||||
int32_t fp_bios_start;
|
||||
|
||||
struct
|
||||
{
|
||||
uint8_t red;
|
||||
uint8_t green;
|
||||
uint8_t blue;
|
||||
uint8_t pad;
|
||||
} palette[256];
|
||||
|
||||
int32_t chipset;
|
||||
uint8_t family;
|
||||
uint8_t rev;
|
||||
int32_t errata;
|
||||
uint32_t video_ram;
|
||||
uint32_t mapped_vram;
|
||||
int32_t vram_width;
|
||||
int32_t vram_ddr;
|
||||
|
||||
int32_t pitch, bpp, depth;
|
||||
|
||||
int32_t has_CRTC2;
|
||||
int32_t is_mobility;
|
||||
int32_t is_IGP;
|
||||
int32_t reversed_DAC;
|
||||
int32_t reversed_TMDS;
|
||||
struct panel_info panel_info;
|
||||
int32_t mon1_type;
|
||||
uint8_t *mon1_EDID;
|
||||
struct fb_videomode *mon1_modedb;
|
||||
int32_t mon1_dbsize;
|
||||
int32_t mon2_type;
|
||||
uint8_t *mon2_EDID;
|
||||
|
||||
uint32_t dp_gui_master_cntl;
|
||||
|
||||
struct pll_info bios_pll;
|
||||
struct pll_info pll;
|
||||
|
||||
uint32_t save_regs[100];
|
||||
int32_t asleep;
|
||||
int32_t lock_blank;
|
||||
int32_t dynclk;
|
||||
int32_t no_schedule;
|
||||
enum radeon_pm_mode pm_mode;
|
||||
|
||||
/* Timer used for delayed LVDS operations */
|
||||
int32_t lvds_timer;
|
||||
uint32_t pending_lvds_gen_cntl;
|
||||
|
||||
#ifdef CONFIG_FB_RADEON_I2C
|
||||
struct radeon_i2c_chan i2c[4];
|
||||
#endif
|
||||
|
||||
/* Texture */
|
||||
|
||||
int32_t RenderInited3D;
|
||||
int32_t tilingEnabled;
|
||||
void *RenderTex;
|
||||
uint32_t RenderTexOffset;
|
||||
int32_t RenderTexSize;
|
||||
void (*RenderCallback)(struct radeonfb_info *rinfo);
|
||||
uint32_t RenderTimeout;
|
||||
uint32_t dst_pitch_offset;
|
||||
|
||||
|
||||
#ifdef _NOT_USED_
|
||||
/* Video & theatre */
|
||||
|
||||
TheatrePtr theatre;
|
||||
|
||||
int32_t MM_TABLE_valid;
|
||||
_MM_TABLE MM_TABLE;
|
||||
|
||||
int32_t RageTheatreCrystal;
|
||||
int32_t RageTheatreTunerPort;
|
||||
int32_t RageTheatreCompositePort;
|
||||
int32_t RageTheatreSVideoPort;
|
||||
int32_t tunerType;
|
||||
|
||||
int32_t videoStatus;
|
||||
int32_t encoding;
|
||||
int32_t overlay_deint32_terlacing_method;
|
||||
int32_t video_stream_active;
|
||||
int32_t capture_vbi_data;
|
||||
int32_t v;
|
||||
void *videoLinear;
|
||||
int32_t videoLinearSize;
|
||||
struct
|
||||
{
|
||||
uint32_t y,u,v;
|
||||
} videoLinearOffset;
|
||||
#endif /* _NOT_USED_ */
|
||||
|
||||
int32_t dec_hue;
|
||||
int32_t dec_saturation;
|
||||
int32_t dec_contrast;
|
||||
int32_t dec_brightness;
|
||||
};
|
||||
|
||||
#define PRIMARY_MONITOR(rinfo) (rinfo->mon1_type)
|
||||
|
||||
/*
|
||||
* IO macros
|
||||
*/
|
||||
|
||||
/*
|
||||
* Note about this function: we have some rare cases where we must not schedule,
|
||||
* this typically happen with our special "wake up early" hook which allows us to
|
||||
* wake up the graphic chip (and thus get the console back) before everything else
|
||||
* on some machines that support that mecanism. At this point, intterrupts are off
|
||||
* and scheduling is not permitted
|
||||
*/
|
||||
static inline void _radeon_msleep(struct radeonfb_info *rinfo, uint32_t ms)
|
||||
{
|
||||
wait_ms(ms);
|
||||
}
|
||||
|
||||
#define radeon_msleep(ms) _radeon_msleep(rinfo,ms)
|
||||
|
||||
extern void _OUTREGP(struct radeonfb_info *rinfo, uint32_t addr, uint32_t val, uint32_t mask);
|
||||
extern void radeon_pll_errata_after_index(struct radeonfb_info *rinfo);
|
||||
extern void radeon_pll_errata_after_data(struct radeonfb_info *rinfo);
|
||||
extern uint32_t __INPLL(struct radeonfb_info *rinfo, uint32_t addr);
|
||||
extern void __OUTPLL(struct radeonfb_info *rinfo, uint32_t index, uint32_t val);
|
||||
extern void __OUTPLLP(struct radeonfb_info *rinfo, uint32_t index, uint32_t val, uint32_t mask);
|
||||
|
||||
#define INREG8(addr) *((volatile uint8_t *)(rinfo->mmio_base + addr))
|
||||
#define INREG16(addr) swpw(*(volatile uint16_t *)(rinfo->mmio_base + addr))
|
||||
#define INREG(addr) swpl(*(volatile uint32_t *)(rinfo->mmio_base + addr))
|
||||
#define OUTREG8(addr, val) (*((volatile uint8_t *)(rinfo->mmio_base + addr)) = val)
|
||||
#define OUTREG16(addr, val) (*((volatile uint16_t *)(rinfo->mmio_base + addr)) = swpw((uint32_t) val))
|
||||
#define OUTREG(addr, val) (*((volatile uint32_t *)(rinfo->mmio_base + addr)) = swpl((uint32_t) val))
|
||||
|
||||
extern int32_t *tab_funcs_pci;
|
||||
#define BIOS_IN8(v) (* ((volatile uint8_t *) rinfo->bios_seg_phys + v))
|
||||
#define BIOS_IN16(v) (swpw(*(volatile uint16_t *) ((uint8_t *) rinfo->bios_seg_phys + v)))
|
||||
#define BIOS_IN32(v) (swpl(*(volatile uint32_t *) ((uint8_t *) rinfo->bios_seg_phys + v)))
|
||||
|
||||
#define ADDRREG(addr) ((volatile uint32_t *)(rinfo->mmio_base + (addr)))
|
||||
#define OUTREGP(addr, val, mask) _OUTREGP(rinfo, addr, val, mask)
|
||||
#define INPLL(addr) __INPLL(rinfo, addr)
|
||||
#define OUTPLL(index, val) __OUTPLL(rinfo, index, val)
|
||||
#define OUTPLLP(index, val, mask) __OUTPLLP(rinfo, index, val, mask)
|
||||
|
||||
/*
|
||||
* Inline utilities
|
||||
*/
|
||||
|
||||
static inline uint32_t radeon_get_dstbpp(uint16_t depth)
|
||||
{
|
||||
switch(depth)
|
||||
{
|
||||
case 8: return DST_8BPP;
|
||||
case 15: return DST_15BPP;
|
||||
case 16: return DST_16BPP;
|
||||
case 32: return DST_32BPP;
|
||||
default: return 0;
|
||||
}
|
||||
}
|
||||
|
||||
/* I2C Functions */
|
||||
extern void radeon_create_i2c_busses(struct radeonfb_info *rinfo);
|
||||
extern void radeon_delete_i2c_busses(struct radeonfb_info *rinfo);
|
||||
extern int32_t radeon_probe_i2c_connector(struct radeonfb_info *rinfo, int32_t conn, uint8_t **out_edid);
|
||||
|
||||
/* PM Functions */
|
||||
/* extern int32_t radeonfb_pci_suspend(struct pci_dev *pdev, uint32_t state);
|
||||
extern int32_t radeonfb_pci_resume(struct pci_dev *pdev); */
|
||||
extern void radeonfb_pm_init(struct radeonfb_info *rinfo, int32_t dynclk);
|
||||
extern void radeonfb_pm_exit(struct radeonfb_info *rinfo);
|
||||
|
||||
/* Monitor probe functions */
|
||||
extern void radeon_probe_screens(struct radeonfb_info *rinfo,
|
||||
const char *monitor_layout, int32_t ignore_edid);
|
||||
extern void radeon_check_modes(struct radeonfb_info *rinfo, struct mode_option *resolution);
|
||||
extern int32_t radeon_match_mode(struct radeonfb_info *rinfo,
|
||||
struct fb_var_screeninfo *dest,
|
||||
const struct fb_var_screeninfo *src);
|
||||
|
||||
/* Video functions */
|
||||
void RADEONResetVideo(struct radeonfb_info *rinfo);
|
||||
int32_t RADEONVIP_read(struct radeonfb_info *rinfo, uint32_t address, uint32_t count, uint8_t *buffer);
|
||||
int32_t RADEONVIP_fifo_read(struct radeonfb_info *rinfo, uint32_t address, uint32_t count, uint8_t *buffer);
|
||||
int32_t RADEONVIP_write(struct radeonfb_info *rinfo, uint32_t address, uint32_t count, uint8_t *buffer);
|
||||
int32_t RADEONVIP_fifo_write(struct radeonfb_info *rinfo, uint32_t address, uint32_t count, uint8_t *buffer);
|
||||
void RADEONVIP_reset(struct radeonfb_info *rinfo);
|
||||
|
||||
void RADEONInitVideo(struct radeonfb_info *rinfo);
|
||||
void RADEONShutdownVideo(struct radeonfb_info *rinfo);
|
||||
int32_t RADEONPutVideo(struct radeonfb_info *rinfo, int32_t src_x, int32_t src_y, int32_t src_w, int32_t src_h,
|
||||
int32_t drw_x, int32_t drw_y, int32_t drw_w, int32_t drw_h);
|
||||
void RADEONStopVideo(struct radeonfb_info *rinfo, int32_t cleanup);
|
||||
|
||||
/* Theatre functions */
|
||||
//extern TheatrePtr DetectTheatre(struct radeonfb_info *rinfo);
|
||||
//extern void RT_SetTint32_t(TheatrePtr t, int32_t hue);
|
||||
//extern void RT_SetSaturation(TheatrePtr t, int32_t Saturation);
|
||||
//extern void RT_SetBrightness(TheatrePtr t, int32_t Brightness);
|
||||
//extern void RT_SetSharpness(TheatrePtr t, uint16_t wSharpness);
|
||||
//extern void RT_SetContrast(TheatrePtr t, int32_t Contrast);
|
||||
//extern void RT_SetInterlace(TheatrePtr t, uint8_t bInterlace);
|
||||
//extern void RT_SetStandard(TheatrePtr t, uint16_t wStandard);
|
||||
//extern void RT_SetCombFilter(TheatrePtr t, uint16_t wStandard, uint16_t wConnector);
|
||||
//extern void RT_SetOutputVideoSize(TheatrePtr t, uint16_t wHorzSize, uint16_t wVertSize, uint8_t fCC_On, uint8_t fVBICap_On);
|
||||
//extern void RT_SetConnector(TheatrePtr t, uint16_t wConnector, int32_t tunerFlag);
|
||||
//extern void InitTheatre(TheatrePtr t);
|
||||
//extern void ShutdownTheatre(TheatrePtr t);
|
||||
//extern void ResetTheatreRegsForNoTVout(TheatrePtr t);
|
||||
//extern void ResetTheatreRegsForTVout(TheatrePtr t);
|
||||
extern void RADEONVIP_reset(struct radeonfb_info *rinfo);
|
||||
|
||||
/* Accel functions */
|
||||
|
||||
extern void radeon_wait_for_fifo_function(struct radeonfb_info *rinfo, int32_t entries);
|
||||
extern void radeon_engine_flush(struct radeonfb_info *rinfo);
|
||||
extern void radeon_engine_reset(struct radeonfb_info *rinfo);
|
||||
extern void radeon_engine_restore(struct radeonfb_info *rinfo);
|
||||
extern void radeon_engine_init(struct radeonfb_info *rinfo);
|
||||
extern void radeon_wait_for_idle_mmio(struct radeonfb_info *rinfo);
|
||||
|
||||
#define radeon_engine_idle() radeon_wait_for_idle_mmio(rinfo)
|
||||
|
||||
#define radeon_wait_for_fifo(rinfo, entries) \
|
||||
do \
|
||||
{ \
|
||||
if (rinfo->fifo_slots < entries) \
|
||||
radeon_wait_for_fifo_function(rinfo, entries); \
|
||||
rinfo->fifo_slots -= entries; \
|
||||
} while (0)
|
||||
|
||||
static inline int32_t radeonfb_sync(struct fb_info *info)
|
||||
{
|
||||
struct radeonfb_info *rinfo = info->par;
|
||||
radeon_engine_idle();
|
||||
return 0;
|
||||
}
|
||||
|
||||
extern void radeon_restore_accel_state_mmio(struct fb_info *info);
|
||||
extern void radeon_setup_for_solid_fill(struct fb_info *info, int32_t color, int32_t rop, uint32_t planemask);
|
||||
extern void radeon_subsequent_solid_fill_rect_mmio(struct fb_info *info, int32_t x, int32_t y, int32_t w, int32_t h);
|
||||
extern void radeon_setup_for_solid_line_mmio(struct fb_info *info, int32_t color, int32_t rop, uint32_t planemask);
|
||||
extern void radeon_subsequent_solid_hor_vert_line_mmio(struct fb_info *info, int32_t x, int32_t y, int32_t len, int32_t dir);
|
||||
extern void radeon_subsequent_solid_two_point_line_mmio(struct fb_info *info, int32_t xa, int32_t ya, int32_t xb,
|
||||
int32_t yb, int32_t flags);
|
||||
extern void radeon_setup_for_dashed_line_mmio(struct fb_info *info, int32_t fg, int32_t bg,
|
||||
int32_t rop, uint32_t planemask, int32_t length, unsigned char *pattern);
|
||||
extern void radeon_subsequent_dashed_two_point_line_mmio(struct fb_info *info,
|
||||
int32_t xa, int32_t ya, int32_t xb, int32_t yb, int32_t flags, int32_t phase);
|
||||
extern void radeon_setup_for_screen_to_screen_copy_mmio(struct fb_info *info,
|
||||
int32_t xdir, int32_t ydir, int32_t rop, uint32_t planemask, int32_t trans_color);
|
||||
extern void radeon_subsequent_screen_to_screen_copy_mmio(struct fb_info *info,
|
||||
int32_t xa, int32_t ya, int32_t xb, int32_t yb, int32_t w, int32_t h);
|
||||
extern void radeon_screen_to_screen_copy_mmio(struct fb_info *info,
|
||||
int32_t xa, int32_t ya, int32_t xb, int32_t yb, int32_t w, int32_t h, int32_t rop);
|
||||
extern void radeon_setup_for_mono_8x8_pattern_fill_mmio(struct fb_info *info,
|
||||
int32_t patternx, int32_t patterny, int32_t fg, int32_t bg, int32_t rop, uint32_t planemask);
|
||||
extern void radeon_subsequent_mono_8x8_pattern_fill_rect_mmio(struct fb_info *info,
|
||||
int32_t patternx, int32_t patterny, int32_t x, int32_t y, int32_t w, int32_t h);
|
||||
extern void radeon_setup_for_scanline_cpu_to_screen_color_expand_fill_mmio(struct fb_info *info,
|
||||
int32_t fg, int32_t bg, int32_t rop, uint32_t planemask);
|
||||
extern void radeon_subsequent_scanline_cpu_to_screen_color_expand_fill_mmio(struct fb_info *info,
|
||||
int32_t x, int32_t y, int32_t w, int32_t h, int32_t skipleft);
|
||||
extern void radeon_subsequent_scanline_mmio(struct fb_info *info, uint32_t *buf);
|
||||
extern void radeon_setup_for_scanline_image_write_mmio(struct fb_info *info,
|
||||
int32_t rop, uint32_t planemask, int32_t trans_color, int32_t bpp);
|
||||
extern void radeon_subsequent_scanline_image_write_rect_mmio(struct fb_info *info,
|
||||
int32_t x, int32_t y, int32_t w, int32_t h, int32_t skipleft);
|
||||
extern void radeon_set_clipping_rectangle_mmio(struct fb_info *info,
|
||||
int32_t xa, int32_t ya, int32_t xb, int32_t yb);
|
||||
extern void radeon_disable_clipping_mmio(struct fb_info *info);
|
||||
|
||||
extern int32_t radeon_setup_for_cpu_to_screen_alpha_texture_mmio(struct fb_info *info,
|
||||
int32_t op, int32_t red, int32_t green, int32_t blue,
|
||||
int32_t alpha, int32_t maskFormat, int32_t dstFormat,
|
||||
uint8_t *alphaPtr, int32_t alphaPitch,
|
||||
int32_t width, int32_t height, int32_t flags);
|
||||
extern int32_t radeon_setup_for_cpu_to_screen_texture_mmio(struct fb_info *info, int32_t op,
|
||||
uint32_t srcFormat, uint32_t dstFormat,
|
||||
uint8_t *texPtr, int32_t texPitch,
|
||||
int32_t width, int32_t height, int32_t flags);
|
||||
extern void radeon_subsequent_cpu_to_screen_texture_mmio(struct fb_info *info,
|
||||
int32_t dstx, int32_t dsty,
|
||||
int32_t srcx, int32_t srcy,
|
||||
int32_t width, int32_t height);
|
||||
/* Cursor functions */
|
||||
extern void radeon_set_cursor_colors(struct fb_info *info, int32_t bg, int32_t fg);
|
||||
extern void radeon_set_cursor_position(struct fb_info *info, int32_t x, int32_t y);
|
||||
extern void radeon_load_cursor_image(struct fb_info *info, unsigned short *mask, unsigned short *data, int32_t zoom);
|
||||
extern void radeon_hide_cursor(struct fb_info *info);
|
||||
extern void radeon_show_cursor(struct fb_info *info);
|
||||
extern long radeon_cursor_init(struct fb_info *info);
|
||||
|
||||
/* Other functions */
|
||||
extern int32_t radeon_screen_blank(struct radeonfb_info *rinfo, int32_t blank, int32_t mode_switch);
|
||||
extern void radeon_write_mode(struct radeonfb_info *rinfo, struct radeon_regs *mode, int32_t reg_only);
|
||||
int32_t radeonfb_setcolreg(uint32_t regno, uint32_t red, uint32_t green,
|
||||
uint32_t blue, uint32_t transp, struct fb_info *info);
|
||||
extern int32_t radeonfb_pci_register(int32_t handle, const struct pci_device_id *ent);
|
||||
extern void radeonfb_pci_unregister(void);
|
||||
|
||||
/* global */
|
||||
extern const char monitor_layout[];
|
||||
extern int16_t default_dynclk;
|
||||
extern int16_t ignore_edid;
|
||||
extern int16_t mirror;
|
||||
extern int16_t virtual;
|
||||
extern int16_t force_measure_pll;
|
||||
extern int16_t zoom_mouse;
|
||||
|
||||
extern struct pci_device_id radeonfb_pci_table[];
|
||||
|
||||
#endif /* __RADEONFB_H__ */
|
||||
48
include/s19reader.h
Normal file
48
include/s19reader.h
Normal file
@@ -0,0 +1,48 @@
|
||||
/*
|
||||
* s19reader.h
|
||||
*
|
||||
* Created on: 17.11.2012
|
||||
* Author: mfro
|
||||
*
|
||||
* This file is part of BaS_gcc.
|
||||
*
|
||||
* BaS_gcc is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* BaS_gcc is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* Copyright 2012 M. Froeschle
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _S19READER_H_
|
||||
#define _S19READER_H_
|
||||
|
||||
typedef enum
|
||||
{
|
||||
OK, /* no error */
|
||||
FAIL, /* general error aka "I don't know what went wrong" */
|
||||
FILE_OPEN, /* file open failed */
|
||||
FILE_READ, /* file read failed */
|
||||
SREC_CORRUPT, /* file doesn't seem to contain valid S-records */
|
||||
MEMCPY_FAILED, /* could not copy buffer to destination */
|
||||
CODE_OVERLAPS, /* copying would overwrite ourself */
|
||||
VERIFY_FAILED, /* destination does not read as we've written to */
|
||||
ILLEGAL_SECTOR /* flash sector number invalid */
|
||||
} err_t;
|
||||
|
||||
typedef err_t (*memcpy_callback_t)(uint8_t *dst, uint8_t *src, size_t length);
|
||||
|
||||
extern void srec_execute(char *filename);
|
||||
extern err_t read_srecords(char *filename, void **start_address, uint32_t *actual_length, memcpy_callback_t callback);
|
||||
extern err_t srec_memcpy(uint8_t *dst, uint8_t *src, size_t n);
|
||||
|
||||
#endif /* _S19READER_H_ */
|
||||
122
include/screen.h
Normal file
122
include/screen.h
Normal file
@@ -0,0 +1,122 @@
|
||||
/*
|
||||
* screen.h - low-level screen routines
|
||||
*
|
||||
* Copyright (c) 2001-2013 The EmuTOS development team
|
||||
*
|
||||
* Authors:
|
||||
* LVL Laurent Vogel
|
||||
* THH Thomas Huth
|
||||
*
|
||||
* This file is distributed under the GPL, version 2 or at your
|
||||
* option any later version. See doc/license.txt for details.
|
||||
*/
|
||||
|
||||
#ifndef SCREEN_H
|
||||
#define SCREEN_H
|
||||
|
||||
#define ST_VRAM_SIZE 32000UL
|
||||
#define TT_VRAM_SIZE 153600UL
|
||||
#define FALCON_VRAM_SIZE 307200UL
|
||||
|
||||
#define VIDEOBASE_ADDR_HI 0xffff8201L
|
||||
#define VIDEOBASE_ADDR_MID 0xffff8203L
|
||||
#define VIDEOBASE_ADDR_LOW 0xffff820dL
|
||||
|
||||
#define SYNCMODE 0xffff820aL
|
||||
|
||||
#define ST_SHIFTER 0xffff8260L
|
||||
#define TT_SHIFTER 0xffff8262L
|
||||
#define SPSHIFT 0xffff8266L
|
||||
|
||||
#define TT_SHIFTER_BITMASK 0x970f /* valid bits in TT_SHIFTER */
|
||||
|
||||
#define ST_PALETTE_REGS 0xffff8240L
|
||||
#define FALCON_PALETTE_REGS 0xffff9800L
|
||||
|
||||
#define TT_PALETTE_BITMASK 0x0fff /* valid bits in TT_PALETTE_REGS */
|
||||
|
||||
/* misc routines */
|
||||
int16_t check_moderez(int16_t moderez);
|
||||
void initialise_palette_registers(int16_t rez,int16_t mode);
|
||||
|
||||
/* hardware dependant xbios routines */
|
||||
|
||||
int16_t esetshift(int16_t mode);
|
||||
int16_t egetshift(void);
|
||||
int16_t esetbank(int16_t bank);
|
||||
int16_t esetcolor(int16_t index,int16_t color);
|
||||
void esetpalette(int16_t index,int16_t count,int16_t *rgb);
|
||||
void egetpalette(int16_t index,int16_t count,int16_t *rgb);
|
||||
int16_t esetgray(int16_t mode);
|
||||
int16_t esetsmear(int16_t mode);
|
||||
|
||||
/* pallette color definitions */
|
||||
|
||||
#define RGB_BLACK 0x0000 /* ST(e) palette */
|
||||
#define RGB_BLUE 0x000f
|
||||
#define RGB_GREEN 0x00f0
|
||||
#define RGB_CYAN 0x00ff
|
||||
#define RGB_RED 0x0f00
|
||||
#define RGB_MAGENTA 0x0f0f
|
||||
#define RGB_LTGRAY 0x0555
|
||||
#define RGB_GRAY 0x0333
|
||||
#define RGB_LTBLUE 0x033f
|
||||
#define RGB_LTGREEN 0x03f3
|
||||
#define RGB_LTCYAN 0x03ff
|
||||
#define RGB_LTRED 0x0f33
|
||||
#define RGB_LTMAGENTA 0x0f3f
|
||||
#define RGB_YELLOW 0x0ff0
|
||||
#define RGB_LTYELLOW 0x0ff3
|
||||
#define RGB_WHITE 0x0fff
|
||||
|
||||
#define TTRGB_BLACK 0x0000 /* TT Palette */
|
||||
#define TTRGB_BLUE 0x000f
|
||||
#define TTRGB_GREEN 0x00f0
|
||||
#define TTRGB_CYAN 0x00ff
|
||||
#define TTRGB_RED 0x0f00
|
||||
#define TTRGB_MAGENTA 0x0f0f
|
||||
#define TTRGB_LTGRAY 0x0aaa
|
||||
#define TTRGB_GRAY 0x0666
|
||||
#define TTRGB_LTBLUE 0x099f
|
||||
#define TTRGB_LTGREEN 0x09f9
|
||||
#define TTRGB_LTCYAN 0x09ff
|
||||
#define TTRGB_LTRED 0x0f99
|
||||
#define TTRGB_LTMAGENTA 0x0f9f
|
||||
#define TTRGB_YELLOW 0x0ff0
|
||||
#define TTRGB_LTYELLOW 0x0ff9
|
||||
#define TTRGB_WHITE 0x0fff
|
||||
|
||||
/* TT resolutions */
|
||||
#define TT_HIGH 6
|
||||
#define TT_MEDIUM 4
|
||||
#define TT_LOW 7
|
||||
|
||||
/* ST(e) resolutions */
|
||||
#define ST_HIGH 2
|
||||
#define ST_MEDIUM 1
|
||||
#define ST_LOW 0
|
||||
|
||||
/* monitor types (from VgetMonitor()) */
|
||||
#define MON_MONO 0 /* ST monochrome */
|
||||
#define MON_COLOR 1 /* ST colour */
|
||||
#define MON_VGA 2 /* VGA */
|
||||
#define MON_TV 3 /* TV via RF modulator */
|
||||
|
||||
/* determine monitor type, ... */
|
||||
void screen_init(void);
|
||||
void set_rez_hacked(void);
|
||||
int rez_changeable(void);
|
||||
int16_t get_monitor_type(void);
|
||||
void screen_get_current_mode_info(uint16_t *planes, uint16_t *hz_rez, uint16_t *vt_rez);
|
||||
|
||||
/* hardware independant xbios routines */
|
||||
|
||||
int32_t physbase(void);
|
||||
int32_t logbase(void);
|
||||
int16_t getrez(void);
|
||||
void setscreen(int32_t logLoc, int32_t physLoc, int16_t rez, int16_t videlmode);
|
||||
void setpalette(int32_t palettePtr);
|
||||
int16_t setcolor(int16_t colorNum, int16_t color);
|
||||
void vsync(void);
|
||||
|
||||
#endif /* SCREEN_H */
|
||||
11
include/setjmp.h
Normal file
11
include/setjmp.h
Normal file
@@ -0,0 +1,11 @@
|
||||
#ifndef _SETJMP_H_
|
||||
#define _SETJMP_H_
|
||||
|
||||
#include "bas_types.h"
|
||||
|
||||
typedef uint32_t jmp_buf[18];
|
||||
|
||||
extern int setjmp(jmp_buf env);
|
||||
extern void longjmp(jmp_buf env, int val);
|
||||
|
||||
#endif /* _SETJMP_H_ */
|
||||
31
include/startcf.h
Normal file
31
include/startcf.h
Normal file
@@ -0,0 +1,31 @@
|
||||
#ifndef _STARTCF_H_
|
||||
#define _STARTCF_H_
|
||||
|
||||
/*
|
||||
* This file is part of BaS_gcc.
|
||||
*
|
||||
* BaS_gcc is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* BaS_gcc is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* Created on: 26.02.2013
|
||||
* Author: Markus Fröschle
|
||||
*/
|
||||
|
||||
#define cf_stack
|
||||
|
||||
#define DIP_SWITCH (*(volatile uint8_t *)(&_MBAR[0xA2C]))
|
||||
#define DIP_SWITCHa __MBAR + 0xA2C
|
||||
|
||||
#define sca_page_ID 6
|
||||
|
||||
#endif /* _STARTCF_H_ */
|
||||
44
include/sysinit.h
Normal file
44
include/sysinit.h
Normal file
@@ -0,0 +1,44 @@
|
||||
/*
|
||||
* File: sysinit.h
|
||||
* Purpose: Firebee Power-on Reset configuration
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
* This file is part of BaS_gcc.
|
||||
*
|
||||
* BaS_gcc is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* BaS_gcc is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* Copyright 2010 - 2012 F. Aschwanden
|
||||
* Copyright 2011 - 2012 V. Riviere
|
||||
* Copyright 2012 M. Froeschle
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef __SYSINIT_H__
|
||||
#define __SYSINIT_H__
|
||||
|
||||
#include <stdbool.h>
|
||||
|
||||
/* function(s) from init_fpga.c */
|
||||
extern bool init_fpga(void);
|
||||
extern void init_usb(void);
|
||||
|
||||
/* fault_vectors */
|
||||
extern void setup_vectors(void);
|
||||
|
||||
extern bool fpga_configured;
|
||||
|
||||
#endif /* __SYSINIT_H__ */
|
||||
|
||||
|
||||
48
include/udp.h
Normal file
48
include/udp.h
Normal file
@@ -0,0 +1,48 @@
|
||||
/*
|
||||
* File: udp.h
|
||||
* Purpose: User Datagram Protocol, UDP, data definitions
|
||||
*
|
||||
* Notes:
|
||||
*/
|
||||
|
||||
#ifndef _UDP_H
|
||||
#define _UDP_H
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
typedef struct
|
||||
{
|
||||
uint16_t src_port;
|
||||
uint16_t dest_port;
|
||||
uint16_t length;
|
||||
uint16_t chksum;
|
||||
} udp_frame_hdr;
|
||||
|
||||
#define UDP_SOURCE(a) (a->src_port)
|
||||
#define UDP_DEST(a) (a->dest_port)
|
||||
#define UDP_LENGTH(a) (a->length)
|
||||
#define UDP_CHKSUM(a) (a->chksum)
|
||||
|
||||
#define DEFAULT_UDP_PORT (0x4321)
|
||||
#define UDP_PORT_TELNET (23)
|
||||
#define UDP_PORT_FTP (21)
|
||||
#define UDP_PORT_TFTP (69)
|
||||
|
||||
/* Protocol Header information */
|
||||
#define UDP_HDR_OFFSET (ETH_HDR_LEN + IP_HDR_SIZE)
|
||||
#define UDP_HDR_SIZE 8
|
||||
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
extern void udp_init(void);
|
||||
extern void udp_prime_port(uint16_t);
|
||||
extern uint16_t udp_obtain_free_port(void);
|
||||
extern void udp_bind_port( uint16_t, void (*)(NIF *,NBUF *));
|
||||
extern void udp_free_port(uint16_t);
|
||||
extern int udp_send(NIF *, uint8_t *, int, int, NBUF *);
|
||||
extern void udp_handler(NIF *, NBUF *);
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* _UDP_H */
|
||||
430
include/usb.h
Normal file
430
include/usb.h
Normal file
@@ -0,0 +1,430 @@
|
||||
/*
|
||||
* (C) Copyright 2001
|
||||
* Denis Peter, MPL AG Switzerland
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*
|
||||
* Note: Part of this code has been derived from linux
|
||||
*
|
||||
*/
|
||||
#ifndef _USB_H_
|
||||
#define _USB_H_
|
||||
|
||||
#include <bas_string.h>
|
||||
#include "driver_mem.h"
|
||||
#include "pci.h"
|
||||
#include "mod_devicetable.h"
|
||||
#include "pci_ids.h"
|
||||
#include "part.h"
|
||||
|
||||
|
||||
extern long *tab_funcs_pci;
|
||||
|
||||
#define __u8 uint8_t
|
||||
#define __u16 uint16_t
|
||||
#define __u32 uint32_t
|
||||
//#define u8 uint8_t
|
||||
#define u16 uint16_t
|
||||
#define u32 uint32_t
|
||||
#define uint8_t uint8_t
|
||||
#define uint32_t uint32_t
|
||||
#define uint16_t uint16_t
|
||||
|
||||
extern void kprint(const char *fmt, ...);
|
||||
extern int sprintD(char *s, const char *fmt, ...);
|
||||
|
||||
#include "usb_defs.h"
|
||||
|
||||
/* Everything is aribtrary */
|
||||
#define USB_ALTSETTINGALLOC 4
|
||||
#define USB_MAXALTSETTING 128 /* Hard limit */
|
||||
|
||||
#define USB_MAX_BUS 3
|
||||
#define USB_MAX_DEVICE 16
|
||||
#define USB_MAXCONFIG 8
|
||||
#define USB_MAXINTERFACES 8
|
||||
#define USB_MAXENDPOINTS 16
|
||||
#define USB_MAXCHILDREN 8 /* This is arbitrary */
|
||||
#define USB_MAX_HUB 16
|
||||
|
||||
#define USB_CNTL_TIMEOUT 100 /* 100 ms timeout */
|
||||
|
||||
#define USB_BUFSIZ 512
|
||||
|
||||
/* String descriptor */
|
||||
struct usb_string_descriptor
|
||||
{
|
||||
uint8_t bLength;
|
||||
uint8_t bDescriptorType;
|
||||
uint16_t wData[1];
|
||||
} __attribute__ ((packed));
|
||||
|
||||
/* device request (setup) */
|
||||
struct devrequest
|
||||
{
|
||||
uint8_t requesttype;
|
||||
uint8_t request;
|
||||
uint16_t value;
|
||||
uint16_t index;
|
||||
uint16_t length;
|
||||
} __attribute__ ((packed));
|
||||
|
||||
/* All standard descriptors have these 2 fields in common */
|
||||
struct usb_descriptor_header
|
||||
{
|
||||
uint8_t bLength;
|
||||
uint8_t bDescriptorType;
|
||||
} __attribute__ ((packed));
|
||||
|
||||
/* Device descriptor */
|
||||
struct usb_device_descriptor
|
||||
{
|
||||
uint8_t bLength;
|
||||
uint8_t bDescriptorType;
|
||||
uint16_t bcdUSB;
|
||||
uint8_t bDeviceClass;
|
||||
uint8_t bDeviceSubClass;
|
||||
uint8_t bDeviceProtocol;
|
||||
uint8_t bMaxPacketSize0;
|
||||
uint16_t idVendor;
|
||||
uint16_t idProduct;
|
||||
uint16_t bcdDevice;
|
||||
uint8_t iManufacturer;
|
||||
uint8_t iProduct;
|
||||
uint8_t iSerialNumber;
|
||||
uint8_t bNumConfigurations;
|
||||
} __attribute__ ((packed));
|
||||
|
||||
/* Endpoint descriptor */
|
||||
struct usb_endpoint_descriptor
|
||||
{
|
||||
uint8_t bLength;
|
||||
uint8_t bDescriptorType;
|
||||
uint8_t bEndpointAddress;
|
||||
uint8_t bmAttributes;
|
||||
uint16_t wMaxPacketSize;
|
||||
uint8_t bInterval;
|
||||
uint8_t bRefresh;
|
||||
uint8_t bSynchAddress;
|
||||
} __attribute__ ((packed)) __attribute__ ((aligned(2)));
|
||||
|
||||
/* Interface descriptor */
|
||||
struct usb_interface_descriptor
|
||||
{
|
||||
uint8_t bLength;
|
||||
uint8_t bDescriptorType;
|
||||
uint8_t bInterfaceNumber;
|
||||
uint8_t bAlternateSetting;
|
||||
uint8_t bNumEndpoints;
|
||||
uint8_t bInterfaceClass;
|
||||
uint8_t bInterfaceSubClass;
|
||||
uint8_t bInterfaceProtocol;
|
||||
uint8_t iInterface;
|
||||
|
||||
uint8_t no_of_ep;
|
||||
uint8_t num_altsetting;
|
||||
uint8_t act_altsetting;
|
||||
|
||||
struct usb_endpoint_descriptor ep_desc[USB_MAXENDPOINTS];
|
||||
} __attribute__ ((packed));
|
||||
|
||||
|
||||
/* Configuration descriptor information.. */
|
||||
struct usb_config_descriptor
|
||||
{
|
||||
uint8_t bLength;
|
||||
uint8_t bDescriptorType;
|
||||
uint16_t wTotalLength;
|
||||
uint8_t bNumInterfaces;
|
||||
uint8_t bConfigurationValue;
|
||||
uint8_t iConfiguration;
|
||||
uint8_t bmAttributes;
|
||||
uint8_t MaxPower;
|
||||
|
||||
uint8_t no_of_if; /* number of interfaces */
|
||||
struct usb_interface_descriptor if_desc[USB_MAXINTERFACES];
|
||||
} __attribute__ ((packed));
|
||||
|
||||
enum
|
||||
{
|
||||
/* Maximum packet size; encoded as 0,1,2,3 = 8,16,32,64 */
|
||||
PACKET_SIZE_8 = 0,
|
||||
PACKET_SIZE_16 = 1,
|
||||
PACKET_SIZE_32 = 2,
|
||||
PACKET_SIZE_64 = 3,
|
||||
};
|
||||
|
||||
struct usb_device
|
||||
{
|
||||
int devnum; /* Device number on USB bus */
|
||||
int speed; /* full/low/high */
|
||||
char mf[32]; /* manufacturer */
|
||||
char prod[32]; /* product */
|
||||
char serial[32]; /* serial number */
|
||||
|
||||
/* Maximum packet size; one of: PACKET_SIZE_* */
|
||||
int maxpacketsize;
|
||||
|
||||
/* one bit for each endpoint ([0] = IN, [1] = OUT) */
|
||||
unsigned int toggle[2];
|
||||
|
||||
/* endpoint halts; one bit per endpoint # & direction;
|
||||
* [0] = IN, [1] = OUT
|
||||
*/
|
||||
unsigned int halted[2];
|
||||
int epmaxpacketin[16]; /* INput endpoint specific maximums */
|
||||
int epmaxpacketout[16]; /* OUTput endpoint specific maximums */
|
||||
|
||||
int configno; /* selected config number */
|
||||
struct usb_device_descriptor descriptor; /* Device Descriptor */
|
||||
struct usb_config_descriptor config; /* config descriptor */
|
||||
|
||||
int have_langid; /* whether string_langid is valid yet */
|
||||
int string_langid; /* language ID for strings */
|
||||
int (*irq_handle)(struct usb_device *dev);
|
||||
uint32_t irq_status;
|
||||
int irq_act_len; /* transfered bytes */
|
||||
void *privptr;
|
||||
|
||||
/*
|
||||
* Child devices - if this is a hub device
|
||||
* Each instance needs its own set of data structures.
|
||||
*/
|
||||
uint32_t status;
|
||||
int act_len; /* transfered bytes */
|
||||
int maxchild; /* Number of ports if hub */
|
||||
int portnr;
|
||||
struct usb_device *parent;
|
||||
struct usb_device *children[USB_MAXCHILDREN];
|
||||
void *priv_hcd;
|
||||
int (*deregister)(struct usb_device *dev);
|
||||
|
||||
struct usb_hub_device *hub;
|
||||
int usbnum;
|
||||
};
|
||||
|
||||
typedef struct
|
||||
{
|
||||
long ident;
|
||||
union
|
||||
{
|
||||
long l;
|
||||
short i[2];
|
||||
char c[4];
|
||||
} v;
|
||||
} USB_COOKIE;
|
||||
|
||||
/*
|
||||
* this is how the lowlevel part communicate with the outer world
|
||||
*/
|
||||
|
||||
extern int ohci_usb_lowlevel_init(int32_t handle, const struct pci_device_id *ent, void **priv);
|
||||
extern int ohci_usb_lowlevel_stop(void *priv);
|
||||
extern int ohci_submit_bulk_msg(struct usb_device *dev, uint32_t pipe, void *buffer, int transfer_len);
|
||||
extern int ohci_submit_control_msg(struct usb_device *dev, uint32_t pipe, void *buffer, int transfer_len, struct devrequest *setup);
|
||||
extern int ohci_submit_int_msg(struct usb_device *dev, uint32_t pipe, void *buffer, int transfer_len, int interval);
|
||||
extern void ohci_usb_enable_interrupt(int enable);
|
||||
|
||||
extern int ehci_usb_lowlevel_init(long handle, const struct pci_device_id *ent, void **priv);
|
||||
extern int ehci_usb_lowlevel_stop(void *priv);
|
||||
extern int ehci_submit_bulk_msg(struct usb_device *dev, uint32_t pipe, void *buffer, int transfer_len);
|
||||
extern int ehci_submit_control_msg(struct usb_device *dev, uint32_t pipe, void *buffer, int transfer_len, struct devrequest *setup);
|
||||
extern int ehci_submit_int_msg(struct usb_device *dev, uint32_t pipe, void *buffer, int transfer_len, int interval);
|
||||
extern void ehci_usb_enable_interrupt(int enable);
|
||||
|
||||
extern void usb_enable_interrupt(int enable);
|
||||
|
||||
extern int usb_new_device(struct usb_device *dev);
|
||||
extern struct usb_device *usb_alloc_new_device(int bus_index, void *priv);
|
||||
extern void usb_disconnect(struct usb_device **pdev);
|
||||
|
||||
#define USB_MAX_STOR_DEV 5
|
||||
|
||||
extern block_dev_desc_t *usb_stor_get_dev(int index);
|
||||
extern int usb_stor_scan(void);
|
||||
extern int usb_stor_info(void);
|
||||
extern int usb_stor_register(struct usb_device *dev);
|
||||
extern int usb_stor_deregister(struct usb_device *dev);
|
||||
|
||||
extern int drv_usb_kbd_init(void);
|
||||
extern int usb_kbd_register(struct usb_device *dev);
|
||||
extern int usb_kbd_deregister(struct usb_device *dev);
|
||||
|
||||
extern int drv_usb_mouse_init(void);
|
||||
extern int usb_mouse_register(struct usb_device *dev);
|
||||
extern int usb_mouse_deregister(struct usb_device *dev);
|
||||
|
||||
/* routines */
|
||||
extern int usb_init(int32_t handle, const struct pci_device_id *ent); /* initialize the USB Controller */
|
||||
extern int usb_stop(void); /* stop the USB Controller */
|
||||
|
||||
extern int usb_set_protocol(struct usb_device *dev, int ifnum, int protocol);
|
||||
extern int usb_set_idle(struct usb_device *dev, int ifnum, int duration, int report_id);
|
||||
extern struct usb_device *usb_get_dev_index(int index, int bus);
|
||||
extern int usb_control_msg(struct usb_device *dev, unsigned int pipe, uint8_t request, uint8_t requesttype,
|
||||
uint16_t value, uint16_t index, void *data, uint16_t size, int timeout);
|
||||
extern int usb_bulk_msg(struct usb_device *dev, unsigned int pipe, void *data, int len, int *actual_length, int timeout);
|
||||
extern int usb_submit_int_msg(struct usb_device *dev, uint32_t pipe, void *buffer, int transfer_len, int interval);
|
||||
extern void usb_disable_asynch(int disable);
|
||||
extern int usb_maxpacket(struct usb_device *dev, uint32_t pipe);
|
||||
|
||||
extern int usb_get_configuration_no(struct usb_device *dev, uint8_t *buffer, int cfgno);
|
||||
extern int usb_get_report(struct usb_device *dev, int ifnum, uint8_t type, uint8_t id, void *buf, int size);
|
||||
extern int usb_get_class_descriptor(struct usb_device *dev, int ifnum, uint8_t type, uint8_t id, void *buf, int size);
|
||||
extern int usb_clear_halt(struct usb_device *dev, int pipe);
|
||||
extern int usb_string(struct usb_device *dev, int index, char *buf, size_t size);
|
||||
extern int usb_set_interface(struct usb_device *dev, int interface, int alternate);
|
||||
|
||||
/*
|
||||
* Calling this entity a "pipe" is glorifying it. A USB pipe
|
||||
* is something embarrassingly simple: it basically consists
|
||||
* of the following information:
|
||||
* - device number (7 bits)
|
||||
* - endpoint number (4 bits)
|
||||
* - current Data0/1 state (1 bit)
|
||||
* - direction (1 bit)
|
||||
* - speed (2 bits)
|
||||
* - max packet size (2 bits: 8, 16, 32 or 64)
|
||||
* - pipe type (2 bits: control, interrupt, bulk, isochronous)
|
||||
*
|
||||
* That's 18 bits. Really. Nothing more. And the USB people have
|
||||
* documented these eighteen bits as some kind of glorious
|
||||
* virtual data structure.
|
||||
*
|
||||
* Let's not fall in that trap. We'll just encode it as a simple
|
||||
* unsigned int. The encoding is:
|
||||
*
|
||||
* - max size: bits 0-1 (00 = 8, 01 = 16, 10 = 32, 11 = 64)
|
||||
* - direction: bit 7 (0 = Host-to-Device [Out],
|
||||
* (1 = Device-to-Host [In])
|
||||
* - device: bits 8-14
|
||||
* - endpoint: bits 15-18
|
||||
* - Data0/1: bit 19
|
||||
* - speed: bit 26 (0 = Full, 1 = Low Speed, 2 = High)
|
||||
* - pipe type: bits 30-31 (00 = isochronous, 01 = interrupt,
|
||||
* 10 = control, 11 = bulk)
|
||||
*
|
||||
* Why? Because it's arbitrary, and whatever encoding we select is really
|
||||
* up to us. This one happens to share a lot of bit positions with the UHCI
|
||||
* specification, so that much of the uhci driver can just mask the bits
|
||||
* appropriately.
|
||||
*/
|
||||
|
||||
/* Create various pipes... */
|
||||
#define create_pipe(dev, endpoint) \
|
||||
(((dev)->devnum << 8) | (endpoint << 15) | \
|
||||
((dev)->speed << 26) | (dev)->maxpacketsize)
|
||||
#define default_pipe(dev) ((dev)->speed << 26)
|
||||
|
||||
#define usb_sndctrlpipe(dev, endpoint) ((PIPE_CONTROL << 30) | \
|
||||
create_pipe(dev, endpoint))
|
||||
#define usb_rcvctrlpipe(dev, endpoint) ((PIPE_CONTROL << 30) | \
|
||||
create_pipe(dev, endpoint) | \
|
||||
USB_DIR_IN)
|
||||
#define usb_sndisocpipe(dev, endpoint) ((PIPE_ISOCHRONOUS << 30) | \
|
||||
create_pipe(dev, endpoint))
|
||||
#define usb_rcvisocpipe(dev, endpoint) ((PIPE_ISOCHRONOUS << 30) | \
|
||||
create_pipe(dev, endpoint) | \
|
||||
USB_DIR_IN)
|
||||
#define usb_sndbulkpipe(dev, endpoint) ((PIPE_BULK << 30) | \
|
||||
create_pipe(dev, endpoint))
|
||||
#define usb_rcvbulkpipe(dev, endpoint) ((PIPE_BULK << 30) | \
|
||||
create_pipe(dev, endpoint) | \
|
||||
USB_DIR_IN)
|
||||
#define usb_sndintpipe(dev, endpoint) ((PIPE_INTERRUPT << 30) | \
|
||||
create_pipe(dev, endpoint))
|
||||
#define usb_rcvintpipe(dev, endpoint) ((PIPE_INTERRUPT << 30) | \
|
||||
create_pipe(dev, endpoint) | \
|
||||
USB_DIR_IN)
|
||||
#define usb_snddefctrl(dev) ((PIPE_CONTROL << 30) | \
|
||||
default_pipe(dev))
|
||||
#define usb_rcvdefctrl(dev) ((PIPE_CONTROL << 30) | \
|
||||
default_pipe(dev) | \
|
||||
USB_DIR_IN)
|
||||
|
||||
/* The D0/D1 toggle bits */
|
||||
#define usb_gettoggle(dev, ep, out) (((dev)->toggle[out] >> ep) & 1)
|
||||
#define usb_dotoggle(dev, ep, out) ((dev)->toggle[out] ^= (1 << ep))
|
||||
#define usb_settoggle(dev, ep, out, bit) ((dev)->toggle[out] = \
|
||||
((dev)->toggle[out] & \
|
||||
~(1 << ep)) | ((bit) << ep))
|
||||
|
||||
/* Endpoint halt control/status */
|
||||
#define usb_endpoint_out(ep_dir) (((ep_dir >> 7) & 1) ^ 1)
|
||||
#define usb_endpoint_halt(dev, ep, out) ((dev)->halted[out] |= (1 << (ep)))
|
||||
#define usb_endpoint_running(dev, ep, out) ((dev)->halted[out] &= ~(1 << (ep)))
|
||||
#define usb_endpoint_halted(dev, ep, out) ((dev)->halted[out] & (1 << (ep)))
|
||||
|
||||
#define usb_packetid(pipe) (((pipe) & USB_DIR_IN) ? USB_PID_IN : \
|
||||
USB_PID_OUT)
|
||||
|
||||
#define usb_pipeout(pipe) ((((pipe) >> 7) & 1) ^ 1)
|
||||
#define usb_pipein(pipe) (((pipe) >> 7) & 1)
|
||||
#define usb_pipedevice(pipe) (((pipe) >> 8) & 0x7f)
|
||||
#define usb_pipe_endpdev(pipe) (((pipe) >> 8) & 0x7ff)
|
||||
#define usb_pipeendpoint(pipe) (((pipe) >> 15) & 0xf)
|
||||
#define usb_pipedata(pipe) (((pipe) >> 19) & 1)
|
||||
#define usb_pipespeed(pipe) (((pipe) >> 26) & 3)
|
||||
#define usb_pipeslow(pipe) (usb_pipespeed(pipe) == USB_SPEED_LOW)
|
||||
#define usb_pipetype(pipe) (((pipe) >> 30) & 3)
|
||||
#define usb_pipeisoc(pipe) (usb_pipetype((pipe)) == PIPE_ISOCHRONOUS)
|
||||
#define usb_pipeint(pipe) (usb_pipetype((pipe)) == PIPE_INTERRUPT)
|
||||
#define usb_pipecontrol(pipe) (usb_pipetype((pipe)) == PIPE_CONTROL)
|
||||
#define usb_pipebulk(pipe) (usb_pipetype((pipe)) == PIPE_BULK)
|
||||
|
||||
|
||||
/*************************************************************************
|
||||
* Hub Stuff
|
||||
*/
|
||||
struct usb_port_status
|
||||
{
|
||||
uint16_t wPortStatus;
|
||||
uint16_t wPortChange;
|
||||
} __attribute__ ((packed));
|
||||
|
||||
struct usb_hub_status
|
||||
{
|
||||
uint16_t wHubStatus;
|
||||
uint16_t wHubChange;
|
||||
} __attribute__ ((packed));
|
||||
|
||||
|
||||
/* Hub descriptor */
|
||||
struct usb_hub_descriptor
|
||||
{
|
||||
uint8_t bLength;
|
||||
uint8_t bDescriptorType;
|
||||
uint8_t bNbrPorts;
|
||||
uint16_t wHubCharacteristics;
|
||||
uint8_t bPwrOn2PwrGood;
|
||||
uint8_t bHubContrCurrent;
|
||||
uint8_t DeviceRemovable[(USB_MAXCHILDREN+1+7)/8];
|
||||
uint8_t PortPowerCtrlMask[(USB_MAXCHILDREN+1+7)/8];
|
||||
/* DeviceRemovable and PortPwrCtrlMask want to be variable-length
|
||||
bitmaps that hold max 255 entries. (bit0 is ignored) */
|
||||
} __attribute__ ((packed));
|
||||
|
||||
|
||||
struct usb_hub_device
|
||||
{
|
||||
struct usb_device *pusb_dev;
|
||||
struct usb_hub_descriptor desc;
|
||||
};
|
||||
|
||||
#endif /*_USB_H_ */
|
||||
252
include/usb_defs.h
Normal file
252
include/usb_defs.h
Normal file
@@ -0,0 +1,252 @@
|
||||
/*
|
||||
* (C) Copyright 2001
|
||||
* Denis Peter, MPL AG Switzerland
|
||||
*
|
||||
* See file CREDITS for list of people who contributed to this
|
||||
* project.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*
|
||||
* Note: Part of this code has been derived from linux
|
||||
*
|
||||
*/
|
||||
#ifndef _USB_DEFS_H_
|
||||
#define _USB_DEFS_H_
|
||||
|
||||
#define CONFIG_USB_INTERRUPT_POLLING
|
||||
/* USB constants */
|
||||
|
||||
/* Device and/or Interface Class codes */
|
||||
#define USB_CLASS_PER_INTERFACE 0 /* for DeviceClass */
|
||||
#define USB_CLASS_AUDIO 1
|
||||
#define USB_CLASS_COMM 2
|
||||
#define USB_CLASS_HID 3
|
||||
#define USB_CLASS_PRINTER 7
|
||||
#define USB_CLASS_MASS_STORAGE 8
|
||||
#define USB_CLASS_HUB 9
|
||||
#define USB_CLASS_DATA 10
|
||||
#define USB_CLASS_VENDOR_SPEC 0xff
|
||||
|
||||
/* some HID sub classes */
|
||||
#define USB_SUB_HID_NONE 0
|
||||
#define USB_SUB_HID_BOOT 1
|
||||
|
||||
/* some UID Protocols */
|
||||
#define USB_PROT_HID_NONE 0
|
||||
#define USB_PROT_HID_KEYBOARD 1
|
||||
#define USB_PROT_HID_MOUSE 2
|
||||
|
||||
|
||||
/* Sub STORAGE Classes */
|
||||
#define US_SC_RBC 1 /* Typically, flash devices */
|
||||
#define US_SC_8020 2 /* CD-ROM */
|
||||
#define US_SC_QIC 3 /* QIC-157 Tapes */
|
||||
#define US_SC_UFI 4 /* Floppy */
|
||||
#define US_SC_8070 5 /* Removable media */
|
||||
#define US_SC_SCSI 6 /* Transparent */
|
||||
#define US_SC_MIN US_SC_RBC
|
||||
#define US_SC_MAX US_SC_SCSI
|
||||
|
||||
/* STORAGE Protocols */
|
||||
#define US_PR_CB 1 /* Control/Bulk w/o interrupt */
|
||||
#define US_PR_CBI 0 /* Control/Bulk/Interrupt */
|
||||
#define US_PR_BULK 0x50 /* bulk only */
|
||||
|
||||
/* USB types */
|
||||
#define USB_TYPE_STANDARD (0x00 << 5)
|
||||
#define USB_TYPE_CLASS (0x01 << 5)
|
||||
#define USB_TYPE_VENDOR (0x02 << 5)
|
||||
#define USB_TYPE_RESERVED (0x03 << 5)
|
||||
|
||||
/* USB recipients */
|
||||
#define USB_RECIP_DEVICE 0x00
|
||||
#define USB_RECIP_INTERFACE 0x01
|
||||
#define USB_RECIP_ENDPOINT 0x02
|
||||
#define USB_RECIP_OTHER 0x03
|
||||
|
||||
/* USB directions */
|
||||
#define USB_DIR_OUT 0
|
||||
#define USB_DIR_IN 0x80
|
||||
|
||||
/* USB device speeds */
|
||||
#define USB_SPEED_FULL 0x0 /* 12Mbps */
|
||||
#define USB_SPEED_LOW 0x1 /* 1.5Mbps */
|
||||
#define USB_SPEED_HIGH 0x2 /* 480Mbps */
|
||||
#define USB_SPEED_RESERVED 0x3
|
||||
|
||||
/* Descriptor types */
|
||||
#define USB_DT_DEVICE 0x01
|
||||
#define USB_DT_CONFIG 0x02
|
||||
#define USB_DT_STRING 0x03
|
||||
#define USB_DT_INTERFACE 0x04
|
||||
#define USB_DT_ENDPOINT 0x05
|
||||
|
||||
#define USB_DT_HID (USB_TYPE_CLASS | 0x01)
|
||||
#define USB_DT_REPORT (USB_TYPE_CLASS | 0x02)
|
||||
#define USB_DT_PHYSICAL (USB_TYPE_CLASS | 0x03)
|
||||
#define USB_DT_HUB (USB_TYPE_CLASS | 0x09)
|
||||
|
||||
/* Descriptor sizes per descriptor type */
|
||||
#define USB_DT_DEVICE_SIZE 18
|
||||
#define USB_DT_CONFIG_SIZE 9
|
||||
#define USB_DT_INTERFACE_SIZE 9
|
||||
#define USB_DT_ENDPOINT_SIZE 7
|
||||
#define USB_DT_ENDPOINT_AUDIO_SIZE 9 /* Audio extension */
|
||||
#define USB_DT_HUB_NONVAR_SIZE 7
|
||||
#define USB_DT_HID_SIZE 9
|
||||
|
||||
/* Endpoints */
|
||||
#define USB_ENDPOINT_NUMBER_MASK 0x0f /* in bEndpointAddress */
|
||||
#define USB_ENDPOINT_DIR_MASK 0x80
|
||||
|
||||
#define USB_ENDPOINT_XFERTYPE_MASK 0x03 /* in bmAttributes */
|
||||
#define USB_ENDPOINT_XFER_CONTROL 0
|
||||
#define USB_ENDPOINT_XFER_ISOC 1
|
||||
#define USB_ENDPOINT_XFER_BULK 2
|
||||
#define USB_ENDPOINT_XFER_INT 3
|
||||
|
||||
/* USB Packet IDs (PIDs) */
|
||||
#define USB_PID_UNDEF_0 0xf0
|
||||
#define USB_PID_OUT 0xe1
|
||||
#define USB_PID_ACK 0xd2
|
||||
#define USB_PID_DATA0 0xc3
|
||||
#define USB_PID_UNDEF_4 0xb4
|
||||
#define USB_PID_SOF 0xa5
|
||||
#define USB_PID_UNDEF_6 0x96
|
||||
#define USB_PID_UNDEF_7 0x87
|
||||
#define USB_PID_UNDEF_8 0x78
|
||||
#define USB_PID_IN 0x69
|
||||
#define USB_PID_NAK 0x5a
|
||||
#define USB_PID_DATA1 0x4b
|
||||
#define USB_PID_PREAMBLE 0x3c
|
||||
#define USB_PID_SETUP 0x2d
|
||||
#define USB_PID_STALL 0x1e
|
||||
#define USB_PID_UNDEF_F 0x0f
|
||||
|
||||
/* Standard requests */
|
||||
#define USB_REQ_GET_STATUS 0x00
|
||||
#define USB_REQ_CLEAR_FEATURE 0x01
|
||||
#define USB_REQ_SET_FEATURE 0x03
|
||||
#define USB_REQ_SET_ADDRESS 0x05
|
||||
#define USB_REQ_GET_DESCRIPTOR 0x06
|
||||
#define USB_REQ_SET_DESCRIPTOR 0x07
|
||||
#define USB_REQ_GET_CONFIGURATION 0x08
|
||||
#define USB_REQ_SET_CONFIGURATION 0x09
|
||||
#define USB_REQ_GET_INTERFACE 0x0A
|
||||
#define USB_REQ_SET_INTERFACE 0x0B
|
||||
#define USB_REQ_SYNCH_FRAME 0x0C
|
||||
|
||||
/* HID requests */
|
||||
#define USB_REQ_GET_REPORT 0x01
|
||||
#define USB_REQ_GET_IDLE 0x02
|
||||
#define USB_REQ_GET_PROTOCOL 0x03
|
||||
#define USB_REQ_SET_REPORT 0x09
|
||||
#define USB_REQ_SET_IDLE 0x0A
|
||||
#define USB_REQ_SET_PROTOCOL 0x0B
|
||||
|
||||
|
||||
/* "pipe" definitions */
|
||||
|
||||
#define PIPE_ISOCHRONOUS 0
|
||||
#define PIPE_INTERRUPT 1
|
||||
#define PIPE_CONTROL 2
|
||||
#define PIPE_BULK 3
|
||||
#define PIPE_DEVEP_MASK 0x0007ff00
|
||||
|
||||
#define USB_ISOCHRONOUS 0
|
||||
#define USB_INTERRUPT 1
|
||||
#define USB_CONTROL 2
|
||||
#define USB_BULK 3
|
||||
|
||||
/* USB-status codes: */
|
||||
#define USB_ST_ACTIVE 0x1 /* TD is active */
|
||||
#define USB_ST_STALLED 0x2 /* TD is stalled */
|
||||
#define USB_ST_BUF_ERR 0x4 /* buffer error */
|
||||
#define USB_ST_BABBLE_DET 0x8 /* Babble detected */
|
||||
#define USB_ST_NAK_REC 0x10 /* NAK Received*/
|
||||
#define USB_ST_CRC_ERR 0x20 /* CRC/timeout Error */
|
||||
#define USB_ST_BIT_ERR 0x40 /* Bitstuff error */
|
||||
#define USB_ST_NOT_PROC 0x80000000L /* Not yet processed */
|
||||
|
||||
|
||||
/*************************************************************************
|
||||
* Hub defines
|
||||
*/
|
||||
|
||||
/*
|
||||
* Hub request types
|
||||
*/
|
||||
|
||||
#define USB_RT_HUB (USB_TYPE_CLASS | USB_RECIP_DEVICE)
|
||||
#define USB_RT_PORT (USB_TYPE_CLASS | USB_RECIP_OTHER)
|
||||
|
||||
/*
|
||||
* Hub Class feature numbers
|
||||
*/
|
||||
#define C_HUB_LOCAL_POWER 0
|
||||
#define C_HUB_OVER_CURRENT 1
|
||||
|
||||
/*
|
||||
* Port feature numbers
|
||||
*/
|
||||
#define USB_PORT_FEAT_CONNECTION 0
|
||||
#define USB_PORT_FEAT_ENABLE 1
|
||||
#define USB_PORT_FEAT_SUSPEND 2
|
||||
#define USB_PORT_FEAT_OVER_CURRENT 3
|
||||
#define USB_PORT_FEAT_RESET 4
|
||||
#define USB_PORT_FEAT_POWER 8
|
||||
#define USB_PORT_FEAT_LOWSPEED 9
|
||||
#define USB_PORT_FEAT_HIGHSPEED 10
|
||||
#define USB_PORT_FEAT_C_CONNECTION 16
|
||||
#define USB_PORT_FEAT_C_ENABLE 17
|
||||
#define USB_PORT_FEAT_C_SUSPEND 18
|
||||
#define USB_PORT_FEAT_C_OVER_CURRENT 19
|
||||
#define USB_PORT_FEAT_C_RESET 20
|
||||
|
||||
/* wPortStatus bits */
|
||||
#define USB_PORT_STAT_CONNECTION 0x0001
|
||||
#define USB_PORT_STAT_ENABLE 0x0002
|
||||
#define USB_PORT_STAT_SUSPEND 0x0004
|
||||
#define USB_PORT_STAT_OVERCURRENT 0x0008
|
||||
#define USB_PORT_STAT_RESET 0x0010
|
||||
#define USB_PORT_STAT_POWER 0x0100
|
||||
#define USB_PORT_STAT_LOW_SPEED 0x0200
|
||||
#define USB_PORT_STAT_HIGH_SPEED 0x0400 /* support for EHCI */
|
||||
#define USB_PORT_STAT_SPEED \
|
||||
(USB_PORT_STAT_LOW_SPEED | USB_PORT_STAT_HIGH_SPEED)
|
||||
|
||||
/* wPortChange bits */
|
||||
#define USB_PORT_STAT_C_CONNECTION 0x0001
|
||||
#define USB_PORT_STAT_C_ENABLE 0x0002
|
||||
#define USB_PORT_STAT_C_SUSPEND 0x0004
|
||||
#define USB_PORT_STAT_C_OVERCURRENT 0x0008
|
||||
#define USB_PORT_STAT_C_RESET 0x0010
|
||||
|
||||
/* wHubCharacteristics (masks) */
|
||||
#define HUB_CHAR_LPSM 0x0003
|
||||
#define HUB_CHAR_COMPOUND 0x0004
|
||||
#define HUB_CHAR_OCPM 0x0018
|
||||
|
||||
/*
|
||||
*Hub Status & Hub Change bit masks
|
||||
*/
|
||||
#define HUB_STATUS_LOCAL_POWER 0x0001
|
||||
#define HUB_STATUS_OVERCURRENT 0x0002
|
||||
|
||||
#define HUB_CHANGE_LOCAL_POWER 0x0001
|
||||
#define HUB_CHANGE_OVERCURRENT 0x0002
|
||||
|
||||
#endif /*_USB_DEFS_H_ */
|
||||
10
include/usb_hub.h
Normal file
10
include/usb_hub.h
Normal file
@@ -0,0 +1,10 @@
|
||||
#ifndef USB_HUB_H
|
||||
#define USB_HUB_H
|
||||
|
||||
extern int bus_index;
|
||||
|
||||
extern void usb_hub_reset(int bus_index);
|
||||
extern int usb_hub_probe(struct usb_device *dev, int ifnum);
|
||||
extern int hub_port_reset(struct usb_device *dev, int port, unsigned short *portstat);
|
||||
|
||||
#endif // USB_HUB_H
|
||||
128
include/util.h
Normal file
128
include/util.h
Normal file
@@ -0,0 +1,128 @@
|
||||
/*
|
||||
* util.h
|
||||
*
|
||||
* Byteswapping macros lend from EmuTOS sources
|
||||
*
|
||||
* This file is part of BaS_gcc.
|
||||
*
|
||||
* BaS_gcc is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* BaS_gcc is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* Created on: 27.10.2013
|
||||
* Author: mfro
|
||||
*/
|
||||
|
||||
#ifndef _UTIL_H_
|
||||
#define _UTIL_H_
|
||||
|
||||
#include <bas_types.h>
|
||||
|
||||
#define NOP() __asm__ __volatile__("nop\n\t" : : : "memory")
|
||||
|
||||
/*
|
||||
* uint16_t swpw(uint16_t val);
|
||||
* swap endianess of val, 16 bits only.
|
||||
*/
|
||||
static inline uint16_t swpw(uint16_t w)
|
||||
{
|
||||
return (w << 8) | (w >> 8);
|
||||
}
|
||||
|
||||
/*
|
||||
* uint32_t swpl(uint32_t val);
|
||||
* swap endianess of val, 32 bits only.
|
||||
* e.g. ABCD => DCBA
|
||||
*/
|
||||
static inline uint32_t swpl(uint32_t l)
|
||||
{
|
||||
return ((l & 0xff000000) >> 24) | ((l & 0x00ff0000) >> 8) |
|
||||
((l & 0x0000ff00) << 8) | (l << 24);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* WORD swpw2(ULONG val);
|
||||
* swap endianness of val, treated as two 16-bit words.
|
||||
* e.g. ABCD => BADC
|
||||
*/
|
||||
|
||||
#define swpw2(a) \
|
||||
__extension__ \
|
||||
({unsigned long _tmp; \
|
||||
__asm__ __volatile__ \
|
||||
("move.b (%1),%0\n\t" \
|
||||
"move.b 1(%1),(%1)\n\t" \
|
||||
"move.b %0,1(%1)\n\t" \
|
||||
"move.b 2(%1),%0\n\t" \
|
||||
"move.b 3(%1),2(%1)\n\t" \
|
||||
"move.b %0,3(%1)" \
|
||||
: "=d"(_tmp) /* outputs */ \
|
||||
: "a"(&a) /* inputs */ \
|
||||
: "cc", "memory" /* clobbered */ \
|
||||
); \
|
||||
})
|
||||
|
||||
/*
|
||||
* WORD set_sr(WORD new);
|
||||
* sets sr to the new value, and return the old sr value
|
||||
*/
|
||||
|
||||
#define set_sr(a) \
|
||||
__extension__ \
|
||||
({short _r, _a = (a); \
|
||||
__asm__ __volatile__ \
|
||||
("move.w sr,%0\n\t" \
|
||||
"move.w %1,sr" \
|
||||
: "=&d"(_r) /* outputs */ \
|
||||
: "nd"(_a) /* inputs */ \
|
||||
: "cc", "memory" /* clobbered */ \
|
||||
); \
|
||||
_r; \
|
||||
})
|
||||
|
||||
|
||||
/*
|
||||
* WORD get_sr(void);
|
||||
* returns the current value of sr.
|
||||
*/
|
||||
|
||||
#define get_sr() \
|
||||
__extension__ \
|
||||
({short _r; \
|
||||
__asm__ volatile \
|
||||
("move.w sr,%0" \
|
||||
: "=dm"(_r) /* outputs */ \
|
||||
: /* inputs */ \
|
||||
: "cc", "memory" /* clobbered */ \
|
||||
); \
|
||||
_r; \
|
||||
})
|
||||
|
||||
|
||||
|
||||
/*
|
||||
* void regsafe_call(void *addr)
|
||||
* Saves all registers to the stack, calls the function
|
||||
* that addr points to, and restores the registers afterwards.
|
||||
*/
|
||||
#define regsafe_call(addr) \
|
||||
__extension__ \
|
||||
({__asm__ volatile ("lea -60(sp),sp\n\t" \
|
||||
"movem.l d0-d7/a0-a6,(sp)"); \
|
||||
((void (*) (void)) addr)(); \
|
||||
__asm__ volatile ("movem.l (sp),d0-d7/a0-a6\n\t" \
|
||||
"lea 60(sp),sp"); \
|
||||
})
|
||||
|
||||
|
||||
#endif /* UTIL_H_ */
|
||||
35
include/version.h
Normal file
35
include/version.h
Normal file
@@ -0,0 +1,35 @@
|
||||
/*
|
||||
* version.h
|
||||
*
|
||||
* Created on: 21.10.2013
|
||||
* Author: Markus Fröschle
|
||||
*
|
||||
* This file is part of BaS_gcc.
|
||||
*
|
||||
* BaS_gcc is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* BaS_gcc is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef VERSION_H_
|
||||
#define VERSION_H_
|
||||
|
||||
/*
|
||||
* increment version number for release
|
||||
*/
|
||||
|
||||
#define MAJOR_VERSION 0
|
||||
#define MINOR_VERSION 93
|
||||
|
||||
|
||||
#endif /* VERSION_H_ */
|
||||
98
include/videl.h
Normal file
98
include/videl.h
Normal file
@@ -0,0 +1,98 @@
|
||||
/*
|
||||
* screen.h - low-level screen routines
|
||||
*
|
||||
* Copyright (c) 2013 The EmuTOS development team
|
||||
*
|
||||
* Authors:
|
||||
* PES Petr Stehlik
|
||||
* RFB Roger Burrows
|
||||
*
|
||||
* This file is distributed under the GPL, version 2 or at your
|
||||
* option any later version. See doc/license.txt for details.
|
||||
*/
|
||||
|
||||
#ifndef VIDEL_H
|
||||
#define VIDEL_H
|
||||
|
||||
#define SPSHIFT 0xffff8266L
|
||||
|
||||
#define FRGB_BLACK 0x00000000 /* Falcon palette */
|
||||
#define FRGB_BLUE 0x000000ff
|
||||
#define FRGB_GREEN 0x00ff0000
|
||||
#define FRGB_CYAN 0x00ff00ff
|
||||
#define FRGB_RED 0xff000000
|
||||
#define FRGB_MAGENTA 0xff0000ff
|
||||
#define FRGB_LTGRAY 0xbbbb00bb
|
||||
#define FRGB_GRAY 0x88880088
|
||||
#define FRGB_LTBLUE 0x000000aa
|
||||
#define FRGB_LTGREEN 0x00aa0000
|
||||
#define FRGB_LTCYAN 0x00aa00aa
|
||||
#define FRGB_LTRED 0xaa000000
|
||||
#define FRGB_LTMAGENTA 0xaa0000aa
|
||||
#define FRGB_YELLOW 0xffff0000
|
||||
#define FRGB_LTYELLOW 0xaaaa0000
|
||||
#define FRGB_WHITE 0xffff00ff
|
||||
|
||||
/* bit settings for Falcon videomodes */
|
||||
#define VIDEL_VALID 0x01ff /* the only bits allowed in a videomode */
|
||||
#define VIDEL_VERTICAL 0x0100 /* if set, use interlace (TV), double line (VGA) */
|
||||
#define VIDEL_COMPAT 0x0080 /* ST-compatible if set */
|
||||
#define VIDEL_OVERSCAN 0x0040 /* overscan if set (not used with VGA) */
|
||||
#define VIDEL_PAL 0x0020 /* PAL if set; otherwise NTSC */
|
||||
#define VIDEL_VGA 0x0010 /* VGA if set; otherwise TV */
|
||||
#define VIDEL_80COL 0x0008 /* 80-column mode if set; otherwise 40 */
|
||||
#define VIDEL_BPPMASK 0x0007 /* mask for bits/pixel encoding */
|
||||
#define VIDEL_1BPP 0 /* 2 colours */
|
||||
#define VIDEL_2BPP 1 /* 4 colours */
|
||||
#define VIDEL_4BPP 2 /* 16 colours */
|
||||
#define VIDEL_8BPP 3 /* 256 colours */
|
||||
#define VIDEL_TRUECOLOR 4 /* 65536 colours */
|
||||
|
||||
/* test for VDI support of videomode */
|
||||
#define VALID_VDI_BPP(mode) ((mode&VIDEL_BPPMASK)<=VIDEL_8BPP)
|
||||
|
||||
/* selected Falcon videomodes */
|
||||
#define FALCON_ST_HIGH (VIDEL_COMPAT|VIDEL_VGA|VIDEL_80COL|VIDEL_1BPP)
|
||||
|
||||
#define FALCON_DEFAULT_BOOT (VIDEL_VERTICAL|VIDEL_80COL|VIDEL_8BPP) /* 640x480x256 colours, TV, NTSC */
|
||||
|
||||
#define FALCON_REZ 3 /* used as a Falcon indicator */
|
||||
|
||||
typedef struct {
|
||||
int16_t vmode; /* video mode (-1 => end marker) */
|
||||
int16_t monitor; /* applicable monitors */
|
||||
uint16_t hht; /* H hold timer */
|
||||
uint16_t hbb; /* H border begin */
|
||||
uint16_t hbe; /* H border end */
|
||||
uint16_t hdb; /* H display begin */
|
||||
uint16_t hde; /* H display end */
|
||||
uint16_t hss; /* H SS */
|
||||
uint16_t vft; /* V freq timer */
|
||||
uint16_t vbb; /* V border begin */
|
||||
uint16_t vbe; /* V border end */
|
||||
uint16_t vdb; /* V display begin */
|
||||
uint16_t vde; /* V display end */
|
||||
uint16_t vss; /* V SS */
|
||||
} VMODE_ENTRY;
|
||||
|
||||
extern void initialise_falcon_palette(int16_t mode);
|
||||
extern const VMODE_ENTRY *lookup_videl_mode(int16_t mode,int16_t monitor);
|
||||
|
||||
/* Public XBIOS functions */
|
||||
extern int16_t vsetmode(int16_t mode);
|
||||
extern int16_t vmontype(void);
|
||||
extern int16_t vsetsync(int16_t external);
|
||||
extern int32_t vgetsize(int16_t mode);
|
||||
extern int16_t vsetrgb(int16_t index,int16_t count, uint32_t *rgb);
|
||||
extern int16_t vgetrgb(int16_t index,int16_t count, uint32_t *rgb);
|
||||
|
||||
/* misc routines */
|
||||
extern int16_t get_videl_mode(void);
|
||||
extern int16_t vfixmode(int16_t mode);
|
||||
extern int16_t videl_check_moderez(int16_t moderez);
|
||||
extern uint32_t videl_vram_size(void);
|
||||
extern void videl_get_current_mode_info(uint16_t *planes, uint16_t *hz_rez, uint16_t *vt_rez);
|
||||
|
||||
extern int16_t current_video_mode;
|
||||
|
||||
#endif /* VIDEL_H */
|
||||
158
include/x86emu.h
Normal file
158
include/x86emu.h
Normal file
@@ -0,0 +1,158 @@
|
||||
/* $NetBSD: x86emu.h,v 1.1 2007/12/01 20:14:10 joerg Exp $ */
|
||||
|
||||
/****************************************************************************
|
||||
*
|
||||
* Realmode X86 Emulator Library
|
||||
*
|
||||
* Copyright (C) 1996-1999 SciTech Software, Inc.
|
||||
* Copyright (C) David Mosberger-Tang
|
||||
* Copyright (C) 1999 Egbert Eich
|
||||
* Copyright (C) 2007 Joerg Sonnenberger
|
||||
*
|
||||
* ========================================================================
|
||||
*
|
||||
* Permission to use, copy, modify, distribute, and sell this software and
|
||||
* its documentation for any purpose is hereby granted without fee,
|
||||
* provided that the above copyright notice appear in all copies and that
|
||||
* both that copyright notice and this permission notice appear in
|
||||
* supporting documentation, and that the name of the authors not be used
|
||||
* in advertising or publicity pertaining to distribution of the software
|
||||
* without specific, written prior permission. The authors makes no
|
||||
* representations about the suitability of this software for any purpose.
|
||||
* It is provided "as is" without express or implied warranty.
|
||||
*
|
||||
* THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
|
||||
* INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
|
||||
* EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
|
||||
* CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
|
||||
* USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
|
||||
* OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
|
||||
* PERFORMANCE OF THIS SOFTWARE.
|
||||
*
|
||||
****************************************************************************/
|
||||
|
||||
#ifndef __X86EMU_X86EMU_H
|
||||
#define __X86EMU_X86EMU_H
|
||||
|
||||
#include "bas_types.h"
|
||||
#include "setjmp.h"
|
||||
|
||||
/*
|
||||
* General EAX, EBX, ECX, EDX type registers. Note that for
|
||||
* portability, and speed, the issue of byte swapping is not addressed
|
||||
* in the registers. All registers are stored in the default format
|
||||
* available on the host machine. The only critical issue is that the
|
||||
* registers should line up EXACTLY in the same manner as they do in
|
||||
* the 386. That is:
|
||||
*
|
||||
* EAX & 0xff === AL
|
||||
* EAX & 0xffff == AX
|
||||
*
|
||||
* etc. The result is that alot of the calculations can then be
|
||||
* done using the native instruction set fully.
|
||||
*/
|
||||
|
||||
|
||||
struct X86EMU_register32 {
|
||||
uint32_t e_reg;
|
||||
};
|
||||
|
||||
struct X86EMU_register16 {
|
||||
uint16_t filler0;
|
||||
uint16_t x_reg;
|
||||
};
|
||||
|
||||
struct X86EMU_register8 {
|
||||
uint8_t filler0, filler1;
|
||||
uint8_t h_reg, l_reg;
|
||||
};
|
||||
|
||||
|
||||
union X86EMU_register {
|
||||
struct X86EMU_register32 I32_reg;
|
||||
struct X86EMU_register16 I16_reg;
|
||||
struct X86EMU_register8 I8_reg;
|
||||
};
|
||||
|
||||
struct X86EMU_regs {
|
||||
uint16_t register_cs;
|
||||
uint16_t register_ds;
|
||||
uint16_t register_es;
|
||||
uint16_t register_fs;
|
||||
uint16_t register_gs;
|
||||
uint16_t register_ss;
|
||||
uint32_t register_flags;
|
||||
union X86EMU_register register_a;
|
||||
union X86EMU_register register_b;
|
||||
union X86EMU_register register_c;
|
||||
union X86EMU_register register_d;
|
||||
|
||||
union X86EMU_register register_sp;
|
||||
union X86EMU_register register_bp;
|
||||
union X86EMU_register register_si;
|
||||
union X86EMU_register register_di;
|
||||
union X86EMU_register register_ip;
|
||||
|
||||
/*
|
||||
* MODE contains information on:
|
||||
* REPE prefix 2 bits repe,repne
|
||||
* SEGMENT overrides 5 bits normal,DS,SS,CS,ES
|
||||
* Delayed flag set 3 bits (zero, signed, parity)
|
||||
* reserved 6 bits
|
||||
* interrupt # 8 bits instruction raised interrupt
|
||||
* BIOS video segregs 4 bits
|
||||
* Interrupt Pending 1 bits
|
||||
* Extern interrupt 1 bits
|
||||
* Halted 1 bits
|
||||
*/
|
||||
uint32_t mode;
|
||||
volatile int intr; /* mask of pending interrupts */
|
||||
uint8_t intno;
|
||||
uint8_t __pad[3];
|
||||
};
|
||||
|
||||
struct X86EMU
|
||||
{
|
||||
char *mem_base;
|
||||
size_t mem_size;
|
||||
void *sys_private;
|
||||
struct X86EMU_regs x86;
|
||||
|
||||
jmp_buf exec_state;
|
||||
|
||||
uint64_t cur_cycles;
|
||||
|
||||
unsigned int cur_mod:2;
|
||||
unsigned int cur_rl:3;
|
||||
unsigned int cur_rh:3;
|
||||
uint32_t cur_offset;
|
||||
|
||||
uint8_t (*emu_rdb)(struct X86EMU *, uint32_t addr);
|
||||
uint16_t (*emu_rdw)(struct X86EMU *, uint32_t addr);
|
||||
uint32_t (*emu_rdl)(struct X86EMU *, uint32_t addr);
|
||||
void (*emu_wrb)(struct X86EMU *, uint32_t addr,uint8_t val);
|
||||
void (*emu_wrw)(struct X86EMU *, uint32_t addr, uint16_t val);
|
||||
void (*emu_wrl)(struct X86EMU *, uint32_t addr, uint32_t val);
|
||||
|
||||
uint8_t (*emu_inb)(struct X86EMU *, uint16_t addr);
|
||||
uint16_t (*emu_inw)(struct X86EMU *, uint16_t addr);
|
||||
uint32_t (*emu_inl)(struct X86EMU *, uint16_t addr);
|
||||
void (*emu_outb)(struct X86EMU *, uint16_t addr, uint8_t val);
|
||||
void (*emu_outw)(struct X86EMU *, uint16_t addr, uint16_t val);
|
||||
void (*emu_outl)(struct X86EMU *, uint16_t addr, uint32_t val);
|
||||
|
||||
void (*_X86EMU_intrTab[256])(struct X86EMU *, int);
|
||||
};
|
||||
|
||||
|
||||
void X86EMU_init_default(struct X86EMU *);
|
||||
|
||||
/* decode.c */
|
||||
|
||||
void X86EMU_exec(struct X86EMU *);
|
||||
void X86EMU_exec_call(struct X86EMU *, uint16_t, uint16_t);
|
||||
void X86EMU_exec_intr(struct X86EMU *, uint8_t);
|
||||
void X86EMU_halt_sys(struct X86EMU *);
|
||||
|
||||
|
||||
#endif /* __X86EMU_X86EMU_H */
|
||||
53
include/x86pcibios.h
Normal file
53
include/x86pcibios.h
Normal file
@@ -0,0 +1,53 @@
|
||||
#ifndef _PCI_BIOS_H_
|
||||
#define _PCI_BIOS_H_
|
||||
|
||||
enum
|
||||
{
|
||||
PCI_BIOS_PRESENT = 0xB101,
|
||||
FIND_PCI_DEVICE = 0xB102,
|
||||
FIND_PCI_CLASS_CODE = 0xB103,
|
||||
GENERATE_SPECIAL_CYCLE = 0xB106,
|
||||
READ_CONFIG_BYTE = 0xB108,
|
||||
READ_CONFIG_WORD = 0xB109,
|
||||
READ_CONFIG_DWORD = 0xB10A,
|
||||
WRITE_CONFIG_BYTE = 0xB10B,
|
||||
WRITE_CONFIG_WORD = 0xB10C,
|
||||
WRITE_CONFIG_DWORD = 0xB10D,
|
||||
GET_IRQ_ROUTING_OPTIONS = 0xB10E,
|
||||
SET_PCI_IRQ = 0xB10F
|
||||
};
|
||||
|
||||
enum
|
||||
{
|
||||
SUCCESSFUL = 0x00,
|
||||
FUNC_NOT_SUPPORTED = 0x81,
|
||||
BAD_VENDOR_ID = 0x83,
|
||||
DEVICE_NOT_FOUND = 0x86,
|
||||
BAD_REGISTER_NUMBER = 0x87,
|
||||
SET_FAILED = 0x88,
|
||||
BUFFER_TOO_SMALL = 0x89
|
||||
};
|
||||
|
||||
extern int x86_pcibios_handler(struct X86EMU *emu);
|
||||
|
||||
|
||||
#define USE_SDRAM
|
||||
#define DIRECT_ACCESS
|
||||
|
||||
#define MEM_WB(where, what) emu->emu_wrb(emu, where, what)
|
||||
#define MEM_WW(where, what) emu->emu_wrw(emu, where, what)
|
||||
#define MEM_WL(where, what) emu->emu_wrl(emu, where, what)
|
||||
|
||||
#define MEM_RB(where) emu->emu_rdb(emu, where)
|
||||
#define MEM_RW(where) emu->emu_rdw(emu, where)
|
||||
#define MEM_RL(where) emu->emu_rdl(emu, where)
|
||||
|
||||
#define PCI_VGA_RAM_IMAGE_START 0xC0000
|
||||
#define PCI_RAM_IMAGE_START 0xD0000
|
||||
#define SYS_BIOS 0xF0000
|
||||
#define SIZE_EMU 0x100000
|
||||
#define BIOS_MEM 0x100000UL
|
||||
|
||||
|
||||
#endif /* _PCI_BIOS_H_ */
|
||||
|
||||
Reference in New Issue
Block a user