Initial commit
This commit is contained in:
Markus
GitHub
52
.gitignore
vendored
Normal file
52
.gitignore
vendored
Normal file
@@ -0,0 +1,52 @@
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||||
# Prerequisites
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||||
*.d
|
||||
|
||||
# Object files
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||||
*.o
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||||
*.ko
|
||||
*.obj
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||||
*.elf
|
||||
|
||||
# Linker output
|
||||
*.ilk
|
||||
*.map
|
||||
*.exp
|
||||
|
||||
# Precompiled Headers
|
||||
*.gch
|
||||
*.pch
|
||||
|
||||
# Libraries
|
||||
*.lib
|
||||
*.a
|
||||
*.la
|
||||
*.lo
|
||||
|
||||
# Shared objects (inc. Windows DLLs)
|
||||
*.dll
|
||||
*.so
|
||||
*.so.*
|
||||
*.dylib
|
||||
|
||||
# Executables
|
||||
*.exe
|
||||
*.out
|
||||
*.app
|
||||
*.i*86
|
||||
*.x86_64
|
||||
*.hex
|
||||
|
||||
# Debug files
|
||||
*.dSYM/
|
||||
*.su
|
||||
*.idb
|
||||
*.pdb
|
||||
|
||||
# Kernel Module Compile Results
|
||||
*.mod*
|
||||
*.cmd
|
||||
.tmp_versions/
|
||||
modules.order
|
||||
Module.symvers
|
||||
Mkfile.old
|
||||
dkms.conf
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||||
@@ -1,16 +0,0 @@
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||||
#set disassemble-next-line on
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||||
define tr
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||||
#!killall m68k-bdm-gdbserver
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||||
target remote | m68k-bdm-gdbserver pipe /dev/bdmcf3
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||||
#target remote localhost:1234
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||||
#target remote | m68k-bdm-gdbserver pipe /dev/tblcf2
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||||
#target dbug /dev/ttyS0
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||||
#monitor bdm-reset
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||||
end
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||||
define tbtr
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||||
target remote | m68k-bdm-gdbserver pipe /dev/tblcf2
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end
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||||
source mcf5474.gdb
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||||
set breakpoint auto-hw
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||||
|
||||
|
||||
22
BaS_gcc/.indent.pro
vendored
22
BaS_gcc/.indent.pro
vendored
@@ -1,22 +0,0 @@
|
||||
-bad
|
||||
-bap
|
||||
-bbb
|
||||
-bbo
|
||||
-bl
|
||||
-blf
|
||||
-bli0
|
||||
-bls
|
||||
-bs
|
||||
-cbi0
|
||||
-cdb
|
||||
-cli4
|
||||
-cs
|
||||
-i4
|
||||
-lp
|
||||
-saf
|
||||
-sai
|
||||
-saw
|
||||
-ts4
|
||||
-npcs
|
||||
-npsl
|
||||
|
||||
@@ -1,3 +0,0 @@
|
||||
// Add predefined macros for your project here. For example:
|
||||
// #define THE_ANSWER 42
|
||||
#define MACHINE_FIREBEE
|
||||
@@ -1 +0,0 @@
|
||||
[General]
|
||||
@@ -1,397 +0,0 @@
|
||||
dma/dma.c
|
||||
dma/MCD_dmaApi.c
|
||||
dma/MCD_tasks.c
|
||||
dma/MCD_tasksInit.c
|
||||
exe/basflash.c
|
||||
exe/basflash_start.c
|
||||
firebee/bas.elf
|
||||
firebee/bas.lk
|
||||
firebee/bas.map
|
||||
firebee/bas.s19
|
||||
firebee/basflash.elf
|
||||
firebee/basflash.lk
|
||||
firebee/basflash.map
|
||||
firebee/basflash.s19
|
||||
firebee/depend
|
||||
firebee/libbas.a
|
||||
firebee/ram.elf
|
||||
firebee/ram.lk
|
||||
firebee/ram.map
|
||||
firebee/ram.s19
|
||||
flash/flash.c
|
||||
flash/s19reader.c
|
||||
flash_scripts/flash_firebee_bas.bdm
|
||||
flash_scripts/flash_firebee_etos.bdm
|
||||
flash_scripts/flash_firebee_firetos.bdm
|
||||
flash_scripts/flash_firebee_fpga.bdm
|
||||
flash_scripts/flash_m548x_bas.bdm
|
||||
flash_scripts/flash_m548x_dbug.bdm
|
||||
flash_scripts/flash_m548x_etos.bdm
|
||||
flash_scripts/m548xlite_dbug_ram.elf
|
||||
flash_scripts/m548xlite_dbug_ram.s19
|
||||
flash_scripts/run_m548x_dbug.bdm
|
||||
fs/cc932.c
|
||||
fs/cc936.c
|
||||
fs/cc949.c
|
||||
fs/cc950.c
|
||||
fs/ccsbcs.c
|
||||
fs/ff.c
|
||||
fs/unicode.c
|
||||
i2c/i2c.c
|
||||
if/driver_vec.c
|
||||
include/acia.h
|
||||
include/am79c874.h
|
||||
include/arp.h
|
||||
include/ati_ids.h
|
||||
include/bas_printf.h
|
||||
include/bas_string.h
|
||||
include/bas_types.h
|
||||
include/bas_utils.h
|
||||
include/bcm5222.h
|
||||
include/bootp.h
|
||||
include/cache.h
|
||||
include/conout.h
|
||||
include/debug.h
|
||||
include/diskio.h
|
||||
include/dma.h
|
||||
include/driver_mem.h
|
||||
include/driver_vec.h
|
||||
include/edid.h
|
||||
include/ehci.h
|
||||
include/eth.h
|
||||
include/exceptions.h
|
||||
include/fb.h
|
||||
include/fec.h
|
||||
include/fecbd.h
|
||||
include/ff.h
|
||||
include/ffconf.h
|
||||
include/firebee.h
|
||||
include/font.h
|
||||
include/i2c-algo-bit.h
|
||||
include/i2c.h
|
||||
include/icmp.h
|
||||
include/ikbd.h
|
||||
include/interrupts.h
|
||||
include/ip.h
|
||||
include/m54455.h
|
||||
include/m5484l.h
|
||||
include/MCD_dma.h
|
||||
include/mcd_initiators.h
|
||||
include/MCD_progCheck.h
|
||||
include/MCD_tasksInit.h
|
||||
include/MCF5475.h
|
||||
include/MCF5475_CLOCK.h
|
||||
include/MCF5475_CTM.h
|
||||
include/MCF5475_DMA.h
|
||||
include/MCF5475_DSPI.h
|
||||
include/MCF5475_EPORT.h
|
||||
include/MCF5475_FBCS.h
|
||||
include/MCF5475_FEC.h
|
||||
include/MCF5475_GPIO.h
|
||||
include/MCF5475_GPT.h
|
||||
include/MCF5475_I2C.h
|
||||
include/MCF5475_INTC.h
|
||||
include/MCF5475_MMU.h
|
||||
include/MCF5475_PAD.h
|
||||
include/MCF5475_PCI.h
|
||||
include/MCF5475_PCIARB.h
|
||||
include/MCF5475_PSC.h
|
||||
include/MCF5475_SDRAMC.h
|
||||
include/MCF5475_SEC.h
|
||||
include/MCF5475_SIU.h
|
||||
include/MCF5475_SLT.h
|
||||
include/MCF5475_SRAM.h
|
||||
include/MCF5475_USB.h
|
||||
include/MCF5475_XLB.h
|
||||
include/mmu.h
|
||||
include/mod_devicetable.h
|
||||
include/nbuf.h
|
||||
include/net.h
|
||||
include/net_timer.h
|
||||
include/nif.h
|
||||
include/ohci.h
|
||||
include/part.h
|
||||
include/pci.h
|
||||
include/pci_errata.h
|
||||
include/pci_ids.h
|
||||
include/queue.h
|
||||
include/radeon_reg.h
|
||||
include/radeonfb.h
|
||||
include/s19reader.h
|
||||
include/screen.h
|
||||
include/sd_card.h
|
||||
include/setjmp.h
|
||||
include/startcf.h
|
||||
include/sysinit.h
|
||||
include/tftp.h
|
||||
include/udp.h
|
||||
include/usb.h
|
||||
include/usb_defs.h
|
||||
include/usb_hub.h
|
||||
include/user_io.h
|
||||
include/util.h
|
||||
include/version.h
|
||||
include/videl.h
|
||||
include/video.h
|
||||
include/wait.h
|
||||
include/x86emu.h
|
||||
include/x86emu_regs.h
|
||||
include/x86pcibios.h
|
||||
include/xhdi_sd.h
|
||||
kbd/ikbd.c
|
||||
m54455/bas.elf
|
||||
m54455/bas.lk
|
||||
m54455/bas.map
|
||||
m54455/bas.s19
|
||||
m54455/basflash.elf
|
||||
m54455/basflash.lk
|
||||
m54455/basflash.map
|
||||
m54455/basflash.s19
|
||||
m54455/depend
|
||||
m54455/libbas.a
|
||||
m54455/ram.elf
|
||||
m54455/ram.lk
|
||||
m54455/ram.map
|
||||
m54455/ram.s19
|
||||
m5484lite/bas.elf
|
||||
m5484lite/bas.lk
|
||||
m5484lite/bas.map
|
||||
m5484lite/bas.s19
|
||||
m5484lite/basflash.elf
|
||||
m5484lite/basflash.lk
|
||||
m5484lite/basflash.map
|
||||
m5484lite/basflash.s19
|
||||
m5484lite/depend
|
||||
m5484lite/libbas.a
|
||||
m5484lite/ram.elf
|
||||
m5484lite/ram.lk
|
||||
m5484lite/ram.map
|
||||
m5484lite/ram.s19
|
||||
net/am79c874.c
|
||||
net/arp.c
|
||||
net/bcm5222.c
|
||||
net/bootp.c
|
||||
net/fec.c
|
||||
net/fecbd.c
|
||||
net/ip.c
|
||||
net/nbuf.c
|
||||
net/net_timer.c
|
||||
net/nif.c
|
||||
net/queue.c
|
||||
net/tftp.c
|
||||
net/udp.c
|
||||
nutil/s19header.c
|
||||
pci/ehci-hcd.c
|
||||
pci/ohci-hcd.c
|
||||
pci/pci.c
|
||||
pci/pci_errata.c
|
||||
pci/pci_wrappers.S
|
||||
radeon/i2c-algo-bit.c
|
||||
radeon/radeon_accel.c
|
||||
radeon/radeon_base.c
|
||||
radeon/radeon_cursor.c
|
||||
radeon/radeon_i2c.c
|
||||
radeon/radeon_monitor.c
|
||||
release/firebee/bas.s19
|
||||
release/m5484lite/bas.s19
|
||||
release/bascook.prg
|
||||
release/readme.txt
|
||||
spi/dspi.c
|
||||
spi/mmc.c
|
||||
spi/sd_card.c
|
||||
sys/BaS.c
|
||||
sys/cache.c
|
||||
sys/driver_mem.c
|
||||
sys/exceptions.S
|
||||
sys/fault_vectors.c
|
||||
sys/init_fpga.c
|
||||
sys/interrupts.c
|
||||
sys/mmu.c
|
||||
sys/startcf.S
|
||||
sys/sysinit.c
|
||||
tos/bascook/sources/bascook.c
|
||||
tos/bascook/bascook.prg
|
||||
tos/bascook/depend
|
||||
tos/bascook/mapfile
|
||||
tos/fpga_test/m5475/mshort/fpga_test.prg
|
||||
tos/fpga_test/m5475/fpga_test.prg
|
||||
tos/fpga_test/sources/fpga_test.c
|
||||
tos/fpga_test/sources/ser_printf.c
|
||||
tos/fpga_test/sources/vmem_test.c
|
||||
tos/fpga_test/depend
|
||||
tos/fpga_test/mapfile
|
||||
tos/jtagwait/include/bas_printf.h
|
||||
tos/jtagwait/include/bas_string.h
|
||||
tos/jtagwait/include/driver_vec.h
|
||||
tos/jtagwait/include/MCF5475.h
|
||||
tos/jtagwait/include/MCF5475_CLOCK.h
|
||||
tos/jtagwait/include/MCF5475_CTM.h
|
||||
tos/jtagwait/include/MCF5475_DMA.h
|
||||
tos/jtagwait/include/MCF5475_DSPI.h
|
||||
tos/jtagwait/include/MCF5475_EPORT.h
|
||||
tos/jtagwait/include/MCF5475_FBCS.h
|
||||
tos/jtagwait/include/MCF5475_FEC.h
|
||||
tos/jtagwait/include/MCF5475_GPIO.h
|
||||
tos/jtagwait/include/MCF5475_GPT.h
|
||||
tos/jtagwait/include/MCF5475_I2C.h
|
||||
tos/jtagwait/include/MCF5475_INTC.h
|
||||
tos/jtagwait/include/MCF5475_MMU.h
|
||||
tos/jtagwait/include/MCF5475_PAD.h
|
||||
tos/jtagwait/include/MCF5475_PCI.h
|
||||
tos/jtagwait/include/MCF5475_PCIARB.h
|
||||
tos/jtagwait/include/MCF5475_PSC.h
|
||||
tos/jtagwait/include/MCF5475_SDRAMC.h
|
||||
tos/jtagwait/include/MCF5475_SEC.h
|
||||
tos/jtagwait/include/MCF5475_SIU.h
|
||||
tos/jtagwait/include/MCF5475_SLT.h
|
||||
tos/jtagwait/include/MCF5475_SRAM.h
|
||||
tos/jtagwait/include/MCF5475_USB.h
|
||||
tos/jtagwait/include/MCF5475_XLB.h
|
||||
tos/jtagwait/m5475/mshort/jtagwait.prg
|
||||
tos/jtagwait/m5475/jtagwait.prg
|
||||
tos/jtagwait/sources/bas_printf.c
|
||||
tos/jtagwait/sources/bas_string.c
|
||||
tos/jtagwait/sources/jtagwait.c
|
||||
tos/jtagwait/sources/printf_helper.S
|
||||
tos/jtagwait/depend
|
||||
tos/jtagwait/mapfile
|
||||
tos/pci_mem/include/bas_string.h
|
||||
tos/pci_mem/include/bas_types.h
|
||||
tos/pci_mem/include/driver_vec.h
|
||||
tos/pci_mem/include/MCF5475.h
|
||||
tos/pci_mem/include/MCF5475_CLOCK.h
|
||||
tos/pci_mem/include/MCF5475_CTM.h
|
||||
tos/pci_mem/include/MCF5475_DMA.h
|
||||
tos/pci_mem/include/MCF5475_DSPI.h
|
||||
tos/pci_mem/include/MCF5475_EPORT.h
|
||||
tos/pci_mem/include/MCF5475_FBCS.h
|
||||
tos/pci_mem/include/MCF5475_FEC.h
|
||||
tos/pci_mem/include/MCF5475_GPIO.h
|
||||
tos/pci_mem/include/MCF5475_GPT.h
|
||||
tos/pci_mem/include/MCF5475_I2C.h
|
||||
tos/pci_mem/include/MCF5475_INTC.h
|
||||
tos/pci_mem/include/MCF5475_MMU.h
|
||||
tos/pci_mem/include/MCF5475_PAD.h
|
||||
tos/pci_mem/include/MCF5475_PCI.h
|
||||
tos/pci_mem/include/MCF5475_PCIARB.h
|
||||
tos/pci_mem/include/MCF5475_PSC.h
|
||||
tos/pci_mem/include/MCF5475_SDRAMC.h
|
||||
tos/pci_mem/include/MCF5475_SEC.h
|
||||
tos/pci_mem/include/MCF5475_SIU.h
|
||||
tos/pci_mem/include/MCF5475_SLT.h
|
||||
tos/pci_mem/include/MCF5475_SRAM.h
|
||||
tos/pci_mem/include/MCF5475_USB.h
|
||||
tos/pci_mem/include/MCF5475_XLB.h
|
||||
tos/pci_mem/include/pci.h
|
||||
tos/pci_mem/include/util.h
|
||||
tos/pci_mem/m5475/mshort/pci_mem.prg
|
||||
tos/pci_mem/m5475/pci_mem.prg
|
||||
tos/pci_mem/sources/pci_mem.c
|
||||
tos/pci_mem/depend
|
||||
tos/pci_mem/mapfile
|
||||
tos/pci_test/include/bas_string.h
|
||||
tos/pci_test/include/bas_types.h
|
||||
tos/pci_test/include/driver_vec.h
|
||||
tos/pci_test/include/MCF5475.h
|
||||
tos/pci_test/include/MCF5475_CLOCK.h
|
||||
tos/pci_test/include/MCF5475_CTM.h
|
||||
tos/pci_test/include/MCF5475_DMA.h
|
||||
tos/pci_test/include/MCF5475_DSPI.h
|
||||
tos/pci_test/include/MCF5475_EPORT.h
|
||||
tos/pci_test/include/MCF5475_FBCS.h
|
||||
tos/pci_test/include/MCF5475_FEC.h
|
||||
tos/pci_test/include/MCF5475_GPIO.h
|
||||
tos/pci_test/include/MCF5475_GPT.h
|
||||
tos/pci_test/include/MCF5475_I2C.h
|
||||
tos/pci_test/include/MCF5475_INTC.h
|
||||
tos/pci_test/include/MCF5475_MMU.h
|
||||
tos/pci_test/include/MCF5475_PAD.h
|
||||
tos/pci_test/include/MCF5475_PCI.h
|
||||
tos/pci_test/include/MCF5475_PCIARB.h
|
||||
tos/pci_test/include/MCF5475_PSC.h
|
||||
tos/pci_test/include/MCF5475_SDRAMC.h
|
||||
tos/pci_test/include/MCF5475_SEC.h
|
||||
tos/pci_test/include/MCF5475_SIU.h
|
||||
tos/pci_test/include/MCF5475_SLT.h
|
||||
tos/pci_test/include/MCF5475_SRAM.h
|
||||
tos/pci_test/include/MCF5475_USB.h
|
||||
tos/pci_test/include/MCF5475_XLB.h
|
||||
tos/pci_test/include/pci.h
|
||||
tos/pci_test/include/util.h
|
||||
tos/pci_test/m5475/mshort/pci_test.prg
|
||||
tos/pci_test/m5475/pci_test.prg
|
||||
tos/pci_test/sources/pci_test.c
|
||||
tos/pci_test/sources/printf_helper.S
|
||||
tos/pci_test/depend
|
||||
tos/pci_test/mapfile
|
||||
tos/vmem_test/include/bas_printf.h
|
||||
tos/vmem_test/include/bas_string.h
|
||||
tos/vmem_test/include/driver_vec.h
|
||||
tos/vmem_test/include/MCF5475.h
|
||||
tos/vmem_test/include/MCF5475_CLOCK.h
|
||||
tos/vmem_test/include/MCF5475_CTM.h
|
||||
tos/vmem_test/include/MCF5475_DMA.h
|
||||
tos/vmem_test/include/MCF5475_DSPI.h
|
||||
tos/vmem_test/include/MCF5475_EPORT.h
|
||||
tos/vmem_test/include/MCF5475_FBCS.h
|
||||
tos/vmem_test/include/MCF5475_FEC.h
|
||||
tos/vmem_test/include/MCF5475_GPIO.h
|
||||
tos/vmem_test/include/MCF5475_GPT.h
|
||||
tos/vmem_test/include/MCF5475_I2C.h
|
||||
tos/vmem_test/include/MCF5475_INTC.h
|
||||
tos/vmem_test/include/MCF5475_MMU.h
|
||||
tos/vmem_test/include/MCF5475_PAD.h
|
||||
tos/vmem_test/include/MCF5475_PCI.h
|
||||
tos/vmem_test/include/MCF5475_PCIARB.h
|
||||
tos/vmem_test/include/MCF5475_PSC.h
|
||||
tos/vmem_test/include/MCF5475_SDRAMC.h
|
||||
tos/vmem_test/include/MCF5475_SEC.h
|
||||
tos/vmem_test/include/MCF5475_SIU.h
|
||||
tos/vmem_test/include/MCF5475_SLT.h
|
||||
tos/vmem_test/include/MCF5475_SRAM.h
|
||||
tos/vmem_test/include/MCF5475_USB.h
|
||||
tos/vmem_test/include/MCF5475_XLB.h
|
||||
tos/vmem_test/m5475/mshort/vmem_test.prg
|
||||
tos/vmem_test/m5475/vmem_test.prg
|
||||
tos/vmem_test/sources/bas_printf.c
|
||||
tos/vmem_test/sources/bas_string.c
|
||||
tos/vmem_test/sources/printf_helper.S
|
||||
tos/vmem_test/sources/vmem_test.c
|
||||
tos/vmem_test/depend
|
||||
tos/vmem_test/mapfile
|
||||
usb/usb.c
|
||||
usb/usb_hub.c
|
||||
usb/usb_kbd.c
|
||||
usb/usb_mouse.c
|
||||
util/bas_printf.c
|
||||
util/bas_string.c
|
||||
util/conout.c
|
||||
util/libgcc_helper.S
|
||||
util/setjmp.S
|
||||
util/wait.c
|
||||
video/fbmem.c
|
||||
video/fbmodedb.c
|
||||
video/fbmon.c
|
||||
video/fnt_st_8x16.c
|
||||
video/offscreen.c
|
||||
video/vdi_fill.c
|
||||
video/videl.c
|
||||
video/video.c
|
||||
x86emu/x86biosemu.c
|
||||
x86emu/x86emu.c
|
||||
x86emu/x86emu_util.c
|
||||
x86emu/x86pcibios.c
|
||||
xhdi/xhdi_interface.c
|
||||
xhdi/xhdi_sd.c
|
||||
xhdi/xhdi_vec.S
|
||||
bas.lk.in
|
||||
bas_firebee.bdm
|
||||
bas_m5484.bdm
|
||||
basflash.lk.in
|
||||
check.bdm
|
||||
COPYING
|
||||
COPYING.LESSER
|
||||
Doxyfile
|
||||
dump.bdm
|
||||
mcf5474.gdb
|
||||
memory_map.txt
|
||||
@@ -1,5 +0,0 @@
|
||||
include
|
||||
tos/jtagwait/include
|
||||
tos/pci_mem/include
|
||||
tos/pci_test/include
|
||||
tos/vmem_test/include
|
||||
674
BaS_gcc/COPYING
674
BaS_gcc/COPYING
@@ -1,674 +0,0 @@
|
||||
GNU GENERAL PUBLIC LICENSE
|
||||
Version 3, 29 June 2007
|
||||
|
||||
Copyright (C) 2007 Free Software Foundation, Inc. <http://fsf.org/>
|
||||
Everyone is permitted to copy and distribute verbatim copies
|
||||
of this license document, but changing it is not allowed.
|
||||
|
||||
Preamble
|
||||
|
||||
The GNU General Public License is a free, copyleft license for
|
||||
software and other kinds of works.
|
||||
|
||||
The licenses for most software and other practical works are designed
|
||||
to take away your freedom to share and change the works. By contrast,
|
||||
the GNU General Public License is intended to guarantee your freedom to
|
||||
share and change all versions of a program--to make sure it remains free
|
||||
software for all its users. We, the Free Software Foundation, use the
|
||||
GNU General Public License for most of our software; it applies also to
|
||||
any other work released this way by its authors. You can apply it to
|
||||
your programs, too.
|
||||
|
||||
When we speak of free software, we are referring to freedom, not
|
||||
price. Our General Public Licenses are designed to make sure that you
|
||||
have the freedom to distribute copies of free software (and charge for
|
||||
them if you wish), that you receive source code or can get it if you
|
||||
want it, that you can change the software or use pieces of it in new
|
||||
free programs, and that you know you can do these things.
|
||||
|
||||
To protect your rights, we need to prevent others from denying you
|
||||
these rights or asking you to surrender the rights. Therefore, you have
|
||||
certain responsibilities if you distribute copies of the software, or if
|
||||
you modify it: responsibilities to respect the freedom of others.
|
||||
|
||||
For example, if you distribute copies of such a program, whether
|
||||
gratis or for a fee, you must pass on to the recipients the same
|
||||
freedoms that you received. You must make sure that they, too, receive
|
||||
or can get the source code. And you must show them these terms so they
|
||||
know their rights.
|
||||
|
||||
Developers that use the GNU GPL protect your rights with two steps:
|
||||
(1) assert copyright on the software, and (2) offer you this License
|
||||
giving you legal permission to copy, distribute and/or modify it.
|
||||
|
||||
For the developers' and authors' protection, the GPL clearly explains
|
||||
that there is no warranty for this free software. For both users' and
|
||||
authors' sake, the GPL requires that modified versions be marked as
|
||||
changed, so that their problems will not be attributed erroneously to
|
||||
authors of previous versions.
|
||||
|
||||
Some devices are designed to deny users access to install or run
|
||||
modified versions of the software inside them, although the manufacturer
|
||||
can do so. This is fundamentally incompatible with the aim of
|
||||
protecting users' freedom to change the software. The systematic
|
||||
pattern of such abuse occurs in the area of products for individuals to
|
||||
use, which is precisely where it is most unacceptable. Therefore, we
|
||||
have designed this version of the GPL to prohibit the practice for those
|
||||
products. If such problems arise substantially in other domains, we
|
||||
stand ready to extend this provision to those domains in future versions
|
||||
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|
||||
|
||||
Finally, every program is threatened constantly by software patents.
|
||||
States should not allow patents to restrict development and use of
|
||||
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|
||||
avoid the special danger that patents applied to a free program could
|
||||
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|
||||
patents cannot be used to render the program non-free.
|
||||
|
||||
The precise terms and conditions for copying, distribution and
|
||||
modification follow.
|
||||
|
||||
TERMS AND CONDITIONS
|
||||
|
||||
0. Definitions.
|
||||
|
||||
"This License" refers to version 3 of the GNU General Public License.
|
||||
|
||||
"Copyright" also means copyright-like laws that apply to other kinds of
|
||||
works, such as semiconductor masks.
|
||||
|
||||
"The Program" refers to any copyrightable work licensed under this
|
||||
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|
||||
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|
||||
|
||||
To "modify" a work means to copy from or adapt all or part of the work
|
||||
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|
||||
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|
||||
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|
||||
|
||||
A "covered work" means either the unmodified Program or a work based
|
||||
on the Program.
|
||||
|
||||
To "propagate" a work means to do anything with it that, without
|
||||
permission, would make you directly or secondarily liable for
|
||||
infringement under applicable copyright law, except executing it on a
|
||||
computer or modifying a private copy. Propagation includes copying,
|
||||
distribution (with or without modification), making available to the
|
||||
public, and in some countries other activities as well.
|
||||
|
||||
To "convey" a work means any kind of propagation that enables other
|
||||
parties to make or receive copies. Mere interaction with a user through
|
||||
a computer network, with no transfer of a copy, is not conveying.
|
||||
|
||||
An interactive user interface displays "Appropriate Legal Notices"
|
||||
to the extent that it includes a convenient and prominently visible
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
the interface presents a list of user commands or options, such as a
|
||||
menu, a prominent item in the list meets this criterion.
|
||||
|
||||
1. Source Code.
|
||||
|
||||
The "source code" for a work means the preferred form of the work
|
||||
for making modifications to it. "Object code" means any non-source
|
||||
form of a work.
|
||||
|
||||
A "Standard Interface" means an interface that either is an official
|
||||
standard defined by a recognized standards body, or, in the case of
|
||||
interfaces specified for a particular programming language, one that
|
||||
is widely used among developers working in that language.
|
||||
|
||||
The "System Libraries" of an executable work include anything, other
|
||||
than the work as a whole, that (a) is included in the normal form of
|
||||
packaging a Major Component, but which is not part of that Major
|
||||
Component, and (b) serves only to enable use of the work with that
|
||||
Major Component, or to implement a Standard Interface for which an
|
||||
implementation is available to the public in source code form. A
|
||||
"Major Component", in this context, means a major essential component
|
||||
(kernel, window system, and so on) of the specific operating system
|
||||
(if any) on which the executable work runs, or a compiler used to
|
||||
produce the work, or an object code interpreter used to run it.
|
||||
|
||||
The "Corresponding Source" for a work in object code form means all
|
||||
the source code needed to generate, install, and (for an executable
|
||||
work) run the object code and to modify the work, including scripts to
|
||||
control those activities. However, it does not include the work's
|
||||
System Libraries, or general-purpose tools or generally available free
|
||||
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|
||||
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|
||||
includes interface definition files associated with source files for
|
||||
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|
||||
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|
||||
such as by intimate data communication or control flow between those
|
||||
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|
||||
|
||||
The Corresponding Source need not include anything that users
|
||||
can regenerate automatically from other parts of the Corresponding
|
||||
Source.
|
||||
|
||||
The Corresponding Source for a work in source code form is that
|
||||
same work.
|
||||
|
||||
2. Basic Permissions.
|
||||
|
||||
All rights granted under this License are granted for the term of
|
||||
copyright on the Program, and are irrevocable provided the stated
|
||||
conditions are met. This License explicitly affirms your unlimited
|
||||
permission to run the unmodified Program. The output from running a
|
||||
covered work is covered by this License only if the output, given its
|
||||
content, constitutes a covered work. This License acknowledges your
|
||||
rights of fair use or other equivalent, as provided by copyright law.
|
||||
|
||||
You may make, run and propagate covered works that you do not
|
||||
convey, without conditions so long as your license otherwise remains
|
||||
in force. You may convey covered works to others for the sole purpose
|
||||
of having them make modifications exclusively for you, or provide you
|
||||
with facilities for running those works, provided that you comply with
|
||||
the terms of this License in conveying all material for which you do
|
||||
not control copyright. Those thus making or running the covered works
|
||||
for you must do so exclusively on your behalf, under your direction
|
||||
and control, on terms that prohibit them from making any copies of
|
||||
your copyrighted material outside their relationship with you.
|
||||
|
||||
Conveying under any other circumstances is permitted solely under
|
||||
the conditions stated below. Sublicensing is not allowed; section 10
|
||||
makes it unnecessary.
|
||||
|
||||
3. Protecting Users' Legal Rights From Anti-Circumvention Law.
|
||||
|
||||
No covered work shall be deemed part of an effective technological
|
||||
measure under any applicable law fulfilling obligations under article
|
||||
11 of the WIPO copyright treaty adopted on 20 December 1996, or
|
||||
similar laws prohibiting or restricting circumvention of such
|
||||
measures.
|
||||
|
||||
When you convey a covered work, you waive any legal power to forbid
|
||||
circumvention of technological measures to the extent such circumvention
|
||||
is effected by exercising rights under this License with respect to
|
||||
the covered work, and you disclaim any intention to limit operation or
|
||||
modification of the work as a means of enforcing, against the work's
|
||||
users, your or third parties' legal rights to forbid circumvention of
|
||||
technological measures.
|
||||
|
||||
4. Conveying Verbatim Copies.
|
||||
|
||||
You may convey verbatim copies of the Program's source code as you
|
||||
receive it, in any medium, provided that you conspicuously and
|
||||
appropriately publish on each copy an appropriate copyright notice;
|
||||
keep intact all notices stating that this License and any
|
||||
non-permissive terms added in accord with section 7 apply to the code;
|
||||
keep intact all notices of the absence of any warranty; and give all
|
||||
recipients a copy of this License along with the Program.
|
||||
|
||||
You may charge any price or no price for each copy that you convey,
|
||||
and you may offer support or warranty protection for a fee.
|
||||
|
||||
5. Conveying Modified Source Versions.
|
||||
|
||||
You may convey a work based on the Program, or the modifications to
|
||||
produce it from the Program, in the form of source code under the
|
||||
terms of section 4, provided that you also meet all of these conditions:
|
||||
|
||||
a) The work must carry prominent notices stating that you modified
|
||||
it, and giving a relevant date.
|
||||
|
||||
b) The work must carry prominent notices stating that it is
|
||||
released under this License and any conditions added under section
|
||||
7. This requirement modifies the requirement in section 4 to
|
||||
"keep intact all notices".
|
||||
|
||||
c) You must license the entire work, as a whole, under this
|
||||
License to anyone who comes into possession of a copy. This
|
||||
License will therefore apply, along with any applicable section 7
|
||||
additional terms, to the whole of the work, and all its parts,
|
||||
regardless of how they are packaged. This License gives no
|
||||
permission to license the work in any other way, but it does not
|
||||
invalidate such permission if you have separately received it.
|
||||
|
||||
d) If the work has interactive user interfaces, each must display
|
||||
Appropriate Legal Notices; however, if the Program has interactive
|
||||
interfaces that do not display Appropriate Legal Notices, your
|
||||
work need not make them do so.
|
||||
|
||||
A compilation of a covered work with other separate and independent
|
||||
works, which are not by their nature extensions of the covered work,
|
||||
and which are not combined with it such as to form a larger program,
|
||||
in or on a volume of a storage or distribution medium, is called an
|
||||
"aggregate" if the compilation and its resulting copyright are not
|
||||
used to limit the access or legal rights of the compilation's users
|
||||
beyond what the individual works permit. Inclusion of a covered work
|
||||
in an aggregate does not cause this License to apply to the other
|
||||
parts of the aggregate.
|
||||
|
||||
6. Conveying Non-Source Forms.
|
||||
|
||||
You may convey a covered work in object code form under the terms
|
||||
of sections 4 and 5, provided that you also convey the
|
||||
machine-readable Corresponding Source under the terms of this License,
|
||||
in one of these ways:
|
||||
|
||||
a) Convey the object code in, or embodied in, a physical product
|
||||
(including a physical distribution medium), accompanied by the
|
||||
Corresponding Source fixed on a durable physical medium
|
||||
customarily used for software interchange.
|
||||
|
||||
b) Convey the object code in, or embodied in, a physical product
|
||||
(including a physical distribution medium), accompanied by a
|
||||
written offer, valid for at least three years and valid for as
|
||||
long as you offer spare parts or customer support for that product
|
||||
model, to give anyone who possesses the object code either (1) a
|
||||
copy of the Corresponding Source for all the software in the
|
||||
product that is covered by this License, on a durable physical
|
||||
medium customarily used for software interchange, for a price no
|
||||
more than your reasonable cost of physically performing this
|
||||
conveying of source, or (2) access to copy the
|
||||
Corresponding Source from a network server at no charge.
|
||||
|
||||
c) Convey individual copies of the object code with a copy of the
|
||||
written offer to provide the Corresponding Source. This
|
||||
alternative is allowed only occasionally and noncommercially, and
|
||||
only if you received the object code with such an offer, in accord
|
||||
with subsection 6b.
|
||||
|
||||
d) Convey the object code by offering access from a designated
|
||||
place (gratis or for a charge), and offer equivalent access to the
|
||||
Corresponding Source in the same way through the same place at no
|
||||
further charge. You need not require recipients to copy the
|
||||
Corresponding Source along with the object code. If the place to
|
||||
copy the object code is a network server, the Corresponding Source
|
||||
may be on a different server (operated by you or a third party)
|
||||
that supports equivalent copying facilities, provided you maintain
|
||||
clear directions next to the object code saying where to find the
|
||||
Corresponding Source. Regardless of what server hosts the
|
||||
Corresponding Source, you remain obligated to ensure that it is
|
||||
available for as long as needed to satisfy these requirements.
|
||||
|
||||
e) Convey the object code using peer-to-peer transmission, provided
|
||||
you inform other peers where the object code and Corresponding
|
||||
Source of the work are being offered to the general public at no
|
||||
charge under subsection 6d.
|
||||
|
||||
A separable portion of the object code, whose source code is excluded
|
||||
from the Corresponding Source as a System Library, need not be
|
||||
included in conveying the object code work.
|
||||
|
||||
A "User Product" is either (1) a "consumer product", which means any
|
||||
tangible personal property which is normally used for personal, family,
|
||||
or household purposes, or (2) anything designed or sold for incorporation
|
||||
into a dwelling. In determining whether a product is a consumer product,
|
||||
doubtful cases shall be resolved in favor of coverage. For a particular
|
||||
product received by a particular user, "normally used" refers to a
|
||||
typical or common use of that class of product, regardless of the status
|
||||
of the particular user or of the way in which the particular user
|
||||
actually uses, or expects or is expected to use, the product. A product
|
||||
is a consumer product regardless of whether the product has substantial
|
||||
commercial, industrial or non-consumer uses, unless such uses represent
|
||||
the only significant mode of use of the product.
|
||||
|
||||
"Installation Information" for a User Product means any methods,
|
||||
procedures, authorization keys, or other information required to install
|
||||
and execute modified versions of a covered work in that User Product from
|
||||
a modified version of its Corresponding Source. The information must
|
||||
suffice to ensure that the continued functioning of the modified object
|
||||
code is in no case prevented or interfered with solely because
|
||||
modification has been made.
|
||||
|
||||
If you convey an object code work under this section in, or with, or
|
||||
specifically for use in, a User Product, and the conveying occurs as
|
||||
part of a transaction in which the right of possession and use of the
|
||||
User Product is transferred to the recipient in perpetuity or for a
|
||||
fixed term (regardless of how the transaction is characterized), the
|
||||
Corresponding Source conveyed under this section must be accompanied
|
||||
by the Installation Information. But this requirement does not apply
|
||||
if neither you nor any third party retains the ability to install
|
||||
modified object code on the User Product (for example, the work has
|
||||
been installed in ROM).
|
||||
|
||||
The requirement to provide Installation Information does not include a
|
||||
requirement to continue to provide support service, warranty, or updates
|
||||
for a work that has been modified or installed by the recipient, or for
|
||||
the User Product in which it has been modified or installed. Access to a
|
||||
network may be denied when the modification itself materially and
|
||||
adversely affects the operation of the network or violates the rules and
|
||||
protocols for communication across the network.
|
||||
|
||||
Corresponding Source conveyed, and Installation Information provided,
|
||||
in accord with this section must be in a format that is publicly
|
||||
documented (and with an implementation available to the public in
|
||||
source code form), and must require no special password or key for
|
||||
unpacking, reading or copying.
|
||||
|
||||
7. Additional Terms.
|
||||
|
||||
"Additional permissions" are terms that supplement the terms of this
|
||||
License by making exceptions from one or more of its conditions.
|
||||
Additional permissions that are applicable to the entire Program shall
|
||||
be treated as though they were included in this License, to the extent
|
||||
that they are valid under applicable law. If additional permissions
|
||||
apply only to part of the Program, that part may be used separately
|
||||
under those permissions, but the entire Program remains governed by
|
||||
this License without regard to the additional permissions.
|
||||
|
||||
When you convey a copy of a covered work, you may at your option
|
||||
remove any additional permissions from that copy, or from any part of
|
||||
it. (Additional permissions may be written to require their own
|
||||
removal in certain cases when you modify the work.) You may place
|
||||
additional permissions on material, added by you to a covered work,
|
||||
for which you have or can give appropriate copyright permission.
|
||||
|
||||
Notwithstanding any other provision of this License, for material you
|
||||
add to a covered work, you may (if authorized by the copyright holders of
|
||||
that material) supplement the terms of this License with terms:
|
||||
|
||||
a) Disclaiming warranty or limiting liability differently from the
|
||||
terms of sections 15 and 16 of this License; or
|
||||
|
||||
b) Requiring preservation of specified reasonable legal notices or
|
||||
author attributions in that material or in the Appropriate Legal
|
||||
Notices displayed by works containing it; or
|
||||
|
||||
c) Prohibiting misrepresentation of the origin of that material, or
|
||||
requiring that modified versions of such material be marked in
|
||||
reasonable ways as different from the original version; or
|
||||
|
||||
d) Limiting the use for publicity purposes of names of licensors or
|
||||
authors of the material; or
|
||||
|
||||
e) Declining to grant rights under trademark law for use of some
|
||||
trade names, trademarks, or service marks; or
|
||||
|
||||
f) Requiring indemnification of licensors and authors of that
|
||||
material by anyone who conveys the material (or modified versions of
|
||||
it) with contractual assumptions of liability to the recipient, for
|
||||
any liability that these contractual assumptions directly impose on
|
||||
those licensors and authors.
|
||||
|
||||
All other non-permissive additional terms are considered "further
|
||||
restrictions" within the meaning of section 10. If the Program as you
|
||||
received it, or any part of it, contains a notice stating that it is
|
||||
governed by this License along with a term that is a further
|
||||
restriction, you may remove that term. If a license document contains
|
||||
a further restriction but permits relicensing or conveying under this
|
||||
License, you may add to a covered work material governed by the terms
|
||||
of that license document, provided that the further restriction does
|
||||
not survive such relicensing or conveying.
|
||||
|
||||
If you add terms to a covered work in accord with this section, you
|
||||
must place, in the relevant source files, a statement of the
|
||||
additional terms that apply to those files, or a notice indicating
|
||||
where to find the applicable terms.
|
||||
|
||||
Additional terms, permissive or non-permissive, may be stated in the
|
||||
form of a separately written license, or stated as exceptions;
|
||||
the above requirements apply either way.
|
||||
|
||||
8. Termination.
|
||||
|
||||
You may not propagate or modify a covered work except as expressly
|
||||
provided under this License. Any attempt otherwise to propagate or
|
||||
modify it is void, and will automatically terminate your rights under
|
||||
this License (including any patent licenses granted under the third
|
||||
paragraph of section 11).
|
||||
|
||||
However, if you cease all violation of this License, then your
|
||||
license from a particular copyright holder is reinstated (a)
|
||||
provisionally, unless and until the copyright holder explicitly and
|
||||
finally terminates your license, and (b) permanently, if the copyright
|
||||
holder fails to notify you of the violation by some reasonable means
|
||||
prior to 60 days after the cessation.
|
||||
|
||||
Moreover, your license from a particular copyright holder is
|
||||
reinstated permanently if the copyright holder notifies you of the
|
||||
violation by some reasonable means, this is the first time you have
|
||||
received notice of violation of this License (for any work) from that
|
||||
copyright holder, and you cure the violation prior to 30 days after
|
||||
your receipt of the notice.
|
||||
|
||||
Termination of your rights under this section does not terminate the
|
||||
licenses of parties who have received copies or rights from you under
|
||||
this License. If your rights have been terminated and not permanently
|
||||
reinstated, you do not qualify to receive new licenses for the same
|
||||
material under section 10.
|
||||
|
||||
9. Acceptance Not Required for Having Copies.
|
||||
|
||||
You are not required to accept this License in order to receive or
|
||||
run a copy of the Program. Ancillary propagation of a covered work
|
||||
occurring solely as a consequence of using peer-to-peer transmission
|
||||
to receive a copy likewise does not require acceptance. However,
|
||||
nothing other than this License grants you permission to propagate or
|
||||
modify any covered work. These actions infringe copyright if you do
|
||||
not accept this License. Therefore, by modifying or propagating a
|
||||
covered work, you indicate your acceptance of this License to do so.
|
||||
|
||||
10. Automatic Licensing of Downstream Recipients.
|
||||
|
||||
Each time you convey a covered work, the recipient automatically
|
||||
receives a license from the original licensors, to run, modify and
|
||||
propagate that work, subject to this License. You are not responsible
|
||||
for enforcing compliance by third parties with this License.
|
||||
|
||||
An "entity transaction" is a transaction transferring control of an
|
||||
organization, or substantially all assets of one, or subdividing an
|
||||
organization, or merging organizations. If propagation of a covered
|
||||
work results from an entity transaction, each party to that
|
||||
transaction who receives a copy of the work also receives whatever
|
||||
licenses to the work the party's predecessor in interest had or could
|
||||
give under the previous paragraph, plus a right to possession of the
|
||||
Corresponding Source of the work from the predecessor in interest, if
|
||||
the predecessor has it or can get it with reasonable efforts.
|
||||
|
||||
You may not impose any further restrictions on the exercise of the
|
||||
rights granted or affirmed under this License. For example, you may
|
||||
not impose a license fee, royalty, or other charge for exercise of
|
||||
rights granted under this License, and you may not initiate litigation
|
||||
(including a cross-claim or counterclaim in a lawsuit) alleging that
|
||||
any patent claim is infringed by making, using, selling, offering for
|
||||
sale, or importing the Program or any portion of it.
|
||||
|
||||
11. Patents.
|
||||
|
||||
A "contributor" is a copyright holder who authorizes use under this
|
||||
License of the Program or a work on which the Program is based. The
|
||||
work thus licensed is called the contributor's "contributor version".
|
||||
|
||||
A contributor's "essential patent claims" are all patent claims
|
||||
owned or controlled by the contributor, whether already acquired or
|
||||
hereafter acquired, that would be infringed by some manner, permitted
|
||||
by this License, of making, using, or selling its contributor version,
|
||||
but do not include claims that would be infringed only as a
|
||||
consequence of further modification of the contributor version. For
|
||||
purposes of this definition, "control" includes the right to grant
|
||||
patent sublicenses in a manner consistent with the requirements of
|
||||
this License.
|
||||
|
||||
Each contributor grants you a non-exclusive, worldwide, royalty-free
|
||||
patent license under the contributor's essential patent claims, to
|
||||
make, use, sell, offer for sale, import and otherwise run, modify and
|
||||
propagate the contents of its contributor version.
|
||||
|
||||
In the following three paragraphs, a "patent license" is any express
|
||||
agreement or commitment, however denominated, not to enforce a patent
|
||||
(such as an express permission to practice a patent or covenant not to
|
||||
sue for patent infringement). To "grant" such a patent license to a
|
||||
party means to make such an agreement or commitment not to enforce a
|
||||
patent against the party.
|
||||
|
||||
If you convey a covered work, knowingly relying on a patent license,
|
||||
and the Corresponding Source of the work is not available for anyone
|
||||
to copy, free of charge and under the terms of this License, through a
|
||||
publicly available network server or other readily accessible means,
|
||||
then you must either (1) cause the Corresponding Source to be so
|
||||
available, or (2) arrange to deprive yourself of the benefit of the
|
||||
patent license for this particular work, or (3) arrange, in a manner
|
||||
consistent with the requirements of this License, to extend the patent
|
||||
license to downstream recipients. "Knowingly relying" means you have
|
||||
actual knowledge that, but for the patent license, your conveying the
|
||||
covered work in a country, or your recipient's use of the covered work
|
||||
in a country, would infringe one or more identifiable patents in that
|
||||
country that you have reason to believe are valid.
|
||||
|
||||
If, pursuant to or in connection with a single transaction or
|
||||
arrangement, you convey, or propagate by procuring conveyance of, a
|
||||
covered work, and grant a patent license to some of the parties
|
||||
receiving the covered work authorizing them to use, propagate, modify
|
||||
or convey a specific copy of the covered work, then the patent license
|
||||
you grant is automatically extended to all recipients of the covered
|
||||
work and works based on it.
|
||||
|
||||
A patent license is "discriminatory" if it does not include within
|
||||
the scope of its coverage, prohibits the exercise of, or is
|
||||
conditioned on the non-exercise of one or more of the rights that are
|
||||
specifically granted under this License. You may not convey a covered
|
||||
work if you are a party to an arrangement with a third party that is
|
||||
in the business of distributing software, under which you make payment
|
||||
to the third party based on the extent of your activity of conveying
|
||||
the work, and under which the third party grants, to any of the
|
||||
parties who would receive the covered work from you, a discriminatory
|
||||
patent license (a) in connection with copies of the covered work
|
||||
conveyed by you (or copies made from those copies), or (b) primarily
|
||||
for and in connection with specific products or compilations that
|
||||
contain the covered work, unless you entered into that arrangement,
|
||||
or that patent license was granted, prior to 28 March 2007.
|
||||
|
||||
Nothing in this License shall be construed as excluding or limiting
|
||||
any implied license or other defenses to infringement that may
|
||||
otherwise be available to you under applicable patent law.
|
||||
|
||||
12. No Surrender of Others' Freedom.
|
||||
|
||||
If conditions are imposed on you (whether by court order, agreement or
|
||||
otherwise) that contradict the conditions of this License, they do not
|
||||
excuse you from the conditions of this License. If you cannot convey a
|
||||
covered work so as to satisfy simultaneously your obligations under this
|
||||
License and any other pertinent obligations, then as a consequence you may
|
||||
not convey it at all. For example, if you agree to terms that obligate you
|
||||
to collect a royalty for further conveying from those to whom you convey
|
||||
the Program, the only way you could satisfy both those terms and this
|
||||
License would be to refrain entirely from conveying the Program.
|
||||
|
||||
13. Use with the GNU Affero General Public License.
|
||||
|
||||
Notwithstanding any other provision of this License, you have
|
||||
permission to link or combine any covered work with a work licensed
|
||||
under version 3 of the GNU Affero General Public License into a single
|
||||
combined work, and to convey the resulting work. The terms of this
|
||||
License will continue to apply to the part which is the covered work,
|
||||
but the special requirements of the GNU Affero General Public License,
|
||||
section 13, concerning interaction through a network will apply to the
|
||||
combination as such.
|
||||
|
||||
14. Revised Versions of this License.
|
||||
|
||||
The Free Software Foundation may publish revised and/or new versions of
|
||||
the GNU General Public License from time to time. Such new versions will
|
||||
be similar in spirit to the present version, but may differ in detail to
|
||||
address new problems or concerns.
|
||||
|
||||
Each version is given a distinguishing version number. If the
|
||||
Program specifies that a certain numbered version of the GNU General
|
||||
Public License "or any later version" applies to it, you have the
|
||||
option of following the terms and conditions either of that numbered
|
||||
version or of any later version published by the Free Software
|
||||
Foundation. If the Program does not specify a version number of the
|
||||
GNU General Public License, you may choose any version ever published
|
||||
by the Free Software Foundation.
|
||||
|
||||
If the Program specifies that a proxy can decide which future
|
||||
versions of the GNU General Public License can be used, that proxy's
|
||||
public statement of acceptance of a version permanently authorizes you
|
||||
to choose that version for the Program.
|
||||
|
||||
Later license versions may give you additional or different
|
||||
permissions. However, no additional obligations are imposed on any
|
||||
author or copyright holder as a result of your choosing to follow a
|
||||
later version.
|
||||
|
||||
15. Disclaimer of Warranty.
|
||||
|
||||
THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY
|
||||
APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT
|
||||
HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY
|
||||
OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO,
|
||||
THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
|
||||
PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM
|
||||
IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF
|
||||
ALL NECESSARY SERVICING, REPAIR OR CORRECTION.
|
||||
|
||||
16. Limitation of Liability.
|
||||
|
||||
IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING
|
||||
WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MODIFIES AND/OR CONVEYS
|
||||
THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY
|
||||
GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE
|
||||
USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF
|
||||
DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD
|
||||
PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS),
|
||||
EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF
|
||||
SUCH DAMAGES.
|
||||
|
||||
17. Interpretation of Sections 15 and 16.
|
||||
|
||||
If the disclaimer of warranty and limitation of liability provided
|
||||
above cannot be given local legal effect according to their terms,
|
||||
reviewing courts shall apply local law that most closely approximates
|
||||
an absolute waiver of all civil liability in connection with the
|
||||
Program, unless a warranty or assumption of liability accompanies a
|
||||
copy of the Program in return for a fee.
|
||||
|
||||
END OF TERMS AND CONDITIONS
|
||||
|
||||
How to Apply These Terms to Your New Programs
|
||||
|
||||
If you develop a new program, and you want it to be of the greatest
|
||||
possible use to the public, the best way to achieve this is to make it
|
||||
free software which everyone can redistribute and change under these terms.
|
||||
|
||||
To do so, attach the following notices to the program. It is safest
|
||||
to attach them to the start of each source file to most effectively
|
||||
state the exclusion of warranty; and each file should have at least
|
||||
the "copyright" line and a pointer to where the full notice is found.
|
||||
|
||||
<one line to give the program's name and a brief idea of what it does.>
|
||||
Copyright (C) <year> <name of author>
|
||||
|
||||
This program is free software: you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation, either version 3 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
|
||||
Also add information on how to contact you by electronic and paper mail.
|
||||
|
||||
If the program does terminal interaction, make it output a short
|
||||
notice like this when it starts in an interactive mode:
|
||||
|
||||
<program> Copyright (C) <year> <name of author>
|
||||
This program comes with ABSOLUTELY NO WARRANTY; for details type `show w'.
|
||||
This is free software, and you are welcome to redistribute it
|
||||
under certain conditions; type `show c' for details.
|
||||
|
||||
The hypothetical commands `show w' and `show c' should show the appropriate
|
||||
parts of the General Public License. Of course, your program's commands
|
||||
might be different; for a GUI interface, you would use an "about box".
|
||||
|
||||
You should also get your employer (if you work as a programmer) or school,
|
||||
if any, to sign a "copyright disclaimer" for the program, if necessary.
|
||||
For more information on this, and how to apply and follow the GNU GPL, see
|
||||
<http://www.gnu.org/licenses/>.
|
||||
|
||||
The GNU General Public License does not permit incorporating your program
|
||||
into proprietary programs. If your program is a subroutine library, you
|
||||
may consider it more useful to permit linking proprietary applications with
|
||||
the library. If this is what you want to do, use the GNU Lesser General
|
||||
Public License instead of this License. But first, please read
|
||||
<http://www.gnu.org/philosophy/why-not-lgpl.html>.
|
||||
@@ -1,330 +0,0 @@
|
||||
GNU LESSER GENERAL PUBLIC LICENSE
|
||||
Version 3, 29 June 2007
|
||||
|
||||
Copyright (C) 2007 Free Software Foundation, Inc. <http://fsf.org/>
|
||||
Everyone is permitted to copy and distribute verbatim copies
|
||||
of this license document, but changing it is not allowed.
|
||||
|
||||
|
||||
This version of the GNU Lesser General Public License incorporates
|
||||
the terms and conditions of version 3 of the GNU General Public
|
||||
License, supplemented by the additional permissions listed below.
|
||||
|
||||
0. Additional Definitions.
|
||||
|
||||
As used herein, "this License" refers to version 3 of the GNU Lesser
|
||||
General Public License, and the "GNU GPL" refers to version 3 of the GNU
|
||||
General Public License.
|
||||
|
||||
"The Library" refers to a covered work governed by this License,
|
||||
other than an Application or a Combined Work as defined below.
|
||||
|
||||
An "Application" is any work that makes use of an interface provided
|
||||
by the Library, but which is not otherwise based on the Library.
|
||||
Defining a subclass of a class defined by the Library is deemed a mode
|
||||
of using an interface provided by the Library.
|
||||
|
||||
A "Combined Work" is a work produced by combining or linking an
|
||||
Application with the Library. The particular version of the Library
|
||||
with which the Combined Work was made is also called the "Linked
|
||||
Version".
|
||||
|
||||
The "Minimal Corresponding Source" for a Combined Work means the
|
||||
Corresponding Source for the Combined Work, excluding any source code
|
||||
for portions of the Combined Work that, considered in isolation, are
|
||||
based on the Application, and not on the Linked Version.
|
||||
|
||||
The "Corresponding Application Code" for a Combined Work means the
|
||||
object code and/or source code for the Application, including any data
|
||||
and utility programs needed for reproducing the Combined Work from the
|
||||
Application, but excluding the System Libraries of the Combined Work.
|
||||
|
||||
1. Exception to Section 3 of the GNU GPL.
|
||||
|
||||
You may convey a covered work under sections 3 and 4 of this License
|
||||
without being bound by section 3 of the GNU GPL.
|
||||
|
||||
2. Conveying Modified Versions.
|
||||
|
||||
If you modify a copy of the Library, and, in your modifications, a
|
||||
facility refers to a function or data to be supplied by an Application
|
||||
that uses the facility (other than as an argument passed when the
|
||||
facility is invoked), then you may convey a copy of the modified
|
||||
version:
|
||||
|
||||
a) under this License, provided that you make a good faith effort to
|
||||
ensure that, in the event an Application does not supply the
|
||||
function or data, the facility still operates, and performs
|
||||
whatever part of its purpose remains meaningful, or
|
||||
|
||||
b) under the GNU GPL, with none of the additional permissions of
|
||||
this License applicable to that copy.
|
||||
|
||||
3. Object Code Incorporating Material from Library Header Files.
|
||||
|
||||
The object code form of an Application may incorporate material from
|
||||
a header file that is part of the Library. You may convey such object
|
||||
code under terms of your choice, provided that, if the incorporated
|
||||
material is not limited to numerical parameters, data structure
|
||||
layouts and accessors, or small macros, inline functions and templates
|
||||
(ten or fewer lines in length), you do both of the following:
|
||||
|
||||
a) Give prominent notice with each copy of the object code that the
|
||||
Library is used in it and that the Library and its use are
|
||||
covered by this License.
|
||||
|
||||
b) Accompany the object code with a copy of the GNU GPL and this license
|
||||
document.
|
||||
|
||||
4. Combined Works.
|
||||
|
||||
You may convey a Combined Work under terms of your choice that,
|
||||
taken together, effectively do not restrict modification of the
|
||||
portions of the Library contained in the Combined Work and reverse
|
||||
engineering for debugging such modifications, if you also do each of
|
||||
the following:
|
||||
|
||||
a) Give prominent notice with each copy of the Combined Work that
|
||||
the Library is used in it and that the Library and its use are
|
||||
covered by this License.
|
||||
|
||||
b) Accompany the Combined Work with a copy of the GNU GPL and this license
|
||||
document.
|
||||
|
||||
c) For a Combined Work that displays copyright notices during
|
||||
execution, include the copyright notice for the Library among
|
||||
these notices, as well as a reference directing the user to the
|
||||
copies of the GNU GPL and this license document.
|
||||
|
||||
d) Do one of the following:
|
||||
|
||||
0) Convey the Minimal Corresponding Source under the terms of this
|
||||
License, and the Corresponding Application Code in a form
|
||||
suitable for, and under terms that permit, the user to
|
||||
recombine or relink the Application with a modified version of
|
||||
the Linked Version to produce a modified Combined Work, in the
|
||||
manner specified by section 6 of the GNU GPL for conveying
|
||||
Corresponding Source.
|
||||
|
||||
1) Use a suitable shared library mechanism for linking with the
|
||||
Library. A suitable mechanism is one that (a) uses at run time
|
||||
a copy of the Library already present on the user's computer
|
||||
system, and (b) will operate properly with a modified version
|
||||
of the Library that is interface-compatible with the Linked
|
||||
Version.
|
||||
|
||||
e) Provide Installation Information, but only if you would otherwise
|
||||
be required to provide such information under section 6 of the
|
||||
GNU GPL, and only to the extent that such information is
|
||||
necessary to install and execute a modified version of the
|
||||
Combined Work produced by recombining or relinking the
|
||||
Application with a modified version of the Linked Version. (If
|
||||
you use option 4d0, the Installation Information must accompany
|
||||
the Minimal Corresponding Source and Corresponding Application
|
||||
Code. If you use option 4d1, you must provide the Installation
|
||||
Information in the manner specified by section 6 of the GNU GPL
|
||||
for conveying Corresponding Source.)
|
||||
|
||||
5. Combined Libraries.
|
||||
|
||||
You may place library facilities that are a work based on the
|
||||
Library side by side in a single library together with other library
|
||||
facilities that are not Applications and are not covered by this
|
||||
License, and convey such a combined library under terms of your
|
||||
choice, if you do both of the following:
|
||||
|
||||
a) Accompany the combined library with a copy of the same work based
|
||||
on the Library, uncombined with any other library facilities,
|
||||
conveyed under the terms of this License.
|
||||
|
||||
b) Give prominent notice with the combined library that part of it
|
||||
is a work based on the Library, and explaining where to find the
|
||||
accompanying uncombined form of the same work.
|
||||
|
||||
6. Revised Versions of the GNU Lesser General Public License.
|
||||
|
||||
The Free Software Foundation may publish revised and/or new versions
|
||||
of the GNU Lesser General Public License from time to time. Such new
|
||||
versions will be similar in spirit to the present version, but may
|
||||
differ in detail to address new problems or concerns.
|
||||
|
||||
Each version is given a distinguishing version number. If the
|
||||
Library as you received it specifies that a certain numbered version
|
||||
of the GNU Lesser General Public License "or any later version"
|
||||
applies to it, you have the option of following the terms and
|
||||
conditions either of that published version or of any later version
|
||||
published by the Free Software Foundation. If the Library as you
|
||||
received it does not specify a version number of the GNU Lesser
|
||||
General Public License, you may choose any version of the GNU Lesser
|
||||
General Public License ever published by the Free Software Foundation.
|
||||
|
||||
If the Library as you received it specifies that a proxy can decide
|
||||
whether future versions of the GNU Lesser General Public License shall
|
||||
apply, that proxy's public statement of acceptance of any version is
|
||||
permanent authorization for you to choose that version for the
|
||||
Library.
|
||||
GNU LESSER GENERAL PUBLIC LICENSE
|
||||
Version 3, 29 June 2007
|
||||
|
||||
Copyright (C) 2007 Free Software Foundation, Inc. <http://fsf.org/>
|
||||
Everyone is permitted to copy and distribute verbatim copies
|
||||
of this license document, but changing it is not allowed.
|
||||
|
||||
|
||||
This version of the GNU Lesser General Public License incorporates
|
||||
the terms and conditions of version 3 of the GNU General Public
|
||||
License, supplemented by the additional permissions listed below.
|
||||
|
||||
0. Additional Definitions.
|
||||
|
||||
As used herein, "this License" refers to version 3 of the GNU Lesser
|
||||
General Public License, and the "GNU GPL" refers to version 3 of the GNU
|
||||
General Public License.
|
||||
|
||||
"The Library" refers to a covered work governed by this License,
|
||||
other than an Application or a Combined Work as defined below.
|
||||
|
||||
An "Application" is any work that makes use of an interface provided
|
||||
by the Library, but which is not otherwise based on the Library.
|
||||
Defining a subclass of a class defined by the Library is deemed a mode
|
||||
of using an interface provided by the Library.
|
||||
|
||||
A "Combined Work" is a work produced by combining or linking an
|
||||
Application with the Library. The particular version of the Library
|
||||
with which the Combined Work was made is also called the "Linked
|
||||
Version".
|
||||
|
||||
The "Minimal Corresponding Source" for a Combined Work means the
|
||||
Corresponding Source for the Combined Work, excluding any source code
|
||||
for portions of the Combined Work that, considered in isolation, are
|
||||
based on the Application, and not on the Linked Version.
|
||||
|
||||
The "Corresponding Application Code" for a Combined Work means the
|
||||
object code and/or source code for the Application, including any data
|
||||
and utility programs needed for reproducing the Combined Work from the
|
||||
Application, but excluding the System Libraries of the Combined Work.
|
||||
|
||||
1. Exception to Section 3 of the GNU GPL.
|
||||
|
||||
You may convey a covered work under sections 3 and 4 of this License
|
||||
without being bound by section 3 of the GNU GPL.
|
||||
|
||||
2. Conveying Modified Versions.
|
||||
|
||||
If you modify a copy of the Library, and, in your modifications, a
|
||||
facility refers to a function or data to be supplied by an Application
|
||||
that uses the facility (other than as an argument passed when the
|
||||
facility is invoked), then you may convey a copy of the modified
|
||||
version:
|
||||
|
||||
a) under this License, provided that you make a good faith effort to
|
||||
ensure that, in the event an Application does not supply the
|
||||
function or data, the facility still operates, and performs
|
||||
whatever part of its purpose remains meaningful, or
|
||||
|
||||
b) under the GNU GPL, with none of the additional permissions of
|
||||
this License applicable to that copy.
|
||||
|
||||
3. Object Code Incorporating Material from Library Header Files.
|
||||
|
||||
The object code form of an Application may incorporate material from
|
||||
a header file that is part of the Library. You may convey such object
|
||||
code under terms of your choice, provided that, if the incorporated
|
||||
material is not limited to numerical parameters, data structure
|
||||
layouts and accessors, or small macros, inline functions and templates
|
||||
(ten or fewer lines in length), you do both of the following:
|
||||
|
||||
a) Give prominent notice with each copy of the object code that the
|
||||
Library is used in it and that the Library and its use are
|
||||
covered by this License.
|
||||
|
||||
b) Accompany the object code with a copy of the GNU GPL and this license
|
||||
document.
|
||||
|
||||
4. Combined Works.
|
||||
|
||||
You may convey a Combined Work under terms of your choice that,
|
||||
taken together, effectively do not restrict modification of the
|
||||
portions of the Library contained in the Combined Work and reverse
|
||||
engineering for debugging such modifications, if you also do each of
|
||||
the following:
|
||||
|
||||
a) Give prominent notice with each copy of the Combined Work that
|
||||
the Library is used in it and that the Library and its use are
|
||||
covered by this License.
|
||||
|
||||
b) Accompany the Combined Work with a copy of the GNU GPL and this license
|
||||
document.
|
||||
|
||||
c) For a Combined Work that displays copyright notices during
|
||||
execution, include the copyright notice for the Library among
|
||||
these notices, as well as a reference directing the user to the
|
||||
copies of the GNU GPL and this license document.
|
||||
|
||||
d) Do one of the following:
|
||||
|
||||
0) Convey the Minimal Corresponding Source under the terms of this
|
||||
License, and the Corresponding Application Code in a form
|
||||
suitable for, and under terms that permit, the user to
|
||||
recombine or relink the Application with a modified version of
|
||||
the Linked Version to produce a modified Combined Work, in the
|
||||
manner specified by section 6 of the GNU GPL for conveying
|
||||
Corresponding Source.
|
||||
|
||||
1) Use a suitable shared library mechanism for linking with the
|
||||
Library. A suitable mechanism is one that (a) uses at run time
|
||||
a copy of the Library already present on the user's computer
|
||||
system, and (b) will operate properly with a modified version
|
||||
of the Library that is interface-compatible with the Linked
|
||||
Version.
|
||||
|
||||
e) Provide Installation Information, but only if you would otherwise
|
||||
be required to provide such information under section 6 of the
|
||||
GNU GPL, and only to the extent that such information is
|
||||
necessary to install and execute a modified version of the
|
||||
Combined Work produced by recombining or relinking the
|
||||
Application with a modified version of the Linked Version. (If
|
||||
you use option 4d0, the Installation Information must accompany
|
||||
the Minimal Corresponding Source and Corresponding Application
|
||||
Code. If you use option 4d1, you must provide the Installation
|
||||
Information in the manner specified by section 6 of the GNU GPL
|
||||
for conveying Corresponding Source.)
|
||||
|
||||
5. Combined Libraries.
|
||||
|
||||
You may place library facilities that are a work based on the
|
||||
Library side by side in a single library together with other library
|
||||
facilities that are not Applications and are not covered by this
|
||||
License, and convey such a combined library under terms of your
|
||||
choice, if you do both of the following:
|
||||
|
||||
a) Accompany the combined library with a copy of the same work based
|
||||
on the Library, uncombined with any other library facilities,
|
||||
conveyed under the terms of this License.
|
||||
|
||||
b) Give prominent notice with the combined library that part of it
|
||||
is a work based on the Library, and explaining where to find the
|
||||
accompanying uncombined form of the same work.
|
||||
|
||||
6. Revised Versions of the GNU Lesser General Public License.
|
||||
|
||||
The Free Software Foundation may publish revised and/or new versions
|
||||
of the GNU Lesser General Public License from time to time. Such new
|
||||
versions will be similar in spirit to the present version, but may
|
||||
differ in detail to address new problems or concerns.
|
||||
|
||||
Each version is given a distinguishing version number. If the
|
||||
Library as you received it specifies that a certain numbered version
|
||||
of the GNU Lesser General Public License "or any later version"
|
||||
applies to it, you have the option of following the terms and
|
||||
conditions either of that published version or of any later version
|
||||
published by the Free Software Foundation. If the Library as you
|
||||
received it does not specify a version number of the GNU Lesser
|
||||
General Public License, you may choose any version of the GNU Lesser
|
||||
General Public License ever published by the Free Software Foundation.
|
||||
|
||||
If the Library as you received it specifies that a proxy can decide
|
||||
whether future versions of the GNU Lesser General Public License shall
|
||||
apply, that proxy's public statement of acceptance of any version is
|
||||
permanent authorization for you to choose that version for the
|
||||
Library.
|
||||
361
BaS_gcc/Makefile
361
BaS_gcc/Makefile
@@ -1,361 +0,0 @@
|
||||
# Makefile for Firebee BaS
|
||||
#
|
||||
# This Makefile is meant for cross compiling the BaS with Vincent Riviere's cross compilers.
|
||||
# If you want to compile native on an Atari (you will need at least GCC 4.6.3), set
|
||||
# TCPREFIX to be empty.
|
||||
#
|
||||
# If you want to compile with the m68k-elf- toolchain, set TCPREFIX accordingly. Requires an extra
|
||||
# installation, but allows source level debugging over BDM with a recent gdb (tested with 7.5),
|
||||
# the m68k BDM tools from sourceforge (http://bdm.sourceforge.net) and a BDM pod (TBLCF and P&E tested).
|
||||
|
||||
|
||||
ifneq (yes,$(VERBOSE))
|
||||
Q=@
|
||||
else
|
||||
Q=
|
||||
endif
|
||||
|
||||
# can be either "Y" or "N" (without quotes). "Y" for using the m68k-elf-, "N" for using the m68k-atari-mint
|
||||
# toolchain
|
||||
COMPILE_ELF=Y
|
||||
|
||||
ifeq (Y,$(COMPILE_ELF))
|
||||
TCPREFIX=m68k-elf-
|
||||
EXE=elf
|
||||
FORMAT=elf32-m68k
|
||||
else
|
||||
TCPREFIX=m68k-atari-mint-
|
||||
EXE=s19
|
||||
FORMAT=srec
|
||||
endif
|
||||
|
||||
CC=$(TCPREFIX)gcc
|
||||
LD=$(TCPREFIX)ld
|
||||
CPP=$(TCPREFIX)cpp
|
||||
OBJCOPY=$(TCPREFIX)objcopy
|
||||
AR=$(TCPREFIX)ar
|
||||
RANLIB=$(TCPREFIX)ranlib
|
||||
NATIVECC=gcc
|
||||
|
||||
ifeq (Y,$(COMPILE_ELF))
|
||||
LDLIBS=-lgcc
|
||||
else
|
||||
LDLIBS=-lgcc
|
||||
endif
|
||||
|
||||
INCLUDE=-Iinclude
|
||||
CFLAGS= -Wall \
|
||||
-O2 \
|
||||
-fomit-frame-pointer \
|
||||
-ffreestanding \
|
||||
-fno-strict-aliasing \
|
||||
-fleading-underscore \
|
||||
-Winline \
|
||||
-Wa,--register-prefix-optional
|
||||
|
||||
CFLAGS_OPTIMIZED = -mcpu=5474 \
|
||||
-Wall \
|
||||
-O2 \
|
||||
-fomit-frame-pointer \
|
||||
-ffreestanding \
|
||||
-fleading-underscore \
|
||||
-Wa,--register-prefix-optional
|
||||
LDFLAGS=
|
||||
|
||||
TRGTDIRS= ./firebee ./m54455 ./m5484lite
|
||||
OBJDIRS=$(patsubst %, %/objs,$(TRGTDIRS))
|
||||
TOOLDIR=util
|
||||
|
||||
VPATH=dma exe flash fs i2c if kbd pci spi sys usb net util video radeon x86emu xhdi
|
||||
|
||||
# Linker control file. The final $(LDCFILE) is intermediate only (preprocessed version of $(LDCSRC)
|
||||
LDCFILE=bas.lk
|
||||
LDRFILE=ram.lk
|
||||
LDCSRC=bas.lk.in
|
||||
LDCBSRC=basflash.lk.in
|
||||
LDCBFS=basflash.lk
|
||||
|
||||
# this Makefile can create the BaS to flash or an arbitrary ram address (for BDM debugging). See
|
||||
# below for the definition of TARGET_ADDRESS
|
||||
FLASH_EXEC=bas.$(EXE)
|
||||
RAM_EXEC=ram.$(EXE)
|
||||
BASFLASH_EXEC=basflash.$(EXE)
|
||||
|
||||
CSRCS= \
|
||||
sysinit.c \
|
||||
init_fpga.c \
|
||||
fault_vectors.c \
|
||||
interrupts.c \
|
||||
\
|
||||
bas_printf.c \
|
||||
bas_string.c \
|
||||
conout.c \
|
||||
\
|
||||
BaS.c \
|
||||
cache.c \
|
||||
mmu.c \
|
||||
mmc.c \
|
||||
unicode.c \
|
||||
ff.c \
|
||||
sd_card.c \
|
||||
wait.c \
|
||||
s19reader.c \
|
||||
flash.c \
|
||||
dma.c \
|
||||
i2c.c \
|
||||
xhdi_sd.c \
|
||||
xhdi_interface.c \
|
||||
pci.c \
|
||||
pci_errata.c \
|
||||
dspi.c \
|
||||
driver_vec.c \
|
||||
driver_mem.c \
|
||||
\
|
||||
MCD_dmaApi.c \
|
||||
MCD_tasks.c \
|
||||
MCD_tasksInit.c \
|
||||
\
|
||||
usb.c \
|
||||
ohci-hcd.c \
|
||||
ehci-hcd.c \
|
||||
usb_hub.c \
|
||||
usb_mouse.c \
|
||||
usb_kbd.c \
|
||||
ikbd.c \
|
||||
\
|
||||
nbuf.c \
|
||||
queue.c \
|
||||
net_timer.c \
|
||||
am79c874.c \
|
||||
bcm5222.c \
|
||||
nif.c \
|
||||
fecbd.c \
|
||||
fec.c \
|
||||
ip.c \
|
||||
udp.c \
|
||||
arp.c \
|
||||
bootp.c \
|
||||
tftp.c \
|
||||
\
|
||||
fbmem.c \
|
||||
fbmon.c \
|
||||
fbmodedb.c \
|
||||
offscreen.c \
|
||||
\
|
||||
videl.c \
|
||||
video.c \
|
||||
\
|
||||
i2c-algo-bit.c \
|
||||
\
|
||||
radeon_base.c \
|
||||
radeon_accel.c \
|
||||
radeon_cursor.c \
|
||||
radeon_monitor.c \
|
||||
radeon_i2c.c \
|
||||
fnt_st_8x16.c \
|
||||
\
|
||||
x86emu.c \
|
||||
x86pcibios.c \
|
||||
x86biosemu.c \
|
||||
x86emu_util.c \
|
||||
\
|
||||
basflash.c \
|
||||
basflash_start.c
|
||||
|
||||
|
||||
ASRCS= \
|
||||
startcf.S \
|
||||
exceptions.S \
|
||||
setjmp.S \
|
||||
xhdi_vec.S \
|
||||
pci_wrappers.S
|
||||
|
||||
ifeq (Y,$(COMPILE_ELF)) # needed for __ vs ___ kludge
|
||||
ASRCS += libgcc_helper.S
|
||||
endif
|
||||
|
||||
SRCS=$(ASRCS) $(CSRCS)
|
||||
COBJS=$(patsubst %.c,%.o,$(CSRCS))
|
||||
AOBJS=$(patsubst %.S,%.o,$(ASRCS))
|
||||
|
||||
OBJS=$(COBJS) $(AOBJS)
|
||||
LIBBAS=libbas.a
|
||||
|
||||
LIBS=$(patsubst %,%/$(LIBBAS),$(TRGTDIRS))
|
||||
|
||||
all: ver fls ram bfl lib tos
|
||||
fls: $(patsubst %,%/$(FLASH_EXEC),$(TRGTDIRS))
|
||||
ram: $(patsubst %,%/$(RAM_EXEC),$(TRGTDIRS))
|
||||
bfl: $(patsubst %,%/$(BASFLASH_EXEC),$(TRGTDIRS))
|
||||
lib: $(LIBS)
|
||||
|
||||
.PHONY: ver
|
||||
ver:
|
||||
touch include/version.h
|
||||
|
||||
.PHONY: tos
|
||||
tos:
|
||||
$(Q)(cd tos; $(MAKE) -s)
|
||||
|
||||
.PHONY: clean
|
||||
clean:
|
||||
$(Q)for d in $(TRGTDIRS);\
|
||||
do rm -f $$d/*.map $$d/*.s19 $$d/*.elf $$d/*.lk $$d/*.a $$d/objs/* $$d/depend;\
|
||||
done
|
||||
$(Q)rm -f tags
|
||||
$(Q)(cd tos; make -s clean)
|
||||
|
||||
|
||||
|
||||
# flags for targets
|
||||
m5484lite/bas.$(EXE): MACHINE=MACHINE_M5484LITE
|
||||
m54455/bas.$(EXE): MACHINE=MACHINE_M54455
|
||||
firebee/bas.$(EXE): MACHINE=MACHINE_FIREBEE
|
||||
|
||||
m5484lite/ram.$(EXE): MACHINE=MACHINE_M5484LITE
|
||||
m54455/ram.$(EXE): MACHINE=MACHINE_M54455
|
||||
firebee/ram.$(EXE): MACHINE=MACHINE_FIREBEE
|
||||
|
||||
m5484lite/basflash.$(EXE): MACHINE=MACHINE_M5484LITE
|
||||
m54455/basflash.$(EXE): MACHINE=MACHINE_M54455
|
||||
firebee/basflash.$(EXE): MACHINE=MACHINE_FIREBEE
|
||||
|
||||
m5484lite/bas.$(EXE): CFLAGS += -mcpu=5484
|
||||
m54455/bas.$(EXE): CFLAGS += -mcpu=54455 -msoft-float
|
||||
firebee/bas.$(EXE): CFLAGS += -mcpu=5474
|
||||
|
||||
m5484lite/ram.$(EXE): CFLAGS += -mcpu=5484
|
||||
m54455/ram.$(EXE): CFLAGS += -mcpu=54455 -msoft-float
|
||||
firebee/ram.$(EXE): CFLAGS += -mcpu=5474
|
||||
|
||||
m5484lite/basflash.$(EXE): CFLAGS += -mcpu=5484
|
||||
m54455/basflash.$(EXE): CFLAGS += -mcpu=54455 -msoft-float
|
||||
firebee/basflash.$(EXE): CFLAGS += -mcpu=5474
|
||||
|
||||
#
|
||||
# generate pattern rules for different object files
|
||||
#
|
||||
define CC_TEMPLATE
|
||||
$(1)/objs/%.o:%.c
|
||||
$(Q)echo CC $$<
|
||||
$(Q)$(CC) $$(CFLAGS) -D$$(MACHINE) $(INCLUDE) -c $$< -o $$@
|
||||
|
||||
$(1)/objs/%.o:%.S
|
||||
$(Q)echo CC $$<
|
||||
$(Q)$(CC) $$(CFLAGS) -Wa,--bitwise-or -D$$(MACHINE) $(INCLUDE) -c $$< -o $$@
|
||||
endef
|
||||
$(foreach DIR,$(TRGTDIRS),$(eval $(call CC_TEMPLATE,$(DIR))))
|
||||
|
||||
# rules for depend
|
||||
define DEP_TEMPLATE
|
||||
ifneq (clean,$$(MAKECMDGOALS))
|
||||
include $(1)/depend
|
||||
endif
|
||||
|
||||
ifeq (firebee,$(1))
|
||||
MACHINE=MACHINE_FIREBEE
|
||||
else
|
||||
MACHINE=MACHINE_M5484LITE
|
||||
endif
|
||||
$(1)/depend:$(SRCS)
|
||||
$(Q)echo DEPEND
|
||||
$(Q)$(CC) $$(CFLAGS) -D$$(MACHINE) $(INCLUDE) -M $$^ | sed -e "s#^\(.*\).o:#"$(1)"/objs/\1.o:#" > $$@
|
||||
endef
|
||||
$(foreach DIR,$(TRGTDIRS),$(eval $(call DEP_TEMPLATE,$(DIR))))
|
||||
|
||||
|
||||
#
|
||||
# generate pattern rules for libraries
|
||||
#
|
||||
define AR_TEMPLATE
|
||||
$(1)_OBJS=$(patsubst %,$(1)/objs/%,$(OBJS))
|
||||
$(1)/$(LIBBAS): $$($(1)_OBJS)
|
||||
$(Q)echo AR $$@
|
||||
$(Q)$(AR) r $$@ $$?
|
||||
$(Q)$(RANLIB) $$@
|
||||
endef
|
||||
$(foreach DIR,$(TRGTDIRS),$(eval $(call AR_TEMPLATE,$(DIR))))
|
||||
|
||||
ifeq ($(COMPILE_ELF),Y)
|
||||
FORMAT_ELF=1
|
||||
else
|
||||
FORMAT_ELF=0
|
||||
endif
|
||||
|
||||
define LK_TEMPLATE
|
||||
$(1)/$$(LDCFILE): $(LDCSRC)
|
||||
$(Q)echo CPP $$<
|
||||
$(Q)$(CPP) $(INCLUDE) -DOBJDIR=$(1)/objs -P -DFORMAT_ELF=$(FORMAT_ELF) -D$$(MACHINE) $$< -o $$@
|
||||
endef
|
||||
$(foreach DIR,$(TRGTDIRS),$(eval $(call LK_TEMPLATE,$(DIR))))
|
||||
|
||||
#
|
||||
# define pattern rules for binaries
|
||||
#
|
||||
define EX_TEMPLATE
|
||||
# pattern rule for flash
|
||||
$(1)_MAPFILE=$(1)/$$(basename $$(FLASH_EXEC)).map
|
||||
$(1)/$$(FLASH_EXEC): $(1)/$(LIBBAS) $(1)/$$(LDCFILE)
|
||||
$(Q)echo CC $$@
|
||||
$(Q)$(CC) $$(CFLAGS) -nostdlib -Wl,--oformat -Wl,$$(FORMAT) -Wl,-Map -Wl,$$($(1)_MAPFILE) -Wl,--cref -Wl,-T -Wl,$(1)/$$(LDCFILE) $(LDLIBS) -o $$@
|
||||
ifeq ($(COMPILE_ELF),Y)
|
||||
$(Q)echo OBJCOPY $$@
|
||||
$(Q)$(OBJCOPY) -O srec $$@ $$(basename $$@).s19
|
||||
else
|
||||
$(Q)echo OBJCOPY $$@
|
||||
$(Q)objcopy -I srec -O elf32-big --alt-machine-code 4 $$@ $$(basename $$@).elf
|
||||
endif
|
||||
|
||||
# pattern rule for RAM
|
||||
$(1)_MAPFILE_RAM=$(1)/$$(basename $$(RAM_EXEC)).map
|
||||
$(1)/$$(RAM_EXEC): $(1)/$(LIBBAS) $(1)/$$(LDCFILE)
|
||||
$(Q)echo CPP $$@
|
||||
$(Q)$(CPP) $(INCLUDE) -DCOMPILE_RAM -DOBJDIR=$(1)/objs -P -DFORMAT_ELF=$(FORMAT_ELF) -D$$(MACHINE) $(LDCSRC) -o $(1)/$$(LDRFILE)
|
||||
$(Q)echo CC $$@
|
||||
$(Q)$(CC) $$(CFLAGS) -nostdlib -Wl,--oformat -Wl,$$(FORMAT) -Wl,-Map -Wl,$$($(1)_MAPFILE_RAM) -Wl,--cref -Wl,-T -Wl,$(1)/$$(LDRFILE) $(LDLIBS) -o $$@
|
||||
ifeq ($(COMPILE_ELF),Y)
|
||||
$(Q)echo OBJCOPY $$@
|
||||
$(Q)$(OBJCOPY) -O srec $$@ $$(basename $$@).s19
|
||||
else
|
||||
$(Q)echo OBJCOPY $$<
|
||||
$(Q)objcopy -I srec -O elf32-big --alt-machine-code 4 $$@ $$(basename $$@).elf
|
||||
endif
|
||||
|
||||
# pattern rule for basflash
|
||||
$(1)_MAPFILE_BFL=$(1)/$$(basename $$(BASFLASH_EXEC)).map
|
||||
$(1)/$$(BASFLASH_EXEC): $(1)/objs/basflash.o $(1)/objs/basflash_start.o $(1)/$(LIBBAS) $(LDCBFL)
|
||||
$(Q)echo CPP $$<
|
||||
$(CPP) $(INCLUDE) -P -DOBJDIR=$(1)/objs -DFORMAT_ELF=$(FORMAT_ELF) -D$$(MACHINE) $(LDCBSRC) -o $(1)/$$(LDCBFS)
|
||||
$(Q)echo CC $$<
|
||||
$(Q)$(CC) -nostdlib -Wl,--oformat -Wl,$$(FORMAT) -Wl,-Map -Wl,$$($(1)_MAPFILE_BFL) -Wl,--cref -Wl,-T -Wl,$(1)/$$(LDCBFS) -L$(1) -lbas $(LDLIBS) -o $$@
|
||||
ifeq ($(COMPILE_ELF),Y)
|
||||
$(Q)echo OBJCOPY $$<
|
||||
$(Q)$(OBJCOPY) -O srec $$@ $$(basename $$@).s19
|
||||
else
|
||||
$(Q)echo OBJCOPY $$<
|
||||
$(Q)objcopy -I srec -O elf32-big --alt-machine-code 4 $$@ $$(basename $$@).elf
|
||||
endif
|
||||
endef
|
||||
$(foreach DIR,$(TRGTDIRS),$(eval $(call EX_TEMPLATE,$(DIR))))
|
||||
|
||||
|
||||
indent: $(CSRCS)
|
||||
indent $<
|
||||
|
||||
.PHONY: tags
|
||||
tags:
|
||||
ctags $(patsubst %,%/*,$(VPATH))
|
||||
|
||||
.PHONY: printvars
|
||||
printvars:
|
||||
$(Q)$(foreach V,$(.VARIABLES), $(if $(filter-out environment% default automatic, $(origin $V)),$(warning $V=$($V))))
|
||||
ifeq (MACHINE_M5484LITE,$$(MACHINE))
|
||||
MNAME=m5484lite
|
||||
else ifeq (MACHINE_FIREBEE,$(MACHINE))
|
||||
MNAME=firebee
|
||||
endif
|
||||
|
||||
tools:
|
||||
$(NATIVECC) $(INCLUDE) -c $(TOOLDIR)/s19header.c -o $(TOOLDIR)/s19header.o
|
||||
$(NATIVECC) -o $(TOOLDIR)/s19header $(TOOLDIR)/s19header.o
|
||||
|
||||
@@ -1,282 +0,0 @@
|
||||
#if defined(MACHINE_FIREBEE)
|
||||
#include "firebee.h"
|
||||
#elif defined(MACHINE_M5484LITE)
|
||||
# include "m5484l.h"
|
||||
#elif defined(MACHINE_M54455)
|
||||
#include "m54455.h"
|
||||
#else
|
||||
#error "unknown machine!"
|
||||
#endif /* MACHINE_M5484LITE */
|
||||
|
||||
/* make bas_rom access flags rx if compiling to RAM */
|
||||
#ifdef COMPILE_RAM
|
||||
#define ROMFLAGS WX
|
||||
#else
|
||||
#define ROMFLAGS RX
|
||||
#endif /* COMPILE_RAM */
|
||||
|
||||
MEMORY
|
||||
{
|
||||
bas_rom (ROMFLAGS) : ORIGIN = TARGET_ADDRESS, LENGTH = 0x00100000
|
||||
/*
|
||||
* target to copy BaS data segment to. 1M should be enough for now
|
||||
*/
|
||||
bas_ram (WX) : ORIGIN = SDRAM_START + SDRAM_SIZE - 0x00200000, LENGTH = 0x00100000
|
||||
/*
|
||||
* driver_ram is an uncached, reserved memory area for drivers (e.g. USB) that need this type of memory
|
||||
*/
|
||||
driver_ram (WX) : ORIGIN = SDRAM_START + SDRAM_SIZE - 0x00100000, LENGTH = 0x00100000
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
/* BaS in ROM */
|
||||
.text :
|
||||
{
|
||||
OBJDIR/startcf.o(.text) /* this one is the entry point so it must be the first */
|
||||
|
||||
OBJDIR/sysinit.o(.text)
|
||||
OBJDIR/fault_vectors.o(.text)
|
||||
#ifdef MACHINE_FIREBEE
|
||||
OBJDIR/init_fpga.o(.text)
|
||||
#endif /* MACHINE_FIREBEE */
|
||||
OBJDIR/wait.o(.text)
|
||||
OBJDIR/exceptions.o(.text)
|
||||
OBJDIR/setjmp.o(.text)
|
||||
OBJDIR/driver_vec.o(.text)
|
||||
OBJDIR/interrupts.o(.text)
|
||||
OBJDIR/mmu.o(.text)
|
||||
|
||||
OBJDIR/BaS.o(.text)
|
||||
OBJDIR/pci.o(.text)
|
||||
. = ALIGN(16);
|
||||
OBJDIR/pci_errata.o(.text)
|
||||
OBJDIR/pci_wrappers.o(.text)
|
||||
OBJDIR/usb.o(.text)
|
||||
OBJDIR/driver_mem.o(.text)
|
||||
OBJDIR/usb_hub.o(.text)
|
||||
OBJDIR/usb_mouse.o(.text)
|
||||
OBJDIR/usb_kbd.o(.text)
|
||||
OBJDIR/ohci-hcd.o(.text)
|
||||
OBJDIR/ehci-hcd.o(.text)
|
||||
OBJDIR/wait.o(.text)
|
||||
|
||||
OBJDIR/nbuf.o(.text)
|
||||
OBJDIR/net_timer.o(.text)
|
||||
OBJDIR/queue.o(.text)
|
||||
OBJDIR/nif.o(.text)
|
||||
OBJDIR/fecbd.o(.text)
|
||||
OBJDIR/fec.o(.text)
|
||||
OBJDIR/am79c874.o(.text)
|
||||
OBJDIR/bcm5222.o(.text)
|
||||
OBJDIR/ip.o(.text)
|
||||
OBJDIR/udp.o(text)
|
||||
OBJDIR/bootp.o(text)
|
||||
OBJDIR/tftp.o(text)
|
||||
OBJDIR/arp.o(text)
|
||||
|
||||
OBJDIR/unicode.o(.text)
|
||||
OBJDIR/mmc.o(.text)
|
||||
OBJDIR/ff.o(.text)
|
||||
OBJDIR/sd_card.o(.text)
|
||||
OBJDIR/s19reader.o(.text)
|
||||
OBJDIR/bas_printf.o(.text)
|
||||
OBJDIR/bas_string.o(.text)
|
||||
OBJDIR/conout.o(.text)
|
||||
#if (FORMAT_ELF == 1)
|
||||
OBJDIR/libgcc_helper.o(.text)
|
||||
#endif
|
||||
OBJDIR/cache.o(.text)
|
||||
OBJDIR/dma.o(.text)
|
||||
OBJDIR/MCD_dmaApi.o(.text)
|
||||
OBJDIR/MCD_tasks.o(.text)
|
||||
OBJDIR/MCD_tasksInit.o(.text)
|
||||
|
||||
OBJDIR/video.o(.text)
|
||||
OBJDIR/videl.o(.text)
|
||||
OBJDIR/fbmem.o(.text)
|
||||
OBJDIR/fbmon.o(.text)
|
||||
OBJDIR/fbmodedb.o(.text)
|
||||
OBJDIR/fnt_st_8x16.o(.text)
|
||||
OBJDIR/offscreen.o(.text)
|
||||
|
||||
OBJDIR/x86emu.o(.text)
|
||||
OBJDIR/x86emu_util.o(.text)
|
||||
OBJDIR/x86pcibios.o(.text)
|
||||
OBJDIR/x86biosemu.o(.text)
|
||||
|
||||
OBJDIR/i2c-algo-bit.o(.text)
|
||||
|
||||
OBJDIR/radeon_base.o(.text)
|
||||
OBJDIR/radeon_accel.o(.text)
|
||||
OBJDIR/radeon_cursor.o(.text)
|
||||
OBJDIR/radeon_monitor.o(.text)
|
||||
OBJDIR/radeon_i2c.o(.text)
|
||||
|
||||
OBJDIR/xhdi_sd.o(.text)
|
||||
OBJDIR/xhdi_interface.o(.text)
|
||||
OBJDIR/xhdi_vec.o(.text)
|
||||
|
||||
#ifdef COMPILE_RAM
|
||||
/*
|
||||
* if we compile to RAM anyway, there is no need to copy anything
|
||||
*/
|
||||
. = ALIGN(4);
|
||||
__BAS_DATA_START = .;
|
||||
*(.data)
|
||||
__BAS_DATA_END = .;
|
||||
__BAS_BSS_START = .;
|
||||
*(.bss)
|
||||
__BAS_BSS_END = .;
|
||||
#endif /* COMPILE_RAM */
|
||||
|
||||
#if (FORMAT_ELF == 1)
|
||||
*(.eh_frame)
|
||||
*(.rodata)
|
||||
*(.rodata.*)
|
||||
#endif
|
||||
} > bas_rom
|
||||
|
||||
|
||||
#if (TARGET_ADDRESS == BOOTFLASH_BASE_ADDRESS)
|
||||
/*
|
||||
* put BaS .data and .bss segments to flash, but relocate it to RAM after initialize_hardware() ran
|
||||
*/
|
||||
.bas :
|
||||
AT (ALIGN(ADDR(.text) + SIZEOF(.text), 4))
|
||||
{
|
||||
. = ALIGN(4); /* same alignment than AT() statement! */
|
||||
__BAS_DATA_START = .;
|
||||
*(.data)
|
||||
__BAS_DATA_END = .;
|
||||
__BAS_BSS_START = .;
|
||||
*(.bss)
|
||||
__BAS_BSS_END = .;
|
||||
|
||||
. = ALIGN(16);
|
||||
} > bas_ram
|
||||
#endif
|
||||
|
||||
.driver_memory :
|
||||
{
|
||||
. = ALIGN(4);
|
||||
_driver_mem_buffer = .;
|
||||
//. = . + DRIVER_MEM_BUFFER_SIZE;
|
||||
} > driver_ram
|
||||
|
||||
/*
|
||||
* Global memory map
|
||||
*/
|
||||
|
||||
/* SDRAM Initialization */
|
||||
___SDRAM = SDRAM_START;
|
||||
___SDRAM_SIZE = SDRAM_SIZE;
|
||||
_SDRAM_VECTOR_TABLE = ___SDRAM;
|
||||
|
||||
/* ST-RAM */
|
||||
__STRAM = ___SDRAM;
|
||||
__STRAM_END = __TOS;
|
||||
|
||||
/* TOS */
|
||||
__TOS = 0x00e00000;
|
||||
|
||||
/* FastRAM */
|
||||
__FASTRAM = 0x10000000;
|
||||
__TARGET_ADDRESS = TARGET_ADDRESS;
|
||||
|
||||
#if TARGET_ADDRESS == BOOTFLASH_BASE_ADDRESS
|
||||
__FASTRAM_END = __BAS_IN_RAM;
|
||||
#else
|
||||
__FASTRAM_END = TARGET_ADDRESS;
|
||||
#endif
|
||||
__FASTRAM_SIZE = __FASTRAM_END - __FASTRAM;
|
||||
|
||||
/* Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes) */
|
||||
___BOOT_FLASH = BOOTFLASH_BASE_ADDRESS;
|
||||
___BOOT_FLASH_SIZE = BOOTFLASH_SIZE;
|
||||
|
||||
#if TARGET_ADDRESS == BOOTFLASH_BASE_ADDRESS
|
||||
/* BaS */
|
||||
__BAS_LMA = LOADADDR(.bas);
|
||||
__BAS_IN_RAM = ADDR(.bas);
|
||||
__BAS_SIZE = SIZEOF(.bas);
|
||||
#else
|
||||
/* BaS is already in RAM - no need to copy anything */
|
||||
__BAS_IN_RAM = __FASTRAM_END;
|
||||
__BAS_SIZE = 0;
|
||||
__BAS_LMA = __BAS_IN_RAM;
|
||||
#endif
|
||||
|
||||
/* Other flash components */
|
||||
__FIRETOS = 0xe0400000;
|
||||
__EMUTOS = EMUTOS_BASE_ADDRESS;
|
||||
__EMUTOS_SIZE = 0x00100000;
|
||||
|
||||
/* where FPGA data lives in flash */
|
||||
__FPGA_CONFIG = 0xe0700000;
|
||||
__FPGA_CONFIG_SIZE = 0x100000;
|
||||
|
||||
/* VIDEO RAM BASIS */
|
||||
__VRAM = 0x60000000;
|
||||
|
||||
/* Memory mapped registers */
|
||||
__MBAR = 0xFF000000;
|
||||
|
||||
/* 32KB on-chip System SRAM */
|
||||
__SYS_SRAM = __MBAR + 0x10000;
|
||||
__SYS_SRAM_SIZE = 0x00008000;
|
||||
|
||||
/* MMU memory mapped registers */
|
||||
__MMUBAR = 0xFF040000;
|
||||
|
||||
#if !defined(MACHINE_M54455) /* MCF54455 does not have RAMBAR0 and RAMBAR1 registers */
|
||||
/*
|
||||
* 4KB on-chip Core SRAM0: -> exception table
|
||||
*/
|
||||
__RAMBAR0 = 0xFF100000;
|
||||
__RAMBAR0_SIZE = 0x00001000;
|
||||
|
||||
/* 4KB on-chip Core SRAM1 */
|
||||
__RAMBAR1 = 0xFF101000;
|
||||
__RAMBAR1_SIZE = 0x00001000;
|
||||
__SUP_SP = __RAMBAR1 + __RAMBAR1_SIZE - 4;
|
||||
#else
|
||||
__RAMBAR0 = 0x80000000; /* RAMBAR must be between 0x80000000 on MCF54455 */
|
||||
__RAMBAR0_SIZE = 0x1000;
|
||||
__SUP_SP = __RAMBAR0 + __RAMBAR0_SIZE + 0x1000 - 4;
|
||||
#endif
|
||||
|
||||
/*
|
||||
* FPGA_JTAG_LOADED (if 1) indicates that FPGA configuration has been loaded through JTAG
|
||||
* and shouldn't be overwritten on boot. For this to work (and not let us be faked
|
||||
* by a random uninitialised value), __FPGA_JTAG_VALID is used as a "magic value" and must be
|
||||
* 0xaffeaffe to make this work.
|
||||
*/
|
||||
#if !defined(MACHINE_M54455) /* MCF54455 does not have RAMBAR0 and RAMBAR1 */
|
||||
__FPGA_JTAG_LOADED = __RAMBAR1;
|
||||
__FPGA_JTAG_VALID = __RAMBAR1 + 4;
|
||||
#else
|
||||
__FPGA_JTAG_LOADED = __RAMBAR0 + 0x1000;
|
||||
__FPGA_JTAG_VALID = __RAMBAR0 + 0x1000 + 4;
|
||||
#endif
|
||||
|
||||
/* system variables */
|
||||
/* RAMBAR0 0 to 0x7FF -> exception vectors */
|
||||
_rt_mod = __RAMBAR0 + 0x800;
|
||||
_rt_ssp = __RAMBAR0 + 0x804;
|
||||
_rt_usp = __RAMBAR0 + 0x808;
|
||||
_rt_vbr = __RAMBAR0 + 0x80C; /* (8)01 */
|
||||
_rt_cacr = __RAMBAR0 + 0x810; /* 002 */
|
||||
_rt_asid = __RAMBAR0 + 0x814; /* 003 */
|
||||
_rt_acr0 = __RAMBAR0 + 0x818; /* 004 */
|
||||
_rt_acr1 = __RAMBAR0 + 0x81c; /* 005 */
|
||||
_rt_acr2 = __RAMBAR0 + 0x820; /* 006 */
|
||||
_rt_acr3 = __RAMBAR0 + 0x824; /* 007 */
|
||||
_rt_mmubar = __RAMBAR0 + 0x828; /* 008 */
|
||||
_rt_sr = __RAMBAR0 + 0x82c;
|
||||
_d0_save = __RAMBAR0 + 0x830;
|
||||
_a7_save = __RAMBAR0 + 0x834;
|
||||
_video_tlb = __RAMBAR0 + 0x838;
|
||||
_video_sbt = __RAMBAR0 + 0x83C;
|
||||
_rt_mbar = __RAMBAR0 + 0x844; /* (c)0f */
|
||||
}
|
||||
@@ -1,68 +0,0 @@
|
||||
#!/usr/local/bin/bdmctrl -D2 -v9 -d9
|
||||
#
|
||||
# firebee board initialization for bdmctrl
|
||||
#
|
||||
open $1
|
||||
reset
|
||||
sleep 10
|
||||
|
||||
# Turn on MBAR at 0xFF00_0000
|
||||
write-ctrl 0x0C0F 0xFF000000
|
||||
|
||||
# set VBR
|
||||
write-ctrl 0x0801 0x00000000
|
||||
|
||||
# Turn on RAMBAR0 at address FF10_0000
|
||||
write-ctrl 0x0C04 0xFF100007
|
||||
|
||||
# Turn on RAMBAR1 at address FF10_1000 (disabled - not mapped by bdm currently)
|
||||
write-ctrl 0x0C05 0xFF101001
|
||||
|
||||
# Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes)
|
||||
write 0xFF000500 0xE0000000 4
|
||||
write 0xFF000508 0x00041180 4
|
||||
write 0xFF000504 0x007F0001 4
|
||||
wait
|
||||
|
||||
# Init CS1 (Atari I/O address range)
|
||||
write 0xFF00050C 0xFFF00000 4
|
||||
write 0xFF000514 0x00002180 4
|
||||
write 0xFF000510 0x000F0001 4
|
||||
# Init CS2 (FireBee 32 bit I/O address range)
|
||||
write 0xFF000518 0xF0000000 4
|
||||
write 0xFF000520 0x00002100 4
|
||||
write 0xFF00051C 0x07FF0001 4
|
||||
# Init CS3 (FireBee 16 bit I/O address range)
|
||||
write 0xFF000524 0xF8000000 4
|
||||
write 0xFF00052C 0x00000180 4
|
||||
write 0xFF000528 0x03FF0001 4
|
||||
# Init CS4 (FireBee video address range)
|
||||
write 0xFF000530 0x40000000 4
|
||||
write 0xFF000538 0x00000018 4
|
||||
write 0xFF000534 0x003F0001 4
|
||||
|
||||
|
||||
# SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes
|
||||
write 0xFF000004 0x000002AA 4 # SDRAMDS configuration
|
||||
write 0xFF000020 0x0000001A 4 # SDRAM CS0 configuration (128Mbytes 0000_0000 - 07FF_FFFF)
|
||||
write 0xFF000024 0x0800001A 4 # SDRAM CS1 configuration (128Mbytes 0800_0000 - 0FFF_FFFF)
|
||||
write 0xFF000028 0x1000001A 4 # SDRAM CS2 configuration (128Mbytes 1000_0000 - 17FF_FFFF)
|
||||
write 0xFF00002C 0x1800001A 4 # SDRAM CS3 configuration (128Mbytes 1800_0000 - 1FFF_FFFF)
|
||||
write 0xFF000108 0x73622830 4 # SDCFG1
|
||||
write 0xFF00010C 0x46770000 4 # SDCFG2
|
||||
|
||||
write 0xFF000104 0xE10D0002 4 # SDCR + IPALL
|
||||
write 0xFF000100 0x40010000 4 # SDMR (write to LEMR)
|
||||
write 0xFF000100 0x048D0000 4 # SDMR (write to LMR)
|
||||
sleep 100
|
||||
write 0xFF000104 0xE10D0002 4 # SDCR + IPALL
|
||||
write 0xFF000104 0xE10D0004 4 # SDCR + IREF (first refresh)
|
||||
write 0xFF000104 0xE10D0004 4 # SDCR + IREF (first refresh)
|
||||
write 0xFF000100 0x008D0000 4 # SDMR (write to LMR)
|
||||
write 0xFF000104 0x710D0F00 4 # SDCR (lock SDMR and enable refresh)
|
||||
sleep 100
|
||||
|
||||
load -v firebee/ram.elf
|
||||
|
||||
execute
|
||||
wait
|
||||
@@ -1,56 +0,0 @@
|
||||
#!/usr/local/bin/bdmctrl -D2 -v9 -d9
|
||||
#
|
||||
# firebee board initialization for bdmctrl
|
||||
#
|
||||
open $1
|
||||
reset
|
||||
sleep 10
|
||||
|
||||
wait
|
||||
|
||||
# set VBR
|
||||
write-ctrl 0x0801 0x00000000
|
||||
dump-register VBR
|
||||
|
||||
# Turn on MBAR at 0xFF00_0000
|
||||
write-ctrl 0x0C0F 0xFF000000
|
||||
dump-register MBAR
|
||||
|
||||
# Turn on RAMBAR0 at address FF10_0000
|
||||
write-ctrl 0x0C04 0xFF100007
|
||||
|
||||
# Turn on RAMBAR1 at address FF10_1000 (disabled - not mapped by bdm currently)
|
||||
write-ctrl 0x0C05 0xFF101001
|
||||
|
||||
# Init CS0 (BootFLASH @ E000_0000 - E03F_FFFF 8Mbytes)
|
||||
write 0xFF000500 0xE0000000 4
|
||||
write 0xFF000508 0x00041180 4
|
||||
write 0xFF000504 0x003F0001 4
|
||||
wait
|
||||
|
||||
# SDRAM Initialization @ 0000_0000 - 0400_0000 64 MBytes
|
||||
write 0xFF000004 0x000002AA 4 # SDRAMDS configuration
|
||||
write 0xFF000020 0x00000019 4 # SDRAM CS0 configuration (64Mbytes 0000_0000 - 07FF_FFFF)
|
||||
write 0xFF000024 0x00000000 4 # SDRAM CS1 configuration
|
||||
write 0xFF000028 0x00000000 4 # SDRAM CS2 configuration
|
||||
write 0xFF00002C 0x00000000 4 # SDRAM CS3 configuration
|
||||
|
||||
write 0xFF000108 0x73711630 4 # SDCFG1
|
||||
write 0xFF00010C 0x46370000 4 # SDCFG2
|
||||
|
||||
write 0xFF000104 0xE10B0002 4 # SDCR + IPALL
|
||||
write 0xFF000100 0x40010000 4 # SDMR (write to LEMR)
|
||||
write 0xFF000100 0x058D0000 4 # SDMR (write to LMR)
|
||||
sleep 100
|
||||
write 0xFF000104 0xE10D0002 4 # SDCR + IPALL
|
||||
write 0xFF000104 0xE10D0004 4 # SDCR + IREF (first refresh)
|
||||
write 0xFF000104 0xE10D0004 4 # SDCR + IREF (first refresh)
|
||||
write 0xFF000100 0x018D0000 4 # SDMR (write to LMR)
|
||||
write 0xFF000104 0x710D0F00 4 # SDCR (lock SDMR and enable refresh)
|
||||
sleep 100
|
||||
|
||||
load -v m5484lite/ram.elf
|
||||
execute
|
||||
# wait is _needed_ here if using the P&E BDM interface. Otherwise
|
||||
# the Coldfire resets after some time!
|
||||
wait
|
||||
@@ -1,115 +0,0 @@
|
||||
#if defined(MACHINE_FIREBEE)
|
||||
#include "firebee.h"
|
||||
#elif defined(MACHINE_M5484LITE)
|
||||
#include "m5484l.h"
|
||||
#elif defined(MACHINE_M54455)
|
||||
#include "m54455.h"
|
||||
#else
|
||||
#error unknown machine
|
||||
#endif
|
||||
|
||||
MEMORY
|
||||
{
|
||||
flasher (WX) : ORIGIN = BFL_TARGET_ADDRESS, LENGTH = 0x00100000 /* target to load basflash */
|
||||
}
|
||||
|
||||
SECTIONS
|
||||
{
|
||||
.text :
|
||||
{
|
||||
OBJDIR/basflash_start.o(.text)
|
||||
OBJDIR/basflash.o(.text)
|
||||
|
||||
*(.data)
|
||||
*(.bss)
|
||||
*(.rodata)
|
||||
*(.rodata.*)
|
||||
} > flasher
|
||||
|
||||
.bas :
|
||||
{
|
||||
}
|
||||
|
||||
#define BAS_LABEL_LMA(x) ((x))
|
||||
/* _xprintf_before_copy = BAS_LABEL_LMA(_xprintf); */
|
||||
/* _display_progress_before_copy = BAS_LABEL_LMA(_display_progress); */
|
||||
/* _flush_and_invalidate_caches_before_copy = BAS_LABEL_LMA(_flush_and_invalidate_caches); */
|
||||
|
||||
/*
|
||||
* Global memory map
|
||||
*/
|
||||
|
||||
/* SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes */
|
||||
___SDRAM = 0x00000000;
|
||||
___SDRAM_SIZE = 0x20000000;
|
||||
|
||||
/* ST-RAM */
|
||||
__STRAM = ___SDRAM;
|
||||
__STRAM_END = __TOS;
|
||||
|
||||
/* TOS */
|
||||
__TOS = 0x00e00000;
|
||||
|
||||
/* FastRAM */
|
||||
__FASTRAM = 0x10000000;
|
||||
__FASTRAM_END = 0x1FFFFFFF;
|
||||
|
||||
/* Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes) */
|
||||
___BOOT_FLASH = 0xe0000000;
|
||||
___BOOT_FLASH_SIZE = 0x00800000;
|
||||
|
||||
/* BaS */
|
||||
__BAS_LMA = LOADADDR(.bas);
|
||||
__BAS_IN_RAM = ADDR(.bas);
|
||||
__BAS_SIZE = SIZEOF(.bas);
|
||||
|
||||
/* Other flash components */
|
||||
__FIRETOS = 0xe0400000;
|
||||
__EMUTOS = 0xe0600000;
|
||||
__EMUTOS_SIZE = 0x00100000;
|
||||
|
||||
/* VIDEO RAM BASIS */
|
||||
__VRAM = 0x60000000;
|
||||
|
||||
/* Memory mapped registers */
|
||||
__MBAR = 0xFF000000;
|
||||
|
||||
/* 32KB on-chip System SRAM */
|
||||
__SYS_SRAM = 0xFF010000;
|
||||
__SYS_SRAM_SIZE = 0x00008000;
|
||||
|
||||
/* MMU memory mapped registers */
|
||||
__MMUBAR = 0xFF040000;
|
||||
|
||||
/*
|
||||
* 4KB on-chip Core SRAM0: -> exception table and exception stack
|
||||
*/
|
||||
__RAMBAR0 = 0xFF100000;
|
||||
__RAMBAR0_SIZE = 0x00001000;
|
||||
__SUP_SP = __RAMBAR0 + __RAMBAR0_SIZE - 4;
|
||||
|
||||
/* system variables */
|
||||
|
||||
/* RAMBAR0 0 to 0x7FF -> exception vectors */
|
||||
_rt_mod = __RAMBAR0 + 0x800;
|
||||
_rt_ssp = __RAMBAR0 + 0x804;
|
||||
_rt_usp = __RAMBAR0 + 0x808;
|
||||
_rt_vbr = __RAMBAR0 + 0x80C; /* (8)01 */
|
||||
_rt_cacr = __RAMBAR0 + 0x810; /* 002 */
|
||||
_rt_asid = __RAMBAR0 + 0x814; /* 003 */
|
||||
_rt_acr0 = __RAMBAR0 + 0x818; /* 004 */
|
||||
_rt_acr1 = __RAMBAR0 + 0x81c; /* 005 */
|
||||
_rt_acr2 = __RAMBAR0 + 0x820; /* 006 */
|
||||
_rt_acr3 = __RAMBAR0 + 0x824; /* 007 */
|
||||
_rt_mmubar = __RAMBAR0 + 0x828; /* 008 */
|
||||
_rt_sr = __RAMBAR0 + 0x82c;
|
||||
_d0_save = __RAMBAR0 + 0x830;
|
||||
_a7_save = __RAMBAR0 + 0x834;
|
||||
_video_tlb = __RAMBAR0 + 0x838;
|
||||
_video_sbt = __RAMBAR0 + 0x83C;
|
||||
_rt_mbar = __RAMBAR0 + 0x844; /* (c)0f */
|
||||
|
||||
/* 4KB on-chip Core SRAM1: -> modified code */
|
||||
__RAMBAR1 = 0xFF101000;
|
||||
__RAMBAR1_SIZE = 0x00001000;
|
||||
}
|
||||
@@ -1,76 +0,0 @@
|
||||
#!/usr/local/bin/bdmctrl -D2 -v9 -d9
|
||||
#
|
||||
# firebee board initialization for bdmctrl
|
||||
#
|
||||
open $1
|
||||
reset
|
||||
|
||||
# set VBR
|
||||
write-ctrl 0x0801 0x00000000
|
||||
# Turn on MBAR at 0xFF00_0000
|
||||
write-ctrl 0x0C0F 0xFF000000
|
||||
|
||||
# Turn on RAMBAR0 at address FF10_0000
|
||||
write-ctrl 0x0C04 0xFF100007
|
||||
|
||||
# Turn on RAMBAR1 at address FF10_1000 (disabled - not mapped by bdm currently)
|
||||
write-ctrl 0x0C05 0xFF101001
|
||||
|
||||
# Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes)
|
||||
write 0xFF000500 0xE0000000 4
|
||||
write 0xFF000508 0x00041180 4
|
||||
write 0xFF000504 0x007F0001 4
|
||||
wait
|
||||
|
||||
# Init CS1 (Atari I/O address range)
|
||||
write 0xFF00050C 0xFFF00000 4
|
||||
write 0xFF000514 0x00002180 4
|
||||
write 0xFF000510 0x000F0001 4
|
||||
# Init CS2 (FireBee 32 bit I/O address range)
|
||||
write 0xFF000518 0xF0000000 4
|
||||
write 0xFF000520 0x00002100 4
|
||||
write 0xFF00051C 0x07FF0001 4
|
||||
# Init CS3 (FireBee 16 bit I/O address range)
|
||||
write 0xFF000524 0xF8000000 4
|
||||
write 0xFF00052C 0x00000180 4
|
||||
write 0xFF000528 0x03FF0001 4
|
||||
# Init CS4 (FireBee video address range)
|
||||
write 0xFF000530 0x40000000 4
|
||||
write 0xFF000538 0x00000018 4
|
||||
write 0xFF000534 0x003F0001 4
|
||||
|
||||
|
||||
# SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes
|
||||
write 0xFF000004 0x000002AA 4 # SDRAMDS configuration
|
||||
write 0xFF000020 0x0000001A 4 # SDRAM CS0 configuration (128Mbytes 0000_0000 - 07FF_FFFF)
|
||||
write 0xFF000024 0x0800001A 4 # SDRAM CS1 configuration (128Mbytes 0800_0000 - 0FFF_FFFF)
|
||||
write 0xFF000028 0x1000001A 4 # SDRAM CS2 configuration (128Mbytes 1000_0000 - 17FF_FFFF)
|
||||
write 0xFF00002C 0x1800001A 4 # SDRAM CS3 configuration (128Mbytes 1800_0000 - 1FFF_FFFF)
|
||||
write 0xFF000108 0x73622830 4 # SDCFG1
|
||||
write 0xFF00010C 0x46770000 4 # SDCFG2
|
||||
|
||||
write 0xFF000104 0xE10D0002 4 # SDCR + IPALL
|
||||
write 0xFF000100 0x40010000 4 # SDMR (write to LEMR)
|
||||
write 0xFF000100 0x048D0000 4 # SDMR (write to LMR)
|
||||
|
||||
write 0xFF000104 0xE10D0002 4 # SDCR + IPALL
|
||||
write 0xFF000104 0xE10D0004 4 # SDCR + IREF (first refresh)
|
||||
write 0xFF000104 0xE10D0004 4 # SDCR + IREF (first refresh)
|
||||
write 0xFF000100 0x008D0000 4 # SDMR (write to LMR)
|
||||
write 0xFF000104 0x710D0F00 4 # SDCR (lock SDMR and enable refresh)
|
||||
|
||||
dump-register SR
|
||||
write-ctrl 0x80e 0x2700
|
||||
write-ctrl 0x2 0xa50c8120
|
||||
dump-register D0
|
||||
dump-register ASID
|
||||
dump-register ACR0
|
||||
dump-register ACR1
|
||||
dump-register ACR2
|
||||
dump-register ACR3
|
||||
dump-register SR
|
||||
dump-register CACR
|
||||
dump-register RAMBAR1
|
||||
dump-register RAMBAR2
|
||||
dump-register MBAR
|
||||
dump-register 0xc05
|
||||
@@ -1,932 +0,0 @@
|
||||
/*
|
||||
* File: MCD_dmaApi.c
|
||||
* Purpose: Main C file for multi-channel DMA API.
|
||||
*
|
||||
* Notes:
|
||||
*/
|
||||
|
||||
#include "MCD_dma.h"
|
||||
#include "MCD_tasksInit.h"
|
||||
#include "MCD_progCheck.h"
|
||||
|
||||
/********************************************************************/
|
||||
/*
|
||||
* This is an API-internal pointer to the DMA's registers
|
||||
*/
|
||||
dmaRegs *MCD_dmaBar;
|
||||
|
||||
/*
|
||||
* These are the real and model task tables as generated by the
|
||||
* build process
|
||||
*/
|
||||
extern TaskTableEntry MCD_realTaskTableSrc[NCHANNELS];
|
||||
extern TaskTableEntry MCD_modelTaskTableSrc[NUMOFVARIANTS];
|
||||
|
||||
/*
|
||||
* However, this (usually) gets relocated to on-chip SRAM, at which
|
||||
* point we access them as these tables
|
||||
*/
|
||||
volatile TaskTableEntry *MCD_taskTable;
|
||||
TaskTableEntry *MCD_modelTaskTable;
|
||||
|
||||
|
||||
/*
|
||||
* MCD_chStatus[] is an array of status indicators for remembering
|
||||
* whether a DMA has ever been attempted on each channel, pausing
|
||||
* status, etc.
|
||||
*/
|
||||
static int MCD_chStatus[NCHANNELS] =
|
||||
{
|
||||
MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA,
|
||||
MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA,
|
||||
MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA,
|
||||
MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA
|
||||
};
|
||||
|
||||
/*
|
||||
* Prototypes for local functions
|
||||
*/
|
||||
static void MCD_memcpy (int *dest, int *src, u32 size);
|
||||
static void MCD_resmActions (int channel);
|
||||
|
||||
/*
|
||||
* Buffer descriptors used for storage of progress info for single Dmas
|
||||
* Also used as storage for the DMA for CRCs for single DMAs
|
||||
* Otherwise, the DMA does not parse these buffer descriptors
|
||||
*/
|
||||
#ifdef MCD_INCLUDE_EU
|
||||
extern MCD_bufDesc MCD_singleBufDescs[NCHANNELS];
|
||||
#else
|
||||
MCD_bufDesc MCD_singleBufDescs[NCHANNELS];
|
||||
#endif
|
||||
MCD_bufDesc *MCD_relocBuffDesc;
|
||||
|
||||
|
||||
/*
|
||||
* Defines for the debug control register's functions
|
||||
*/
|
||||
#define DBG_CTL_COMP1_TASK (0x00002000) /* have comparator 1 look for a task # */
|
||||
#define DBG_CTL_ENABLE (DBG_CTL_AUTO_ARM | \
|
||||
DBG_CTL_BREAK | \
|
||||
DBG_CTL_INT_BREAK | \
|
||||
DBG_CTL_COMP1_TASK)
|
||||
#define DBG_CTL_DISABLE (DBG_CTL_AUTO_ARM | \
|
||||
DBG_CTL_INT_BREAK | \
|
||||
DBG_CTL_COMP1_TASK)
|
||||
#define DBG_KILL_ALL_STAT (0xFFFFFFFF)
|
||||
|
||||
/*
|
||||
* Offset to context save area where progress info is stored
|
||||
*/
|
||||
#define CSAVE_OFFSET 10
|
||||
|
||||
/*
|
||||
* Defines for Byte Swapping
|
||||
*/
|
||||
#define MCD_BYTE_SWAP_KILLER 0xFFF8888F
|
||||
#define MCD_NO_BYTE_SWAP_ATALL 0x00040000
|
||||
|
||||
/*
|
||||
* Execution Unit Identifiers
|
||||
*/
|
||||
#define MAC 0 /* legacy - not used */
|
||||
#define LUAC 1 /* legacy - not used */
|
||||
#define CRC 2 /* legacy - not used */
|
||||
#define LURC 3 /* Logic Unit with CRC */
|
||||
|
||||
/*
|
||||
* Task Identifiers
|
||||
*/
|
||||
#define TASK_CHAINNOEU 0
|
||||
#define TASK_SINGLENOEU 1
|
||||
#ifdef MCD_INCLUDE_EU
|
||||
#define TASK_CHAINEU 2
|
||||
#define TASK_SINGLEEU 3
|
||||
#define TASK_FECRX 4
|
||||
#define TASK_FECTX 5
|
||||
#else
|
||||
#define TASK_CHAINEU 0
|
||||
#define TASK_SINGLEEU 1
|
||||
#define TASK_FECRX 2
|
||||
#define TASK_FECTX 3
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Structure to remember which variant is on which channel
|
||||
* TBD- need this?
|
||||
*/
|
||||
typedef struct MCD_remVariants_struct MCD_remVariant;
|
||||
struct MCD_remVariants_struct
|
||||
{
|
||||
int remDestRsdIncr[NCHANNELS]; /* -1,0,1 */
|
||||
int remSrcRsdIncr[NCHANNELS]; /* -1,0,1 */
|
||||
s16 remDestIncr[NCHANNELS]; /* DestIncr */
|
||||
s16 remSrcIncr[NCHANNELS]; /* srcIncr */
|
||||
u32 remXferSize[NCHANNELS]; /* xferSize */
|
||||
};
|
||||
|
||||
/*
|
||||
* Structure to remember the startDma parameters for each channel
|
||||
*/
|
||||
MCD_remVariant MCD_remVariants;
|
||||
/********************************************************************/
|
||||
/*
|
||||
* Function: MCD_initDma
|
||||
* Purpose: Initializes the DMA API by setting up a pointer to the DMA
|
||||
* registers, relocating and creating the appropriate task
|
||||
* structures, and setting up some global settings
|
||||
* Arguments:
|
||||
* dmaBarAddr - pointer to the multichannel DMA registers
|
||||
* taskTableDest - location to move DMA task code and structs to
|
||||
* flags - operational parameters
|
||||
* Return Value:
|
||||
* MCD_TABLE_UNALIGNED if taskTableDest is not 512-byte aligned
|
||||
* MCD_OK otherwise
|
||||
*/
|
||||
extern u32 MCD_funcDescTab0[];
|
||||
|
||||
int MCD_initDma (dmaRegs *dmaBarAddr, void *taskTableDest, u32 flags)
|
||||
{
|
||||
int i;
|
||||
TaskTableEntry *entryPtr;
|
||||
|
||||
/* setup the local pointer to register set */
|
||||
MCD_dmaBar = dmaBarAddr;
|
||||
|
||||
/* do we need to move/create a task table */
|
||||
if ((flags & MCD_RELOC_TASKS) != 0)
|
||||
{
|
||||
int fixedSize;
|
||||
u32 *fixedPtr;
|
||||
/*int *tablePtr = taskTableDest;TBD*/
|
||||
int varTabsOffset, funcDescTabsOffset, contextSavesOffset;
|
||||
int taskDescTabsOffset;
|
||||
int taskTableSize, varTabsSize, funcDescTabsSize, contextSavesSize;
|
||||
int taskDescTabSize;
|
||||
|
||||
|
||||
/* check if physical address is aligned on 512 byte boundary */
|
||||
if (((u32) taskTableDest & 0x000001ff) != 0)
|
||||
return MCD_TABLE_UNALIGNED;
|
||||
|
||||
MCD_taskTable = taskTableDest; /* set up local pointer to task Table */
|
||||
|
||||
/*
|
||||
* Create a task table:
|
||||
* - compute aligned base offsets for variable tables and
|
||||
* function descriptor tables, then
|
||||
* - loop through the task table and setup the pointers
|
||||
* - copy over model task table with the the actual task descriptor
|
||||
* tables
|
||||
*/
|
||||
|
||||
taskTableSize = NCHANNELS * sizeof(TaskTableEntry);
|
||||
/* align variable tables to size */
|
||||
varTabsOffset = taskTableSize + (u32)taskTableDest;
|
||||
if ((varTabsOffset & (VAR_TAB_SIZE - 1)) != 0)
|
||||
varTabsOffset = (varTabsOffset + VAR_TAB_SIZE) & (~VAR_TAB_SIZE);
|
||||
/* align function descriptor tables */
|
||||
varTabsSize = NCHANNELS * VAR_TAB_SIZE;
|
||||
funcDescTabsOffset = varTabsOffset + varTabsSize;
|
||||
|
||||
if ((funcDescTabsOffset & (FUNCDESC_TAB_SIZE - 1)) != 0)
|
||||
funcDescTabsOffset = (funcDescTabsOffset + FUNCDESC_TAB_SIZE) &
|
||||
(~FUNCDESC_TAB_SIZE);
|
||||
|
||||
funcDescTabsSize = FUNCDESC_TAB_NUM * FUNCDESC_TAB_SIZE;
|
||||
contextSavesOffset = funcDescTabsOffset + funcDescTabsSize;
|
||||
contextSavesSize = (NCHANNELS * CONTEXT_SAVE_SIZE);
|
||||
fixedSize = taskTableSize + varTabsSize + funcDescTabsSize +
|
||||
contextSavesSize;
|
||||
|
||||
/* zero the thing out */
|
||||
fixedPtr = (u32 *)taskTableDest;
|
||||
for (i = 0;i<(fixedSize/4);i++)
|
||||
fixedPtr[i] = 0;
|
||||
|
||||
entryPtr = (TaskTableEntry*)MCD_taskTable;
|
||||
/* set up fixed pointers */
|
||||
for (i = 0; i < NCHANNELS; i++)
|
||||
{
|
||||
entryPtr[i].varTab = (u32)varTabsOffset; /* update ptr to local value */
|
||||
entryPtr[i].FDTandFlags = (u32)funcDescTabsOffset | MCD_TT_FLAGS_DEF;
|
||||
entryPtr[i].contextSaveSpace = (u32)contextSavesOffset;
|
||||
varTabsOffset += VAR_TAB_SIZE;
|
||||
#ifdef MCD_INCLUDE_EU /* if not there is only one, just point to the same one */
|
||||
funcDescTabsOffset += FUNCDESC_TAB_SIZE;
|
||||
#endif
|
||||
contextSavesOffset += CONTEXT_SAVE_SIZE;
|
||||
}
|
||||
/* copy over the function descriptor table */
|
||||
for ( i = 0; i < FUNCDESC_TAB_NUM; i++)
|
||||
{
|
||||
MCD_memcpy((void*)(entryPtr[i].FDTandFlags & ~MCD_TT_FLAGS_MASK),
|
||||
(void*)MCD_funcDescTab0, FUNCDESC_TAB_SIZE);
|
||||
}
|
||||
|
||||
/* copy model task table to where the context saves stuff leaves off*/
|
||||
MCD_modelTaskTable = (TaskTableEntry*)contextSavesOffset;
|
||||
|
||||
MCD_memcpy ((void*)MCD_modelTaskTable, (void*)MCD_modelTaskTableSrc,
|
||||
NUMOFVARIANTS * sizeof(TaskTableEntry));
|
||||
|
||||
entryPtr = MCD_modelTaskTable; /* point to local version of
|
||||
model task table */
|
||||
taskDescTabsOffset = (u32)MCD_modelTaskTable +
|
||||
(NUMOFVARIANTS * sizeof(TaskTableEntry));
|
||||
|
||||
/* copy actual task code and update TDT ptrs in local model task table */
|
||||
for (i = 0; i < NUMOFVARIANTS; i++)
|
||||
{
|
||||
taskDescTabSize = entryPtr[i].TDTend - entryPtr[i].TDTstart + 4;
|
||||
MCD_memcpy ((void*)taskDescTabsOffset, (void*)entryPtr[i].TDTstart, taskDescTabSize);
|
||||
entryPtr[i].TDTstart = (u32)taskDescTabsOffset;
|
||||
taskDescTabsOffset += taskDescTabSize;
|
||||
entryPtr[i].TDTend = (u32)taskDescTabsOffset - 4;
|
||||
}
|
||||
#ifdef MCD_INCLUDE_EU /* Tack single DMA BDs onto end of code so API controls
|
||||
where they are since DMA might write to them */
|
||||
MCD_relocBuffDesc = (MCD_bufDesc*)(entryPtr[NUMOFVARIANTS - 1].TDTend + 4);
|
||||
#else /* DMA does not touch them so they can be wherever and we don't need to
|
||||
waste SRAM on them */
|
||||
MCD_relocBuffDesc = MCD_singleBufDescs;
|
||||
#endif
|
||||
}
|
||||
else
|
||||
{
|
||||
/* point the would-be relocated task tables and the
|
||||
buffer descriptors to the ones the linker generated */
|
||||
|
||||
if (((u32)MCD_realTaskTableSrc & 0x000001ff) != 0)
|
||||
return(MCD_TABLE_UNALIGNED);
|
||||
|
||||
/* need to add code to make sure that every thing else is aligned properly TBD*/
|
||||
/* this is problematic if we init more than once or after running tasks,
|
||||
need to add variable to see if we have aleady init'd */
|
||||
entryPtr = MCD_realTaskTableSrc;
|
||||
for (i = 0; i < NCHANNELS; i++)
|
||||
{
|
||||
if (((entryPtr[i].varTab & (VAR_TAB_SIZE - 1)) != 0) ||
|
||||
((entryPtr[i].FDTandFlags & (FUNCDESC_TAB_SIZE - 1)) != 0))
|
||||
return(MCD_TABLE_UNALIGNED);
|
||||
}
|
||||
|
||||
MCD_taskTable = MCD_realTaskTableSrc;
|
||||
MCD_modelTaskTable = MCD_modelTaskTableSrc;
|
||||
MCD_relocBuffDesc = MCD_singleBufDescs;
|
||||
}
|
||||
|
||||
|
||||
/* Make all channels as totally inactive, and remember them as such: */
|
||||
|
||||
MCD_dmaBar->taskbar = (u32) MCD_taskTable;
|
||||
for (i = 0; i < NCHANNELS; i++)
|
||||
{
|
||||
MCD_dmaBar->taskControl[i] = 0x0;
|
||||
MCD_chStatus[i] = MCD_NO_DMA;
|
||||
}
|
||||
|
||||
/* Set up pausing mechanism to inactive state: */
|
||||
MCD_dmaBar->debugComp1 = 0; /* no particular values yet for either comparator registers */
|
||||
MCD_dmaBar->debugComp2 = 0;
|
||||
MCD_dmaBar->debugControl = DBG_CTL_DISABLE;
|
||||
MCD_dmaBar->debugStatus = DBG_KILL_ALL_STAT;
|
||||
|
||||
/* enable or disable commbus prefetch, really need an ifdef or
|
||||
something to keep from trying to set this in the 8220 */
|
||||
if ((flags & MCD_COMM_PREFETCH_EN) != 0)
|
||||
MCD_dmaBar->ptdControl &= ~PTD_CTL_COMM_PREFETCH;
|
||||
else
|
||||
MCD_dmaBar->ptdControl |= PTD_CTL_COMM_PREFETCH;
|
||||
|
||||
return MCD_OK;
|
||||
}
|
||||
/*********************** End of MCD_initDma() ***********************/
|
||||
|
||||
/********************************************************************/
|
||||
/* Function: MCD_dmaStatus
|
||||
* Purpose: Returns the status of the DMA on the requested channel
|
||||
* Arguments: channel - channel number
|
||||
* Returns: Predefined status indicators
|
||||
*/
|
||||
int MCD_dmaStatus (int channel)
|
||||
{
|
||||
u16 tcrValue;
|
||||
|
||||
if((channel < 0) || (channel >= NCHANNELS))
|
||||
return(MCD_CHANNEL_INVALID);
|
||||
|
||||
tcrValue = MCD_dmaBar->taskControl[channel];
|
||||
if ((tcrValue & TASK_CTL_EN) == 0)
|
||||
{ /* nothing running */
|
||||
/* if last reported with task enabled */
|
||||
if ( MCD_chStatus[channel] == MCD_RUNNING
|
||||
|| MCD_chStatus[channel] == MCD_IDLE)
|
||||
MCD_chStatus[channel] = MCD_DONE;
|
||||
}
|
||||
else /* something is running */
|
||||
{
|
||||
/* There are three possibilities: paused, running or idle. */
|
||||
if ( MCD_chStatus[channel] == MCD_RUNNING
|
||||
|| MCD_chStatus[channel] == MCD_IDLE)
|
||||
{
|
||||
MCD_dmaBar->ptdDebug = PTD_DBG_TSK_VLD_INIT;
|
||||
/* This register is selected to know which initiator is
|
||||
actually asserted. */
|
||||
if ((MCD_dmaBar->ptdDebug >> channel ) & 0x1 )
|
||||
MCD_chStatus[channel] = MCD_RUNNING;
|
||||
else
|
||||
MCD_chStatus[channel] = MCD_IDLE;
|
||||
/* do not change the status if it is already paused. */
|
||||
}
|
||||
}
|
||||
return MCD_chStatus[channel];
|
||||
}
|
||||
/******************** End of MCD_dmaStatus() ************************/
|
||||
|
||||
/********************************************************************/
|
||||
/* Function: MCD_startDma
|
||||
* Ppurpose: Starts a particular kind of DMA
|
||||
* Arguments: see below
|
||||
* Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
|
||||
*/
|
||||
|
||||
int MCD_startDma (
|
||||
int channel, /* the channel on which to run the DMA */
|
||||
s8 *srcAddr, /* the address to move data from, or physical buffer-descriptor address */
|
||||
s16 srcIncr, /* the amount to increment the source address per transfer */
|
||||
s8 *destAddr, /* the address to move data to */
|
||||
s16 destIncr, /* the amount to increment the destination address per transfer */
|
||||
u32 dmaSize, /* the number of bytes to transfer independent of the transfer size */
|
||||
u32 xferSize, /* the number bytes in of each data movement (1, 2, or 4) */
|
||||
u32 initiator, /* what device initiates the DMA */
|
||||
int priority, /* priority of the DMA */
|
||||
u32 flags, /* flags describing the DMA */
|
||||
u32 funcDesc /* a description of byte swapping, bit swapping, and CRC actions */
|
||||
#ifdef MCD_NEED_ADDR_TRANS
|
||||
s8 *srcAddrVirt /* virtual buffer descriptor address TBD*/
|
||||
#endif
|
||||
)
|
||||
{
|
||||
int srcRsdIncr, destRsdIncr;
|
||||
int *cSave;
|
||||
short xferSizeIncr;
|
||||
int tcrCount = 0;
|
||||
#ifdef MCD_INCLUDE_EU
|
||||
u32 *realFuncArray;
|
||||
#endif
|
||||
|
||||
if((channel < 0) || (channel >= NCHANNELS))
|
||||
return(MCD_CHANNEL_INVALID);
|
||||
|
||||
/* tbd - need to determine the proper response to a bad funcDesc when not
|
||||
including EU functions, for now, assign a benign funcDesc, but maybe
|
||||
should return an error */
|
||||
#ifndef MCD_INCLUDE_EU
|
||||
funcDesc = MCD_FUNC_NOEU1;
|
||||
#endif
|
||||
|
||||
#ifdef MCD_DEBUG
|
||||
printf("startDma:Setting up params\n");
|
||||
#endif
|
||||
/* Set us up for task-wise priority. We don't technically need to do this on every start, but
|
||||
since the register involved is in the same longword as other registers that users are in control
|
||||
of, setting it more than once is probably preferable. That since the documentation doesn't seem
|
||||
to be completely consistent about the nature of the PTD control register. */
|
||||
MCD_dmaBar->ptdControl |= (u16) 0x8000;
|
||||
#if 1 /* Not sure what we need to keep here rtm TBD */
|
||||
/* Calculate additional parameters to the regular DMA calls. */
|
||||
srcRsdIncr = srcIncr < 0 ? -1 : (srcIncr > 0 ? 1 : 0);
|
||||
destRsdIncr = destIncr < 0 ? -1 : (destIncr > 0 ? 1 : 0);
|
||||
|
||||
xferSizeIncr = (xferSize & 0xffff) | 0x20000000;
|
||||
|
||||
/* Remember for each channel which variant is running. */
|
||||
MCD_remVariants.remSrcRsdIncr[channel] = srcRsdIncr;
|
||||
MCD_remVariants.remDestRsdIncr[channel] = destRsdIncr;
|
||||
MCD_remVariants.remDestIncr[channel] = destIncr;
|
||||
MCD_remVariants.remSrcIncr[channel] = srcIncr;
|
||||
MCD_remVariants.remXferSize[channel] = xferSize;
|
||||
#endif
|
||||
|
||||
cSave = (int*)(MCD_taskTable[channel].contextSaveSpace) + CSAVE_OFFSET + CURRBD;
|
||||
|
||||
#ifdef MCD_INCLUDE_EU /* may move this to EU specific calls */
|
||||
realFuncArray = (u32 *) (MCD_taskTable[channel].FDTandFlags & 0xffffff00);
|
||||
/* Modify the LURC's normal and byte-residue-loop functions according to parameter. */
|
||||
realFuncArray[(LURC*16)] = xferSize == 4 ?
|
||||
funcDesc : xferSize == 2 ?
|
||||
funcDesc & 0xfffff00f : funcDesc & 0xffff000f;
|
||||
realFuncArray[(LURC*16+1)] = (funcDesc & MCD_BYTE_SWAP_KILLER) | MCD_NO_BYTE_SWAP_ATALL;
|
||||
#endif
|
||||
/* Write the initiator field in the TCR, and also set the initiator-hold
|
||||
bit. Note that,due to a hardware quirk, this could collide with an
|
||||
MDE access to the initiator-register file, so we have to verify that the write
|
||||
reads back correctly. */
|
||||
|
||||
MCD_dmaBar->taskControl[channel] =
|
||||
(initiator << 8) | TASK_CTL_HIPRITSKEN | TASK_CTL_HLDINITNUM;
|
||||
|
||||
while(((MCD_dmaBar->taskControl[channel] & 0x1fff) !=
|
||||
((initiator << 8) | TASK_CTL_HIPRITSKEN | TASK_CTL_HLDINITNUM)) &&
|
||||
(tcrCount < 1000))
|
||||
{
|
||||
tcrCount++;
|
||||
/*MCD_dmaBar->ptd_tcr[channel] = (initiator << 8) | 0x0020;*/
|
||||
MCD_dmaBar->taskControl[channel] =
|
||||
(initiator << 8) | TASK_CTL_HIPRITSKEN | TASK_CTL_HLDINITNUM;
|
||||
}
|
||||
|
||||
MCD_dmaBar->priority[channel] = (u8)priority & PRIORITY_PRI_MASK;
|
||||
/* should be albe to handle this stuff with only one write to ts reg - tbd */
|
||||
if (channel < 8 && channel >= 0)
|
||||
{
|
||||
MCD_dmaBar->taskSize0 &= ~(0xf << (7-channel)*4);
|
||||
MCD_dmaBar->taskSize0 |= (xferSize & 3) << (((7 - channel)*4) + 2);
|
||||
MCD_dmaBar->taskSize0 |= (xferSize & 3) << ((7 - channel)*4);
|
||||
}
|
||||
else
|
||||
{
|
||||
MCD_dmaBar->taskSize1 &= ~(0xf << (15-channel)*4);
|
||||
MCD_dmaBar->taskSize1 |= (xferSize & 3) << (((15 - channel)*4) + 2);
|
||||
MCD_dmaBar->taskSize1 |= (xferSize & 3) << ((15 - channel)*4);
|
||||
}
|
||||
|
||||
/* setup task table flags/options which mostly control the line buffers */
|
||||
MCD_taskTable[channel].FDTandFlags &= ~MCD_TT_FLAGS_MASK;
|
||||
MCD_taskTable[channel].FDTandFlags |= (MCD_TT_FLAGS_MASK & flags);
|
||||
|
||||
if (flags & MCD_FECTX_DMA)
|
||||
{
|
||||
/* TDTStart and TDTEnd */
|
||||
MCD_taskTable[channel].TDTstart = MCD_modelTaskTable[TASK_FECTX].TDTstart;
|
||||
MCD_taskTable[channel].TDTend = MCD_modelTaskTable[TASK_FECTX].TDTend;
|
||||
MCD_startDmaENetXmit(srcAddr, srcAddr, destAddr, MCD_taskTable, channel);
|
||||
}
|
||||
else if (flags & MCD_FECRX_DMA)
|
||||
{
|
||||
/* TDTStart and TDTEnd */
|
||||
MCD_taskTable[channel].TDTstart = MCD_modelTaskTable[TASK_FECRX].TDTstart;
|
||||
MCD_taskTable[channel].TDTend = MCD_modelTaskTable[TASK_FECRX].TDTend;
|
||||
MCD_startDmaENetRcv(srcAddr, srcAddr, destAddr, MCD_taskTable, channel);
|
||||
}
|
||||
else if(flags & MCD_SINGLE_DMA)
|
||||
{
|
||||
/* this buffer descriptor is used for storing off initial parameters for later
|
||||
progress query calculation and for the DMA to write the resulting checksum
|
||||
The DMA does not use this to determine how to operate, that info is passed
|
||||
with the init routine*/
|
||||
MCD_relocBuffDesc[channel].srcAddr = srcAddr;
|
||||
MCD_relocBuffDesc[channel].destAddr = destAddr;
|
||||
MCD_relocBuffDesc[channel].lastDestAddr = destAddr; /* definitely not its final value */
|
||||
MCD_relocBuffDesc[channel].dmaSize = dmaSize;
|
||||
MCD_relocBuffDesc[channel].flags = 0; /* not used */
|
||||
MCD_relocBuffDesc[channel].csumResult = 0; /* not used */
|
||||
MCD_relocBuffDesc[channel].next = 0; /* not used */
|
||||
|
||||
/* Initialize the progress-querying stuff to show no progress:*/
|
||||
((volatile int *)MCD_taskTable[channel].contextSaveSpace)[SRCPTR + CSAVE_OFFSET] = (int)srcAddr;
|
||||
((volatile int *)MCD_taskTable[channel].contextSaveSpace)[DESTPTR + CSAVE_OFFSET] = (int)destAddr;
|
||||
((volatile int *)MCD_taskTable[channel].contextSaveSpace)[DCOUNT + CSAVE_OFFSET] = 0;
|
||||
((volatile int *)MCD_taskTable[channel].contextSaveSpace)[CURRBD + CSAVE_OFFSET] =
|
||||
(u32) &(MCD_relocBuffDesc[channel]);
|
||||
/* tbd - need to keep the user from trying to call the EU routine
|
||||
when MCD_INCLUDE_EU is not defined */
|
||||
if( funcDesc == MCD_FUNC_NOEU1 || funcDesc == MCD_FUNC_NOEU2)
|
||||
{
|
||||
/* TDTStart and TDTEnd */
|
||||
MCD_taskTable[channel].TDTstart = MCD_modelTaskTable[TASK_SINGLENOEU].TDTstart;
|
||||
MCD_taskTable[channel].TDTend = MCD_modelTaskTable[TASK_SINGLENOEU].TDTend;
|
||||
MCD_startDmaSingleNoEu(srcAddr, srcIncr, destAddr, destIncr, dmaSize,
|
||||
xferSizeIncr, flags, (int *)&(MCD_relocBuffDesc[channel]), cSave,
|
||||
MCD_taskTable, channel);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* TDTStart and TDTEnd */
|
||||
MCD_taskTable[channel].TDTstart = MCD_modelTaskTable[TASK_SINGLEEU].TDTstart;
|
||||
MCD_taskTable[channel].TDTend = MCD_modelTaskTable[TASK_SINGLEEU].TDTend;
|
||||
MCD_startDmaSingleEu(srcAddr, srcIncr, destAddr, destIncr, dmaSize,
|
||||
xferSizeIncr, flags, (int *)&(MCD_relocBuffDesc[channel]), cSave,
|
||||
MCD_taskTable, channel);
|
||||
}
|
||||
}
|
||||
else
|
||||
{ /* chained DMAS */
|
||||
/* Initialize the progress-querying stuff to show no progress:*/
|
||||
#if 1 /* (!defined(MCD_NEED_ADDR_TRANS)) */
|
||||
((volatile int *)MCD_taskTable[channel].contextSaveSpace)[SRCPTR + CSAVE_OFFSET]
|
||||
= (int)((MCD_bufDesc*) srcAddr)->srcAddr;
|
||||
((volatile int *)MCD_taskTable[channel].contextSaveSpace)[DESTPTR + CSAVE_OFFSET]
|
||||
= (int)((MCD_bufDesc*) srcAddr)->destAddr;
|
||||
#else /* if using address translation, need the virtual addr of the first buffdesc */
|
||||
((volatile int *)MCD_taskTable[channel].contextSaveSpace)[SRCPTR + CSAVE_OFFSET]
|
||||
= (int)((MCD_bufDesc*) srcAddrVirt)->srcAddr;
|
||||
((volatile int *)MCD_taskTable[channel].contextSaveSpace)[DESTPTR + CSAVE_OFFSET]
|
||||
= (int)((MCD_bufDesc*) srcAddrVirt)->destAddr;
|
||||
#endif
|
||||
((volatile int *)MCD_taskTable[channel].contextSaveSpace)[DCOUNT + CSAVE_OFFSET] = 0;
|
||||
((volatile int *)MCD_taskTable[channel].contextSaveSpace)[CURRBD + CSAVE_OFFSET] = (u32) srcAddr;
|
||||
|
||||
if( funcDesc == MCD_FUNC_NOEU1 || funcDesc == MCD_FUNC_NOEU2)
|
||||
{
|
||||
/*TDTStart and TDTEnd*/
|
||||
MCD_taskTable[channel].TDTstart = MCD_modelTaskTable[TASK_CHAINNOEU].TDTstart;
|
||||
MCD_taskTable[channel].TDTend = MCD_modelTaskTable[TASK_CHAINNOEU].TDTend;
|
||||
MCD_startDmaChainNoEu((int *)srcAddr, srcIncr, destIncr, xferSize,
|
||||
xferSizeIncr, cSave, MCD_taskTable, channel);
|
||||
}
|
||||
else
|
||||
{
|
||||
/*TDTStart and TDTEnd*/
|
||||
MCD_taskTable[channel].TDTstart = MCD_modelTaskTable[TASK_CHAINEU].TDTstart;
|
||||
MCD_taskTable[channel].TDTend = MCD_modelTaskTable[TASK_CHAINEU].TDTend;
|
||||
MCD_startDmaChainEu((int *)srcAddr, srcIncr, destIncr, xferSize,
|
||||
xferSizeIncr, cSave, MCD_taskTable, channel);
|
||||
}
|
||||
}
|
||||
MCD_chStatus[channel] = MCD_IDLE;
|
||||
return MCD_OK;
|
||||
}
|
||||
|
||||
/************************ End of MCD_startDma() *********************/
|
||||
|
||||
/********************************************************************/
|
||||
/* Function: MCD_XferProgrQuery
|
||||
* Purpose: Returns progress of DMA on requested channel
|
||||
* Arguments: channel - channel to retrieve progress for
|
||||
* progRep - pointer to user supplied MCD_XferProg struct
|
||||
* Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
|
||||
*
|
||||
* Notes:
|
||||
* MCD_XferProgrQuery() upon completing or after aborting a DMA, or
|
||||
* while the DMA is in progress, this function returns the first
|
||||
* DMA-destination address not (or not yet) used in the DMA. When
|
||||
* encountering a non-ready buffer descriptor, the information for
|
||||
* the last completed descriptor is returned.
|
||||
*
|
||||
* MCD_XferProgQuery() has to avoid the possibility of getting
|
||||
* partially-updated information in the event that we should happen
|
||||
* to query DMA progress just as the DMA is updating it. It does that
|
||||
* by taking advantage of the fact context is not saved frequently for
|
||||
* the most part. We therefore read it at least twice until we get the
|
||||
* same information twice in a row.
|
||||
*
|
||||
* Because a small, but not insignificant, amount of time is required
|
||||
* to write out the progress-query information, especially upon
|
||||
* completion of the DMA, it would be wise to guarantee some time lag
|
||||
* between successive readings of the progress-query information.
|
||||
*/
|
||||
|
||||
/*
|
||||
* How many iterations of the loop below to execute to stabilize values
|
||||
*/
|
||||
#define STABTIME 0
|
||||
|
||||
int MCD_XferProgrQuery (int channel, MCD_XferProg *progRep)
|
||||
{
|
||||
MCD_XferProg prevRep;
|
||||
int again; /* true if we are to try again to get consistent results */
|
||||
int i; /* used as a time-waste counter */
|
||||
int destDiffBytes; /* Total number of bytes that we think actually got xfered. */
|
||||
int numIterations; /* number of iterations */
|
||||
int bytesNotXfered; /* bytes that did not get xfered. */
|
||||
s8 *LWAlignedInitDestAddr, *LWAlignedCurrDestAddr;
|
||||
int subModVal, addModVal; /* Mode values to added and subtracted from the
|
||||
final destAddr */
|
||||
|
||||
if((channel < 0) || (channel >= NCHANNELS))
|
||||
return(MCD_CHANNEL_INVALID);
|
||||
|
||||
/* Read a trial value for the progress-reporting values*/
|
||||
prevRep.lastSrcAddr =
|
||||
(s8 *) ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[SRCPTR + CSAVE_OFFSET];
|
||||
prevRep.lastDestAddr =
|
||||
(s8 *) ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[DESTPTR + CSAVE_OFFSET];
|
||||
prevRep.dmaSize = ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[DCOUNT + CSAVE_OFFSET];
|
||||
prevRep.currBufDesc =
|
||||
(MCD_bufDesc*) ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[CURRBD + CSAVE_OFFSET];
|
||||
/* Repeatedly reread those values until they match previous values: */
|
||||
do {
|
||||
/* Waste a little bit of time to ensure stability: */
|
||||
for (i = 0; i < STABTIME; i++)
|
||||
i += i >> 2; /* make sure this loop does something so that it doesn't get optimized out */
|
||||
/* Check them again: */
|
||||
progRep->lastSrcAddr =
|
||||
(s8 *) ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[SRCPTR + CSAVE_OFFSET];
|
||||
progRep->lastDestAddr =
|
||||
(s8 *) ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[DESTPTR + CSAVE_OFFSET];
|
||||
progRep->dmaSize = ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[DCOUNT + CSAVE_OFFSET];
|
||||
progRep->currBufDesc =
|
||||
(MCD_bufDesc*) ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[CURRBD + CSAVE_OFFSET];
|
||||
/* See if they match: */
|
||||
if ( prevRep.lastSrcAddr != progRep->lastSrcAddr
|
||||
|| prevRep.lastDestAddr != progRep->lastDestAddr
|
||||
|| prevRep.dmaSize != progRep->dmaSize
|
||||
|| prevRep.currBufDesc != progRep->currBufDesc)
|
||||
{
|
||||
/* If they don't match, remember previous values and try again:*/
|
||||
prevRep.lastSrcAddr = progRep->lastSrcAddr;
|
||||
prevRep.lastDestAddr = progRep->lastDestAddr;
|
||||
prevRep.dmaSize = progRep->dmaSize;
|
||||
prevRep.currBufDesc = progRep->currBufDesc;
|
||||
again = MCD_TRUE;
|
||||
}
|
||||
else
|
||||
again = MCD_FALSE;
|
||||
} while (again == MCD_TRUE);
|
||||
|
||||
|
||||
/* Update the dCount, srcAddr and destAddr */
|
||||
/* To calculate dmaCount, we consider destination address. C
|
||||
overs M1,P1,Z for destination */
|
||||
switch(MCD_remVariants.remDestRsdIncr[channel]) {
|
||||
case MINUS1:
|
||||
subModVal = ((int)progRep->lastDestAddr) & ((MCD_remVariants.remXferSize[channel]) - 1);
|
||||
addModVal = ((int)progRep->currBufDesc->destAddr) & ((MCD_remVariants.remXferSize[channel]) - 1);
|
||||
LWAlignedInitDestAddr = (progRep->currBufDesc->destAddr) - addModVal;
|
||||
LWAlignedCurrDestAddr = (progRep->lastDestAddr) - subModVal;
|
||||
destDiffBytes = LWAlignedInitDestAddr - LWAlignedCurrDestAddr;
|
||||
bytesNotXfered = (destDiffBytes/MCD_remVariants.remDestIncr[channel]) *
|
||||
( MCD_remVariants.remDestIncr[channel]
|
||||
+ MCD_remVariants.remXferSize[channel]);
|
||||
progRep->dmaSize = destDiffBytes - bytesNotXfered + addModVal - subModVal;
|
||||
break;
|
||||
case ZERO:
|
||||
progRep->lastDestAddr = progRep->currBufDesc->destAddr;
|
||||
break;
|
||||
case PLUS1:
|
||||
/* This value has to be subtracted from the final calculated dCount. */
|
||||
subModVal = ((int)progRep->currBufDesc->destAddr) & ((MCD_remVariants.remXferSize[channel]) - 1);
|
||||
/* These bytes are already in lastDestAddr. */
|
||||
addModVal = ((int)progRep->lastDestAddr) & ((MCD_remVariants.remXferSize[channel]) - 1);
|
||||
LWAlignedInitDestAddr = (progRep->currBufDesc->destAddr) - subModVal;
|
||||
LWAlignedCurrDestAddr = (progRep->lastDestAddr) - addModVal;
|
||||
destDiffBytes = (progRep->lastDestAddr - LWAlignedInitDestAddr);
|
||||
numIterations = ( LWAlignedCurrDestAddr - LWAlignedInitDestAddr)/MCD_remVariants.remDestIncr[channel];
|
||||
bytesNotXfered = numIterations *
|
||||
( MCD_remVariants.remDestIncr[channel]
|
||||
- MCD_remVariants.remXferSize[channel]);
|
||||
progRep->dmaSize = destDiffBytes - bytesNotXfered - subModVal;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
/* This covers M1,P1,Z for source */
|
||||
switch(MCD_remVariants.remSrcRsdIncr[channel]) {
|
||||
case MINUS1:
|
||||
progRep->lastSrcAddr =
|
||||
progRep->currBufDesc->srcAddr +
|
||||
( MCD_remVariants.remSrcIncr[channel] *
|
||||
(progRep->dmaSize/MCD_remVariants.remXferSize[channel]));
|
||||
break;
|
||||
case ZERO:
|
||||
progRep->lastSrcAddr = progRep->currBufDesc->srcAddr;
|
||||
break;
|
||||
case PLUS1:
|
||||
progRep->lastSrcAddr =
|
||||
progRep->currBufDesc->srcAddr +
|
||||
( MCD_remVariants.remSrcIncr[channel] *
|
||||
(progRep->dmaSize/MCD_remVariants.remXferSize[channel]));
|
||||
break;
|
||||
default: break;
|
||||
}
|
||||
|
||||
return MCD_OK;
|
||||
}
|
||||
/******************* End of MCD_XferProgrQuery() ********************/
|
||||
|
||||
/********************************************************************/
|
||||
/* MCD_resmActions() does the majority of the actions of a DMA resume.
|
||||
* It is called from MCD_killDma() and MCD_resumeDma(). It has to be
|
||||
* a separate function because the kill function has to negate the task
|
||||
* enable before resuming it, but the resume function has to do nothing
|
||||
* if there is no DMA on that channel (i.e., if the enable bit is 0).
|
||||
*/
|
||||
static void MCD_resmActions (int channel)
|
||||
{
|
||||
MCD_dmaBar->debugControl = DBG_CTL_DISABLE;
|
||||
MCD_dmaBar->debugStatus = MCD_dmaBar->debugStatus;
|
||||
MCD_dmaBar->ptdDebug = PTD_DBG_TSK_VLD_INIT; /* This register is selected to know
|
||||
which initiator is actually asserted. */
|
||||
if((MCD_dmaBar->ptdDebug >> channel ) & 0x1)
|
||||
MCD_chStatus[channel] = MCD_RUNNING;
|
||||
else
|
||||
MCD_chStatus[channel] = MCD_IDLE;
|
||||
}
|
||||
/********************* End of MCD_resmActions() *********************/
|
||||
|
||||
/********************************************************************/
|
||||
/* Function: MCD_killDma
|
||||
* Purpose: Halt the DMA on the requested channel, without any
|
||||
* intention of resuming the DMA.
|
||||
* Arguments: channel - requested channel
|
||||
* Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
|
||||
*
|
||||
* Notes:
|
||||
* A DMA may be killed from any state, including paused state, and it
|
||||
* always goes to the MCD_HALTED state even if it is killed while in
|
||||
* the MCD_NO_DMA or MCD_IDLE states.
|
||||
*/
|
||||
int MCD_killDma (int channel)
|
||||
{
|
||||
/* MCD_XferProg progRep; */
|
||||
|
||||
if((channel < 0) || (channel >= NCHANNELS))
|
||||
return(MCD_CHANNEL_INVALID);
|
||||
|
||||
MCD_dmaBar->taskControl[channel] = 0x0;
|
||||
MCD_resumeDma (channel);
|
||||
/*
|
||||
* This must be after the write to the TCR so that the task doesn't
|
||||
* start up again momentarily, and before the status assignment so
|
||||
* as to override whatever MCD_resumeDma() may do to the channel
|
||||
* status.
|
||||
*/
|
||||
MCD_chStatus[channel] = MCD_HALTED;
|
||||
|
||||
/*
|
||||
* Update the current buffer descriptor's lastDestAddr field
|
||||
*
|
||||
* MCD_XferProgrQuery (channel, &progRep);
|
||||
* progRep.currBufDesc->lastDestAddr = progRep.lastDestAddr;
|
||||
*/
|
||||
return MCD_OK;
|
||||
}
|
||||
/************************ End of MCD_killDma() **********************/
|
||||
|
||||
/********************************************************************/
|
||||
/* Function: MCD_continDma
|
||||
* Purpose: Continue a DMA which as stopped due to encountering an
|
||||
* unready buffer descriptor.
|
||||
* Arguments: channel - channel to continue the DMA on
|
||||
* Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
|
||||
*
|
||||
* Notes:
|
||||
* This routine does not check to see if there is a task which can
|
||||
* be continued. Also this routine should not be used with single DMAs.
|
||||
*/
|
||||
int MCD_continDma (int channel)
|
||||
{
|
||||
if((channel < 0) || (channel >= NCHANNELS))
|
||||
return(MCD_CHANNEL_INVALID);
|
||||
|
||||
MCD_dmaBar->taskControl[channel] |= TASK_CTL_EN;
|
||||
MCD_chStatus[channel] = MCD_RUNNING;
|
||||
|
||||
return MCD_OK;
|
||||
}
|
||||
/********************** End of MCD_continDma() **********************/
|
||||
|
||||
/*********************************************************************
|
||||
* MCD_pauseDma() and MCD_resumeDma() below use the DMA's debug unit
|
||||
* to freeze a task and resume it. We freeze a task by breakpointing
|
||||
* on the stated task. That is, not any specific place in the task,
|
||||
* but any time that task executes. In particular, when that task
|
||||
* executes, we want to freeze that task and only that task.
|
||||
*
|
||||
* The bits of the debug control register influence interrupts vs.
|
||||
* breakpoints as follows:
|
||||
* - Bits 14 and 0 enable or disable debug functions. If enabled, you
|
||||
* will get the interrupt but you may or may not get a breakpoint.
|
||||
* - Bits 2 and 1 decide whether you also get a breakpoint in addition
|
||||
* to an interrupt.
|
||||
*
|
||||
* The debug unit can do these actions in response to either internally
|
||||
* detected breakpoint conditions from the comparators, or in response
|
||||
* to the external breakpoint pin, or both.
|
||||
* - Bits 14 and 1 perform the above-described functions for
|
||||
* internally-generated conditions, i.e., the debug comparators.
|
||||
* - Bits 0 and 2 perform the above-described functions for external
|
||||
* conditions, i.e., the breakpoint external pin.
|
||||
*
|
||||
* Note that, although you "always" get the interrupt when you turn
|
||||
* the debug functions, the interrupt can nevertheless, if desired, be
|
||||
* masked by the corresponding bit in the PTD's IMR. Note also that
|
||||
* this means that bits 14 and 0 must enable debug functions before
|
||||
* bits 1 and 2, respectively, have any effect.
|
||||
*
|
||||
* NOTE: It's extremely important to not pause more than one DMA channel
|
||||
* at a time.
|
||||
********************************************************************/
|
||||
|
||||
/********************************************************************/
|
||||
/* Function: MCD_pauseDma
|
||||
* Purpose: Pauses the DMA on a given channel (if any DMA is running
|
||||
* on that channel).
|
||||
* Arguments: channel
|
||||
* Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
|
||||
*/
|
||||
int MCD_pauseDma (int channel)
|
||||
{
|
||||
/* MCD_XferProg progRep; */
|
||||
|
||||
if((channel < 0) || (channel >= NCHANNELS))
|
||||
return(MCD_CHANNEL_INVALID);
|
||||
|
||||
if (MCD_dmaBar->taskControl[channel] & TASK_CTL_EN)
|
||||
{
|
||||
MCD_dmaBar->debugComp1 = channel;
|
||||
MCD_dmaBar->debugControl = DBG_CTL_ENABLE | (1 << (channel + 16));
|
||||
MCD_chStatus[channel] = MCD_PAUSED;
|
||||
|
||||
/*
|
||||
* Update the current buffer descriptor's lastDestAddr field
|
||||
*
|
||||
* MCD_XferProgrQuery (channel, &progRep);
|
||||
* progRep.currBufDesc->lastDestAddr = progRep.lastDestAddr;
|
||||
*/
|
||||
}
|
||||
return MCD_OK;
|
||||
}
|
||||
/************************* End of MCD_pauseDma() ********************/
|
||||
|
||||
/********************************************************************/
|
||||
/* Function: MCD_resumeDma
|
||||
* Purpose: Resumes the DMA on a given channel (if any DMA is
|
||||
* running on that channel).
|
||||
* Arguments: channel - channel on which to resume DMA
|
||||
* Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
|
||||
*/
|
||||
int MCD_resumeDma (int channel)
|
||||
{
|
||||
if((channel < 0) || (channel >= NCHANNELS))
|
||||
return(MCD_CHANNEL_INVALID);
|
||||
|
||||
if (MCD_dmaBar->taskControl[channel] & TASK_CTL_EN)
|
||||
MCD_resmActions (channel);
|
||||
|
||||
return MCD_OK;
|
||||
}
|
||||
/************************ End of MCD_resumeDma() ********************/
|
||||
|
||||
/********************************************************************/
|
||||
/* Function: MCD_csumQuery
|
||||
* Purpose: Provide the checksum after performing a non-chained DMA
|
||||
* Arguments: channel - channel to report on
|
||||
* csum - pointer to where to write the checksum/CRC
|
||||
* Returns: MCD_ERROR if the channel is invalid, else MCD_OK
|
||||
*
|
||||
* Notes:
|
||||
*
|
||||
*/
|
||||
int MCD_csumQuery (int channel, u32 *csum)
|
||||
{
|
||||
#ifdef MCD_INCLUDE_EU
|
||||
if((channel < 0) || (channel >= NCHANNELS))
|
||||
return(MCD_CHANNEL_INVALID);
|
||||
|
||||
*csum = MCD_relocBuffDesc[channel].csumResult;
|
||||
return(MCD_OK);
|
||||
#else
|
||||
return MCD_ERROR;
|
||||
#endif
|
||||
}
|
||||
/*********************** End of MCD_resumeDma() *********************/
|
||||
|
||||
/********************************************************************/
|
||||
/* Function: MCD_getCodeSize
|
||||
* Purpose: Provide the size requirements of the microcoded tasks
|
||||
* Returns: Size in bytes
|
||||
*/
|
||||
int MCD_getCodeSize(void)
|
||||
{
|
||||
#ifdef MCD_INCLUDE_EU
|
||||
return(0x2b5c);
|
||||
#else
|
||||
return(0x173c);
|
||||
#endif
|
||||
}
|
||||
/********************** End of MCD_getCodeSize() ********************/
|
||||
|
||||
/********************************************************************/
|
||||
/* Function: MCD_getVersion
|
||||
* Purpose: Provide the version string and number
|
||||
* Arguments: longVersion - user supplied pointer to a pointer to a char
|
||||
* which points to the version string
|
||||
* Returns: Version number and version string (by reference)
|
||||
*/
|
||||
char MCD_versionString[] = "Multi-channel DMA API Alpha v0.3 (2004-04-26)";
|
||||
#define MCD_REV_MAJOR 0x00
|
||||
#define MCD_REV_MINOR 0x03
|
||||
|
||||
int MCD_getVersion(char **longVersion)
|
||||
{
|
||||
*longVersion = MCD_versionString;
|
||||
return((MCD_REV_MAJOR << 8) | MCD_REV_MINOR);
|
||||
}
|
||||
/********************** End of MCD_getVersion() *********************/
|
||||
|
||||
/********************************************************************/
|
||||
/* Private version of memcpy()
|
||||
* Note that everything this is used for is longword-aligned.
|
||||
*/
|
||||
static void MCD_memcpy (int *dest, int *src, u32 size)
|
||||
{
|
||||
u32 i;
|
||||
|
||||
for (i = 0; i < size; i += sizeof(int), dest++, src++)
|
||||
*dest = *src;
|
||||
}
|
||||
/********************************************************************/
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,224 +0,0 @@
|
||||
/*
|
||||
* File: MCD_tasksInit.c
|
||||
* Purpose: Functions for initializing variable tables of different
|
||||
* types of tasks.
|
||||
*
|
||||
* Notes:
|
||||
*/
|
||||
|
||||
/*
|
||||
* Do not edit!
|
||||
*/
|
||||
|
||||
#include "MCD_dma.h"
|
||||
|
||||
extern dmaRegs *MCD_dmaBar;
|
||||
|
||||
|
||||
/*
|
||||
* Task 0
|
||||
*/
|
||||
|
||||
void MCD_startDmaChainNoEu(int *currBD, short srcIncr, short destIncr, int xferSize, short xferSizeIncr, int *cSave, volatile TaskTableEntry *taskTable, int channel)
|
||||
{
|
||||
|
||||
MCD_SET_VAR(taskTable+channel, 2, (u32)currBD); /* var[2] */
|
||||
MCD_SET_VAR(taskTable+channel, 25, (u32)(0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */
|
||||
MCD_SET_VAR(taskTable+channel, 24, (u32)(0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */
|
||||
MCD_SET_VAR(taskTable+channel, 11, (u32)xferSize); /* var[11] */
|
||||
MCD_SET_VAR(taskTable+channel, 26, (u32)(0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */
|
||||
MCD_SET_VAR(taskTable+channel, 0, (u32)cSave); /* var[0] */
|
||||
MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */
|
||||
MCD_SET_VAR(taskTable+channel, 3, (u32)0x00000000); /* var[3] */
|
||||
MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */
|
||||
MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */
|
||||
MCD_SET_VAR(taskTable+channel, 6, (u32)0x00000000); /* var[6] */
|
||||
MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */
|
||||
MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */
|
||||
MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000000); /* var[9] */
|
||||
MCD_SET_VAR(taskTable+channel, 10, (u32)0x00000000); /* var[10] */
|
||||
MCD_SET_VAR(taskTable+channel, 12, (u32)0x00000000); /* var[12] */
|
||||
MCD_SET_VAR(taskTable+channel, 13, (u32)0x80000000); /* var[13] */
|
||||
MCD_SET_VAR(taskTable+channel, 14, (u32)0x00000010); /* var[14] */
|
||||
MCD_SET_VAR(taskTable+channel, 15, (u32)0x00000004); /* var[15] */
|
||||
MCD_SET_VAR(taskTable+channel, 16, (u32)0x08000000); /* var[16] */
|
||||
MCD_SET_VAR(taskTable+channel, 27, (u32)0x00000000); /* inc[3] */
|
||||
MCD_SET_VAR(taskTable+channel, 28, (u32)0x80000000); /* inc[4] */
|
||||
MCD_SET_VAR(taskTable+channel, 29, (u32)0x80000001); /* inc[5] */
|
||||
MCD_SET_VAR(taskTable+channel, 30, (u32)0x40000000); /* inc[6] */
|
||||
|
||||
/* Set the task's Enable bit in its Task Control Register */
|
||||
MCD_dmaBar->taskControl[channel] |= (u16)0x8000;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Task 1
|
||||
*/
|
||||
|
||||
void MCD_startDmaSingleNoEu(char *srcAddr, short srcIncr, char *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel)
|
||||
{
|
||||
|
||||
MCD_SET_VAR(taskTable+channel, 7, (u32)srcAddr); /* var[7] */
|
||||
MCD_SET_VAR(taskTable+channel, 25, (u32)(0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */
|
||||
MCD_SET_VAR(taskTable+channel, 2, (u32)destAddr); /* var[2] */
|
||||
MCD_SET_VAR(taskTable+channel, 24, (u32)(0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */
|
||||
MCD_SET_VAR(taskTable+channel, 3, (u32)dmaSize); /* var[3] */
|
||||
MCD_SET_VAR(taskTable+channel, 26, (u32)(0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */
|
||||
MCD_SET_VAR(taskTable+channel, 5, (u32)flags); /* var[5] */
|
||||
MCD_SET_VAR(taskTable+channel, 1, (u32)currBD); /* var[1] */
|
||||
MCD_SET_VAR(taskTable+channel, 0, (u32)cSave); /* var[0] */
|
||||
MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */
|
||||
MCD_SET_VAR(taskTable+channel, 6, (u32)0x00000000); /* var[6] */
|
||||
MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */
|
||||
MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000004); /* var[9] */
|
||||
MCD_SET_VAR(taskTable+channel, 10, (u32)0x08000000); /* var[10] */
|
||||
MCD_SET_VAR(taskTable+channel, 27, (u32)0x00000000); /* inc[3] */
|
||||
MCD_SET_VAR(taskTable+channel, 28, (u32)0x80000001); /* inc[4] */
|
||||
MCD_SET_VAR(taskTable+channel, 29, (u32)0x40000000); /* inc[5] */
|
||||
|
||||
/* Set the task's Enable bit in its Task Control Register */
|
||||
MCD_dmaBar->taskControl[channel] |= (u16)0x8000;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Task 2
|
||||
*/
|
||||
|
||||
void MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr, int xferSize, short xferSizeIncr, int *cSave, volatile TaskTableEntry *taskTable, int channel)
|
||||
{
|
||||
|
||||
MCD_SET_VAR(taskTable+channel, 3, (u32)currBD); /* var[3] */
|
||||
MCD_SET_VAR(taskTable+channel, 25, (u32)(0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */
|
||||
MCD_SET_VAR(taskTable+channel, 24, (u32)(0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */
|
||||
MCD_SET_VAR(taskTable+channel, 12, (u32)xferSize); /* var[12] */
|
||||
MCD_SET_VAR(taskTable+channel, 26, (u32)(0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */
|
||||
MCD_SET_VAR(taskTable+channel, 0, (u32)cSave); /* var[0] */
|
||||
MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */
|
||||
MCD_SET_VAR(taskTable+channel, 2, (u32)0x00000000); /* var[2] */
|
||||
MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */
|
||||
MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */
|
||||
MCD_SET_VAR(taskTable+channel, 6, (u32)0x00000000); /* var[6] */
|
||||
MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */
|
||||
MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */
|
||||
MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000000); /* var[9] */
|
||||
MCD_SET_VAR(taskTable+channel, 10, (u32)0x00000000); /* var[10] */
|
||||
MCD_SET_VAR(taskTable+channel, 11, (u32)0x00000000); /* var[11] */
|
||||
MCD_SET_VAR(taskTable+channel, 13, (u32)0x00000000); /* var[13] */
|
||||
MCD_SET_VAR(taskTable+channel, 14, (u32)0x80000000); /* var[14] */
|
||||
MCD_SET_VAR(taskTable+channel, 15, (u32)0x00000010); /* var[15] */
|
||||
MCD_SET_VAR(taskTable+channel, 16, (u32)0x00000001); /* var[16] */
|
||||
MCD_SET_VAR(taskTable+channel, 17, (u32)0x00000004); /* var[17] */
|
||||
MCD_SET_VAR(taskTable+channel, 18, (u32)0x08000000); /* var[18] */
|
||||
MCD_SET_VAR(taskTable+channel, 27, (u32)0x00000000); /* inc[3] */
|
||||
MCD_SET_VAR(taskTable+channel, 28, (u32)0x80000000); /* inc[4] */
|
||||
MCD_SET_VAR(taskTable+channel, 29, (u32)0xc0000000); /* inc[5] */
|
||||
MCD_SET_VAR(taskTable+channel, 30, (u32)0x80000001); /* inc[6] */
|
||||
MCD_SET_VAR(taskTable+channel, 31, (u32)0x40000000); /* inc[7] */
|
||||
|
||||
/* Set the task's Enable bit in its Task Control Register */
|
||||
MCD_dmaBar->taskControl[channel] |= (u16)0x8000;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Task 3
|
||||
*/
|
||||
|
||||
void MCD_startDmaSingleEu(char *srcAddr, short srcIncr, char *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel)
|
||||
{
|
||||
|
||||
MCD_SET_VAR(taskTable+channel, 8, (u32)srcAddr); /* var[8] */
|
||||
MCD_SET_VAR(taskTable+channel, 25, (u32)(0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */
|
||||
MCD_SET_VAR(taskTable+channel, 3, (u32)destAddr); /* var[3] */
|
||||
MCD_SET_VAR(taskTable+channel, 24, (u32)(0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */
|
||||
MCD_SET_VAR(taskTable+channel, 4, (u32)dmaSize); /* var[4] */
|
||||
MCD_SET_VAR(taskTable+channel, 26, (u32)(0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */
|
||||
MCD_SET_VAR(taskTable+channel, 6, (u32)flags); /* var[6] */
|
||||
MCD_SET_VAR(taskTable+channel, 2, (u32)currBD); /* var[2] */
|
||||
MCD_SET_VAR(taskTable+channel, 0, (u32)cSave); /* var[0] */
|
||||
MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */
|
||||
MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */
|
||||
MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */
|
||||
MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000000); /* var[9] */
|
||||
MCD_SET_VAR(taskTable+channel, 10, (u32)0x00000001); /* var[10] */
|
||||
MCD_SET_VAR(taskTable+channel, 11, (u32)0x00000004); /* var[11] */
|
||||
MCD_SET_VAR(taskTable+channel, 12, (u32)0x08000000); /* var[12] */
|
||||
MCD_SET_VAR(taskTable+channel, 27, (u32)0x00000000); /* inc[3] */
|
||||
MCD_SET_VAR(taskTable+channel, 28, (u32)0xc0000000); /* inc[4] */
|
||||
MCD_SET_VAR(taskTable+channel, 29, (u32)0x80000000); /* inc[5] */
|
||||
MCD_SET_VAR(taskTable+channel, 30, (u32)0x80000001); /* inc[6] */
|
||||
MCD_SET_VAR(taskTable+channel, 31, (u32)0x40000000); /* inc[7] */
|
||||
|
||||
/* Set the task's Enable bit in its Task Control Register */
|
||||
MCD_dmaBar->taskControl[channel] |= (u16)0x8000;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Task 4
|
||||
*/
|
||||
|
||||
void MCD_startDmaENetRcv(char *bDBase, char *currBD, char *rcvFifoPtr, volatile TaskTableEntry *taskTable, int channel)
|
||||
{
|
||||
|
||||
MCD_SET_VAR(taskTable+channel, 0, (u32)bDBase); /* var[0] */
|
||||
MCD_SET_VAR(taskTable+channel, 3, (u32)currBD); /* var[3] */
|
||||
MCD_SET_VAR(taskTable+channel, 6, (u32)rcvFifoPtr); /* var[6] */
|
||||
MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */
|
||||
MCD_SET_VAR(taskTable+channel, 2, (u32)0x00000000); /* var[2] */
|
||||
MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */
|
||||
MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */
|
||||
MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */
|
||||
MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */
|
||||
MCD_SET_VAR(taskTable+channel, 9, (u32)0x0000ffff); /* var[9] */
|
||||
MCD_SET_VAR(taskTable+channel, 10, (u32)0x30000000); /* var[10] */
|
||||
MCD_SET_VAR(taskTable+channel, 11, (u32)0x0fffffff); /* var[11] */
|
||||
MCD_SET_VAR(taskTable+channel, 12, (u32)0x00000008); /* var[12] */
|
||||
MCD_SET_VAR(taskTable+channel, 24, (u32)0x00000000); /* inc[0] */
|
||||
MCD_SET_VAR(taskTable+channel, 25, (u32)0x60000000); /* inc[1] */
|
||||
MCD_SET_VAR(taskTable+channel, 26, (u32)0x20000004); /* inc[2] */
|
||||
MCD_SET_VAR(taskTable+channel, 27, (u32)0x40000000); /* inc[3] */
|
||||
|
||||
/* Set the task's Enable bit in its Task Control Register */
|
||||
MCD_dmaBar->taskControl[channel] |= (u16)0x8000;
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Task 5
|
||||
*/
|
||||
|
||||
void MCD_startDmaENetXmit(char *bDBase, char *currBD, char *xmitFifoPtr, volatile TaskTableEntry *taskTable, int channel)
|
||||
{
|
||||
|
||||
MCD_SET_VAR(taskTable+channel, 0, (u32)bDBase); /* var[0] */
|
||||
MCD_SET_VAR(taskTable+channel, 3, (u32)currBD); /* var[3] */
|
||||
MCD_SET_VAR(taskTable+channel, 11, (u32)xmitFifoPtr); /* var[11] */
|
||||
MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */
|
||||
MCD_SET_VAR(taskTable+channel, 2, (u32)0x00000000); /* var[2] */
|
||||
MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */
|
||||
MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */
|
||||
MCD_SET_VAR(taskTable+channel, 6, (u32)0x00000000); /* var[6] */
|
||||
MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */
|
||||
MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */
|
||||
MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000000); /* var[9] */
|
||||
MCD_SET_VAR(taskTable+channel, 10, (u32)0x00000000); /* var[10] */
|
||||
MCD_SET_VAR(taskTable+channel, 12, (u32)0x00000000); /* var[12] */
|
||||
MCD_SET_VAR(taskTable+channel, 13, (u32)0x0000ffff); /* var[13] */
|
||||
MCD_SET_VAR(taskTable+channel, 14, (u32)0xffffffff); /* var[14] */
|
||||
MCD_SET_VAR(taskTable+channel, 15, (u32)0x00000004); /* var[15] */
|
||||
MCD_SET_VAR(taskTable+channel, 16, (u32)0x00000008); /* var[16] */
|
||||
MCD_SET_VAR(taskTable+channel, 24, (u32)0x00000000); /* inc[0] */
|
||||
MCD_SET_VAR(taskTable+channel, 25, (u32)0x60000000); /* inc[1] */
|
||||
MCD_SET_VAR(taskTable+channel, 26, (u32)0x40000000); /* inc[2] */
|
||||
MCD_SET_VAR(taskTable+channel, 27, (u32)0xc000fffc); /* inc[3] */
|
||||
MCD_SET_VAR(taskTable+channel, 28, (u32)0xe0000004); /* inc[4] */
|
||||
MCD_SET_VAR(taskTable+channel, 29, (u32)0x80000000); /* inc[5] */
|
||||
MCD_SET_VAR(taskTable+channel, 30, (u32)0x4000ffff); /* inc[6] */
|
||||
MCD_SET_VAR(taskTable+channel, 31, (u32)0xe0000001); /* inc[7] */
|
||||
|
||||
/* Set the task's Enable bit in its Task Control Register */
|
||||
MCD_dmaBar->taskControl[channel] |= (u16)0x8000;
|
||||
}
|
||||
@@ -1,674 +0,0 @@
|
||||
/*
|
||||
* dma.c
|
||||
*
|
||||
*
|
||||
* This file is part of BaS_gcc.
|
||||
*
|
||||
* BaS_gcc is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* BaS_gcc is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* Created on: 26.02.2013
|
||||
* Author: Markus Fröschle
|
||||
*/
|
||||
|
||||
#include "dma.h"
|
||||
#include <MCD_dma.h>
|
||||
#include "mcd_initiators.h"
|
||||
#include "bas_printf.h"
|
||||
#include "bas_string.h"
|
||||
#include "cache.h"
|
||||
#include "exceptions.h"
|
||||
|
||||
#if defined(MACHINE_FIREBEE)
|
||||
#include "firebee.h"
|
||||
#elif defined(MACHINE_M5484LITE)
|
||||
#include "m5484l.h"
|
||||
#elif defined(MACHINE_M54455)
|
||||
#include "m54455.h"
|
||||
#else
|
||||
#error "unknown machine!"
|
||||
#endif /* MACHINE_FIREBEE */
|
||||
|
||||
// #define DEBUG
|
||||
#include "debug.h"
|
||||
|
||||
extern char _SYS_SRAM[];
|
||||
#define SYS_SRAM &_SYS_SRAM[0]
|
||||
|
||||
struct dma_channel
|
||||
{
|
||||
int req;
|
||||
void (*handler)(void);
|
||||
};
|
||||
|
||||
static char used_reqs[32] =
|
||||
{
|
||||
DMA_ALWAYS, DMA_DSPI_RXFIFO, DMA_DSPI_TXFIFO, DMA_DREQ0,
|
||||
DMA_PSC0_RX, DMA_PSC0_TX, DMA_USB_EP0, DMA_USB_EP1,
|
||||
DMA_USB_EP2, DMA_USB_EP3, DMA_PCI_TX, DMA_PCI_RX,
|
||||
DMA_PSC1_RX, DMA_PSC1_TX, DMA_I2C_RX, DMA_I2C_TX,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0,
|
||||
0, 0, 0, 0
|
||||
};
|
||||
|
||||
static struct dma_channel dma_channel[NCHANNELS] =
|
||||
{
|
||||
{-1, NULL}, {-1, NULL}, {-1, NULL}, {-1, NULL},
|
||||
{-1, NULL}, {-1, NULL}, {-1, NULL}, {-1, NULL},
|
||||
{-1, NULL}, {-1, NULL}, {-1, NULL}, {-1, NULL},
|
||||
{-1, NULL}, {-1, NULL}, {-1, NULL}, {-1, NULL},
|
||||
};
|
||||
|
||||
/*
|
||||
* Enable all DMA interrupts
|
||||
*
|
||||
*/
|
||||
void dma_irq_enable(void)
|
||||
{
|
||||
/* Unmask all task interrupts */
|
||||
MCF_DMA_DIMR = 0;
|
||||
|
||||
/* Clear the interrupt pending register */
|
||||
MCF_DMA_DIPR = 0;
|
||||
|
||||
dbg("DMA task interrupts unmasked.\r\n");
|
||||
}
|
||||
|
||||
/*
|
||||
* Disable all DMA interrupts
|
||||
*/
|
||||
void dma_irq_disable(void)
|
||||
{
|
||||
/* Mask all task interrupts */
|
||||
MCF_DMA_DIMR = (uint32_t) ~0;
|
||||
|
||||
/* Clear any pending task interrupts */
|
||||
MCF_DMA_DIPR = (uint32_t) ~0;
|
||||
|
||||
/* Mask the DMA interrupt in the interrupt controller */
|
||||
MCF_INTC_IMRH |= MCF_INTC_IMRH_INT_MASK48;
|
||||
|
||||
dbg("DMA interrupts masked and disabled\r\n");
|
||||
}
|
||||
|
||||
int dma_set_initiator(int initiator)
|
||||
{
|
||||
switch (initiator)
|
||||
{
|
||||
/* these initiators are always active */
|
||||
case DMA_ALWAYS:
|
||||
case DMA_DSPI_RXFIFO:
|
||||
case DMA_DSPI_TXFIFO:
|
||||
case DMA_DREQ0:
|
||||
case DMA_PSC0_RX:
|
||||
case DMA_PSC0_TX:
|
||||
case DMA_USB_EP0:
|
||||
case DMA_USB_EP1:
|
||||
case DMA_USB_EP2:
|
||||
case DMA_USB_EP3:
|
||||
case DMA_PCI_TX:
|
||||
case DMA_PCI_RX:
|
||||
case DMA_PSC1_RX:
|
||||
case DMA_I2C_RX:
|
||||
case DMA_I2C_TX:
|
||||
break;
|
||||
|
||||
case DMA_FEC0_RX:
|
||||
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC16(3)) | MCF_DMA_IMCR_IMC16_FEC0RX;
|
||||
used_reqs[16] = DMA_FEC0_RX;
|
||||
break;
|
||||
|
||||
case DMA_FEC0_TX:
|
||||
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC17(3)) | MCF_DMA_IMCR_IMC17_FEC0TX;
|
||||
used_reqs[17] = DMA_FEC0_TX;
|
||||
break;
|
||||
|
||||
case DMA_FEC1_RX:
|
||||
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC20(3)) | MCF_DMA_IMCR_IMC20_FEC1RX;
|
||||
used_reqs[20] = DMA_FEC1_RX;
|
||||
break;
|
||||
|
||||
case DMA_FEC1_TX:
|
||||
if (used_reqs[21] == 0)
|
||||
{
|
||||
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC21(3)) | MCF_DMA_IMCR_IMC21_FEC1TX;
|
||||
used_reqs[21] = DMA_FEC1_TX;
|
||||
}
|
||||
else if (used_reqs[25] == 0)
|
||||
{
|
||||
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC25(3)) | MCF_DMA_IMCR_IMC25_FEC1TX;
|
||||
used_reqs[25] = DMA_FEC1_TX;
|
||||
}
|
||||
else if (used_reqs[31] == 0)
|
||||
{
|
||||
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC31(3)) | MCF_DMA_IMCR_IMC31_FEC1TX;
|
||||
used_reqs[31] = DMA_FEC1_TX;
|
||||
}
|
||||
else /* No empty slots */
|
||||
{
|
||||
err("no free slot found\r\n");
|
||||
|
||||
return 1;
|
||||
}
|
||||
break;
|
||||
|
||||
case DMA_DREQ1:
|
||||
if (used_reqs[29] == 0)
|
||||
{
|
||||
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC29(3)) | MCF_DMA_IMCR_IMC29_DREQ1;
|
||||
used_reqs[29] = DMA_DREQ1;
|
||||
}
|
||||
else if (used_reqs[21] == 0)
|
||||
{
|
||||
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC21(3)) | MCF_DMA_IMCR_IMC21_DREQ1;
|
||||
used_reqs[21] = DMA_DREQ1;
|
||||
}
|
||||
else /* No empty slots */
|
||||
{
|
||||
err("no free slot\r\n");
|
||||
|
||||
return 1;
|
||||
}
|
||||
break;
|
||||
|
||||
case DMA_CTM0:
|
||||
if (used_reqs[24] == 0)
|
||||
{
|
||||
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC24(3)) | MCF_DMA_IMCR_IMC24_CTM0;
|
||||
used_reqs[24] = DMA_CTM0;
|
||||
}
|
||||
else /* No empty slots */
|
||||
{
|
||||
err("no free slot\r\n");
|
||||
|
||||
return 1;
|
||||
}
|
||||
break;
|
||||
|
||||
case DMA_CTM1:
|
||||
if (used_reqs[25] == 0)
|
||||
{
|
||||
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC25(3)) | MCF_DMA_IMCR_IMC25_CTM1;
|
||||
used_reqs[25] = DMA_CTM1;
|
||||
}
|
||||
else /* No empty slots */
|
||||
{
|
||||
err("no free slot\r\n");
|
||||
|
||||
return 1;
|
||||
}
|
||||
break;
|
||||
|
||||
case DMA_CTM2:
|
||||
if (used_reqs[26] == 0)
|
||||
{
|
||||
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC26(3)) | MCF_DMA_IMCR_IMC26_CTM2;
|
||||
used_reqs[26] = DMA_CTM2;
|
||||
}
|
||||
else /* No empty slots */
|
||||
{
|
||||
err("no free slot\r\n");
|
||||
|
||||
return 1;
|
||||
}
|
||||
break;
|
||||
|
||||
case DMA_CTM3:
|
||||
if (used_reqs[27] == 0)
|
||||
{
|
||||
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC27(3)) | MCF_DMA_IMCR_IMC27_CTM3;
|
||||
used_reqs[27] = DMA_CTM3;
|
||||
}
|
||||
else /* No empty slots */
|
||||
{
|
||||
err("no free slot\r\n");
|
||||
|
||||
return 1;
|
||||
}
|
||||
break;
|
||||
|
||||
case DMA_CTM4:
|
||||
if (used_reqs[28] == 0)
|
||||
{
|
||||
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC28(3)) | MCF_DMA_IMCR_IMC28_CTM4;
|
||||
used_reqs[28] = DMA_CTM4;
|
||||
}
|
||||
else /* No empty slots */
|
||||
{
|
||||
err("no free slot\r\n");
|
||||
|
||||
return 1;
|
||||
}
|
||||
break;
|
||||
|
||||
case DMA_CTM5:
|
||||
if (used_reqs[29] == 0)
|
||||
{
|
||||
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC29(3)) | MCF_DMA_IMCR_IMC29_CTM5;
|
||||
used_reqs[29] = DMA_CTM5;
|
||||
}
|
||||
else /* No empty slots */
|
||||
{
|
||||
err("no free slot\r\n");
|
||||
|
||||
return 1;
|
||||
}
|
||||
break;
|
||||
|
||||
case DMA_CTM6:
|
||||
if (used_reqs[30] == 0)
|
||||
{
|
||||
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC30(3)) | MCF_DMA_IMCR_IMC30_CTM6;
|
||||
used_reqs[30] = DMA_CTM6;
|
||||
}
|
||||
else /* No empty slots */
|
||||
{
|
||||
err("no free slot\r\n");
|
||||
|
||||
return 1;
|
||||
}
|
||||
break;
|
||||
|
||||
case DMA_CTM7:
|
||||
if (used_reqs[31] == 0)
|
||||
{
|
||||
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC31(3)) | MCF_DMA_IMCR_IMC31_CTM7;
|
||||
used_reqs[31] = DMA_CTM7;
|
||||
}
|
||||
else /* No empty slots */
|
||||
{
|
||||
err("no free slot\r\n");
|
||||
|
||||
return 1;
|
||||
}
|
||||
break;
|
||||
|
||||
case DMA_USBEP4:
|
||||
if (used_reqs[26] == 0)
|
||||
{
|
||||
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC26(3)) | MCF_DMA_IMCR_IMC26_USBEP4;
|
||||
used_reqs[26] = DMA_USBEP4;
|
||||
}
|
||||
else /* No empty slots */
|
||||
{
|
||||
err("no free slot\r\n");
|
||||
|
||||
return 1;
|
||||
}
|
||||
break;
|
||||
|
||||
case DMA_USBEP5:
|
||||
if (used_reqs[27] == 0)
|
||||
{
|
||||
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC27(3)) | MCF_DMA_IMCR_IMC27_USBEP5;
|
||||
used_reqs[27] = DMA_USBEP5;
|
||||
}
|
||||
else /* No empty slots */
|
||||
{
|
||||
err("no free slot\r\n");
|
||||
|
||||
return 1;
|
||||
}
|
||||
break;
|
||||
|
||||
case DMA_USBEP6:
|
||||
if (used_reqs[28] == 0)
|
||||
{
|
||||
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC28(3)) | MCF_DMA_IMCR_IMC28_USBEP6;
|
||||
used_reqs[28] = DMA_USBEP6;
|
||||
}
|
||||
else /* No empty slots */
|
||||
{
|
||||
err("no free slot\r\n");
|
||||
return 1;
|
||||
}
|
||||
break;
|
||||
|
||||
case DMA_PSC2_RX:
|
||||
if (used_reqs[28] == 0)
|
||||
{
|
||||
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC28(3)) | MCF_DMA_IMCR_IMC28_PSC2RX;
|
||||
used_reqs[28] = DMA_PSC2_RX; }
|
||||
else /* No empty slots */
|
||||
{
|
||||
err("no free slot\r\n");
|
||||
|
||||
return 1;
|
||||
}
|
||||
break;
|
||||
|
||||
case DMA_PSC2_TX:
|
||||
if (used_reqs[29] == 0)
|
||||
{
|
||||
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC29(3)) | MCF_DMA_IMCR_IMC29_PSC2TX;
|
||||
used_reqs[29] = DMA_PSC2_TX;
|
||||
}
|
||||
else /* No empty slots */
|
||||
{
|
||||
err("no free slot\r\n");
|
||||
|
||||
return 1;
|
||||
}
|
||||
break;
|
||||
|
||||
case DMA_PSC3_RX:
|
||||
if (used_reqs[30] == 0)
|
||||
{
|
||||
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC30(3)) | MCF_DMA_IMCR_IMC30_PSC3RX;
|
||||
used_reqs[30] = DMA_PSC3_RX;
|
||||
}
|
||||
else /* No empty slots */
|
||||
{
|
||||
err("no free slot\r\n");
|
||||
|
||||
return 1;
|
||||
}
|
||||
break;
|
||||
|
||||
case DMA_PSC3_TX:
|
||||
if (used_reqs[31] == 0)
|
||||
{
|
||||
MCF_DMA_IMCR = (MCF_DMA_IMCR & ~MCF_DMA_IMCR_IMC31(3)) | MCF_DMA_IMCR_IMC31_PSC3TX;
|
||||
used_reqs[31] = DMA_PSC3_TX;
|
||||
}
|
||||
else /* No empty slots */
|
||||
{
|
||||
err("no free slot\r\n");
|
||||
|
||||
return 1;
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
{
|
||||
err("don't know what to do\r\n");
|
||||
|
||||
return 1;
|
||||
}
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Return the initiator number for the given requestor
|
||||
*
|
||||
* Parameters:
|
||||
* requestor Initiator/Requestor identifier
|
||||
*
|
||||
* Return Value:
|
||||
* The initiator number (0-31) if initiator has been assigned
|
||||
* 0 (always initiator) otherwise
|
||||
*/
|
||||
uint32_t dma_get_initiator(int requestor)
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0; i < sizeof(used_reqs); ++i)
|
||||
{
|
||||
if (used_reqs[i] == requestor)
|
||||
return i;
|
||||
}
|
||||
err("no initiator found for requestor %d\r\n", requestor);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* Remove the given initiator from the active list
|
||||
*
|
||||
* Parameters:
|
||||
* requestor Initiator/Requestor identifier
|
||||
*/
|
||||
void dma_free_initiator(int requestor)
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
for (i = 16; i < sizeof(used_reqs); ++i)
|
||||
{
|
||||
if (used_reqs[i] == requestor)
|
||||
{
|
||||
used_reqs[i] = 0;
|
||||
break;
|
||||
}
|
||||
}
|
||||
dbg("DMA requestor %d freed\r\n", requestor);
|
||||
}
|
||||
|
||||
/*
|
||||
* Attempt to find an available channel and mark it as used
|
||||
*
|
||||
* Parameters:
|
||||
* requestor Initiator/Requestor identifier
|
||||
*
|
||||
* Return Value:
|
||||
* First available channel or -1 if they are all occupied
|
||||
*/
|
||||
int dma_set_channel(int requestor, void (*handler)(void))
|
||||
{
|
||||
int i;
|
||||
|
||||
/* Check to see if this requestor is already assigned to a channel */
|
||||
dbg("check if requestor %d is already assigned to a channel\r\n", requestor);
|
||||
if ((i = dma_get_channel(requestor)) != -1)
|
||||
{
|
||||
return i;
|
||||
}
|
||||
|
||||
for (i = 0; i < NCHANNELS; ++i)
|
||||
{
|
||||
if (dma_channel[i].req == -1)
|
||||
{
|
||||
dma_channel[i].req = requestor;
|
||||
dma_channel[i].handler = handler;
|
||||
dbg("assigned channel %d to requestor %d\r\n", i, requestor);
|
||||
return i;
|
||||
}
|
||||
}
|
||||
err("no free DMA channel found for requestor %d\r\n", requestor);
|
||||
|
||||
/* All channels taken */
|
||||
return -1;
|
||||
}
|
||||
|
||||
void dma_clear_channel(int channel)
|
||||
{
|
||||
if(channel >= 0 && channel < NCHANNELS)
|
||||
{
|
||||
dma_channel[channel].req = -1;
|
||||
dma_channel[channel].handler = NULL;
|
||||
dbg("cleared DMA channel %d\r\n", channel);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Return the channel being initiated by the given requestor
|
||||
*
|
||||
* Parameters:
|
||||
* requestor Initiator/Requestor identifier
|
||||
*
|
||||
* Return Value:
|
||||
* Channel that the requestor is controlling or -1 if hasn't been
|
||||
* activated
|
||||
*/
|
||||
int dma_get_channel(int requestor)
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0; i < NCHANNELS; ++i)
|
||||
{
|
||||
if (dma_channel[i].req == requestor)
|
||||
return i;
|
||||
}
|
||||
dbg("no channel occupied by requestor %d\r\n", requestor);
|
||||
return -1;
|
||||
}
|
||||
|
||||
/*
|
||||
* Remove the channel being initiated by the given requestor from
|
||||
* the active list
|
||||
*
|
||||
* Parameters:
|
||||
* requestor Initiator/Requestor identifier
|
||||
*/
|
||||
void dma_free_channel(int requestor)
|
||||
{
|
||||
uint32_t i;
|
||||
|
||||
for (i = 0; i < NCHANNELS; ++i)
|
||||
{
|
||||
if (dma_channel[i].req == requestor)
|
||||
{
|
||||
dma_channel[i].req = -1;
|
||||
dma_channel[i].handler = NULL;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* This is the catch-all interrupt handler for the mult-channel DMA
|
||||
*/
|
||||
bool dma_interrupt_handler(void *arg1, void *arg2)
|
||||
{
|
||||
int i, interrupts;
|
||||
uint32_t ipl;
|
||||
|
||||
ipl = set_ipl(7); /* do not disturb */
|
||||
|
||||
/*
|
||||
* Determine which interrupt(s) triggered by AND'ing the
|
||||
* pending interrupts with those that aren't masked.
|
||||
*/
|
||||
interrupts = MCF_DMA_DIPR & ~MCF_DMA_DIMR;
|
||||
|
||||
/* Make sure we are here for a reason */
|
||||
if (interrupts == 0)
|
||||
{
|
||||
err("not DMA interrupt!\r\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
dbg("");
|
||||
/* Clear the interrupt in the pending register */
|
||||
MCF_DMA_DIPR = interrupts;
|
||||
|
||||
for (i = 0; i < 16; ++i, interrupts >>= 1)
|
||||
{
|
||||
if (interrupts & 0x1)
|
||||
{
|
||||
/* If there is a handler, call it */
|
||||
if (dma_channel[i].handler != NULL)
|
||||
{
|
||||
dbg("call handler for DMA channel %d (%p)\r\n", i, dma_channel[i].handler);
|
||||
dma_channel[i].handler();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
set_ipl(ipl);
|
||||
|
||||
return true; /* handled */
|
||||
}
|
||||
/********************************************************************/
|
||||
|
||||
void *dma_memcpy(void *dst, void *src, size_t n)
|
||||
{
|
||||
int ret;
|
||||
|
||||
#ifdef DBG_DMA
|
||||
int32_t time;
|
||||
int32_t start;
|
||||
int32_t end;
|
||||
|
||||
start = MCF_SLT0_SCNT;
|
||||
#endif /* DBG_DMA */
|
||||
|
||||
ret = MCD_startDma(1, src, 4, dst, 4, n, 4, DMA_ALWAYS, 0, MCD_SINGLE_DMA, 0);
|
||||
if (ret == MCD_OK)
|
||||
{
|
||||
dbg("DMA on channel 1 successfully started\r\n");
|
||||
}
|
||||
|
||||
do
|
||||
{
|
||||
ret = MCD_dmaStatus(1);
|
||||
#ifdef _NOT_USED_ /* suppress annoying printout for now */
|
||||
switch (ret)
|
||||
{
|
||||
case MCD_NO_DMA:
|
||||
xprintf("MCD_NO_DMA: no DMA active on this channel\r\n");
|
||||
return NULL;
|
||||
break;
|
||||
case MCD_IDLE:
|
||||
xprintf("MCD_IDLE: DMA defined but not active (initiator not ready)\r\n");
|
||||
break;
|
||||
case MCD_RUNNING:
|
||||
xprintf("MCD_RUNNING: DMA active and working on this channel\r\n");
|
||||
break;
|
||||
case MCD_PAUSED:
|
||||
xprintf("MCD_PAUSED: DMA defined and enabled, but currently paused\r\n");
|
||||
break;
|
||||
case MCD_HALTED:
|
||||
xprintf("MCD_HALTED: DMA killed\r\n");
|
||||
return NULL;
|
||||
break;
|
||||
case MCD_DONE:
|
||||
xprintf("MCD_DONE: DMA finished\r\n");
|
||||
break;
|
||||
case MCD_CHANNEL_INVALID:
|
||||
xprintf("MCD_CHANNEL_INVALID: invalid DMA channel\r\n");
|
||||
return NULL;
|
||||
break;
|
||||
default:
|
||||
xprintf("unknown DMA status %d\r\n", ret);
|
||||
break;
|
||||
}
|
||||
#endif
|
||||
} while (ret != MCD_DONE);
|
||||
|
||||
#ifdef DBG_DMA
|
||||
end = MCF_SLT0_SCNT;
|
||||
time = (start - end) / (SYSCLK / 1000) / 1000;
|
||||
dbg("took %d ms (%f Mbytes/second)\r\n", time, n / (float) time / 1000.0);
|
||||
#endif /* DBG_DMA */
|
||||
|
||||
return dst;
|
||||
}
|
||||
|
||||
int dma_init(void)
|
||||
{
|
||||
int i;
|
||||
int res;
|
||||
|
||||
dbg("MCD DMA API initialization: ");
|
||||
res = MCD_initDma((dmaRegs *) &_MBAR[0x8000], SYS_SRAM, MCD_RELOC_TASKS | MCD_COMM_PREFETCH_EN);
|
||||
if (res != MCD_OK)
|
||||
{
|
||||
err("DMA API initialization failed (0x%x)\r\n", res);
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* make sure dma_channel array is properly initialized
|
||||
*/
|
||||
for (i = 0; i < NCHANNELS; i++)
|
||||
{
|
||||
dma_channel[i].req = -1;
|
||||
dma_channel[i].handler = NULL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -1,17 +0,0 @@
|
||||
#!/usr/local/bin/bdmctrl -D2 -v9 -d9
|
||||
#
|
||||
# firebee board initialization for bdmctrl
|
||||
#
|
||||
open $1
|
||||
|
||||
dump-register D0
|
||||
#dump-register ASID
|
||||
dump-register ACR0
|
||||
dump-register ACR1
|
||||
#dump-register ACR2
|
||||
#dump-register ACR3
|
||||
dump-register SR
|
||||
dump-register CACR
|
||||
# dump-register RAMBAR1
|
||||
# dump-register RAMBAR2
|
||||
dump-register MBAR
|
||||
@@ -1,679 +0,0 @@
|
||||
/*
|
||||
* basflash.c
|
||||
*
|
||||
*
|
||||
* This file is part of BaS_gcc.
|
||||
*
|
||||
* BaS_gcc is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* BaS_gcc is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* Created on: 26.02.2013
|
||||
* Author: Markus Fröschle
|
||||
*/
|
||||
|
||||
#include <bas_types.h>
|
||||
#include "bas_printf.h"
|
||||
#include "bas_string.h"
|
||||
#include "diskio.h"
|
||||
#include "ff.h"
|
||||
#include "s19reader.h"
|
||||
|
||||
#if defined(MACHINE_FIREBEE)
|
||||
#include "firebee.h"
|
||||
#elif defined(MACHINE_M5484LITE)
|
||||
#include "m5484l.h"
|
||||
#elif defined(MACHINE_M54455)
|
||||
#include "m54455.h"
|
||||
#else
|
||||
error unknown machine!
|
||||
#endif /* MACHINE_M5484LITE */
|
||||
|
||||
#define AMD_FLASH_BUS_SHIFT 1
|
||||
#define AMD_FLASH_CELL volatile uint16_t
|
||||
#define AMD_FLASH_CELL_BYTES 2
|
||||
#define AMD_FLASH_CELL_MASK 0x1
|
||||
#define AMD_FLASH_CMD_DATA(x) ((uint16_t) x)
|
||||
|
||||
struct amd_flash_sector_info
|
||||
{
|
||||
uint32_t size; /* sector size in bytes */
|
||||
uint32_t offset; /* offset from base of device */
|
||||
};
|
||||
|
||||
/*
|
||||
* AM29LV640D flash layout (bottom boot as used in the Firebee)
|
||||
*/
|
||||
static struct amd_flash_sector_info sector[] =
|
||||
{
|
||||
{ 8 * 1024, 0x00000000 }, /* SA0 */
|
||||
{ 8 * 1024, 0x00008000 }, /* SA1 */
|
||||
{ 8 * 1024, 0x00010000 }, /* SA2 */
|
||||
{ 8 * 1024, 0x00018000 }, /* SA3 */
|
||||
{ 8 * 1024, 0x00020000 }, /* SA4 */
|
||||
{ 8 * 1024, 0x00028000 }, /* SA5 */
|
||||
{ 8 * 1024, 0x00030000 }, /* SA6 */
|
||||
{ 8 * 1024, 0x00038000 }, /* SA7 */
|
||||
{ 8 * 1024, 0x00040000 }, /* SA8 */
|
||||
{ 64 * 1024, 0x00048000 }, /* SA9 */
|
||||
{ 64 * 1024, 0x00050000 }, /* SA10 */
|
||||
{ 64 * 1024, 0x00058000 }, /* SA11 */
|
||||
{ 64 * 1024, 0x00060000 }, /* SA12 */
|
||||
{ 64 * 1024, 0x00068000 }, /* SA13 */
|
||||
{ 64 * 1024, 0x00070000 }, /* SA14 */
|
||||
{ 64 * 1024, 0x00078000 }, /* SA15 */
|
||||
{ 64 * 1024, 0x00080000 }, /* SA16 */
|
||||
{ 64 * 1024, 0x00088000 }, /* SA17 */
|
||||
{ 64 * 1024, 0x00090000 }, /* SA18 */
|
||||
{ 64 * 1024, 0x00098000 }, /* SA19 */
|
||||
{ 64 * 1024, 0x000a0000 }, /* SA20 */
|
||||
{ 64 * 1024, 0x000a8000 }, /* SA21 */
|
||||
{ 64 * 1024, 0x000b0000 }, /* SA22 */
|
||||
{ 64 * 1024, 0x000b8000 }, /* SA23 */
|
||||
{ 64 * 1024, 0x000c0000 }, /* SA24 */
|
||||
{ 64 * 1024, 0x000c8000 }, /* SA25 */
|
||||
{ 64 * 1024, 0x000d0000 }, /* SA26 */
|
||||
{ 64 * 1024, 0x000d8000 }, /* SA27 */
|
||||
{ 64 * 1024, 0x000e0000 }, /* SA28 */
|
||||
{ 64 * 1024, 0x000e8000 }, /* SA29 */
|
||||
{ 64 * 1024, 0x000f0000 }, /* SA30 */
|
||||
{ 64 * 1024, 0x000f8000 }, /* SA31 */
|
||||
{ 64 * 1024, 0x00100000 }, /* SA32 */
|
||||
{ 64 * 1024, 0x00108000 }, /* SA32 */
|
||||
{ 64 * 1024, 0x00110000 }, /* SA34 */
|
||||
{ 64 * 1024, 0x00118000 }, /* SA35 */
|
||||
{ 64 * 1024, 0x00120000 }, /* SA36 */
|
||||
{ 64 * 1024, 0x00128000 }, /* SA37 */
|
||||
{ 64 * 1024, 0x00130000 }, /* SA38 */
|
||||
{ 64 * 1024, 0x00138000 }, /* SA39 */
|
||||
{ 64 * 1024, 0x00140000 }, /* SA40 */
|
||||
{ 64 * 1024, 0x00148000 }, /* SA41 */
|
||||
{ 64 * 1024, 0x00150000 }, /* SA42 */
|
||||
{ 64 * 1024, 0x00158000 }, /* SA43 */
|
||||
{ 64 * 1024, 0x00160000 }, /* SA44 */
|
||||
{ 64 * 1024, 0x00168000 }, /* SA45 */
|
||||
{ 64 * 1024, 0x00170000 }, /* SA46 */
|
||||
{ 64 * 1024, 0x00178000 }, /* SA47 */
|
||||
{ 64 * 1024, 0x00180000 }, /* SA48 */
|
||||
{ 64 * 1024, 0x00188000 }, /* SA49 */
|
||||
{ 64 * 1024, 0x00190000 }, /* SA50 */
|
||||
{ 64 * 1024, 0x00198000 }, /* SA51 */
|
||||
{ 64 * 1024, 0x001a0000 }, /* SA52 */
|
||||
{ 64 * 1024, 0x001a8000 }, /* SA53 */
|
||||
{ 64 * 1024, 0x001b0000 }, /* SA54 */
|
||||
{ 64 * 1024, 0x001b8000 }, /* SA55 */
|
||||
{ 64 * 1024, 0x001c0000 }, /* SA56 */
|
||||
{ 64 * 1024, 0x001c8000 }, /* SA57 */
|
||||
{ 64 * 1024, 0x001d0000 }, /* SA58 */
|
||||
{ 64 * 1024, 0x001d8000 }, /* SA59 */
|
||||
{ 64 * 1024, 0x001e0000 }, /* SA60 */
|
||||
{ 64 * 1024, 0x001e8000 }, /* SA61 */
|
||||
{ 64 * 1024, 0x001f0000 }, /* SA62 */
|
||||
{ 64 * 1024, 0x001f8000 }, /* SA63 */
|
||||
{ 64 * 1024, 0x00200000 }, /* SA64 */
|
||||
{ 64 * 1024, 0x00208000 }, /* SA65 */
|
||||
{ 64 * 1024, 0x00210000 }, /* SA66 */
|
||||
{ 64 * 1024, 0x00218000 }, /* SA67 */
|
||||
{ 64 * 1024, 0x00220000 }, /* SA68 */
|
||||
{ 64 * 1024, 0x00228000 }, /* SA69 */
|
||||
{ 64 * 1024, 0x00230000 }, /* SA70 */
|
||||
{ 64 * 1024, 0x00238000 }, /* SA71 */
|
||||
{ 64 * 1024, 0x00240000 }, /* SA72 */
|
||||
{ 64 * 1024, 0x00248000 }, /* SA73 */
|
||||
{ 64 * 1024, 0x00250000 }, /* SA74 */
|
||||
{ 64 * 1024, 0x00258000 }, /* SA75 */
|
||||
{ 64 * 1024, 0x00260000 }, /* SA76 */
|
||||
{ 64 * 1024, 0x00268000 }, /* SA77 */
|
||||
{ 64 * 1024, 0x00270000 }, /* SA78 */
|
||||
{ 64 * 1024, 0x00278000 }, /* SA79 */
|
||||
{ 64 * 1024, 0x00280000 }, /* SA80 */
|
||||
{ 64 * 1024, 0x00288000 }, /* SA81 */
|
||||
{ 64 * 1024, 0x00290000 }, /* SA82 */
|
||||
{ 64 * 1024, 0x00298000 }, /* SA83 */
|
||||
{ 64 * 1024, 0x002a0000 }, /* SA84 */
|
||||
{ 64 * 1024, 0x002a8000 }, /* SA85 */
|
||||
{ 64 * 1024, 0x002b0000 }, /* SA86 */
|
||||
{ 64 * 1024, 0x002b8000 }, /* SA87 */
|
||||
{ 64 * 1024, 0x002c0000 }, /* SA88 */
|
||||
{ 64 * 1024, 0x002c8000 }, /* SA89 */
|
||||
{ 64 * 1024, 0x002d0000 }, /* SA90 */
|
||||
{ 64 * 1024, 0x002d8000 }, /* SA91 */
|
||||
{ 64 * 1024, 0x002e0000 }, /* SA92 */
|
||||
{ 64 * 1024, 0x002e8000 }, /* SA93 */
|
||||
{ 64 * 1024, 0x002f0000 }, /* SA94 */
|
||||
{ 64 * 1024, 0x002f8000 }, /* SA95 */
|
||||
{ 64 * 1024, 0x00300000 }, /* SA96 */
|
||||
{ 64 * 1024, 0x00308000 }, /* SA97 */
|
||||
{ 64 * 1024, 0x00310000 }, /* SA98 */
|
||||
{ 64 * 1024, 0x00318000 }, /* SA99 */
|
||||
{ 64 * 1024, 0x00320000 }, /* SA100 */
|
||||
{ 64 * 1024, 0x00328000 }, /* SA101 */
|
||||
{ 64 * 1024, 0x00330000 }, /* SA102 */
|
||||
{ 64 * 1024, 0x00338000 }, /* SA103 */
|
||||
{ 64 * 1024, 0x00340000 }, /* SA104 */
|
||||
{ 64 * 1024, 0x00348000 }, /* SA105 */
|
||||
{ 64 * 1024, 0x00350000 }, /* SA106 */
|
||||
{ 64 * 1024, 0x00358000 }, /* SA107 */
|
||||
{ 64 * 1024, 0x00360000 }, /* SA108 */
|
||||
{ 64 * 1024, 0x00368000 }, /* SA109 */
|
||||
{ 64 * 1024, 0x00370000 }, /* SA110 */
|
||||
{ 64 * 1024, 0x00378000 }, /* SA111 */
|
||||
{ 64 * 1024, 0x00380000 }, /* SA112 */
|
||||
{ 64 * 1024, 0x00388000 }, /* SA113 */
|
||||
{ 64 * 1024, 0x00390000 }, /* SA114 */
|
||||
{ 64 * 1024, 0x00398000 }, /* SA115 */
|
||||
{ 64 * 1024, 0x003a0000 }, /* SA116 */
|
||||
{ 64 * 1024, 0x003a8000 }, /* SA117 */
|
||||
{ 64 * 1024, 0x003b0000 }, /* SA118 */
|
||||
{ 64 * 1024, 0x003b8000 }, /* SA119 */
|
||||
{ 64 * 1024, 0x003c0000 }, /* SA120 */
|
||||
{ 64 * 1024, 0x003c8000 }, /* SA121 */
|
||||
{ 64 * 1024, 0x003d0000 }, /* SA122 */
|
||||
{ 64 * 1024, 0x003d8000 }, /* SA123 */
|
||||
{ 64 * 1024, 0x003e0000 }, /* SA124 */
|
||||
{ 64 * 1024, 0x003e8000 }, /* SA125 */
|
||||
{ 64 * 1024, 0x003f0000 }, /* SA126 */
|
||||
{ 64 * 1024, 0x003f8000 }, /* SA127 */
|
||||
};
|
||||
|
||||
static const int AMD_FLASH_SECTORS = sizeof(sector) / sizeof(struct amd_flash_sector_info);
|
||||
|
||||
#define SOFFSET(n) (sector[n].offset)
|
||||
#define SADDR(n) (SOFFSET(n) >> AMD_FLASH_BUS_SHIFT)
|
||||
#define SSIZE(n) (sector[n].size)
|
||||
|
||||
#define AMD_FLASH_DEVICES 1
|
||||
|
||||
static AMD_FLASH_CELL *pFlash;
|
||||
|
||||
typedef struct romram
|
||||
{
|
||||
uint32_t flash_address;
|
||||
uint32_t ram_address;
|
||||
char *name;
|
||||
} ROMRAM;
|
||||
|
||||
#if defined(MACHINE_FIREBEE)
|
||||
static const struct romram flash_areas[] =
|
||||
{
|
||||
{ 0xe0600000, 0x00e00000, "EmuTOS" }, /* EmuTOS */
|
||||
{ 0xe0400000, 0x00e00000, "FireTOS" }, /* FireTOS */
|
||||
{ 0xe0700000, 0x00e00000, "FPGA" }, /* FPGA config */
|
||||
};
|
||||
static const int num_flash_areas = sizeof(flash_areas) / sizeof(struct romram);
|
||||
#endif
|
||||
|
||||
#define FLASH_ADDRESS 0xe0000000
|
||||
|
||||
/*
|
||||
* erase a flash sector
|
||||
*
|
||||
* sector_num is the index into the sector table above.
|
||||
*
|
||||
* FIXME: need to disable data cache to ensure proper operation
|
||||
*/
|
||||
void amd_flash_sector_erase(int n)
|
||||
{
|
||||
volatile AMD_FLASH_CELL status;
|
||||
|
||||
pFlash[0x555] = AMD_FLASH_CMD_DATA(0xAA);
|
||||
pFlash[0x2AA] = AMD_FLASH_CMD_DATA(0x55);
|
||||
pFlash[0x555] = AMD_FLASH_CMD_DATA(0x80);
|
||||
pFlash[0x555] = AMD_FLASH_CMD_DATA(0xAA);
|
||||
pFlash[0x2AA] = AMD_FLASH_CMD_DATA(0x55);
|
||||
pFlash[SADDR(n)] = AMD_FLASH_CMD_DATA(0x30);
|
||||
|
||||
do
|
||||
status = pFlash[SADDR(n)];
|
||||
while ((status & AMD_FLASH_CMD_DATA(0x80)) != AMD_FLASH_CMD_DATA(0x80));
|
||||
|
||||
/*
|
||||
* Place device in read mode
|
||||
*/
|
||||
pFlash[0] = AMD_FLASH_CMD_DATA(0xAA);
|
||||
pFlash[0] = AMD_FLASH_CMD_DATA(0x55);
|
||||
pFlash[0] = AMD_FLASH_CMD_DATA(0xF0);
|
||||
}
|
||||
|
||||
int amd_flash_erase(void *start, int bytes, void (*putchar)(int))
|
||||
{
|
||||
int i, ebytes = 0;
|
||||
|
||||
if (bytes == 0)
|
||||
return 0;
|
||||
|
||||
for (i = 0; i < AMD_FLASH_SECTORS; i++)
|
||||
{
|
||||
if (start >= (void *)((void *) pFlash + SOFFSET(i)) &&
|
||||
start <= (void *)((void *) pFlash + SOFFSET(i) + (SSIZE(i) - 1)))
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
while (ebytes < bytes)
|
||||
{
|
||||
if (putchar != NULL)
|
||||
{
|
||||
putchar('.');
|
||||
}
|
||||
amd_flash_sector_erase(i);
|
||||
ebytes += SSIZE(i);
|
||||
i++;
|
||||
}
|
||||
|
||||
if (putchar != NULL)
|
||||
{
|
||||
putchar(10); /* LF */
|
||||
putchar(13); /* CR */
|
||||
}
|
||||
|
||||
return ebytes;
|
||||
}
|
||||
|
||||
void amd_flash_program_cell(AMD_FLASH_CELL *dst, AMD_FLASH_CELL data)
|
||||
{
|
||||
volatile AMD_FLASH_CELL status;
|
||||
int retry;
|
||||
|
||||
pFlash[0x555] = AMD_FLASH_CMD_DATA(0xAA);
|
||||
pFlash[0x2AA] = AMD_FLASH_CMD_DATA(0x55);
|
||||
pFlash[0x555] = AMD_FLASH_CMD_DATA(0xA0);
|
||||
*dst = data;
|
||||
|
||||
/*
|
||||
* Wait for program operation to finish
|
||||
* (Data# Polling Algorithm)
|
||||
*/
|
||||
retry = 0;
|
||||
while (1)
|
||||
{
|
||||
status = *dst;
|
||||
if ((status & AMD_FLASH_CMD_DATA(0x80)) ==
|
||||
(data & AMD_FLASH_CMD_DATA(0x80)))
|
||||
{
|
||||
break;
|
||||
}
|
||||
if (status & AMD_FLASH_CMD_DATA(0x20))
|
||||
{
|
||||
status = *dst;
|
||||
if ((status & AMD_FLASH_CMD_DATA(0x80)) ==
|
||||
(data & AMD_FLASH_CMD_DATA(0x80)))
|
||||
{
|
||||
break;
|
||||
}
|
||||
if (++retry > 1024)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
int amd_flash_program(void *dest, void *source, int bytes, int erase, void (*func)(void), void (*putchar)(int))
|
||||
{
|
||||
AMD_FLASH_CELL *src, *dst;
|
||||
int hashi=1,hashj=0;
|
||||
char hash[5];
|
||||
|
||||
hash[0]=8; /* Backspace */
|
||||
hash[1]=124;/* "|" */
|
||||
hash[2]=47; /* "/" */
|
||||
hash[3]=45; /* "-" */
|
||||
hash[4]=92; /* "\" */
|
||||
|
||||
src = (AMD_FLASH_CELL *)source;
|
||||
dst = (AMD_FLASH_CELL *)dest;
|
||||
|
||||
/*
|
||||
* Place device in read mode
|
||||
*/
|
||||
pFlash[0] = AMD_FLASH_CMD_DATA(0xAA);
|
||||
pFlash[0] = AMD_FLASH_CMD_DATA(0x55);
|
||||
pFlash[0] = AMD_FLASH_CMD_DATA(0xF0);
|
||||
|
||||
/*
|
||||
* Erase device if necessary
|
||||
*/
|
||||
if (erase)
|
||||
{
|
||||
amd_flash_erase(dest, bytes, putchar);
|
||||
}
|
||||
|
||||
/*
|
||||
* Program device
|
||||
*/
|
||||
while (bytes > 0)
|
||||
{
|
||||
amd_flash_program_cell(dst,*src);
|
||||
|
||||
/* Verify Write */
|
||||
if (*dst == *src)
|
||||
{
|
||||
bytes -= AMD_FLASH_CELL_BYTES;
|
||||
*dst++, *src++;
|
||||
|
||||
if ((putchar != NULL))
|
||||
{
|
||||
/* Hash marks to indicate progress */
|
||||
if (hashj == 0x1000)
|
||||
{
|
||||
hashj = -1;
|
||||
putchar(hash[0]);
|
||||
putchar(hash[hashi]);
|
||||
|
||||
hashi++;
|
||||
if (hashi == 5)
|
||||
{
|
||||
hashi=1;
|
||||
}
|
||||
|
||||
}
|
||||
hashj++;
|
||||
}
|
||||
}
|
||||
else
|
||||
break;
|
||||
}
|
||||
|
||||
/*
|
||||
* Place device in read mode
|
||||
*/
|
||||
pFlash[0] = AMD_FLASH_CMD_DATA(0xAA);
|
||||
pFlash[0] = AMD_FLASH_CMD_DATA(0x55);
|
||||
pFlash[0] = AMD_FLASH_CMD_DATA(0xF0);
|
||||
|
||||
if (putchar != NULL)
|
||||
{
|
||||
putchar(hash[0]);
|
||||
}
|
||||
|
||||
/*
|
||||
* If a function was passed in, call it now
|
||||
*/
|
||||
if ((func != NULL))
|
||||
{
|
||||
func();
|
||||
}
|
||||
|
||||
return ((int)src - (int)source);
|
||||
}
|
||||
|
||||
/*
|
||||
* this callback just does nothing besides returning OK. Meant to do a dry run over the file to check its integrity
|
||||
*/
|
||||
static err_t simulate()
|
||||
{
|
||||
err_t ret = OK;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static err_t flash(uint8_t *dst, uint8_t *src, uint32_t length)
|
||||
{
|
||||
err_t ret = OK;
|
||||
|
||||
/* TODO: do the actual flash */
|
||||
amd_flash_program(dst, src, length, 1, NULL, xputchar);
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* this callback verifies the data against the S-record file contents after a write to destination
|
||||
*/
|
||||
static err_t verify(uint8_t *dst, uint8_t *src, size_t length)
|
||||
{
|
||||
uint8_t *end = src + length;
|
||||
|
||||
do
|
||||
{
|
||||
if (*src++ != *dst++)
|
||||
return FAIL;
|
||||
} while (src < end);
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
void srec_flash(char *flash_filename)
|
||||
{
|
||||
DRESULT res;
|
||||
FRESULT fres;
|
||||
FATFS fs;
|
||||
FIL file;
|
||||
err_t err;
|
||||
void *start_address;
|
||||
uint32_t length;
|
||||
|
||||
res = disk_status(0);
|
||||
if (res == RES_OK)
|
||||
{
|
||||
fres = f_mount(0, &fs);
|
||||
if (fres == FR_OK)
|
||||
{
|
||||
if ((fres = f_open(&file, flash_filename, FA_READ) != FR_OK))
|
||||
{
|
||||
xprintf("flasher file %s not present on disk\r\n",
|
||||
flash_filename);
|
||||
}
|
||||
else
|
||||
{
|
||||
f_close(&file);
|
||||
|
||||
/* first pass: parse and check for inconsistencies */
|
||||
xprintf("check file integrity: ");
|
||||
err = read_srecords(flash_filename, &start_address, &length,
|
||||
simulate);
|
||||
if (err == OK)
|
||||
{
|
||||
xprintf("OK.\r\nerase flash area (from %p, length 0x%lx): ",
|
||||
start_address, length);
|
||||
err = amd_flash_erase(start_address, length, xputchar);
|
||||
|
||||
/* next pass: copy data to destination */
|
||||
xprintf("OK.\r\flash data: ");
|
||||
err = read_srecords(flash_filename, &start_address, &length, flash);
|
||||
if (err == OK)
|
||||
{
|
||||
/* next pass: verify data */
|
||||
xprintf("OK.\r\nverify data: ");
|
||||
err = read_srecords(flash_filename, &start_address,
|
||||
&length, verify);
|
||||
if (err == OK)
|
||||
{
|
||||
typedef void void_func(void);
|
||||
void_func *func;
|
||||
|
||||
xprintf("OK.\r\n");
|
||||
|
||||
xprintf(
|
||||
"target successfully written and verified. Start address: %p\r\n",
|
||||
start_address);
|
||||
|
||||
func = (void_func *) start_address;
|
||||
(*func)();
|
||||
}
|
||||
else
|
||||
{
|
||||
xprintf("failed\r\n");
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
xprintf("failed\r\n");
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
xprintf("failed\r\n");
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
// xprintf("could not mount FAT FS\r\n");
|
||||
}
|
||||
f_mount(0, 0L);
|
||||
}
|
||||
else
|
||||
{
|
||||
// xprintf("could not initialize SD card\r\n");
|
||||
}
|
||||
}
|
||||
|
||||
err_t srec_load(char *flash_filename)
|
||||
{
|
||||
FRESULT fres;
|
||||
FIL file;
|
||||
err_t err;
|
||||
void *start_address;
|
||||
uint32_t length;
|
||||
|
||||
if ((fres = f_open(&file, flash_filename, FA_READ) != FR_OK))
|
||||
{
|
||||
xprintf("flasher file %s not present on disk\r\n", flash_filename);
|
||||
}
|
||||
else
|
||||
{
|
||||
f_close(&file);
|
||||
|
||||
/* first pass: parse and check for inconsistencies */
|
||||
xprintf("check file integrity: ");
|
||||
err = read_srecords(flash_filename, &start_address, &length, simulate);
|
||||
if (err == OK)
|
||||
{
|
||||
/* next pass: copy data to destination */
|
||||
xprintf("OK (start address = %p).\r\ncopy/flash data: ", start_address);
|
||||
err = read_srecords(flash_filename, &start_address, &length, srec_memcpy);
|
||||
if (err == OK)
|
||||
{
|
||||
/* next pass: verify data */
|
||||
xprintf("OK (start address = %p).\r\nverify data: ", start_address);
|
||||
err = read_srecords(flash_filename, &start_address, &length, verify);
|
||||
if (err == OK)
|
||||
{
|
||||
typedef void void_func(void);
|
||||
void_func *func;
|
||||
|
||||
xprintf("OK.\r\n");
|
||||
xprintf(
|
||||
"target successfully written and verified. Start address: %p\r\n",
|
||||
start_address);
|
||||
|
||||
func = (void_func *) start_address;
|
||||
(*func)();
|
||||
}
|
||||
else
|
||||
{
|
||||
xprintf("failed\r\n");
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
xprintf("failed\r\n");
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
xprintf("failed\r\n");
|
||||
}
|
||||
}
|
||||
return OK;
|
||||
}
|
||||
|
||||
void basflash(void)
|
||||
{
|
||||
// const char *basflash_str = "\\BASFLASH";
|
||||
const char *bastest_str = "\\BASTEST";
|
||||
DRESULT res;
|
||||
FRESULT fres;
|
||||
FATFS fs;
|
||||
|
||||
xprintf("\r\nHello from BASFLASH.S19!\r\n\r\n");
|
||||
|
||||
/*
|
||||
* read \BASTEST\ folder contents (search for .S19-files). If found load them to their final destination
|
||||
* (after BaS has copied them, not their flash location) and return.
|
||||
*
|
||||
* Files located in the BASTEST-folder thus override those in flash. Useful for testing before flashing
|
||||
*/
|
||||
res = disk_status(0);
|
||||
xprintf("disk_status(0) = %d\r\n", res);
|
||||
if (res == RES_OK)
|
||||
{
|
||||
fres = f_mount(0, &fs);
|
||||
xprintf("f_mount() = %d\r\n", fres);
|
||||
if (fres == FR_OK)
|
||||
{
|
||||
DIR directory;
|
||||
|
||||
fres = f_opendir(&directory, bastest_str);
|
||||
xprintf("f_opendir() = %d\r\n", fres);
|
||||
if (fres == FR_OK)
|
||||
{
|
||||
FILINFO fileinfo;
|
||||
|
||||
fres = f_readdir(&directory, &fileinfo);
|
||||
xprintf("f_readdir() = %d\r\n", fres);
|
||||
while (fres == FR_OK)
|
||||
{
|
||||
const char *srec_ext = ".S19";
|
||||
char path[30];
|
||||
|
||||
if (fileinfo.fname[0] != '\0') /* found a file */
|
||||
{
|
||||
xprintf("check file %s (%s == %s ?)\r\n",
|
||||
fileinfo.fname,
|
||||
&fileinfo.fname[strlen(fileinfo.fname) - 4],
|
||||
srec_ext);
|
||||
if (strlen(fileinfo.fname) >= 4
|
||||
&& strncmp(
|
||||
&fileinfo.fname[strlen(fileinfo.fname)
|
||||
- 4], srec_ext, 4) == 0) /* we have a .S19 file */
|
||||
{
|
||||
/*
|
||||
* build path + filename
|
||||
*/
|
||||
strcpy(path, bastest_str);
|
||||
strcat(path, "\\");
|
||||
strncat(path, fileinfo.fname, 13);
|
||||
|
||||
xprintf("loading file %s\r\n", path);
|
||||
/*
|
||||
* load file
|
||||
*/
|
||||
srec_load(path);
|
||||
// {
|
||||
// xprintf("failed to load file %s\r\n", path);
|
||||
// error handling
|
||||
// }
|
||||
}
|
||||
}
|
||||
else
|
||||
break; /* exit if no file found */
|
||||
fres = f_readdir(&directory, &fileinfo);
|
||||
xprintf("f_readdir() = %d\r\n", fres);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
xprintf("f_opendir %s failed with error code %d\r\n",
|
||||
bastest_str, fres);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
// xprintf("could not mount FAT FS\r\n");
|
||||
}
|
||||
f_mount(0, 0L); /* unmount SD card */
|
||||
}
|
||||
}
|
||||
@@ -1,43 +0,0 @@
|
||||
/*
|
||||
* basflash_start.c
|
||||
*
|
||||
*
|
||||
* This file is part of BaS_gcc.
|
||||
*
|
||||
* BaS_gcc is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* BaS_gcc is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* Created on: 26.02.2013
|
||||
* Author: Markus Fröschle
|
||||
*/
|
||||
|
||||
#include <bas_types.h>
|
||||
|
||||
#define STACKSIZE 16384
|
||||
static uint32_t ownstack[STACKSIZE];
|
||||
static uint32_t *stackptr = &ownstack[STACKSIZE - 1];
|
||||
|
||||
/*
|
||||
* setup our own stack in SDRAM to prevent clashing BaS's in SRAM (size limited).
|
||||
*/
|
||||
void startup(void)
|
||||
{
|
||||
static uint32_t oldstack;
|
||||
|
||||
void basflash(void);
|
||||
__asm__ __volatile__("move.l sp,%0\n\t" : "=g"(oldstack) : :);
|
||||
__asm__ __volatile__("move.l %0,sp\n\t" : : "g"(stackptr) : );
|
||||
basflash();
|
||||
__asm__ __volatile__("move.l %0,sp\n\t" : : "g"(oldstack) : "sp");
|
||||
(void) stackptr; /* make compiler happy about unused variables */
|
||||
}
|
||||
@@ -1,383 +0,0 @@
|
||||
#include <stddef.h>
|
||||
#include "bas_types.h"
|
||||
|
||||
#if defined(MACHINE_FIREBEE)
|
||||
#include "firebee.h"
|
||||
#elif defined(MACHINE_M5484LITE)
|
||||
#include "m5484l.h"
|
||||
#endif /* MACHINE_FIREBEE */
|
||||
|
||||
#define AMD_FLASH_BUS_SHIFT 1
|
||||
#define AMD_FLASH_CELL volatile uint16_t
|
||||
#define AMD_FLASH_CELL_BYTES 2
|
||||
#define AMD_FLASH_CELL_MASK 0x1
|
||||
#define AMD_FLASH_CMD_DATA(x) ((uint16_t) x)
|
||||
|
||||
struct amd_flash_sector_info
|
||||
{
|
||||
uint32_t size; /* sector size in bytes */
|
||||
uint32_t offset; /* offset from base of device */
|
||||
};
|
||||
|
||||
/*
|
||||
* AM29LV640D flash layout (bottom boot as used in the Firebee )
|
||||
*/
|
||||
static struct amd_flash_sector_info sector[] =
|
||||
{
|
||||
{ 8 * 1024, 0x00000000 }, /* SA0 */
|
||||
{ 8 * 1024, 0x00008000 }, /* SA1 */
|
||||
{ 8 * 1024, 0x00010000 }, /* SA2 */
|
||||
{ 8 * 1024, 0x00018000 }, /* SA3 */
|
||||
{ 8 * 1024, 0x00020000 }, /* SA4 */
|
||||
{ 8 * 1024, 0x00028000 }, /* SA5 */
|
||||
{ 8 * 1024, 0x00030000 }, /* SA6 */
|
||||
{ 8 * 1024, 0x00038000 }, /* SA7 */
|
||||
{ 8 * 1024, 0x00040000 }, /* SA8 */
|
||||
{ 64 * 1024, 0x00048000 }, /* SA9 */
|
||||
{ 64 * 1024, 0x00050000 }, /* SA10 */
|
||||
{ 64 * 1024, 0x00058000 }, /* SA11 */
|
||||
{ 64 * 1024, 0x00060000 }, /* SA12 */
|
||||
{ 64 * 1024, 0x00068000 }, /* SA13 */
|
||||
{ 64 * 1024, 0x00070000 }, /* SA14 */
|
||||
{ 64 * 1024, 0x00078000 }, /* SA15 */
|
||||
{ 64 * 1024, 0x00080000 }, /* SA16 */
|
||||
{ 64 * 1024, 0x00088000 }, /* SA17 */
|
||||
{ 64 * 1024, 0x00090000 }, /* SA18 */
|
||||
{ 64 * 1024, 0x00098000 }, /* SA19 */
|
||||
{ 64 * 1024, 0x000a0000 }, /* SA20 */
|
||||
{ 64 * 1024, 0x000a8000 }, /* SA21 */
|
||||
{ 64 * 1024, 0x000b0000 }, /* SA22 */
|
||||
{ 64 * 1024, 0x000b8000 }, /* SA23 */
|
||||
{ 64 * 1024, 0x000c0000 }, /* SA24 */
|
||||
{ 64 * 1024, 0x000c8000 }, /* SA25 */
|
||||
{ 64 * 1024, 0x000d0000 }, /* SA26 */
|
||||
{ 64 * 1024, 0x000d8000 }, /* SA27 */
|
||||
{ 64 * 1024, 0x000e0000 }, /* SA28 */
|
||||
{ 64 * 1024, 0x000e8000 }, /* SA29 */
|
||||
{ 64 * 1024, 0x000f0000 }, /* SA30 */
|
||||
{ 64 * 1024, 0x000f8000 }, /* SA31 */
|
||||
{ 64 * 1024, 0x00100000 }, /* SA32 */
|
||||
{ 64 * 1024, 0x00108000 }, /* SA32 */
|
||||
{ 64 * 1024, 0x00110000 }, /* SA34 */
|
||||
{ 64 * 1024, 0x00118000 }, /* SA35 */
|
||||
{ 64 * 1024, 0x00120000 }, /* SA36 */
|
||||
{ 64 * 1024, 0x00128000 }, /* SA37 */
|
||||
{ 64 * 1024, 0x00130000 }, /* SA38 */
|
||||
{ 64 * 1024, 0x00138000 }, /* SA39 */
|
||||
{ 64 * 1024, 0x00140000 }, /* SA40 */
|
||||
{ 64 * 1024, 0x00148000 }, /* SA41 */
|
||||
{ 64 * 1024, 0x00150000 }, /* SA42 */
|
||||
{ 64 * 1024, 0x00158000 }, /* SA43 */
|
||||
{ 64 * 1024, 0x00160000 }, /* SA44 */
|
||||
{ 64 * 1024, 0x00168000 }, /* SA45 */
|
||||
{ 64 * 1024, 0x00170000 }, /* SA46 */
|
||||
{ 64 * 1024, 0x00178000 }, /* SA47 */
|
||||
{ 64 * 1024, 0x00180000 }, /* SA48 */
|
||||
{ 64 * 1024, 0x00188000 }, /* SA49 */
|
||||
{ 64 * 1024, 0x00190000 }, /* SA50 */
|
||||
{ 64 * 1024, 0x00198000 }, /* SA51 */
|
||||
{ 64 * 1024, 0x001a0000 }, /* SA52 */
|
||||
{ 64 * 1024, 0x001a8000 }, /* SA53 */
|
||||
{ 64 * 1024, 0x001b0000 }, /* SA54 */
|
||||
{ 64 * 1024, 0x001b8000 }, /* SA55 */
|
||||
{ 64 * 1024, 0x001c0000 }, /* SA56 */
|
||||
{ 64 * 1024, 0x001c8000 }, /* SA57 */
|
||||
{ 64 * 1024, 0x001d0000 }, /* SA58 */
|
||||
{ 64 * 1024, 0x001d8000 }, /* SA59 */
|
||||
{ 64 * 1024, 0x001e0000 }, /* SA60 */
|
||||
{ 64 * 1024, 0x001e8000 }, /* SA61 */
|
||||
{ 64 * 1024, 0x001f0000 }, /* SA62 */
|
||||
{ 64 * 1024, 0x001f8000 }, /* SA63 */
|
||||
{ 64 * 1024, 0x00200000 }, /* SA64 */
|
||||
{ 64 * 1024, 0x00208000 }, /* SA65 */
|
||||
{ 64 * 1024, 0x00210000 }, /* SA66 */
|
||||
{ 64 * 1024, 0x00218000 }, /* SA67 */
|
||||
{ 64 * 1024, 0x00220000 }, /* SA68 */
|
||||
{ 64 * 1024, 0x00228000 }, /* SA69 */
|
||||
{ 64 * 1024, 0x00230000 }, /* SA70 */
|
||||
{ 64 * 1024, 0x00238000 }, /* SA71 */
|
||||
{ 64 * 1024, 0x00240000 }, /* SA72 */
|
||||
{ 64 * 1024, 0x00248000 }, /* SA73 */
|
||||
{ 64 * 1024, 0x00250000 }, /* SA74 */
|
||||
{ 64 * 1024, 0x00258000 }, /* SA75 */
|
||||
{ 64 * 1024, 0x00260000 }, /* SA76 */
|
||||
{ 64 * 1024, 0x00268000 }, /* SA77 */
|
||||
{ 64 * 1024, 0x00270000 }, /* SA78 */
|
||||
{ 64 * 1024, 0x00278000 }, /* SA79 */
|
||||
{ 64 * 1024, 0x00280000 }, /* SA80 */
|
||||
{ 64 * 1024, 0x00288000 }, /* SA81 */
|
||||
{ 64 * 1024, 0x00290000 }, /* SA82 */
|
||||
{ 64 * 1024, 0x00298000 }, /* SA83 */
|
||||
{ 64 * 1024, 0x002a0000 }, /* SA84 */
|
||||
{ 64 * 1024, 0x002a8000 }, /* SA85 */
|
||||
{ 64 * 1024, 0x002b0000 }, /* SA86 */
|
||||
{ 64 * 1024, 0x002b8000 }, /* SA87 */
|
||||
{ 64 * 1024, 0x002c0000 }, /* SA88 */
|
||||
{ 64 * 1024, 0x002c8000 }, /* SA89 */
|
||||
{ 64 * 1024, 0x002d0000 }, /* SA90 */
|
||||
{ 64 * 1024, 0x002d8000 }, /* SA91 */
|
||||
{ 64 * 1024, 0x002e0000 }, /* SA92 */
|
||||
{ 64 * 1024, 0x002e8000 }, /* SA93 */
|
||||
{ 64 * 1024, 0x002f0000 }, /* SA94 */
|
||||
{ 64 * 1024, 0x002f8000 }, /* SA95 */
|
||||
{ 64 * 1024, 0x00300000 }, /* SA96 */
|
||||
{ 64 * 1024, 0x00308000 }, /* SA97 */
|
||||
{ 64 * 1024, 0x00310000 }, /* SA98 */
|
||||
{ 64 * 1024, 0x00318000 }, /* SA99 */
|
||||
{ 64 * 1024, 0x00320000 }, /* SA100 */
|
||||
{ 64 * 1024, 0x00328000 }, /* SA101 */
|
||||
{ 64 * 1024, 0x00330000 }, /* SA102 */
|
||||
{ 64 * 1024, 0x00338000 }, /* SA103 */
|
||||
{ 64 * 1024, 0x00340000 }, /* SA104 */
|
||||
{ 64 * 1024, 0x00348000 }, /* SA105 */
|
||||
{ 64 * 1024, 0x00350000 }, /* SA106 */
|
||||
{ 64 * 1024, 0x00358000 }, /* SA107 */
|
||||
{ 64 * 1024, 0x00360000 }, /* SA108 */
|
||||
{ 64 * 1024, 0x00368000 }, /* SA109 */
|
||||
{ 64 * 1024, 0x00370000 }, /* SA110 */
|
||||
{ 64 * 1024, 0x00378000 }, /* SA111 */
|
||||
{ 64 * 1024, 0x00380000 }, /* SA112 */
|
||||
{ 64 * 1024, 0x00388000 }, /* SA113 */
|
||||
{ 64 * 1024, 0x00390000 }, /* SA114 */
|
||||
{ 64 * 1024, 0x00398000 }, /* SA115 */
|
||||
{ 64 * 1024, 0x003a0000 }, /* SA116 */
|
||||
{ 64 * 1024, 0x003a8000 }, /* SA117 */
|
||||
{ 64 * 1024, 0x003b0000 }, /* SA118 */
|
||||
{ 64 * 1024, 0x003b8000 }, /* SA119 */
|
||||
{ 64 * 1024, 0x003c0000 }, /* SA120 */
|
||||
{ 64 * 1024, 0x003c8000 }, /* SA121 */
|
||||
{ 64 * 1024, 0x003d0000 }, /* SA122 */
|
||||
{ 64 * 1024, 0x003d8000 }, /* SA123 */
|
||||
{ 64 * 1024, 0x003e0000 }, /* SA124 */
|
||||
{ 64 * 1024, 0x003e8000 }, /* SA125 */
|
||||
{ 64 * 1024, 0x003f0000 }, /* SA126 */
|
||||
{ 64 * 1024, 0x003f8000 }, /* SA127 */
|
||||
};
|
||||
|
||||
static const int AMD_FLASH_SECTORS = sizeof(sector) / sizeof(struct amd_flash_sector_info);
|
||||
|
||||
#define SOFFSET(n) (sector[n].offset)
|
||||
#define SADDR(n) (SOFFSET(n) >> AMD_FLASH_BUS_SHIFT)
|
||||
#define SSIZE(n) (sector[n].size)
|
||||
|
||||
#define AMD_FLASH_DEVICES 1
|
||||
|
||||
static AMD_FLASH_CELL *pFlash;
|
||||
|
||||
typedef struct romram
|
||||
{
|
||||
uint32_t flash_address;
|
||||
uint32_t ram_address;
|
||||
char *name;
|
||||
} ROMRAM;
|
||||
|
||||
static const struct romram flash_areas[] =
|
||||
{
|
||||
{ 0xe0000000, 0x00e00000, "BaS" }, /* BaS */
|
||||
{ 0xe0600000, 0x00e00000, "EmuTOS" }, /* EmuTOS */
|
||||
{ 0xe0400000, 0x00e00000, "FireTOS" }, /* FireTOS */
|
||||
{ 0xe0700000, 0x00e00000, "FPGA" }, /* FPGA config */
|
||||
};
|
||||
static const int num_flash_areas = sizeof(flash_areas) / sizeof(struct romram);
|
||||
|
||||
#define FLASH_ADDRESS BOOTFLASH_BASE_ADDRESS
|
||||
|
||||
/*
|
||||
* erase a flash sector
|
||||
*
|
||||
* sector_num is the index into the sector table above.
|
||||
*
|
||||
* FIXME: need to disable data cache to ensure proper operation
|
||||
*/
|
||||
void amd_flash_sector_erase(int n)
|
||||
{
|
||||
volatile AMD_FLASH_CELL status;
|
||||
|
||||
(void) num_flash_areas; /* to make compiler happy */
|
||||
|
||||
pFlash[0x555] = AMD_FLASH_CMD_DATA(0xAA);
|
||||
pFlash[0x2AA] = AMD_FLASH_CMD_DATA(0x55);
|
||||
pFlash[0x555] = AMD_FLASH_CMD_DATA(0x80);
|
||||
pFlash[0x555] = AMD_FLASH_CMD_DATA(0xAA);
|
||||
pFlash[0x2AA] = AMD_FLASH_CMD_DATA(0x55);
|
||||
pFlash[SADDR(n)] = AMD_FLASH_CMD_DATA(0x30);
|
||||
|
||||
do
|
||||
status = pFlash[SADDR(n)];
|
||||
while ((status & AMD_FLASH_CMD_DATA(0x80)) != AMD_FLASH_CMD_DATA(0x80));
|
||||
|
||||
/*
|
||||
* Place device in read mode
|
||||
*/
|
||||
pFlash[0] = AMD_FLASH_CMD_DATA(0xAA);
|
||||
pFlash[0] = AMD_FLASH_CMD_DATA(0x55);
|
||||
pFlash[0] = AMD_FLASH_CMD_DATA(0xF0);
|
||||
}
|
||||
|
||||
int amd_flash_erase(void *start, int bytes, void (*putchar)(int))
|
||||
{
|
||||
int i, ebytes = 0;
|
||||
|
||||
if (bytes == 0)
|
||||
return 0;
|
||||
|
||||
for (i = 0; i < AMD_FLASH_SECTORS; i++)
|
||||
{
|
||||
if (start >= (void *)((void *) pFlash + SOFFSET(i)) &&
|
||||
start <= (void *)((void *) pFlash + SOFFSET(i) + (SSIZE(i) - 1)))
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
while (ebytes < bytes)
|
||||
{
|
||||
if (putchar != NULL)
|
||||
{
|
||||
putchar('.');
|
||||
}
|
||||
amd_flash_sector_erase(i);
|
||||
ebytes += SSIZE(i);
|
||||
i++;
|
||||
}
|
||||
|
||||
if (putchar != NULL)
|
||||
{
|
||||
putchar(10); /* LF */
|
||||
putchar(13); /* CR */
|
||||
}
|
||||
|
||||
return ebytes;
|
||||
}
|
||||
|
||||
void amd_flash_program_cell(AMD_FLASH_CELL *dst, AMD_FLASH_CELL data)
|
||||
{
|
||||
volatile AMD_FLASH_CELL status;
|
||||
int retry;
|
||||
|
||||
pFlash[0x555] = AMD_FLASH_CMD_DATA(0xAA);
|
||||
pFlash[0x2AA] = AMD_FLASH_CMD_DATA(0x55);
|
||||
pFlash[0x555] = AMD_FLASH_CMD_DATA(0xA0);
|
||||
*dst = data;
|
||||
|
||||
/*
|
||||
* Wait for program operation to finish
|
||||
* (Data# Polling Algorithm)
|
||||
*/
|
||||
retry = 0;
|
||||
while (1)
|
||||
{
|
||||
status = *dst;
|
||||
if ((status & AMD_FLASH_CMD_DATA(0x80)) ==
|
||||
(data & AMD_FLASH_CMD_DATA(0x80)))
|
||||
{
|
||||
break;
|
||||
}
|
||||
if (status & AMD_FLASH_CMD_DATA(0x20))
|
||||
{
|
||||
status = *dst;
|
||||
if ((status & AMD_FLASH_CMD_DATA(0x80)) ==
|
||||
(data & AMD_FLASH_CMD_DATA(0x80)))
|
||||
{
|
||||
break;
|
||||
}
|
||||
if (++retry > 1024)
|
||||
{
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
int amd_flash_program(void *dest, void *source, int bytes, int erase, void (*func)(void), void (*putchar)(int))
|
||||
{
|
||||
AMD_FLASH_CELL *src;
|
||||
AMD_FLASH_CELL *dst;
|
||||
int hashi = 1;
|
||||
int hashj = 0;
|
||||
char hash[5];
|
||||
|
||||
hash[0] = 8; /* Backspace */
|
||||
hash[1] = 124;/* "|" */
|
||||
hash[2] = 47; /* "/" */
|
||||
hash[3] = 45; /* "-" */
|
||||
hash[4] = 92; /* "\" */
|
||||
|
||||
src = (AMD_FLASH_CELL *)source;
|
||||
dst = (AMD_FLASH_CELL *)dest;
|
||||
|
||||
/*
|
||||
* Place device in read mode
|
||||
*/
|
||||
pFlash[0] = AMD_FLASH_CMD_DATA(0xAA);
|
||||
pFlash[0] = AMD_FLASH_CMD_DATA(0x55);
|
||||
pFlash[0] = AMD_FLASH_CMD_DATA(0xF0);
|
||||
|
||||
/*
|
||||
* Erase device if necessary
|
||||
*/
|
||||
if (erase)
|
||||
{
|
||||
amd_flash_erase(dest, bytes, putchar);
|
||||
}
|
||||
|
||||
/*
|
||||
* Program device
|
||||
*/
|
||||
while (bytes > 0)
|
||||
{
|
||||
amd_flash_program_cell(dst, *src);
|
||||
|
||||
/* Verify Write */
|
||||
if (*dst == *src)
|
||||
{
|
||||
bytes -= AMD_FLASH_CELL_BYTES;
|
||||
*dst++, *src++;
|
||||
|
||||
if ((putchar != NULL))
|
||||
{
|
||||
/* Hash marks to indicate progress */
|
||||
if (hashj == 0x1000)
|
||||
{
|
||||
hashj = -1;
|
||||
putchar(hash[0]);
|
||||
putchar(hash[hashi]);
|
||||
|
||||
hashi++;
|
||||
if (hashi == 5)
|
||||
{
|
||||
hashi = 1;
|
||||
}
|
||||
|
||||
}
|
||||
hashj++;
|
||||
}
|
||||
}
|
||||
else
|
||||
break;
|
||||
}
|
||||
|
||||
/*
|
||||
* Place device in read mode
|
||||
*/
|
||||
pFlash[0] = AMD_FLASH_CMD_DATA(0xAA);
|
||||
pFlash[0] = AMD_FLASH_CMD_DATA(0x55);
|
||||
pFlash[0] = AMD_FLASH_CMD_DATA(0xF0);
|
||||
|
||||
if (putchar != NULL)
|
||||
{
|
||||
putchar(hash[0]);
|
||||
}
|
||||
|
||||
/*
|
||||
* If a function was passed in, call it now
|
||||
*/
|
||||
if ((func != NULL))
|
||||
{
|
||||
func();
|
||||
}
|
||||
|
||||
return ((int)src - (int)source);
|
||||
}
|
||||
|
||||
@@ -1,449 +0,0 @@
|
||||
/*
|
||||
* s19reader.c
|
||||
*
|
||||
* Created on: 17.12.2012
|
||||
* Author: mfro
|
||||
* The ACP Firebee project
|
||||
*
|
||||
* This file is part of BaS_gcc.
|
||||
*
|
||||
* BaS_gcc is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* BaS_gcc is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* Copyright 2012 M. Froeschle
|
||||
*/
|
||||
|
||||
#include <bas_types.h>
|
||||
|
||||
#include "bas_printf.h"
|
||||
#include "bas_string.h"
|
||||
#include "sd_card.h"
|
||||
#include "diskio.h"
|
||||
#include "ff.h"
|
||||
#include "s19reader.h"
|
||||
#include "dma.h"
|
||||
#include "cache.h"
|
||||
|
||||
// #define DEBUG
|
||||
#include "debug.h"
|
||||
|
||||
/*
|
||||
* Yes, I know. The following doesn't really look like code should look like...
|
||||
*
|
||||
* I did try to map structures over the S-records with (packed) which didn't work reliably due to gcc _not_ packing them appropiate
|
||||
* and finally ended up with this. Not nice, put paid (and working).
|
||||
*
|
||||
*/
|
||||
#define SREC_TYPE(a) (a)[0] /* type of record */
|
||||
#define SREC_COUNT(a) (a)[1] /* length of valid bytes to follow */
|
||||
#define SREC_ADDR16(a) (256 * (a)[2] + (a)[3]) /* 2 byte address field */
|
||||
#define SREC_ADDR24(a) (0x10000 * (a)[2] + 0x100 * \
|
||||
(a)[3] + (a)[4]) /* 3 byte address field */
|
||||
#define SREC_ADDR32(a) (0x1000000 * a[2] + 0x10000 * \
|
||||
(a)[3] + 0x100 * (a)[4] + (a)[5]) /* 4 byte address field */
|
||||
#define SREC_DATA16(a) ((uint8_t *)&((a)[4])) /* address of first byte of data in a record */
|
||||
#define SREC_DATA24(a) ((uint8_t *)&((a)[5])) /* address of first data byte in 24 bit record */
|
||||
#define SREC_DATA32(a) ((uint8_t *)&((a)[6])) /* adress of first byte of a record with 32 bit address field */
|
||||
#define SREC_DATA16_SIZE(a) (SREC_COUNT((a)) - 3) /* length of the data[] array without the checksum field */
|
||||
#define SREC_DATA24_SIZE(a) (SREC_COUNT((a)) - 4) /* length of the data[] array without the checksum field */
|
||||
#define SREC_DATA32_SIZE(a) (SREC_COUNT((a)) - 5) /* length of the data[] array without the checksum field */
|
||||
#define SREC_CHECKSUM(a) (a)[SREC_COUNT(a) + 2 - 1] /* record's checksum (two's complement of the sum of all bytes) */
|
||||
|
||||
/*
|
||||
* convert a single hex character into byte
|
||||
*/
|
||||
static uint8_t nibble_to_byte(uint8_t nibble)
|
||||
{
|
||||
if ((nibble >= '0') && (nibble <= '9'))
|
||||
return nibble - '0';
|
||||
else if ((nibble >= 'A' && nibble <= 'F'))
|
||||
return 10 + nibble - 'A';
|
||||
else if ((nibble >= 'a' && nibble <= 'f'))
|
||||
return 10 + nibble - 'a';
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*
|
||||
* convert two hex characters into byte
|
||||
*/
|
||||
static uint8_t hex_to_byte(uint8_t hex[2])
|
||||
{
|
||||
return 16 * (nibble_to_byte(hex[0])) + (nibble_to_byte(hex[1]));
|
||||
}
|
||||
|
||||
#ifdef _NOT_USED_
|
||||
/*
|
||||
* convert four hex characters into a 16 bit word
|
||||
*/
|
||||
static uint16_t hex_to_word(uint8_t hex[4])
|
||||
{
|
||||
return 256 * hex_to_byte(&hex[0]) + hex_to_byte(&hex[2]);
|
||||
}
|
||||
|
||||
/*
|
||||
* convert eight hex characters into a 32 bit word
|
||||
*/
|
||||
static uint32_t hex_to_long(uint8_t hex[8])
|
||||
{
|
||||
return 65536 * hex_to_word(&hex[0]) + hex_to_word(&hex[4]);
|
||||
}
|
||||
#endif /* _NOT_USED_ */
|
||||
|
||||
/*
|
||||
* compute the record checksum
|
||||
*
|
||||
* it consists of the one's complement of the byte sum of the data from the count field until the end
|
||||
*/
|
||||
static uint8_t checksum(uint8_t arr[])
|
||||
{
|
||||
int i;
|
||||
uint8_t cs = SREC_COUNT(arr);
|
||||
|
||||
for (i = 0; i < SREC_COUNT(arr) - 1; i++)
|
||||
{
|
||||
cs += arr[i + 2];
|
||||
}
|
||||
return ~cs;
|
||||
}
|
||||
|
||||
#ifdef _NOT_USED_
|
||||
void print_record(uint8_t *arr)
|
||||
{
|
||||
switch (SREC_TYPE(arr))
|
||||
{
|
||||
case 0:
|
||||
{
|
||||
xprintf("type 0x%x ", SREC_TYPE(arr));
|
||||
xprintf("count 0x%x ", SREC_COUNT(arr));
|
||||
xprintf("addr 0x%x ", SREC_ADDR16(arr));
|
||||
xprintf("module %11.11s ", SREC_DATA16(arr));
|
||||
xprintf("chk 0x%x 0x%x\r\n", SREC_CHECKSUM(arr), checksum(arr));
|
||||
}
|
||||
break;
|
||||
|
||||
case 3:
|
||||
case 7:
|
||||
{
|
||||
xprintf("type 0x%x ", SREC_TYPE(arr));
|
||||
xprintf("count 0x%x ", SREC_COUNT(arr));
|
||||
xprintf("addr 0x%x ", SREC_ADDR32(arr));
|
||||
xprintf("data %02x,%02x,%02x,%02x,... ",
|
||||
SREC_DATA32(arr)[0], SREC_DATA32(arr)[1], SREC_DATA32(arr)[3], SREC_DATA32(arr)[4]);
|
||||
xprintf("chk 0x%x 0x%x\r\n", SREC_CHECKSUM(arr), checksum(arr));
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
xprintf("unsupported report type %d in print_record\r\n", arr[0]);
|
||||
break;
|
||||
}
|
||||
}
|
||||
#endif /* _NOT_USED_ */
|
||||
|
||||
/*
|
||||
* convert an S-record line into its corresponding byte vector (ASCII->binary)
|
||||
*/
|
||||
static void line_to_vector(uint8_t *buff, uint8_t *vector)
|
||||
{
|
||||
int i;
|
||||
int length;
|
||||
uint8_t *vp = vector;
|
||||
|
||||
length = hex_to_byte(buff + 2);
|
||||
|
||||
buff++;
|
||||
*vp++ = nibble_to_byte(*buff); /* record type. Only one single nibble */
|
||||
buff++;
|
||||
|
||||
for (i = 0; i <= length; i++)
|
||||
{
|
||||
*vp++ = hex_to_byte(buff);
|
||||
buff += 2;
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* read and parse a Motorola S-record file and copy contents to dst. The theory of operation is to read and parse the S-record file
|
||||
* and to use the supplied callback routine to copy the buffer to the destination once the S-record line is converted.
|
||||
* The memcpy callback can be anything (as long as it conforms parameter-wise) - a basically empty function to just let
|
||||
* read_srecords validate the file, a standard memcpy() to copy file contents to destination RAM or a more sophisticated
|
||||
* routine that does write/erase flash
|
||||
*
|
||||
* FIXME: Currently only records that the gcc toolchain emits are supported.
|
||||
*
|
||||
* Parameters:
|
||||
* IN
|
||||
* filename - the filename that contains the S-records
|
||||
* callback - the memcpy() routine discussed above
|
||||
* OUT
|
||||
* start_address - the execution address of the code as read from the file. Can be used to jump into and execute it
|
||||
* actual_length - the overall length of the binary code read from the file
|
||||
* returns
|
||||
* OK or an err_t error code if anything failed
|
||||
*/
|
||||
err_t read_srecords(char *filename, void **start_address, uint32_t *actual_length, memcpy_callback_t callback)
|
||||
{
|
||||
FRESULT fres;
|
||||
FIL file;
|
||||
err_t ret = OK;
|
||||
uint32_t length = 0;
|
||||
|
||||
if ((fres = f_open(&file, filename, FA_READ) == FR_OK))
|
||||
{
|
||||
uint8_t line[255];
|
||||
int lineno = 0;
|
||||
int data_records = 0;
|
||||
bool found_block_header = false;
|
||||
bool found_block_end = false;
|
||||
bool found_block_data = false;
|
||||
|
||||
*actual_length = 0;
|
||||
|
||||
while (ret == OK && (uint8_t *) f_gets((char *) line, sizeof(line), &file) != NULL)
|
||||
{
|
||||
lineno++;
|
||||
uint8_t vector[80];
|
||||
|
||||
memset(vector, 0, sizeof(vector));
|
||||
line_to_vector(line, vector); /* vector now contains the decoded contents of line, from line[1] on */
|
||||
|
||||
if (line[0] == 'S')
|
||||
{
|
||||
if (SREC_CHECKSUM(vector) != checksum(vector))
|
||||
{
|
||||
xprintf("invalid checksum 0x%x (should be 0x%x) in line %d\r\n",
|
||||
SREC_CHECKSUM(vector), checksum(vector), lineno);
|
||||
ret = FAIL;
|
||||
}
|
||||
|
||||
switch (vector[0])
|
||||
{
|
||||
case 0: /* block header */
|
||||
found_block_header = true;
|
||||
if (found_block_data || found_block_end)
|
||||
{
|
||||
xprintf("S7 or S3 record found before S0: S-records corrupt?\r\n");
|
||||
ret = FAIL;
|
||||
}
|
||||
|
||||
break;
|
||||
|
||||
case 2: /* three byte address field data record */
|
||||
if (!found_block_header || found_block_end)
|
||||
{
|
||||
xprintf("S2 record found before S0 or after S7: S-records corrupt?\r\n");
|
||||
ret = FAIL;
|
||||
}
|
||||
ret = callback((uint8_t *) SREC_ADDR24(vector), SREC_DATA24(vector), SREC_DATA24_SIZE(vector));
|
||||
length += SREC_DATA24_SIZE(vector);
|
||||
data_records++;
|
||||
break;
|
||||
|
||||
case 3: /* four byte address field data record */
|
||||
if (!found_block_header || found_block_end)
|
||||
{
|
||||
xprintf("S3 record found before S0 or after S7: S-records corrupt?\r\n");
|
||||
ret = FAIL;
|
||||
}
|
||||
length += SREC_DATA32_SIZE(vector);
|
||||
ret = callback((uint8_t *) SREC_ADDR32(vector), SREC_DATA32(vector), SREC_DATA32_SIZE(vector));
|
||||
data_records++;
|
||||
break;
|
||||
|
||||
case 7: /* four byte address field end record */
|
||||
if (!found_block_header || found_block_end)
|
||||
{
|
||||
xprintf("S7 record found before S0 or after S7: S-records corrupt?\r\n");
|
||||
}
|
||||
else
|
||||
{
|
||||
// xprintf("S7 record (end) found after %d valid data blocks\r\n", data_records);
|
||||
*start_address = (void *) SREC_ADDR32(vector);
|
||||
xprintf("%d blocks read. Found start address %p\r\n", data_records, *start_address);
|
||||
}
|
||||
break;
|
||||
|
||||
case 8: /* three byte address field end record */
|
||||
if (!found_block_header || found_block_end)
|
||||
{
|
||||
xprintf("S8 record found before S0 or after S8: S-records corrupt?\r\n");
|
||||
}
|
||||
else
|
||||
{
|
||||
// xprintf("S8 record (end) found after %d valid data blocks\r\n", data_records);
|
||||
*start_address = (void *) SREC_ADDR24(vector);
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
xprintf("unsupported record type (%d) found in line %d\r\n", vector[0], lineno);
|
||||
xprintf("offending line: \r\n");
|
||||
xprintf("%s\r\n", line);
|
||||
ret = FAIL;
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
xprintf("illegal character ('%c') found on line %d: S-records corrupt?\r\n", line[0], lineno);
|
||||
ret = FAIL;
|
||||
break;
|
||||
}
|
||||
}
|
||||
f_close(&file);
|
||||
}
|
||||
else
|
||||
{
|
||||
xprintf("could not open file %s\r\n", filename);
|
||||
ret = FILE_OPEN;
|
||||
}
|
||||
*actual_length = length;
|
||||
return ret;
|
||||
}
|
||||
|
||||
/*
|
||||
* this callback just does nothing besides returning OK. Meant to do a dry run over the file to check its integrity
|
||||
*/
|
||||
static err_t simulate()
|
||||
{
|
||||
err_t ret = OK;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
||||
#ifdef _NOT_USED_
|
||||
static err_t flash(uint8_t *dst, uint8_t *src, uint32_t length)
|
||||
{
|
||||
err_t ret = OK;
|
||||
|
||||
/* TODO: do the actual flash */
|
||||
amd_flash_program(dst, src, length, false, NULL, xputchar);
|
||||
|
||||
return ret;
|
||||
}
|
||||
#endif /* _NOT_USED_ */
|
||||
|
||||
|
||||
/*
|
||||
* this callback verifies the data against the S-record file contents after a write to destination
|
||||
*/
|
||||
static err_t verify(uint8_t *dst, uint8_t *src, size_t length)
|
||||
{
|
||||
uint8_t *end = src + length;
|
||||
|
||||
do
|
||||
{
|
||||
if (*src++ != *dst++)
|
||||
{
|
||||
xprintf("data differs at %p (expected 0x%02x, got 0x%02x)\r\n",
|
||||
*(src - 1), *(dst - 1));
|
||||
return FAIL;
|
||||
}
|
||||
} while (src < end);
|
||||
|
||||
return OK;
|
||||
}
|
||||
|
||||
/*
|
||||
* needed to avoid missing type cast warning below
|
||||
*/
|
||||
err_t srec_memcpy(uint8_t *dst, uint8_t *src, size_t n)
|
||||
{
|
||||
err_t e = OK;
|
||||
|
||||
xprintf(".");
|
||||
dbg("\r\ncopy from %p to %p, length %d", src, dst, n);
|
||||
// dma_memcpy((void *) dst, (void *) src, n);
|
||||
memcpy((void *) dst, (void *) src, n);
|
||||
return e;
|
||||
}
|
||||
|
||||
void srec_execute(char *flasher_filename)
|
||||
{
|
||||
DRESULT res;
|
||||
FRESULT fres;
|
||||
FATFS fs;
|
||||
FIL file;
|
||||
err_t err;
|
||||
void *start_address;
|
||||
uint32_t length;
|
||||
|
||||
disk_initialize(0);
|
||||
res = disk_status(0);
|
||||
if (res == RES_OK)
|
||||
{
|
||||
fres = f_mount(0, &fs);
|
||||
if (fres == FR_OK)
|
||||
{
|
||||
if ((fres = f_open(&file, flasher_filename, FA_READ) != FR_OK))
|
||||
{
|
||||
xprintf("flasher file %s not present on disk\r\n", flasher_filename);
|
||||
}
|
||||
else
|
||||
{
|
||||
f_close(&file);
|
||||
|
||||
/* first pass: parse and check for inconsistencies */
|
||||
xprintf("check file integrity: ");
|
||||
err = read_srecords(flasher_filename, &start_address, &length, simulate);
|
||||
if (err == OK)
|
||||
{
|
||||
/* next pass: copy data to destination */
|
||||
xprintf("OK (start address=%p, length = %ld).\r\ncopy data: ", start_address, length);
|
||||
err = read_srecords(flasher_filename, &start_address, &length, srec_memcpy);
|
||||
if (err == OK)
|
||||
{
|
||||
/* next pass: verify data */
|
||||
xprintf("OK.\r\nverify data: ");
|
||||
err = read_srecords(flasher_filename, &start_address, &length, verify);
|
||||
if (err == OK)
|
||||
{
|
||||
xprintf("OK.\r\n");
|
||||
|
||||
typedef void void_func(void);
|
||||
void_func *func;
|
||||
xprintf("target successfully written and verified. Start address: %p\r\n", start_address);
|
||||
|
||||
func = start_address;
|
||||
flush_and_invalidate_caches();
|
||||
(*func)();
|
||||
}
|
||||
else
|
||||
{
|
||||
xprintf("failed\r\n");
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
xprintf("failed\r\n");
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
xprintf("failed\r\n");
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
// xprintf("could not mount FAT FS\r\n");
|
||||
}
|
||||
f_mount(0, NULL);
|
||||
}
|
||||
else
|
||||
{
|
||||
// xprintf("could not initialize SD card\r\n");
|
||||
}
|
||||
}
|
||||
|
||||
@@ -1,53 +0,0 @@
|
||||
#!/usr/local/bin/bdmctrl -D2
|
||||
#
|
||||
# firebee board initialization for bdmctrl
|
||||
#
|
||||
open $1
|
||||
reset
|
||||
sleep 1
|
||||
|
||||
wait
|
||||
|
||||
# use system sdram as flashlib scratch area.
|
||||
# TODO: plugin flashing seems to work o.k. now for smaller binaries, while it doesn't for larger ones (EmuTOS) yet.
|
||||
# This seems to be related to large flash buffers and PC-relative adressing of the plugin
|
||||
flash-plugin 0x1000 0xf000 flash29.plugin
|
||||
# notify flashlib that we have flash at address 0xE0000000, length 0x7FFFFF, plugin is flash29
|
||||
flash 0xe0000000
|
||||
|
||||
# Erase flash from 0xE0000000 to 0xE00FFFFF (reserved space for BaS)
|
||||
#
|
||||
# Caution: sector offset numbers need to be the ones from the x16 address range
|
||||
# column and they vary in size - needs to be exactly as in the data sheet (p. 9)
|
||||
#
|
||||
|
||||
erase 0xe0000000 0
|
||||
erase 0xe0000000 0x1000
|
||||
erase 0xe0000000 0x2000
|
||||
erase 0xe0000000 0x3000
|
||||
erase 0xe0000000 0x4000
|
||||
erase 0xe0000000 0x5000
|
||||
erase 0xe0000000 0x6000
|
||||
erase 0xe0000000 0x7000
|
||||
erase 0xe0000000 0x8000
|
||||
erase 0xe0000000 0x10000
|
||||
erase 0xe0000000 0x18000
|
||||
erase 0xe0000000 0x20000
|
||||
erase 0xe0000000 0x28000
|
||||
erase 0xe0000000 0x30000
|
||||
erase 0xe0000000 0x38000
|
||||
erase 0xe0000000 0x40000
|
||||
erase 0xe0000000 0x48000
|
||||
erase 0xe0000000 0x50000
|
||||
erase 0xe0000000 0x58000
|
||||
erase 0xe0000000 0x60000
|
||||
erase 0xe0000000 0x70000
|
||||
erase 0xe0000000 0x78000
|
||||
|
||||
erase-wait 0xe0000000
|
||||
# should now have erased from 0xe0000000 to 0xe00fffff
|
||||
|
||||
dump-mem 0xe0010000 0x20 b
|
||||
|
||||
load -v ../firebee/bas.elf
|
||||
wait
|
||||
@@ -1,81 +0,0 @@
|
||||
#!/usr/local/bin/bdmctrl -D2
|
||||
#
|
||||
# flash EmuTOS using bdmctrl
|
||||
#
|
||||
open $1
|
||||
reset
|
||||
|
||||
# Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes)
|
||||
write 0xFF000500 0xE0000000 4
|
||||
write 0xFF000508 0x00001180 4
|
||||
write 0xFF000504 0x007F0001 4
|
||||
|
||||
# SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes
|
||||
write 0xFF000004 0x000002AA 4 # SDRAMDS configuration
|
||||
write 0xFF000020 0x0000001A 4 # SDRAM CS0 configuration (128Mbytes 0000_0000 - 07FF_FFFF)
|
||||
write 0xFF000024 0x0800001A 4 # SDRAM CS1 configuration (128Mbytes 0800_0000 - 0FFF_FFFF)
|
||||
write 0xFF000028 0x1000001A 4 # SDRAM CS2 configuration (128Mbytes 1000_0000 - 17FF_FFFF)
|
||||
write 0xFF00002C 0x1800001A 4 # SDRAM CS3 configuration (128Mbytes 1800_0000 - 1FFF_FFFF)
|
||||
write 0xFF000108 0x73622830 4 # SDCFG1
|
||||
write 0xFF00010C 0x46770000 4 # SDCFG2
|
||||
|
||||
write 0xFF000104 0xE10D0002 4 # SDCR + IPALL
|
||||
write 0xFF000100 0x40010000 4 # SDMR (write to LEMR)
|
||||
write 0xFF000100 0x048D0000 4 # SDMR (write to LMR)
|
||||
sleep 100
|
||||
write 0xFF000104 0xE10D0002 4 # SDCR + IPALL
|
||||
write 0xFF000104 0xE10D0004 4 # SDCR + IREF (first refresh)
|
||||
write 0xFF000104 0xE10D0004 4 # SDCR + IREF (first refresh)
|
||||
write 0xFF000100 0x008D0000 4 # SDMR (write to LMR)
|
||||
write 0xFF000104 0x710D0F00 4 # SDCR (lock SDMR and enable refresh)
|
||||
sleep 10
|
||||
|
||||
|
||||
# use system sdram as flashlib scratch area
|
||||
# flashing EmuTOS with plugin does not work yet (at least not for 64bit hosts)
|
||||
#flash-plugin 0x1000 0xf000 flash29.plugin
|
||||
|
||||
# notify flashlib that we have flash at address 0xE0000000, length 0x7FFFFF, plugin is flash29
|
||||
flash 0xe0000000
|
||||
|
||||
# Erase flash from 0xE0600000 to 0xE06FFFFF (reserved space for EmuTOS)
|
||||
#
|
||||
# Caution: sector offset numbers need to be the ones from the x16 address range
|
||||
# column and they vary in size - needs to be exactly as in the data sheet (p. 9)
|
||||
#
|
||||
# contrary to documentation, it seems we need to erase-wait after each sector
|
||||
|
||||
erase 0xe0000000 0x300000
|
||||
erase-wait 0xe0000000
|
||||
erase 0xe0000000 0x308000
|
||||
erase-wait 0xe0000000
|
||||
erase 0xe0000000 0x310000
|
||||
erase-wait 0xe0000000
|
||||
erase 0xe0000000 0x318000
|
||||
erase-wait 0xe0000000
|
||||
erase 0xe0000000 0x320000
|
||||
erase-wait 0xe0000000
|
||||
erase 0xe0000000 0x328000
|
||||
erase-wait 0xe0000000
|
||||
erase 0xe0000000 0x330000
|
||||
erase-wait 0xe0000000
|
||||
erase 0xe0000000 0x338000
|
||||
erase-wait 0xe0000000
|
||||
erase 0xe0000000 0x340000
|
||||
erase-wait 0xe0000000
|
||||
erase 0xe0000000 0x348000
|
||||
erase-wait 0xe0000000
|
||||
erase 0xe0000000 0x350000
|
||||
erase-wait 0xe0000000
|
||||
erase 0xe0000000 0x358000
|
||||
erase-wait 0xe0000000
|
||||
erase 0xe0000000 0x360000
|
||||
erase-wait 0xe0000000
|
||||
erase 0xe0000000 0x368000
|
||||
erase-wait 0xe0000000
|
||||
erase 0xe0000000 0x370000
|
||||
erase-wait 0xe0000000
|
||||
erase 0xe0000000 0x378000
|
||||
erase-wait 0xe0000000
|
||||
|
||||
load -v emutos-firebee.elf
|
||||
@@ -1,59 +0,0 @@
|
||||
#!/usr/local/bin/bdmctrl -D2
|
||||
#
|
||||
# firebee board initialization for bdmctrl
|
||||
#
|
||||
open $1
|
||||
reset
|
||||
|
||||
# Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes)
|
||||
write 0xFF000500 0xE0000000 4
|
||||
write 0xFF000508 0x00001180 4
|
||||
write 0xFF000504 0x007F0001 4
|
||||
|
||||
# notify flashlib that we have flash at address 0xE0000000, length 0x7FFFFF, plugin is flash29
|
||||
flash 0xe0000000
|
||||
|
||||
# flash-plugin (target-based flashing) does not work yet
|
||||
# flash-plugin 0x10000000 0x4000 flash29.plugin
|
||||
|
||||
# Erase flash from 0xE0400000 to 0xE04FFFFF (reserved space for FireTOS)
|
||||
#
|
||||
# Caution: sector offset numbers need to be the ones from the x16 address range
|
||||
# column and they vary in size - needs to be exactly as in the data sheet (p. 9)
|
||||
#
|
||||
# contrary to documentation, it seems we need to erase-wait after each sector
|
||||
|
||||
erase 0xe0000000 0x200000
|
||||
erase-wait 0xe0000000
|
||||
erase 0xe0000000 0x208000
|
||||
erase-wait 0xe0000000
|
||||
erase 0xe0000000 0x210000
|
||||
erase-wait 0xe0000000
|
||||
erase 0xe0000000 0x218000
|
||||
erase-wait 0xe0000000
|
||||
erase 0xe0000000 0x220000
|
||||
erase-wait 0xe0000000
|
||||
erase 0xe0000000 0x228000
|
||||
erase-wait 0xe0000000
|
||||
erase 0xe0000000 0x230000
|
||||
erase-wait 0xe0000000
|
||||
erase 0xe0000000 0x238000
|
||||
erase-wait 0xe0000000
|
||||
erase 0xe0000000 0x240000
|
||||
erase-wait 0xe0000000
|
||||
erase 0xe0000000 0x248000
|
||||
erase-wait 0xe0000000
|
||||
erase 0xe0000000 0x250000
|
||||
erase-wait 0xe0000000
|
||||
erase 0xe0000000 0x258000
|
||||
erase-wait 0xe0000000
|
||||
erase 0xe0000000 0x260000
|
||||
erase-wait 0xe0000000
|
||||
erase 0xe0000000 0x268000
|
||||
erase-wait 0xe0000000
|
||||
erase 0xe0000000 0x270000
|
||||
erase-wait 0xe0000000
|
||||
erase 0xe0000000 0x278000
|
||||
erase-wait 0xe0000000
|
||||
|
||||
load -v firetos.elf
|
||||
@@ -1,77 +0,0 @@
|
||||
#!/usr/local/bin/bdmctrl -D2
|
||||
#
|
||||
# firebee board initialization for bdmctrl
|
||||
#
|
||||
open $1
|
||||
#reset
|
||||
|
||||
# Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes)
|
||||
write 0xFF000500 0xE0000000 4
|
||||
write 0xFF000508 0x00001180 4
|
||||
write 0xFF000504 0x007F0001 4
|
||||
|
||||
# notify flashlib that we have flash at address 0xE0000000, length 0x7FFFFF, plugin is flash29
|
||||
flash 0xe0000000
|
||||
|
||||
# flash-plugin (target-based flashing) does not work yet
|
||||
#flash-plugin 0x10000000 0x4000 flash29.plugin
|
||||
|
||||
# Erase flash from 0xE0700000 to 0xE07FFFFF (reserved space for FPGA)
|
||||
#
|
||||
# Caution: sector offset numbers need to be the ones from the x16 address range
|
||||
# column and they vary in size - needs to be exactly as in the data sheet (p. 9)
|
||||
#
|
||||
# contrary to documentation, it seems we need to erase-wait after each sector
|
||||
|
||||
erase 0xe0000000 0x380000
|
||||
erase-wait 0xe0000000
|
||||
erase 0xe0000000 0x388000
|
||||
erase-wait 0xe0000000
|
||||
erase 0xe0000000 0x390000
|
||||
erase-wait 0xe0000000
|
||||
erase 0xe0000000 0x398000
|
||||
erase-wait 0xe0000000
|
||||
erase 0xe0000000 0x3A0000
|
||||
erase-wait 0xe0000000
|
||||
erase 0xe0000000 0x3A0000
|
||||
erase-wait 0xe0000000
|
||||
erase 0xe0000000 0x3A8000
|
||||
erase-wait 0xe0000000
|
||||
erase 0xe0000000 0x3B0000
|
||||
erase-wait 0xe0000000
|
||||
erase 0xe0000000 0x3B8000
|
||||
erase-wait 0xe0000000
|
||||
erase 0xe0000000 0x3C0000
|
||||
erase-wait 0xe0000000
|
||||
erase 0xe0000000 0x3C8000
|
||||
erase-wait 0xe0000000
|
||||
erase 0xe0000000 0x3D0000
|
||||
erase-wait 0xe0000000
|
||||
erase 0xe0000000 0x3D8000
|
||||
erase-wait 0xe0000000
|
||||
erase 0xe0000000 0x3E0000
|
||||
erase-wait 0xe0000000
|
||||
erase 0xe0000000 0x3E8000
|
||||
erase-wait 0xe0000000
|
||||
erase 0xe0000000 0x3F0000
|
||||
erase-wait 0xe0000000
|
||||
erase 0xe0000000 0x3F8000
|
||||
erase-wait 0xe0000000
|
||||
erase 0xe0000000 0x3F9000
|
||||
erase-wait 0xe0000000
|
||||
erase 0xe0000000 0x3FA000
|
||||
erase-wait 0xe0000000
|
||||
erase 0xe0000000 0x3FB000
|
||||
erase-wait 0xe0000000
|
||||
erase 0xe0000000 0x3FC000
|
||||
erase-wait 0xe0000000
|
||||
erase 0xe0000000 0x3FD000
|
||||
erase-wait 0xe0000000
|
||||
erase 0xe0000000 0x3FE000
|
||||
erase-wait 0xe0000000
|
||||
erase 0xe0000000 0x3FF000
|
||||
erase-wait 0xe0000000
|
||||
|
||||
wait
|
||||
|
||||
load -v FPGA.elf
|
||||
@@ -1,92 +0,0 @@
|
||||
#!/usr/local/bin/bdmctrl
|
||||
#
|
||||
# m548x board initialization for bdmctrl
|
||||
#
|
||||
open $1
|
||||
reset
|
||||
wait
|
||||
|
||||
# set VBR
|
||||
write-ctrl 0x0801 0x00000000
|
||||
dump-register VBR
|
||||
|
||||
# Turn on MBAR at 0xFF00_0000
|
||||
write-ctrl 0x0C0F 0xFF000000
|
||||
dump-register MBAR
|
||||
|
||||
# Turn on RAMBAR0 at address FF10_0000
|
||||
write-ctrl 0x0C04 0xFF100007
|
||||
|
||||
# Turn on RAMBAR1 at address FF10_1000 (disabled - not mapped by bdm currently)
|
||||
write-ctrl 0x0C05 0xFF101001
|
||||
|
||||
#
|
||||
# Init CS0 (BootFLASH @ E000_0000 - E03F_FFFF 4Mbytes)
|
||||
write 0xFF000500 0xE0000000 4
|
||||
#write 0xFF000508 0x00041180 4
|
||||
write 0xFF000508 0x00100D80 4
|
||||
write 0xFF000504 0x003F0001 4
|
||||
|
||||
# SDRAM Initialization @ 0000_0000 - 03FF_FFFF 64 Mbytes
|
||||
write 0xFF000004 0x000002AA 4 # SDRAMDS configuration
|
||||
write 0xFF000020 0x00000019 4 # SDRAM CS0 configuration (128Mbytes 0000_0000 - 07FF_FFFF)
|
||||
write 0xFF000024 0x08000000 4 # SDRAM CS1 configuration (128Mbytes 0800_0000 - 0FFF_FFFF)
|
||||
write 0xFF000028 0x10000000 4 # SDRAM CS2 configuration (128Mbytes 1000_0000 - 17FF_FFFF)
|
||||
write 0xFF00002C 0x18000000 4 # SDRAM CS3 configuration (128Mbytes 1800_0000 - 1FFF_FFFF)
|
||||
write 0xFF000108 0x73711630 4 # SDCFG1
|
||||
write 0xFF00010C 0x46370000 4 # SDCFG2
|
||||
|
||||
write 0xFF000104 0xE10B0002 4 # SDCR + IPALL
|
||||
write 0xFF000100 0x40010000 4 # SDMR (write to LEMR)
|
||||
write 0xFF000100 0x058D0000 4 # SDMR (write to LMR)
|
||||
sleep 100
|
||||
write 0xFF000104 0xE10D0002 4 # SDCR + IPALL
|
||||
write 0xFF000104 0xE10D0004 4 # SDCR + IREF (first refresh)
|
||||
write 0xFF000104 0xE10D0004 4 # SDCR + IREF (first refresh)
|
||||
write 0xFF000100 0x018D0000 4 # SDMR (write to LMR)
|
||||
write 0xFF000104 0x710D0F00 4 # SDCR (lock SDMR and enable refresh)
|
||||
sleep 10
|
||||
|
||||
|
||||
# use system sdram as flashlib scratch area.
|
||||
# TODO: plugin flashing seems to work o.k. now for smaller binaries, while it doesn't for larger ones (EmuTOS) yet.
|
||||
# This seems to be related to large flash buffers and PC-relative adressing of the plugin
|
||||
#flash-plugin 0x1000 0xf000 flash29.plugin
|
||||
# notify flashlib that we have flash at address 0xE0000000, length 0x7FFFFF, plugin is flash29
|
||||
flash 0xE0000000
|
||||
#flash-plugin 0x1000 0xf000 flashintelc3.plugin
|
||||
|
||||
# Erase flash from 0xE0000000 to 0xE00FFFFF (reserved space for bas)
|
||||
#
|
||||
# Caution: sector offset numbers need to be the ones from the x16 address range
|
||||
# column and they vary in size - needs to be exactly as in the data sheet (p. 9)
|
||||
#
|
||||
# contrary to documentation, it seems we need to erase-wait after each sector
|
||||
|
||||
erase 0xE0000000 0
|
||||
erase 0xE0000000 1
|
||||
erase 0xE0000000 2
|
||||
erase 0xE0000000 3
|
||||
erase 0xE0000000 4
|
||||
erase 0xE0000000 5
|
||||
erase 0xE0000000 6
|
||||
erase 0xE0000000 7
|
||||
erase 0xE0000000 8
|
||||
erase 0xE0000000 9
|
||||
erase 0xE0000000 10
|
||||
erase 0xE0000000 11
|
||||
erase 0xE0000000 12
|
||||
erase 0xE0000000 13
|
||||
#erase 0xE0000000 0x2000
|
||||
#erase 0xE0000000 0x3000
|
||||
#erase 0xE0000000 0x4000
|
||||
#erase 0xE0000000 0x5000
|
||||
#erase 0xE0000000 0x00006000
|
||||
#erase 0xE0000000 0x00007000
|
||||
#erase 0xE0000000 0x00008000
|
||||
#erase 0xE0000000 0x00009000
|
||||
#erase 0xE0000000 0x0000a000
|
||||
#erase 0xE0000000 0x0000b000
|
||||
#erase-wait 0xe0000000
|
||||
load -v ../m5484lite/bas.elf
|
||||
wait
|
||||
@@ -1,77 +0,0 @@
|
||||
#!/usr/local/bin/bdmctrl
|
||||
#
|
||||
# m548x board initialization for bdmctrl
|
||||
#
|
||||
open $1
|
||||
reset
|
||||
wait
|
||||
|
||||
# set VBR
|
||||
write-ctrl 0x0801 0x00000000
|
||||
dump-register VBR
|
||||
|
||||
# Turn on MBAR at 0x1000_0000
|
||||
write-ctrl 0x0C0F 0x10000000
|
||||
dump-register MBAR
|
||||
|
||||
# Turn on RAMBAR0 at address 2000_0000
|
||||
write-ctrl 0x0C04 0x20000007
|
||||
|
||||
# Turn on RAMBAR1 at address FF10_1000 (disabled - not mapped by bdm currently)
|
||||
write-ctrl 0x0C05 0x20001001
|
||||
|
||||
#
|
||||
# Init CS0 (BootFLASH @ FF80_0000 - FFBF_FFFF 4Mbytes)
|
||||
write 0xFF000500 0xFF800000 4
|
||||
write 0xFF000508 0x00100D80 4
|
||||
write 0xFF000504 0x003F0001 4
|
||||
|
||||
# SDRAM Initialization @ 0000_0000 - 03FF_FFFF 64 Mbytes
|
||||
write 0xFF000004 0x000002AA 4 # SDRAMDS configuration
|
||||
write 0xFF000020 0x00000019 4 # SDRAM CS0 configuration (128Mbytes 0000_0000 - 07FF_FFFF)
|
||||
write 0xFF000024 0x08000000 4 # SDRAM CS1 configuration (128Mbytes 0800_0000 - 0FFF_FFFF)
|
||||
write 0xFF000028 0x10000000 4 # SDRAM CS2 configuration (128Mbytes 1000_0000 - 17FF_FFFF)
|
||||
write 0xFF00002C 0x18000000 4 # SDRAM CS3 configuration (128Mbytes 1800_0000 - 1FFF_FFFF)
|
||||
write 0xFF000108 0x73711630 4 # SDCFG1
|
||||
write 0xFF00010C 0x46370000 4 # SDCFG2
|
||||
|
||||
write 0xFF000104 0xE10B0002 4 # SDCR + IPALL
|
||||
write 0xFF000100 0x40010000 4 # SDMR (write to LEMR)
|
||||
write 0xFF000100 0x058D0000 4 # SDMR (write to LMR)
|
||||
sleep 100
|
||||
write 0xFF000104 0xE10D0002 4 # SDCR + IPALL
|
||||
write 0xFF000104 0xE10D0004 4 # SDCR + IREF (first refresh)
|
||||
write 0xFF000104 0xE10D0004 4 # SDCR + IREF (first refresh)
|
||||
write 0xFF000100 0x018D0000 4 # SDMR (write to LMR)
|
||||
write 0xFF000104 0x710D0F00 4 # SDCR (lock SDMR and enable refresh)
|
||||
sleep 10
|
||||
|
||||
|
||||
# use system sdram as flashlib scratch area.
|
||||
# TODO: plugin flashing seems to work o.k. now for smaller binaries, while it doesn't for larger ones (EmuTOS) yet.
|
||||
# This seems to be related to large flash buffers and PC-relative adressing of the plugin
|
||||
#flash-plugin 0x1000 0xf000 flash29.plugin
|
||||
# notify flashlib that we have flash at address 0xE0000000, length 0x7FFFFF, plugin is flash29
|
||||
flash 0xFF800000
|
||||
#flash-plugin 0x1000 0xf000 flashintelc3.plugin
|
||||
|
||||
# Erase flash from 0xFF800000 to 0xFFBFFFFF (reserved space for bas)
|
||||
#
|
||||
# contrary to documentation, it seems we need to erase-wait after each sector
|
||||
|
||||
erase 0xFF800000 0
|
||||
erase 0xFF800000 1
|
||||
erase 0xFF800000 2
|
||||
erase 0xFF800000 3
|
||||
erase 0xFF800000 4
|
||||
erase 0xFF800000 5
|
||||
erase 0xFF800000 6
|
||||
erase 0xFF800000 7
|
||||
erase 0xFF800000 8
|
||||
erase 0xFF800000 9
|
||||
erase 0xFF800000 10
|
||||
erase 0xFF800000 11
|
||||
erase 0xFF800000 12
|
||||
erase 0xFF800000 13
|
||||
load -v m548xlite_dbug_flash.elf
|
||||
wait
|
||||
@@ -1,66 +0,0 @@
|
||||
#!/usr/local/bin/bdmctrl -D2
|
||||
#
|
||||
# flash EmuTOS using bdmctrl
|
||||
#
|
||||
open $1
|
||||
reset
|
||||
|
||||
# Turn on RAMBAR0 at address FF10_0000
|
||||
write-ctrl 0x0C04 0xFF100007
|
||||
|
||||
# Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes)
|
||||
write 0xFF000500 0xE0000000 4
|
||||
write 0xFF000508 0x00001180 4
|
||||
write 0xFF000504 0x007F0001 4
|
||||
|
||||
# SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes
|
||||
write 0xFF000004 0x000002AA 4 # SDRAMDS configuration
|
||||
write 0xFF000020 0x0000001A 4 # SDRAM CS0 configuration (128Mbytes 0000_0000 - 07FF_FFFF)
|
||||
write 0xFF000024 0x0800001A 4 # SDRAM CS1 configuration (128Mbytes 0800_0000 - 0FFF_FFFF)
|
||||
write 0xFF000028 0x1000001A 4 # SDRAM CS2 configuration (128Mbytes 1000_0000 - 17FF_FFFF)
|
||||
write 0xFF00002C 0x1800001A 4 # SDRAM CS3 configuration (128Mbytes 1800_0000 - 1FFF_FFFF)
|
||||
write 0xFF000108 0x73622830 4 # SDCFG1
|
||||
write 0xFF00010C 0x46770000 4 # SDCFG2
|
||||
|
||||
write 0xFF000104 0xE10D0002 4 # SDCR + IPALL
|
||||
write 0xFF000100 0x40010000 4 # SDMR (write to LEMR)
|
||||
write 0xFF000100 0x048D0000 4 # SDMR (write to LMR)
|
||||
sleep 100
|
||||
write 0xFF000104 0xE10D0002 4 # SDCR + IPALL
|
||||
write 0xFF000104 0xE10D0004 4 # SDCR + IREF (first refresh)
|
||||
write 0xFF000104 0xE10D0004 4 # SDCR + IREF (first refresh)
|
||||
write 0xFF000100 0x008D0000 4 # SDMR (write to LMR)
|
||||
write 0xFF000104 0x710D0F00 4 # SDCR (lock SDMR and enable refresh)
|
||||
sleep 10
|
||||
|
||||
|
||||
# use sram as flashlib scratch area
|
||||
# flashing EmuTOS with plugin does not work yet (at least not for 64bit hosts)
|
||||
#flash-plugin 0xFF101000 0xffff flashintelc3.plugin
|
||||
|
||||
# notify flashlib that we have flash at address 0xE0000000, length 0x7FFFFF, plugin is flash29
|
||||
flash 0xe0000000
|
||||
|
||||
# Erase flash from 0xE0100000 to 0xE01FFFFF (reserved space for EmuTOS on the m5484lite)
|
||||
|
||||
erase 0xe0000000 21
|
||||
erase 0xe0000000 22
|
||||
erase 0xe0000000 23
|
||||
erase 0xe0000000 24
|
||||
erase 0xe0000000 25
|
||||
erase 0xe0000000 26
|
||||
erase 0xe0000000 27
|
||||
erase 0xe0000000 28
|
||||
erase 0xe0000000 29
|
||||
erase 0xe0000000 30
|
||||
erase 0xe0000000 31
|
||||
erase 0xe0000000 32
|
||||
erase 0xe0000000 33
|
||||
erase 0xe0000000 34
|
||||
erase 0xe0000000 35
|
||||
erase 0xe0000000 36
|
||||
erase 0xe0000000 37
|
||||
erase 0xe0000000 38
|
||||
erase 0xe0000000 39
|
||||
|
||||
load ../../emutos/emutos-m548x-bas.elf
|
||||
Binary file not shown.
File diff suppressed because it is too large
Load Diff
@@ -1,55 +0,0 @@
|
||||
#!/usr/local/bin/bdmctrl -D2 -v9 -d9
|
||||
#
|
||||
# firebee board initialization for bdmctrl
|
||||
#
|
||||
open $1
|
||||
reset
|
||||
sleep 1
|
||||
|
||||
wait
|
||||
|
||||
# set VBR
|
||||
write-ctrl 0x0801 0x00000000
|
||||
dump-register VBR
|
||||
|
||||
# Turn on MBAR at 0x1000_0000
|
||||
write-ctrl 0x0C0F 0x10000000
|
||||
dump-register MBAR
|
||||
|
||||
# Turn on RAMBAR0 at address 20000000
|
||||
write-ctrl 0x0C04 0x20000021
|
||||
|
||||
# Turn on RAMBAR1 at address 20001000
|
||||
write-ctrl 0x0C05 0x20001021
|
||||
|
||||
# Init CS0 (BootFLASH @ ff80_0000 - ff8F_FFFF 8Mbytes)
|
||||
write 0x10000500 0xff800000 4
|
||||
write 0x10000508 0x00041180 4
|
||||
write 0x10000504 0x003F0001 4
|
||||
wait
|
||||
|
||||
# SDRAM Initialization @ 0000_0000 - 03FF_FFFF 64 MBytes
|
||||
write 0x10000004 0x000002AA 4 # SDRAMDS configuration
|
||||
write 0x10000020 0x00000019 4 # SDRAM CS0 configuration (64Mbytes 0000_0000 - 03FF_FFFF)
|
||||
write 0x10000024 0x00000000 4 # SDRAM CS1 configuration
|
||||
write 0x10000028 0x00000000 4 # SDRAM CS2 configuration
|
||||
write 0x1000002C 0x00000000 4 # SDRAM CS3 configuration
|
||||
|
||||
write 0x10000108 0x73711630 4 # SDCFG1
|
||||
write 0x1000010C 0x46370000 4 # SDCFG2
|
||||
|
||||
write 0x10000104 0xE10B0002 4 # SDCR + IPALL
|
||||
write 0x10000100 0x40010000 4 # SDMR (write to LEMR)
|
||||
write 0x10000100 0x058D0000 4 # SDMR (write to LMR)
|
||||
sleep 100
|
||||
write 0x10000104 0xE10D0002 4 # SDCR + IPALL
|
||||
write 0x10000104 0xE10D0004 4 # SDCR + IREF (first refresh)
|
||||
write 0x10000104 0xE10D0004 4 # SDCR + IREF (first refresh)
|
||||
write 0x10000100 0x018D0000 4 # SDMR (write to LMR)
|
||||
write 0x10000104 0x710D0F00 4 # SDCR (lock SDMR and enable refresh)
|
||||
sleep 100
|
||||
|
||||
load m548xlite_dbug_ram.elf
|
||||
|
||||
execute
|
||||
wait
|
||||
3798
BaS_gcc/fs/cc932.c
3798
BaS_gcc/fs/cc932.c
File diff suppressed because it is too large
Load Diff
10973
BaS_gcc/fs/cc936.c
10973
BaS_gcc/fs/cc936.c
File diff suppressed because it is too large
Load Diff
8603
BaS_gcc/fs/cc949.c
8603
BaS_gcc/fs/cc949.c
File diff suppressed because it is too large
Load Diff
6829
BaS_gcc/fs/cc950.c
6829
BaS_gcc/fs/cc950.c
File diff suppressed because it is too large
Load Diff
@@ -1,619 +0,0 @@
|
||||
/*------------------------------------------------------------------------*/
|
||||
/* Unicode - Local code bidirectional converter (C)ChaN, 2009 */
|
||||
/* (SBCS code pages) */
|
||||
/*------------------------------------------------------------------------*/
|
||||
/* 437 U.S. (OEM)
|
||||
/ 720 Arabic (OEM)
|
||||
/ 1256 Arabic (Windows)
|
||||
/ 737 Greek (OEM)
|
||||
/ 1253 Greek (Windows)
|
||||
/ 1250 Central Europe (Windows)
|
||||
/ 775 Baltic (OEM)
|
||||
/ 1257 Baltic (Windows)
|
||||
/ 850 Multilingual Latin 1 (OEM)
|
||||
/ 852 Latin 2 (OEM)
|
||||
/ 1252 Latin 1 (Windows)
|
||||
/ 855 Cyrillic (OEM)
|
||||
/ 1251 Cyrillic (Windows)
|
||||
/ 866 Russian (OEM)
|
||||
/ 857 Turkish (OEM)
|
||||
/ 1254 Turkish (Windows)
|
||||
/ 858 Multilingual Latin 1 + Euro (OEM)
|
||||
/ 862 Hebrew (OEM)
|
||||
/ 1255 Hebrew (Windows)
|
||||
/ 874 Thai (OEM, Windows)
|
||||
/ 1258 Vietnam (OEM, Windows)
|
||||
*/
|
||||
|
||||
#include <ff.h>
|
||||
#include <bas_types.h>
|
||||
|
||||
#if _CODE_PAGE == 437
|
||||
#define _TBLDEF 1
|
||||
static
|
||||
const uint16_t Tbl[] =
|
||||
{
|
||||
/* CP437(0x80-0xFF) to Unicode conversion table */
|
||||
0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7,
|
||||
0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5,
|
||||
0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9,
|
||||
0x00FF, 0x00D6, 0x00DC, 0x00A2, 0x00A3, 0x00A5, 0x20A7, 0x0192,
|
||||
0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA,
|
||||
0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB,
|
||||
0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556,
|
||||
0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
|
||||
0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F,
|
||||
0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
|
||||
0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B,
|
||||
0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
|
||||
0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4,
|
||||
0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229,
|
||||
0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248,
|
||||
0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0
|
||||
};
|
||||
|
||||
#elif _CODE_PAGE == 720
|
||||
#define _TBLDEF 1
|
||||
static
|
||||
const uint16_t Tbl[] =
|
||||
{
|
||||
/* CP720(0x80-0xFF) to Unicode conversion table */
|
||||
0x0000, 0x0000, 0x00E9, 0x00E2, 0x0000, 0x00E0, 0x0000, 0x00E7,
|
||||
0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x0000, 0x0000, 0x0000,
|
||||
0x0000, 0x0651, 0x0652, 0x00F4, 0x00A4, 0x0640, 0x00FB, 0x00F9,
|
||||
0x0621, 0x0622, 0x0623, 0x0624, 0x00A3, 0x0625, 0x0626, 0x0627,
|
||||
0x0628, 0x0629, 0x062A, 0x062B, 0x062C, 0x062D, 0x062E, 0x062F,
|
||||
0x0630, 0x0631, 0x0632, 0x0633, 0x0634, 0x0635, 0x00AB, 0x00BB,
|
||||
0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556,
|
||||
0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
|
||||
0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F,
|
||||
0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
|
||||
0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B,
|
||||
0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
|
||||
0x0636, 0x0637, 0x0638, 0x0639, 0x063A, 0x0641, 0x00B5, 0x0642,
|
||||
0x0643, 0x0644, 0x0645, 0x0646, 0x0647, 0x0648, 0x0649, 0x064A,
|
||||
0x2261, 0x064B, 0x064C, 0x064D, 0x064E, 0x064F, 0xO650, 0x2248,
|
||||
0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0
|
||||
};
|
||||
|
||||
#elif _CODE_PAGE == 737
|
||||
#define _TBLDEF 1
|
||||
static
|
||||
const uint16_t Tbl[] =
|
||||
{
|
||||
/* CP737(0x80-0xFF) to Unicode conversion table */
|
||||
0x0391, 0x0392, 0x0393, 0x0394, 0x0395, 0x0396, 0x0397, 0x0398,
|
||||
0x0399, 0x039A, 0x039B, 0x039C, 0x039D, 0x039E, 0x039F, 0x03A0,
|
||||
0x03A1, 0x03A3, 0x03A4, 0x03A5, 0x03A6, 0x03A7, 0x03A8, 0x03A9,
|
||||
0x03B1, 0x03B2, 0x03B3, 0x03B4, 0x03B5, 0x03B6, 0x03B7, 0x03B8,
|
||||
0x03B9, 0x03BA, 0x03BB, 0x03BC, 0x03BD, 0x03BE, 0x03BF, 0x03C0,
|
||||
0x03C1, 0x03C3, 0x03C2, 0x03C4, 0x03C5, 0x03C6, 0x03C7, 0x03C8,
|
||||
0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556,
|
||||
0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
|
||||
0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F,
|
||||
0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
|
||||
0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B,
|
||||
0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
|
||||
0x03C9, 0x03AC, 0x03AD, 0x03AE, 0x03CA, 0x03AF, 0x03CC, 0x03CD,
|
||||
0x03CB, 0x03CE, 0x0386, 0x0388, 0x0389, 0x038A, 0x038C, 0x038E,
|
||||
0x038F, 0x00B1, 0x2265, 0x2264, 0x03AA, 0x03AB, 0x00F7, 0x2248,
|
||||
0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0
|
||||
};
|
||||
|
||||
#elif _CODE_PAGE == 775
|
||||
#define _TBLDEF 1
|
||||
static
|
||||
const uint16_t Tbl[] =
|
||||
{
|
||||
/* CP775(0x80-0xFF) to Unicode conversion table */
|
||||
0x0106, 0x00FC, 0x00E9, 0x0101, 0x00E4, 0x0123, 0x00E5, 0x0107,
|
||||
0x0142, 0x0113, 0x0156, 0x0157, 0x012B, 0x0179, 0x00C4, 0x00C5,
|
||||
0x00C9, 0x00E6, 0x00C6, 0x014D, 0x00F6, 0x0122, 0x00A2, 0x015A,
|
||||
0x015B, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x00A4,
|
||||
0x0100, 0x012A, 0x00F3, 0x017B, 0x017C, 0x017A, 0x201D, 0x00A6,
|
||||
0x00A9, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x0141, 0x00AB, 0x00BB,
|
||||
0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x0104, 0x010C, 0x0118,
|
||||
0x0116, 0x2563, 0x2551, 0x2557, 0x255D, 0x012E, 0x0160, 0x2510,
|
||||
0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x0172, 0x016A,
|
||||
0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x017D,
|
||||
0x0105, 0x010D, 0x0119, 0x0117, 0x012F, 0x0161, 0x0173, 0x016B,
|
||||
0x017E, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
|
||||
0x00D3, 0x00DF, 0x014C, 0x0143, 0x00F5, 0x00D5, 0x00B5, 0x0144,
|
||||
0x0136, 0x0137, 0x013B, 0x013C, 0x0146, 0x0112, 0x0145, 0x2019,
|
||||
0x00AD, 0x00B1, 0x201C, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x201E,
|
||||
0x00B0, 0x2219, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0
|
||||
};
|
||||
|
||||
#elif _CODE_PAGE == 850
|
||||
#define _TBLDEF 1
|
||||
static
|
||||
const uint16_t Tbl[] =
|
||||
{
|
||||
/* CP850(0x80-0xFF) to Unicode conversion table */
|
||||
0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7,
|
||||
0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5,
|
||||
0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9,
|
||||
0x00FF, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x0192,
|
||||
0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA,
|
||||
0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB,
|
||||
0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0,
|
||||
0x00A9, 0x2563, 0x2551, 0x2557, 0x255D, 0x00A2, 0x00A5, 0x2510,
|
||||
0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3,
|
||||
0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4,
|
||||
0x00F0, 0x00D0, 0x00CA, 0x00CB, 0x00C8, 0x0131, 0x00CD, 0x00CE,
|
||||
0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00A6, 0x00CC, 0x2580,
|
||||
0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x00FE,
|
||||
0x00DE, 0x00DA, 0x00DB, 0x00D9, 0x00FD, 0x00DD, 0x00AF, 0x00B4,
|
||||
0x00AD, 0x00B1, 0x2017, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8,
|
||||
0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0
|
||||
};
|
||||
|
||||
#elif _CODE_PAGE == 852
|
||||
#define _TBLDEF 1
|
||||
static
|
||||
const uint16_t Tbl[] =
|
||||
{
|
||||
/* CP852(0x80-0xFF) to Unicode conversion table */
|
||||
0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x016F, 0x0107, 0x00E7,
|
||||
0x0142, 0x00EB, 0x0150, 0x0151, 0x00EE, 0x0179, 0x00C4, 0x0106,
|
||||
0x00C9, 0x0139, 0x013A, 0x00F4, 0x00F6, 0x013D, 0x013E, 0x015A,
|
||||
0x015B, 0x00D6, 0x00DC, 0x0164, 0x0165, 0x0141, 0x00D7, 0x010D,
|
||||
0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x0104, 0x0105, 0x017D, 0x017E,
|
||||
0x0118, 0x0119, 0x00AC, 0x017A, 0x010C, 0x015F, 0x00AB, 0x00BB,
|
||||
0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x011A,
|
||||
0x015E, 0x2563, 0x2551, 0x2557, 0x255D, 0x017B, 0x017C, 0x2510,
|
||||
0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x0102, 0x0103,
|
||||
0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4,
|
||||
0x0111, 0x0110, 0x010E, 0x00CB, 0x010F, 0x0147, 0x00CD, 0x00CE,
|
||||
0x011B, 0x2518, 0x250C, 0x2588, 0x2584, 0x0162, 0x016E, 0x2580,
|
||||
0x00D3, 0x00DF, 0x00D4, 0x0143, 0x0144, 0x0148, 0x0160, 0x0161,
|
||||
0x0154, 0x00DA, 0x0155, 0x0170, 0x00FD, 0x00DD, 0x0163, 0x00B4,
|
||||
0x00AD, 0x02DD, 0x02DB, 0x02C7, 0x02D8, 0x00A7, 0x00F7, 0x00B8,
|
||||
0x00B0, 0x00A8, 0x02D9, 0x0171, 0x0158, 0x0159, 0x25A0, 0x00A0
|
||||
};
|
||||
|
||||
#elif _CODE_PAGE == 855
|
||||
#define _TBLDEF 1
|
||||
static
|
||||
const uint16_t Tbl[] =
|
||||
{
|
||||
/* CP855(0x80-0xFF) to Unicode conversion table */
|
||||
0x0452, 0x0402, 0x0453, 0x0403, 0x0451, 0x0401, 0x0454, 0x0404,
|
||||
0x0455, 0x0405, 0x0456, 0x0406, 0x0457, 0x0407, 0x0458, 0x0408,
|
||||
0x0459, 0x0409, 0x045A, 0x040A, 0x045B, 0x040B, 0x045C, 0x040C,
|
||||
0x045E, 0x040E, 0x045F, 0x040F, 0x044E, 0x042E, 0x044A, 0x042A,
|
||||
0x0430, 0x0410, 0x0431, 0x0411, 0x0446, 0x0426, 0x0434, 0x0414,
|
||||
0x0435, 0x0415, 0x0444, 0x0424, 0x0433, 0x0413, 0x00AB, 0x00BB,
|
||||
0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x0445, 0x0425, 0x0438,
|
||||
0x0418, 0x2563, 0x2551, 0x2557, 0x255D, 0x0439, 0x0419, 0x2510,
|
||||
0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x043A, 0x041A,
|
||||
0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4,
|
||||
0x043B, 0x041B, 0x043C, 0x041C, 0x043D, 0x041D, 0x043E, 0x041E,
|
||||
0x043F, 0x2518, 0x250C, 0x2588, 0x2584, 0x041F, 0x044F, 0x2580,
|
||||
0x042F, 0x0440, 0x0420, 0x0441, 0x0421, 0x0442, 0x0422, 0x0443,
|
||||
0x0423, 0x0436, 0x0416, 0x0432, 0x0412, 0x044C, 0x042C, 0x2116,
|
||||
0x00AD, 0x044B, 0x042B, 0x0437, 0x0417, 0x0448, 0x0428, 0x044D,
|
||||
0x042D, 0x0449, 0x0429, 0x0447, 0x0427, 0x00A7, 0x25A0, 0x00A0
|
||||
};
|
||||
|
||||
#elif _CODE_PAGE == 857
|
||||
#define _TBLDEF 1
|
||||
static
|
||||
const uint16_t Tbl[] =
|
||||
{
|
||||
/* CP857(0x80-0xFF) to Unicode conversion table */
|
||||
0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7,
|
||||
0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x0131, 0x00C4, 0x00C5,
|
||||
0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9,
|
||||
0x0130, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x015E, 0x015F,
|
||||
0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x011E, 0x011F,
|
||||
0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB,
|
||||
0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0,
|
||||
0x00A9, 0x2563, 0x2551, 0x2557, 0x255D, 0x00A2, 0x00A5, 0x2510,
|
||||
0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3,
|
||||
0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4,
|
||||
0x00BA, 0x00AA, 0x00CA, 0x00CB, 0x00C8, 0x0000, 0x00CD, 0x00CE,
|
||||
0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00A6, 0x00CC, 0x2580,
|
||||
0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x0000,
|
||||
0x00D7, 0x00DA, 0x00DB, 0x00D9, 0x00EC, 0x00FF, 0x00AF, 0x00B4,
|
||||
0x00AD, 0x00B1, 0x0000, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8,
|
||||
0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0
|
||||
};
|
||||
|
||||
#elif _CODE_PAGE == 858
|
||||
#define _TBLDEF 1
|
||||
static
|
||||
const uint16_t Tbl[] =
|
||||
{
|
||||
/* CP858(0x80-0xFF) to Unicode conversion table */
|
||||
0x00C7, 0x00FC, 0x00E9, 0x00E2, 0x00E4, 0x00E0, 0x00E5, 0x00E7,
|
||||
0x00EA, 0x00EB, 0x00E8, 0x00EF, 0x00EE, 0x00EC, 0x00C4, 0x00C5,
|
||||
0x00C9, 0x00E6, 0x00C6, 0x00F4, 0x00F6, 0x00F2, 0x00FB, 0x00F9,
|
||||
0x00FF, 0x00D6, 0x00DC, 0x00F8, 0x00A3, 0x00D8, 0x00D7, 0x0192,
|
||||
0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA,
|
||||
0x00BF, 0x00AE, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB,
|
||||
0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x00C1, 0x00C2, 0x00C0,
|
||||
0x00A9, 0x2563, 0x2551, 0x2557, 0x2550, 0x00A2, 0x00A5, 0x2510,
|
||||
0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x00E3, 0x00C3,
|
||||
0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x00A4,
|
||||
0x00F0, 0x00D0, 0x00CA, 0x00CB, 0x00C8, 0x20AC, 0x00CD, 0x00CE,
|
||||
0x00CF, 0x2518, 0x250C, 0x2588, 0x2584, 0x00C6, 0x00CC, 0x2580,
|
||||
0x00D3, 0x00DF, 0x00D4, 0x00D2, 0x00F5, 0x00D5, 0x00B5, 0x00FE,
|
||||
0x00DE, 0x00DA, 0x00DB, 0x00D9, 0x00FD, 0x00DD, 0x00AF, 0x00B4,
|
||||
0x00AD, 0x00B1, 0x2017, 0x00BE, 0x00B6, 0x00A7, 0x00F7, 0x00B8,
|
||||
0x00B0, 0x00A8, 0x00B7, 0x00B9, 0x00B3, 0x00B2, 0x25A0, 0x00A0
|
||||
};
|
||||
|
||||
#elif _CODE_PAGE == 862
|
||||
#define _TBLDEF 1
|
||||
static
|
||||
const uint16_t Tbl[] =
|
||||
{
|
||||
/* CP862(0x80-0xFF) to Unicode conversion table */
|
||||
0x05D0, 0x05D1, 0x05D2, 0x05D3, 0x05D4, 0x05D5, 0x05D6, 0x05D7,
|
||||
0x05D8, 0x05D9, 0x05DA, 0x05DB, 0x05DC, 0x05DD, 0x05DE, 0x05DF,
|
||||
0x05E0, 0x05E1, 0x05E2, 0x05E3, 0x05E4, 0x05E5, 0x05E6, 0x05E7,
|
||||
0x05E8, 0x05E9, 0x05EA, 0x00A2, 0x00A3, 0x00A5, 0x20A7, 0x0192,
|
||||
0x00E1, 0x00ED, 0x00F3, 0x00FA, 0x00F1, 0x00D1, 0x00AA, 0x00BA,
|
||||
0x00BF, 0x2310, 0x00AC, 0x00BD, 0x00BC, 0x00A1, 0x00AB, 0x00BB,
|
||||
0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556,
|
||||
0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
|
||||
0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F,
|
||||
0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
|
||||
0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B,
|
||||
0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
|
||||
0x03B1, 0x00DF, 0x0393, 0x03C0, 0x03A3, 0x03C3, 0x00B5, 0x03C4,
|
||||
0x03A6, 0x0398, 0x03A9, 0x03B4, 0x221E, 0x03C6, 0x03B5, 0x2229,
|
||||
0x2261, 0x00B1, 0x2265, 0x2264, 0x2320, 0x2321, 0x00F7, 0x2248,
|
||||
0x00B0, 0x2219, 0x00B7, 0x221A, 0x207F, 0x00B2, 0x25A0, 0x00A0
|
||||
};
|
||||
|
||||
#elif _CODE_PAGE == 866
|
||||
#define _TBLDEF 1
|
||||
static
|
||||
const uint16_t Tbl[] =
|
||||
{
|
||||
/* CP866(0x80-0xFF) to Unicode conversion table */
|
||||
0x0410, 0x0411, 0x0412, 0x0413, 0x0414, 0x0415, 0x0416, 0x0417,
|
||||
0x0418, 0x0419, 0x041A, 0x041B, 0x041C, 0x041D, 0x041E, 0x041F,
|
||||
0x0420, 0x0421, 0x0422, 0x0423, 0x0424, 0x0425, 0x0426, 0x0427,
|
||||
0x0428, 0x0429, 0x042A, 0x042B, 0x042C, 0x042D, 0x042E, 0x042F,
|
||||
0x0430, 0x0431, 0x0432, 0x0433, 0x0434, 0x0435, 0x0436, 0x0437,
|
||||
0x0438, 0x0439, 0x043A, 0x043B, 0x043C, 0x043D, 0x043E, 0x043F,
|
||||
0x2591, 0x2592, 0x2593, 0x2502, 0x2524, 0x2561, 0x2562, 0x2556,
|
||||
0x2555, 0x2563, 0x2551, 0x2557, 0x255D, 0x255C, 0x255B, 0x2510,
|
||||
0x2514, 0x2534, 0x252C, 0x251C, 0x2500, 0x253C, 0x255E, 0x255F,
|
||||
0x255A, 0x2554, 0x2569, 0x2566, 0x2560, 0x2550, 0x256C, 0x2567,
|
||||
0x2568, 0x2564, 0x2565, 0x2559, 0x2558, 0x2552, 0x2553, 0x256B,
|
||||
0x256A, 0x2518, 0x250C, 0x2588, 0x2584, 0x258C, 0x2590, 0x2580,
|
||||
0x0440, 0x0441, 0x0442, 0x0443, 0x0444, 0x0445, 0x0446, 0x0447,
|
||||
0x0448, 0x0449, 0x044A, 0x044B, 0x044C, 0x044D, 0x044E, 0x044F,
|
||||
0x0401, 0x0451, 0x0404, 0x0454, 0x0407, 0x0457, 0x040E, 0x045E,
|
||||
0x00B0, 0x2219, 0x00B7, 0x221A, 0x2116, 0x00A4, 0x25A0, 0x00A0
|
||||
};
|
||||
|
||||
#elif _CODE_PAGE == 874
|
||||
#define _TBLDEF 1
|
||||
static
|
||||
const uint16_t Tbl[] =
|
||||
{
|
||||
/* CP874(0x80-0xFF) to Unicode conversion table */
|
||||
0x20AC, 0x0000, 0x0000, 0x0000, 0x0000, 0x2026, 0x0000, 0x0000,
|
||||
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
|
||||
0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
|
||||
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
|
||||
0x00A0, 0x0E01, 0x0E02, 0x0E03, 0x0E04, 0x0E05, 0x0E06, 0x0E07,
|
||||
0x0E08, 0x0E09, 0x0E0A, 0x0E0B, 0x0E0C, 0x0E0D, 0x0E0E, 0x0E0F,
|
||||
0x0E10, 0x0E11, 0x0E12, 0x0E13, 0x0E14, 0x0E15, 0x0E16, 0x0E17,
|
||||
0x0E18, 0x0E19, 0x0E1A, 0x0E1B, 0x0E1C, 0x0E1D, 0x0E1E, 0x0E1F,
|
||||
0x0E20, 0x0E21, 0x0E22, 0x0E23, 0x0E24, 0x0E25, 0x0E26, 0x0E27,
|
||||
0x0E28, 0x0E29, 0x0E2A, 0x0E2B, 0x0E2C, 0x0E2D, 0x0E2E, 0x0E2F,
|
||||
0x0E30, 0x0E31, 0x0E32, 0x0E33, 0x0E34, 0x0E35, 0x0E36, 0x0E37,
|
||||
0x0E38, 0x0E39, 0x0E3A, 0x0000, 0x0000, 0x0000, 0x0000, 0x0E3F,
|
||||
0x0E40, 0x0E41, 0x0E42, 0x0E43, 0x0E44, 0x0E45, 0x0E46, 0x0E47,
|
||||
0x0E48, 0x0E49, 0x0E4A, 0x0E4B, 0x0E4C, 0x0E4D, 0x0E4E, 0x0E4F,
|
||||
0x0E50, 0x0E51, 0x0E52, 0x0E53, 0x0E54, 0x0E55, 0x0E56, 0x0E57,
|
||||
0x0E58, 0x0E59, 0x0E5A, 0x0E5B, 0x0000, 0x0000, 0x0000, 0x0000
|
||||
};
|
||||
|
||||
#elif _CODE_PAGE == 1250
|
||||
#define _TBLDEF 1
|
||||
static
|
||||
const uint16_t Tbl[] =
|
||||
{
|
||||
/* CP1250(0x80-0xFF) to Unicode conversion table */
|
||||
0x20AC, 0x0000, 0x201A, 0x0000, 0x201E, 0x2026, 0x2020, 0x2021,
|
||||
0x0000, 0x2030, 0x0160, 0x2039, 0x015A, 0x0164, 0x017D, 0x0179,
|
||||
0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
|
||||
0x0000, 0x2122, 0x0161, 0x203A, 0x015B, 0x0165, 0x017E, 0x017A,
|
||||
0x00A0, 0x02C7, 0x02D8, 0x0141, 0x00A4, 0x0104, 0x00A6, 0x00A7,
|
||||
0x00A8, 0x00A9, 0x015E, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x017B,
|
||||
0x00B0, 0x00B1, 0x02DB, 0x0142, 0x00B4, 0x00B5, 0x00B6, 0x00B7,
|
||||
0x00B8, 0x0105, 0x015F, 0x00BB, 0x013D, 0x02DD, 0x013E, 0x017C,
|
||||
0x0154, 0x00C1, 0x00C2, 0x0102, 0x00C4, 0x0139, 0x0106, 0x00C7,
|
||||
0x010C, 0x00C9, 0x0118, 0x00CB, 0x011A, 0x00CD, 0x00CE, 0x010E,
|
||||
0x0110, 0x0143, 0x0147, 0x00D3, 0x00D4, 0x0150, 0x00D6, 0x00D7,
|
||||
0x0158, 0x016E, 0x00DA, 0x0170, 0x00DC, 0x00DD, 0x0162, 0x00DF,
|
||||
0x0155, 0x00E1, 0x00E2, 0x0103, 0x00E4, 0x013A, 0x0107, 0x00E7,
|
||||
0x010D, 0x00E9, 0x0119, 0x00EB, 0x011B, 0x00ED, 0x00EE, 0x010F,
|
||||
0x0111, 0x0144, 0x0148, 0x00F3, 0x00F4, 0x0151, 0x00F6, 0x00F7,
|
||||
0x0159, 0x016F, 0x00FA, 0x0171, 0x00FC, 0x00FD, 0x0163, 0x02D9
|
||||
};
|
||||
|
||||
#elif _CODE_PAGE == 1251
|
||||
#define _TBLDEF 1
|
||||
static
|
||||
const uint16_t Tbl[] =
|
||||
{
|
||||
/* CP1251(0x80-0xFF) to Unicode conversion table */
|
||||
0x0402, 0x0403, 0x201A, 0x0453, 0x201E, 0x2026, 0x2020, 0x2021,
|
||||
0x20AC, 0x2030, 0x0409, 0x2039, 0x040A, 0x040C, 0x040B, 0x040F,
|
||||
0x0452, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
|
||||
0x0000, 0x2111, 0x0459, 0x203A, 0x045A, 0x045C, 0x045B, 0x045F,
|
||||
0x00A0, 0x040E, 0x045E, 0x0408, 0x00A4, 0x0490, 0x00A6, 0x00A7,
|
||||
0x0401, 0x00A9, 0x0404, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x0407,
|
||||
0x00B0, 0x00B1, 0x0406, 0x0456, 0x0491, 0x00B5, 0x00B6, 0x00B7,
|
||||
0x0451, 0x2116, 0x0454, 0x00BB, 0x0458, 0x0405, 0x0455, 0x0457,
|
||||
0x0410, 0x0411, 0x0412, 0x0413, 0x0414, 0x0415, 0x0416, 0x0417,
|
||||
0x0418, 0x0419, 0x041A, 0x041B, 0x041C, 0x041D, 0x041E, 0x041F,
|
||||
0x0420, 0x0421, 0x0422, 0x0423, 0x0424, 0x0425, 0x0426, 0x0427,
|
||||
0x0428, 0x0429, 0x042A, 0x042B, 0x042C, 0x042D, 0x042E, 0x042F,
|
||||
0x0430, 0x0431, 0x0432, 0x0433, 0x0434, 0x0435, 0x0436, 0x0437,
|
||||
0x0438, 0x0439, 0x043A, 0x043B, 0x043C, 0x043D, 0x043E, 0x043F,
|
||||
0x0440, 0x0441, 0x0442, 0x0443, 0x0444, 0x0445, 0x0446, 0x0447,
|
||||
0x0448, 0x0449, 0x044A, 0x044B, 0x044C, 0x044D, 0x044E, 0x044F
|
||||
};
|
||||
|
||||
#elif _CODE_PAGE == 1252
|
||||
#define _TBLDEF 1
|
||||
static
|
||||
const uint16_t Tbl[] =
|
||||
{
|
||||
/* CP1252(0x80-0xFF) to Unicode conversion table */
|
||||
0x20AC, 0x0000, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021,
|
||||
0x02C6, 0x2030, 0x0160, 0x2039, 0x0152, 0x0000, 0x017D, 0x0000,
|
||||
0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
|
||||
0x02DC, 0x2122, 0x0161, 0x203A, 0x0153, 0x0000, 0x017E, 0x0178,
|
||||
0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7,
|
||||
0x00A8, 0x00A9, 0x00AA, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF,
|
||||
0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7,
|
||||
0x00B8, 0x00B9, 0x00BA, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF,
|
||||
0x00C0, 0x00C1, 0x00C2, 0x00C3, 0x00C4, 0x00C5, 0x00C6, 0x00C7,
|
||||
0x00C8, 0x00C9, 0x00CA, 0x00CB, 0x00CC, 0x00CD, 0x00CE, 0x00CF,
|
||||
0x00D0, 0x00D1, 0x00D2, 0x00D3, 0x00D4, 0x00D5, 0x00D6, 0x00D7,
|
||||
0x00D8, 0x00D9, 0x00DA, 0x00DB, 0x00DC, 0x00DD, 0x00DE, 0x00DF,
|
||||
0x00E0, 0x00E1, 0x00E2, 0x00E3, 0x00E4, 0x00E5, 0x00E6, 0x00E7,
|
||||
0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x00EC, 0x00ED, 0x00EE, 0x00EF,
|
||||
0x00F0, 0x00F1, 0x00F2, 0x00F3, 0x00F4, 0x00F5, 0x00F6, 0x00F7,
|
||||
0x00F8, 0x00F9, 0x00FA, 0x00FB, 0x00FC, 0x00FD, 0x00FE, 0x00FF
|
||||
};
|
||||
|
||||
#elif _CODE_PAGE == 1253
|
||||
#define _TBLDEF 1
|
||||
static
|
||||
const uint16_t Tbl[] =
|
||||
{
|
||||
/* CP1253(0x80-0xFF) to Unicode conversion table */
|
||||
0x20AC, 0x0000, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021,
|
||||
0x0000, 0x2030, 0x0000, 0x2039, 0x000C, 0x0000, 0x0000, 0x0000,
|
||||
0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
|
||||
0x0000, 0x2122, 0x0000, 0x203A, 0x0000, 0x0000, 0x0000, 0x0000,
|
||||
0x00A0, 0x0385, 0x0386, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7,
|
||||
0x00A8, 0x00A9, 0x0000, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x2015,
|
||||
0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x0384, 0x00B5, 0x00B6, 0x00B7,
|
||||
0x0388, 0x0389, 0x038A, 0x00BB, 0x038C, 0x00BD, 0x038E, 0x038F,
|
||||
0x0390, 0x0391, 0x0392, 0x0393, 0x0394, 0x0395, 0x0396, 0x0397,
|
||||
0x0398, 0x0399, 0x039A, 0x039B, 0x039C, 0x039D, 0x039E, 0x039F,
|
||||
0x03A0, 0x03A1, 0x0000, 0x03A3, 0x03A4, 0x03A5, 0x03A6, 0x03A7,
|
||||
0x03A8, 0x03A9, 0x03AA, 0x03AD, 0x03AC, 0x03AD, 0x03AE, 0x03AF,
|
||||
0x03B0, 0x03B1, 0x03B2, 0x03B3, 0x03B4, 0x03B5, 0x03B6, 0x03B7,
|
||||
0x03B8, 0x03B9, 0x03BA, 0x03BB, 0x03BC, 0x03BD, 0x03BE, 0x03BF,
|
||||
0x03C0, 0x03C1, 0x03C2, 0x03C3, 0x03C4, 0x03C5, 0x03C6, 0x03C7,
|
||||
0x03C8, 0x03C9, 0x03CA, 0x03CB, 0x03CC, 0x03CD, 0x03CE, 0x0000
|
||||
};
|
||||
|
||||
#elif _CODE_PAGE == 1254
|
||||
#define _TBLDEF 1
|
||||
static
|
||||
const uint16_t Tbl[] =
|
||||
{
|
||||
/* CP1254(0x80-0xFF) to Unicode conversion table */
|
||||
0x20AC, 0x0000, 0x210A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021,
|
||||
0x02C6, 0x2030, 0x0160, 0x2039, 0x0152, 0x0000, 0x0000, 0x0000,
|
||||
0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
|
||||
0x02DC, 0x2122, 0x0161, 0x203A, 0x0153, 0x0000, 0x0000, 0x0178,
|
||||
0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7,
|
||||
0x00A8, 0x00A9, 0x00AA, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF,
|
||||
0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7,
|
||||
0x00B8, 0x00B9, 0x00BA, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF,
|
||||
0x00C0, 0x00C1, 0x00C2, 0x00C3, 0x00C4, 0x00C5, 0x00C6, 0x00C7,
|
||||
0x00C8, 0x00C9, 0x00CA, 0x00CB, 0x00CC, 0x00CD, 0x00CE, 0x00CF,
|
||||
0x011E, 0x00D1, 0x00D2, 0x00D3, 0x00D4, 0x00D5, 0x00D6, 0x00D7,
|
||||
0x00D8, 0x00D9, 0x00DA, 0x00BD, 0x00DC, 0x0130, 0x015E, 0x00DF,
|
||||
0x00E0, 0x00E1, 0x00E2, 0x00E3, 0x00E4, 0x00E5, 0x00E6, 0x00E7,
|
||||
0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x00EC, 0x00ED, 0x00EE, 0x00EF,
|
||||
0x011F, 0x00F1, 0x00F2, 0x00F3, 0x00F4, 0x00F5, 0x00F6, 0x00F7,
|
||||
0x00F8, 0x00F9, 0x00FA, 0x00FB, 0x00FC, 0x0131, 0x015F, 0x00FF
|
||||
};
|
||||
|
||||
#elif _CODE_PAGE == 1255
|
||||
#define _TBLDEF 1
|
||||
static
|
||||
const uint16_t Tbl[] =
|
||||
{
|
||||
/* CP1255(0x80-0xFF) to Unicode conversion table */
|
||||
0x20AC, 0x0000, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021,
|
||||
0x02C6, 0x2030, 0x0000, 0x2039, 0x0000, 0x0000, 0x0000, 0x0000,
|
||||
0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
|
||||
0x02DC, 0x2122, 0x0000, 0x203A, 0x0000, 0x0000, 0x0000, 0x0000,
|
||||
0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7,
|
||||
0x00A8, 0x00A9, 0x00D7, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF,
|
||||
0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7,
|
||||
0x00B8, 0x00B9, 0x00F7, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF,
|
||||
0x05B0, 0x05B1, 0x05B2, 0x05B3, 0x05B4, 0x05B5, 0x05B6, 0x05B7,
|
||||
0x05B8, 0x05B9, 0x0000, 0x05BB, 0x05BC, 0x05BD, 0x05BE, 0x05BF,
|
||||
0x05C0, 0x05C1, 0x05C2, 0x05C3, 0x05F0, 0x05F1, 0x05F2, 0x05F3,
|
||||
0x05F4, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000,
|
||||
0x05D0, 0x05D1, 0x05D2, 0x05D3, 0x05D4, 0x05D5, 0x05D6, 0x05D7,
|
||||
0x05D8, 0x05D9, 0x05DA, 0x05DB, 0x05DC, 0x05DD, 0x05DE, 0x05DF,
|
||||
0x05E0, 0x05E1, 0x05E2, 0x05E3, 0x05E4, 0x05E5, 0x05E6, 0x05E7,
|
||||
0x05E8, 0x05E9, 0x05EA, 0x0000, 0x0000, 0x200E, 0x200F, 0x0000
|
||||
};
|
||||
|
||||
#elif _CODE_PAGE == 1256
|
||||
#define _TBLDEF 1
|
||||
static
|
||||
const uint16_t Tbl[] =
|
||||
{
|
||||
/* CP1256(0x80-0xFF) to Unicode conversion table */
|
||||
0x20AC, 0x067E, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021,
|
||||
0x02C6, 0x2030, 0x0679, 0x2039, 0x0152, 0x0686, 0x0698, 0x0688,
|
||||
0x06AF, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
|
||||
0x06A9, 0x2122, 0x0691, 0x203A, 0x0153, 0x200C, 0x200D, 0x06BA,
|
||||
0x00A0, 0x060C, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7,
|
||||
0x00A8, 0x00A9, 0x06BE, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF,
|
||||
0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7,
|
||||
0x00B8, 0x00B9, 0x061B, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x061F,
|
||||
0x06C1, 0x0621, 0x0622, 0x0623, 0x0624, 0x0625, 0x0626, 0x0627,
|
||||
0x0628, 0x0629, 0x062A, 0x062B, 0x062C, 0x062D, 0x062E, 0x062F,
|
||||
0x0630, 0x0631, 0x0632, 0x0633, 0x0634, 0x0635, 0x0636, 0x00D7,
|
||||
0x0637, 0x0638, 0x0639, 0x063A, 0x0640, 0x0640, 0x0642, 0x0643,
|
||||
0x00E0, 0x0644, 0x00E2, 0x0645, 0x0646, 0x0647, 0x0648, 0x00E7,
|
||||
0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x0649, 0x064A, 0x00EE, 0x00EF,
|
||||
0x064B, 0x064C, 0x064D, 0x064E, 0x00F4, 0x064F, 0x0650, 0x00F7,
|
||||
0x0651, 0x00F9, 0x0652, 0x00FB, 0x00FC, 0x200E, 0x200F, 0x06D2
|
||||
}
|
||||
|
||||
#elif _CODE_PAGE == 1257
|
||||
#define _TBLDEF 1
|
||||
static
|
||||
const uint16_t Tbl[] =
|
||||
{
|
||||
/* CP1257(0x80-0xFF) to Unicode conversion table */
|
||||
0x20AC, 0x0000, 0x201A, 0x0000, 0x201E, 0x2026, 0x2020, 0x2021,
|
||||
0x0000, 0x2030, 0x0000, 0x2039, 0x0000, 0x00A8, 0x02C7, 0x00B8,
|
||||
0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
|
||||
0x0000, 0x2122, 0x0000, 0x203A, 0x0000, 0x00AF, 0x02DB, 0x0000,
|
||||
0x00A0, 0x0000, 0x00A2, 0x00A3, 0x00A4, 0x0000, 0x00A6, 0x00A7,
|
||||
0x00D8, 0x00A9, 0x0156, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF,
|
||||
0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7,
|
||||
0x00B8, 0x00B9, 0x0157, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00E6,
|
||||
0x0104, 0x012E, 0x0100, 0x0106, 0x00C4, 0x00C5, 0x0118, 0x0112,
|
||||
0x010C, 0x00C9, 0x0179, 0x0116, 0x0122, 0x0136, 0x012A, 0x013B,
|
||||
0x0160, 0x0143, 0x0145, 0x00D3, 0x014C, 0x00D5, 0x00D6, 0x00D7,
|
||||
0x0172, 0x0141, 0x015A, 0x016A, 0x00DC, 0x017B, 0x017D, 0x00DF,
|
||||
0x0105, 0x012F, 0x0101, 0x0107, 0x00E4, 0x00E5, 0x0119, 0x0113,
|
||||
0x010D, 0x00E9, 0x017A, 0x0117, 0x0123, 0x0137, 0x012B, 0x013C,
|
||||
0x0161, 0x0144, 0x0146, 0x00F3, 0x014D, 0x00F5, 0x00F6, 0x00F7,
|
||||
0x0173, 0x014E, 0x015B, 0x016B, 0x00FC, 0x017C, 0x017E, 0x02D9
|
||||
};
|
||||
|
||||
#elif _CODE_PAGE == 1258
|
||||
#define _TBLDEF 1
|
||||
static
|
||||
const uint16_t Tbl[] =
|
||||
{
|
||||
/* CP1258(0x80-0xFF) to Unicode conversion table */
|
||||
0x20AC, 0x0000, 0x201A, 0x0192, 0x201E, 0x2026, 0x2020, 0x2021,
|
||||
0x02C6, 0x2030, 0x0000, 0x2039, 0x0152, 0x0000, 0x0000, 0x0000,
|
||||
0x0000, 0x2018, 0x2019, 0x201C, 0x201D, 0x2022, 0x2013, 0x2014,
|
||||
0x02DC, 0x2122, 0x0000, 0x203A, 0x0153, 0x0000, 0x0000, 0x0178,
|
||||
0x00A0, 0x00A1, 0x00A2, 0x00A3, 0x00A4, 0x00A5, 0x00A6, 0x00A7,
|
||||
0x00A8, 0x00A9, 0x00AA, 0x00AB, 0x00AC, 0x00AD, 0x00AE, 0x00AF,
|
||||
0x00B0, 0x00B1, 0x00B2, 0x00B3, 0x00B4, 0x00B5, 0x00B6, 0x00B7,
|
||||
0x00B8, 0x00B9, 0x00BA, 0x00BB, 0x00BC, 0x00BD, 0x00BE, 0x00BF,
|
||||
0x00C0, 0x00C1, 0x00C2, 0x0102, 0x00C4, 0x00C5, 0x00C6, 0x00C7,
|
||||
0x00C8, 0x00C9, 0x00CA, 0x00CB, 0x0300, 0x00CD, 0x00CE, 0x00CF,
|
||||
0x0110, 0x00D1, 0x0309, 0x00D3, 0x00D4, 0x01A0, 0x00D6, 0x00D7,
|
||||
0x00D8, 0x00D9, 0x00DA, 0x00DB, 0x00DC, 0x01AF, 0x0303, 0x00DF,
|
||||
0x00E0, 0x00E1, 0x00E2, 0x0103, 0x00E4, 0x00E5, 0x00E6, 0x00E7,
|
||||
0x00E8, 0x00E9, 0x00EA, 0x00EB, 0x0301, 0x00ED, 0x00EE, 0x00EF,
|
||||
0x0111, 0x00F1, 0x0323, 0x00F3, 0x00F4, 0x01A1, 0x00F6, 0x00F7,
|
||||
0x00F8, 0x00F9, 0x00FA, 0x00FB, 0x00FC, 0x01B0, 0x20AB, 0x00FF
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
#if !_TBLDEF || !_USE_LFN
|
||||
#error This file is not needed in current configuration. Remove from the project.
|
||||
#endif
|
||||
|
||||
|
||||
uint16_t ff_convert ( /* Converted character, Returns zero on error */
|
||||
uint16_t src, /* Character code to be converted */
|
||||
uint32_t dir /* 0: Unicode to OEMCP, 1: OEMCP to Unicode */
|
||||
)
|
||||
{
|
||||
uint16_t c;
|
||||
|
||||
|
||||
if (src < 0x80) { /* ASCII */
|
||||
c = src;
|
||||
|
||||
} else {
|
||||
if (dir) { /* OEMCP to Unicode */
|
||||
c = (src >= 0x100) ? 0 : Tbl[src - 0x80];
|
||||
|
||||
} else { /* Unicode to OEMCP */
|
||||
for (c = 0; c < 0x80; c++) {
|
||||
if (src == Tbl[c]) break;
|
||||
}
|
||||
c = (c + 0x80) & 0xFF;
|
||||
}
|
||||
}
|
||||
|
||||
return c;
|
||||
}
|
||||
|
||||
|
||||
uint16_t ff_wtoupper ( /* Upper converted character */
|
||||
uint16_t chr /* Input character */
|
||||
)
|
||||
{
|
||||
static const uint16_t tbl_lower[] =
|
||||
{
|
||||
0x61, 0x62, 0x63, 0x64, 0x65, 0x66, 0x67, 0x68,
|
||||
0x69, 0x6A, 0x6B, 0x6C, 0x6D, 0x6E, 0x6F, 0x70,
|
||||
0x71, 0x72, 0x73, 0x74, 0x75, 0x76, 0x77, 0x78,
|
||||
0x79, 0x7A, 0xA1, 0x00A2, 0x00A3, 0x00A5, 0x00AC, 0x00AF,
|
||||
0xE0, 0xE1, 0xE2, 0xE3, 0xE4, 0xE5, 0xE6, 0xE7,
|
||||
0xE8, 0xE9, 0xEA, 0xEB, 0xEC, 0xED, 0xEE, 0xEF,
|
||||
0xF0, 0xF1, 0xF2, 0xF3, 0xF4, 0xF5, 0xF6, 0xF8,
|
||||
0xF9, 0xFA, 0xFB, 0xFC, 0xFD, 0xFE, 0x0FF, 0x101,
|
||||
0x103, 0x105, 0x107, 0x109, 0x10B, 0x10D, 0x10F,
|
||||
0x111, 0x113, 0x115, 0x117, 0x119, 0x11B, 0x11D,
|
||||
0x11F, 0x121, 0x123, 0x125, 0x127, 0x129, 0x12B,
|
||||
0x12D, 0x12F, 0x131, 0x133, 0x135, 0x137, 0x13A,
|
||||
0x13C, 0x13E, 0x140, 0x142, 0x144, 0x146, 0x148,
|
||||
0x14B, 0x14D, 0x14F, 0x151, 0x153, 0x155, 0x157,
|
||||
0x159, 0x15B, 0x15D, 0x15F, 0x161, 0x163, 0x165,
|
||||
0x167, 0x169, 0x16B, 0x16D, 0x16F, 0x171, 0x173,
|
||||
0x175, 0x177, 0x17A, 0x17C, 0x17E, 0x192, 0x3B1,
|
||||
0x3B2, 0x3B3, 0x3B4, 0x3B5, 0x3B6, 0x3B7, 0x3B8,
|
||||
0x3B9, 0x3BA, 0x3BB, 0x3BC, 0x3BD, 0x3BE, 0x3BF,
|
||||
0x3C0, 0x3C1, 0x3C3, 0x3C4, 0x3C5, 0x3C6, 0x3C7,
|
||||
0x3C8, 0x3C9, 0x3CA, 0x430, 0x431, 0x432, 0x433,
|
||||
0x434, 0x435, 0x436, 0x437, 0x438, 0x439, 0x43A,
|
||||
0x43B, 0x43C, 0x43D, 0x43E, 0x43F, 0x440, 0x441,
|
||||
0x442, 0x443, 0x444, 0x445, 0x446, 0x447, 0x448,
|
||||
0x449, 0x44A, 0x44B, 0x44C, 0x44D, 0x44E, 0x44F,
|
||||
0x451, 0x452, 0x453, 0x454, 0x455, 0x456, 0x457,
|
||||
0x458, 0x459, 0x45A, 0x45B, 0x45C, 0x45E, 0x45F,
|
||||
0x2170, 0x2171, 0x2172, 0x2173, 0x2174, 0x2175, 0x2176, 0x2177,
|
||||
0x2178, 0x2179, 0x217A, 0x217B, 0x217C, 0x217D, 0x217E, 0x217F,
|
||||
0xFF41, 0xFF42, 0xFF43, 0xFF44, 0xFF45, 0xFF46, 0xFF47, 0xFF48,
|
||||
0xFF49, 0xFF4A, 0xFF4B, 0xFF4C, 0xFF4D, 0xFF4E, 0xFF4F, 0xFF50,
|
||||
0xFF51, 0xFF52, 0xFF53, 0xFF54, 0xFF55, 0xFF56, 0xFF57, 0xFF58,
|
||||
0xFF59, 0xFF5A, 0
|
||||
};
|
||||
static const uint16_t tbl_upper[] =
|
||||
{
|
||||
0x41, 0x42, 0x43, 0x44, 0x45, 0x46, 0x47, 0x48, 0x49, 0x4A, 0x4B, 0x4C, 0x4D, 0x4E, 0x4F, 0x50, 0x51, 0x52, 0x53, 0x54, 0x55, 0x56, 0x57, 0x58, 0x59, 0x5A, 0x21, 0xFFE0, 0xFFE1, 0xFFE5, 0xFFE2, 0xFFE3, 0xC0, 0xC1, 0xC2, 0xC3, 0xC4, 0xC5, 0xC6, 0xC7, 0xC8, 0xC9, 0xCA, 0xCB, 0xCC, 0xCD, 0xCE, 0xCF, 0xD0, 0xD1, 0xD2, 0xD3, 0xD4, 0xD5, 0xD6, 0xD8, 0xD9, 0xDA, 0xDB, 0xDC, 0xDD, 0xDE, 0x178, 0x100, 0x102, 0x104, 0x106, 0x108, 0x10A, 0x10C, 0x10E, 0x110, 0x112, 0x114, 0x116, 0x118, 0x11A, 0x11C, 0x11E, 0x120, 0x122, 0x124, 0x126, 0x128, 0x12A, 0x12C, 0x12E, 0x130, 0x132, 0x134, 0x136, 0x139, 0x13B, 0x13D, 0x13F, 0x141, 0x143, 0x145, 0x147, 0x14A, 0x14C, 0x14E, 0x150, 0x152, 0x154, 0x156, 0x158, 0x15A, 0x15C, 0x15E, 0x160, 0x162, 0x164, 0x166, 0x168, 0x16A, 0x16C, 0x16E, 0x170, 0x172, 0x174, 0x176, 0x179, 0x17B, 0x17D, 0x191, 0x391, 0x392, 0x393, 0x394, 0x395, 0x396, 0x397, 0x398, 0x399, 0x39A, 0x39B, 0x39C, 0x39D, 0x39E, 0x39F, 0x3A0, 0x3A1, 0x3A3, 0x3A4, 0x3A5, 0x3A6, 0x3A7, 0x3A8, 0x3A9, 0x3AA, 0x410, 0x411, 0x412, 0x413, 0x414, 0x415, 0x416, 0x417, 0x418, 0x419, 0x41A, 0x41B, 0x41C, 0x41D, 0x41E, 0x41F, 0x420, 0x421, 0x422, 0x423, 0x424, 0x425, 0x426, 0x427, 0x428, 0x429, 0x42A, 0x42B, 0x42C, 0x42D, 0x42E, 0x42F, 0x401, 0x402, 0x403, 0x404, 0x405, 0x406, 0x407, 0x408, 0x409, 0x40A, 0x40B, 0x40C, 0x40E, 0x40F, 0x2160, 0x2161, 0x2162, 0x2163, 0x2164, 0x2165, 0x2166, 0x2167, 0x2168, 0x2169, 0x216A, 0x216B, 0x216C, 0x216D, 0x216E, 0x216F, 0xFF21, 0xFF22, 0xFF23, 0xFF24, 0xFF25, 0xFF26, 0xFF27, 0xFF28, 0xFF29, 0xFF2A, 0xFF2B, 0xFF2C, 0xFF2D, 0xFF2E, 0xFF2F, 0xFF30, 0xFF31, 0xFF32, 0xFF33, 0xFF34, 0xFF35, 0xFF36, 0xFF37, 0xFF38, 0xFF39, 0xFF3A, 0 };
|
||||
int i;
|
||||
|
||||
|
||||
for (i = 0; tbl_lower[i] && chr != tbl_lower[i]; i++) ;
|
||||
|
||||
return tbl_lower[i] ? tbl_upper[i] : chr;
|
||||
}
|
||||
4159
BaS_gcc/fs/ff.c
4159
BaS_gcc/fs/ff.c
File diff suppressed because it is too large
Load Diff
@@ -1,17 +0,0 @@
|
||||
#include <ff.h>
|
||||
|
||||
#if _USE_LFN != 0
|
||||
|
||||
#if _CODE_PAGE == 932
|
||||
#include "cc932.c"
|
||||
#elif _CODE_PAGE == 936
|
||||
#include "cc936.c"
|
||||
#elif _CODE_PAGE == 949
|
||||
#include "cc949.c"
|
||||
#elif _CODE_PAGE == 950
|
||||
#include "cc950.c"
|
||||
#else
|
||||
#include "ccsbcs.c"
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -1,41 +0,0 @@
|
||||
|
||||
#include <bas_types.h>
|
||||
|
||||
void i2c_init(void)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
void i2c_set_frequency(int hz)
|
||||
{
|
||||
}
|
||||
|
||||
int i2c_read(int address, char *data, int length, bool repeated)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int i2c_read_byte(int ack)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int i2c_write(int address, const char *data, int length, bool repeated)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
int i2c_write_byte(int data)
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
|
||||
void i2c_start(void)
|
||||
{
|
||||
|
||||
}
|
||||
|
||||
void i2c_stop(void)
|
||||
{
|
||||
|
||||
}
|
||||
@@ -1,299 +0,0 @@
|
||||
/*
|
||||
* driver_vec.c
|
||||
*
|
||||
* Expose BaS drivers to OS
|
||||
*
|
||||
* This file is part of BaS_gcc.
|
||||
*
|
||||
* BaS_gcc is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* BaS_gcc is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
*
|
||||
* Created on: 24.10.2013
|
||||
* Author: Markus Fröschle
|
||||
*/
|
||||
|
||||
#include <bas_types.h>
|
||||
#include "version.h"
|
||||
#include "xhdi_sd.h"
|
||||
#include "dma.h"
|
||||
#include "driver_vec.h"
|
||||
#include "driver_mem.h"
|
||||
#include "pci.h"
|
||||
#include "mmu.h"
|
||||
|
||||
/*
|
||||
* driver interface struct for the SD card BaS driver
|
||||
*/
|
||||
static struct xhdi_driver_interface xhdi_call_interface =
|
||||
{
|
||||
xhdi_call
|
||||
};
|
||||
|
||||
/*
|
||||
* driver interface struct for the BaS multichannel DMA driver
|
||||
* This is exactly the same thing FireTOS provides and the MiNT FEC drivers expect.
|
||||
* It can be directly used in TOS to register the corresponding cookie ("DMAC").
|
||||
*/
|
||||
static struct dma_driver_interface dma_interface =
|
||||
{
|
||||
.version = 0x0101,
|
||||
.magic = 0x444d4143, /* 'DMAC' */
|
||||
.dma_set_initiator = dma_set_initiator,
|
||||
.dma_get_initiator = dma_get_initiator,
|
||||
.dma_free_initiator = dma_free_initiator,
|
||||
.dma_set_channel = dma_set_channel,
|
||||
.dma_get_channel = dma_get_channel,
|
||||
.dma_free_channel = dma_free_channel,
|
||||
.dma_clear_channel = dma_clear_channel,
|
||||
.MCD_startDma = (int (*)(long, int8_t *, unsigned int, int8_t *, unsigned int,
|
||||
unsigned int, unsigned int, unsigned int, int,
|
||||
unsigned int, unsigned int)) MCD_startDma,
|
||||
.MCD_dmaStatus = (int32_t (*)(int32_t)) MCD_dmaStatus,
|
||||
.MCD_XferProgrQuery = (int32_t (*)(int32_t, MCD_XferProg *)) MCD_XferProgrQuery,
|
||||
.MCD_killDma = (int32_t (*)(int32_t)) MCD_killDma,
|
||||
.MCD_continDma = (int32_t (*)(int32_t)) MCD_continDma,
|
||||
.MCD_pauseDma = (int32_t (*)(int32_t)) MCD_pauseDma,
|
||||
.MCD_resumeDma = (int32_t (*)(int32_t)) MCD_resumeDma,
|
||||
.MCD_csumQuery = (int32_t (*)(int32_t, uint32_t *)) MCD_csumQuery,
|
||||
.dma_malloc = driver_mem_alloc,
|
||||
.dma_free = driver_mem_free
|
||||
};
|
||||
|
||||
extern struct fb_info *info_fb;
|
||||
|
||||
/*
|
||||
* driver interface struct for the PCI_BIOS BaS driver
|
||||
*/
|
||||
static struct pci_bios_interface pci_interface =
|
||||
{
|
||||
.subjar = 0,
|
||||
.version = 0x00010000,
|
||||
.find_pci_device = wrapper_find_pci_device,
|
||||
.find_pci_classcode = wrapper_find_pci_classcode,
|
||||
.read_config_byte = wrapper_read_config_byte,
|
||||
.read_config_word = wrapper_read_config_word,
|
||||
.read_config_longword = wrapper_read_config_longword,
|
||||
.fast_read_config_byte = wrapper_fast_read_config_byte,
|
||||
.fast_read_config_word = wrapper_fast_read_config_word,
|
||||
.fast_read_config_longword = wrapper_fast_read_config_longword,
|
||||
.write_config_byte = wrapper_write_config_byte,
|
||||
.write_config_word = wrapper_write_config_word,
|
||||
.write_config_longword = wrapper_write_config_longword,
|
||||
.hook_interrupt = wrapper_hook_interrupt,
|
||||
.unhook_interrupt = wrapper_unhook_interrupt,
|
||||
.special_cycle = wrapper_special_cycle,
|
||||
.get_routing = wrapper_get_routing,
|
||||
.set_interrupt = wrapper_set_interrupt,
|
||||
.get_resource = wrapper_get_resource,
|
||||
.get_card_used = wrapper_get_card_used,
|
||||
.set_card_used = wrapper_set_card_used,
|
||||
.read_mem_byte = wrapper_read_mem_byte,
|
||||
.read_mem_word = wrapper_read_mem_word,
|
||||
.read_mem_longword = wrapper_read_mem_longword,
|
||||
.fast_read_mem_byte = wrapper_fast_read_mem_byte,
|
||||
.fast_read_mem_word = wrapper_fast_read_mem_word,
|
||||
.fast_read_mem_longword = wrapper_fast_read_mem_longword,
|
||||
.write_mem_byte = wrapper_write_mem_byte,
|
||||
.write_mem_word = wrapper_write_mem_word,
|
||||
.write_mem_longword = wrapper_write_mem_longword,
|
||||
.read_io_byte = wrapper_read_io_byte,
|
||||
.read_io_word = wrapper_read_io_word,
|
||||
.read_io_longword = wrapper_read_io_longword,
|
||||
.fast_read_io_byte = wrapper_fast_read_io_byte,
|
||||
.fast_read_io_word = wrapper_fast_read_io_word,
|
||||
.fast_read_io_longword = wrapper_fast_read_io_longword,
|
||||
.write_io_byte = wrapper_write_io_byte,
|
||||
.write_io_word = wrapper_write_io_word,
|
||||
.write_io_longword = wrapper_write_io_longword,
|
||||
.get_machine_id = wrapper_get_machine_id,
|
||||
.get_pagesize = wrapper_get_pagesize,
|
||||
.virt_to_bus = wrapper_virt_to_bus,
|
||||
.bus_to_virt = wrapper_bus_to_virt,
|
||||
.virt_to_phys = wrapper_virt_to_phys,
|
||||
.phys_to_virt = wrapper_phys_to_virt,
|
||||
};
|
||||
|
||||
static struct pci_native_driver_interface_0_1 pci_native_interface_0_1 =
|
||||
{
|
||||
.pci_read_config_longword = pci_read_config_longword,
|
||||
.pci_read_config_word = pci_read_config_word,
|
||||
.pci_read_config_byte = pci_read_config_byte,
|
||||
.pci_write_config_longword = pci_write_config_longword,
|
||||
.pci_write_config_word = pci_write_config_word,
|
||||
.pci_write_config_byte = pci_write_config_byte,
|
||||
.pci_hook_interrupt = pci_hook_interrupt,
|
||||
.pci_unhook_interrupt = pci_unhook_interrupt,
|
||||
.pci_get_resource = pci_get_resource,
|
||||
};
|
||||
|
||||
static struct pci_native_driver_interface pci_native_interface =
|
||||
{
|
||||
.pci_read_config_longword = pci_read_config_longword,
|
||||
.pci_read_config_word = pci_read_config_word,
|
||||
.pci_read_config_byte = pci_read_config_byte,
|
||||
.pci_write_config_longword = pci_write_config_longword,
|
||||
.pci_write_config_word = pci_write_config_word,
|
||||
.pci_write_config_byte = pci_write_config_byte,
|
||||
.pci_hook_interrupt = pci_hook_interrupt,
|
||||
.pci_unhook_interrupt = pci_unhook_interrupt,
|
||||
.pci_find_device = pci_find_device,
|
||||
.pci_find_classcode = pci_find_classcode,
|
||||
.pci_get_resource = pci_get_resource,
|
||||
};
|
||||
/*
|
||||
* driver interface struct for the BaS framebuffer video driver
|
||||
*/
|
||||
static struct framebuffer_driver_interface framebuffer_interface =
|
||||
{
|
||||
.framebuffer_info = &info_fb
|
||||
};
|
||||
|
||||
/*
|
||||
* driver interface struct for the BaS MMU driver
|
||||
*/
|
||||
static struct mmu_driver_interface mmu_interface =
|
||||
{
|
||||
.map_page_locked = &mmu_map_data_page_locked,
|
||||
.unlock_page = &mmu_unlock_data_page,
|
||||
.report_locked_pages = &mmu_report_locked_pages,
|
||||
.report_pagesize = &mmu_report_pagesize
|
||||
};
|
||||
|
||||
static struct generic_interface interfaces[] =
|
||||
{
|
||||
{
|
||||
/* BaS SD-card driver interface */
|
||||
|
||||
.type = XHDI_DRIVER,
|
||||
.name = "SDCARD",
|
||||
.description = "BaS SD Card driver",
|
||||
.version = 0,
|
||||
.revision = 1,
|
||||
.interface.xhdi = &xhdi_call_interface
|
||||
},
|
||||
{
|
||||
.type = MCD_DRIVER,
|
||||
.name = "MCDDMA",
|
||||
.description = "BaS Multichannel DMA driver",
|
||||
.version = 0,
|
||||
.revision = 1,
|
||||
.interface.dma = &dma_interface,
|
||||
},
|
||||
{
|
||||
.type = VIDEO_DRIVER,
|
||||
.name = "RADEON",
|
||||
.description = "BaS RADEON framebuffer driver",
|
||||
.version = 0,
|
||||
.revision = 1,
|
||||
.interface.fb = &framebuffer_interface,
|
||||
},
|
||||
{
|
||||
.type = PCI_DRIVER,
|
||||
.name = "PCI",
|
||||
.description = "BaS PCI_BIOS driver",
|
||||
.version = 0,
|
||||
.revision = 1,
|
||||
.interface.pci = &pci_interface,
|
||||
},
|
||||
{
|
||||
.type = MMU_DRIVER,
|
||||
.name = "MMU",
|
||||
.description = "BaS MMU driver",
|
||||
.version = 0,
|
||||
.revision = 1,
|
||||
.interface.mmu = &mmu_interface,
|
||||
},
|
||||
{
|
||||
.type = PCI_NATIVE_DRIVER,
|
||||
.name = "PCI_N",
|
||||
.description = "BaS PCI native",
|
||||
.version = 0,
|
||||
.revision = 1,
|
||||
.interface.pci_native = (struct pci_native_driver_interface *) &pci_native_interface_0_1,
|
||||
},
|
||||
{
|
||||
.type = PCI_NATIVE_DRIVER,
|
||||
.name = "PCI_N",
|
||||
.description = "BaS PCI native",
|
||||
.version = 0,
|
||||
.revision = 2,
|
||||
.interface.pci_native = &pci_native_interface,
|
||||
},
|
||||
|
||||
/* insert new drivers here */
|
||||
|
||||
{
|
||||
.type = END_OF_DRIVERS
|
||||
}
|
||||
};
|
||||
|
||||
extern void remove_handler(void); /* forward declaration */
|
||||
|
||||
/*
|
||||
* this is the driver table we expose to the OS
|
||||
*/
|
||||
static struct driver_table bas_drivers =
|
||||
{
|
||||
.bas_version = MAJOR_VERSION,
|
||||
.bas_revision = MINOR_VERSION,
|
||||
.remove_handler = remove_handler,
|
||||
.interfaces = interfaces
|
||||
};
|
||||
|
||||
void remove_handler(void)
|
||||
{
|
||||
extern void std_exc_vec(void);
|
||||
uint32_t *trap_0_vector = (uint32_t *) 0x80;
|
||||
|
||||
*trap_0_vector = (uint32_t) std_exc_vec;
|
||||
}
|
||||
|
||||
/*
|
||||
* trap #0 entry point
|
||||
*
|
||||
* this is used to retrieve the driver table that gets exposed to the OS by BaS
|
||||
*/
|
||||
void __attribute__((interrupt)) get_bas_drivers(void)
|
||||
{
|
||||
__asm__ __volatile(
|
||||
/*
|
||||
* (sp) should now point to the next instruction after the trap
|
||||
* The trap itself is 2 bytes, the four bytes before that must
|
||||
* read '_BAS', otherwise we are not meant by this call
|
||||
*/
|
||||
" move.l a0,-(sp) \n\t" // save registers
|
||||
" move.l d0,-(sp) \n\t"
|
||||
" move.l 12(sp),a0 \n\t" // get return address
|
||||
" move.l -6(a0),d0 \n\t" //
|
||||
" cmp.l #0x5f424153,d0 \n\t" // is it '_BAS'?
|
||||
" beq fetch_drivers \n\t" // yes
|
||||
/*
|
||||
* This seems indeed a "normal" trap #0. Better pass control to "normal" trap #0 processing
|
||||
* If trap #0 isn't set to something sensible, we'll probably crash here, but this must be
|
||||
* prevented on the caller side.
|
||||
*/
|
||||
" move.l (sp)+,d0 \n\t" // restore registers
|
||||
" move.l (sp)+,a0 \n\t"
|
||||
" move.l 0x80,-(sp) \n\t" // fetch vector
|
||||
" rts \n\t" // and jump through it
|
||||
|
||||
"fetch_drivers: \n\t"
|
||||
" move.l #%[drivers],d0 \n\t" // return driver struct in d0
|
||||
" addq.l #4,sp \n\t" // adjust stack
|
||||
" move.l (sp)+,a0 \n\t" // restore register
|
||||
: /* no output */
|
||||
: [drivers] "o" (bas_drivers) /* input */
|
||||
: /* clobber */
|
||||
);
|
||||
}
|
||||
@@ -1,362 +0,0 @@
|
||||
/*
|
||||
* File: MCD_dma.h
|
||||
* Purpose: Main header file for multi-channel DMA API.
|
||||
*
|
||||
* Notes:
|
||||
*/
|
||||
#ifndef _MCD_API_H
|
||||
#define _MCD_API_H
|
||||
|
||||
/*
|
||||
* Turn Execution Unit tasks ON (#define) or OFF (#undef)
|
||||
*/
|
||||
#undef MCD_INCLUDE_EU
|
||||
//#define MCD_INCLUDE_EU
|
||||
/*
|
||||
* Number of DMA channels
|
||||
*/
|
||||
#define NCHANNELS 16
|
||||
|
||||
/*
|
||||
* Total number of variants
|
||||
*/
|
||||
#ifdef MCD_INCLUDE_EU
|
||||
#define NUMOFVARIANTS 6
|
||||
#else
|
||||
#define NUMOFVARIANTS 4
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Define sizes of the various tables
|
||||
*/
|
||||
#define TASK_TABLE_SIZE (NCHANNELS*32)
|
||||
#define VAR_TAB_SIZE (128)
|
||||
#define CONTEXT_SAVE_SIZE (128)
|
||||
#define FUNCDESC_TAB_SIZE (256)
|
||||
|
||||
#ifdef MCD_INCLUDE_EU
|
||||
#define FUNCDESC_TAB_NUM 16
|
||||
#else
|
||||
#define FUNCDESC_TAB_NUM 1
|
||||
#endif
|
||||
|
||||
|
||||
#ifndef DEFINESONLY
|
||||
|
||||
/*
|
||||
* Portability typedefs
|
||||
*/
|
||||
typedef int s32;
|
||||
typedef unsigned int u32;
|
||||
typedef short s16;
|
||||
typedef unsigned short u16;
|
||||
typedef char s8;
|
||||
typedef unsigned char u8;
|
||||
|
||||
/*
|
||||
* These structures represent the internal registers of the
|
||||
* multi-channel DMA
|
||||
*/
|
||||
struct dmaRegs_s {
|
||||
u32 taskbar; /* task table base address register */
|
||||
u32 currPtr;
|
||||
u32 endPtr;
|
||||
u32 varTablePtr;
|
||||
u16 dma_rsvd0;
|
||||
u16 ptdControl; /* ptd control */
|
||||
u32 intPending; /* interrupt pending register */
|
||||
u32 intMask; /* interrupt mask register */
|
||||
u16 taskControl[16]; /* task control registers */
|
||||
u8 priority[32]; /* priority registers */
|
||||
u32 initiatorMux; /* initiator mux control */
|
||||
u32 taskSize0; /* task size control register 0. */
|
||||
u32 taskSize1; /* task size control register 1. */
|
||||
u32 dma_rsvd1; /* reserved */
|
||||
u32 dma_rsvd2; /* reserved */
|
||||
u32 debugComp1; /* debug comparator 1 */
|
||||
u32 debugComp2; /* debug comparator 2 */
|
||||
u32 debugControl; /* debug control */
|
||||
u32 debugStatus; /* debug status */
|
||||
u32 ptdDebug; /* priority task decode debug */
|
||||
u32 dma_rsvd3[31]; /* reserved */
|
||||
};
|
||||
typedef volatile struct dmaRegs_s dmaRegs;
|
||||
|
||||
#endif
|
||||
|
||||
/*
|
||||
* PTD contrl reg bits
|
||||
*/
|
||||
#define PTD_CTL_TSK_PRI 0x8000
|
||||
#define PTD_CTL_COMM_PREFETCH 0x0001
|
||||
|
||||
/*
|
||||
* Task Control reg bits and field masks
|
||||
*/
|
||||
#define TASK_CTL_EN 0x8000
|
||||
#define TASK_CTL_VALID 0x4000
|
||||
#define TASK_CTL_ALWAYS 0x2000
|
||||
#define TASK_CTL_INIT_MASK 0x1f00
|
||||
#define TASK_CTL_ASTRT 0x0080
|
||||
#define TASK_CTL_HIPRITSKEN 0x0040
|
||||
#define TASK_CTL_HLDINITNUM 0x0020
|
||||
#define TASK_CTL_ASTSKNUM_MASK 0x000f
|
||||
|
||||
/*
|
||||
* Priority reg bits and field masks
|
||||
*/
|
||||
#define PRIORITY_HLD 0x80
|
||||
#define PRIORITY_PRI_MASK 0x07
|
||||
|
||||
/*
|
||||
* Debug Control reg bits and field masks
|
||||
*/
|
||||
#define DBG_CTL_BLOCK_TASKS_MASK 0xffff0000
|
||||
#define DBG_CTL_AUTO_ARM 0x00008000
|
||||
#define DBG_CTL_BREAK 0x00004000
|
||||
#define DBG_CTL_COMP1_TYP_MASK 0x00003800
|
||||
#define DBG_CTL_COMP2_TYP_MASK 0x00000070
|
||||
#define DBG_CTL_EXT_BREAK 0x00000004
|
||||
#define DBG_CTL_INT_BREAK 0x00000002
|
||||
|
||||
/*
|
||||
* PTD Debug reg selector addresses
|
||||
* This reg must be written with a value to show the contents of
|
||||
* one of the desired internal register.
|
||||
*/
|
||||
#define PTD_DBG_REQ 0x00 /* shows the state of 31 initiators */
|
||||
#define PTD_DBG_TSK_VLD_INIT 0x01 /* shows which 16 tasks are valid and
|
||||
have initiators asserted */
|
||||
|
||||
|
||||
/*
|
||||
* General return values
|
||||
*/
|
||||
#define MCD_OK 0
|
||||
#define MCD_ERROR -1
|
||||
#define MCD_TABLE_UNALIGNED -2
|
||||
#define MCD_CHANNEL_INVALID -3
|
||||
|
||||
/*
|
||||
* MCD_initDma input flags
|
||||
*/
|
||||
#define MCD_RELOC_TASKS 0x00000001
|
||||
#define MCD_NO_RELOC_TASKS 0x00000000
|
||||
#define MCD_COMM_PREFETCH_EN 0x00000002 /* Commbus Prefetching - MCF547x/548x ONLY */
|
||||
|
||||
/*
|
||||
* MCD_dmaStatus Status Values for each channel
|
||||
*/
|
||||
#define MCD_NO_DMA 1 /* No DMA has been requested since reset */
|
||||
#define MCD_IDLE 2 /* DMA active, but the initiator is currently inactive */
|
||||
#define MCD_RUNNING 3 /* DMA active, and the initiator is currently active */
|
||||
#define MCD_PAUSED 4 /* DMA active but it is currently paused */
|
||||
#define MCD_HALTED 5 /* the most recent DMA has been killed with MCD_killTask() */
|
||||
#define MCD_DONE 6 /* the most recent DMA has completed. */
|
||||
|
||||
|
||||
/*
|
||||
* MCD_startDma parameter defines
|
||||
*/
|
||||
|
||||
/*
|
||||
* Constants for the funcDesc parameter
|
||||
*/
|
||||
/* Byte swapping: */
|
||||
#define MCD_NO_BYTE_SWAP 0x00045670 /* to disable byte swapping. */
|
||||
#define MCD_BYTE_REVERSE 0x00076540 /* to reverse the bytes of each u32 of the DMAed data. */
|
||||
#define MCD_U16_REVERSE 0x00067450 /* to reverse the 16-bit halves of
|
||||
each 32-bit data value being DMAed.*/
|
||||
#define MCD_U16_BYTE_REVERSE 0x00054760 /* to reverse the byte halves of each
|
||||
16-bit half of each 32-bit data value DMAed */
|
||||
#define MCD_NO_BIT_REV 0x00000000 /* do not reverse the bits of each byte DMAed. */
|
||||
#define MCD_BIT_REV 0x00088880 /* reverse the bits of each byte DMAed */
|
||||
/* CRCing: */
|
||||
#define MCD_CRC16 0xc0100000 /* to perform CRC-16 on DMAed data. */
|
||||
#define MCD_CRCCCITT 0xc0200000 /* to perform CRC-CCITT on DMAed data. */
|
||||
#define MCD_CRC32 0xc0300000 /* to perform CRC-32 on DMAed data. */
|
||||
#define MCD_CSUMINET 0xc0400000 /* to perform internet checksums on DMAed data.*/
|
||||
#define MCD_NO_CSUM 0xa0000000 /* to perform no checksumming. */
|
||||
|
||||
#define MCD_FUNC_NOEU1 (MCD_NO_BYTE_SWAP | MCD_NO_BIT_REV | MCD_NO_CSUM)
|
||||
#define MCD_FUNC_NOEU2 (MCD_NO_BYTE_SWAP | MCD_NO_CSUM)
|
||||
|
||||
/*
|
||||
* Constants for the flags parameter
|
||||
*/
|
||||
#define MCD_TT_FLAGS_RL 0x00000001 /* Read line */
|
||||
#define MCD_TT_FLAGS_CW 0x00000002 /* Combine Writes */
|
||||
#define MCD_TT_FLAGS_SP 0x00000004 /* Speculative prefetch(XLB) MCF547x/548x ONLY */
|
||||
#define MCD_TT_FLAGS_MASK 0x000000ff
|
||||
#define MCD_TT_FLAGS_DEF (MCD_TT_FLAGS_RL | MCD_TT_FLAGS_CW)
|
||||
|
||||
#define MCD_SINGLE_DMA 0x00000100 /* Unchained DMA */
|
||||
#define MCD_CHAIN_DMA /* TBD */
|
||||
#define MCD_EU_DMA /* TBD */
|
||||
#define MCD_FECTX_DMA 0x00001000 /* FEC TX ring DMA */
|
||||
#define MCD_FECRX_DMA 0x00002000 /* FEC RX ring DMA */
|
||||
|
||||
|
||||
/* these flags are valid for MCD_startDma and the chained buffer descriptors */
|
||||
#define MCD_BUF_READY 0x80000000 /* indicates that this buffer is now under the DMA's control */
|
||||
#define MCD_WRAP 0x20000000 /* to tell the FEC Dmas to wrap to the first BD */
|
||||
#define MCD_INTERRUPT 0x10000000 /* to generate an interrupt after completion of the DMA. */
|
||||
#define MCD_END_FRAME 0x08000000 /* tell the DMA to end the frame when transferring
|
||||
last byte of data in buffer */
|
||||
#define MCD_CRC_RESTART 0x40000000 /* to empty out the accumulated checksum
|
||||
prior to performing the DMA. */
|
||||
|
||||
/* Defines for the FEC buffer descriptor control/status word*/
|
||||
#define MCD_FEC_BUF_READY 0x8000
|
||||
#define MCD_FEC_WRAP 0x2000
|
||||
#define MCD_FEC_INTERRUPT 0x1000
|
||||
#define MCD_FEC_END_FRAME 0x0800
|
||||
|
||||
|
||||
/*
|
||||
* Defines for general intuitiveness
|
||||
*/
|
||||
|
||||
#define MCD_TRUE 1
|
||||
#define MCD_FALSE 0
|
||||
|
||||
/*
|
||||
* Three different cases for destination and source.
|
||||
*/
|
||||
#define MINUS1 -1
|
||||
#define ZERO 0
|
||||
#define PLUS1 1
|
||||
|
||||
#ifndef DEFINESONLY
|
||||
|
||||
/* Task Table Entry struct*/
|
||||
typedef struct {
|
||||
u32 TDTstart; /* task descriptor table start */
|
||||
u32 TDTend; /* task descriptor table end */
|
||||
u32 varTab; /* variable table start */
|
||||
u32 FDTandFlags; /* function descriptor table start and flags */
|
||||
volatile u32 descAddrAndStatus;
|
||||
volatile u32 modifiedVarTab;
|
||||
u32 contextSaveSpace; /* context save space start */
|
||||
u32 literalBases;
|
||||
} TaskTableEntry;
|
||||
|
||||
|
||||
/* Chained buffer descriptor */
|
||||
typedef volatile struct MCD_bufDesc_struct MCD_bufDesc;
|
||||
struct MCD_bufDesc_struct {
|
||||
u32 flags; /* flags describing the DMA */
|
||||
u32 csumResult; /* checksum from checksumming performed since last checksum reset */
|
||||
s8 *srcAddr; /* the address to move data from */
|
||||
s8 *destAddr; /* the address to move data to */
|
||||
s8 *lastDestAddr; /* the last address written to */
|
||||
u32 dmaSize; /* the number of bytes to transfer independent of the transfer size */
|
||||
MCD_bufDesc *next; /* next buffer descriptor in chain */
|
||||
u32 info; /* private information about this descriptor; DMA does not affect it */
|
||||
};
|
||||
|
||||
/* Progress Query struct */
|
||||
typedef volatile struct MCD_XferProg_struct {
|
||||
s8 *lastSrcAddr; /* the most-recent or last, post-increment source address */
|
||||
s8 *lastDestAddr; /* the most-recent or last, post-increment destination address */
|
||||
u32 dmaSize; /* the amount of data transferred for the current buffer */
|
||||
MCD_bufDesc *currBufDesc;/* pointer to the current buffer descriptor being DMAed */
|
||||
} MCD_XferProg;
|
||||
|
||||
|
||||
/* FEC buffer descriptor */
|
||||
typedef volatile struct MCD_bufDescFec_struct {
|
||||
u16 statCtrl;
|
||||
u16 length;
|
||||
u32 dataPointer;
|
||||
} MCD_bufDescFec;
|
||||
|
||||
|
||||
/*************************************************************************/
|
||||
/*
|
||||
* API function Prototypes - see MCD_dmaApi.c for further notes
|
||||
*/
|
||||
|
||||
/*
|
||||
* MCD_startDma starts a particular kind of DMA .
|
||||
*/
|
||||
int MCD_startDma (
|
||||
int channel, /* the channel on which to run the DMA */
|
||||
s8 *srcAddr, /* the address to move data from, or buffer-descriptor address */
|
||||
s16 srcIncr, /* the amount to increment the source address per transfer */
|
||||
s8 *destAddr, /* the address to move data to */
|
||||
s16 destIncr, /* the amount to increment the destination address per transfer */
|
||||
u32 dmaSize, /* the number of bytes to transfer independent of the transfer size */
|
||||
u32 xferSize, /* the number bytes in of each data movement (1, 2, or 4) */
|
||||
u32 initiator, /* what device initiates the DMA */
|
||||
int priority, /* priority of the DMA */
|
||||
u32 flags, /* flags describing the DMA */
|
||||
u32 funcDesc /* a description of byte swapping, bit swapping, and CRC actions */
|
||||
);
|
||||
|
||||
/*
|
||||
* MCD_initDma() initializes the DMA API by setting up a pointer to the DMA
|
||||
* registers, relocating and creating the appropriate task structures, and
|
||||
* setting up some global settings
|
||||
*/
|
||||
int MCD_initDma (dmaRegs *sDmaBarAddr, void *taskTableDest, u32 flags);
|
||||
|
||||
/*
|
||||
* MCD_dmaStatus() returns the status of the DMA on the requested channel.
|
||||
*/
|
||||
int MCD_dmaStatus (int channel);
|
||||
|
||||
/*
|
||||
* MCD_XferProgrQuery() returns progress of DMA on requested channel
|
||||
*/
|
||||
int MCD_XferProgrQuery (int channel, MCD_XferProg *progRep);
|
||||
|
||||
/*
|
||||
* MCD_killDma() halts the DMA on the requested channel, without any
|
||||
* intention of resuming the DMA.
|
||||
*/
|
||||
int MCD_killDma (int channel);
|
||||
|
||||
/*
|
||||
* MCD_continDma() continues a DMA which as stopped due to encountering an
|
||||
* unready buffer descriptor.
|
||||
*/
|
||||
int MCD_continDma (int channel);
|
||||
|
||||
/*
|
||||
* MCD_pauseDma() pauses the DMA on the given channel ( if any DMA is
|
||||
* running on that channel).
|
||||
*/
|
||||
int MCD_pauseDma (int channel);
|
||||
|
||||
/*
|
||||
* MCD_resumeDma() resumes the DMA on a given channel (if any DMA is
|
||||
* running on that channel).
|
||||
*/
|
||||
int MCD_resumeDma (int channel);
|
||||
|
||||
/*
|
||||
* MCD_csumQuery provides the checksum/CRC after performing a non-chained DMA
|
||||
*/
|
||||
int MCD_csumQuery (int channel, u32 *csum);
|
||||
|
||||
/*
|
||||
* MCD_getCodeSize provides the packed size required by the microcoded task
|
||||
* and structures.
|
||||
*/
|
||||
int MCD_getCodeSize(void);
|
||||
|
||||
/*
|
||||
* MCD_getVersion provides a pointer to a version string and returns a
|
||||
* version number.
|
||||
*/
|
||||
int MCD_getVersion(char **longVersion);
|
||||
|
||||
/* macro for setting a location in the variable table */
|
||||
#define MCD_SET_VAR(taskTab,idx,value) ((u32 *)(taskTab)->varTab)[idx] = value
|
||||
/* Note that MCD_SET_VAR() is invoked many times in firing up a DMA function,
|
||||
so I'm avoiding surrounding it with "do {} while(0)" */
|
||||
|
||||
#endif /* DEFINESONLY */
|
||||
|
||||
#endif /* _MCD_API_H */
|
||||
@@ -1,5 +0,0 @@
|
||||
/* This file is autogenerated. Do not change */
|
||||
#define CURRBD 4
|
||||
#define DCOUNT 6
|
||||
#define DESTPTR 5
|
||||
#define SRCPTR 7
|
||||
@@ -1,44 +0,0 @@
|
||||
#ifndef MCD_TSK_INIT_H
|
||||
#define MCD_TSK_INIT_H 1
|
||||
|
||||
/*
|
||||
* Do not edit!
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
* Task 0
|
||||
*/
|
||||
void MCD_startDmaChainNoEu(int *currBD, short srcIncr, short destIncr, int xferSize, short xferSizeIncr, int *cSave, volatile TaskTableEntry *taskTable, int channel);
|
||||
|
||||
|
||||
/*
|
||||
* Task 1
|
||||
*/
|
||||
void MCD_startDmaSingleNoEu(char *srcAddr, short srcIncr, char *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel);
|
||||
|
||||
|
||||
/*
|
||||
* Task 2
|
||||
*/
|
||||
void MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr, int xferSize, short xferSizeIncr, int *cSave, volatile TaskTableEntry *taskTable, int channel);
|
||||
|
||||
|
||||
/*
|
||||
* Task 3
|
||||
*/
|
||||
void MCD_startDmaSingleEu(char *srcAddr, short srcIncr, char *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel);
|
||||
|
||||
|
||||
/*
|
||||
* Task 4
|
||||
*/
|
||||
void MCD_startDmaENetRcv(char *bDBase, char *currBD, char *rcvFifoPtr, volatile TaskTableEntry *taskTable, int channel);
|
||||
|
||||
|
||||
/*
|
||||
* Task 5
|
||||
*/
|
||||
void MCD_startDmaENetXmit(char *bDBase, char *currBD, char *xmitFifoPtr, volatile TaskTableEntry *taskTable, int channel);
|
||||
|
||||
#endif /* MCD_TSK_INIT_H */
|
||||
@@ -1,67 +0,0 @@
|
||||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.81
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF5475_H__
|
||||
#define __MCF5475_H__
|
||||
|
||||
#include <bas_types.h>
|
||||
/***
|
||||
* MCF5475 Derivative Memory map definitions from linker command files:
|
||||
* __MBAR, __MMUBAR, __RAMBAR0, __RAMBAR0_SIZE, __RAMBAR1, __RAMBAR1_SIZE
|
||||
* linker symbols must be defined in the linker command file.
|
||||
*/
|
||||
|
||||
typedef uint32_t __attribute__((__may_alias__)) uint32_t_a; /* a type to avoid gcc's complaints about pointer aliasing */
|
||||
|
||||
extern uint8_t _MBAR[];
|
||||
extern uint8_t _MMUBAR[];
|
||||
extern uint8_t _RAMBAR0[];
|
||||
extern uint8_t _RAMBAR0_SIZE[];
|
||||
extern uint8_t _RAMBAR1[];
|
||||
extern uint8_t _RAMBAR1_SIZE[];
|
||||
|
||||
#define MBAR_ADDRESS (uint32_t)_MBAR
|
||||
#define MMUBAR_ADDRESS (uint32_t)_MMUBAR
|
||||
#define RAMBAR0_ADDRESS (uint32_t)_RAMBAR0
|
||||
#define RAMBAR0_SIZE (uint32_t)_RAMBAR0_SIZE
|
||||
#define RAMBAR1_ADDRESS (uint32_t)_RAMBAR1
|
||||
#define RAMBAR1_SIZE (uint32_t)_RAMBAR1_SIZE
|
||||
|
||||
|
||||
#include "MCF5475_SIU.h"
|
||||
#include "MCF5475_MMU.h"
|
||||
#include "MCF5475_SDRAMC.h"
|
||||
#include "MCF5475_XLB.h"
|
||||
#include "MCF5475_CLOCK.h"
|
||||
#include "MCF5475_FBCS.h"
|
||||
#include "MCF5475_INTC.h"
|
||||
#include "MCF5475_GPT.h"
|
||||
#include "MCF5475_SLT.h"
|
||||
#include "MCF5475_GPIO.h"
|
||||
#include "MCF5475_PAD.h"
|
||||
#include "MCF5475_PCI.h"
|
||||
#include "MCF5475_PCIARB.h"
|
||||
#include "MCF5475_EPORT.h"
|
||||
#include "MCF5475_CTM.h"
|
||||
#include "MCF5475_DMA.h"
|
||||
#include "MCF5475_PSC.h"
|
||||
#include "MCF5475_DSPI.h"
|
||||
#include "MCF5475_I2C.h"
|
||||
#include "MCF5475_FEC.h"
|
||||
#include "MCF5475_USB.h"
|
||||
#include "MCF5475_SRAM.h"
|
||||
#include "MCF5475_SEC.h"
|
||||
|
||||
#endif /* __MCF5475_H__ */
|
||||
@@ -1,47 +0,0 @@
|
||||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.81
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF5475_CLOCK_H__
|
||||
#define __MCF5475_CLOCK_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Clock Module (CLOCK)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_CLOCK_SPCR (*(volatile uint32_t*)(&_MBAR[0x300]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_CLOCK_SPCR */
|
||||
#define MCF_CLOCK_SPCR_MEMEN (0x1)
|
||||
#define MCF_CLOCK_SPCR_PCIEN (0x2)
|
||||
#define MCF_CLOCK_SPCR_FBEN (0x4)
|
||||
#define MCF_CLOCK_SPCR_CAN0EN (0x8)
|
||||
#define MCF_CLOCK_SPCR_DMAEN (0x10)
|
||||
#define MCF_CLOCK_SPCR_FEC0EN (0x20)
|
||||
#define MCF_CLOCK_SPCR_FEC1EN (0x40)
|
||||
#define MCF_CLOCK_SPCR_USBEN (0x80)
|
||||
#define MCF_CLOCK_SPCR_PSCEN (0x200)
|
||||
#define MCF_CLOCK_SPCR_CAN1EN (0x800)
|
||||
#define MCF_CLOCK_SPCR_CRYENA (0x1000)
|
||||
#define MCF_CLOCK_SPCR_CRYENB (0x2000)
|
||||
#define MCF_CLOCK_SPCR_COREN (0x4000)
|
||||
#define MCF_CLOCK_SPCR_PLLK (0x80000000)
|
||||
|
||||
|
||||
#endif /* __MCF5475_CLOCK_H__ */
|
||||
@@ -1,76 +0,0 @@
|
||||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.81
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF5475_CTM_H__
|
||||
#define __MCF5475_CTM_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Comm Timer Module (CTM)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_CTM_CTCR0 (*(volatile uint32_t*)(&_MBAR[0x7F00]))
|
||||
#define MCF_CTM_CTCR1 (*(volatile uint32_t*)(&_MBAR[0x7F04]))
|
||||
#define MCF_CTM_CTCR2 (*(volatile uint32_t*)(&_MBAR[0x7F08]))
|
||||
#define MCF_CTM_CTCR3 (*(volatile uint32_t*)(&_MBAR[0x7F0C]))
|
||||
#define MCF_CTM_CTCR4 (*(volatile uint32_t*)(&_MBAR[0x7F10]))
|
||||
#define MCF_CTM_CTCR5 (*(volatile uint32_t*)(&_MBAR[0x7F14]))
|
||||
#define MCF_CTM_CTCR6 (*(volatile uint32_t*)(&_MBAR[0x7F18]))
|
||||
#define MCF_CTM_CTCR7 (*(volatile uint32_t*)(&_MBAR[0x7F1C]))
|
||||
#define MCF_CTM_CTCRF(x) (*(volatile uint32_t*)(&_MBAR[0x7F00 + ((x)*0x4)]))
|
||||
#define MCF_CTM_CTCRV(x) (*(volatile uint32_t*)(&_MBAR[0x7F10 + ((x-4)*0x4)]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_CTM_CTCRF */
|
||||
#define MCF_CTM_CTCRF_CRV(x) (((x)&0xFFFF)<<0)
|
||||
#define MCF_CTM_CTCRF_S(x) (((x)&0xF)<<0x10)
|
||||
#define MCF_CTM_CTCRF_S_CLK_1 (0)
|
||||
#define MCF_CTM_CTCRF_S_CLK_2 (0x10000)
|
||||
#define MCF_CTM_CTCRF_S_CLK_4 (0x20000)
|
||||
#define MCF_CTM_CTCRF_S_CLK_8 (0x30000)
|
||||
#define MCF_CTM_CTCRF_S_CLK_16 (0x40000)
|
||||
#define MCF_CTM_CTCRF_S_CLK_32 (0x50000)
|
||||
#define MCF_CTM_CTCRF_S_CLK_64 (0x60000)
|
||||
#define MCF_CTM_CTCRF_S_CLK_128 (0x70000)
|
||||
#define MCF_CTM_CTCRF_S_CLK_256 (0x80000)
|
||||
#define MCF_CTM_CTCRF_S_CLK_EXT (0x90000)
|
||||
#define MCF_CTM_CTCRF_PCT(x) (((x)&0x7)<<0x14)
|
||||
#define MCF_CTM_CTCRF_PCT_100 (0)
|
||||
#define MCF_CTM_CTCRF_PCT_50 (0x100000)
|
||||
#define MCF_CTM_CTCRF_PCT_25 (0x200000)
|
||||
#define MCF_CTM_CTCRF_PCT_12p5 (0x300000)
|
||||
#define MCF_CTM_CTCRF_PCT_6p25 (0x400000)
|
||||
#define MCF_CTM_CTCRF_PCT_OFF (0x500000)
|
||||
#define MCF_CTM_CTCRF_M (0x800000)
|
||||
#define MCF_CTM_CTCRF_IM (0x1000000)
|
||||
#define MCF_CTM_CTCRF_I (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_CTM_CTCRV */
|
||||
#define MCF_CTM_CTCRV_CRV(x) (((x)&0xFFFFFF)<<0)
|
||||
#define MCF_CTM_CTCRV_PCT(x) (((x)&0x7)<<0x18)
|
||||
#define MCF_CTM_CTCRV_PCT_100 (0)
|
||||
#define MCF_CTM_CTCRV_PCT_50 (0x1000000)
|
||||
#define MCF_CTM_CTCRV_PCT_25 (0x2000000)
|
||||
#define MCF_CTM_CTCRV_PCT_12p5 (0x3000000)
|
||||
#define MCF_CTM_CTCRV_PCT_6p25 (0x4000000)
|
||||
#define MCF_CTM_CTCRV_PCT_OFF (0x5000000)
|
||||
#define MCF_CTM_CTCRV_M (0x8000000)
|
||||
#define MCF_CTM_CTCRV_S (0x10000000)
|
||||
|
||||
|
||||
#endif /* __MCF5475_CTM_H__ */
|
||||
@@ -1,234 +0,0 @@
|
||||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.81
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF5475_DMA_H__
|
||||
#define __MCF5475_DMA_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Multichannel DMA (DMA)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_DMA_TASKBAR (*(volatile uint32_t*)(&_MBAR[0x8000]))
|
||||
#define MCF_DMA_CP (*(volatile uint32_t*)(&_MBAR[0x8004]))
|
||||
#define MCF_DMA_EP (*(volatile uint32_t*)(&_MBAR[0x8008]))
|
||||
#define MCF_DMA_VP (*(volatile uint32_t*)(&_MBAR[0x800C]))
|
||||
#define MCF_DMA_PTD (*(volatile uint32_t*)(&_MBAR[0x8010]))
|
||||
#define MCF_DMA_DIPR (*(volatile uint32_t*)(&_MBAR[0x8014]))
|
||||
#define MCF_DMA_DIMR (*(volatile uint32_t*)(&_MBAR[0x8018]))
|
||||
#define MCF_DMA_TCR0 (*(volatile uint16_t*)(&_MBAR[0x801C]))
|
||||
#define MCF_DMA_TCR1 (*(volatile uint16_t*)(&_MBAR[0x801E]))
|
||||
#define MCF_DMA_TCR2 (*(volatile uint16_t*)(&_MBAR[0x8020]))
|
||||
#define MCF_DMA_TCR3 (*(volatile uint16_t*)(&_MBAR[0x8022]))
|
||||
#define MCF_DMA_TCR4 (*(volatile uint16_t*)(&_MBAR[0x8024]))
|
||||
#define MCF_DMA_TCR5 (*(volatile uint16_t*)(&_MBAR[0x8026]))
|
||||
#define MCF_DMA_TCR6 (*(volatile uint16_t*)(&_MBAR[0x8028]))
|
||||
#define MCF_DMA_TCR7 (*(volatile uint16_t*)(&_MBAR[0x802A]))
|
||||
#define MCF_DMA_TCR8 (*(volatile uint16_t*)(&_MBAR[0x802C]))
|
||||
#define MCF_DMA_TCR9 (*(volatile uint16_t*)(&_MBAR[0x802E]))
|
||||
#define MCF_DMA_TCR10 (*(volatile uint16_t*)(&_MBAR[0x8030]))
|
||||
#define MCF_DMA_TCR11 (*(volatile uint16_t*)(&_MBAR[0x8032]))
|
||||
#define MCF_DMA_TCR12 (*(volatile uint16_t*)(&_MBAR[0x8034]))
|
||||
#define MCF_DMA_TCR13 (*(volatile uint16_t*)(&_MBAR[0x8036]))
|
||||
#define MCF_DMA_TCR14 (*(volatile uint16_t*)(&_MBAR[0x8038]))
|
||||
#define MCF_DMA_TCR15 (*(volatile uint16_t*)(&_MBAR[0x803A]))
|
||||
#define MCF_DMA_PRIOR0 (*(volatile uint8_t *)(&_MBAR[0x803C]))
|
||||
#define MCF_DMA_PRIOR1 (*(volatile uint8_t *)(&_MBAR[0x803D]))
|
||||
#define MCF_DMA_PRIOR2 (*(volatile uint8_t *)(&_MBAR[0x803E]))
|
||||
#define MCF_DMA_PRIOR3 (*(volatile uint8_t *)(&_MBAR[0x803F]))
|
||||
#define MCF_DMA_PRIOR4 (*(volatile uint8_t *)(&_MBAR[0x8040]))
|
||||
#define MCF_DMA_PRIOR5 (*(volatile uint8_t *)(&_MBAR[0x8041]))
|
||||
#define MCF_DMA_PRIOR6 (*(volatile uint8_t *)(&_MBAR[0x8042]))
|
||||
#define MCF_DMA_PRIOR7 (*(volatile uint8_t *)(&_MBAR[0x8043]))
|
||||
#define MCF_DMA_PRIOR8 (*(volatile uint8_t *)(&_MBAR[0x8044]))
|
||||
#define MCF_DMA_PRIOR9 (*(volatile uint8_t *)(&_MBAR[0x8045]))
|
||||
#define MCF_DMA_PRIOR10 (*(volatile uint8_t *)(&_MBAR[0x8046]))
|
||||
#define MCF_DMA_PRIOR11 (*(volatile uint8_t *)(&_MBAR[0x8047]))
|
||||
#define MCF_DMA_PRIOR12 (*(volatile uint8_t *)(&_MBAR[0x8048]))
|
||||
#define MCF_DMA_PRIOR13 (*(volatile uint8_t *)(&_MBAR[0x8049]))
|
||||
#define MCF_DMA_PRIOR14 (*(volatile uint8_t *)(&_MBAR[0x804A]))
|
||||
#define MCF_DMA_PRIOR15 (*(volatile uint8_t *)(&_MBAR[0x804B]))
|
||||
#define MCF_DMA_PRIOR16 (*(volatile uint8_t *)(&_MBAR[0x804C]))
|
||||
#define MCF_DMA_PRIOR17 (*(volatile uint8_t *)(&_MBAR[0x804D]))
|
||||
#define MCF_DMA_PRIOR18 (*(volatile uint8_t *)(&_MBAR[0x804E]))
|
||||
#define MCF_DMA_PRIOR19 (*(volatile uint8_t *)(&_MBAR[0x804F]))
|
||||
#define MCF_DMA_PRIOR20 (*(volatile uint8_t *)(&_MBAR[0x8050]))
|
||||
#define MCF_DMA_PRIOR21 (*(volatile uint8_t *)(&_MBAR[0x8051]))
|
||||
#define MCF_DMA_PRIOR22 (*(volatile uint8_t *)(&_MBAR[0x8052]))
|
||||
#define MCF_DMA_PRIOR23 (*(volatile uint8_t *)(&_MBAR[0x8053]))
|
||||
#define MCF_DMA_PRIOR24 (*(volatile uint8_t *)(&_MBAR[0x8054]))
|
||||
#define MCF_DMA_PRIOR25 (*(volatile uint8_t *)(&_MBAR[0x8055]))
|
||||
#define MCF_DMA_PRIOR26 (*(volatile uint8_t *)(&_MBAR[0x8056]))
|
||||
#define MCF_DMA_PRIOR27 (*(volatile uint8_t *)(&_MBAR[0x8057]))
|
||||
#define MCF_DMA_PRIOR28 (*(volatile uint8_t *)(&_MBAR[0x8058]))
|
||||
#define MCF_DMA_PRIOR29 (*(volatile uint8_t *)(&_MBAR[0x8059]))
|
||||
#define MCF_DMA_PRIOR30 (*(volatile uint8_t *)(&_MBAR[0x805A]))
|
||||
#define MCF_DMA_PRIOR31 (*(volatile uint8_t *)(&_MBAR[0x805B]))
|
||||
#define MCF_DMA_IMCR (*(volatile uint32_t*)(&_MBAR[0x805C]))
|
||||
#define MCF_DMA_TSKSZ0 (*(volatile uint32_t*)(&_MBAR[0x8060]))
|
||||
#define MCF_DMA_TSKSZ1 (*(volatile uint32_t*)(&_MBAR[0x8064]))
|
||||
#define MCF_DMA_DBGCOMP0 (*(volatile uint32_t*)(&_MBAR[0x8070]))
|
||||
#define MCF_DMA_DBGCOMP2 (*(volatile uint32_t*)(&_MBAR[0x8074]))
|
||||
#define MCF_DMA_DBGCTL (*(volatile uint32_t*)(&_MBAR[0x8078]))
|
||||
#define MCF_DMA_TCR(x) (*(volatile uint16_t*)(&_MBAR[0x801C + ((x)*0x2)]))
|
||||
#define MCF_DMA_PRIOR(x) (*(volatile uint8_t *)(&_MBAR[0x803C + ((x)*0x1)]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_DMA_TASKBAR */
|
||||
#define MCF_DMA_TASKBAR_TASK_BASE_ADDRESS(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_DMA_CP */
|
||||
#define MCF_DMA_CP_DESCRIPTOR_POINTER(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_DMA_EP */
|
||||
#define MCF_DMA_EP_DESCRIPTOR_POINTER(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_DMA_VP */
|
||||
#define MCF_DMA_VP_VARIABLE_POINTER(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_DMA_PTD */
|
||||
#define MCF_DMA_PTD_PCTL0 (0x1)
|
||||
#define MCF_DMA_PTD_PCTL1 (0x2)
|
||||
#define MCF_DMA_PTD_PCTL13 (0x2000)
|
||||
#define MCF_DMA_PTD_PCTL14 (0x4000)
|
||||
#define MCF_DMA_PTD_PCTL15 (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_DMA_DIPR */
|
||||
#define MCF_DMA_DIPR_TASK(x) (((x)&0xFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_DMA_DIMR */
|
||||
#define MCF_DMA_DIMR_TASK(x) (((x)&0xFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_DMA_TCR */
|
||||
#define MCF_DMA_TCR_ASTSKNUM(x) (((x)&0xF)<<0)
|
||||
#define MCF_DMA_TCR_HLDINITNUM (0x20)
|
||||
#define MCF_DMA_TCR_HIPRITSKEN (0x40)
|
||||
#define MCF_DMA_TCR_ASTRT (0x80)
|
||||
#define MCF_DMA_TCR_INITNUM(x) (((x)&0x1F)<<0x8)
|
||||
#define MCF_DMA_TCR_ALWINIT (0x2000)
|
||||
#define MCF_DMA_TCR_V (0x4000)
|
||||
#define MCF_DMA_TCR_EN (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_DMA_PRIOR */
|
||||
#define MCF_DMA_PRIOR_PRI(x) (((x)&0x7)<<0)
|
||||
#define MCF_DMA_PRIOR_HLD (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_DMA_IMCR */
|
||||
#define MCF_DMA_IMCR_IMC16(x) (((x)&0x3)<<0)
|
||||
#define MCF_DMA_IMCR_IMC17(x) (((x)&0x3)<<0x2)
|
||||
#define MCF_DMA_IMCR_IMC18(x) (((x)&0x3)<<0x4)
|
||||
#define MCF_DMA_IMCR_IMC19(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_DMA_IMCR_IMC20(x) (((x)&0x3)<<0x8)
|
||||
#define MCF_DMA_IMCR_IMC21(x) (((x)&0x3)<<0xA)
|
||||
#define MCF_DMA_IMCR_IMC22(x) (((x)&0x3)<<0xC)
|
||||
#define MCF_DMA_IMCR_IMC23(x) (((x)&0x3)<<0xE)
|
||||
#define MCF_DMA_IMCR_IMC24(x) (((x)&0x3)<<0x10)
|
||||
#define MCF_DMA_IMCR_IMC25(x) (((x)&0x3)<<0x12)
|
||||
#define MCF_DMA_IMCR_IMC26(x) (((x)&0x3)<<0x14)
|
||||
#define MCF_DMA_IMCR_IMC27(x) (((x)&0x3)<<0x16)
|
||||
#define MCF_DMA_IMCR_IMC28(x) (((x)&0x3)<<0x18)
|
||||
#define MCF_DMA_IMCR_IMC29(x) (((x)&0x3)<<0x1A)
|
||||
#define MCF_DMA_IMCR_IMC30(x) (((x)&0x3)<<0x1C)
|
||||
#define MCF_DMA_IMCR_IMC31(x) (((x)&0x3)<<0x1E)
|
||||
|
||||
|
||||
#define MCF_DMA_IMCR_IMC16_FEC0RX (0x00000000)
|
||||
#define MCF_DMA_IMCR_IMC17_FEC0TX (0x00000000)
|
||||
#define MCF_DMA_IMCR_IMC18_FEC0RX (0x00000020)
|
||||
#define MCF_DMA_IMCR_IMC19_FEC0TX (0x00000080)
|
||||
#define MCF_DMA_IMCR_IMC20_FEC1RX (0x00000100)
|
||||
#define MCF_DMA_IMCR_IMC21_DREQ1 (0x00000000)
|
||||
#define MCF_DMA_IMCR_IMC21_FEC1TX (0x00000400)
|
||||
#define MCF_DMA_IMCR_IMC22_FEC0RX (0x00001000)
|
||||
#define MCF_DMA_IMCR_IMC23_FEC0TX (0x00004000)
|
||||
#define MCF_DMA_IMCR_IMC24_CTM0 (0x00010000)
|
||||
#define MCF_DMA_IMCR_IMC24_FEC1RX (0x00020000)
|
||||
#define MCF_DMA_IMCR_IMC25_CTM1 (0x00040000)
|
||||
#define MCF_DMA_IMCR_IMC25_FEC1TX (0x00080000)
|
||||
#define MCF_DMA_IMCR_IMC26_USBEP4 (0x00000000)
|
||||
#define MCF_DMA_IMCR_IMC26_CTM2 (0x00200000)
|
||||
#define MCF_DMA_IMCR_IMC27_USBEP5 (0x00000000)
|
||||
#define MCF_DMA_IMCR_IMC27_CTM3 (0x00800000)
|
||||
#define MCF_DMA_IMCR_IMC28_USBEP6 (0x00000000)
|
||||
#define MCF_DMA_IMCR_IMC28_CTM4 (0x01000000)
|
||||
#define MCF_DMA_IMCR_IMC28_DREQ1 (0x02000000)
|
||||
#define MCF_DMA_IMCR_IMC28_PSC2RX (0x03000000)
|
||||
#define MCF_DMA_IMCR_IMC29_DREQ1 (0x04000000)
|
||||
#define MCF_DMA_IMCR_IMC29_CTM5 (0x08000000)
|
||||
#define MCF_DMA_IMCR_IMC29_PSC2TX (0x0C000000)
|
||||
#define MCF_DMA_IMCR_IMC30_FEC1RX (0x00000000)
|
||||
#define MCF_DMA_IMCR_IMC30_CTM6 (0x10000000)
|
||||
#define MCF_DMA_IMCR_IMC30_PSC3RX (0x30000000)
|
||||
#define MCF_DMA_IMCR_IMC31_FEC1TX (0x00000000)
|
||||
#define MCF_DMA_IMCR_IMC31_CTM7 (0x80000000)
|
||||
#define MCF_DMA_IMCR_IMC31_PSC3TX (0xC0000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_DMA_TSKSZ0 */
|
||||
#define MCF_DMA_TSKSZ0_DSTSZ7(x) (((x)&0x3)<<0)
|
||||
#define MCF_DMA_TSKSZ0_SRCSZ7(x) (((x)&0x3)<<0x2)
|
||||
#define MCF_DMA_TSKSZ0_DSTSZ6(x) (((x)&0x3)<<0x4)
|
||||
#define MCF_DMA_TSKSZ0_SRCSZ6(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_DMA_TSKSZ0_DSTSZ5(x) (((x)&0x3)<<0x8)
|
||||
#define MCF_DMA_TSKSZ0_SRCSZ5(x) (((x)&0x3)<<0xA)
|
||||
#define MCF_DMA_TSKSZ0_DSTSZ4(x) (((x)&0x3)<<0xC)
|
||||
#define MCF_DMA_TSKSZ0_SRCSZ4(x) (((x)&0x3)<<0xE)
|
||||
#define MCF_DMA_TSKSZ0_DSTSZ3(x) (((x)&0x3)<<0x10)
|
||||
#define MCF_DMA_TSKSZ0_SRCSZ3(x) (((x)&0x3)<<0x12)
|
||||
#define MCF_DMA_TSKSZ0_DSTSZ2(x) (((x)&0x3)<<0x14)
|
||||
#define MCF_DMA_TSKSZ0_SRCSZ2(x) (((x)&0x3)<<0x16)
|
||||
#define MCF_DMA_TSKSZ0_DSTSZ1(x) (((x)&0x3)<<0x18)
|
||||
#define MCF_DMA_TSKSZ0_SRCSZ1(x) (((x)&0x3)<<0x1A)
|
||||
#define MCF_DMA_TSKSZ0_DSTSZ0(x) (((x)&0x3)<<0x1C)
|
||||
#define MCF_DMA_TSKSZ0_SRCSZ0(x) (((x)&0x3)<<0x1E)
|
||||
|
||||
/* Bit definitions and macros for MCF_DMA_TSKSZ1 */
|
||||
#define MCF_DMA_TSKSZ1_DSTSZ15(x) (((x)&0x3)<<0)
|
||||
#define MCF_DMA_TSKSZ1_SRCSZ15(x) (((x)&0x3)<<0x2)
|
||||
#define MCF_DMA_TSKSZ1_DSTSZ14(x) (((x)&0x3)<<0x4)
|
||||
#define MCF_DMA_TSKSZ1_SRCSZ14(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_DMA_TSKSZ1_DSTSZ13(x) (((x)&0x3)<<0x8)
|
||||
#define MCF_DMA_TSKSZ1_SRCSZ13(x) (((x)&0x3)<<0xA)
|
||||
#define MCF_DMA_TSKSZ1_DSTSZ12(x) (((x)&0x3)<<0xC)
|
||||
#define MCF_DMA_TSKSZ1_SRCSZ12(x) (((x)&0x3)<<0xE)
|
||||
#define MCF_DMA_TSKSZ1_DSTSZ11(x) (((x)&0x3)<<0x10)
|
||||
#define MCF_DMA_TSKSZ1_SRCSZ11(x) (((x)&0x3)<<0x12)
|
||||
#define MCF_DMA_TSKSZ1_DSTSZ10(x) (((x)&0x3)<<0x14)
|
||||
#define MCF_DMA_TSKSZ1_SRCSZ10(x) (((x)&0x3)<<0x16)
|
||||
#define MCF_DMA_TSKSZ1_DSTSZ9(x) (((x)&0x3)<<0x18)
|
||||
#define MCF_DMA_TSKSZ1_SRCSZ9(x) (((x)&0x3)<<0x1A)
|
||||
#define MCF_DMA_TSKSZ1_DSTSZ8(x) (((x)&0x3)<<0x1C)
|
||||
#define MCF_DMA_TSKSZ1_SRCSZ8(x) (((x)&0x3)<<0x1E)
|
||||
|
||||
/* Bit definitions and macros for MCF_DMA_DBGCOMP0 */
|
||||
#define MCF_DMA_DBGCOMP0_COMPARATOR_VALUE(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_DMA_DBGCOMP2 */
|
||||
#define MCF_DMA_DBGCOMP2_COMPARATOR_VALUE(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_DMA_DBGCTL */
|
||||
#define MCF_DMA_DBGCTL_I (0x2)
|
||||
#define MCF_DMA_DBGCTL_E (0x4)
|
||||
#define MCF_DMA_DBGCTL_AND_OR (0x80)
|
||||
#define MCF_DMA_DBGCTL_COMPARATOR_TYPE_2(x) (((x)&0x7)<<0x8)
|
||||
#define MCF_DMA_DBGCTL_COMPARATOR_TYPE_1(x) (((x)&0x7)<<0xB)
|
||||
#define MCF_DMA_DBGCTL_B (0x4000)
|
||||
#define MCF_DMA_DBGCTL_AA (0x8000)
|
||||
#define MCF_DMA_DBGCTL_BLOCK_TASKS(x) (((x)&0xFFFF)<<0x10)
|
||||
|
||||
|
||||
#endif /* __MCF5475_DMA_H__ */
|
||||
@@ -1,150 +0,0 @@
|
||||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.81
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF5475_DSPI_H__
|
||||
#define __MCF5475_DSPI_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* DMA Serial Peripheral Interface (DSPI)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_DSPI_DMCR (*(volatile uint32_t*)(&_MBAR[0x8A00]))
|
||||
#define MCF_DSPI_DTCR (*(volatile uint32_t*)(&_MBAR[0x8A08]))
|
||||
#define MCF_DSPI_DCTAR0 (*(volatile uint32_t*)(&_MBAR[0x8A0C]))
|
||||
#define MCF_DSPI_DCTAR1 (*(volatile uint32_t*)(&_MBAR[0x8A10]))
|
||||
#define MCF_DSPI_DCTAR2 (*(volatile uint32_t*)(&_MBAR[0x8A14]))
|
||||
#define MCF_DSPI_DCTAR3 (*(volatile uint32_t*)(&_MBAR[0x8A18]))
|
||||
#define MCF_DSPI_DCTAR4 (*(volatile uint32_t*)(&_MBAR[0x8A1C]))
|
||||
#define MCF_DSPI_DCTAR5 (*(volatile uint32_t*)(&_MBAR[0x8A20]))
|
||||
#define MCF_DSPI_DCTAR6 (*(volatile uint32_t*)(&_MBAR[0x8A24]))
|
||||
#define MCF_DSPI_DCTAR7 (*(volatile uint32_t*)(&_MBAR[0x8A28]))
|
||||
#define MCF_DSPI_DSR (*(volatile uint32_t*)(&_MBAR[0x8A2C]))
|
||||
#define MCF_DSPI_DIRSR (*(volatile uint32_t*)(&_MBAR[0x8A30]))
|
||||
#define MCF_DSPI_DTFR (*(volatile uint32_t*)(&_MBAR[0x8A34]))
|
||||
#define MCF_DSPI_DRFR (*(volatile uint32_t*)(&_MBAR[0x8A38]))
|
||||
#define MCF_DSPI_DTFDR0 (*(volatile uint32_t*)(&_MBAR[0x8A3C]))
|
||||
#define MCF_DSPI_DTFDR1 (*(volatile uint32_t*)(&_MBAR[0x8A40]))
|
||||
#define MCF_DSPI_DTFDR2 (*(volatile uint32_t*)(&_MBAR[0x8A44]))
|
||||
#define MCF_DSPI_DTFDR3 (*(volatile uint32_t*)(&_MBAR[0x8A48]))
|
||||
#define MCF_DSPI_DRFDR0 (*(volatile uint32_t*)(&_MBAR[0x8A7C]))
|
||||
#define MCF_DSPI_DRFDR1 (*(volatile uint32_t*)(&_MBAR[0x8A80]))
|
||||
#define MCF_DSPI_DRFDR2 (*(volatile uint32_t*)(&_MBAR[0x8A84]))
|
||||
#define MCF_DSPI_DRFDR3 (*(volatile uint32_t*)(&_MBAR[0x8A88]))
|
||||
#define MCF_DSPI_DCTAR(x) (*(volatile uint32_t*)(&_MBAR[0x8A0C + ((x)*0x4)]))
|
||||
#define MCF_DSPI_DTFDR(x) (*(volatile uint32_t*)(&_MBAR[0x8A3C + ((x)*0x4)]))
|
||||
#define MCF_DSPI_DRFDR(x) (*(volatile uint32_t*)(&_MBAR[0x8A7C + ((x)*0x4)]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_DSPI_DMCR */
|
||||
#define MCF_DSPI_DMCR_HALT (0x1)
|
||||
#define MCF_DSPI_DMCR_SMPL_PT(x) (((x)&0x3)<<0x8)
|
||||
#define MCF_DSPI_DMCR_SMPL_PT_0CLK (0)
|
||||
#define MCF_DSPI_DMCR_SMPL_PT_1CLK (0x100)
|
||||
#define MCF_DSPI_DMCR_SMPL_PT_2CLK (0x200)
|
||||
#define MCF_DSPI_DMCR_CRXF (0x400)
|
||||
#define MCF_DSPI_DMCR_CTXF (0x800)
|
||||
#define MCF_DSPI_DMCR_DRXF (0x1000)
|
||||
#define MCF_DSPI_DMCR_DTXF (0x2000)
|
||||
#define MCF_DSPI_DMCR_CSIS0 (0x10000)
|
||||
#define MCF_DSPI_DMCR_CSIS2 (0x40000)
|
||||
#define MCF_DSPI_DMCR_CSIS3 (0x80000)
|
||||
#define MCF_DSPI_DMCR_CSIS5 (0x200000)
|
||||
#define MCF_DSPI_DMCR_ROOE (0x1000000)
|
||||
#define MCF_DSPI_DMCR_PCSSE (0x2000000)
|
||||
#define MCF_DSPI_DMCR_MTFE (0x4000000)
|
||||
#define MCF_DSPI_DMCR_FRZ (0x8000000)
|
||||
#define MCF_DSPI_DMCR_DCONF(x) (((x)&0x3)<<0x1C)
|
||||
#define MCF_DSPI_DMCR_CSCK (0x40000000)
|
||||
#define MCF_DSPI_DMCR_MSTR (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_DSPI_DTCR */
|
||||
#define MCF_DSPI_DTCR_SPI_TCNT(x) (((x)&0xFFFF)<<0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_DSPI_DCTAR */
|
||||
#define MCF_DSPI_DCTAR_BR(x) (((x)&0xF)<<0)
|
||||
#define MCF_DSPI_DCTAR_DT(x) (((x)&0xF)<<0x4)
|
||||
#define MCF_DSPI_DCTAR_ASC(x) (((x)&0xF)<<0x8)
|
||||
#define MCF_DSPI_DCTAR_CSSCK(x) (((x)&0xF)<<0xC)
|
||||
#define MCF_DSPI_DCTAR_PBR(x) (((x)&0x3)<<0x10)
|
||||
#define MCF_DSPI_DCTAR_PBR_1CLK (0)
|
||||
#define MCF_DSPI_DCTAR_PBR_3CLK (0x10000)
|
||||
#define MCF_DSPI_DCTAR_PBR_5CLK (0x20000)
|
||||
#define MCF_DSPI_DCTAR_PBR_7CLK (0x30000)
|
||||
#define MCF_DSPI_DCTAR_PDT(x) (((x)&0x3)<<0x12)
|
||||
#define MCF_DSPI_DCTAR_PDT_1CLK (0)
|
||||
#define MCF_DSPI_DCTAR_PDT_3CLK (0x40000)
|
||||
#define MCF_DSPI_DCTAR_PDT_5CLK (0x80000)
|
||||
#define MCF_DSPI_DCTAR_PDT_7CLK (0xC0000)
|
||||
#define MCF_DSPI_DCTAR_PASC(x) (((x)&0x3)<<0x14)
|
||||
#define MCF_DSPI_DCTAR_PASC_1CLK (0)
|
||||
#define MCF_DSPI_DCTAR_PASC_3CLK (0x100000)
|
||||
#define MCF_DSPI_DCTAR_PASC_5CLK (0x200000)
|
||||
#define MCF_DSPI_DCTAR_PASC_7CLK (0x300000)
|
||||
#define MCF_DSPI_DCTAR_PCSSCK(x) (((x)&0x3)<<0x16)
|
||||
#define MCF_DSPI_DCTAR_LSBFE (0x1000000)
|
||||
#define MCF_DSPI_DCTAR_CPHA (0x2000000)
|
||||
#define MCF_DSPI_DCTAR_CPOL (0x4000000)
|
||||
#define MCF_DSPI_DCTAR_TRSZ(x) (((x)&0xF)<<0x1B)
|
||||
|
||||
/* Bit definitions and macros for MCF_DSPI_DSR */
|
||||
#define MCF_DSPI_DSR_RXPTR(x) (((x)&0xF)<<0)
|
||||
#define MCF_DSPI_DSR_RXCTR(x) (((x)&0xF)<<0x4)
|
||||
#define MCF_DSPI_DSR_TXPTR(x) (((x)&0xF)<<0x8)
|
||||
#define MCF_DSPI_DSR_TXCTR(x) (((x)&0xF)<<0xC)
|
||||
#define MCF_DSPI_DSR_RFDF (0x20000)
|
||||
#define MCF_DSPI_DSR_RFOF (0x80000)
|
||||
#define MCF_DSPI_DSR_TFFF (0x2000000)
|
||||
#define MCF_DSPI_DSR_TFUF (0x8000000)
|
||||
#define MCF_DSPI_DSR_EOQF (0x10000000)
|
||||
#define MCF_DSPI_DSR_TXRXS (0x40000000)
|
||||
#define MCF_DSPI_DSR_TCF (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_DSPI_DIRSR */
|
||||
#define MCF_DSPI_DIRSR_RFDFS (0x10000)
|
||||
#define MCF_DSPI_DIRSR_RFDFE (0x20000)
|
||||
#define MCF_DSPI_DIRSR_RFOFE (0x80000)
|
||||
#define MCF_DSPI_DIRSR_TFFFS (0x1000000)
|
||||
#define MCF_DSPI_DIRSR_TFFFE (0x2000000)
|
||||
#define MCF_DSPI_DIRSR_TFUFE (0x8000000)
|
||||
#define MCF_DSPI_DIRSR_EOQFE (0x10000000)
|
||||
#define MCF_DSPI_DIRSR_TCFE (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_DSPI_DTFR */
|
||||
#define MCF_DSPI_DTFR_TXDATA(x) (((x)&0xFFFF)<<0)
|
||||
#define MCF_DSPI_DTFR_CS0 (0x10000)
|
||||
#define MCF_DSPI_DTFR_CS2 (0x40000)
|
||||
#define MCF_DSPI_DTFR_CS3 (0x80000)
|
||||
#define MCF_DSPI_DTFR_CS5 (0x200000)
|
||||
#define MCF_DSPI_DTFR_CTCNT (0x4000000)
|
||||
#define MCF_DSPI_DTFR_EOQ (0x8000000)
|
||||
#define MCF_DSPI_DTFR_CTAS(x) (((x)&0x7)<<0x1C)
|
||||
#define MCF_DSPI_DTFR_CONT (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_DSPI_DRFR */
|
||||
#define MCF_DSPI_DRFR_RXDATA(x) (((x)&0xFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_DSPI_DTFDR */
|
||||
#define MCF_DSPI_DTFDR_TXDATA(x) (((x)&0xFFFF)<<0)
|
||||
#define MCF_DSPI_DTFDR_TXCMD(x) (((x)&0xFFFF)<<0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_DSPI_DRFDR */
|
||||
#define MCF_DSPI_DRFDR_RXDATA(x) (((x)&0xFFFF)<<0)
|
||||
|
||||
|
||||
#endif /* __MCF5475_DSPI_H__ */
|
||||
@@ -1,123 +0,0 @@
|
||||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.81
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF5475_EPORT_H__
|
||||
#define __MCF5475_EPORT_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Edge Port Module (EPORT)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_EPORT_EPPAR (*(volatile uint16_t*)(&_MBAR[0xF00]))
|
||||
#define MCF_EPORT_EPDDR (*(volatile uint8_t *)(&_MBAR[0xF04]))
|
||||
#define MCF_EPORT_EPIER (*(volatile uint8_t *)(&_MBAR[0xF05]))
|
||||
#define MCF_EPORT_EPDR (*(volatile uint8_t *)(&_MBAR[0xF08]))
|
||||
#define MCF_EPORT_EPPDR (*(volatile uint8_t *)(&_MBAR[0xF09]))
|
||||
#define MCF_EPORT_EPFR (*(volatile uint8_t *)(&_MBAR[0xF0C]))
|
||||
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_EPORT_EPPAR */
|
||||
#define MCF_EPORT_EPPAR_EPPA1(x) (((x)&0x3)<<0x2)
|
||||
#define MCF_EPORT_EPPAR_EPPA1_LEVEL (0)
|
||||
#define MCF_EPORT_EPPAR_EPPA1_RISING (0x4)
|
||||
#define MCF_EPORT_EPPAR_EPPA1_FALLING (0x8)
|
||||
#define MCF_EPORT_EPPAR_EPPA1_BOTH (0xC)
|
||||
#define MCF_EPORT_EPPAR_EPPA2(x) (((x)&0x3)<<0x4)
|
||||
#define MCF_EPORT_EPPAR_EPPA2_LEVEL (0)
|
||||
#define MCF_EPORT_EPPAR_EPPA2_RISING (0x10)
|
||||
#define MCF_EPORT_EPPAR_EPPA2_FALLING (0x20)
|
||||
#define MCF_EPORT_EPPAR_EPPA2_BOTH (0x30)
|
||||
#define MCF_EPORT_EPPAR_EPPA3(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_EPORT_EPPAR_EPPA3_LEVEL (0)
|
||||
#define MCF_EPORT_EPPAR_EPPA3_RISING (0x40)
|
||||
#define MCF_EPORT_EPPAR_EPPA3_FALLING (0x80)
|
||||
#define MCF_EPORT_EPPAR_EPPA3_BOTH (0xC0)
|
||||
#define MCF_EPORT_EPPAR_EPPA4(x) (((x)&0x3)<<0x8)
|
||||
#define MCF_EPORT_EPPAR_EPPA4_LEVEL (0)
|
||||
#define MCF_EPORT_EPPAR_EPPA4_RISING (0x100)
|
||||
#define MCF_EPORT_EPPAR_EPPA4_FALLING (0x200)
|
||||
#define MCF_EPORT_EPPAR_EPPA4_BOTH (0x300)
|
||||
#define MCF_EPORT_EPPAR_EPPA5(x) (((x)&0x3)<<0xA)
|
||||
#define MCF_EPORT_EPPAR_EPPA5_LEVEL (0)
|
||||
#define MCF_EPORT_EPPAR_EPPA5_RISING (0x400)
|
||||
#define MCF_EPORT_EPPAR_EPPA5_FALLING (0x800)
|
||||
#define MCF_EPORT_EPPAR_EPPA5_BOTH (0xC00)
|
||||
#define MCF_EPORT_EPPAR_EPPA6(x) (((x)&0x3)<<0xC)
|
||||
#define MCF_EPORT_EPPAR_EPPA6_LEVEL (0)
|
||||
#define MCF_EPORT_EPPAR_EPPA6_RISING (0x1000)
|
||||
#define MCF_EPORT_EPPAR_EPPA6_FALLING (0x2000)
|
||||
#define MCF_EPORT_EPPAR_EPPA6_BOTH (0x3000)
|
||||
#define MCF_EPORT_EPPAR_EPPA7(x) (((x)&0x3)<<0xE)
|
||||
#define MCF_EPORT_EPPAR_EPPA7_LEVEL (0)
|
||||
#define MCF_EPORT_EPPAR_EPPA7_RISING (0x4000)
|
||||
#define MCF_EPORT_EPPAR_EPPA7_FALLING (0x8000)
|
||||
#define MCF_EPORT_EPPAR_EPPA7_BOTH (0xC000)
|
||||
#define MCF_EPORT_EPPAR_LEVEL (0)
|
||||
#define MCF_EPORT_EPPAR_RISING (0x1)
|
||||
#define MCF_EPORT_EPPAR_FALLING (0x2)
|
||||
#define MCF_EPORT_EPPAR_BOTH (0x3)
|
||||
|
||||
/* Bit definitions and macros for MCF_EPORT_EPDDR */
|
||||
#define MCF_EPORT_EPDDR_EPDD1 (0x2)
|
||||
#define MCF_EPORT_EPDDR_EPDD2 (0x4)
|
||||
#define MCF_EPORT_EPDDR_EPDD3 (0x8)
|
||||
#define MCF_EPORT_EPDDR_EPDD4 (0x10)
|
||||
#define MCF_EPORT_EPDDR_EPDD5 (0x20)
|
||||
#define MCF_EPORT_EPDDR_EPDD6 (0x40)
|
||||
#define MCF_EPORT_EPDDR_EPDD7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_EPORT_EPIER */
|
||||
#define MCF_EPORT_EPIER_EPIE1 (0x2)
|
||||
#define MCF_EPORT_EPIER_EPIE2 (0x4)
|
||||
#define MCF_EPORT_EPIER_EPIE3 (0x8)
|
||||
#define MCF_EPORT_EPIER_EPIE4 (0x10)
|
||||
#define MCF_EPORT_EPIER_EPIE5 (0x20)
|
||||
#define MCF_EPORT_EPIER_EPIE6 (0x40)
|
||||
#define MCF_EPORT_EPIER_EPIE7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_EPORT_EPDR */
|
||||
#define MCF_EPORT_EPDR_EPD1 (0x2)
|
||||
#define MCF_EPORT_EPDR_EPD2 (0x4)
|
||||
#define MCF_EPORT_EPDR_EPD3 (0x8)
|
||||
#define MCF_EPORT_EPDR_EPD4 (0x10)
|
||||
#define MCF_EPORT_EPDR_EPD5 (0x20)
|
||||
#define MCF_EPORT_EPDR_EPD6 (0x40)
|
||||
#define MCF_EPORT_EPDR_EPD7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_EPORT_EPPDR */
|
||||
#define MCF_EPORT_EPPDR_EPPD1 (0x2)
|
||||
#define MCF_EPORT_EPPDR_EPPD2 (0x4)
|
||||
#define MCF_EPORT_EPPDR_EPPD3 (0x8)
|
||||
#define MCF_EPORT_EPPDR_EPPD4 (0x10)
|
||||
#define MCF_EPORT_EPPDR_EPPD5 (0x20)
|
||||
#define MCF_EPORT_EPPDR_EPPD6 (0x40)
|
||||
#define MCF_EPORT_EPPDR_EPPD7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_EPORT_EPFR */
|
||||
#define MCF_EPORT_EPFR_EPF1 (0x2)
|
||||
#define MCF_EPORT_EPFR_EPF2 (0x4)
|
||||
#define MCF_EPORT_EPFR_EPF3 (0x8)
|
||||
#define MCF_EPORT_EPFR_EPF4 (0x10)
|
||||
#define MCF_EPORT_EPFR_EPF5 (0x20)
|
||||
#define MCF_EPORT_EPFR_EPF6 (0x40)
|
||||
#define MCF_EPORT_EPFR_EPF7 (0x80)
|
||||
|
||||
|
||||
#endif /* __MCF5475_EPORT_H__ */
|
||||
@@ -1,100 +0,0 @@
|
||||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.81
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF5475_FBCS_H__
|
||||
#define __MCF5475_FBCS_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* FlexBus Chip Select Module (FBCS)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_FBCS0_CSAR (*(volatile uint32_t*)(&_MBAR[0x500]))
|
||||
#define MCF_FBCS0_CSMR (*(volatile uint32_t*)(&_MBAR[0x504]))
|
||||
#define MCF_FBCS0_CSCR (*(volatile uint32_t*)(&_MBAR[0x508]))
|
||||
|
||||
#define MCF_FBCS1_CSAR (*(volatile uint32_t*)(&_MBAR[0x50C]))
|
||||
#define MCF_FBCS1_CSMR (*(volatile uint32_t*)(&_MBAR[0x510]))
|
||||
#define MCF_FBCS1_CSCR (*(volatile uint32_t*)(&_MBAR[0x514]))
|
||||
|
||||
#define MCF_FBCS2_CSAR (*(volatile uint32_t*)(&_MBAR[0x518]))
|
||||
#define MCF_FBCS2_CSMR (*(volatile uint32_t*)(&_MBAR[0x51C]))
|
||||
#define MCF_FBCS2_CSCR (*(volatile uint32_t*)(&_MBAR[0x520]))
|
||||
|
||||
#define MCF_FBCS3_CSAR (*(volatile uint32_t*)(&_MBAR[0x524]))
|
||||
#define MCF_FBCS3_CSMR (*(volatile uint32_t*)(&_MBAR[0x528]))
|
||||
#define MCF_FBCS3_CSCR (*(volatile uint32_t*)(&_MBAR[0x52C]))
|
||||
|
||||
#define MCF_FBCS4_CSAR (*(volatile uint32_t*)(&_MBAR[0x530]))
|
||||
#define MCF_FBCS4_CSMR (*(volatile uint32_t*)(&_MBAR[0x534]))
|
||||
#define MCF_FBCS4_CSCR (*(volatile uint32_t*)(&_MBAR[0x538]))
|
||||
|
||||
#define MCF_FBCS5_CSAR (*(volatile uint32_t*)(&_MBAR[0x53C]))
|
||||
#define MCF_FBCS5_CSMR (*(volatile uint32_t*)(&_MBAR[0x540]))
|
||||
#define MCF_FBCS5_CSCR (*(volatile uint32_t*)(&_MBAR[0x544]))
|
||||
|
||||
#define MCF_FBCS_CSAR(x) (*(volatile uint32_t*)(&_MBAR[0x500 + ((x)*0xC)]))
|
||||
#define MCF_FBCS_CSMR(x) (*(volatile uint32_t*)(&_MBAR[0x504 + ((x)*0xC)]))
|
||||
#define MCF_FBCS_CSCR(x) (*(volatile uint32_t*)(&_MBAR[0x508 + ((x)*0xC)]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_FBCS_CSAR */
|
||||
#define MCF_FBCS_CSAR_BA(x) ((x)&0xFFFF0000)
|
||||
|
||||
/* Bit definitions and macros for MCF_FBCS_CSMR */
|
||||
#define MCF_FBCS_CSMR_V (0x1)
|
||||
#define MCF_FBCS_CSMR_WP (0x100)
|
||||
#define MCF_FBCS_CSMR_BAM(x) (((x)&0xFFFF)<<0x10)
|
||||
#define MCF_FBCS_CSMR_BAM_4G (0xFFFF0000)
|
||||
#define MCF_FBCS_CSMR_BAM_2G (0x7FFF0000)
|
||||
#define MCF_FBCS_CSMR_BAM_1G (0x3FFF0000)
|
||||
#define MCF_FBCS_CSMR_BAM_1024M (0x3FFF0000)
|
||||
#define MCF_FBCS_CSMR_BAM_512M (0x1FFF0000)
|
||||
#define MCF_FBCS_CSMR_BAM_256M (0xFFF0000)
|
||||
#define MCF_FBCS_CSMR_BAM_128M (0x7FF0000)
|
||||
#define MCF_FBCS_CSMR_BAM_64M (0x3FF0000)
|
||||
#define MCF_FBCS_CSMR_BAM_32M (0x1FF0000)
|
||||
#define MCF_FBCS_CSMR_BAM_16M (0xFF0000)
|
||||
#define MCF_FBCS_CSMR_BAM_8M (0x7F0000)
|
||||
#define MCF_FBCS_CSMR_BAM_4M (0x3F0000)
|
||||
#define MCF_FBCS_CSMR_BAM_2M (0x1F0000)
|
||||
#define MCF_FBCS_CSMR_BAM_1M (0xF0000)
|
||||
#define MCF_FBCS_CSMR_BAM_1024K (0xF0000)
|
||||
#define MCF_FBCS_CSMR_BAM_512K (0x70000)
|
||||
#define MCF_FBCS_CSMR_BAM_256K (0x30000)
|
||||
#define MCF_FBCS_CSMR_BAM_128K (0x10000)
|
||||
#define MCF_FBCS_CSMR_BAM_64K (0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FBCS_CSCR */
|
||||
#define MCF_FBCS_CSCR_BSTW (0x8)
|
||||
#define MCF_FBCS_CSCR_BSTR (0x10)
|
||||
#define MCF_FBCS_CSCR_BEM (0x20)
|
||||
#define MCF_FBCS_CSCR_PS(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_FBCS_CSCR_PS_32 (0)
|
||||
#define MCF_FBCS_CSCR_PS_8 (0x40)
|
||||
#define MCF_FBCS_CSCR_PS_16 (0x80)
|
||||
#define MCF_FBCS_CSCR_AA (0x100)
|
||||
#define MCF_FBCS_CSCR_WS(x) (((x)&0x3F)<<0xA)
|
||||
#define MCF_FBCS_CSCR_WRAH(x) (((x)&0x3)<<0x10)
|
||||
#define MCF_FBCS_CSCR_RDAH(x) (((x)&0x3)<<0x12)
|
||||
#define MCF_FBCS_CSCR_ASET(x) (((x)&0x3)<<0x14)
|
||||
#define MCF_FBCS_CSCR_SWSEN (0x800000)
|
||||
#define MCF_FBCS_CSCR_SWS(x) (((x)&0x3F)<<0x1A)
|
||||
|
||||
|
||||
#endif /* __MCF5475_FBCS_H__ */
|
||||
@@ -1,680 +0,0 @@
|
||||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.81
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF5475_FEC_H__
|
||||
#define __MCF5475_FEC_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Fast Ethernet Controller(FEC)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_FEC0_EIR (*(volatile uint32_t*)(&_MBAR[0x9004]))
|
||||
#define MCF_FEC0_EIMR (*(volatile uint32_t*)(&_MBAR[0x9008]))
|
||||
#define MCF_FEC0_ECR (*(volatile uint32_t*)(&_MBAR[0x9024]))
|
||||
#define MCF_FEC0_MMFR (*(volatile uint32_t*)(&_MBAR[0x9040]))
|
||||
#define MCF_FEC0_MSCR (*(volatile uint32_t*)(&_MBAR[0x9044]))
|
||||
#define MCF_FEC0_MIBC (*(volatile uint32_t*)(&_MBAR[0x9064]))
|
||||
#define MCF_FEC0_RCR (*(volatile uint32_t*)(&_MBAR[0x9084]))
|
||||
#define MCF_FEC0_RHR (*(volatile uint32_t*)(&_MBAR[0x9088]))
|
||||
#define MCF_FEC0_TCR (*(volatile uint32_t*)(&_MBAR[0x90C4]))
|
||||
#define MCF_FEC0_PALR (*(volatile uint32_t*)(&_MBAR[0x90E4]))
|
||||
#define MCF_FEC0_PAHR (*(volatile uint32_t*)(&_MBAR[0x90E8]))
|
||||
#define MCF_FEC0_OPD (*(volatile uint32_t*)(&_MBAR[0x90EC]))
|
||||
#define MCF_FEC0_IAUR (*(volatile uint32_t*)(&_MBAR[0x9118]))
|
||||
#define MCF_FEC0_IALR (*(volatile uint32_t*)(&_MBAR[0x911C]))
|
||||
#define MCF_FEC0_GAUR (*(volatile uint32_t*)(&_MBAR[0x9120]))
|
||||
#define MCF_FEC0_GALR (*(volatile uint32_t*)(&_MBAR[0x9124]))
|
||||
#define MCF_FEC0_FECTFWR (*(volatile uint32_t*)(&_MBAR[0x9144]))
|
||||
#define MCF_FEC0_FECRFDR (*(volatile uint32_t*)(&_MBAR[0x9184]))
|
||||
#define MCF_FEC0_FECRFSR (*(volatile uint32_t*)(&_MBAR[0x9188]))
|
||||
#define MCF_FEC0_FECRFCR (*(volatile uint32_t*)(&_MBAR[0x918C]))
|
||||
#define MCF_FEC0_FECRLRFP (*(volatile uint32_t*)(&_MBAR[0x9190]))
|
||||
#define MCF_FEC0_FECRLWFP (*(volatile uint32_t*)(&_MBAR[0x9194]))
|
||||
#define MCF_FEC0_FECRFAR (*(volatile uint32_t*)(&_MBAR[0x9198]))
|
||||
#define MCF_FEC0_FECRFRP (*(volatile uint32_t*)(&_MBAR[0x919C]))
|
||||
#define MCF_FEC0_FECRFWP (*(volatile uint32_t*)(&_MBAR[0x91A0]))
|
||||
#define MCF_FEC0_FECTFDR (*(volatile uint32_t*)(&_MBAR[0x91A4]))
|
||||
#define MCF_FEC0_FECTFSR (*(volatile uint32_t*)(&_MBAR[0x91A8]))
|
||||
#define MCF_FEC0_FECTFCR (*(volatile uint32_t*)(&_MBAR[0x91AC]))
|
||||
#define MCF_FEC0_FECTLRFP (*(volatile uint32_t*)(&_MBAR[0x91B0]))
|
||||
#define MCF_FEC0_FECTLWFP (*(volatile uint32_t*)(&_MBAR[0x91B4]))
|
||||
#define MCF_FEC0_FECTFAR (*(volatile uint32_t*)(&_MBAR[0x91B8]))
|
||||
#define MCF_FEC0_FECTFRP (*(volatile uint32_t*)(&_MBAR[0x91BC]))
|
||||
#define MCF_FEC0_FECTFWP (*(volatile uint32_t*)(&_MBAR[0x91C0]))
|
||||
#define MCF_FEC0_FECFRST (*(volatile uint32_t*)(&_MBAR[0x91C4]))
|
||||
#define MCF_FEC0_FECCTCWR (*(volatile uint32_t*)(&_MBAR[0x91C8]))
|
||||
#define MCF_FEC0_RMON_T_DROP (*(volatile uint32_t*)(&_MBAR[0x9200]))
|
||||
#define MCF_FEC0_RMON_T_PACKETS (*(volatile uint32_t*)(&_MBAR[0x9204]))
|
||||
#define MCF_FEC0_RMON_T_BC_PKT (*(volatile uint32_t*)(&_MBAR[0x9208]))
|
||||
#define MCF_FEC0_RMON_T_MC_PKT (*(volatile uint32_t*)(&_MBAR[0x920C]))
|
||||
#define MCF_FEC0_RMON_T_CRC_ALIGN (*(volatile uint32_t*)(&_MBAR[0x9210]))
|
||||
#define MCF_FEC0_RMON_T_UNDERSIZE (*(volatile uint32_t*)(&_MBAR[0x9214]))
|
||||
#define MCF_FEC0_RMON_T_OVERSIZE (*(volatile uint32_t*)(&_MBAR[0x9218]))
|
||||
#define MCF_FEC0_RMON_T_FRAG (*(volatile uint32_t*)(&_MBAR[0x921C]))
|
||||
#define MCF_FEC0_RMON_T_JAB (*(volatile uint32_t*)(&_MBAR[0x9220]))
|
||||
#define MCF_FEC0_RMON_T_COL (*(volatile uint32_t*)(&_MBAR[0x9224]))
|
||||
#define MCF_FEC0_RMON_T_P64 (*(volatile uint32_t*)(&_MBAR[0x9228]))
|
||||
#define MCF_FEC0_RMON_T_P65TO127 (*(volatile uint32_t*)(&_MBAR[0x922C]))
|
||||
#define MCF_FEC0_RMON_T_P128TO255 (*(volatile uint32_t*)(&_MBAR[0x9230]))
|
||||
#define MCF_FEC0_RMON_T_P256TO511 (*(volatile uint32_t*)(&_MBAR[0x9234]))
|
||||
#define MCF_FEC0_RMON_T_P512TO1023 (*(volatile uint32_t*)(&_MBAR[0x9238]))
|
||||
#define MCF_FEC0_RMON_T_P1024TO2047 (*(volatile uint32_t*)(&_MBAR[0x923C]))
|
||||
#define MCF_FEC0_RMON_T_P_GTE2048 (*(volatile uint32_t*)(&_MBAR[0x9240]))
|
||||
#define MCF_FEC0_RMON_T_OCTETS (*(volatile uint32_t*)(&_MBAR[0x9244]))
|
||||
#define MCF_FEC0_IEEE_T_DROP (*(volatile uint32_t*)(&_MBAR[0x9248]))
|
||||
#define MCF_FEC0_IEEE_T_FRAME_OK (*(volatile uint32_t*)(&_MBAR[0x924C]))
|
||||
#define MCF_FEC0_IEEE_T_1COL (*(volatile uint32_t*)(&_MBAR[0x9250]))
|
||||
#define MCF_FEC0_IEEE_T_MCOL (*(volatile uint32_t*)(&_MBAR[0x9254]))
|
||||
#define MCF_FEC0_IEEE_T_DEF (*(volatile uint32_t*)(&_MBAR[0x9258]))
|
||||
#define MCF_FEC0_IEEE_T_LCOL (*(volatile uint32_t*)(&_MBAR[0x925C]))
|
||||
#define MCF_FEC0_IEEE_T_EXCOL (*(volatile uint32_t*)(&_MBAR[0x9260]))
|
||||
#define MCF_FEC0_IEEE_T_MACERR (*(volatile uint32_t*)(&_MBAR[0x9264]))
|
||||
#define MCF_FEC0_IEEE_T_CSERR (*(volatile uint32_t*)(&_MBAR[0x9268]))
|
||||
#define MCF_FEC0_IEEE_T_SQE (*(volatile uint32_t*)(&_MBAR[0x926C]))
|
||||
#define MCF_FEC0_IEEE_T_FDXFC (*(volatile uint32_t*)(&_MBAR[0x9270]))
|
||||
#define MCF_FEC0_IEEE_T_OCTETS_OK (*(volatile uint32_t*)(&_MBAR[0x9274]))
|
||||
#define MCF_FEC0_RMON_R_DROP (*(volatile uint32_t*)(&_MBAR[0x9280]))
|
||||
#define MCF_FEC0_RMON_R_PACKETS (*(volatile uint32_t*)(&_MBAR[0x9284]))
|
||||
#define MCF_FEC0_RMON_R_BC_PKT (*(volatile uint32_t*)(&_MBAR[0x9288]))
|
||||
#define MCF_FEC0_RMON_R_MC_PKT (*(volatile uint32_t*)(&_MBAR[0x928C]))
|
||||
#define MCF_FEC0_RMON_R_CRC_ALIGN (*(volatile uint32_t*)(&_MBAR[0x9290]))
|
||||
#define MCF_FEC0_RMON_R_UNDERSIZE (*(volatile uint32_t*)(&_MBAR[0x9294]))
|
||||
#define MCF_FEC0_RMON_R_OVERSIZE (*(volatile uint32_t*)(&_MBAR[0x9298]))
|
||||
#define MCF_FEC0_RMON_R_FRAG (*(volatile uint32_t*)(&_MBAR[0x929C]))
|
||||
#define MCF_FEC0_RMON_R_JAB (*(volatile uint32_t*)(&_MBAR[0x92A0]))
|
||||
#define MCF_FEC0_RMON_R_RESVD_0 (*(volatile uint32_t*)(&_MBAR[0x92A4]))
|
||||
#define MCF_FEC0_RMON_R_P64 (*(volatile uint32_t*)(&_MBAR[0x92A8]))
|
||||
#define MCF_FEC0_RMON_R_P65TO127 (*(volatile uint32_t*)(&_MBAR[0x92AC]))
|
||||
#define MCF_FEC0_RMON_R_P128TO255 (*(volatile uint32_t*)(&_MBAR[0x92B0]))
|
||||
#define MCF_FEC0_RMON_R_P256TO511 (*(volatile uint32_t*)(&_MBAR[0x92B4]))
|
||||
#define MCF_FEC0_RMON_R_P512TO1023 (*(volatile uint32_t*)(&_MBAR[0x92B8]))
|
||||
#define MCF_FEC0_RMON_R_P1024TO2047 (*(volatile uint32_t*)(&_MBAR[0x92BC]))
|
||||
#define MCF_FEC0_RMON_R_P_GTE2048 (*(volatile uint32_t*)(&_MBAR[0x92C0]))
|
||||
#define MCF_FEC0_RMON_R_OCTETS (*(volatile uint32_t*)(&_MBAR[0x92C4]))
|
||||
#define MCF_FEC0_IEEE_R_DROP (*(volatile uint32_t*)(&_MBAR[0x92C8]))
|
||||
#define MCF_FEC0_IEEE_R_FRAME_OK (*(volatile uint32_t*)(&_MBAR[0x92CC]))
|
||||
#define MCF_FEC0_IEEE_R_CRC (*(volatile uint32_t*)(&_MBAR[0x92D0]))
|
||||
#define MCF_FEC0_IEEE_R_ALIGN (*(volatile uint32_t*)(&_MBAR[0x92D4]))
|
||||
#define MCF_FEC0_IEEE_R_MACERR (*(volatile uint32_t*)(&_MBAR[0x92D8]))
|
||||
#define MCF_FEC0_IEEE_R_FDXFC (*(volatile uint32_t*)(&_MBAR[0x92DC]))
|
||||
#define MCF_FEC0_IEEE_R_OCTETS_OK (*(volatile uint32_t*)(&_MBAR[0x92E0]))
|
||||
|
||||
#define MCF_FEC1_EIR (*(volatile uint32_t*)(&_MBAR[0x9804]))
|
||||
#define MCF_FEC1_EIMR (*(volatile uint32_t*)(&_MBAR[0x9808]))
|
||||
#define MCF_FEC1_ECR (*(volatile uint32_t*)(&_MBAR[0x9824]))
|
||||
#define MCF_FEC1_MMFR (*(volatile uint32_t*)(&_MBAR[0x9840]))
|
||||
#define MCF_FEC1_MSCR (*(volatile uint32_t*)(&_MBAR[0x9844]))
|
||||
#define MCF_FEC1_MIBC (*(volatile uint32_t*)(&_MBAR[0x9864]))
|
||||
#define MCF_FEC1_RCR (*(volatile uint32_t*)(&_MBAR[0x9884]))
|
||||
#define MCF_FEC1_RHR (*(volatile uint32_t*)(&_MBAR[0x9888]))
|
||||
#define MCF_FEC1_TCR (*(volatile uint32_t*)(&_MBAR[0x98C4]))
|
||||
#define MCF_FEC1_PALR (*(volatile uint32_t*)(&_MBAR[0x98E4]))
|
||||
#define MCF_FEC1_PAHR (*(volatile uint32_t*)(&_MBAR[0x98E8]))
|
||||
#define MCF_FEC1_OPD (*(volatile uint32_t*)(&_MBAR[0x98EC]))
|
||||
#define MCF_FEC1_IAUR (*(volatile uint32_t*)(&_MBAR[0x9918]))
|
||||
#define MCF_FEC1_IALR (*(volatile uint32_t*)(&_MBAR[0x991C]))
|
||||
#define MCF_FEC1_GAUR (*(volatile uint32_t*)(&_MBAR[0x9920]))
|
||||
#define MCF_FEC1_GALR (*(volatile uint32_t*)(&_MBAR[0x9924]))
|
||||
#define MCF_FEC1_FECTFWR (*(volatile uint32_t*)(&_MBAR[0x9944]))
|
||||
#define MCF_FEC1_FECRFDR (*(volatile uint32_t*)(&_MBAR[0x9984]))
|
||||
#define MCF_FEC1_FECRFSR (*(volatile uint32_t*)(&_MBAR[0x9988]))
|
||||
#define MCF_FEC1_FECRFCR (*(volatile uint32_t*)(&_MBAR[0x998C]))
|
||||
#define MCF_FEC1_FECRLRFP (*(volatile uint32_t*)(&_MBAR[0x9990]))
|
||||
#define MCF_FEC1_FECRLWFP (*(volatile uint32_t*)(&_MBAR[0x9994]))
|
||||
#define MCF_FEC1_FECRFAR (*(volatile uint32_t*)(&_MBAR[0x9998]))
|
||||
#define MCF_FEC1_FECRFRP (*(volatile uint32_t*)(&_MBAR[0x999C]))
|
||||
#define MCF_FEC1_FECRFWP (*(volatile uint32_t*)(&_MBAR[0x99A0]))
|
||||
#define MCF_FEC1_FECTFDR (*(volatile uint32_t*)(&_MBAR[0x99A4]))
|
||||
#define MCF_FEC1_FECTFSR (*(volatile uint32_t*)(&_MBAR[0x99A8]))
|
||||
#define MCF_FEC1_FECTFCR (*(volatile uint32_t*)(&_MBAR[0x99AC]))
|
||||
#define MCF_FEC1_FECTLRFP (*(volatile uint32_t*)(&_MBAR[0x99B0]))
|
||||
#define MCF_FEC1_FECTLWFP (*(volatile uint32_t*)(&_MBAR[0x99B4]))
|
||||
#define MCF_FEC1_FECTFAR (*(volatile uint32_t*)(&_MBAR[0x99B8]))
|
||||
#define MCF_FEC1_FECTFRP (*(volatile uint32_t*)(&_MBAR[0x99BC]))
|
||||
#define MCF_FEC1_FECTFWP (*(volatile uint32_t*)(&_MBAR[0x99C0]))
|
||||
#define MCF_FEC1_FECFRST (*(volatile uint32_t*)(&_MBAR[0x99C4]))
|
||||
#define MCF_FEC1_FECCTCWR (*(volatile uint32_t*)(&_MBAR[0x99C8]))
|
||||
#define MCF_FEC1_RMON_T_DROP (*(volatile uint32_t*)(&_MBAR[0x9A00]))
|
||||
#define MCF_FEC1_RMON_T_PACKETS (*(volatile uint32_t*)(&_MBAR[0x9A04]))
|
||||
#define MCF_FEC1_RMON_T_BC_PKT (*(volatile uint32_t*)(&_MBAR[0x9A08]))
|
||||
#define MCF_FEC1_RMON_T_MC_PKT (*(volatile uint32_t*)(&_MBAR[0x9A0C]))
|
||||
#define MCF_FEC1_RMON_T_CRC_ALIGN (*(volatile uint32_t*)(&_MBAR[0x9A10]))
|
||||
#define MCF_FEC1_RMON_T_UNDERSIZE (*(volatile uint32_t*)(&_MBAR[0x9A14]))
|
||||
#define MCF_FEC1_RMON_T_OVERSIZE (*(volatile uint32_t*)(&_MBAR[0x9A18]))
|
||||
#define MCF_FEC1_RMON_T_FRAG (*(volatile uint32_t*)(&_MBAR[0x9A1C]))
|
||||
#define MCF_FEC1_RMON_T_JAB (*(volatile uint32_t*)(&_MBAR[0x9A20]))
|
||||
#define MCF_FEC1_RMON_T_COL (*(volatile uint32_t*)(&_MBAR[0x9A24]))
|
||||
#define MCF_FEC1_RMON_T_P64 (*(volatile uint32_t*)(&_MBAR[0x9A28]))
|
||||
#define MCF_FEC1_RMON_T_P65TO127 (*(volatile uint32_t*)(&_MBAR[0x9A2C]))
|
||||
#define MCF_FEC1_RMON_T_P128TO255 (*(volatile uint32_t*)(&_MBAR[0x9A30]))
|
||||
#define MCF_FEC1_RMON_T_P256TO511 (*(volatile uint32_t*)(&_MBAR[0x9A34]))
|
||||
#define MCF_FEC1_RMON_T_P512TO1023 (*(volatile uint32_t*)(&_MBAR[0x9A38]))
|
||||
#define MCF_FEC1_RMON_T_P1024TO2047 (*(volatile uint32_t*)(&_MBAR[0x9A3C]))
|
||||
#define MCF_FEC1_RMON_T_P_GTE2048 (*(volatile uint32_t*)(&_MBAR[0x9A40]))
|
||||
#define MCF_FEC1_RMON_T_OCTETS (*(volatile uint32_t*)(&_MBAR[0x9A44]))
|
||||
#define MCF_FEC1_IEEE_T_DROP (*(volatile uint32_t*)(&_MBAR[0x9A48]))
|
||||
#define MCF_FEC1_IEEE_T_FRAME_OK (*(volatile uint32_t*)(&_MBAR[0x9A4C]))
|
||||
#define MCF_FEC1_IEEE_T_1COL (*(volatile uint32_t*)(&_MBAR[0x9A50]))
|
||||
#define MCF_FEC1_IEEE_T_MCOL (*(volatile uint32_t*)(&_MBAR[0x9A54]))
|
||||
#define MCF_FEC1_IEEE_T_DEF (*(volatile uint32_t*)(&_MBAR[0x9A58]))
|
||||
#define MCF_FEC1_IEEE_T_LCOL (*(volatile uint32_t*)(&_MBAR[0x9A5C]))
|
||||
#define MCF_FEC1_IEEE_T_EXCOL (*(volatile uint32_t*)(&_MBAR[0x9A60]))
|
||||
#define MCF_FEC1_IEEE_T_MACERR (*(volatile uint32_t*)(&_MBAR[0x9A64]))
|
||||
#define MCF_FEC1_IEEE_T_CSERR (*(volatile uint32_t*)(&_MBAR[0x9A68]))
|
||||
#define MCF_FEC1_IEEE_T_SQE (*(volatile uint32_t*)(&_MBAR[0x9A6C]))
|
||||
#define MCF_FEC1_IEEE_T_FDXFC (*(volatile uint32_t*)(&_MBAR[0x9A70]))
|
||||
#define MCF_FEC1_IEEE_T_OCTETS_OK (*(volatile uint32_t*)(&_MBAR[0x9A74]))
|
||||
#define MCF_FEC1_RMON_R_DROP (*(volatile uint32_t*)(&_MBAR[0x9A80]))
|
||||
#define MCF_FEC1_RMON_R_PACKETS (*(volatile uint32_t*)(&_MBAR[0x9A84]))
|
||||
#define MCF_FEC1_RMON_R_BC_PKT (*(volatile uint32_t*)(&_MBAR[0x9A88]))
|
||||
#define MCF_FEC1_RMON_R_MC_PKT (*(volatile uint32_t*)(&_MBAR[0x9A8C]))
|
||||
#define MCF_FEC1_RMON_R_CRC_ALIGN (*(volatile uint32_t*)(&_MBAR[0x9A90]))
|
||||
#define MCF_FEC1_RMON_R_UNDERSIZE (*(volatile uint32_t*)(&_MBAR[0x9A94]))
|
||||
#define MCF_FEC1_RMON_R_OVERSIZE (*(volatile uint32_t*)(&_MBAR[0x9A98]))
|
||||
#define MCF_FEC1_RMON_R_FRAG (*(volatile uint32_t*)(&_MBAR[0x9A9C]))
|
||||
#define MCF_FEC1_RMON_R_JAB (*(volatile uint32_t*)(&_MBAR[0x9AA0]))
|
||||
#define MCF_FEC1_RMON_R_RESVD_0 (*(volatile uint32_t*)(&_MBAR[0x9AA4]))
|
||||
#define MCF_FEC1_RMON_R_P64 (*(volatile uint32_t*)(&_MBAR[0x9AA8]))
|
||||
#define MCF_FEC1_RMON_R_P65TO127 (*(volatile uint32_t*)(&_MBAR[0x9AAC]))
|
||||
#define MCF_FEC1_RMON_R_P128TO255 (*(volatile uint32_t*)(&_MBAR[0x9AB0]))
|
||||
#define MCF_FEC1_RMON_R_P256TO511 (*(volatile uint32_t*)(&_MBAR[0x9AB4]))
|
||||
#define MCF_FEC1_RMON_R_P512TO1023 (*(volatile uint32_t*)(&_MBAR[0x9AB8]))
|
||||
#define MCF_FEC1_RMON_R_P1024TO2047 (*(volatile uint32_t*)(&_MBAR[0x9ABC]))
|
||||
#define MCF_FEC1_RMON_R_P_GTE2048 (*(volatile uint32_t*)(&_MBAR[0x9AC0]))
|
||||
#define MCF_FEC1_RMON_R_OCTETS (*(volatile uint32_t*)(&_MBAR[0x9AC4]))
|
||||
#define MCF_FEC1_IEEE_R_DROP (*(volatile uint32_t*)(&_MBAR[0x9AC8]))
|
||||
#define MCF_FEC1_IEEE_R_FRAME_OK (*(volatile uint32_t*)(&_MBAR[0x9ACC]))
|
||||
#define MCF_FEC1_IEEE_R_CRC (*(volatile uint32_t*)(&_MBAR[0x9AD0]))
|
||||
#define MCF_FEC1_IEEE_R_ALIGN (*(volatile uint32_t*)(&_MBAR[0x9AD4]))
|
||||
#define MCF_FEC1_IEEE_R_MACERR (*(volatile uint32_t*)(&_MBAR[0x9AD8]))
|
||||
#define MCF_FEC1_IEEE_R_FDXFC (*(volatile uint32_t*)(&_MBAR[0x9ADC]))
|
||||
#define MCF_FEC1_IEEE_R_OCTETS_OK (*(volatile uint32_t*)(&_MBAR[0x9AE0]))
|
||||
|
||||
#define MCF_FEC_EIR(x) (*(volatile uint32_t*)(&_MBAR[0x9004 + ((x)*0x800)]))
|
||||
#define MCF_FEC_EIMR(x) (*(volatile uint32_t*)(&_MBAR[0x9008 + ((x)*0x800)]))
|
||||
#define MCF_FEC_ECR(x) (*(volatile uint32_t*)(&_MBAR[0x9024 + ((x)*0x800)]))
|
||||
#define MCF_FEC_MMFR(x) (*(volatile uint32_t*)(&_MBAR[0x9040 + ((x)*0x800)]))
|
||||
#define MCF_FEC_MSCR(x) (*(volatile uint32_t*)(&_MBAR[0x9044 + ((x)*0x800)]))
|
||||
#define MCF_FEC_MIBC(x) (*(volatile uint32_t*)(&_MBAR[0x9064 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RCR(x) (*(volatile uint32_t*)(&_MBAR[0x9084 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RHR(x) (*(volatile uint32_t*)(&_MBAR[0x9088 + ((x)*0x800)]))
|
||||
#define MCF_FEC_TCR(x) (*(volatile uint32_t*)(&_MBAR[0x90C4 + ((x)*0x800)]))
|
||||
#define MCF_FEC_PALR(x) (*(volatile uint32_t*)(&_MBAR[0x90E4 + ((x)*0x800)]))
|
||||
#define MCF_FEC_PAHR(x) (*(volatile uint32_t*)(&_MBAR[0x90E8 + ((x)*0x800)]))
|
||||
#define MCF_FEC_OPD(x) (*(volatile uint32_t*)(&_MBAR[0x90EC + ((x)*0x800)]))
|
||||
#define MCF_FEC_IAUR(x) (*(volatile uint32_t*)(&_MBAR[0x9118 + ((x)*0x800)]))
|
||||
#define MCF_FEC_IALR(x) (*(volatile uint32_t*)(&_MBAR[0x911C + ((x)*0x800)]))
|
||||
#define MCF_FEC_GAUR(x) (*(volatile uint32_t*)(&_MBAR[0x9120 + ((x)*0x800)]))
|
||||
#define MCF_FEC_GALR(x) (*(volatile uint32_t*)(&_MBAR[0x9124 + ((x)*0x800)]))
|
||||
#define MCF_FEC_FECTFWR(x) (*(volatile uint32_t*)(&_MBAR[0x9144 + ((x)*0x800)]))
|
||||
#define MCF_FEC_FECRFDR(x) (*(volatile uint32_t*)(&_MBAR[0x9184 + ((x)*0x800)]))
|
||||
#define MCF_FEC_FECRFSR(x) (*(volatile uint32_t*)(&_MBAR[0x9188 + ((x)*0x800)]))
|
||||
#define MCF_FEC_FECRFCR(x) (*(volatile uint32_t*)(&_MBAR[0x918C + ((x)*0x800)]))
|
||||
#define MCF_FEC_FECRLRFP(x) (*(volatile uint32_t*)(&_MBAR[0x9190 + ((x)*0x800)]))
|
||||
#define MCF_FEC_FECRLWFP(x) (*(volatile uint32_t*)(&_MBAR[0x9194 + ((x)*0x800)]))
|
||||
#define MCF_FEC_FECRFAR(x) (*(volatile uint32_t*)(&_MBAR[0x9198 + ((x)*0x800)]))
|
||||
#define MCF_FEC_FECRFRP(x) (*(volatile uint32_t*)(&_MBAR[0x919C + ((x)*0x800)]))
|
||||
#define MCF_FEC_FECRFWP(x) (*(volatile uint32_t*)(&_MBAR[0x91A0 + ((x)*0x800)]))
|
||||
#define MCF_FEC_FECTFDR(x) (*(volatile uint32_t*)(&_MBAR[0x91A4 + ((x)*0x800)]))
|
||||
#define MCF_FEC_FECTFSR(x) (*(volatile uint32_t*)(&_MBAR[0x91A8 + ((x)*0x800)]))
|
||||
#define MCF_FEC_FECTFCR(x) (*(volatile uint32_t*)(&_MBAR[0x91AC + ((x)*0x800)]))
|
||||
#define MCF_FEC_FECTLRFP(x) (*(volatile uint32_t*)(&_MBAR[0x91B0 + ((x)*0x800)]))
|
||||
#define MCF_FEC_FECTLWFP(x) (*(volatile uint32_t*)(&_MBAR[0x91B4 + ((x)*0x800)]))
|
||||
#define MCF_FEC_FECTFAR(x) (*(volatile uint32_t*)(&_MBAR[0x91B8 + ((x)*0x800)]))
|
||||
#define MCF_FEC_FECTFRP(x) (*(volatile uint32_t*)(&_MBAR[0x91BC + ((x)*0x800)]))
|
||||
#define MCF_FEC_FECTFWP(x) (*(volatile uint32_t*)(&_MBAR[0x91C0 + ((x)*0x800)]))
|
||||
#define MCF_FEC_FECFRST(x) (*(volatile uint32_t*)(&_MBAR[0x91C4 + ((x)*0x800)]))
|
||||
#define MCF_FEC_FECCTCWR(x) (*(volatile uint32_t*)(&_MBAR[0x91C8 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_T_DROP(x) (*(volatile uint32_t*)(&_MBAR[0x9200 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_T_PACKETS(x) (*(volatile uint32_t*)(&_MBAR[0x9204 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_T_BC_PKT(x) (*(volatile uint32_t*)(&_MBAR[0x9208 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_T_MC_PKT(x) (*(volatile uint32_t*)(&_MBAR[0x920C + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_T_CRC_ALIGN(x) (*(volatile uint32_t*)(&_MBAR[0x9210 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_T_UNDERSIZE(x) (*(volatile uint32_t*)(&_MBAR[0x9214 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_T_OVERSIZE(x) (*(volatile uint32_t*)(&_MBAR[0x9218 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_T_FRAG(x) (*(volatile uint32_t*)(&_MBAR[0x921C + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_T_JAB(x) (*(volatile uint32_t*)(&_MBAR[0x9220 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_T_COL(x) (*(volatile uint32_t*)(&_MBAR[0x9224 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_T_P64(x) (*(volatile uint32_t*)(&_MBAR[0x9228 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_T_P65TO127(x) (*(volatile uint32_t*)(&_MBAR[0x922C + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_T_P128TO255(x) (*(volatile uint32_t*)(&_MBAR[0x9230 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_T_P256TO511(x) (*(volatile uint32_t*)(&_MBAR[0x9234 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_T_P512TO1023(x) (*(volatile uint32_t*)(&_MBAR[0x9238 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_T_P1024TO2047(x) (*(volatile uint32_t*)(&_MBAR[0x923C + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_T_P_GTE2048(x) (*(volatile uint32_t*)(&_MBAR[0x9240 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_T_OCTETS(x) (*(volatile uint32_t*)(&_MBAR[0x9244 + ((x)*0x800)]))
|
||||
#define MCF_FEC_IEEE_T_DROP(x) (*(volatile uint32_t*)(&_MBAR[0x9248 + ((x)*0x800)]))
|
||||
#define MCF_FEC_IEEE_T_FRAME_OK(x) (*(volatile uint32_t*)(&_MBAR[0x924C + ((x)*0x800)]))
|
||||
#define MCF_FEC_IEEE_T_1COL(x) (*(volatile uint32_t*)(&_MBAR[0x9250 + ((x)*0x800)]))
|
||||
#define MCF_FEC_IEEE_T_MCOL(x) (*(volatile uint32_t*)(&_MBAR[0x9254 + ((x)*0x800)]))
|
||||
#define MCF_FEC_IEEE_T_DEF(x) (*(volatile uint32_t*)(&_MBAR[0x9258 + ((x)*0x800)]))
|
||||
#define MCF_FEC_IEEE_T_LCOL(x) (*(volatile uint32_t*)(&_MBAR[0x925C + ((x)*0x800)]))
|
||||
#define MCF_FEC_IEEE_T_EXCOL(x) (*(volatile uint32_t*)(&_MBAR[0x9260 + ((x)*0x800)]))
|
||||
#define MCF_FEC_IEEE_T_MACERR(x) (*(volatile uint32_t*)(&_MBAR[0x9264 + ((x)*0x800)]))
|
||||
#define MCF_FEC_IEEE_T_CSERR(x) (*(volatile uint32_t*)(&_MBAR[0x9268 + ((x)*0x800)]))
|
||||
#define MCF_FEC_IEEE_T_SQE(x) (*(volatile uint32_t*)(&_MBAR[0x926C + ((x)*0x800)]))
|
||||
#define MCF_FEC_IEEE_T_FDXFC(x) (*(volatile uint32_t*)(&_MBAR[0x9270 + ((x)*0x800)]))
|
||||
#define MCF_FEC_IEEE_T_OCTETS_OK(x) (*(volatile uint32_t*)(&_MBAR[0x9274 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_R_DROP(x) (*(volatile uint32_t*)(&_MBAR[0x9280 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_R_PACKETS(x) (*(volatile uint32_t*)(&_MBAR[0x9284 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_R_BC_PKT(x) (*(volatile uint32_t*)(&_MBAR[0x9288 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_R_MC_PKT(x) (*(volatile uint32_t*)(&_MBAR[0x928C + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_R_CRC_ALIGN(x) (*(volatile uint32_t*)(&_MBAR[0x9290 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_R_UNDERSIZE(x) (*(volatile uint32_t*)(&_MBAR[0x9294 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_R_OVERSIZE(x) (*(volatile uint32_t*)(&_MBAR[0x9298 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_R_FRAG(x) (*(volatile uint32_t*)(&_MBAR[0x929C + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_R_JAB(x) (*(volatile uint32_t*)(&_MBAR[0x92A0 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_R_RESVD_0(x) (*(volatile uint32_t*)(&_MBAR[0x92A4 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_R_P64(x) (*(volatile uint32_t*)(&_MBAR[0x92A8 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_R_P65TO127(x) (*(volatile uint32_t*)(&_MBAR[0x92AC + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_R_P128TO255(x) (*(volatile uint32_t*)(&_MBAR[0x92B0 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_R_P256TO511(x) (*(volatile uint32_t*)(&_MBAR[0x92B4 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_R_P512TO1023(x) (*(volatile uint32_t*)(&_MBAR[0x92B8 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_R_P1024TO2047(x) (*(volatile uint32_t*)(&_MBAR[0x92BC + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_R_P_GTE2048(x) (*(volatile uint32_t*)(&_MBAR[0x92C0 + ((x)*0x800)]))
|
||||
#define MCF_FEC_RMON_R_OCTETS(x) (*(volatile uint32_t*)(&_MBAR[0x92C4 + ((x)*0x800)]))
|
||||
#define MCF_FEC_IEEE_R_DROP(x) (*(volatile uint32_t*)(&_MBAR[0x92C8 + ((x)*0x800)]))
|
||||
#define MCF_FEC_IEEE_R_FRAME_OK(x) (*(volatile uint32_t*)(&_MBAR[0x92CC + ((x)*0x800)]))
|
||||
#define MCF_FEC_IEEE_R_CRC(x) (*(volatile uint32_t*)(&_MBAR[0x92D0 + ((x)*0x800)]))
|
||||
#define MCF_FEC_IEEE_R_ALIGN(x) (*(volatile uint32_t*)(&_MBAR[0x92D4 + ((x)*0x800)]))
|
||||
#define MCF_FEC_IEEE_R_MACERR(x) (*(volatile uint32_t*)(&_MBAR[0x92D8 + ((x)*0x800)]))
|
||||
#define MCF_FEC_IEEE_R_FDXFC(x) (*(volatile uint32_t*)(&_MBAR[0x92DC + ((x)*0x800)]))
|
||||
#define MCF_FEC_IEEE_R_OCTETS_OK(x) (*(volatile uint32_t*)(&_MBAR[0x92E0 + ((x)*0x800)]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_EIR */
|
||||
#define MCF_FEC_EIR_RFERR (0x20000)
|
||||
#define MCF_FEC_EIR_XFERR (0x40000)
|
||||
#define MCF_FEC_EIR_XFUN (0x80000)
|
||||
#define MCF_FEC_EIR_RL (0x100000)
|
||||
#define MCF_FEC_EIR_LC (0x200000)
|
||||
#define MCF_FEC_EIR_MII (0x800000)
|
||||
#define MCF_FEC_EIR_TXF (0x8000000)
|
||||
#define MCF_FEC_EIR_GRA (0x10000000)
|
||||
#define MCF_FEC_EIR_BABT (0x20000000)
|
||||
#define MCF_FEC_EIR_BABR (0x40000000)
|
||||
#define MCF_FEC_EIR_HBERR (0x80000000)
|
||||
#define MCF_FEC_EIR_CLEAR_ALL (0xFFFFFFFF)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_EIMR */
|
||||
#define MCF_FEC_EIMR_RFERR (0x20000)
|
||||
#define MCF_FEC_EIMR_XFERR (0x40000)
|
||||
#define MCF_FEC_EIMR_XFUN (0x80000)
|
||||
#define MCF_FEC_EIMR_RL (0x100000)
|
||||
#define MCF_FEC_EIMR_LC (0x200000)
|
||||
#define MCF_FEC_EIMR_MII (0x800000)
|
||||
#define MCF_FEC_EIMR_TXF (0x8000000)
|
||||
#define MCF_FEC_EIMR_GRA (0x10000000)
|
||||
#define MCF_FEC_EIMR_BABT (0x20000000)
|
||||
#define MCF_FEC_EIMR_BABR (0x40000000)
|
||||
#define MCF_FEC_EIMR_HBERR (0x80000000)
|
||||
#define MCF_FEC_EIMR_MASK_ALL (0)
|
||||
#define MCF_FEC_EIMR_UNMASK_ALL (0xFFFFFFFF)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_ECR */
|
||||
#define MCF_FEC_ECR_RESET (0x1)
|
||||
#define MCF_FEC_ECR_ETHER_EN (0x2)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_MMFR */
|
||||
#define MCF_FEC_MMFR_DATA(x) (((x)&0xFFFF)<<0)
|
||||
#define MCF_FEC_MMFR_TA(x) (((x)&0x3)<<0x10)
|
||||
#define MCF_FEC_MMFR_TA_10 (0x20000)
|
||||
#define MCF_FEC_MMFR_RA(x) (((x)&0x1F)<<0x12)
|
||||
#define MCF_FEC_MMFR_PA(x) (((x)&0x1F)<<0x17)
|
||||
#define MCF_FEC_MMFR_OP(x) (((x)&0x3)<<0x1C)
|
||||
#define MCF_FEC_MMFR_OP_READ (0x20000000)
|
||||
#define MCF_FEC_MMFR_OP_WRITE (0x10000000)
|
||||
#define MCF_FEC_MMFR_ST(x) (((x)&0x3)<<0x1E)
|
||||
#define MCF_FEC_MMFR_ST_01 (0x40000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_MSCR */
|
||||
#define MCF_FEC_MSCR_MII_SPEED(x) (((x)&0x3F)<<0x1)
|
||||
#define MCF_FEC_MSCR_DIS_PREAMBLE (0x80)
|
||||
#define MCF_FEC_MSCR_MII_SPEED_133 (0x1B<<0x1)
|
||||
#define MCF_FEC_MSCR_MII_SPEED_120 (0x18<<0x1)
|
||||
#define MCF_FEC_MSCR_MII_SPEED_66 (0xE<<0x1)
|
||||
#define MCF_FEC_MSCR_MII_SPEED_60 (0xC<<0x1)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_MIBC */
|
||||
#define MCF_FEC_MIBC_MIB_IDLE (0x40000000)
|
||||
#define MCF_FEC_MIBC_MIB_DISABLE (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RCR */
|
||||
#define MCF_FEC_RCR_LOOP (0x1)
|
||||
#define MCF_FEC_RCR_DRT (0x2)
|
||||
#define MCF_FEC_RCR_MII_MODE (0x4)
|
||||
#define MCF_FEC_RCR_PROM (0x8)
|
||||
#define MCF_FEC_RCR_BC_REJ (0x10)
|
||||
#define MCF_FEC_RCR_FCE (0x20)
|
||||
#define MCF_FEC_RCR_MAX_FL(x) (((x)&0x7FF)<<0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RHR */
|
||||
#define MCF_FEC_RHR_HASH(x) (((x)&0x3F)<<0x18)
|
||||
#define MCF_FEC_RHR_MULTCAST (0x40000000)
|
||||
#define MCF_FEC_RHR_FCE (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_TCR */
|
||||
#define MCF_FEC_TCR_GTS (0x1)
|
||||
#define MCF_FEC_TCR_HBC (0x2)
|
||||
#define MCF_FEC_TCR_FDEN (0x4)
|
||||
#define MCF_FEC_TCR_TFC_PAUSE (0x8)
|
||||
#define MCF_FEC_TCR_RFC_PAUSE (0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_PALR */
|
||||
#define MCF_FEC_PALR_PADDR1(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_PAHR */
|
||||
#define MCF_FEC_PAHR_TYPE(x) (((x)&0xFFFF)<<0)
|
||||
#define MCF_FEC_PAHR_PADDR2(x) (((x)&0xFFFF)<<0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_OPD */
|
||||
#define MCF_FEC_OPD_PAUSE_DUR(x) (((x)&0xFFFF)<<0)
|
||||
#define MCF_FEC_OPD_OPCODE(x) (((x)&0xFFFF)<<0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IAUR */
|
||||
#define MCF_FEC_IAUR_IADDR1(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IALR */
|
||||
#define MCF_FEC_IALR_IADDR2(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_GAUR */
|
||||
#define MCF_FEC_GAUR_GADDR1(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_GALR */
|
||||
#define MCF_FEC_GALR_GADDR2(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FECTFWR */
|
||||
#define MCF_FEC_FECTFWR_X_WMRK(x) (((x)&0xF)<<0)
|
||||
#define MCF_FEC_FECTFWR_X_WMRK_64 (0)
|
||||
#define MCF_FEC_FECTFWR_X_WMRK_128 (0x1)
|
||||
#define MCF_FEC_FECTFWR_X_WMRK_192 (0x2)
|
||||
#define MCF_FEC_FECTFWR_X_WMRK_256 (0x3)
|
||||
#define MCF_FEC_FECTFWR_X_WMRK_320 (0x4)
|
||||
#define MCF_FEC_FECTFWR_X_WMRK_384 (0x5)
|
||||
#define MCF_FEC_FECTFWR_X_WMRK_448 (0x6)
|
||||
#define MCF_FEC_FECTFWR_X_WMRK_512 (0x7)
|
||||
#define MCF_FEC_FECTFWR_X_WMRK_576 (0x8)
|
||||
#define MCF_FEC_FECTFWR_X_WMRK_640 (0x9)
|
||||
#define MCF_FEC_FECTFWR_X_WMRK_704 (0xA)
|
||||
#define MCF_FEC_FECTFWR_X_WMRK_768 (0xB)
|
||||
#define MCF_FEC_FECTFWR_X_WMRK_832 (0xC)
|
||||
#define MCF_FEC_FECTFWR_X_WMRK_896 (0xD)
|
||||
#define MCF_FEC_FECTFWR_X_WMRK_960 (0xE)
|
||||
#define MCF_FEC_FECTFWR_X_WMRK_1024 (0xF)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FECRFDR */
|
||||
#define MCF_FEC_FECRFDR_FIFO_DATA(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FECRFSR */
|
||||
#define MCF_FEC_FECRFSR_EMT (0x10000)
|
||||
#define MCF_FEC_FECRFSR_ALARM (0x20000)
|
||||
#define MCF_FEC_FECRFSR_FU (0x40000)
|
||||
#define MCF_FEC_FECRFSR_FRMRDY (0x80000)
|
||||
#define MCF_FEC_FECRFSR_OF (0x100000)
|
||||
#define MCF_FEC_FECRFSR_UF (0x200000)
|
||||
#define MCF_FEC_FECRFSR_RXW (0x400000)
|
||||
#define MCF_FEC_FECRFSR_FAE (0x800000)
|
||||
#define MCF_FEC_FECRFSR_FRM(x) (((x)&0xF)<<0x18)
|
||||
#define MCF_FEC_FECRFSR_IP (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FECRFCR */
|
||||
#define MCF_FEC_FECRFCR_COUNTER(x) (((x)&0xFFFF)<<0)
|
||||
#define MCF_FEC_FECRFCR_OF_MSK (0x80000)
|
||||
#define MCF_FEC_FECRFCR_UF_MSK (0x100000)
|
||||
#define MCF_FEC_FECRFCR_RXW_MSK (0x200000)
|
||||
#define MCF_FEC_FECRFCR_FAE_MSK (0x400000)
|
||||
#define MCF_FEC_FECRFCR_IP_MSK (0x800000)
|
||||
#define MCF_FEC_FECRFCR_GR(x) (((x)&0x7)<<0x18)
|
||||
#define MCF_FEC_FECRFCR_FRMEN (0x8000000)
|
||||
#define MCF_FEC_FECRFCR_TIMER (0x10000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FECRLRFP */
|
||||
#define MCF_FEC_FECRLRFP_LRFP(x) (((x)&0x3FF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FECRLWFP */
|
||||
#define MCF_FEC_FECRLWFP_LWFP(x) (((x)&0x3FF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FECRFAR */
|
||||
#define MCF_FEC_FECRFAR_ALARM(x) (((x)&0x3FF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FECRFRP */
|
||||
#define MCF_FEC_FECRFRP_READ(x) (((x)&0x3FF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FECRFWP */
|
||||
#define MCF_FEC_FECRFWP_WRITE(x) (((x)&0x3FF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FECTFDR */
|
||||
#define MCF_FEC_FECTFDR_FIFO_DATA(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FECTFSR */
|
||||
#define MCF_FEC_FECTFSR_EMT (0x10000)
|
||||
#define MCF_FEC_FECTFSR_ALARM (0x20000)
|
||||
#define MCF_FEC_FECTFSR_FU (0x40000)
|
||||
#define MCF_FEC_FECTFSR_FRMRDY (0x80000)
|
||||
#define MCF_FEC_FECTFSR_OF (0x100000)
|
||||
#define MCF_FEC_FECTFSR_UF (0x200000)
|
||||
#define MCF_FEC_FECTFSR_FAE (0x800000)
|
||||
#define MCF_FEC_FECTFSR_FRM(x) (((x)&0xF)<<0x18)
|
||||
#define MCF_FEC_FECTFSR_TXW (0x40000000)
|
||||
#define MCF_FEC_FECTFSR_IP (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FECTFCR */
|
||||
#define MCF_FEC_FECTFCR_RESERVED (0x200000)
|
||||
#define MCF_FEC_FECTFCR_COUNTER(x) (((x)&0xFFFF)<<0|0x200000)
|
||||
#define MCF_FEC_FECTFCR_TXW_MASK (0x240000)
|
||||
#define MCF_FEC_FECTFCR_OF_MSK (0x280000)
|
||||
#define MCF_FEC_FECTFCR_UF_MSK (0x300000)
|
||||
#define MCF_FEC_FECTFCR_FAE_MSK (0x600000)
|
||||
#define MCF_FEC_FECTFCR_IP_MSK (0xA00000)
|
||||
#define MCF_FEC_FECTFCR_GR(x) (((x)&0x7)<<0x18|0x200000)
|
||||
#define MCF_FEC_FECTFCR_FRMEN (0x8200000)
|
||||
#define MCF_FEC_FECTFCR_TIMER (0x10200000)
|
||||
#define MCF_FEC_FECTFCR_WFR (0x20200000)
|
||||
#define MCF_FEC_FECTFCR_WCTL (0x40200000)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FECTLRFP */
|
||||
#define MCF_FEC_FECTLRFP_LRFP(x) (((x)&0x3FF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FECTLWFP */
|
||||
#define MCF_FEC_FECTLWFP_LWFP(x) (((x)&0x3FF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FECTFAR */
|
||||
#define MCF_FEC_FECTFAR_ALARM(x) (((x)&0x3FF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FECTFRP */
|
||||
#define MCF_FEC_FECTFRP_READ(x) (((x)&0x3FF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FECTFWP */
|
||||
#define MCF_FEC_FECTFWP_WRITE(x) (((x)&0x3FF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FECFRST */
|
||||
#define MCF_FEC_FECFRST_RST_CTL (0x1000000)
|
||||
#define MCF_FEC_FECFRST_SW_RST (0x2000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_FECCTCWR */
|
||||
#define MCF_FEC_FECCTCWR_TFCW (0x1000000)
|
||||
#define MCF_FEC_FECCTCWR_CRC (0x2000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_DROP */
|
||||
#define MCF_FEC_RMON_T_DROP_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_PACKETS */
|
||||
#define MCF_FEC_RMON_T_PACKETS_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_BC_PKT */
|
||||
#define MCF_FEC_RMON_T_BC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_MC_PKT */
|
||||
#define MCF_FEC_RMON_T_MC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_CRC_ALIGN */
|
||||
#define MCF_FEC_RMON_T_CRC_ALIGN_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_UNDERSIZE */
|
||||
#define MCF_FEC_RMON_T_UNDERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_OVERSIZE */
|
||||
#define MCF_FEC_RMON_T_OVERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_FRAG */
|
||||
#define MCF_FEC_RMON_T_FRAG_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_JAB */
|
||||
#define MCF_FEC_RMON_T_JAB_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_COL */
|
||||
#define MCF_FEC_RMON_T_COL_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_P64 */
|
||||
#define MCF_FEC_RMON_T_P64_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_P65TO127 */
|
||||
#define MCF_FEC_RMON_T_P65TO127_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_P128TO255 */
|
||||
#define MCF_FEC_RMON_T_P128TO255_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_P256TO511 */
|
||||
#define MCF_FEC_RMON_T_P256TO511_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_P512TO1023 */
|
||||
#define MCF_FEC_RMON_T_P512TO1023_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_P1024TO2047 */
|
||||
#define MCF_FEC_RMON_T_P1024TO2047_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_P_GTE2048 */
|
||||
#define MCF_FEC_RMON_T_P_GTE2048_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_T_OCTETS */
|
||||
#define MCF_FEC_RMON_T_OCTETS_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_T_DROP */
|
||||
#define MCF_FEC_IEEE_T_DROP_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_T_FRAME_OK */
|
||||
#define MCF_FEC_IEEE_T_FRAME_OK_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_T_1COL */
|
||||
#define MCF_FEC_IEEE_T_1COL_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_T_MCOL */
|
||||
#define MCF_FEC_IEEE_T_MCOL_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_T_DEF */
|
||||
#define MCF_FEC_IEEE_T_DEF_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_T_LCOL */
|
||||
#define MCF_FEC_IEEE_T_LCOL_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_T_EXCOL */
|
||||
#define MCF_FEC_IEEE_T_EXCOL_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_T_MACERR */
|
||||
#define MCF_FEC_IEEE_T_MACERR_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_T_CSERR */
|
||||
#define MCF_FEC_IEEE_T_CSERR_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_T_SQE */
|
||||
#define MCF_FEC_IEEE_T_SQE_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_T_FDXFC */
|
||||
#define MCF_FEC_IEEE_T_FDXFC_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_T_OCTETS_OK */
|
||||
#define MCF_FEC_IEEE_T_OCTETS_OK_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_DROP */
|
||||
#define MCF_FEC_RMON_R_DROP_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_PACKETS */
|
||||
#define MCF_FEC_RMON_R_PACKETS_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_BC_PKT */
|
||||
#define MCF_FEC_RMON_R_BC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_MC_PKT */
|
||||
#define MCF_FEC_RMON_R_MC_PKT_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_CRC_ALIGN */
|
||||
#define MCF_FEC_RMON_R_CRC_ALIGN_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_UNDERSIZE */
|
||||
#define MCF_FEC_RMON_R_UNDERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_OVERSIZE */
|
||||
#define MCF_FEC_RMON_R_OVERSIZE_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_FRAG */
|
||||
#define MCF_FEC_RMON_R_FRAG_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_JAB */
|
||||
#define MCF_FEC_RMON_R_JAB_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_RESVD_0 */
|
||||
#define MCF_FEC_RMON_R_RESVD_0_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_P64 */
|
||||
#define MCF_FEC_RMON_R_P64_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_P65TO127 */
|
||||
#define MCF_FEC_RMON_R_P65TO127_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_P128TO255 */
|
||||
#define MCF_FEC_RMON_R_P128TO255_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_P256TO511 */
|
||||
#define MCF_FEC_RMON_R_P256TO511_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_P512TO1023 */
|
||||
#define MCF_FEC_RMON_R_P512TO1023_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_P1024TO2047 */
|
||||
#define MCF_FEC_RMON_R_P1024TO2047_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_P_GTE2048 */
|
||||
#define MCF_FEC_RMON_R_P_GTE2048_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_RMON_R_OCTETS */
|
||||
#define MCF_FEC_RMON_R_OCTETS_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_R_DROP */
|
||||
#define MCF_FEC_IEEE_R_DROP_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_R_FRAME_OK */
|
||||
#define MCF_FEC_IEEE_R_FRAME_OK_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_R_CRC */
|
||||
#define MCF_FEC_IEEE_R_CRC_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_R_ALIGN */
|
||||
#define MCF_FEC_IEEE_R_ALIGN_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_R_MACERR */
|
||||
#define MCF_FEC_IEEE_R_MACERR_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_R_FDXFC */
|
||||
#define MCF_FEC_IEEE_R_FDXFC_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_FEC_IEEE_R_OCTETS_OK */
|
||||
#define MCF_FEC_IEEE_R_OCTETS_OK_Value(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
|
||||
#endif /* __MCF5475_FEC_H__ */
|
||||
@@ -1,543 +0,0 @@
|
||||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.81
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF5475_GPIO_H__
|
||||
#define __MCF5475_GPIO_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* General Purpose I/O (GPIO)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_GPIO_PODR_FBCTL (*(volatile uint8_t *)(&_MBAR[0xA00]))
|
||||
#define MCF_GPIO_PDDR_FBCTL (*(volatile uint8_t *)(&_MBAR[0xA10]))
|
||||
#define MCF_GPIO_PPDSDR_FBCTL (*(volatile uint8_t *)(&_MBAR[0xA20]))
|
||||
#define MCF_GPIO_PCLRR_FBCTL (*(volatile uint8_t *)(&_MBAR[0xA30]))
|
||||
|
||||
#define MCF_GPIO_PODR_FBCS (*(volatile uint8_t *)(&_MBAR[0xA01]))
|
||||
#define MCF_GPIO_PDDR_FBCS (*(volatile uint8_t *)(&_MBAR[0xA11]))
|
||||
#define MCF_GPIO_PPDSDR_FBCS (*(volatile uint8_t *)(&_MBAR[0xA21]))
|
||||
#define MCF_GPIO_PCLRR_FBCS (*(volatile uint8_t *)(&_MBAR[0xA31]))
|
||||
|
||||
#define MCF_GPIO_PODR_DMA (*(volatile uint8_t *)(&_MBAR[0xA02]))
|
||||
#define MCF_GPIO_PDDR_DMA (*(volatile uint8_t *)(&_MBAR[0xA12]))
|
||||
#define MCF_GPIO_PPDSDR_DMA (*(volatile uint8_t *)(&_MBAR[0xA22]))
|
||||
#define MCF_GPIO_PCLRR_DMA (*(volatile uint8_t *)(&_MBAR[0xA32]))
|
||||
|
||||
#define MCF_GPIO_PODR_FEC0H (*(volatile uint8_t *)(&_MBAR[0xA04]))
|
||||
#define MCF_GPIO_PDDR_FEC0H (*(volatile uint8_t *)(&_MBAR[0xA14]))
|
||||
#define MCF_GPIO_PPDSDR_FEC0H (*(volatile uint8_t *)(&_MBAR[0xA24]))
|
||||
#define MCF_GPIO_PCLRR_FEC0H (*(volatile uint8_t *)(&_MBAR[0xA34]))
|
||||
|
||||
#define MCF_GPIO_PODR_FEC0L (*(volatile uint8_t *)(&_MBAR[0xA05]))
|
||||
#define MCF_GPIO_PDDR_FEC0L (*(volatile uint8_t *)(&_MBAR[0xA15]))
|
||||
#define MCF_GPIO_PPDSDR_FEC0L (*(volatile uint8_t *)(&_MBAR[0xA25]))
|
||||
#define MCF_GPIO_PCLRR_FEC0L (*(volatile uint8_t *)(&_MBAR[0xA35]))
|
||||
|
||||
#define MCF_GPIO_PODR_FEC1H (*(volatile uint8_t *)(&_MBAR[0xA06]))
|
||||
#define MCF_GPIO_PDDR_FEC1H (*(volatile uint8_t *)(&_MBAR[0xA16]))
|
||||
#define MCF_GPIO_PPDSDR_FEC1H (*(volatile uint8_t *)(&_MBAR[0xA26]))
|
||||
#define MCF_GPIO_PCLRR_FEC1H (*(volatile uint8_t *)(&_MBAR[0xA36]))
|
||||
|
||||
#define MCF_GPIO_PODR_FEC1L (*(volatile uint8_t *)(&_MBAR[0xA07]))
|
||||
#define MCF_GPIO_PDDR_FEC1L (*(volatile uint8_t *)(&_MBAR[0xA17]))
|
||||
#define MCF_GPIO_PPDSDR_FEC1L (*(volatile uint8_t *)(&_MBAR[0xA27]))
|
||||
#define MCF_GPIO_PCLRR_FEC1L (*(volatile uint8_t *)(&_MBAR[0xA37]))
|
||||
|
||||
#define MCF_GPIO_PODR_FECI2C (*(volatile uint8_t *)(&_MBAR[0xA08]))
|
||||
#define MCF_GPIO_PDDR_FECI2C (*(volatile uint8_t *)(&_MBAR[0xA18]))
|
||||
#define MCF_GPIO_PPDSDR_FECI2C (*(volatile uint8_t *)(&_MBAR[0xA28]))
|
||||
#define MCF_GPIO_PCLRR_FECI2C (*(volatile uint8_t *)(&_MBAR[0xA38]))
|
||||
|
||||
#define MCF_GPIO_PODR_PCIBG (*(volatile uint8_t *)(&_MBAR[0xA09]))
|
||||
#define MCF_GPIO_PDDR_PCIBG (*(volatile uint8_t *)(&_MBAR[0xA19]))
|
||||
#define MCF_GPIO_PPDSDR_PCIBG (*(volatile uint8_t *)(&_MBAR[0xA29]))
|
||||
#define MCF_GPIO_PCLRR_PCIBG (*(volatile uint8_t *)(&_MBAR[0xA39]))
|
||||
|
||||
#define MCF_GPIO_PODR_PCIBR (*(volatile uint8_t *)(&_MBAR[0xA0A]))
|
||||
#define MCF_GPIO_PDDR_PCIBR (*(volatile uint8_t *)(&_MBAR[0xA1A]))
|
||||
#define MCF_GPIO_PPDSDR_PCIBR (*(volatile uint8_t *)(&_MBAR[0xA2A]))
|
||||
#define MCF_GPIO_PCLRR_PCIBR (*(volatile uint8_t *)(&_MBAR[0xA3A]))
|
||||
|
||||
#define MCF_GPIO2_PODR_PSC3PSC (*(volatile uint8_t *)(&_MBAR[0xA0C]))
|
||||
#define MCF_GPIO2_PDDR_PSC3PSC (*(volatile uint8_t *)(&_MBAR[0xA1C]))
|
||||
#define MCF_GPIO2_PPDSDR_PSC3PSC (*(volatile uint8_t *)(&_MBAR[0xA2C]))
|
||||
#define MCF_GPIO2_PCLRR_PSC3PSC (*(volatile uint8_t *)(&_MBAR[0xA3C]))
|
||||
|
||||
#define MCF_GPIO0_PODR_PSC1PSC (*(volatile uint8_t *)(&_MBAR[0xA0D]))
|
||||
#define MCF_GPIO0_PDDR_PSC1PSC (*(volatile uint8_t *)(&_MBAR[0xA1D]))
|
||||
#define MCF_GPIO0_PPDSDR_PSC1PSC (*(volatile uint8_t *)(&_MBAR[0xA2D]))
|
||||
#define MCF_GPIO0_PCLRR_PSC1PSC (*(volatile uint8_t *)(&_MBAR[0xA3D]))
|
||||
|
||||
#define MCF_GPIO_PODR_DSPI (*(volatile uint8_t *)(&_MBAR[0xA0E]))
|
||||
#define MCF_GPIO_PDDR_DSPI (*(volatile uint8_t *)(&_MBAR[0xA1E]))
|
||||
#define MCF_GPIO_PPDSDR_DSPI (*(volatile uint8_t *)(&_MBAR[0xA2E]))
|
||||
#define MCF_GPIO_PCLRR_DSPI (*(volatile uint8_t *)(&_MBAR[0xA3E]))
|
||||
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PODR_FBCTL */
|
||||
#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL0 (0x1)
|
||||
#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL1 (0x2)
|
||||
#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL2 (0x4)
|
||||
#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL3 (0x8)
|
||||
#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL4 (0x10)
|
||||
#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL5 (0x20)
|
||||
#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL6 (0x40)
|
||||
#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PDDR_FBCTL */
|
||||
#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL0 (0x1)
|
||||
#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL1 (0x2)
|
||||
#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL2 (0x4)
|
||||
#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL3 (0x8)
|
||||
#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL4 (0x10)
|
||||
#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL5 (0x20)
|
||||
#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL6 (0x40)
|
||||
#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCTL */
|
||||
#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL0 (0x1)
|
||||
#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL1 (0x2)
|
||||
#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL2 (0x4)
|
||||
#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL3 (0x8)
|
||||
#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL4 (0x10)
|
||||
#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL5 (0x20)
|
||||
#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL6 (0x40)
|
||||
#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCTL */
|
||||
#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL0 (0x1)
|
||||
#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL1 (0x2)
|
||||
#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL2 (0x4)
|
||||
#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL3 (0x8)
|
||||
#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL4 (0x10)
|
||||
#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL5 (0x20)
|
||||
#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL6 (0x40)
|
||||
#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PODR_FBCS */
|
||||
#define MCF_GPIO_PODR_FBCS_PODR_FBCS1 (0x2)
|
||||
#define MCF_GPIO_PODR_FBCS_PODR_FBCS2 (0x4)
|
||||
#define MCF_GPIO_PODR_FBCS_PODR_FBCS3 (0x8)
|
||||
#define MCF_GPIO_PODR_FBCS_PODR_FBCS4 (0x10)
|
||||
#define MCF_GPIO_PODR_FBCS_PODR_FBCS5 (0x20)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PDDR_FBCS */
|
||||
#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS1 (0x2)
|
||||
#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS2 (0x4)
|
||||
#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS3 (0x8)
|
||||
#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS4 (0x10)
|
||||
#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS5 (0x20)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCS */
|
||||
#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS1 (0x2)
|
||||
#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS2 (0x4)
|
||||
#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS3 (0x8)
|
||||
#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS4 (0x10)
|
||||
#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS5 (0x20)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCS */
|
||||
#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS1 (0x2)
|
||||
#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS2 (0x4)
|
||||
#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS3 (0x8)
|
||||
#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS4 (0x10)
|
||||
#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS5 (0x20)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PODR_DMA */
|
||||
#define MCF_GPIO_PODR_DMA_PODR_DMA0 (0x1)
|
||||
#define MCF_GPIO_PODR_DMA_PODR_DMA1 (0x2)
|
||||
#define MCF_GPIO_PODR_DMA_PODR_DMA2 (0x4)
|
||||
#define MCF_GPIO_PODR_DMA_PODR_DMA3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PDDR_DMA */
|
||||
#define MCF_GPIO_PDDR_DMA_PDDR_DMA0 (0x1)
|
||||
#define MCF_GPIO_PDDR_DMA_PDDR_DMA1 (0x2)
|
||||
#define MCF_GPIO_PDDR_DMA_PDDR_DMA2 (0x4)
|
||||
#define MCF_GPIO_PDDR_DMA_PDDR_DMA3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PPDSDR_DMA */
|
||||
#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA0 (0x1)
|
||||
#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA1 (0x2)
|
||||
#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA2 (0x4)
|
||||
#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PCLRR_DMA */
|
||||
#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA0 (0x1)
|
||||
#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA1 (0x2)
|
||||
#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA2 (0x4)
|
||||
#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PODR_FEC0H */
|
||||
#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H0 (0x1)
|
||||
#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H1 (0x2)
|
||||
#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H2 (0x4)
|
||||
#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H3 (0x8)
|
||||
#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H4 (0x10)
|
||||
#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H5 (0x20)
|
||||
#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H6 (0x40)
|
||||
#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0H */
|
||||
#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H0 (0x1)
|
||||
#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H1 (0x2)
|
||||
#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H2 (0x4)
|
||||
#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H3 (0x8)
|
||||
#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H4 (0x10)
|
||||
#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H5 (0x20)
|
||||
#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H6 (0x40)
|
||||
#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0H */
|
||||
#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H0 (0x1)
|
||||
#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H1 (0x2)
|
||||
#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H2 (0x4)
|
||||
#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H3 (0x8)
|
||||
#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H4 (0x10)
|
||||
#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H5 (0x20)
|
||||
#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H6 (0x40)
|
||||
#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0H */
|
||||
#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H0 (0x1)
|
||||
#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H1 (0x2)
|
||||
#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H2 (0x4)
|
||||
#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H3 (0x8)
|
||||
#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H4 (0x10)
|
||||
#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H5 (0x20)
|
||||
#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H6 (0x40)
|
||||
#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PODR_FEC0L */
|
||||
#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L0 (0x1)
|
||||
#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L1 (0x2)
|
||||
#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L2 (0x4)
|
||||
#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L3 (0x8)
|
||||
#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L4 (0x10)
|
||||
#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L5 (0x20)
|
||||
#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L6 (0x40)
|
||||
#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0L */
|
||||
#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L0 (0x1)
|
||||
#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L1 (0x2)
|
||||
#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L2 (0x4)
|
||||
#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L3 (0x8)
|
||||
#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L4 (0x10)
|
||||
#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L5 (0x20)
|
||||
#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L6 (0x40)
|
||||
#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0L */
|
||||
#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L0 (0x1)
|
||||
#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L1 (0x2)
|
||||
#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L2 (0x4)
|
||||
#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L3 (0x8)
|
||||
#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L4 (0x10)
|
||||
#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L5 (0x20)
|
||||
#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L6 (0x40)
|
||||
#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0L */
|
||||
#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L0 (0x1)
|
||||
#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L1 (0x2)
|
||||
#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L2 (0x4)
|
||||
#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L3 (0x8)
|
||||
#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L4 (0x10)
|
||||
#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L5 (0x20)
|
||||
#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L6 (0x40)
|
||||
#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PODR_FEC1H */
|
||||
#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H0 (0x1)
|
||||
#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H1 (0x2)
|
||||
#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H2 (0x4)
|
||||
#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H3 (0x8)
|
||||
#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H4 (0x10)
|
||||
#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H5 (0x20)
|
||||
#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H6 (0x40)
|
||||
#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1H */
|
||||
#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H0 (0x1)
|
||||
#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H1 (0x2)
|
||||
#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H2 (0x4)
|
||||
#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H3 (0x8)
|
||||
#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H4 (0x10)
|
||||
#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H5 (0x20)
|
||||
#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H6 (0x40)
|
||||
#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1H */
|
||||
#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H0 (0x1)
|
||||
#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H1 (0x2)
|
||||
#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H2 (0x4)
|
||||
#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H3 (0x8)
|
||||
#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H4 (0x10)
|
||||
#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H5 (0x20)
|
||||
#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H6 (0x40)
|
||||
#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1H */
|
||||
#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H0 (0x1)
|
||||
#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H1 (0x2)
|
||||
#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H2 (0x4)
|
||||
#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H3 (0x8)
|
||||
#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H4 (0x10)
|
||||
#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H5 (0x20)
|
||||
#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H6 (0x40)
|
||||
#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PODR_FEC1L */
|
||||
#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L0 (0x1)
|
||||
#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L1 (0x2)
|
||||
#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L2 (0x4)
|
||||
#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L3 (0x8)
|
||||
#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L4 (0x10)
|
||||
#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L5 (0x20)
|
||||
#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L6 (0x40)
|
||||
#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1L */
|
||||
#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L0 (0x1)
|
||||
#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L1 (0x2)
|
||||
#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L2 (0x4)
|
||||
#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L3 (0x8)
|
||||
#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4 (0x10)
|
||||
#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L5 (0x20)
|
||||
#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L6 (0x40)
|
||||
#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1L */
|
||||
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L0 (0x1)
|
||||
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L1 (0x2)
|
||||
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L2 (0x4)
|
||||
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L3 (0x8)
|
||||
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L4 (0x10)
|
||||
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L5 (0x20)
|
||||
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L6 (0x40)
|
||||
#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1L */
|
||||
#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L0 (0x1)
|
||||
#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L1 (0x2)
|
||||
#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L2 (0x4)
|
||||
#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L3 (0x8)
|
||||
#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L4 (0x10)
|
||||
#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L5 (0x20)
|
||||
#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L6 (0x40)
|
||||
#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L7 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PODR_FECI2C */
|
||||
#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C0 (0x1)
|
||||
#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C1 (0x2)
|
||||
#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C2 (0x4)
|
||||
#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PDDR_FECI2C */
|
||||
#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0 (0x1)
|
||||
#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1 (0x2)
|
||||
#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C2 (0x4)
|
||||
#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECI2C */
|
||||
#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C0 (0x1)
|
||||
#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C1 (0x2)
|
||||
#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C2 (0x4)
|
||||
#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PCLRR_FECI2C */
|
||||
#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C0 (0x1)
|
||||
#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C1 (0x2)
|
||||
#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C2 (0x4)
|
||||
#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PODR_PCIBG */
|
||||
#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG0 (0x1)
|
||||
#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG1 (0x2)
|
||||
#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG2 (0x4)
|
||||
#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG3 (0x8)
|
||||
#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG4 (0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBG */
|
||||
#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG0 (0x1)
|
||||
#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG1 (0x2)
|
||||
#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG2 (0x4)
|
||||
#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG3 (0x8)
|
||||
#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG4 (0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBG */
|
||||
#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG0 (0x1)
|
||||
#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG1 (0x2)
|
||||
#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG2 (0x4)
|
||||
#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG3 (0x8)
|
||||
#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG4 (0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBG */
|
||||
#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG0 (0x1)
|
||||
#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG1 (0x2)
|
||||
#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG2 (0x4)
|
||||
#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG3 (0x8)
|
||||
#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG4 (0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PODR_PCIBR */
|
||||
#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR0 (0x1)
|
||||
#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR1 (0x2)
|
||||
#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR2 (0x4)
|
||||
#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR3 (0x8)
|
||||
#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR4 (0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBR */
|
||||
#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR0 (0x1)
|
||||
#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR1 (0x2)
|
||||
#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR2 (0x4)
|
||||
#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR3 (0x8)
|
||||
#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR4 (0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBR */
|
||||
#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR0 (0x1)
|
||||
#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR1 (0x2)
|
||||
#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR2 (0x4)
|
||||
#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR3 (0x8)
|
||||
#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR4 (0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBR */
|
||||
#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR0 (0x1)
|
||||
#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR1 (0x2)
|
||||
#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR2 (0x4)
|
||||
#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR3 (0x8)
|
||||
#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR4 (0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PODR_PSC3PSC */
|
||||
#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC20 (0x1)
|
||||
#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC21 (0x2)
|
||||
#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC22 (0x4)
|
||||
#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC23 (0x8)
|
||||
#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC24 (0x10)
|
||||
#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC25 (0x20)
|
||||
#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC26 (0x40)
|
||||
#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC27 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PDDR_PSC3PSC */
|
||||
#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC20 (0x1)
|
||||
#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC21 (0x2)
|
||||
#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC22 (0x4)
|
||||
#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC23 (0x8)
|
||||
#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC24 (0x10)
|
||||
#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC25 (0x20)
|
||||
#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC26 (0x40)
|
||||
#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC27 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC3PSC */
|
||||
#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC20 (0x1)
|
||||
#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC21 (0x2)
|
||||
#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC22 (0x4)
|
||||
#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC23 (0x8)
|
||||
#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC24 (0x10)
|
||||
#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC25 (0x20)
|
||||
#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC26 (0x40)
|
||||
#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC27 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC3PSC */
|
||||
#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC20 (0x1)
|
||||
#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC21 (0x2)
|
||||
#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC22 (0x4)
|
||||
#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC23 (0x8)
|
||||
#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC24 (0x10)
|
||||
#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC25 (0x20)
|
||||
#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC26 (0x40)
|
||||
#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC27 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PODR_PSC1PSC */
|
||||
#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC00 (0x1)
|
||||
#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC01 (0x2)
|
||||
#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC02 (0x4)
|
||||
#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC03 (0x8)
|
||||
#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC04 (0x10)
|
||||
#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC05 (0x20)
|
||||
#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC06 (0x40)
|
||||
#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC07 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PDDR_PSC1PSC */
|
||||
#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC00 (0x1)
|
||||
#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC01 (0x2)
|
||||
#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC02 (0x4)
|
||||
#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC03 (0x8)
|
||||
#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC04 (0x10)
|
||||
#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC05 (0x20)
|
||||
#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC06 (0x40)
|
||||
#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC07 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC1PSC */
|
||||
#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC00 (0x1)
|
||||
#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC01 (0x2)
|
||||
#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC02 (0x4)
|
||||
#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC03 (0x8)
|
||||
#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC04 (0x10)
|
||||
#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC05 (0x20)
|
||||
#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC06 (0x40)
|
||||
#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC07 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC1PSC */
|
||||
#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC00 (0x1)
|
||||
#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC01 (0x2)
|
||||
#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC02 (0x4)
|
||||
#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC03 (0x8)
|
||||
#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC04 (0x10)
|
||||
#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC05 (0x20)
|
||||
#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC06 (0x40)
|
||||
#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC07 (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PODR_DSPI */
|
||||
#define MCF_GPIO_PODR_DSPI_PODR_DSPI0 (0x1)
|
||||
#define MCF_GPIO_PODR_DSPI_PODR_DSPI1 (0x2)
|
||||
#define MCF_GPIO_PODR_DSPI_PODR_DSPI2 (0x4)
|
||||
#define MCF_GPIO_PODR_DSPI_PODR_DSPI3 (0x8)
|
||||
#define MCF_GPIO_PODR_DSPI_PODR_DSPI4 (0x10)
|
||||
#define MCF_GPIO_PODR_DSPI_PODR_DSPI5 (0x20)
|
||||
#define MCF_GPIO_PODR_DSPI_PODR_DSPI6 (0x40)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PDDR_DSPI */
|
||||
#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI0 (0x1)
|
||||
#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI1 (0x2)
|
||||
#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI2 (0x4)
|
||||
#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI3 (0x8)
|
||||
#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI4 (0x10)
|
||||
#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI5 (0x20)
|
||||
#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI6 (0x40)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PPDSDR_DSPI */
|
||||
#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI0 (0x1)
|
||||
#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI1 (0x2)
|
||||
#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI2 (0x4)
|
||||
#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI3 (0x8)
|
||||
#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI4 (0x10)
|
||||
#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI5 (0x20)
|
||||
#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI6 (0x40)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPIO_PCLRR_DSPI */
|
||||
#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI0 (0x1)
|
||||
#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI1 (0x2)
|
||||
#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI2 (0x4)
|
||||
#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI3 (0x8)
|
||||
#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI4 (0x10)
|
||||
#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI5 (0x20)
|
||||
#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI6 (0x40)
|
||||
|
||||
|
||||
#endif /* __MCF5475_GPIO_H__ */
|
||||
@@ -1,100 +0,0 @@
|
||||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.81
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF5475_GPT_H__
|
||||
#define __MCF5475_GPT_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* General Purpose Timers (GPT)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_GPT0_GMS (*(volatile uint32_t*)(&_MBAR[0x800]))
|
||||
#define MCF_GPT0_GCIR (*(volatile uint32_t*)(&_MBAR[0x804]))
|
||||
#define MCF_GPT0_GPWM (*(volatile uint32_t*)(&_MBAR[0x808]))
|
||||
#define MCF_GPT0_GSR (*(volatile uint32_t*)(&_MBAR[0x80C]))
|
||||
|
||||
#define MCF_GPT1_GMS (*(volatile uint32_t*)(&_MBAR[0x810]))
|
||||
#define MCF_GPT1_GCIR (*(volatile uint32_t*)(&_MBAR[0x814]))
|
||||
#define MCF_GPT1_GPWM (*(volatile uint32_t*)(&_MBAR[0x818]))
|
||||
#define MCF_GPT1_GSR (*(volatile uint32_t*)(&_MBAR[0x81C]))
|
||||
|
||||
#define MCF_GPT2_GMS (*(volatile uint32_t*)(&_MBAR[0x820]))
|
||||
#define MCF_GPT2_GCIR (*(volatile uint32_t*)(&_MBAR[0x824]))
|
||||
#define MCF_GPT2_GPWM (*(volatile uint32_t*)(&_MBAR[0x828]))
|
||||
#define MCF_GPT2_GSR (*(volatile uint32_t*)(&_MBAR[0x82C]))
|
||||
|
||||
#define MCF_GPT3_GMS (*(volatile uint32_t*)(&_MBAR[0x830]))
|
||||
#define MCF_GPT3_GCIR (*(volatile uint32_t*)(&_MBAR[0x834]))
|
||||
#define MCF_GPT3_GPWM (*(volatile uint32_t*)(&_MBAR[0x838]))
|
||||
#define MCF_GPT3_GSR (*(volatile uint32_t*)(&_MBAR[0x83C]))
|
||||
|
||||
#define MCF_GPT_GMS(x) (*(volatile uint32_t*)(&_MBAR[0x800 + ((x)*0x10)]))
|
||||
#define MCF_GPT_GCIR(x) (*(volatile uint32_t*)(&_MBAR[0x804 + ((x)*0x10)]))
|
||||
#define MCF_GPT_GPWM(x) (*(volatile uint32_t*)(&_MBAR[0x808 + ((x)*0x10)]))
|
||||
#define MCF_GPT_GSR(x) (*(volatile uint32_t*)(&_MBAR[0x80C + ((x)*0x10)]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_GPT_GMS */
|
||||
#define MCF_GPT_GMS_TMS(x) (((x)&0x7)<<0)
|
||||
#define MCF_GPT_GMS_TMS_DISABLE (0)
|
||||
#define MCF_GPT_GMS_TMS_INCAPT (0x1)
|
||||
#define MCF_GPT_GMS_TMS_OUTCAPT (0x2)
|
||||
#define MCF_GPT_GMS_TMS_PWM (0x3)
|
||||
#define MCF_GPT_GMS_TMS_GPIO (0x4)
|
||||
#define MCF_GPT_GMS_GPIO(x) (((x)&0x3)<<0x4)
|
||||
#define MCF_GPT_GMS_GPIO_INPUT (0)
|
||||
#define MCF_GPT_GMS_GPIO_OUTLO (0x20)
|
||||
#define MCF_GPT_GMS_GPIO_OUTHI (0x30)
|
||||
#define MCF_GPT_GMS_IEN (0x100)
|
||||
#define MCF_GPT_GMS_OD (0x200)
|
||||
#define MCF_GPT_GMS_SC (0x400)
|
||||
#define MCF_GPT_GMS_CE (0x1000)
|
||||
#define MCF_GPT_GMS_WDEN (0x8000)
|
||||
#define MCF_GPT_GMS_ICT(x) (((x)&0x3)<<0x10)
|
||||
#define MCF_GPT_GMS_ICT_ANY (0)
|
||||
#define MCF_GPT_GMS_ICT_RISE (0x10000)
|
||||
#define MCF_GPT_GMS_ICT_FALL (0x20000)
|
||||
#define MCF_GPT_GMS_ICT_PULSE (0x30000)
|
||||
#define MCF_GPT_GMS_OCT(x) (((x)&0x3)<<0x14)
|
||||
#define MCF_GPT_GMS_OCT_FRCLOW (0)
|
||||
#define MCF_GPT_GMS_OCT_PULSEHI (0x100000)
|
||||
#define MCF_GPT_GMS_OCT_PULSELO (0x200000)
|
||||
#define MCF_GPT_GMS_OCT_TOGGLE (0x300000)
|
||||
#define MCF_GPT_GMS_OCPW(x) (((x)&0xFF)<<0x18)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPT_GCIR */
|
||||
#define MCF_GPT_GCIR_CNT(x) (((x)&0xFFFF)<<0)
|
||||
#define MCF_GPT_GCIR_PRE(x) (((x)&0xFFFF)<<0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPT_GPWM */
|
||||
#define MCF_GPT_GPWM_LOAD (0x1)
|
||||
#define MCF_GPT_GPWM_PWMOP (0x100)
|
||||
#define MCF_GPT_GPWM_WIDTH(x) (((x)&0xFFFF)<<0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_GPT_GSR */
|
||||
#define MCF_GPT_GSR_CAPT (0x1)
|
||||
#define MCF_GPT_GSR_COMP (0x2)
|
||||
#define MCF_GPT_GSR_PWMP (0x4)
|
||||
#define MCF_GPT_GSR_TEXP (0x8)
|
||||
#define MCF_GPT_GSR_PIN (0x100)
|
||||
#define MCF_GPT_GSR_OVF(x) (((x)&0x7)<<0xC)
|
||||
#define MCF_GPT_GSR_CAPTURE(x) (((x)&0xFFFF)<<0x10)
|
||||
|
||||
|
||||
#endif /* __MCF5475_GPT_H__ */
|
||||
@@ -1,69 +0,0 @@
|
||||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.81
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF5475_I2C_H__
|
||||
#define __MCF5475_I2C_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* I2C Module (I2C)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_I2C_I2ADR (*(volatile uint8_t *)(&_MBAR[0x8F00]))
|
||||
#define MCF_I2C_I2FDR (*(volatile uint8_t *)(&_MBAR[0x8F04]))
|
||||
#define MCF_I2C_I2CR (*(volatile uint8_t *)(&_MBAR[0x8F08]))
|
||||
#define MCF_I2C_I2SR (*(volatile uint8_t *)(&_MBAR[0x8F0C]))
|
||||
#define MCF_I2C_I2DR (*(volatile uint8_t *)(&_MBAR[0x8F10]))
|
||||
#define MCF_I2C_I2ICR (*(volatile uint8_t *)(&_MBAR[0x8F20]))
|
||||
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_I2C_I2ADR */
|
||||
#define MCF_I2C_I2ADR_ADR(x) (((x)&0x7F)<<0x1)
|
||||
|
||||
/* Bit definitions and macros for MCF_I2C_I2FDR */
|
||||
#define MCF_I2C_I2FDR_IC(x) (((x)&0x3F)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_I2C_I2CR */
|
||||
#define MCF_I2C_I2CR_RSTA (0x4)
|
||||
#define MCF_I2C_I2CR_TXAK (0x8)
|
||||
#define MCF_I2C_I2CR_MTX (0x10)
|
||||
#define MCF_I2C_I2CR_MSTA (0x20)
|
||||
#define MCF_I2C_I2CR_IIEN (0x40)
|
||||
#define MCF_I2C_I2CR_IEN (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_I2C_I2SR */
|
||||
#define MCF_I2C_I2SR_RXAK (0x1)
|
||||
#define MCF_I2C_I2SR_IIF (0x2)
|
||||
#define MCF_I2C_I2SR_SRW (0x4)
|
||||
#define MCF_I2C_I2SR_IAL (0x10)
|
||||
#define MCF_I2C_I2SR_IBB (0x20)
|
||||
#define MCF_I2C_I2SR_IAAS (0x40)
|
||||
#define MCF_I2C_I2SR_ICF (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_I2C_I2DR */
|
||||
#define MCF_I2C_I2DR_DATA(x) (((x)&0xFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_I2C_I2ICR */
|
||||
#define MCF_I2C_I2ICR_IE (0x1)
|
||||
#define MCF_I2C_I2ICR_RE (0x2)
|
||||
#define MCF_I2C_I2ICR_TE (0x4)
|
||||
#define MCF_I2C_I2ICR_BNBE (0x8)
|
||||
|
||||
|
||||
#endif /* __MCF5475_I2C_H__ */
|
||||
@@ -1,330 +0,0 @@
|
||||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.81
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF5475_INTC_H__
|
||||
#define __MCF5475_INTC_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Interrupt Controller (INTC)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_INTC_IPRH (*(volatile uint32_t*)(&_MBAR[0x700]))
|
||||
#define MCF_INTC_IPRL (*(volatile uint32_t*)(&_MBAR[0x704]))
|
||||
#define MCF_INTC_IMRH (*(volatile uint32_t*)(&_MBAR[0x708]))
|
||||
#define MCF_INTC_IMRL (*(volatile uint32_t*)(&_MBAR[0x70C]))
|
||||
#define MCF_INTC_INTFRCH (*(volatile uint32_t*)(&_MBAR[0x710]))
|
||||
#define MCF_INTC_INTFRCL (*(volatile uint32_t*)(&_MBAR[0x714]))
|
||||
#define MCF_INTC_IRLR (*(volatile uint8_t *)(&_MBAR[0x718]))
|
||||
#define MCF_INTC_IACKLPR (*(volatile uint8_t *)(&_MBAR[0x719]))
|
||||
#define MCF_INTC_ICR01 (*(volatile uint8_t *)(&_MBAR[0x741]))
|
||||
#define MCF_INTC_ICR02 (*(volatile uint8_t *)(&_MBAR[0x742]))
|
||||
#define MCF_INTC_ICR03 (*(volatile uint8_t *)(&_MBAR[0x743]))
|
||||
#define MCF_INTC_ICR04 (*(volatile uint8_t *)(&_MBAR[0x744]))
|
||||
#define MCF_INTC_ICR05 (*(volatile uint8_t *)(&_MBAR[0x745]))
|
||||
#define MCF_INTC_ICR06 (*(volatile uint8_t *)(&_MBAR[0x746]))
|
||||
#define MCF_INTC_ICR07 (*(volatile uint8_t *)(&_MBAR[0x747]))
|
||||
#define MCF_INTC_ICR08 (*(volatile uint8_t *)(&_MBAR[0x748]))
|
||||
#define MCF_INTC_ICR09 (*(volatile uint8_t *)(&_MBAR[0x749]))
|
||||
#define MCF_INTC_ICR10 (*(volatile uint8_t *)(&_MBAR[0x74A]))
|
||||
#define MCF_INTC_ICR11 (*(volatile uint8_t *)(&_MBAR[0x74B]))
|
||||
#define MCF_INTC_ICR12 (*(volatile uint8_t *)(&_MBAR[0x74C]))
|
||||
#define MCF_INTC_ICR13 (*(volatile uint8_t *)(&_MBAR[0x74D]))
|
||||
#define MCF_INTC_ICR14 (*(volatile uint8_t *)(&_MBAR[0x74E]))
|
||||
#define MCF_INTC_ICR15 (*(volatile uint8_t *)(&_MBAR[0x74F]))
|
||||
#define MCF_INTC_ICR16 (*(volatile uint8_t *)(&_MBAR[0x750]))
|
||||
#define MCF_INTC_ICR17 (*(volatile uint8_t *)(&_MBAR[0x751]))
|
||||
#define MCF_INTC_ICR18 (*(volatile uint8_t *)(&_MBAR[0x752]))
|
||||
#define MCF_INTC_ICR19 (*(volatile uint8_t *)(&_MBAR[0x753]))
|
||||
#define MCF_INTC_ICR20 (*(volatile uint8_t *)(&_MBAR[0x754]))
|
||||
#define MCF_INTC_ICR21 (*(volatile uint8_t *)(&_MBAR[0x755]))
|
||||
#define MCF_INTC_ICR22 (*(volatile uint8_t *)(&_MBAR[0x756]))
|
||||
#define MCF_INTC_ICR23 (*(volatile uint8_t *)(&_MBAR[0x757]))
|
||||
#define MCF_INTC_ICR24 (*(volatile uint8_t *)(&_MBAR[0x758]))
|
||||
#define MCF_INTC_ICR25 (*(volatile uint8_t *)(&_MBAR[0x759]))
|
||||
#define MCF_INTC_ICR26 (*(volatile uint8_t *)(&_MBAR[0x75A]))
|
||||
#define MCF_INTC_ICR27 (*(volatile uint8_t *)(&_MBAR[0x75B]))
|
||||
#define MCF_INTC_ICR28 (*(volatile uint8_t *)(&_MBAR[0x75C]))
|
||||
#define MCF_INTC_ICR29 (*(volatile uint8_t *)(&_MBAR[0x75D]))
|
||||
#define MCF_INTC_ICR30 (*(volatile uint8_t *)(&_MBAR[0x75E]))
|
||||
#define MCF_INTC_ICR31 (*(volatile uint8_t *)(&_MBAR[0x75F]))
|
||||
#define MCF_INTC_ICR32 (*(volatile uint8_t *)(&_MBAR[0x760]))
|
||||
#define MCF_INTC_ICR33 (*(volatile uint8_t *)(&_MBAR[0x761]))
|
||||
#define MCF_INTC_ICR34 (*(volatile uint8_t *)(&_MBAR[0x762]))
|
||||
#define MCF_INTC_ICR35 (*(volatile uint8_t *)(&_MBAR[0x763]))
|
||||
#define MCF_INTC_ICR36 (*(volatile uint8_t *)(&_MBAR[0x764]))
|
||||
#define MCF_INTC_ICR37 (*(volatile uint8_t *)(&_MBAR[0x765]))
|
||||
#define MCF_INTC_ICR38 (*(volatile uint8_t *)(&_MBAR[0x766]))
|
||||
#define MCF_INTC_ICR39 (*(volatile uint8_t *)(&_MBAR[0x767]))
|
||||
#define MCF_INTC_ICR40 (*(volatile uint8_t *)(&_MBAR[0x768]))
|
||||
#define MCF_INTC_ICR41 (*(volatile uint8_t *)(&_MBAR[0x769]))
|
||||
#define MCF_INTC_ICR42 (*(volatile uint8_t *)(&_MBAR[0x76A]))
|
||||
#define MCF_INTC_ICR43 (*(volatile uint8_t *)(&_MBAR[0x76B]))
|
||||
#define MCF_INTC_ICR44 (*(volatile uint8_t *)(&_MBAR[0x76C]))
|
||||
#define MCF_INTC_ICR45 (*(volatile uint8_t *)(&_MBAR[0x76D]))
|
||||
#define MCF_INTC_ICR46 (*(volatile uint8_t *)(&_MBAR[0x76E]))
|
||||
#define MCF_INTC_ICR47 (*(volatile uint8_t *)(&_MBAR[0x76F]))
|
||||
#define MCF_INTC_ICR48 (*(volatile uint8_t *)(&_MBAR[0x770]))
|
||||
#define MCF_INTC_ICR49 (*(volatile uint8_t *)(&_MBAR[0x771]))
|
||||
#define MCF_INTC_ICR50 (*(volatile uint8_t *)(&_MBAR[0x772]))
|
||||
#define MCF_INTC_ICR51 (*(volatile uint8_t *)(&_MBAR[0x773]))
|
||||
#define MCF_INTC_ICR52 (*(volatile uint8_t *)(&_MBAR[0x774]))
|
||||
#define MCF_INTC_ICR53 (*(volatile uint8_t *)(&_MBAR[0x775]))
|
||||
#define MCF_INTC_ICR54 (*(volatile uint8_t *)(&_MBAR[0x776]))
|
||||
#define MCF_INTC_ICR55 (*(volatile uint8_t *)(&_MBAR[0x777]))
|
||||
#define MCF_INTC_ICR56 (*(volatile uint8_t *)(&_MBAR[0x778]))
|
||||
#define MCF_INTC_ICR57 (*(volatile uint8_t *)(&_MBAR[0x779]))
|
||||
#define MCF_INTC_ICR58 (*(volatile uint8_t *)(&_MBAR[0x77A]))
|
||||
#define MCF_INTC_ICR59 (*(volatile uint8_t *)(&_MBAR[0x77B]))
|
||||
#define MCF_INTC_ICR60 (*(volatile uint8_t *)(&_MBAR[0x77C]))
|
||||
#define MCF_INTC_ICR61 (*(volatile uint8_t *)(&_MBAR[0x77D]))
|
||||
#define MCF_INTC_ICR62 (*(volatile uint8_t *)(&_MBAR[0x77E]))
|
||||
#define MCF_INTC_ICR63 (*(volatile uint8_t *)(&_MBAR[0x77F]))
|
||||
#define MCF_INTC_SWIACK (*(volatile uint8_t *)(&_MBAR[0x7E0]))
|
||||
#define MCF_INTC_L1IACK (*(volatile uint8_t *)(&_MBAR[0x7E4]))
|
||||
#define MCF_INTC_L2IACK (*(volatile uint8_t *)(&_MBAR[0x7E8]))
|
||||
#define MCF_INTC_L3IACK (*(volatile uint8_t *)(&_MBAR[0x7EC]))
|
||||
#define MCF_INTC_L4IACK (*(volatile uint8_t *)(&_MBAR[0x7F0]))
|
||||
#define MCF_INTC_L5IACK (*(volatile uint8_t *)(&_MBAR[0x7F4]))
|
||||
#define MCF_INTC_L6IACK (*(volatile uint8_t *)(&_MBAR[0x7F8]))
|
||||
#define MCF_INTC_L7IACK (*(volatile uint8_t *)(&_MBAR[0x7FC]))
|
||||
#define MCF_INTC_ICR(x) (*(volatile uint8_t *)(&_MBAR[0x741 + ((x-1)*0x1)]))
|
||||
#define MCF_INTC_LIACK(x) (*(volatile uint8_t *)(&_MBAR[0x7E4 + ((x-1)*0x4)]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC_IPRH */
|
||||
#define MCF_INTC_IPRH_INT32 (0x1)
|
||||
#define MCF_INTC_IPRH_INT33 (0x2)
|
||||
#define MCF_INTC_IPRH_INT34 (0x4)
|
||||
#define MCF_INTC_IPRH_INT35 (0x8)
|
||||
#define MCF_INTC_IPRH_INT36 (0x10)
|
||||
#define MCF_INTC_IPRH_INT37 (0x20)
|
||||
#define MCF_INTC_IPRH_INT38 (0x40)
|
||||
#define MCF_INTC_IPRH_INT39 (0x80)
|
||||
#define MCF_INTC_IPRH_INT40 (0x100)
|
||||
#define MCF_INTC_IPRH_INT41 (0x200)
|
||||
#define MCF_INTC_IPRH_INT42 (0x400)
|
||||
#define MCF_INTC_IPRH_INT43 (0x800)
|
||||
#define MCF_INTC_IPRH_INT44 (0x1000)
|
||||
#define MCF_INTC_IPRH_INT45 (0x2000)
|
||||
#define MCF_INTC_IPRH_INT46 (0x4000)
|
||||
#define MCF_INTC_IPRH_INT47 (0x8000)
|
||||
#define MCF_INTC_IPRH_INT48 (0x10000)
|
||||
#define MCF_INTC_IPRH_INT49 (0x20000)
|
||||
#define MCF_INTC_IPRH_INT50 (0x40000)
|
||||
#define MCF_INTC_IPRH_INT51 (0x80000)
|
||||
#define MCF_INTC_IPRH_INT52 (0x100000)
|
||||
#define MCF_INTC_IPRH_INT53 (0x200000)
|
||||
#define MCF_INTC_IPRH_INT54 (0x400000)
|
||||
#define MCF_INTC_IPRH_INT55 (0x800000)
|
||||
#define MCF_INTC_IPRH_INT56 (0x1000000)
|
||||
#define MCF_INTC_IPRH_INT57 (0x2000000)
|
||||
#define MCF_INTC_IPRH_INT58 (0x4000000)
|
||||
#define MCF_INTC_IPRH_INT59 (0x8000000)
|
||||
#define MCF_INTC_IPRH_INT60 (0x10000000)
|
||||
#define MCF_INTC_IPRH_INT61 (0x20000000)
|
||||
#define MCF_INTC_IPRH_INT62 (0x40000000)
|
||||
#define MCF_INTC_IPRH_INT63 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC_IPRL */
|
||||
#define MCF_INTC_IPRL_INT1 (0x2)
|
||||
#define MCF_INTC_IPRL_INT2 (0x4)
|
||||
#define MCF_INTC_IPRL_INT3 (0x8)
|
||||
#define MCF_INTC_IPRL_INT4 (0x10)
|
||||
#define MCF_INTC_IPRL_INT5 (0x20)
|
||||
#define MCF_INTC_IPRL_INT6 (0x40)
|
||||
#define MCF_INTC_IPRL_INT7 (0x80)
|
||||
#define MCF_INTC_IPRL_INT8 (0x100)
|
||||
#define MCF_INTC_IPRL_INT9 (0x200)
|
||||
#define MCF_INTC_IPRL_INT10 (0x400)
|
||||
#define MCF_INTC_IPRL_INT11 (0x800)
|
||||
#define MCF_INTC_IPRL_INT12 (0x1000)
|
||||
#define MCF_INTC_IPRL_INT13 (0x2000)
|
||||
#define MCF_INTC_IPRL_INT14 (0x4000)
|
||||
#define MCF_INTC_IPRL_INT15 (0x8000)
|
||||
#define MCF_INTC_IPRL_INT16 (0x10000)
|
||||
#define MCF_INTC_IPRL_INT17 (0x20000)
|
||||
#define MCF_INTC_IPRL_INT18 (0x40000)
|
||||
#define MCF_INTC_IPRL_INT19 (0x80000)
|
||||
#define MCF_INTC_IPRL_INT20 (0x100000)
|
||||
#define MCF_INTC_IPRL_INT21 (0x200000)
|
||||
#define MCF_INTC_IPRL_INT22 (0x400000)
|
||||
#define MCF_INTC_IPRL_INT23 (0x800000)
|
||||
#define MCF_INTC_IPRL_INT24 (0x1000000)
|
||||
#define MCF_INTC_IPRL_INT25 (0x2000000)
|
||||
#define MCF_INTC_IPRL_INT26 (0x4000000)
|
||||
#define MCF_INTC_IPRL_INT27 (0x8000000)
|
||||
#define MCF_INTC_IPRL_INT28 (0x10000000)
|
||||
#define MCF_INTC_IPRL_INT29 (0x20000000)
|
||||
#define MCF_INTC_IPRL_INT30 (0x40000000)
|
||||
#define MCF_INTC_IPRL_INT31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC_IMRH */
|
||||
#define MCF_INTC_IMRH_INT_MASK32 (0x1)
|
||||
#define MCF_INTC_IMRH_INT_MASK33 (0x2)
|
||||
#define MCF_INTC_IMRH_INT_MASK34 (0x4)
|
||||
#define MCF_INTC_IMRH_INT_MASK35 (0x8)
|
||||
#define MCF_INTC_IMRH_INT_MASK36 (0x10)
|
||||
#define MCF_INTC_IMRH_INT_MASK37 (0x20)
|
||||
#define MCF_INTC_IMRH_INT_MASK38 (0x40)
|
||||
#define MCF_INTC_IMRH_INT_MASK39 (0x80)
|
||||
#define MCF_INTC_IMRH_INT_MASK40 (0x100)
|
||||
#define MCF_INTC_IMRH_INT_MASK41 (0x200)
|
||||
#define MCF_INTC_IMRH_INT_MASK42 (0x400)
|
||||
#define MCF_INTC_IMRH_INT_MASK43 (0x800)
|
||||
#define MCF_INTC_IMRH_INT_MASK44 (0x1000)
|
||||
#define MCF_INTC_IMRH_INT_MASK45 (0x2000)
|
||||
#define MCF_INTC_IMRH_INT_MASK46 (0x4000)
|
||||
#define MCF_INTC_IMRH_INT_MASK47 (0x8000)
|
||||
#define MCF_INTC_IMRH_INT_MASK48 (0x10000)
|
||||
#define MCF_INTC_IMRH_INT_MASK49 (0x20000)
|
||||
#define MCF_INTC_IMRH_INT_MASK50 (0x40000)
|
||||
#define MCF_INTC_IMRH_INT_MASK51 (0x80000)
|
||||
#define MCF_INTC_IMRH_INT_MASK52 (0x100000)
|
||||
#define MCF_INTC_IMRH_INT_MASK53 (0x200000)
|
||||
#define MCF_INTC_IMRH_INT_MASK54 (0x400000)
|
||||
#define MCF_INTC_IMRH_INT_MASK55 (0x800000)
|
||||
#define MCF_INTC_IMRH_INT_MASK56 (0x1000000)
|
||||
#define MCF_INTC_IMRH_INT_MASK57 (0x2000000)
|
||||
#define MCF_INTC_IMRH_INT_MASK58 (0x4000000)
|
||||
#define MCF_INTC_IMRH_INT_MASK59 (0x8000000)
|
||||
#define MCF_INTC_IMRH_INT_MASK60 (0x10000000)
|
||||
#define MCF_INTC_IMRH_INT_MASK61 (0x20000000)
|
||||
#define MCF_INTC_IMRH_INT_MASK62 (0x40000000)
|
||||
#define MCF_INTC_IMRH_INT_MASK63 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC_IMRL */
|
||||
#define MCF_INTC_IMRL_MASKALL (0x1)
|
||||
#define MCF_INTC_IMRL_INT_MASK1 (0x2)
|
||||
#define MCF_INTC_IMRL_INT_MASK2 (0x4)
|
||||
#define MCF_INTC_IMRL_INT_MASK3 (0x8)
|
||||
#define MCF_INTC_IMRL_INT_MASK4 (0x10)
|
||||
#define MCF_INTC_IMRL_INT_MASK5 (0x20)
|
||||
#define MCF_INTC_IMRL_INT_MASK6 (0x40)
|
||||
#define MCF_INTC_IMRL_INT_MASK7 (0x80)
|
||||
#define MCF_INTC_IMRL_INT_MASK8 (0x100)
|
||||
#define MCF_INTC_IMRL_INT_MASK9 (0x200)
|
||||
#define MCF_INTC_IMRL_INT_MASK10 (0x400)
|
||||
#define MCF_INTC_IMRL_INT_MASK11 (0x800)
|
||||
#define MCF_INTC_IMRL_INT_MASK12 (0x1000)
|
||||
#define MCF_INTC_IMRL_INT_MASK13 (0x2000)
|
||||
#define MCF_INTC_IMRL_INT_MASK14 (0x4000)
|
||||
#define MCF_INTC_IMRL_INT_MASK15 (0x8000)
|
||||
#define MCF_INTC_IMRL_INT_MASK16 (0x10000)
|
||||
#define MCF_INTC_IMRL_INT_MASK17 (0x20000)
|
||||
#define MCF_INTC_IMRL_INT_MASK18 (0x40000)
|
||||
#define MCF_INTC_IMRL_INT_MASK19 (0x80000)
|
||||
#define MCF_INTC_IMRL_INT_MASK20 (0x100000)
|
||||
#define MCF_INTC_IMRL_INT_MASK21 (0x200000)
|
||||
#define MCF_INTC_IMRL_INT_MASK22 (0x400000)
|
||||
#define MCF_INTC_IMRL_INT_MASK23 (0x800000)
|
||||
#define MCF_INTC_IMRL_INT_MASK24 (0x1000000)
|
||||
#define MCF_INTC_IMRL_INT_MASK25 (0x2000000)
|
||||
#define MCF_INTC_IMRL_INT_MASK26 (0x4000000)
|
||||
#define MCF_INTC_IMRL_INT_MASK27 (0x8000000)
|
||||
#define MCF_INTC_IMRL_INT_MASK28 (0x10000000)
|
||||
#define MCF_INTC_IMRL_INT_MASK29 (0x20000000)
|
||||
#define MCF_INTC_IMRL_INT_MASK30 (0x40000000)
|
||||
#define MCF_INTC_IMRL_INT_MASK31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC_INTFRCH */
|
||||
#define MCF_INTC_INTFRCH_INTFRC32 (0x1)
|
||||
#define MCF_INTC_INTFRCH_INTFRC33 (0x2)
|
||||
#define MCF_INTC_INTFRCH_INTFRC34 (0x4)
|
||||
#define MCF_INTC_INTFRCH_INTFRC35 (0x8)
|
||||
#define MCF_INTC_INTFRCH_INTFRC36 (0x10)
|
||||
#define MCF_INTC_INTFRCH_INTFRC37 (0x20)
|
||||
#define MCF_INTC_INTFRCH_INTFRC38 (0x40)
|
||||
#define MCF_INTC_INTFRCH_INTFRC39 (0x80)
|
||||
#define MCF_INTC_INTFRCH_INTFRC40 (0x100)
|
||||
#define MCF_INTC_INTFRCH_INTFRC41 (0x200)
|
||||
#define MCF_INTC_INTFRCH_INTFRC42 (0x400)
|
||||
#define MCF_INTC_INTFRCH_INTFRC43 (0x800)
|
||||
#define MCF_INTC_INTFRCH_INTFRC44 (0x1000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC45 (0x2000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC46 (0x4000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC47 (0x8000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC48 (0x10000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC49 (0x20000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC50 (0x40000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC51 (0x80000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC52 (0x100000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC53 (0x200000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC54 (0x400000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC55 (0x800000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC56 (0x1000000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC57 (0x2000000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC58 (0x4000000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC59 (0x8000000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC60 (0x10000000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC61 (0x20000000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC62 (0x40000000)
|
||||
#define MCF_INTC_INTFRCH_INTFRC63 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC_INTFRCL */
|
||||
#define MCF_INTC_INTFRCL_INTFRC1 (0x2)
|
||||
#define MCF_INTC_INTFRCL_INTFRC2 (0x4)
|
||||
#define MCF_INTC_INTFRCL_INTFRC3 (0x8)
|
||||
#define MCF_INTC_INTFRCL_INTFRC4 (0x10)
|
||||
#define MCF_INTC_INTFRCL_INTFRC5 (0x20)
|
||||
#define MCF_INTC_INTFRCL_INTFRC6 (0x40)
|
||||
#define MCF_INTC_INTFRCL_INTFRC7 (0x80)
|
||||
#define MCF_INTC_INTFRCL_INTFRC8 (0x100)
|
||||
#define MCF_INTC_INTFRCL_INTFRC9 (0x200)
|
||||
#define MCF_INTC_INTFRCL_INTFRC10 (0x400)
|
||||
#define MCF_INTC_INTFRCL_INTFRC11 (0x800)
|
||||
#define MCF_INTC_INTFRCL_INTFRC12 (0x1000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC13 (0x2000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC14 (0x4000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC15 (0x8000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC16 (0x10000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC17 (0x20000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC18 (0x40000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC19 (0x80000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC20 (0x100000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC21 (0x200000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC22 (0x400000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC23 (0x800000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC24 (0x1000000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC25 (0x2000000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC26 (0x4000000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC27 (0x8000000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC28 (0x10000000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC29 (0x20000000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC30 (0x40000000)
|
||||
#define MCF_INTC_INTFRCL_INTFRC31 (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC_IRLR */
|
||||
#define MCF_INTC_IRLR_IRQ(x) (((x)&0x7F)<<0x1)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC_IACKLPR */
|
||||
#define MCF_INTC_IACKLPR_PRI(x) (((x)&0xF)<<0)
|
||||
#define MCF_INTC_IACKLPR_LEVEL(x) (((x)&0x7)<<0x4)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC_ICR */
|
||||
#define MCF_INTC_ICR_IP(x) (((x)&0x7)<<0)
|
||||
#define MCF_INTC_ICR_IL(x) (((x)&0x7)<<0x3)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC_SWIACK */
|
||||
#define MCF_INTC_SWIACK_VECTOR(x) (((x)&0xFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_INTC_LIACK */
|
||||
#define MCF_INTC_LIACK_VECTOR(x) (((x)&0xFF)<<0)
|
||||
|
||||
|
||||
#endif /* __MCF5475_INTC_H__ */
|
||||
@@ -1,79 +0,0 @@
|
||||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.81
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF5475_MMU_H__
|
||||
#define __MCF5475_MMU_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Memory Management Unit (MMU)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
|
||||
/* note the uint32_t_a - this is to avoid gcc warnings about pointer aliasing */
|
||||
#define MCF_MMU_MMUCR (*(volatile uint32_t_a*)(&_MMUBAR[0]))
|
||||
#define MCF_MMU_MMUOR (*(volatile uint32_t_a*)(&_MMUBAR[0x4]))
|
||||
#define MCF_MMU_MMUSR (*(volatile uint32_t_a*)(&_MMUBAR[0x8]))
|
||||
#define MCF_MMU_MMUAR (*(volatile uint32_t_a*)(&_MMUBAR[0x10]))
|
||||
#define MCF_MMU_MMUTR (*(volatile uint32_t_a*)(&_MMUBAR[0x14]))
|
||||
#define MCF_MMU_MMUDR (*(volatile uint32_t_a*)(&_MMUBAR[0x18]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_MMU_MMUCR */
|
||||
#define MCF_MMU_MMUCR_EN (0x1)
|
||||
#define MCF_MMU_MMUCR_ASM (0x2)
|
||||
|
||||
/* Bit definitions and macros for MCF_MMU_MMUOR */
|
||||
#define MCF_MMU_MMUOR_UAA (0x1)
|
||||
#define MCF_MMU_MMUOR_ACC (0x2)
|
||||
#define MCF_MMU_MMUOR_RW (0x4)
|
||||
#define MCF_MMU_MMUOR_ADR (0x8)
|
||||
#define MCF_MMU_MMUOR_ITLB (0x10)
|
||||
#define MCF_MMU_MMUOR_CAS (0x20)
|
||||
#define MCF_MMU_MMUOR_CNL (0x40)
|
||||
#define MCF_MMU_MMUOR_CA (0x80)
|
||||
#define MCF_MMU_MMUOR_STLB (0x100)
|
||||
#define MCF_MMU_MMUOR_AA(x) (((x)&0xFFFF)<<0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_MMU_MMUSR */
|
||||
#define MCF_MMU_MMUSR_HIT (0x2)
|
||||
#define MCF_MMU_MMUSR_WF (0x8)
|
||||
#define MCF_MMU_MMUSR_RF (0x10)
|
||||
#define MCF_MMU_MMUSR_SPF (0x20)
|
||||
|
||||
/* Bit definitions and macros for MCF_MMU_MMUAR */
|
||||
#define MCF_MMU_MMUAR_FA(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_MMU_MMUTR */
|
||||
#define MCF_MMU_MMUTR_V (0x1)
|
||||
#define MCF_MMU_MMUTR_SG (0x2)
|
||||
#define MCF_MMU_MMUTR_ID(x) (((x) & 0xFF) << 0x2)
|
||||
#define MCF_MMU_MMUTR_VA(x) (((x)&0x3FFFFF)<<0xA)
|
||||
|
||||
/* Bit definitions and macros for MCF_MMU_MMUDR */
|
||||
#define MCF_MMU_MMUDR_LK (0x2)
|
||||
#define MCF_MMU_MMUDR_X (0x4)
|
||||
#define MCF_MMU_MMUDR_W (0x8)
|
||||
#define MCF_MMU_MMUDR_R (0x10)
|
||||
#define MCF_MMU_MMUDR_SP (0x20)
|
||||
#define MCF_MMU_MMUDR_CM(x) (((x) & 0x3) << 0x6)
|
||||
#define MCF_MMU_MMUDR_SZ(x) (((x) & 0x3) << 0x8)
|
||||
#define MCF_MMU_MMUDR_PA(x) (((x) & 0x3FFFFF) << 0xA)
|
||||
|
||||
|
||||
#endif /* __MCF5475_MMU_H__ */
|
||||
@@ -1,233 +0,0 @@
|
||||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.81
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF5475_PAD_H__
|
||||
#define __MCF5475_PAD_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Common GPIO
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_PAD_PAR_FBCTL (*(volatile uint16_t*)(&_MBAR[0xA40]))
|
||||
#define MCF_PAD_PAR_FBCS (*(volatile uint8_t *)(&_MBAR[0xA42]))
|
||||
#define MCF_PAD_PAR_DMA (*(volatile uint8_t *)(&_MBAR[0xA43]))
|
||||
#define MCF_PAD_PAR_FECI2CIRQ (*(volatile uint16_t*)(&_MBAR[0xA44]))
|
||||
#define MCF_PAD_PAR_PCIBG (*(volatile uint16_t*)(&_MBAR[0xA48]))
|
||||
#define MCF_PAD_PAR_PCIBR (*(volatile uint16_t*)(&_MBAR[0xA4A]))
|
||||
#define MCF_PAD_PAR_PSC3 (*(volatile uint8_t *)(&_MBAR[0xA4C]))
|
||||
#define MCF_PAD_PAR_PSC2 (*(volatile uint8_t *)(&_MBAR[0xA4D]))
|
||||
#define MCF_PAD_PAR_PSC1 (*(volatile uint8_t *)(&_MBAR[0xA4E]))
|
||||
#define MCF_PAD_PAR_PSC0 (*(volatile uint8_t *)(&_MBAR[0xA4F]))
|
||||
#define MCF_PAD_PAR_DSPI (*(volatile uint16_t*)(&_MBAR[0xA50]))
|
||||
#define MCF_PAD_PAR_TIMER (*(volatile uint8_t *)(&_MBAR[0xA52]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_PAD_PAR_FBCTL */
|
||||
#define MCF_PAD_PAR_FBCTL_PAR_ALE(x) (((x)&0x3)<<0)
|
||||
#define MCF_PAD_PAR_FBCTL_PAR_ALE_GPIO (0)
|
||||
#define MCF_PAD_PAR_FBCTL_PAR_ALE_TBST (0x2)
|
||||
#define MCF_PAD_PAR_FBCTL_PAR_ALE_ALE (0x3)
|
||||
#define MCF_PAD_PAR_FBCTL_PAR_TA (0x4)
|
||||
#define MCF_PAD_PAR_FBCTL_PAR_RWB(x) (((x)&0x3)<<0x4)
|
||||
#define MCF_PAD_PAR_FBCTL_PAR_RWB_GPIO (0)
|
||||
#define MCF_PAD_PAR_FBCTL_PAR_RWB_TBST (0x20)
|
||||
#define MCF_PAD_PAR_FBCTL_PAR_RWB_RW (0x30)
|
||||
#define MCF_PAD_PAR_FBCTL_PAR_OE (0x40)
|
||||
#define MCF_PAD_PAR_FBCTL_PAR_BWE0 (0x100)
|
||||
#define MCF_PAD_PAR_FBCTL_PAR_BWE1 (0x400)
|
||||
#define MCF_PAD_PAR_FBCTL_PAR_BWE2 (0x1000)
|
||||
#define MCF_PAD_PAR_FBCTL_PAR_BWE3 (0x4000)
|
||||
|
||||
/* Bit definitions and macros for MCF_PAD_PAR_FBCS */
|
||||
#define MCF_PAD_PAR_FBCS_PAR_CS1 (0x2)
|
||||
#define MCF_PAD_PAR_FBCS_PAR_CS2 (0x4)
|
||||
#define MCF_PAD_PAR_FBCS_PAR_CS3 (0x8)
|
||||
#define MCF_PAD_PAR_FBCS_PAR_CS4 (0x10)
|
||||
#define MCF_PAD_PAR_FBCS_PAR_CS5 (0x20)
|
||||
|
||||
/* Bit definitions and macros for MCF_PAD_PAR_DMA */
|
||||
#define MCF_PAD_PAR_DMA_PAR_DREQ0(x) (((x)&0x3)<<0)
|
||||
#define MCF_PAD_PAR_DMA_PAR_DREQ0_GPIO (0)
|
||||
#define MCF_PAD_PAR_DMA_PAR_DREQ0_TIN0 (0x2)
|
||||
#define MCF_PAD_PAR_DMA_PAR_DREQ0_DREQ0 (0x3)
|
||||
#define MCF_PAD_PAR_DMA_PAR_DREQ1(x) (((x)&0x3)<<0x2)
|
||||
#define MCF_PAD_PAR_DMA_PAR_DREQ1_GPIO (0)
|
||||
#define MCF_PAD_PAR_DMA_PAR_DREQ1_IRQ1 (0x4)
|
||||
#define MCF_PAD_PAR_DMA_PAR_DREQ1_TIN1 (0x8)
|
||||
#define MCF_PAD_PAR_DMA_PAR_DREQ1_DREQ1 (0xC)
|
||||
#define MCF_PAD_PAR_DMA_PAR_DACK0(x) (((x)&0x3)<<0x4)
|
||||
#define MCF_PAD_PAR_DMA_PAR_DACK0_GPIO (0)
|
||||
#define MCF_PAD_PAR_DMA_PAR_DACK0_TOUT0 (0x20)
|
||||
#define MCF_PAD_PAR_DMA_PAR_DACK0_DACK0 (0x30)
|
||||
#define MCF_PAD_PAR_DMA_PAR_DACK1(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_PAD_PAR_DMA_PAR_DACK1_GPIO (0)
|
||||
#define MCF_PAD_PAR_DMA_PAR_DACK1_TOUT1 (0x80)
|
||||
#define MCF_PAD_PAR_DMA_PAR_DACK1_DACK1 (0xC0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PAD_PAR_FECI2CIRQ */
|
||||
#define MCF_PAD_PAR_FECI2CIRQ_PAR_IRQ5 (0x1)
|
||||
#define MCF_PAD_PAR_FECI2CIRQ_PAR_IRQ6 (0x2)
|
||||
#define MCF_PAD_PAR_FECI2CIRQ_PAR_SCL (0x4)
|
||||
#define MCF_PAD_PAR_FECI2CIRQ_PAR_SDA (0x8)
|
||||
#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDC(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDC_SCL (0x80)
|
||||
#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDC_E1MDC (0xC0)
|
||||
#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDIO(x) (((x)&0x3)<<0x8)
|
||||
#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDIO_SDA (0x200)
|
||||
#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDIO_E1MDIO (0x300)
|
||||
#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MII (0x400)
|
||||
#define MCF_PAD_PAR_FECI2CIRQ_PAR_E17 (0x800)
|
||||
#define MCF_PAD_PAR_FECI2CIRQ_PAR_E0MDC (0x1000)
|
||||
#define MCF_PAD_PAR_FECI2CIRQ_PAR_E0MDIO (0x2000)
|
||||
#define MCF_PAD_PAR_FECI2CIRQ_PAR_E0MII (0x4000)
|
||||
#define MCF_PAD_PAR_FECI2CIRQ_PAR_E07 (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_PAD_PAR_PCIBG */
|
||||
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0(x) (((x)&0x3)<<0)
|
||||
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0_GPIO (0)
|
||||
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0_TOUT0 (0x2)
|
||||
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0_PCIBG0 (0x3)
|
||||
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1(x) (((x)&0x3)<<0x2)
|
||||
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1_GPIO (0)
|
||||
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1_TOUT1 (0x8)
|
||||
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1_PCIBG1 (0xC)
|
||||
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2(x) (((x)&0x3)<<0x4)
|
||||
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2_GPIO (0)
|
||||
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2_TOUT2 (0x20)
|
||||
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2_PCIBG2 (0x30)
|
||||
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3_GPIO (0)
|
||||
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3_TOUT3 (0x80)
|
||||
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3_PCIBG3 (0xC0)
|
||||
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4(x) (((x)&0x3)<<0x8)
|
||||
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4_GPIO (0)
|
||||
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4_TBST (0x200)
|
||||
#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4_PCIBG4 (0x300)
|
||||
|
||||
/* Bit definitions and macros for MCF_PAD_PAR_PCIBR */
|
||||
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0(x) (((x)&0x3)<<0)
|
||||
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0_GPIO (0)
|
||||
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0_TIN0 (0x2)
|
||||
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0_PCIBR0 (0x3)
|
||||
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1(x) (((x)&0x3)<<0x2)
|
||||
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1_GPIO (0)
|
||||
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1_TIN1 (0x8)
|
||||
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1_PCIBR1 (0xC)
|
||||
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2(x) (((x)&0x3)<<0x4)
|
||||
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2_GPIO (0)
|
||||
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2_TIN2 (0x20)
|
||||
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2_PCIBR2 (0x30)
|
||||
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3_GPIO (0)
|
||||
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3_TIN3 (0x80)
|
||||
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3_PCIBR3 (0xC0)
|
||||
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4(x) (((x)&0x3)<<0x8)
|
||||
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4_GPIO (0)
|
||||
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4_IRQ4 (0x200)
|
||||
#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4_PCIBR4 (0x300)
|
||||
|
||||
/* Bit definitions and macros for MCF_PAD_PAR_PSC3 */
|
||||
#define MCF_PAD_PAR_PSC3_PAR_TXD3 (0x4)
|
||||
#define MCF_PAD_PAR_PSC3_PAR_RXD3 (0x8)
|
||||
#define MCF_PAD_PAR_PSC3_PAR_RTS3(x) (((x)&0x3)<<0x4)
|
||||
#define MCF_PAD_PAR_PSC3_PAR_RTS3_GPIO (0)
|
||||
#define MCF_PAD_PAR_PSC3_PAR_RTS3_FSYNC (0x20)
|
||||
#define MCF_PAD_PAR_PSC3_PAR_RTS3_RTS (0x30)
|
||||
#define MCF_PAD_PAR_PSC3_PAR_CTS3(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_PAD_PAR_PSC3_PAR_CTS3_GPIO (0)
|
||||
#define MCF_PAD_PAR_PSC3_PAR_CTS3_BCLK (0x80)
|
||||
#define MCF_PAD_PAR_PSC3_PAR_CTS3_CTS (0xC0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PAD_PAR_PSC2 */
|
||||
#define MCF_PAD_PAR_PSC2_PAR_TXD2 (0x4)
|
||||
#define MCF_PAD_PAR_PSC2_PAR_RXD2 (0x8)
|
||||
#define MCF_PAD_PAR_PSC2_PAR_RTS2(x) (((x)&0x3)<<0x4)
|
||||
#define MCF_PAD_PAR_PSC2_PAR_RTS2_GPIO (0)
|
||||
#define MCF_PAD_PAR_PSC2_PAR_RTS2_FSYNC (0x20)
|
||||
#define MCF_PAD_PAR_PSC2_PAR_RTS2_RTS (0x30)
|
||||
#define MCF_PAD_PAR_PSC2_PAR_CTS2(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_PAD_PAR_PSC2_PAR_CTS2_GPIO (0)
|
||||
#define MCF_PAD_PAR_PSC2_PAR_CTS2_BCLK (0x80)
|
||||
#define MCF_PAD_PAR_PSC2_PAR_CTS2_CTS (0xC0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PAD_PAR_PSC1 */
|
||||
#define MCF_PAD_PAR_PSC1_PAR_TXD1 (0x4)
|
||||
#define MCF_PAD_PAR_PSC1_PAR_RXD1 (0x8)
|
||||
#define MCF_PAD_PAR_PSC1_PAR_RTS1(x) (((x)&0x3)<<0x4)
|
||||
#define MCF_PAD_PAR_PSC1_PAR_RTS1_GPIO (0)
|
||||
#define MCF_PAD_PAR_PSC1_PAR_RTS1_FSYNC (0x20)
|
||||
#define MCF_PAD_PAR_PSC1_PAR_RTS1_RTS (0x30)
|
||||
#define MCF_PAD_PAR_PSC1_PAR_CTS1(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_PAD_PAR_PSC1_PAR_CTS1_GPIO (0)
|
||||
#define MCF_PAD_PAR_PSC1_PAR_CTS1_BCLK (0x80)
|
||||
#define MCF_PAD_PAR_PSC1_PAR_CTS1_CTS (0xC0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PAD_PAR_PSC0 */
|
||||
#define MCF_PAD_PAR_PSC0_PAR_TXD0 (0x4)
|
||||
#define MCF_PAD_PAR_PSC0_PAR_RXD0 (0x8)
|
||||
#define MCF_PAD_PAR_PSC0_PAR_RTS0(x) (((x)&0x3)<<0x4)
|
||||
#define MCF_PAD_PAR_PSC0_PAR_RTS0_GPIO (0)
|
||||
#define MCF_PAD_PAR_PSC0_PAR_RTS0_FSYNC (0x20)
|
||||
#define MCF_PAD_PAR_PSC0_PAR_RTS0_RTS (0x30)
|
||||
#define MCF_PAD_PAR_PSC0_PAR_CTS0(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_PAD_PAR_PSC0_PAR_CTS0_GPIO (0)
|
||||
#define MCF_PAD_PAR_PSC0_PAR_CTS0_BCLK (0x80)
|
||||
#define MCF_PAD_PAR_PSC0_PAR_CTS0_CTS (0xC0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PAD_PAR_DSPI */
|
||||
#define MCF_PAD_PAR_DSPI_PAR_SOUT(x) (((x)&0x3)<<0)
|
||||
#define MCF_PAD_PAR_DSPI_PAR_SOUT_GPIO (0)
|
||||
#define MCF_PAD_PAR_DSPI_PAR_SOUT_TXD (0x2)
|
||||
#define MCF_PAD_PAR_DSPI_PAR_SOUT_SOUT (0x3)
|
||||
#define MCF_PAD_PAR_DSPI_PAR_SIN(x) (((x)&0x3)<<0x2)
|
||||
#define MCF_PAD_PAR_DSPI_PAR_SIN_GPIO (0)
|
||||
#define MCF_PAD_PAR_DSPI_PAR_SIN_RXD (0x8)
|
||||
#define MCF_PAD_PAR_DSPI_PAR_SIN_SIN (0xC)
|
||||
#define MCF_PAD_PAR_DSPI_PAR_SCK(x) (((x)&0x3)<<0x4)
|
||||
#define MCF_PAD_PAR_DSPI_PAR_SCK_GPIO (0)
|
||||
#define MCF_PAD_PAR_DSPI_PAR_SCK_BCLK (0x10)
|
||||
#define MCF_PAD_PAR_DSPI_PAR_SCK_CTS (0x20)
|
||||
#define MCF_PAD_PAR_DSPI_PAR_SCK_SCK (0x30)
|
||||
#define MCF_PAD_PAR_DSPI_PAR_CS0(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_PAD_PAR_DSPI_PAR_CS0_GPIO (0)
|
||||
#define MCF_PAD_PAR_DSPI_PAR_CS0_FSYNC (0x40)
|
||||
#define MCF_PAD_PAR_DSPI_PAR_CS0_RTS (0x80)
|
||||
#define MCF_PAD_PAR_DSPI_PAR_CS0_DSPICS0 (0xC0)
|
||||
#define MCF_PAD_PAR_DSPI_PAR_CS2(x) (((x)&0x3)<<0x8)
|
||||
#define MCF_PAD_PAR_DSPI_PAR_CS2_GPIO (0)
|
||||
#define MCF_PAD_PAR_DSPI_PAR_CS2_TOUT2 (0x200)
|
||||
#define MCF_PAD_PAR_DSPI_PAR_CS2_DSPICS2 (0x300)
|
||||
#define MCF_PAD_PAR_DSPI_PAR_CS3(x) (((x)&0x3)<<0xA)
|
||||
#define MCF_PAD_PAR_DSPI_PAR_CS3_GPIO (0)
|
||||
#define MCF_PAD_PAR_DSPI_PAR_CS3_TOUT3 (0x800)
|
||||
#define MCF_PAD_PAR_DSPI_PAR_CS3_DSPICS3 (0xC00)
|
||||
#define MCF_PAD_PAR_DSPI_PAR_CS5 (0x1000)
|
||||
|
||||
/* Bit definitions and macros for MCF_PAD_PAR_TIMER */
|
||||
#define MCF_PAD_PAR_TIMER_PAR_TOUT2 (0x1)
|
||||
#define MCF_PAD_PAR_TIMER_PAR_TIN2(x) (((x)&0x3)<<0x1)
|
||||
#define MCF_PAD_PAR_TIMER_PAR_TIN2_IRQ2 (0x4)
|
||||
#define MCF_PAD_PAR_TIMER_PAR_TIN2_TIN2 (0x6)
|
||||
#define MCF_PAD_PAR_TIMER_PAR_TOUT3 (0x8)
|
||||
#define MCF_PAD_PAR_TIMER_PAR_TIN3(x) (((x)&0x3)<<0x4)
|
||||
#define MCF_PAD_PAR_TIMER_PAR_TIN3_IRQ3 (0x20)
|
||||
#define MCF_PAD_PAR_TIMER_PAR_TIN3_TIN3 (0x30)
|
||||
|
||||
|
||||
#endif /* __MCF5475_PAD_H__ */
|
||||
@@ -1,376 +0,0 @@
|
||||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.81
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF5475_PCI_H__
|
||||
#define __MCF5475_PCI_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* PCI Bus Controller (PCI)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_PCI_PCIIDR (*(volatile uint32_t*)(&_MBAR[0xB00]))
|
||||
#define MCF_PCI_PCISCR (*(volatile uint32_t*)(&_MBAR[0xB04]))
|
||||
#define MCF_PCI_PCICCRIR (*(volatile uint32_t*)(&_MBAR[0xB08]))
|
||||
#define MCF_PCI_PCICR1 (*(volatile uint32_t*)(&_MBAR[0xB0C]))
|
||||
#define MCF_PCI_PCIBAR0 (*(volatile uint32_t*)(&_MBAR[0xB10]))
|
||||
#define MCF_PCI_PCIBAR1 (*(volatile uint32_t*)(&_MBAR[0xB14]))
|
||||
#define MCF_PCI_PCICCPR (*(volatile uint32_t*)(&_MBAR[0xB28]))
|
||||
#define MCF_PCI_PCISID (*(volatile uint32_t*)(&_MBAR[0xB2C]))
|
||||
#define MCF_PCI_PCICR2 (*(volatile uint32_t*)(&_MBAR[0xB3C]))
|
||||
#define MCF_PCI_PCIGSCR (*(volatile uint32_t*)(&_MBAR[0xB60]))
|
||||
#define MCF_PCI_PCITBATR0 (*(volatile uint32_t*)(&_MBAR[0xB64]))
|
||||
#define MCF_PCI_PCITBATR1 (*(volatile uint32_t*)(&_MBAR[0xB68]))
|
||||
#define MCF_PCI_PCITCR (*(volatile uint32_t*)(&_MBAR[0xB6C]))
|
||||
#define MCF_PCI_PCIIW0BTAR (*(volatile uint32_t*)(&_MBAR[0xB70]))
|
||||
#define MCF_PCI_PCIIW1BTAR (*(volatile uint32_t*)(&_MBAR[0xB74]))
|
||||
#define MCF_PCI_PCIIW2BTAR (*(volatile uint32_t*)(&_MBAR[0xB78]))
|
||||
#define MCF_PCI_PCIIWCR (*(volatile uint32_t*)(&_MBAR[0xB80]))
|
||||
#define MCF_PCI_PCIICR (*(volatile uint32_t*)(&_MBAR[0xB84]))
|
||||
#define MCF_PCI_PCIISR (*(volatile uint32_t*)(&_MBAR[0xB88]))
|
||||
#define MCF_PCI_PCICAR (*(volatile uint32_t*)(&_MBAR[0xBF8]))
|
||||
#define MCF_PCI_PCITPSR (*(volatile uint32_t*)(&_MBAR[0x8400]))
|
||||
#define MCF_PCI_PCITSAR (*(volatile uint32_t*)(&_MBAR[0x8404]))
|
||||
#define MCF_PCI_PCITTCR (*(volatile uint32_t*)(&_MBAR[0x8408]))
|
||||
#define MCF_PCI_PCITER (*(volatile uint32_t*)(&_MBAR[0x840C]))
|
||||
#define MCF_PCI_PCITNAR (*(volatile uint32_t*)(&_MBAR[0x8410]))
|
||||
#define MCF_PCI_PCITLWR (*(volatile uint32_t*)(&_MBAR[0x8414]))
|
||||
#define MCF_PCI_PCITDCR (*(volatile uint32_t*)(&_MBAR[0x8418]))
|
||||
#define MCF_PCI_PCITSR (*(volatile uint32_t*)(&_MBAR[0x841C]))
|
||||
#define MCF_PCI_PCITFDR (*(volatile uint32_t*)(&_MBAR[0x8440]))
|
||||
#define MCF_PCI_PCITFSR (*(volatile uint32_t*)(&_MBAR[0x8444]))
|
||||
#define MCF_PCI_PCITFCR (*(volatile uint32_t*)(&_MBAR[0x8448]))
|
||||
#define MCF_PCI_PCITFAR (*(volatile uint32_t*)(&_MBAR[0x844C]))
|
||||
#define MCF_PCI_PCITFRPR (*(volatile uint32_t*)(&_MBAR[0x8450]))
|
||||
#define MCF_PCI_PCITFWPR (*(volatile uint32_t*)(&_MBAR[0x8454]))
|
||||
#define MCF_PCI_PCIRPSR (*(volatile uint32_t*)(&_MBAR[0x8480]))
|
||||
#define MCF_PCI_PCIRSAR (*(volatile uint32_t*)(&_MBAR[0x8484]))
|
||||
#define MCF_PCI_PCIRTCR (*(volatile uint32_t*)(&_MBAR[0x8488]))
|
||||
#define MCF_PCI_PCIRER (*(volatile uint32_t*)(&_MBAR[0x848C]))
|
||||
#define MCF_PCI_PCIRNAR (*(volatile uint32_t*)(&_MBAR[0x8490]))
|
||||
#define MCF_PCI_PCIRDCR (*(volatile uint32_t*)(&_MBAR[0x8498]))
|
||||
#define MCF_PCI_PCIRSR (*(volatile uint32_t*)(&_MBAR[0x849C]))
|
||||
#define MCF_PCI_PCIRFDR (*(volatile uint32_t*)(&_MBAR[0x84C0]))
|
||||
#define MCF_PCI_PCIRFSR (*(volatile uint32_t*)(&_MBAR[0x84C4]))
|
||||
#define MCF_PCI_PCIRFCR (*(volatile uint32_t*)(&_MBAR[0x84C8]))
|
||||
#define MCF_PCI_PCIRFAR (*(volatile uint32_t*)(&_MBAR[0x84CC]))
|
||||
#define MCF_PCI_PCIRFRPR (*(volatile uint32_t*)(&_MBAR[0x84D0]))
|
||||
#define MCF_PCI_PCIRFWPR (*(volatile uint32_t*)(&_MBAR[0x84D4]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCIIDR */
|
||||
#define MCF_PCI_PCIIDR_VENDORID(x) (((x)&0xFFFF)<<0)
|
||||
#define MCF_PCI_PCIIDR_DEVICEID(x) (((x)&0xFFFF)<<0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCISCR */
|
||||
#define MCF_PCI_PCISCR_IO (0x1)
|
||||
#define MCF_PCI_PCISCR_M (0x2)
|
||||
#define MCF_PCI_PCISCR_B (0x4)
|
||||
#define MCF_PCI_PCISCR_SP (0x8)
|
||||
#define MCF_PCI_PCISCR_MW (0x10)
|
||||
#define MCF_PCI_PCISCR_V (0x20)
|
||||
#define MCF_PCI_PCISCR_PER (0x40)
|
||||
#define MCF_PCI_PCISCR_ST (0x80)
|
||||
#define MCF_PCI_PCISCR_S (0x100)
|
||||
#define MCF_PCI_PCISCR_F (0x200)
|
||||
#define MCF_PCI_PCISCR_C (0x100000)
|
||||
#define MCF_PCI_PCISCR_66M (0x200000)
|
||||
#define MCF_PCI_PCISCR_R (0x400000)
|
||||
#define MCF_PCI_PCISCR_FC (0x800000)
|
||||
#define MCF_PCI_PCISCR_DP (0x1000000)
|
||||
#define MCF_PCI_PCISCR_DT(x) (((x)&0x3)<<0x19)
|
||||
#define MCF_PCI_PCISCR_TS (0x8000000)
|
||||
#define MCF_PCI_PCISCR_TR (0x10000000)
|
||||
#define MCF_PCI_PCISCR_MA (0x20000000)
|
||||
#define MCF_PCI_PCISCR_SE (0x40000000)
|
||||
#define MCF_PCI_PCISCR_PE (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCICCRIR */
|
||||
#define MCF_PCI_PCICCRIR_REVISIONID(x) (((x)&0xFF)<<0)
|
||||
#define MCF_PCI_PCICCRIR_CLASSCODE(x) (((x)&0xFFFFFF)<<0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCICR1 */
|
||||
#define MCF_PCI_PCICR1_CACHELINESIZE(x) (((x)&0xFF)<<0)
|
||||
#define MCF_PCI_PCICR1_LATTIMER(x) (((x)&0xFF)<<0x8)
|
||||
#define MCF_PCI_PCICR1_HEADERTYPE(x) (((x)&0xFF)<<0x10)
|
||||
#define MCF_PCI_PCICR1_BIST(x) (((x)&0xFF)<<0x18)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCIBAR0 */
|
||||
#define MCF_PCI_PCIBAR0_IOM (0x1)
|
||||
#define MCF_PCI_PCIBAR0_RANGE(x) (((x)&0x3)<<0x1)
|
||||
#define MCF_PCI_PCIBAR0_PREF (0x8)
|
||||
#define MCF_PCI_PCIBAR0_BAR0(x) (((x)&0x3FFF)<<0x12)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCIBAR1 */
|
||||
#define MCF_PCI_PCIBAR1_IOM (0x1)
|
||||
#define MCF_PCI_PCIBAR1_RANGE(x) (((x)&0x3)<<0x1)
|
||||
#define MCF_PCI_PCIBAR1_PREF (0x8)
|
||||
#define MCF_PCI_PCIBAR1_BAR1(x) (((x)&0x3)<<0x1E)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCICCPR */
|
||||
#define MCF_PCI_PCICCPR_PCICCP(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCISID */
|
||||
#define MCF_PCI_PCISID_VENDORID(x) (((x)&0xFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCICR2 */
|
||||
#define MCF_PCI_PCICR2_INTLINE(x) (((x)&0xFF)<<0)
|
||||
#define MCF_PCI_PCICR2_INTPIN(x) (((x)&0xFF)<<0x8)
|
||||
#define MCF_PCI_PCICR2_MINGNT(x) (((x)&0xFF)<<0x10)
|
||||
#define MCF_PCI_PCICR2_MAXLAT(x) (((x)&0xFF)<<0x18)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCIGSCR */
|
||||
#define MCF_PCI_PCIGSCR_PR (0x1)
|
||||
#define MCF_PCI_PCIGSCR_SEE (0x1000)
|
||||
#define MCF_PCI_PCIGSCR_PEE (0x2000)
|
||||
#define MCF_PCI_PCIGSCR_CLKINRESERVED(x) (((x)&0x7)<<0x10)
|
||||
#define MCF_PCI_PCIGSCR_XLB2CLKIN(x) (((x)&0x7)<<0x18)
|
||||
#define MCF_PCI_PCIGSCR_SE (0x10000000)
|
||||
#define MCF_PCI_PCIGSCR_PE (0x20000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCITBATR0 */
|
||||
#define MCF_PCI_PCITBATR0_EN (0x1)
|
||||
#define MCF_PCI_PCITBATR0_BAT0(x) (((x)&0x3FFF)<<0x12)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCITBATR1 */
|
||||
#define MCF_PCI_PCITBATR1_EN (0x1)
|
||||
#define MCF_PCI_PCITBATR1_BAT1(x) (((x)&0x3)<<0x1E)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCITCR */
|
||||
#define MCF_PCI_PCITCR_P (0x10000)
|
||||
#define MCF_PCI_PCITCR_LD (0x1000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCIIW0BTAR */
|
||||
#define MCF_PCI_PCIIW0BTAR_WTA0(x) (((x)&0xFF)<<0x8)
|
||||
#define MCF_PCI_PCIIW0BTAR_WAM0(x) (((x)&0xFF)<<0x10)
|
||||
#define MCF_PCI_PCIIW0BTAR_WBA0(x) (((x)&0xFF)<<0x18)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCIIW1BTAR */
|
||||
#define MCF_PCI_PCIIW1BTAR_WTA1(x) (((x)&0xFF)<<0x8)
|
||||
#define MCF_PCI_PCIIW1BTAR_WAM1(x) (((x)&0xFF)<<0x10)
|
||||
#define MCF_PCI_PCIIW1BTAR_WBA1(x) (((x)&0xFF)<<0x18)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCIIW2BTAR */
|
||||
#define MCF_PCI_PCIIW2BTAR_WTA2(x) (((x)&0xFF)<<0x8)
|
||||
#define MCF_PCI_PCIIW2BTAR_WAM2(x) (((x)&0xFF)<<0x10)
|
||||
#define MCF_PCI_PCIIW2BTAR_WBA2(x) (((x)&0xFF)<<0x18)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCIIWCR */
|
||||
#define MCF_PCI_PCIIWCR_WINCTRL2_E (0x100)
|
||||
#define MCF_PCI_PCIIWCR_WINCTRL2_PRC(x) (((x)&0x3)<<0x9)
|
||||
#define MCF_PCI_PCIIWCR_WINCTRL2_IOM (0x800)
|
||||
#define MCF_PCI_PCIIWCR_WINCTRL1_E (0x10000)
|
||||
#define MCF_PCI_PCIIWCR_WINCTRL1_PRC(x) (((x)&0x3)<<0x11)
|
||||
#define MCF_PCI_PCIIWCR_WINCTRL1_IOM (0x80000)
|
||||
#define MCF_PCI_PCIIWCR_WINCTRL0_E (0x1000000)
|
||||
#define MCF_PCI_PCIIWCR_WINCTRL0_PRC(x) (((x)&0x3)<<0x19)
|
||||
#define MCF_PCI_PCIIWCR_WINCTRL0_IOM (0x8000000)
|
||||
#define MCF_PCI_PCIIWCR_WINCTRL2_MEMREAD (0x100)
|
||||
#define MCF_PCI_PCIIWCR_WINCTRL2_MEMRDLINE (0x300)
|
||||
#define MCF_PCI_PCIIWCR_WINCTRL2_MEMRDMUL (0x500)
|
||||
#define MCF_PCI_PCIIWCR_WINCTRL2_IO (0x900)
|
||||
#define MCF_PCI_PCIIWCR_WINCTRL1_MEMREAD (0x10000)
|
||||
#define MCF_PCI_PCIIWCR_WINCTRL1_MEMRDLINE (0x30000)
|
||||
#define MCF_PCI_PCIIWCR_WINCTRL1_MEMRDMUL (0x50000)
|
||||
#define MCF_PCI_PCIIWCR_WINCTRL1_IO (0x90000)
|
||||
#define MCF_PCI_PCIIWCR_WINCTRL0_MEMREAD (0x1000000)
|
||||
#define MCF_PCI_PCIIWCR_WINCTRL0_MEMRDLINE (0x3000000)
|
||||
#define MCF_PCI_PCIIWCR_WINCTRL0_MEMRDMUL (0x5000000)
|
||||
#define MCF_PCI_PCIIWCR_WINCTRL0_IO (0x9000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCIICR */
|
||||
#define MCF_PCI_PCIICR_MAXRETRY(x) (((x)&0xFF)<<0)
|
||||
#define MCF_PCI_PCIICR_TAE (0x1000000)
|
||||
#define MCF_PCI_PCIICR_IAE (0x2000000)
|
||||
#define MCF_PCI_PCIICR_REE (0x4000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCIISR */
|
||||
#define MCF_PCI_PCIISR_TA (0x1000000)
|
||||
#define MCF_PCI_PCIISR_IA (0x2000000)
|
||||
#define MCF_PCI_PCIISR_RE (0x4000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCICAR */
|
||||
#define MCF_PCI_PCICAR_DWORD(x) (((x)&0x3F)<<0x2)
|
||||
#define MCF_PCI_PCICAR_FUNCNUM(x) (((x)&0x7)<<0x8)
|
||||
#define MCF_PCI_PCICAR_DEVNUM(x) (((x)&0x1F)<<0xB)
|
||||
#define MCF_PCI_PCICAR_BUSNUM(x) (((x)&0xFF)<<0x10)
|
||||
#define MCF_PCI_PCICAR_E (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCITPSR */
|
||||
#define MCF_PCI_PCITPSR_PKTSIZE(x) (((x)&0xFFFF)<<0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCITSAR */
|
||||
#define MCF_PCI_PCITSAR_STARTADD(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCITTCR */
|
||||
#define MCF_PCI_PCITTCR_DI (0x1)
|
||||
#define MCF_PCI_PCITTCR_W (0x10)
|
||||
#define MCF_PCI_PCITTCR_MAXBEATS(x) (((x)&0x7)<<0x8)
|
||||
#define MCF_PCI_PCITTCR_MAXRETRY(x) (((x)&0xFF)<<0x10)
|
||||
#define MCF_PCI_PCITTCR_PCICMD(x) (((x)&0xF)<<0x18)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCITER */
|
||||
#define MCF_PCI_PCITER_NE (0x10000)
|
||||
#define MCF_PCI_PCITER_IAE (0x20000)
|
||||
#define MCF_PCI_PCITER_TAE (0x40000)
|
||||
#define MCF_PCI_PCITER_RE (0x80000)
|
||||
#define MCF_PCI_PCITER_SE (0x100000)
|
||||
#define MCF_PCI_PCITER_FEE (0x200000)
|
||||
#define MCF_PCI_PCITER_ME (0x1000000)
|
||||
#define MCF_PCI_PCITER_BE (0x8000000)
|
||||
#define MCF_PCI_PCITER_CM (0x10000000)
|
||||
#define MCF_PCI_PCITER_RF (0x40000000)
|
||||
#define MCF_PCI_PCITER_RC (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCITNAR */
|
||||
#define MCF_PCI_PCITNAR_NEXTADDRESS(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCITLWR */
|
||||
#define MCF_PCI_PCITLWR_LASTWORD(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCITDCR */
|
||||
#define MCF_PCI_PCITDCR_PKTSDONE(x) (((x)&0xFFFF)<<0)
|
||||
#define MCF_PCI_PCITDCR_BYTESDONE(x) (((x)&0xFFFF)<<0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCITSR */
|
||||
#define MCF_PCI_PCITSR_IA (0x10000)
|
||||
#define MCF_PCI_PCITSR_TA (0x20000)
|
||||
#define MCF_PCI_PCITSR_RE (0x40000)
|
||||
#define MCF_PCI_PCITSR_SE (0x80000)
|
||||
#define MCF_PCI_PCITSR_FE (0x100000)
|
||||
#define MCF_PCI_PCITSR_BE1 (0x200000)
|
||||
#define MCF_PCI_PCITSR_BE2 (0x400000)
|
||||
#define MCF_PCI_PCITSR_BE3 (0x800000)
|
||||
#define MCF_PCI_PCITSR_NT (0x1000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCITFDR */
|
||||
#define MCF_PCI_PCITFDR_FIFODATAWORD(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCITFSR */
|
||||
#define MCF_PCI_PCITFSR_EMPTY (0x10000)
|
||||
#define MCF_PCI_PCITFSR_ALARM (0x20000)
|
||||
#define MCF_PCI_PCITFSR_FULL (0x40000)
|
||||
#define MCF_PCI_PCITFSR_FR (0x80000)
|
||||
#define MCF_PCI_PCITFSR_OF (0x100000)
|
||||
#define MCF_PCI_PCITFSR_UF (0x200000)
|
||||
#define MCF_PCI_PCITFSR_RXW (0x400000)
|
||||
#define MCF_PCI_PCITFSR_FAE (0x800000)
|
||||
#define MCF_PCI_PCITFSR_TXW (0x40000000)
|
||||
#define MCF_PCI_PCITFSR_IP (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCITFCR */
|
||||
#define MCF_PCI_PCITFCR_TXW_MASK (0x40000)
|
||||
#define MCF_PCI_PCITFCR_OF_MASK (0x80000)
|
||||
#define MCF_PCI_PCITFCR_UF_MASK (0x100000)
|
||||
#define MCF_PCI_PCITFCR_RXW_MASK (0x200000)
|
||||
#define MCF_PCI_PCITFCR_FAE_MASK (0x400000)
|
||||
#define MCF_PCI_PCITFCR_IP_MASK (0x800000)
|
||||
#define MCF_PCI_PCITFCR_GR(x) (((x)&0x7)<<0x18)
|
||||
#define MCF_PCI_PCITFCR_WFR (0x20000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCITFAR */
|
||||
#define MCF_PCI_PCITFAR_ALARM(x) (((x)&0xFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCITFRPR */
|
||||
#define MCF_PCI_PCITFRPR_READPTR(x) (((x)&0x7F)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCITFWPR */
|
||||
#define MCF_PCI_PCITFWPR_WRITEPTR(x) (((x)&0x7F)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCIRPSR */
|
||||
#define MCF_PCI_PCIRPSR_PKTSIZE(x) (((x)&0xFFFF)<<0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCIRSAR */
|
||||
#define MCF_PCI_PCIRSAR_STARTADD(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCIRTCR */
|
||||
#define MCF_PCI_PCIRTCR_DI (0x1)
|
||||
#define MCF_PCI_PCIRTCR_W (0x10)
|
||||
#define MCF_PCI_PCIRTCR_MAXBEATS(x) (((x)&0x7)<<0x8)
|
||||
#define MCF_PCI_PCIRTCR_FB (0x1000)
|
||||
#define MCF_PCI_PCIRTCR_MAXRETRY(x) (((x)&0xFF)<<0x10)
|
||||
#define MCF_PCI_PCIRTCR_PCICMD(x) (((x)&0xF)<<0x18)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCIRER */
|
||||
#define MCF_PCI_PCIRER_NE (0x10000)
|
||||
#define MCF_PCI_PCIRER_IAE (0x20000)
|
||||
#define MCF_PCI_PCIRER_TAE (0x40000)
|
||||
#define MCF_PCI_PCIRER_RE (0x80000)
|
||||
#define MCF_PCI_PCIRER_SE (0x100000)
|
||||
#define MCF_PCI_PCIRER_FEE (0x200000)
|
||||
#define MCF_PCI_PCIRER_ME (0x1000000)
|
||||
#define MCF_PCI_PCIRER_BE (0x8000000)
|
||||
#define MCF_PCI_PCIRER_CM (0x10000000)
|
||||
#define MCF_PCI_PCIRER_FE (0x20000000)
|
||||
#define MCF_PCI_PCIRER_RF (0x40000000)
|
||||
#define MCF_PCI_PCIRER_RC (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCIRNAR */
|
||||
#define MCF_PCI_PCIRNAR_NEXTADDRESS(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCIRDCR */
|
||||
#define MCF_PCI_PCIRDCR_PKTSDONE(x) (((x)&0xFFFF)<<0)
|
||||
#define MCF_PCI_PCIRDCR_BYTESDONE(x) (((x)&0xFFFF)<<0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCIRSR */
|
||||
#define MCF_PCI_PCIRSR_IA (0x10000)
|
||||
#define MCF_PCI_PCIRSR_TA (0x20000)
|
||||
#define MCF_PCI_PCIRSR_RE (0x40000)
|
||||
#define MCF_PCI_PCIRSR_SE (0x80000)
|
||||
#define MCF_PCI_PCIRSR_FE (0x100000)
|
||||
#define MCF_PCI_PCIRSR_BE1 (0x200000)
|
||||
#define MCF_PCI_PCIRSR_BE2 (0x400000)
|
||||
#define MCF_PCI_PCIRSR_BE3 (0x800000)
|
||||
#define MCF_PCI_PCIRSR_NT (0x1000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCIRFDR */
|
||||
#define MCF_PCI_PCIRFDR_FIFODATAWORD(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCIRFSR */
|
||||
#define MCF_PCI_PCIRFSR_EMPTY (0x10000)
|
||||
#define MCF_PCI_PCIRFSR_ALARM (0x20000)
|
||||
#define MCF_PCI_PCIRFSR_FULL (0x40000)
|
||||
#define MCF_PCI_PCIRFSR_FR (0x80000)
|
||||
#define MCF_PCI_PCIRFSR_OF (0x100000)
|
||||
#define MCF_PCI_PCIRFSR_UF (0x200000)
|
||||
#define MCF_PCI_PCIRFSR_RXW (0x400000)
|
||||
#define MCF_PCI_PCIRFSR_FAE (0x800000)
|
||||
#define MCF_PCI_PCIRFSR_TXW (0x40000000)
|
||||
#define MCF_PCI_PCIRFSR_IP (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCIRFCR */
|
||||
#define MCF_PCI_PCIRFCR_TXW_MASK (0x40000)
|
||||
#define MCF_PCI_PCIRFCR_OF_MASK (0x80000)
|
||||
#define MCF_PCI_PCIRFCR_UF_MASK (0x100000)
|
||||
#define MCF_PCI_PCIRFCR_RXW_MASK (0x200000)
|
||||
#define MCF_PCI_PCIRFCR_FAE_MASK (0x400000)
|
||||
#define MCF_PCI_PCIRFCR_IP_MASK (0x800000)
|
||||
#define MCF_PCI_PCIRFCR_GR(x) (((x)&0x7)<<0x18)
|
||||
#define MCF_PCI_PCIRFCR_WFR (0x20000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCIRFAR */
|
||||
#define MCF_PCI_PCIRFAR_ALARM(x) (((x)&0x7F)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCIRFRPR */
|
||||
#define MCF_PCI_PCIRFRPR_READPTR(x) (((x)&0x7F)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCI_PCIRFWPR */
|
||||
#define MCF_PCI_PCIRFWPR_WRITEPTR(x) (((x)&0x7F)<<0)
|
||||
|
||||
|
||||
#endif /* __MCF5475_PCI_H__ */
|
||||
@@ -1,43 +0,0 @@
|
||||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.81
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF5475_PCIARB_H__
|
||||
#define __MCF5475_PCIARB_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* PCI Bus Arbiter Module (PCIARB)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_PCIARB_PACR (*(volatile uint32_t*)(&_MBAR[0xC00]))
|
||||
#define MCF_PCIARB_PASR (*(volatile uint32_t*)(&_MBAR[0xC04]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_PCIARB_PACR */
|
||||
#define MCF_PCIARB_PACR_INTMPRI (0x1)
|
||||
#define MCF_PCIARB_PACR_EXTMPRI(x) (((x)&0x1F)<<0x1)
|
||||
#define MCF_PCIARB_PACR_INTMINTEN (0x10000)
|
||||
#define MCF_PCIARB_PACR_EXTMINTEN(x) (((x)&0x1F)<<0x11)
|
||||
#define MCF_PCIARB_PACR_DS (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_PCIARB_PASR */
|
||||
#define MCF_PCIARB_PASR_ITLMBK (0x10000)
|
||||
#define MCF_PCIARB_PASR_EXTMBK(x) (((x)&0x1F)<<0x11)
|
||||
|
||||
|
||||
#endif /* __MCF5475_PCIARB_H__ */
|
||||
@@ -1,527 +0,0 @@
|
||||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.81
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF5475_PSC_H__
|
||||
#define __MCF5475_PSC_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Programmable Serial Controller (PSC)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_PSC0_PSCMR2 (*(volatile uint8_t *)(&_MBAR[0x8600]))
|
||||
#define MCF_PSC0_PSCMR1 (*(volatile uint8_t *)(&_MBAR[0x8600]))
|
||||
#define MCF_PSC0_PSCCSR (*(volatile uint8_t *)(&_MBAR[0x8604]))
|
||||
#define MCF_PSC0_PSCSR (*(volatile uint16_t*)(&_MBAR[0x8604]))
|
||||
#define MCF_PSC0_PSCCR (*(volatile uint8_t *)(&_MBAR[0x8608]))
|
||||
#define MCF_PSC0_PSCRB_8BIT (*(volatile uint32_t*)(&_MBAR[0x860C]))
|
||||
#define MCF_PSC0_PSCTB_8BIT (*(volatile uint32_t*)(&_MBAR[0x860C]))
|
||||
#define MCF_PSC0_PSCRB_16BIT (*(volatile uint32_t*)(&_MBAR[0x860C]))
|
||||
#define MCF_PSC0_PSCTB_16BIT (*(volatile uint32_t*)(&_MBAR[0x860C]))
|
||||
#define MCF_PSC0_PSCRB_AC97 (*(volatile uint32_t*)(&_MBAR[0x860C]))
|
||||
#define MCF_PSC0_PSCTB_AC97 (*(volatile uint32_t*)(&_MBAR[0x860C]))
|
||||
#define MCF_PSC0_PSCIPCR (*(volatile uint8_t *)(&_MBAR[0x8610]))
|
||||
#define MCF_PSC0_PSCACR (*(volatile uint8_t *)(&_MBAR[0x8610]))
|
||||
#define MCF_PSC0_PSCIMR (*(volatile uint16_t*)(&_MBAR[0x8614]))
|
||||
#define MCF_PSC0_PSCISR (*(volatile uint16_t*)(&_MBAR[0x8614]))
|
||||
#define MCF_PSC0_PSCCTUR (*(volatile uint8_t *)(&_MBAR[0x8618]))
|
||||
#define MCF_PSC0_PSCCTLR (*(volatile uint8_t *)(&_MBAR[0x861C]))
|
||||
#define MCF_PSC0_PSCIP (*(volatile uint8_t *)(&_MBAR[0x8634]))
|
||||
#define MCF_PSC0_PSCOPSET (*(volatile uint8_t *)(&_MBAR[0x8638]))
|
||||
#define MCF_PSC0_PSCOPRESET (*(volatile uint8_t *)(&_MBAR[0x863C]))
|
||||
#define MCF_PSC0_PSCSICR (*(volatile uint8_t *)(&_MBAR[0x8640]))
|
||||
#define MCF_PSC0_PSCIRCR1 (*(volatile uint8_t *)(&_MBAR[0x8644]))
|
||||
#define MCF_PSC0_PSCIRCR2 (*(volatile uint8_t *)(&_MBAR[0x8648]))
|
||||
#define MCF_PSC0_PSCIRSDR (*(volatile uint8_t *)(&_MBAR[0x864C]))
|
||||
#define MCF_PSC0_PSCIRMDR (*(volatile uint8_t *)(&_MBAR[0x8650]))
|
||||
#define MCF_PSC0_PSCIRFDR (*(volatile uint8_t *)(&_MBAR[0x8654]))
|
||||
#define MCF_PSC0_PSCRFCNT (*(volatile uint16_t*)(&_MBAR[0x8658]))
|
||||
#define MCF_PSC0_PSCTFCNT (*(volatile uint16_t*)(&_MBAR[0x865C]))
|
||||
#define MCF_PSC0_PSCRFDR (*(volatile uint32_t*)(&_MBAR[0x8660]))
|
||||
#define MCF_PSC0_PSCRFSR (*(volatile uint16_t*)(&_MBAR[0x8664]))
|
||||
#define MCF_PSC0_PSCRFCR (*(volatile uint32_t*)(&_MBAR[0x8668]))
|
||||
#define MCF_PSC0_PSCRFAR (*(volatile uint16_t*)(&_MBAR[0x866E]))
|
||||
#define MCF_PSC0_PSCRFRP (*(volatile uint16_t*)(&_MBAR[0x8672]))
|
||||
#define MCF_PSC0_PSCRFWP (*(volatile uint16_t*)(&_MBAR[0x8676]))
|
||||
#define MCF_PSC0_PSCRLRFP (*(volatile uint16_t*)(&_MBAR[0x867A]))
|
||||
#define MCF_PSC0_PSCRLWFP (*(volatile uint16_t*)(&_MBAR[0x867E]))
|
||||
#define MCF_PSC0_PSCTFDR (*(volatile uint32_t*)(&_MBAR[0x8680]))
|
||||
#define MCF_PSC0_PSCTFSR (*(volatile uint16_t*)(&_MBAR[0x8684]))
|
||||
#define MCF_PSC0_PSCTFCR (*(volatile uint32_t*)(&_MBAR[0x8688]))
|
||||
#define MCF_PSC0_PSCTFAR (*(volatile uint16_t*)(&_MBAR[0x868E]))
|
||||
#define MCF_PSC0_PSCTFRP (*(volatile uint16_t*)(&_MBAR[0x8692]))
|
||||
#define MCF_PSC0_PSCTFWP (*(volatile uint16_t*)(&_MBAR[0x8696]))
|
||||
#define MCF_PSC0_PSCTLRFP (*(volatile uint16_t*)(&_MBAR[0x869A]))
|
||||
#define MCF_PSC0_PSCTLWFP (*(volatile uint16_t*)(&_MBAR[0x869E]))
|
||||
|
||||
#define MCF_PSC1_PSCMR2 (*(volatile uint8_t *)(&_MBAR[0x8700]))
|
||||
#define MCF_PSC1_PSCMR1 (*(volatile uint8_t *)(&_MBAR[0x8700]))
|
||||
#define MCF_PSC1_PSCCSR (*(volatile uint8_t *)(&_MBAR[0x8704]))
|
||||
#define MCF_PSC1_PSCSR (*(volatile uint16_t*)(&_MBAR[0x8704]))
|
||||
#define MCF_PSC1_PSCCR (*(volatile uint8_t *)(&_MBAR[0x8708]))
|
||||
#define MCF_PSC1_PSCRB_8BIT (*(volatile uint32_t*)(&_MBAR[0x870C]))
|
||||
#define MCF_PSC1_PSCTB_8BIT (*(volatile uint32_t*)(&_MBAR[0x870C]))
|
||||
#define MCF_PSC1_PSCRB_16BIT (*(volatile uint32_t*)(&_MBAR[0x870C]))
|
||||
#define MCF_PSC1_PSCTB_16BIT (*(volatile uint32_t*)(&_MBAR[0x870C]))
|
||||
#define MCF_PSC1_PSCRB_AC97 (*(volatile uint32_t*)(&_MBAR[0x870C]))
|
||||
#define MCF_PSC1_PSCTB_AC97 (*(volatile uint32_t*)(&_MBAR[0x870C]))
|
||||
#define MCF_PSC1_PSCIPCR (*(volatile uint8_t *)(&_MBAR[0x8710]))
|
||||
#define MCF_PSC1_PSCACR (*(volatile uint8_t *)(&_MBAR[0x8710]))
|
||||
#define MCF_PSC1_PSCIMR (*(volatile uint16_t*)(&_MBAR[0x8714]))
|
||||
#define MCF_PSC1_PSCISR (*(volatile uint16_t*)(&_MBAR[0x8714]))
|
||||
#define MCF_PSC1_PSCCTUR (*(volatile uint8_t *)(&_MBAR[0x8718]))
|
||||
#define MCF_PSC1_PSCCTLR (*(volatile uint8_t *)(&_MBAR[0x871C]))
|
||||
#define MCF_PSC1_PSCIP (*(volatile uint8_t *)(&_MBAR[0x8734]))
|
||||
#define MCF_PSC1_PSCOPSET (*(volatile uint8_t *)(&_MBAR[0x8738]))
|
||||
#define MCF_PSC1_PSCOPRESET (*(volatile uint8_t *)(&_MBAR[0x873C]))
|
||||
#define MCF_PSC1_PSCSICR (*(volatile uint8_t *)(&_MBAR[0x8740]))
|
||||
#define MCF_PSC1_PSCIRCR1 (*(volatile uint8_t *)(&_MBAR[0x8744]))
|
||||
#define MCF_PSC1_PSCIRCR2 (*(volatile uint8_t *)(&_MBAR[0x8748]))
|
||||
#define MCF_PSC1_PSCIRSDR (*(volatile uint8_t *)(&_MBAR[0x874C]))
|
||||
#define MCF_PSC1_PSCIRMDR (*(volatile uint8_t *)(&_MBAR[0x8750]))
|
||||
#define MCF_PSC1_PSCIRFDR (*(volatile uint8_t *)(&_MBAR[0x8754]))
|
||||
#define MCF_PSC1_PSCRFCNT (*(volatile uint16_t*)(&_MBAR[0x8758]))
|
||||
#define MCF_PSC1_PSCTFCNT (*(volatile uint16_t*)(&_MBAR[0x875C]))
|
||||
#define MCF_PSC1_PSCRFDR (*(volatile uint32_t*)(&_MBAR[0x8760]))
|
||||
#define MCF_PSC1_PSCRFSR (*(volatile uint16_t*)(&_MBAR[0x8764]))
|
||||
#define MCF_PSC1_PSCRFCR (*(volatile uint32_t*)(&_MBAR[0x8768]))
|
||||
#define MCF_PSC1_PSCRFAR (*(volatile uint16_t*)(&_MBAR[0x876E]))
|
||||
#define MCF_PSC1_PSCRFRP (*(volatile uint16_t*)(&_MBAR[0x8772]))
|
||||
#define MCF_PSC1_PSCRFWP (*(volatile uint16_t*)(&_MBAR[0x8776]))
|
||||
#define MCF_PSC1_PSCRLRFP (*(volatile uint16_t*)(&_MBAR[0x877A]))
|
||||
#define MCF_PSC1_PSCRLWFP (*(volatile uint16_t*)(&_MBAR[0x877E]))
|
||||
#define MCF_PSC1_PSCTFDR (*(volatile uint32_t*)(&_MBAR[0x8780]))
|
||||
#define MCF_PSC1_PSCTFSR (*(volatile uint16_t*)(&_MBAR[0x8784]))
|
||||
#define MCF_PSC1_PSCTFCR (*(volatile uint32_t*)(&_MBAR[0x8788]))
|
||||
#define MCF_PSC1_PSCTFAR (*(volatile uint16_t*)(&_MBAR[0x878E]))
|
||||
#define MCF_PSC1_PSCTFRP (*(volatile uint16_t*)(&_MBAR[0x8792]))
|
||||
#define MCF_PSC1_PSCTFWP (*(volatile uint16_t*)(&_MBAR[0x8796]))
|
||||
#define MCF_PSC1_PSCTLRFP (*(volatile uint16_t*)(&_MBAR[0x879A]))
|
||||
#define MCF_PSC1_PSCTLWFP (*(volatile uint16_t*)(&_MBAR[0x879E]))
|
||||
|
||||
#define MCF_PSC2_PSCMR2 (*(volatile uint8_t *)(&_MBAR[0x8800]))
|
||||
#define MCF_PSC2_PSCMR1 (*(volatile uint8_t *)(&_MBAR[0x8800]))
|
||||
#define MCF_PSC2_PSCCSR (*(volatile uint8_t *)(&_MBAR[0x8804]))
|
||||
#define MCF_PSC2_PSCSR (*(volatile uint16_t*)(&_MBAR[0x8804]))
|
||||
#define MCF_PSC2_PSCCR (*(volatile uint8_t *)(&_MBAR[0x8808]))
|
||||
#define MCF_PSC2_PSCRB_8BIT (*(volatile uint32_t*)(&_MBAR[0x880C]))
|
||||
#define MCF_PSC2_PSCTB_8BIT (*(volatile uint32_t*)(&_MBAR[0x880C]))
|
||||
#define MCF_PSC2_PSCRB_16BIT (*(volatile uint32_t*)(&_MBAR[0x880C]))
|
||||
#define MCF_PSC2_PSCTB_16BIT (*(volatile uint32_t*)(&_MBAR[0x880C]))
|
||||
#define MCF_PSC2_PSCRB_AC97 (*(volatile uint32_t*)(&_MBAR[0x880C]))
|
||||
#define MCF_PSC2_PSCTB_AC97 (*(volatile uint32_t*)(&_MBAR[0x880C]))
|
||||
#define MCF_PSC2_PSCIPCR (*(volatile uint8_t *)(&_MBAR[0x8810]))
|
||||
#define MCF_PSC2_PSCACR (*(volatile uint8_t *)(&_MBAR[0x8810]))
|
||||
#define MCF_PSC2_PSCIMR (*(volatile uint16_t*)(&_MBAR[0x8814]))
|
||||
#define MCF_PSC2_PSCISR (*(volatile uint16_t*)(&_MBAR[0x8814]))
|
||||
#define MCF_PSC2_PSCCTUR (*(volatile uint8_t *)(&_MBAR[0x8818]))
|
||||
#define MCF_PSC2_PSCCTLR (*(volatile uint8_t *)(&_MBAR[0x881C]))
|
||||
#define MCF_PSC2_PSCIP (*(volatile uint8_t *)(&_MBAR[0x8834]))
|
||||
#define MCF_PSC2_PSCOPSET (*(volatile uint8_t *)(&_MBAR[0x8838]))
|
||||
#define MCF_PSC2_PSCOPRESET (*(volatile uint8_t *)(&_MBAR[0x883C]))
|
||||
#define MCF_PSC2_PSCSICR (*(volatile uint8_t *)(&_MBAR[0x8840]))
|
||||
#define MCF_PSC2_PSCIRCR1 (*(volatile uint8_t *)(&_MBAR[0x8844]))
|
||||
#define MCF_PSC2_PSCIRCR2 (*(volatile uint8_t *)(&_MBAR[0x8848]))
|
||||
#define MCF_PSC2_PSCIRSDR (*(volatile uint8_t *)(&_MBAR[0x884C]))
|
||||
#define MCF_PSC2_PSCIRMDR (*(volatile uint8_t *)(&_MBAR[0x8850]))
|
||||
#define MCF_PSC2_PSCIRFDR (*(volatile uint8_t *)(&_MBAR[0x8854]))
|
||||
#define MCF_PSC2_PSCRFCNT (*(volatile uint16_t*)(&_MBAR[0x8858]))
|
||||
#define MCF_PSC2_PSCTFCNT (*(volatile uint16_t*)(&_MBAR[0x885C]))
|
||||
#define MCF_PSC2_PSCRFDR (*(volatile uint32_t*)(&_MBAR[0x8860]))
|
||||
#define MCF_PSC2_PSCRFSR (*(volatile uint16_t*)(&_MBAR[0x8864]))
|
||||
#define MCF_PSC2_PSCRFCR (*(volatile uint32_t*)(&_MBAR[0x8868]))
|
||||
#define MCF_PSC2_PSCRFAR (*(volatile uint16_t*)(&_MBAR[0x886E]))
|
||||
#define MCF_PSC2_PSCRFRP (*(volatile uint16_t*)(&_MBAR[0x8872]))
|
||||
#define MCF_PSC2_PSCRFWP (*(volatile uint16_t*)(&_MBAR[0x8876]))
|
||||
#define MCF_PSC2_PSCRLRFP (*(volatile uint16_t*)(&_MBAR[0x887A]))
|
||||
#define MCF_PSC2_PSCRLWFP (*(volatile uint16_t*)(&_MBAR[0x887E]))
|
||||
#define MCF_PSC2_PSCTFDR (*(volatile uint32_t*)(&_MBAR[0x8880]))
|
||||
#define MCF_PSC2_PSCTFSR (*(volatile uint16_t*)(&_MBAR[0x8884]))
|
||||
#define MCF_PSC2_PSCTFCR (*(volatile uint32_t*)(&_MBAR[0x8888]))
|
||||
#define MCF_PSC2_PSCTFAR (*(volatile uint16_t*)(&_MBAR[0x888E]))
|
||||
#define MCF_PSC2_PSCTFRP (*(volatile uint16_t*)(&_MBAR[0x8892]))
|
||||
#define MCF_PSC2_PSCTFWP (*(volatile uint16_t*)(&_MBAR[0x8896]))
|
||||
#define MCF_PSC2_PSCTLRFP (*(volatile uint16_t*)(&_MBAR[0x889A]))
|
||||
#define MCF_PSC2_PSCTLWFP (*(volatile uint16_t*)(&_MBAR[0x889E]))
|
||||
|
||||
#define MCF_PSC3_PSCMR2 (*(volatile uint8_t *)(&_MBAR[0x8900]))
|
||||
#define MCF_PSC3_PSCMR1 (*(volatile uint8_t *)(&_MBAR[0x8900]))
|
||||
#define MCF_PSC3_PSCCSR (*(volatile uint8_t *)(&_MBAR[0x8904]))
|
||||
#define MCF_PSC3_PSCSR (*(volatile uint16_t*)(&_MBAR[0x8904]))
|
||||
#define MCF_PSC3_PSCCR (*(volatile uint8_t *)(&_MBAR[0x8908]))
|
||||
#define MCF_PSC3_PSCRB_8BIT (*(volatile uint32_t*)(&_MBAR[0x890C]))
|
||||
#define MCF_PSC3_PSCTB_8BIT (*(volatile uint32_t*)(&_MBAR[0x890C]))
|
||||
#define MCF_PSC3_PSCRB_16BIT (*(volatile uint32_t*)(&_MBAR[0x890C]))
|
||||
#define MCF_PSC3_PSCTB_16BIT (*(volatile uint32_t*)(&_MBAR[0x890C]))
|
||||
#define MCF_PSC3_PSCRB_AC97 (*(volatile uint32_t*)(&_MBAR[0x890C]))
|
||||
#define MCF_PSC3_PSCTB_AC97 (*(volatile uint32_t*)(&_MBAR[0x890C]))
|
||||
#define MCF_PSC3_PSCIPCR (*(volatile uint8_t *)(&_MBAR[0x8910]))
|
||||
#define MCF_PSC3_PSCACR (*(volatile uint8_t *)(&_MBAR[0x8910]))
|
||||
#define MCF_PSC3_PSCIMR (*(volatile uint16_t*)(&_MBAR[0x8914]))
|
||||
#define MCF_PSC3_PSCISR (*(volatile uint16_t*)(&_MBAR[0x8914]))
|
||||
#define MCF_PSC3_PSCCTUR (*(volatile uint8_t *)(&_MBAR[0x8918]))
|
||||
#define MCF_PSC3_PSCCTLR (*(volatile uint8_t *)(&_MBAR[0x891C]))
|
||||
#define MCF_PSC3_PSCIP (*(volatile uint8_t *)(&_MBAR[0x8934]))
|
||||
#define MCF_PSC3_PSCOPSET (*(volatile uint8_t *)(&_MBAR[0x8938]))
|
||||
#define MCF_PSC3_PSCOPRESET (*(volatile uint8_t *)(&_MBAR[0x893C]))
|
||||
#define MCF_PSC3_PSCSICR (*(volatile uint8_t *)(&_MBAR[0x8940]))
|
||||
#define MCF_PSC3_PSCIRCR1 (*(volatile uint8_t *)(&_MBAR[0x8944]))
|
||||
#define MCF_PSC3_PSCIRCR2 (*(volatile uint8_t *)(&_MBAR[0x8948]))
|
||||
#define MCF_PSC3_PSCIRSDR (*(volatile uint8_t *)(&_MBAR[0x894C]))
|
||||
#define MCF_PSC3_PSCIRMDR (*(volatile uint8_t *)(&_MBAR[0x8950]))
|
||||
#define MCF_PSC3_PSCIRFDR (*(volatile uint8_t *)(&_MBAR[0x8954]))
|
||||
#define MCF_PSC3_PSCRFCNT (*(volatile uint16_t*)(&_MBAR[0x8958]))
|
||||
#define MCF_PSC3_PSCTFCNT (*(volatile uint16_t*)(&_MBAR[0x895C]))
|
||||
#define MCF_PSC3_PSCRFDR (*(volatile uint32_t*)(&_MBAR[0x8960]))
|
||||
#define MCF_PSC3_PSCRFSR (*(volatile uint16_t*)(&_MBAR[0x8964]))
|
||||
#define MCF_PSC3_PSCRFCR (*(volatile uint32_t*)(&_MBAR[0x8968]))
|
||||
#define MCF_PSC3_PSCRFAR (*(volatile uint16_t*)(&_MBAR[0x896E]))
|
||||
#define MCF_PSC3_PSCRFRP (*(volatile uint16_t*)(&_MBAR[0x8972]))
|
||||
#define MCF_PSC3_PSCRFWP (*(volatile uint16_t*)(&_MBAR[0x8976]))
|
||||
#define MCF_PSC3_PSCRLRFP (*(volatile uint16_t*)(&_MBAR[0x897A]))
|
||||
#define MCF_PSC3_PSCRLWFP (*(volatile uint16_t*)(&_MBAR[0x897E]))
|
||||
#define MCF_PSC3_PSCTFDR (*(volatile uint32_t*)(&_MBAR[0x8980]))
|
||||
#define MCF_PSC3_PSCTFSR (*(volatile uint16_t*)(&_MBAR[0x8984]))
|
||||
#define MCF_PSC3_PSCTFCR (*(volatile uint32_t*)(&_MBAR[0x8988]))
|
||||
#define MCF_PSC3_PSCTFAR (*(volatile uint16_t*)(&_MBAR[0x898E]))
|
||||
#define MCF_PSC3_PSCTFRP (*(volatile uint16_t*)(&_MBAR[0x8992]))
|
||||
#define MCF_PSC3_PSCTFWP (*(volatile uint16_t*)(&_MBAR[0x8996]))
|
||||
#define MCF_PSC3_PSCTLRFP (*(volatile uint16_t*)(&_MBAR[0x899A]))
|
||||
#define MCF_PSC3_PSCTLWFP (*(volatile uint16_t*)(&_MBAR[0x899E]))
|
||||
|
||||
#define MCF_PSC_PSCMR(x) (*(volatile uint8_t *)(&_MBAR[0x8600 + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCCSR(x) (*(volatile uint8_t *)(&_MBAR[0x8604 + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCSR(x) (*(volatile uint16_t*)(&_MBAR[0x8604 + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCCR(x) (*(volatile uint8_t *)(&_MBAR[0x8608 + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCRB_8BIT(x) (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCTB_8BIT(x) (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCRB_16BIT(x) (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCTB_16BIT(x) (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCRB_AC97(x) (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCTB_AC97(x) (*(volatile uint32_t*)(&_MBAR[0x860C + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCIPCR(x) (*(volatile uint8_t *)(&_MBAR[0x8610 + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCACR(x) (*(volatile uint8_t *)(&_MBAR[0x8610 + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCIMR(x) (*(volatile uint16_t*)(&_MBAR[0x8614 + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCISR(x) (*(volatile uint16_t*)(&_MBAR[0x8614 + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCCTUR(x) (*(volatile uint8_t *)(&_MBAR[0x8618 + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCCTLR(x) (*(volatile uint8_t *)(&_MBAR[0x861C + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCIP(x) (*(volatile uint8_t *)(&_MBAR[0x8634 + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCOPSET(x) (*(volatile uint8_t *)(&_MBAR[0x8638 + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCOPRESET(x) (*(volatile uint8_t *)(&_MBAR[0x863C + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCSICR(x) (*(volatile uint8_t *)(&_MBAR[0x8640 + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCIRCR1(x) (*(volatile uint8_t *)(&_MBAR[0x8644 + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCIRCR2(x) (*(volatile uint8_t *)(&_MBAR[0x8648 + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCIRSDR(x) (*(volatile uint8_t *)(&_MBAR[0x864C + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCIRMDR(x) (*(volatile uint8_t *)(&_MBAR[0x8650 + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCIRFDR(x) (*(volatile uint8_t *)(&_MBAR[0x8654 + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCRFCNT(x) (*(volatile uint16_t*)(&_MBAR[0x8658 + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCTFCNT(x) (*(volatile uint16_t*)(&_MBAR[0x865C + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCRFDR(x) (*(volatile uint32_t*)(&_MBAR[0x8660 + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCRFSR(x) (*(volatile uint16_t*)(&_MBAR[0x8664 + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCRFCR(x) (*(volatile uint32_t*)(&_MBAR[0x8668 + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCRFAR(x) (*(volatile uint16_t*)(&_MBAR[0x866E + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCRFRP(x) (*(volatile uint16_t*)(&_MBAR[0x8672 + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCRFWP(x) (*(volatile uint16_t*)(&_MBAR[0x8676 + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCRLRFP(x) (*(volatile uint16_t*)(&_MBAR[0x867A + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCRLWFP(x) (*(volatile uint16_t*)(&_MBAR[0x867E + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCTFDR(x) (*(volatile uint32_t*)(&_MBAR[0x8680 + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCTFSR(x) (*(volatile uint16_t*)(&_MBAR[0x8684 + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCTFCR(x) (*(volatile uint32_t*)(&_MBAR[0x8688 + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCTFAR(x) (*(volatile uint16_t*)(&_MBAR[0x868E + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCTFRP(x) (*(volatile uint16_t*)(&_MBAR[0x8692 + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCTFWP(x) (*(volatile uint16_t*)(&_MBAR[0x8696 + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCTLRFP(x) (*(volatile uint16_t*)(&_MBAR[0x869A + ((x)*0x100)]))
|
||||
#define MCF_PSC_PSCTLWFP(x) (*(volatile uint16_t*)(&_MBAR[0x869E + ((x)*0x100)]))
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCMR */
|
||||
#define MCF_PSC_PSCMR_SB(x) (((x)&0xF)<<0)
|
||||
#define MCF_PSC_PSCMR_TXCTS (0x10)
|
||||
#define MCF_PSC_PSCMR_TXRTS (0x20)
|
||||
#define MCF_PSC_PSCMR_CM(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_PSC_PSCMR_CM_NORMAL (0)
|
||||
#define MCF_PSC_PSCMR_CM_ECHO (0x40)
|
||||
#define MCF_PSC_PSCMR_CM_LOCAL_LOOP (0x80)
|
||||
#define MCF_PSC_PSCMR_CM_REMOTE_LOOP (0xC0)
|
||||
#define MCF_PSC_PSCMR_SB_STOP_BITS_1 (0x7)
|
||||
#define MCF_PSC_PSCMR_SB_STOP_BITS_15 (0x8)
|
||||
#define MCF_PSC_PSCMR_SB_STOP_BITS_2 (0xF)
|
||||
#define MCF_PSC_PSCMR_PM_MULTI_ADDR (0x1C)
|
||||
#define MCF_PSC_PSCMR_PM_MULTI_DATA (0x18)
|
||||
#define MCF_PSC_PSCMR_PM_NONE (0x10)
|
||||
#define MCF_PSC_PSCMR_PM_FORCE_HI (0xC)
|
||||
#define MCF_PSC_PSCMR_PM_FORCE_LO (0x8)
|
||||
#define MCF_PSC_PSCMR_PM_ODD (0x4)
|
||||
#define MCF_PSC_PSCMR_PM_EVEN (0)
|
||||
#define MCF_PSC_PSCMR_BC(x) (((x)&0x3)<<0)
|
||||
#define MCF_PSC_PSCMR_BC_5 (0)
|
||||
#define MCF_PSC_PSCMR_BC_6 (0x1)
|
||||
#define MCF_PSC_PSCMR_BC_7 (0x2)
|
||||
#define MCF_PSC_PSCMR_BC_8 (0x3)
|
||||
#define MCF_PSC_PSCMR_PT (0x4)
|
||||
#define MCF_PSC_PSCMR_PM(x) (((x)&0x3)<<0x3)
|
||||
#define MCF_PSC_PSCMR_ERR (0x20)
|
||||
#define MCF_PSC_PSCMR_RXIRQ_FU (0x40)
|
||||
#define MCF_PSC_PSCMR_RXRTS (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCCSR */
|
||||
#define MCF_PSC_PSCCSR_TCSEL(x) (((x)&0xF)<<0)
|
||||
#define MCF_PSC_PSCCSR_RCSEL(x) (((x)&0xF)<<0x4)
|
||||
#define MCF_PSC_PSCCSR_TCSEL_SYS_CLK (0x0D)
|
||||
#define MCF_PSC_PSCCSR_TCSEL_CTM16 (0x0E)
|
||||
#define MCF_PSC_PSCCSR_TCSEL_CTM (0x0F)
|
||||
#define MCF_PSC_PSCCSR_RCSEL_SYS_CLK (0xD0)
|
||||
#define MCF_PSC_PSCCSR_RCSEL_CTM16 (0xE0)
|
||||
#define MCF_PSC_PSCCSR_RCSEL_CTM (0xF0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCSR */
|
||||
#define MCF_PSC_PSCSR_ERR (0x40)
|
||||
#define MCF_PSC_PSCSR_CDE_DEOF (0x80)
|
||||
#define MCF_PSC_PSCSR_RXRDY (0x100)
|
||||
#define MCF_PSC_PSCSR_FU (0x200)
|
||||
#define MCF_PSC_PSCSR_TXRDY (0x400)
|
||||
#define MCF_PSC_PSCSR_TXEMP_URERR (0x800)
|
||||
#define MCF_PSC_PSCSR_OE (0x1000)
|
||||
#define MCF_PSC_PSCSR_PE_CRCERR (0x2000)
|
||||
#define MCF_PSC_PSCSR_FE_PHYERR (0x4000)
|
||||
#define MCF_PSC_PSCSR_RB_NEOF (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCCR */
|
||||
#define MCF_PSC_PSCCR_RXC(x) (((x)&0x3)<<0)
|
||||
#define MCF_PSC_PSCCR_RX_ENABLED (0x1)
|
||||
#define MCF_PSC_PSCCR_RX_DISABLED (0x2)
|
||||
#define MCF_PSC_PSCCR_TXC(x) (((x)&0x3)<<0x2)
|
||||
#define MCF_PSC_PSCCR_TX_ENABLED (0x4)
|
||||
#define MCF_PSC_PSCCR_TX_DISABLED (0x8)
|
||||
#define MCF_PSC_PSCCR_MISC(x) (((x)&0x7)<<0x4)
|
||||
#define MCF_PSC_PSCCR_NONE (0)
|
||||
#define MCF_PSC_PSCCR_RESET_MR (0x10)
|
||||
#define MCF_PSC_PSCCR_RESET_RX (0x20)
|
||||
#define MCF_PSC_PSCCR_RESET_TX (0x30)
|
||||
#define MCF_PSC_PSCCR_RESET_ERROR (0x40)
|
||||
#define MCF_PSC_PSCCR_RESET_BKCHGINT (0x50)
|
||||
#define MCF_PSC_PSCCR_START_BREAK (0x60)
|
||||
#define MCF_PSC_PSCCR_STOP_BREAK (0x70)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCRB_8BIT */
|
||||
#define MCF_PSC_PSCRB_8BIT_RB3(x) (((x)&0xFF)<<0)
|
||||
#define MCF_PSC_PSCRB_8BIT_RB2(x) (((x)&0xFF)<<0x8)
|
||||
#define MCF_PSC_PSCRB_8BIT_RB1(x) (((x)&0xFF)<<0x10)
|
||||
#define MCF_PSC_PSCRB_8BIT_RB0(x) (((x)&0xFF)<<0x18)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCTB_8BIT */
|
||||
#define MCF_PSC_PSCTB_8BIT_TB3(x) (((x)&0xFF)<<0)
|
||||
#define MCF_PSC_PSCTB_8BIT_TB2(x) (((x)&0xFF)<<0x8)
|
||||
#define MCF_PSC_PSCTB_8BIT_TB1(x) (((x)&0xFF)<<0x10)
|
||||
#define MCF_PSC_PSCTB_8BIT_TB0(x) (((x)&0xFF)<<0x18)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCRB_16BIT */
|
||||
#define MCF_PSC_PSCRB_16BIT_RB1(x) (((x)&0xFFFF)<<0)
|
||||
#define MCF_PSC_PSCRB_16BIT_RB0(x) (((x)&0xFFFF)<<0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCTB_16BIT */
|
||||
#define MCF_PSC_PSCTB_16BIT_TB1(x) (((x)&0xFFFF)<<0)
|
||||
#define MCF_PSC_PSCTB_16BIT_TB0(x) (((x)&0xFFFF)<<0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCRB_AC97 */
|
||||
#define MCF_PSC_PSCRB_AC97_SOF (0x800)
|
||||
#define MCF_PSC_PSCRB_AC97_RB(x) (((x)&0xFFFFF)<<0xC)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCTB_AC97 */
|
||||
#define MCF_PSC_PSCTB_AC97_TB(x) (((x)&0xFFFFF)<<0xC)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCIPCR */
|
||||
#define MCF_PSC_PSCIPCR_RESERVED (0xC)
|
||||
#define MCF_PSC_PSCIPCR_CTS (0xD)
|
||||
#define MCF_PSC_PSCIPCR_D_CTS (0x1C)
|
||||
#define MCF_PSC_PSCIPCR_SYNC (0x8C)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCACR */
|
||||
#define MCF_PSC_PSCACR_IEC0 (0x1)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCIMR */
|
||||
#define MCF_PSC_PSCIMR_ERR (0x40)
|
||||
#define MCF_PSC_PSCIMR_DEOF (0x80)
|
||||
#define MCF_PSC_PSCIMR_TXRDY (0x100)
|
||||
#define MCF_PSC_PSCIMR_RXRDY_FU (0x200)
|
||||
#define MCF_PSC_PSCIMR_DB (0x400)
|
||||
#define MCF_PSC_PSCIMR_IPC (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCISR */
|
||||
#define MCF_PSC_PSCISR_ERR (0x40)
|
||||
#define MCF_PSC_PSCISR_DEOF (0x80)
|
||||
#define MCF_PSC_PSCISR_TXRDY (0x100)
|
||||
#define MCF_PSC_PSCISR_RXRDY_FU (0x200)
|
||||
#define MCF_PSC_PSCISR_DB (0x400)
|
||||
#define MCF_PSC_PSCISR_IPC (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCCTUR */
|
||||
#define MCF_PSC_PSCCTUR_CT(x) (((x)&0xFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCCTLR */
|
||||
#define MCF_PSC_PSCCTLR_CT(x) (((x)&0xFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCIP */
|
||||
#define MCF_PSC_PSCIP_CTS (0x1)
|
||||
#define MCF_PSC_PSCIP_TGL (0x40)
|
||||
#define MCF_PSC_PSCIP_LPWR_B (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCOPSET */
|
||||
#define MCF_PSC_PSCOPSET_RTS (0x1)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCOPRESET */
|
||||
#define MCF_PSC_PSCOPRESET_RTS (0x1)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCSICR */
|
||||
#define MCF_PSC_PSCSICR_SIM(x) (((x)&0x7)<<0)
|
||||
#define MCF_PSC_PSCSICR_SIM_UART (0)
|
||||
#define MCF_PSC_PSCSICR_SIM_MODEM8 (0x1)
|
||||
#define MCF_PSC_PSCSICR_SIM_MODEM16 (0x2)
|
||||
#define MCF_PSC_PSCSICR_SIM_AC97 (0x3)
|
||||
#define MCF_PSC_PSCSICR_SIM_SIR (0x4)
|
||||
#define MCF_PSC_PSCSICR_SIM_MIR (0x5)
|
||||
#define MCF_PSC_PSCSICR_SIM_FIR (0x6)
|
||||
#define MCF_PSC_PSCSICR_SHDIR (0x10)
|
||||
#define MCF_PSC_PSCSICR_DTS1 (0x20)
|
||||
#define MCF_PSC_PSCSICR_AWR (0x40)
|
||||
#define MCF_PSC_PSCSICR_ACRB (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCIRCR1 */
|
||||
#define MCF_PSC_PSCIRCR1_SPUL (0x1)
|
||||
#define MCF_PSC_PSCIRCR1_SIPEN (0x2)
|
||||
#define MCF_PSC_PSCIRCR1_FD (0x4)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCIRCR2 */
|
||||
#define MCF_PSC_PSCIRCR2_NXTEOF (0x1)
|
||||
#define MCF_PSC_PSCIRCR2_ABORT (0x2)
|
||||
#define MCF_PSC_PSCIRCR2_SIPREQ (0x4)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCIRSDR */
|
||||
#define MCF_PSC_PSCIRSDR_IRSTIM(x) (((x)&0xFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCIRMDR */
|
||||
#define MCF_PSC_PSCIRMDR_M_FDIV(x) (((x)&0x7F)<<0)
|
||||
#define MCF_PSC_PSCIRMDR_FREQ (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCIRFDR */
|
||||
#define MCF_PSC_PSCIRFDR_F_FDIV(x) (((x)&0xF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCRFCNT */
|
||||
#define MCF_PSC_PSCRFCNT_CNT(x) (((x)&0x1FF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCTFCNT */
|
||||
#define MCF_PSC_PSCTFCNT_CNT(x) (((x)&0x1FF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCRFDR */
|
||||
#define MCF_PSC_PSCRFDR_DATA(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCRFSR */
|
||||
#define MCF_PSC_PSCRFSR_EMT (0x1)
|
||||
#define MCF_PSC_PSCRFSR_ALARM (0x2)
|
||||
#define MCF_PSC_PSCRFSR_FU (0x4)
|
||||
#define MCF_PSC_PSCRFSR_FRMRDY (0x8)
|
||||
#define MCF_PSC_PSCRFSR_OF (0x10)
|
||||
#define MCF_PSC_PSCRFSR_UF (0x20)
|
||||
#define MCF_PSC_PSCRFSR_RXW (0x40)
|
||||
#define MCF_PSC_PSCRFSR_FAE (0x80)
|
||||
#define MCF_PSC_PSCRFSR_FRM(x) (((x)&0xF)<<0x8)
|
||||
#define MCF_PSC_PSCRFSR_FRM_BYTE0 (0x800)
|
||||
#define MCF_PSC_PSCRFSR_FRM_BYTE1 (0x400)
|
||||
#define MCF_PSC_PSCRFSR_FRM_BYTE2 (0x200)
|
||||
#define MCF_PSC_PSCRFSR_FRM_BYTE3 (0x100)
|
||||
#define MCF_PSC_PSCRFSR_TAG(x) (((x)&0x3)<<0xC)
|
||||
#define MCF_PSC_PSCRFSR_TXW (0x4000)
|
||||
#define MCF_PSC_PSCRFSR_IP (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCRFCR */
|
||||
#define MCF_PSC_PSCRFCR_CNTR(x) (((x)&0xFFFF)<<0)
|
||||
#define MCF_PSC_PSCRFCR_TXW_MSK (0x40000)
|
||||
#define MCF_PSC_PSCRFCR_OF_MSK (0x80000)
|
||||
#define MCF_PSC_PSCRFCR_UF_MSK (0x100000)
|
||||
#define MCF_PSC_PSCRFCR_RXW_MSK (0x200000)
|
||||
#define MCF_PSC_PSCRFCR_FAE_MSK (0x400000)
|
||||
#define MCF_PSC_PSCRFCR_IP_MSK (0x800000)
|
||||
#define MCF_PSC_PSCRFCR_GR(x) (((x)&0x7)<<0x18)
|
||||
#define MCF_PSC_PSCRFCR_FRMEN (0x8000000)
|
||||
#define MCF_PSC_PSCRFCR_TIMER (0x10000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCRFAR */
|
||||
#define MCF_PSC_PSCRFAR_ALARM(x) (((x)&0x1FF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCRFRP */
|
||||
#define MCF_PSC_PSCRFRP_READ(x) (((x)&0x1FF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCRFWP */
|
||||
#define MCF_PSC_PSCRFWP_WRITE(x) (((x)&0x1FF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCRLRFP */
|
||||
#define MCF_PSC_PSCRLRFP_LRFP(x) (((x)&0x1FF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCRLWFP */
|
||||
#define MCF_PSC_PSCRLWFP_LWFP(x) (((x)&0x1FF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCTFDR */
|
||||
#define MCF_PSC_PSCTFDR_DATA(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCTFSR */
|
||||
#define MCF_PSC_PSCTFSR_EMT (0x1)
|
||||
#define MCF_PSC_PSCTFSR_ALARM (0x2)
|
||||
#define MCF_PSC_PSCTFSR_FU (0x4)
|
||||
#define MCF_PSC_PSCTFSR_FRMRDY (0x8)
|
||||
#define MCF_PSC_PSCTFSR_OF (0x10)
|
||||
#define MCF_PSC_PSCTFSR_UF (0x20)
|
||||
#define MCF_PSC_PSCTFSR_RXW (0x40)
|
||||
#define MCF_PSC_PSCTFSR_FAE (0x80)
|
||||
#define MCF_PSC_PSCTFSR_FRM(x) (((x)&0xF)<<0x8)
|
||||
#define MCF_PSC_PSCTFSR_FRM_BYTE0 (0x800)
|
||||
#define MCF_PSC_PSCTFSR_FRM_BYTE1 (0x400)
|
||||
#define MCF_PSC_PSCTFSR_FRM_BYTE2 (0x200)
|
||||
#define MCF_PSC_PSCTFSR_FRM_BYTE3 (0x100)
|
||||
#define MCF_PSC_PSCTFSR_TAG(x) (((x)&0x3)<<0xC)
|
||||
#define MCF_PSC_PSCTFSR_TXW (0x4000)
|
||||
#define MCF_PSC_PSCTFSR_IP (0x8000)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCTFCR */
|
||||
#define MCF_PSC_PSCTFCR_CNTR(x) (((x)&0xFFFF)<<0)
|
||||
#define MCF_PSC_PSCTFCR_TXW_MSK (0x40000)
|
||||
#define MCF_PSC_PSCTFCR_OF_MSK (0x80000)
|
||||
#define MCF_PSC_PSCTFCR_UF_MSK (0x100000)
|
||||
#define MCF_PSC_PSCTFCR_RXW_MSK (0x200000)
|
||||
#define MCF_PSC_PSCTFCR_FAE_MSK (0x400000)
|
||||
#define MCF_PSC_PSCTFCR_IP_MSK (0x800000)
|
||||
#define MCF_PSC_PSCTFCR_GR(x) (((x)&0x7)<<0x18)
|
||||
#define MCF_PSC_PSCTFCR_FRMEN (0x8000000)
|
||||
#define MCF_PSC_PSCTFCR_TIMER (0x10000000)
|
||||
#define MCF_PSC_PSCTFCR_WFR (0x20000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCTFAR */
|
||||
#define MCF_PSC_PSCTFAR_ALARM(x) (((x)&0x1FF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCTFRP */
|
||||
#define MCF_PSC_PSCTFRP_READ(x) (((x)&0x1FF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCTFWP */
|
||||
#define MCF_PSC_PSCTFWP_WRITE(x) (((x)&0x1FF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCTLRFP */
|
||||
#define MCF_PSC_PSCTLRFP_LRFP(x) (((x)&0x1FF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_PSC_PSCTLWFP */
|
||||
#define MCF_PSC_PSCTLWFP_LWFP(x) (((x)&0x1FF)<<0)
|
||||
|
||||
|
||||
#endif /* __MCF5475_PSC_H__ */
|
||||
@@ -1,106 +0,0 @@
|
||||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.81
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF5475_SDRAMC_H__
|
||||
#define __MCF5475_SDRAMC_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Synchronous DRAM Controller (SDRAMC)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_SDRAMC_SDRAMDS (*(volatile uint32_t*)(&_MBAR[0x4]))
|
||||
#define MCF_SDRAMC_CS0CFG (*(volatile uint32_t*)(&_MBAR[0x20]))
|
||||
#define MCF_SDRAMC_CS1CFG (*(volatile uint32_t*)(&_MBAR[0x24]))
|
||||
#define MCF_SDRAMC_CS2CFG (*(volatile uint32_t*)(&_MBAR[0x28]))
|
||||
#define MCF_SDRAMC_CS3CFG (*(volatile uint32_t*)(&_MBAR[0x2C]))
|
||||
#define MCF_SDRAMC_SDMR (*(volatile uint32_t*)(&_MBAR[0x100]))
|
||||
#define MCF_SDRAMC_SDCR (*(volatile uint32_t*)(&_MBAR[0x104]))
|
||||
#define MCF_SDRAMC_SDCFG1 (*(volatile uint32_t*)(&_MBAR[0x108]))
|
||||
#define MCF_SDRAMC_SDCFG2 (*(volatile uint32_t*)(&_MBAR[0x10C]))
|
||||
#define MCF_SDRAMC_CSCFG(x) (*(volatile uint32_t*)(&_MBAR[0x20 + ((x)*0x4)]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_SDRAMC_SDRAMDS */
|
||||
#define MCF_SDRAMC_SDRAMDS_SB_D(x) (((x)&0x3)<<0)
|
||||
#define MCF_SDRAMC_SDRAMDS_SB_S(x) (((x)&0x3)<<0x2)
|
||||
#define MCF_SDRAMC_SDRAMDS_SB_A(x) (((x)&0x3)<<0x4)
|
||||
#define MCF_SDRAMC_SDRAMDS_SB_C(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_SDRAMC_SDRAMDS_SB_E(x) (((x)&0x3)<<0x8)
|
||||
#define MCF_SDRAMC_SDRAMDS_DRIVE_24MA (0)
|
||||
#define MCF_SDRAMC_SDRAMDS_DRIVE_16MA (0x1)
|
||||
#define MCF_SDRAMC_SDRAMDS_DRIVE_8MA (0x2)
|
||||
#define MCF_SDRAMC_SDRAMDS_DRIVE_NONE (0x3)
|
||||
|
||||
/* Bit definitions and macros for MCF_SDRAMC_CSCFG */
|
||||
#define MCF_SDRAMC_CSCFG_CSSZ(x) (((x)&0x1F)<<0)
|
||||
#define MCF_SDRAMC_CSCFG_CSSZ_DISABLED (0)
|
||||
#define MCF_SDRAMC_CSCFG_CSSZ_1MBYTE (0x13)
|
||||
#define MCF_SDRAMC_CSCFG_CSSZ_2MBYTE (0x14)
|
||||
#define MCF_SDRAMC_CSCFG_CSSZ_4MBYTE (0x15)
|
||||
#define MCF_SDRAMC_CSCFG_CSSZ_8MBYTE (0x16)
|
||||
#define MCF_SDRAMC_CSCFG_CSSZ_16MBYTE (0x17)
|
||||
#define MCF_SDRAMC_CSCFG_CSSZ_32MBYTE (0x18)
|
||||
#define MCF_SDRAMC_CSCFG_CSSZ_64MBYTE (0x19)
|
||||
#define MCF_SDRAMC_CSCFG_CSSZ_128MBYTE (0x1A)
|
||||
#define MCF_SDRAMC_CSCFG_CSSZ_256MBYTE (0x1B)
|
||||
#define MCF_SDRAMC_CSCFG_CSSZ_512MBYTE (0x1C)
|
||||
#define MCF_SDRAMC_CSCFG_CSSZ_1GBYTE (0x1D)
|
||||
#define MCF_SDRAMC_CSCFG_CSSZ_2GBYTE (0x1E)
|
||||
#define MCF_SDRAMC_CSCFG_CSSZ_4GBYTE (0x1F)
|
||||
#define MCF_SDRAMC_CSCFG_CSBA(x) (((x)&0xFFF)<<0x14)
|
||||
#define MCF_SDRAMC_CSCFG_BA(x) ((x)&0xFFF00000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SDRAMC_SDMR */
|
||||
#define MCF_SDRAMC_SDMR_CMD (0x10000)
|
||||
#define MCF_SDRAMC_SDMR_AD(x) (((x)&0xFFF)<<0x12)
|
||||
#define MCF_SDRAMC_SDMR_BNKAD(x) (((x)&0x3)<<0x1E)
|
||||
#define MCF_SDRAMC_SDMR_BK_LMR (0)
|
||||
#define MCF_SDRAMC_SDMR_BK_LEMR (0x40000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SDRAMC_SDCR */
|
||||
#define MCF_SDRAMC_SDCR_IPALL (0x2)
|
||||
#define MCF_SDRAMC_SDCR_IREF (0x4)
|
||||
#define MCF_SDRAMC_SDCR_BUFF (0x10)
|
||||
#define MCF_SDRAMC_SDCR_DQS_OE(x) (((x)&0xF)<<0x8)
|
||||
#define MCF_SDRAMC_SDCR_RCNT(x) (((x)&0x3F)<<0x10)
|
||||
#define MCF_SDRAMC_SDCR_DRIVE (0x400000)
|
||||
#define MCF_SDRAMC_SDCR_AP (0x800000)
|
||||
#define MCF_SDRAMC_SDCR_MUX(x) (((x)&0x3)<<0x18)
|
||||
#define MCF_SDRAMC_SDCR_REF (0x10000000)
|
||||
#define MCF_SDRAMC_SDCR_DDR (0x20000000)
|
||||
#define MCF_SDRAMC_SDCR_CKE (0x40000000)
|
||||
#define MCF_SDRAMC_SDCR_MODE_EN (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SDRAMC_SDCFG1 */
|
||||
#define MCF_SDRAMC_SDCFG1_WTLAT(x) (((x)&0x7)<<0x4)
|
||||
#define MCF_SDRAMC_SDCFG1_REF2ACT(x) (((x)&0xF)<<0x8)
|
||||
#define MCF_SDRAMC_SDCFG1_PRE2ACT(x) (((x)&0x7)<<0xC)
|
||||
#define MCF_SDRAMC_SDCFG1_ACT2RW(x) (((x)&0x7)<<0x10)
|
||||
#define MCF_SDRAMC_SDCFG1_RDLAT(x) (((x)&0xF)<<0x14)
|
||||
#define MCF_SDRAMC_SDCFG1_SWT2RD(x) (((x)&0x7)<<0x18)
|
||||
#define MCF_SDRAMC_SDCFG1_SRD2RW(x) (((x)&0xF)<<0x1C)
|
||||
|
||||
/* Bit definitions and macros for MCF_SDRAMC_SDCFG2 */
|
||||
#define MCF_SDRAMC_SDCFG2_BL(x) (((x)&0xF)<<0x10)
|
||||
#define MCF_SDRAMC_SDCFG2_BRD2WT(x) (((x)&0xF)<<0x14)
|
||||
#define MCF_SDRAMC_SDCFG2_BWT2RW(x) (((x)&0xF)<<0x18)
|
||||
#define MCF_SDRAMC_SDCFG2_BRD2PRE(x) (((x)&0xF)<<0x1C)
|
||||
|
||||
|
||||
#endif /* __MCF5475_SDRAMC_H__ */
|
||||
@@ -1,398 +0,0 @@
|
||||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.81
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF5475_SEC_H__
|
||||
#define __MCF5475_SEC_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Integrated Security Engine (SEC)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_SEC_EUACRH (*(volatile uint32_t*)(&_MBAR[0x21000]))
|
||||
#define MCF_SEC_EUACRL (*(volatile uint32_t*)(&_MBAR[0x21004]))
|
||||
#define MCF_SEC_SIMRH (*(volatile uint32_t*)(&_MBAR[0x21008]))
|
||||
#define MCF_SEC_SIMRL (*(volatile uint32_t*)(&_MBAR[0x2100C]))
|
||||
#define MCF_SEC_SISRH (*(volatile uint32_t*)(&_MBAR[0x21010]))
|
||||
#define MCF_SEC_SISRL (*(volatile uint32_t*)(&_MBAR[0x21014]))
|
||||
#define MCF_SEC_SICRH (*(volatile uint32_t*)(&_MBAR[0x21018]))
|
||||
#define MCF_SEC_SICRL (*(volatile uint32_t*)(&_MBAR[0x2101C]))
|
||||
#define MCF_SEC_SIDR (*(volatile uint32_t*)(&_MBAR[0x21020]))
|
||||
#define MCF_SEC_EUASRH (*(volatile uint32_t*)(&_MBAR[0x21028]))
|
||||
#define MCF_SEC_EUASRL (*(volatile uint32_t*)(&_MBAR[0x2102C]))
|
||||
#define MCF_SEC_SMCR (*(volatile uint32_t*)(&_MBAR[0x21030]))
|
||||
#define MCF_SEC_MEAR (*(volatile uint32_t*)(&_MBAR[0x21038]))
|
||||
#define MCF_SEC_CCCR0 (*(volatile uint32_t*)(&_MBAR[0x2200C]))
|
||||
#define MCF_SEC_CCPSRH0 (*(volatile uint32_t*)(&_MBAR[0x22010]))
|
||||
#define MCF_SEC_CCPSRL0 (*(volatile uint32_t*)(&_MBAR[0x22014]))
|
||||
#define MCF_SEC_CDPR0 (*(volatile uint32_t*)(&_MBAR[0x22044]))
|
||||
#define MCF_SEC_FR0 (*(volatile uint32_t*)(&_MBAR[0x2204C]))
|
||||
#define MCF_SEC_CCCR1 (*(volatile uint32_t*)(&_MBAR[0x2300C]))
|
||||
#define MCF_SEC_CCPSRH1 (*(volatile uint32_t*)(&_MBAR[0x23010]))
|
||||
#define MCF_SEC_CCPSRL1 (*(volatile uint32_t*)(&_MBAR[0x23014]))
|
||||
#define MCF_SEC_CDPR1 (*(volatile uint32_t*)(&_MBAR[0x23044]))
|
||||
#define MCF_SEC_FR1 (*(volatile uint32_t*)(&_MBAR[0x2304C]))
|
||||
#define MCF_SEC_AFRCR (*(volatile uint32_t*)(&_MBAR[0x28018]))
|
||||
#define MCF_SEC_AFSR (*(volatile uint32_t*)(&_MBAR[0x28028]))
|
||||
#define MCF_SEC_AFISR (*(volatile uint32_t*)(&_MBAR[0x28030]))
|
||||
#define MCF_SEC_AFIMR (*(volatile uint32_t*)(&_MBAR[0x28038]))
|
||||
#define MCF_SEC_DRCR (*(volatile uint32_t*)(&_MBAR[0x2A018]))
|
||||
#define MCF_SEC_DSR (*(volatile uint32_t*)(&_MBAR[0x2A028]))
|
||||
#define MCF_SEC_DISR (*(volatile uint32_t*)(&_MBAR[0x2A030]))
|
||||
#define MCF_SEC_DIMR (*(volatile uint32_t*)(&_MBAR[0x2A038]))
|
||||
#define MCF_SEC_MDRCR (*(volatile uint32_t*)(&_MBAR[0x2C018]))
|
||||
#define MCF_SEC_MDSR (*(volatile uint32_t*)(&_MBAR[0x2C028]))
|
||||
#define MCF_SEC_MDISR (*(volatile uint32_t*)(&_MBAR[0x2C030]))
|
||||
#define MCF_SEC_MDIMR (*(volatile uint32_t*)(&_MBAR[0x2C038]))
|
||||
#define MCF_SEC_RNGRCR (*(volatile uint32_t*)(&_MBAR[0x2E018]))
|
||||
#define MCF_SEC_RNGSR (*(volatile uint32_t*)(&_MBAR[0x2E028]))
|
||||
#define MCF_SEC_RNGISR (*(volatile uint32_t*)(&_MBAR[0x2E030]))
|
||||
#define MCF_SEC_RNGIMR (*(volatile uint32_t*)(&_MBAR[0x2E038]))
|
||||
#define MCF_SEC_AESRCR (*(volatile uint32_t*)(&_MBAR[0x32018]))
|
||||
#define MCF_SEC_AESSR (*(volatile uint32_t*)(&_MBAR[0x32028]))
|
||||
#define MCF_SEC_AESISR (*(volatile uint32_t*)(&_MBAR[0x32030]))
|
||||
#define MCF_SEC_AESIMR (*(volatile uint32_t*)(&_MBAR[0x32038]))
|
||||
#define MCF_SEC_CCCRn(x) (*(volatile uint32_t*)(&_MBAR[0x2200C + ((x)*0x1000)]))
|
||||
#define MCF_SEC_CCPSRHn(x) (*(volatile uint32_t*)(&_MBAR[0x22010 + ((x)*0x1000)]))
|
||||
#define MCF_SEC_CCPSRLn(x) (*(volatile uint32_t*)(&_MBAR[0x22014 + ((x)*0x1000)]))
|
||||
#define MCF_SEC_CDPRn(x) (*(volatile uint32_t*)(&_MBAR[0x22044 + ((x)*0x1000)]))
|
||||
#define MCF_SEC_FRn(x) (*(volatile uint32_t*)(&_MBAR[0x2204C + ((x)*0x1000)]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_EUACRH */
|
||||
#define MCF_SEC_EUACRH_AFEU(x) (((x)&0xF)<<0)
|
||||
#define MCF_SEC_EUACRH_AFFEU_NOASSIGN (0)
|
||||
#define MCF_SEC_EUACRH_AFFEU_CHA0 (0x1)
|
||||
#define MCF_SEC_EUACRH_AFFEU_CHA1 (0x2)
|
||||
#define MCF_SEC_EUACRH_MDEU(x) (((x)&0xF)<<0x8)
|
||||
#define MCF_SEC_EUACRH_MDEU_NOASSIGN (0)
|
||||
#define MCF_SEC_EUACRH_MDEU_CHA0 (0x100)
|
||||
#define MCF_SEC_EUACRH_MDEU_CHA1 (0x200)
|
||||
#define MCF_SEC_EUACRH_RNG(x) (((x)&0xF)<<0x18)
|
||||
#define MCF_SEC_EUACRH_RNG_NOASSIGN (0)
|
||||
#define MCF_SEC_EUACRH_RNG_CHA0 (0x1000000)
|
||||
#define MCF_SEC_EUACRH_RNG_CHA1 (0x2000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_EUACRL */
|
||||
#define MCF_SEC_EUACRL_AESU(x) (((x)&0xF)<<0x10)
|
||||
#define MCF_SEC_EUACRL_AESU_NOASSIGN (0)
|
||||
#define MCF_SEC_EUACRL_AESU_CHA0 (0x10000)
|
||||
#define MCF_SEC_EUACRL_AESU_CHA1 (0x20000)
|
||||
#define MCF_SEC_EUACRL_DEU(x) (((x)&0xF)<<0x18)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_SIMRH */
|
||||
#define MCF_SEC_SIMRH_AERR (0x8000000)
|
||||
#define MCF_SEC_SIMRH_CHA_0_DN (0x10000000)
|
||||
#define MCF_SEC_SIMRH_CHA_0_ERR (0x20000000)
|
||||
#define MCF_SEC_SIMRH_CHA_1_DN (0x40000000)
|
||||
#define MCF_SEC_SIMRH_CHA_1_ERR (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_SIMRL */
|
||||
#define MCF_SEC_SIMRL_TEA (0x40)
|
||||
#define MCF_SEC_SIMRL_DEU_DN (0x100)
|
||||
#define MCF_SEC_SIMRL_DEU_ERR (0x200)
|
||||
#define MCF_SEC_SIMRL_AESU_DN (0x1000)
|
||||
#define MCF_SEC_SIMRL_AESU_ERR (0x2000)
|
||||
#define MCF_SEC_SIMRL_MDEU_DN (0x10000)
|
||||
#define MCF_SEC_SIMRL_MDEU_ERR (0x20000)
|
||||
#define MCF_SEC_SIMRL_AFEU_DN (0x100000)
|
||||
#define MCF_SEC_SIMRL_AFEU_ERR (0x200000)
|
||||
#define MCF_SEC_SIMRL_RNG_DN (0x1000000)
|
||||
#define MCF_SEC_SIMRL_RNG_ERR (0x2000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_SISRH */
|
||||
#define MCF_SEC_SISRH_AERR (0x8000000)
|
||||
#define MCF_SEC_SISRH_CHA_0_DN (0x10000000)
|
||||
#define MCF_SEC_SISRH_CHA_0_ERR (0x20000000)
|
||||
#define MCF_SEC_SISRH_CHA_1_DN (0x40000000)
|
||||
#define MCF_SEC_SISRH_CHA_1_ERR (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_SISRL */
|
||||
#define MCF_SEC_SISRL_TEA (0x40)
|
||||
#define MCF_SEC_SISRL_DEU_DN (0x100)
|
||||
#define MCF_SEC_SISRL_DEU_ERR (0x200)
|
||||
#define MCF_SEC_SISRL_AESU_DN (0x1000)
|
||||
#define MCF_SEC_SISRL_AESU_ERR (0x2000)
|
||||
#define MCF_SEC_SISRL_MDEU_DN (0x10000)
|
||||
#define MCF_SEC_SISRL_MDEU_ERR (0x20000)
|
||||
#define MCF_SEC_SISRL_AFEU_DN (0x100000)
|
||||
#define MCF_SEC_SISRL_AFEU_ERR (0x200000)
|
||||
#define MCF_SEC_SISRL_RNG_DN (0x1000000)
|
||||
#define MCF_SEC_SISRL_RNG_ERR (0x2000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_SICRH */
|
||||
#define MCF_SEC_SICRH_AERR (0x8000000)
|
||||
#define MCF_SEC_SICRH_CHA_0_DN (0x10000000)
|
||||
#define MCF_SEC_SICRH_CHA_0_ERR (0x20000000)
|
||||
#define MCF_SEC_SICRH_CHA_1_DN (0x40000000)
|
||||
#define MCF_SEC_SICRH_CHA_1_ERR (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_SICRL */
|
||||
#define MCF_SEC_SICRL_TEA (0x40)
|
||||
#define MCF_SEC_SICRL_DEU_DN (0x100)
|
||||
#define MCF_SEC_SICRL_DEU_ERR (0x200)
|
||||
#define MCF_SEC_SICRL_AESU_DN (0x1000)
|
||||
#define MCF_SEC_SICRL_AESU_ERR (0x2000)
|
||||
#define MCF_SEC_SICRL_MDEU_DN (0x10000)
|
||||
#define MCF_SEC_SICRL_MDEU_ERR (0x20000)
|
||||
#define MCF_SEC_SICRL_AFEU_DN (0x100000)
|
||||
#define MCF_SEC_SICRL_AFEU_ERR (0x200000)
|
||||
#define MCF_SEC_SICRL_RNG_DN (0x1000000)
|
||||
#define MCF_SEC_SICRL_RNG_ERR (0x2000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_SIDR */
|
||||
#define MCF_SEC_SIDR_VERSION(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_EUASRH */
|
||||
#define MCF_SEC_EUASRH_AFEU(x) (((x)&0xF)<<0)
|
||||
#define MCF_SEC_EUASRH_MDEU(x) (((x)&0xF)<<0x8)
|
||||
#define MCF_SEC_EUASRH_RNG(x) (((x)&0xF)<<0x18)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_EUASRL */
|
||||
#define MCF_SEC_EUASRL_AESU(x) (((x)&0xF)<<0x10)
|
||||
#define MCF_SEC_EUASRL_DEU(x) (((x)&0xF)<<0x18)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_SMCR */
|
||||
#define MCF_SEC_SMCR_CURR_CHAN(x) (((x)&0xF)<<0x4)
|
||||
#define MCF_SEC_SMCR_CURR_CHAN_1 (0x10)
|
||||
#define MCF_SEC_SMCR_CURR_CHAN_2 (0x20)
|
||||
#define MCF_SEC_SMCR_SWR (0x1000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_MEAR */
|
||||
#define MCF_SEC_MEAR_ADDRESS(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_CCCRn */
|
||||
#define MCF_SEC_CCCRn_RST (0x1)
|
||||
#define MCF_SEC_CCCRn_CDIE (0x2)
|
||||
#define MCF_SEC_CCCRn_NT (0x4)
|
||||
#define MCF_SEC_CCCRn_NE (0x8)
|
||||
#define MCF_SEC_CCCRn_WE (0x10)
|
||||
#define MCF_SEC_CCCRn_BURST_SIZE(x) (((x)&0x7)<<0x8)
|
||||
#define MCF_SEC_CCCRn_BURST_SIZE_2 (0)
|
||||
#define MCF_SEC_CCCRn_BURST_SIZE_8 (0x100)
|
||||
#define MCF_SEC_CCCRn_BURST_SIZE_16 (0x200)
|
||||
#define MCF_SEC_CCCRn_BURST_SIZE_24 (0x300)
|
||||
#define MCF_SEC_CCCRn_BURST_SIZE_32 (0x400)
|
||||
#define MCF_SEC_CCCRn_BURST_SIZE_40 (0x500)
|
||||
#define MCF_SEC_CCCRn_BURST_SIZE_48 (0x600)
|
||||
#define MCF_SEC_CCCRn_BURST_SIZE_56 (0x700)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_CCPSRHn */
|
||||
#define MCF_SEC_CCPSRHn_STATE(x) (((x)&0xFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_CCPSRLn */
|
||||
#define MCF_SEC_CCPSRLn_PAIR_PTR(x) (((x)&0xFF)<<0)
|
||||
#define MCF_SEC_CCPSRLn_EUERR (0x100)
|
||||
#define MCF_SEC_CCPSRLn_SERR (0x200)
|
||||
#define MCF_SEC_CCPSRLn_DERR (0x400)
|
||||
#define MCF_SEC_CCPSRLn_PERR (0x1000)
|
||||
#define MCF_SEC_CCPSRLn_TEA (0x2000)
|
||||
#define MCF_SEC_CCPSRLn_SD (0x10000)
|
||||
#define MCF_SEC_CCPSRLn_PD (0x20000)
|
||||
#define MCF_SEC_CCPSRLn_SRD (0x40000)
|
||||
#define MCF_SEC_CCPSRLn_PRD (0x80000)
|
||||
#define MCF_SEC_CCPSRLn_SG (0x100000)
|
||||
#define MCF_SEC_CCPSRLn_PG (0x200000)
|
||||
#define MCF_SEC_CCPSRLn_SR (0x400000)
|
||||
#define MCF_SEC_CCPSRLn_PR (0x800000)
|
||||
#define MCF_SEC_CCPSRLn_MO (0x1000000)
|
||||
#define MCF_SEC_CCPSRLn_MI (0x2000000)
|
||||
#define MCF_SEC_CCPSRLn_STAT (0x4000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_CDPRn */
|
||||
#define MCF_SEC_CDPRn_CDP(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_FRn */
|
||||
#define MCF_SEC_FRn_FETCH_ADDR(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_AFRCR */
|
||||
#define MCF_SEC_AFRCR_SR (0x1000000)
|
||||
#define MCF_SEC_AFRCR_MI (0x2000000)
|
||||
#define MCF_SEC_AFRCR_RI (0x4000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_AFSR */
|
||||
#define MCF_SEC_AFSR_RD (0x1000000)
|
||||
#define MCF_SEC_AFSR_ID (0x2000000)
|
||||
#define MCF_SEC_AFSR_IE (0x4000000)
|
||||
#define MCF_SEC_AFSR_OFR (0x8000000)
|
||||
#define MCF_SEC_AFSR_IFW (0x10000000)
|
||||
#define MCF_SEC_AFSR_HALT (0x20000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_AFISR */
|
||||
#define MCF_SEC_AFISR_DSE (0x10000)
|
||||
#define MCF_SEC_AFISR_KSE (0x20000)
|
||||
#define MCF_SEC_AFISR_CE (0x40000)
|
||||
#define MCF_SEC_AFISR_ERE (0x80000)
|
||||
#define MCF_SEC_AFISR_IE (0x100000)
|
||||
#define MCF_SEC_AFISR_OFU (0x2000000)
|
||||
#define MCF_SEC_AFISR_IFO (0x4000000)
|
||||
#define MCF_SEC_AFISR_IFE (0x10000000)
|
||||
#define MCF_SEC_AFISR_OFE (0x20000000)
|
||||
#define MCF_SEC_AFISR_AE (0x40000000)
|
||||
#define MCF_SEC_AFISR_ME (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_AFIMR */
|
||||
#define MCF_SEC_AFIMR_DSE (0x10000)
|
||||
#define MCF_SEC_AFIMR_KSE (0x20000)
|
||||
#define MCF_SEC_AFIMR_CE (0x40000)
|
||||
#define MCF_SEC_AFIMR_ERE (0x80000)
|
||||
#define MCF_SEC_AFIMR_IE (0x100000)
|
||||
#define MCF_SEC_AFIMR_OFU (0x2000000)
|
||||
#define MCF_SEC_AFIMR_IFO (0x4000000)
|
||||
#define MCF_SEC_AFIMR_IFE (0x10000000)
|
||||
#define MCF_SEC_AFIMR_OFE (0x20000000)
|
||||
#define MCF_SEC_AFIMR_AE (0x40000000)
|
||||
#define MCF_SEC_AFIMR_ME (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_DRCR */
|
||||
#define MCF_SEC_DRCR_SR (0x1000000)
|
||||
#define MCF_SEC_DRCR_MI (0x2000000)
|
||||
#define MCF_SEC_DRCR_RI (0x4000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_DSR */
|
||||
#define MCF_SEC_DSR_RD (0x1000000)
|
||||
#define MCF_SEC_DSR_ID (0x2000000)
|
||||
#define MCF_SEC_DSR_IE (0x4000000)
|
||||
#define MCF_SEC_DSR_OFR (0x8000000)
|
||||
#define MCF_SEC_DSR_IFW (0x10000000)
|
||||
#define MCF_SEC_DSR_HALT (0x20000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_DISR */
|
||||
#define MCF_SEC_DISR_DSE (0x10000)
|
||||
#define MCF_SEC_DISR_KSE (0x20000)
|
||||
#define MCF_SEC_DISR_CE (0x40000)
|
||||
#define MCF_SEC_DISR_ERE (0x80000)
|
||||
#define MCF_SEC_DISR_IE (0x100000)
|
||||
#define MCF_SEC_DISR_KPE (0x200000)
|
||||
#define MCF_SEC_DISR_OFU (0x2000000)
|
||||
#define MCF_SEC_DISR_IFO (0x4000000)
|
||||
#define MCF_SEC_DISR_IFE (0x10000000)
|
||||
#define MCF_SEC_DISR_OFE (0x20000000)
|
||||
#define MCF_SEC_DISR_AE (0x40000000)
|
||||
#define MCF_SEC_DISR_ME (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_DIMR */
|
||||
#define MCF_SEC_DIMR_DSE (0x10000)
|
||||
#define MCF_SEC_DIMR_KSE (0x20000)
|
||||
#define MCF_SEC_DIMR_CE (0x40000)
|
||||
#define MCF_SEC_DIMR_ERE (0x80000)
|
||||
#define MCF_SEC_DIMR_IE (0x100000)
|
||||
#define MCF_SEC_DIMR_KPE (0x200000)
|
||||
#define MCF_SEC_DIMR_OFU (0x2000000)
|
||||
#define MCF_SEC_DIMR_IFO (0x4000000)
|
||||
#define MCF_SEC_DIMR_IFE (0x10000000)
|
||||
#define MCF_SEC_DIMR_OFE (0x20000000)
|
||||
#define MCF_SEC_DIMR_AE (0x40000000)
|
||||
#define MCF_SEC_DIMR_ME (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_MDRCR */
|
||||
#define MCF_SEC_MDRCR_SR (0x1000000)
|
||||
#define MCF_SEC_MDRCR_MI (0x2000000)
|
||||
#define MCF_SEC_MDRCR_RI (0x4000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_MDSR */
|
||||
#define MCF_SEC_MDSR_RD (0x1000000)
|
||||
#define MCF_SEC_MDSR_ID (0x2000000)
|
||||
#define MCF_SEC_MDSR_IE (0x4000000)
|
||||
#define MCF_SEC_MDSR_IFW (0x10000000)
|
||||
#define MCF_SEC_MDSR_HALT (0x20000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_MDISR */
|
||||
#define MCF_SEC_MDISR_DSE (0x10000)
|
||||
#define MCF_SEC_MDISR_KSE (0x20000)
|
||||
#define MCF_SEC_MDISR_CE (0x40000)
|
||||
#define MCF_SEC_MDISR_ERE (0x80000)
|
||||
#define MCF_SEC_MDISR_IE (0x100000)
|
||||
#define MCF_SEC_MDISR_IFO (0x4000000)
|
||||
#define MCF_SEC_MDISR_AE (0x40000000)
|
||||
#define MCF_SEC_MDISR_ME (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_MDIMR */
|
||||
#define MCF_SEC_MDIMR_DSE (0x10000)
|
||||
#define MCF_SEC_MDIMR_KSE (0x20000)
|
||||
#define MCF_SEC_MDIMR_CE (0x40000)
|
||||
#define MCF_SEC_MDIMR_ERE (0x80000)
|
||||
#define MCF_SEC_MDIMR_IE (0x100000)
|
||||
#define MCF_SEC_MDIMR_IFO (0x4000000)
|
||||
#define MCF_SEC_MDIMR_AE (0x40000000)
|
||||
#define MCF_SEC_MDIMR_ME (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_RNGRCR */
|
||||
#define MCF_SEC_RNGRCR_SR (0x1000000)
|
||||
#define MCF_SEC_RNGRCR_MI (0x2000000)
|
||||
#define MCF_SEC_RNGRCR_RI (0x4000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_RNGSR */
|
||||
#define MCF_SEC_RNGSR_RD (0x1000000)
|
||||
#define MCF_SEC_RNGSR_IE (0x4000000)
|
||||
#define MCF_SEC_RNGSR_OFR (0x8000000)
|
||||
#define MCF_SEC_RNGSR_HALT (0x20000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_RNGISR */
|
||||
#define MCF_SEC_RNGISR_IE (0x100000)
|
||||
#define MCF_SEC_RNGISR_OFU (0x2000000)
|
||||
#define MCF_SEC_RNGISR_AE (0x40000000)
|
||||
#define MCF_SEC_RNGISR_ME (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_RNGIMR */
|
||||
#define MCF_SEC_RNGIMR_IE (0x100000)
|
||||
#define MCF_SEC_RNGIMR_OFU (0x2000000)
|
||||
#define MCF_SEC_RNGIMR_AE (0x40000000)
|
||||
#define MCF_SEC_RNGIMR_ME (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_AESRCR */
|
||||
#define MCF_SEC_AESRCR_SR (0x1000000)
|
||||
#define MCF_SEC_AESRCR_MI (0x2000000)
|
||||
#define MCF_SEC_AESRCR_RI (0x4000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_AESSR */
|
||||
#define MCF_SEC_AESSR_RD (0x1000000)
|
||||
#define MCF_SEC_AESSR_ID (0x2000000)
|
||||
#define MCF_SEC_AESSR_IE (0x4000000)
|
||||
#define MCF_SEC_AESSR_OFR (0x8000000)
|
||||
#define MCF_SEC_AESSR_IFW (0x10000000)
|
||||
#define MCF_SEC_AESSR_HALT (0x20000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_AESISR */
|
||||
#define MCF_SEC_AESISR_DSE (0x10000)
|
||||
#define MCF_SEC_AESISR_KSE (0x20000)
|
||||
#define MCF_SEC_AESISR_CE (0x40000)
|
||||
#define MCF_SEC_AESISR_ERE (0x80000)
|
||||
#define MCF_SEC_AESISR_IE (0x100000)
|
||||
#define MCF_SEC_AESISR_OFU (0x2000000)
|
||||
#define MCF_SEC_AESISR_IFO (0x4000000)
|
||||
#define MCF_SEC_AESISR_IFE (0x10000000)
|
||||
#define MCF_SEC_AESISR_OFE (0x20000000)
|
||||
#define MCF_SEC_AESISR_AE (0x40000000)
|
||||
#define MCF_SEC_AESISR_ME (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SEC_AESIMR */
|
||||
#define MCF_SEC_AESIMR_DSE (0x10000)
|
||||
#define MCF_SEC_AESIMR_KSE (0x20000)
|
||||
#define MCF_SEC_AESIMR_CE (0x40000)
|
||||
#define MCF_SEC_AESIMR_ERE (0x80000)
|
||||
#define MCF_SEC_AESIMR_IE (0x100000)
|
||||
#define MCF_SEC_AESIMR_OFU (0x2000000)
|
||||
#define MCF_SEC_AESIMR_IFO (0x4000000)
|
||||
#define MCF_SEC_AESIMR_IFE (0x10000000)
|
||||
#define MCF_SEC_AESIMR_OFE (0x20000000)
|
||||
#define MCF_SEC_AESIMR_AE (0x40000000)
|
||||
#define MCF_SEC_AESIMR_ME (0x80000000)
|
||||
|
||||
|
||||
#endif /* __MCF5475_SEC_H__ */
|
||||
@@ -1,67 +0,0 @@
|
||||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.81
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF5475_SIU_H__
|
||||
#define __MCF5475_SIU_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* System Integration Unit (SIU)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_SIU_SBCR (*(volatile uint32_t*)(&_MBAR[0x10]))
|
||||
#define MCF_SIU_SECSACR (*(volatile uint32_t*)(&_MBAR[0x38]))
|
||||
#define MCF_SIU_RSR (*(volatile uint32_t*)(&_MBAR[0x44]))
|
||||
#define MCF_SIU_JTAGID (*(volatile uint32_t*)(&_MBAR[0x50]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_SIU_SBCR */
|
||||
#define MCF_SIU_SBCR_PIN2DSPI (0x8000000)
|
||||
#define MCF_SIU_SBCR_DMA2CPU (0x10000000)
|
||||
#define MCF_SIU_SBCR_CPU2DMA (0x20000000)
|
||||
#define MCF_SIU_SBCR_PIN2DMA (0x40000000)
|
||||
#define MCF_SIU_SBCR_PIN2CPU (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SIU_SECSACR */
|
||||
#define MCF_SIU_SECSACR_SEQEN (0x1)
|
||||
|
||||
/* Bit definitions and macros for MCF_SIU_RSR */
|
||||
#define MCF_SIU_RSR_RST (0x1)
|
||||
#define MCF_SIU_RSR_RSTWD (0x2)
|
||||
#define MCF_SIU_RSR_RSTJTG (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_SIU_JTAGID */
|
||||
#define MCF_SIU_JTAGID_JTAGID(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_SIU_JTAGID */
|
||||
#define MCF_SIU_JTAGID_REV (0xF0000000)
|
||||
#define MCF_SIU_JTAGID_PROCESSOR (0x0FFFFFFF)
|
||||
#define MCF_SIU_JTAGID_MCF5485 (0x0800C01D)
|
||||
#define MCF_SIU_JTAGID_MCF5484 (0x0800D01D)
|
||||
#define MCF_SIU_JTAGID_MCF5483 (0x0800E01D)
|
||||
#define MCF_SIU_JTAGID_MCF5482 (0x0800F01D)
|
||||
#define MCF_SIU_JTAGID_MCF5481 (0x0801001D)
|
||||
#define MCF_SIU_JTAGID_MCF5480 (0x0801101D)
|
||||
#define MCF_SIU_JTAGID_MCF5475 (0x0801201D)
|
||||
#define MCF_SIU_JTAGID_MCF5474 (0x0801301D)
|
||||
#define MCF_SIU_JTAGID_MCF5473 (0x0801401D)
|
||||
#define MCF_SIU_JTAGID_MCF5472 (0x0801501D)
|
||||
#define MCF_SIU_JTAGID_MCF5471 (0x0801601D)
|
||||
#define MCF_SIU_JTAGID_MCF5470 (0x0801701D)
|
||||
|
||||
#endif /* __MCF5475_SIU_H__ */
|
||||
@@ -1,59 +0,0 @@
|
||||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.81
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF5475_SLT_H__
|
||||
#define __MCF5475_SLT_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Slice Timers (SLT)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_SLT0_STCNT (*(volatile uint32_t*)(&_MBAR[0x900]))
|
||||
#define MCF_SLT0_SCR (*(volatile uint32_t*)(&_MBAR[0x904]))
|
||||
#define MCF_SLT0_SCNT (*(volatile uint32_t*)(&_MBAR[0x908]))
|
||||
#define MCF_SLT0_SSR (*(volatile uint32_t*)(&_MBAR[0x90C]))
|
||||
|
||||
#define MCF_SLT1_STCNT (*(volatile uint32_t*)(&_MBAR[0x910]))
|
||||
#define MCF_SLT1_SCR (*(volatile uint32_t*)(&_MBAR[0x914]))
|
||||
#define MCF_SLT1_SCNT (*(volatile uint32_t*)(&_MBAR[0x918]))
|
||||
#define MCF_SLT1_SSR (*(volatile uint32_t*)(&_MBAR[0x91C]))
|
||||
|
||||
#define MCF_SLT_STCNT(x) (*(volatile uint32_t*)(&_MBAR[0x900 + ((x)*0x10)]))
|
||||
#define MCF_SLT_SCR(x) (*(volatile uint32_t*)(&_MBAR[0x904 + ((x)*0x10)]))
|
||||
#define MCF_SLT_SCNT(x) (*(volatile int32_t*)(&_MBAR[0x908 + ((x)*0x10)]))
|
||||
#define MCF_SLT_SSR(x) (*(volatile uint32_t*)(&_MBAR[0x90C + ((x)*0x10)]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_SLT_STCNT */
|
||||
#define MCF_SLT_STCNT_TC(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_SLT_SCR */
|
||||
#define MCF_SLT_SCR_TEN (0x1000000)
|
||||
#define MCF_SLT_SCR_IEN (0x2000000)
|
||||
#define MCF_SLT_SCR_RUN (0x4000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SLT_SCNT */
|
||||
#define MCF_SLT_SCNT_CNT(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_SLT_SSR */
|
||||
#define MCF_SLT_SSR_ST (0x1000000)
|
||||
#define MCF_SLT_SSR_BE (0x2000000)
|
||||
|
||||
|
||||
#endif /* __MCF5475_SLT_H__ */
|
||||
@@ -1,62 +0,0 @@
|
||||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.81
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF5475_SRAM_H__
|
||||
#define __MCF5475_SRAM_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* System SRAM Module (SRAM)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_SRAM_SSCR (*(volatile uint32_t*)(&__MBAR[0x1FFC0]))
|
||||
#define MCF_SRAM_TCCR (*(volatile uint32_t*)(&__MBAR[0x1FFC4]))
|
||||
#define MCF_SRAM_TCCRDR (*(volatile uint32_t*)(&__MBAR[0x1FFC8]))
|
||||
#define MCF_SRAM_TCCRDW (*(volatile uint32_t*)(&__MBAR[0x1FFCC]))
|
||||
#define MCF_SRAM_TCCRSEC (*(volatile uint32_t*)(&__MBAR[0x1FFD0]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_SRAM_SSCR */
|
||||
#define MCF_SRAM_SSCR_INLV (0x10000)
|
||||
|
||||
/* Bit definitions and macros for MCF_SRAM_TCCR */
|
||||
#define MCF_SRAM_TCCR_BANK0_TC(x) (((x)&0xF)<<0)
|
||||
#define MCF_SRAM_TCCR_BANK1_TC(x) (((x)&0xF)<<0x8)
|
||||
#define MCF_SRAM_TCCR_BANK2_TC(x) (((x)&0xF)<<0x10)
|
||||
#define MCF_SRAM_TCCR_BANK3_TC(x) (((x)&0xF)<<0x18)
|
||||
|
||||
/* Bit definitions and macros for MCF_SRAM_TCCRDR */
|
||||
#define MCF_SRAM_TCCRDR_BANK0_TC(x) (((x)&0xF)<<0)
|
||||
#define MCF_SRAM_TCCRDR_BANK1_TC(x) (((x)&0xF)<<0x8)
|
||||
#define MCF_SRAM_TCCRDR_BANK2_TC(x) (((x)&0xF)<<0x10)
|
||||
#define MCF_SRAM_TCCRDR_BANK3_TC(x) (((x)&0xF)<<0x18)
|
||||
|
||||
/* Bit definitions and macros for MCF_SRAM_TCCRDW */
|
||||
#define MCF_SRAM_TCCRDW_BANK0_TC(x) (((x)&0xF)<<0)
|
||||
#define MCF_SRAM_TCCRDW_BANK1_TC(x) (((x)&0xF)<<0x8)
|
||||
#define MCF_SRAM_TCCRDW_BANK2_TC(x) (((x)&0xF)<<0x10)
|
||||
#define MCF_SRAM_TCCRDW_BANK3_TC(x) (((x)&0xF)<<0x18)
|
||||
|
||||
/* Bit definitions and macros for MCF_SRAM_TCCRSEC */
|
||||
#define MCF_SRAM_TCCRSEC_BANK0_TC(x) (((x)&0xF)<<0)
|
||||
#define MCF_SRAM_TCCRSEC_BANK1_TC(x) (((x)&0xF)<<0x8)
|
||||
#define MCF_SRAM_TCCRSEC_BANK2_TC(x) (((x)&0xF)<<0x10)
|
||||
#define MCF_SRAM_TCCRSEC_BANK3_TC(x) (((x)&0xF)<<0x18)
|
||||
|
||||
|
||||
#endif /* __MCF5475_SRAM_H__ */
|
||||
@@ -1,554 +0,0 @@
|
||||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.81
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF5475_USB_H__
|
||||
#define __MCF5475_USB_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* Universal Serial Bus Interface (USB)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_USB_USBAISR (*(volatile uint8_t *)(&__MBAR[0xB000]))
|
||||
#define MCF_USB_USBAIMR (*(volatile uint8_t *)(&__MBAR[0xB001]))
|
||||
#define MCF_USB_EPINFO (*(volatile uint8_t *)(&__MBAR[0xB003]))
|
||||
#define MCF_USB_CFGR (*(volatile uint8_t *)(&__MBAR[0xB004]))
|
||||
#define MCF_USB_CFGAR (*(volatile uint8_t *)(&__MBAR[0xB005]))
|
||||
#define MCF_USB_SPEEDR (*(volatile uint8_t *)(&__MBAR[0xB006]))
|
||||
#define MCF_USB_FRMNUMR (*(volatile uint16_t*)(&__MBAR[0xB00E]))
|
||||
#define MCF_USB_EPTNR (*(volatile uint16_t*)(&__MBAR[0xB010]))
|
||||
#define MCF_USB_IFUR (*(volatile uint16_t*)(&__MBAR[0xB014]))
|
||||
#define MCF_USB_IFR0 (*(volatile uint16_t*)(&__MBAR[0xB040]))
|
||||
#define MCF_USB_IFR1 (*(volatile uint16_t*)(&__MBAR[0xB042]))
|
||||
#define MCF_USB_IFR2 (*(volatile uint16_t*)(&__MBAR[0xB044]))
|
||||
#define MCF_USB_IFR3 (*(volatile uint16_t*)(&__MBAR[0xB046]))
|
||||
#define MCF_USB_IFR4 (*(volatile uint16_t*)(&__MBAR[0xB048]))
|
||||
#define MCF_USB_IFR5 (*(volatile uint16_t*)(&__MBAR[0xB04A]))
|
||||
#define MCF_USB_IFR6 (*(volatile uint16_t*)(&__MBAR[0xB04C]))
|
||||
#define MCF_USB_IFR7 (*(volatile uint16_t*)(&__MBAR[0xB04E]))
|
||||
#define MCF_USB_IFR8 (*(volatile uint16_t*)(&__MBAR[0xB050]))
|
||||
#define MCF_USB_IFR9 (*(volatile uint16_t*)(&__MBAR[0xB052]))
|
||||
#define MCF_USB_IFR10 (*(volatile uint16_t*)(&__MBAR[0xB054]))
|
||||
#define MCF_USB_IFR11 (*(volatile uint16_t*)(&__MBAR[0xB056]))
|
||||
#define MCF_USB_IFR12 (*(volatile uint16_t*)(&__MBAR[0xB058]))
|
||||
#define MCF_USB_IFR13 (*(volatile uint16_t*)(&__MBAR[0xB05A]))
|
||||
#define MCF_USB_IFR14 (*(volatile uint16_t*)(&__MBAR[0xB05C]))
|
||||
#define MCF_USB_IFR15 (*(volatile uint16_t*)(&__MBAR[0xB05E]))
|
||||
#define MCF_USB_IFR16 (*(volatile uint16_t*)(&__MBAR[0xB060]))
|
||||
#define MCF_USB_IFR17 (*(volatile uint16_t*)(&__MBAR[0xB062]))
|
||||
#define MCF_USB_IFR18 (*(volatile uint16_t*)(&__MBAR[0xB064]))
|
||||
#define MCF_USB_IFR19 (*(volatile uint16_t*)(&__MBAR[0xB066]))
|
||||
#define MCF_USB_IFR20 (*(volatile uint16_t*)(&__MBAR[0xB068]))
|
||||
#define MCF_USB_IFR21 (*(volatile uint16_t*)(&__MBAR[0xB06A]))
|
||||
#define MCF_USB_IFR22 (*(volatile uint16_t*)(&__MBAR[0xB06C]))
|
||||
#define MCF_USB_IFR23 (*(volatile uint16_t*)(&__MBAR[0xB06E]))
|
||||
#define MCF_USB_IFR24 (*(volatile uint16_t*)(&__MBAR[0xB070]))
|
||||
#define MCF_USB_IFR25 (*(volatile uint16_t*)(&__MBAR[0xB072]))
|
||||
#define MCF_USB_IFR26 (*(volatile uint16_t*)(&__MBAR[0xB074]))
|
||||
#define MCF_USB_IFR27 (*(volatile uint16_t*)(&__MBAR[0xB076]))
|
||||
#define MCF_USB_IFR28 (*(volatile uint16_t*)(&__MBAR[0xB078]))
|
||||
#define MCF_USB_IFR29 (*(volatile uint16_t*)(&__MBAR[0xB07A]))
|
||||
#define MCF_USB_IFR30 (*(volatile uint16_t*)(&__MBAR[0xB07C]))
|
||||
#define MCF_USB_IFR31 (*(volatile uint16_t*)(&__MBAR[0xB07E]))
|
||||
#define MCF_USB_PPCNT (*(volatile uint16_t*)(&__MBAR[0xB080]))
|
||||
#define MCF_USB_DPCNT (*(volatile uint16_t*)(&__MBAR[0xB082]))
|
||||
#define MCF_USB_CRCECNT (*(volatile uint16_t*)(&__MBAR[0xB084]))
|
||||
#define MCF_USB_BSECNT (*(volatile uint16_t*)(&__MBAR[0xB086]))
|
||||
#define MCF_USB_PIDECNT (*(volatile uint16_t*)(&__MBAR[0xB088]))
|
||||
#define MCF_USB_FRMECNT (*(volatile uint16_t*)(&__MBAR[0xB08A]))
|
||||
#define MCF_USB_TXPCNT (*(volatile uint16_t*)(&__MBAR[0xB08C]))
|
||||
#define MCF_USB_CNTOVR (*(volatile uint8_t *)(&__MBAR[0xB08E]))
|
||||
#define MCF_USB_EP0ACR (*(volatile uint8_t *)(&__MBAR[0xB101]))
|
||||
#define MCF_USB_EP0MPSR (*(volatile uint16_t*)(&__MBAR[0xB102]))
|
||||
#define MCF_USB_EP0IFR (*(volatile uint8_t *)(&__MBAR[0xB104]))
|
||||
#define MCF_USB_EP0SR (*(volatile uint8_t *)(&__MBAR[0xB105]))
|
||||
#define MCF_USB_BMRTR (*(volatile uint8_t *)(&__MBAR[0xB106]))
|
||||
#define MCF_USB_BRTR (*(volatile uint8_t *)(&__MBAR[0xB107]))
|
||||
#define MCF_USB_WVALUER (*(volatile uint16_t*)(&__MBAR[0xB108]))
|
||||
#define MCF_USB_WINDEXR (*(volatile uint16_t*)(&__MBAR[0xB10A]))
|
||||
#define MCF_USB_WLENGTHR (*(volatile uint16_t*)(&__MBAR[0xB10C]))
|
||||
#define MCF_USB_EP1OUTACR (*(volatile uint8_t *)(&__MBAR[0xB131]))
|
||||
#define MCF_USB_EP1OUTMPSR (*(volatile uint16_t*)(&__MBAR[0xB132]))
|
||||
#define MCF_USB_EP1OUTIFR (*(volatile uint8_t *)(&__MBAR[0xB134]))
|
||||
#define MCF_USB_EP1OUTSR (*(volatile uint8_t *)(&__MBAR[0xB135]))
|
||||
#define MCF_USB_EP1OUTSFR (*(volatile uint16_t*)(&__MBAR[0xB13E]))
|
||||
#define MCF_USB_EP1INACR (*(volatile uint8_t *)(&__MBAR[0xB149]))
|
||||
#define MCF_USB_EP1INMPSR (*(volatile uint16_t*)(&__MBAR[0xB14A]))
|
||||
#define MCF_USB_EP1INIFR (*(volatile uint8_t *)(&__MBAR[0xB14C]))
|
||||
#define MCF_USB_EP1INSR (*(volatile uint8_t *)(&__MBAR[0xB14D]))
|
||||
#define MCF_USB_EP1INSFR (*(volatile uint16_t*)(&__MBAR[0xB156]))
|
||||
#define MCF_USB_EP2OUTACR (*(volatile uint8_t *)(&__MBAR[0xB161]))
|
||||
#define MCF_USB_EP2OUTMPSR (*(volatile uint16_t*)(&__MBAR[0xB162]))
|
||||
#define MCF_USB_EP2OUTIFR (*(volatile uint8_t *)(&__MBAR[0xB164]))
|
||||
#define MCF_USB_EP2OUTSR (*(volatile uint8_t *)(&__MBAR[0xB165]))
|
||||
#define MCF_USB_EP2OUTSFR (*(volatile uint16_t*)(&__MBAR[0xB16E]))
|
||||
#define MCF_USB_EP2INACR (*(volatile uint8_t *)(&__MBAR[0xB179]))
|
||||
#define MCF_USB_EP2INMPSR (*(volatile uint16_t*)(&__MBAR[0xB17A]))
|
||||
#define MCF_USB_EP2INIFR (*(volatile uint8_t *)(&__MBAR[0xB17C]))
|
||||
#define MCF_USB_EP2INSR (*(volatile uint8_t *)(&__MBAR[0xB17D]))
|
||||
#define MCF_USB_EP2INSFR (*(volatile uint16_t*)(&__MBAR[0xB186]))
|
||||
#define MCF_USB_EP3OUTACR (*(volatile uint8_t *)(&__MBAR[0xB191]))
|
||||
#define MCF_USB_EP3OUTMPSR (*(volatile uint16_t*)(&__MBAR[0xB192]))
|
||||
#define MCF_USB_EP3OUTIFR (*(volatile uint8_t *)(&__MBAR[0xB194]))
|
||||
#define MCF_USB_EP3OUTSR (*(volatile uint8_t *)(&__MBAR[0xB195]))
|
||||
#define MCF_USB_EP3OUTSFR (*(volatile uint16_t*)(&__MBAR[0xB19E]))
|
||||
#define MCF_USB_EP3INACR (*(volatile uint8_t *)(&__MBAR[0xB1A9]))
|
||||
#define MCF_USB_EP3INMPSR (*(volatile uint16_t*)(&__MBAR[0xB1AA]))
|
||||
#define MCF_USB_EP3INIFR (*(volatile uint8_t *)(&__MBAR[0xB1AC]))
|
||||
#define MCF_USB_EP3INSR (*(volatile uint8_t *)(&__MBAR[0xB1AD]))
|
||||
#define MCF_USB_EP3INSFR (*(volatile uint16_t*)(&__MBAR[0xB1B6]))
|
||||
#define MCF_USB_EP4OUTACR (*(volatile uint8_t *)(&__MBAR[0xB1C1]))
|
||||
#define MCF_USB_EP4OUTMPSR (*(volatile uint16_t*)(&__MBAR[0xB1C2]))
|
||||
#define MCF_USB_EP4OUTIFR (*(volatile uint8_t *)(&__MBAR[0xB1C4]))
|
||||
#define MCF_USB_EP4OUTSR (*(volatile uint8_t *)(&__MBAR[0xB1C5]))
|
||||
#define MCF_USB_EP4OUTSFR (*(volatile uint16_t*)(&__MBAR[0xB1CE]))
|
||||
#define MCF_USB_EP4INACR (*(volatile uint8_t *)(&__MBAR[0xB1D9]))
|
||||
#define MCF_USB_EP4INMPSR (*(volatile uint16_t*)(&__MBAR[0xB1DA]))
|
||||
#define MCF_USB_EP4INIFR (*(volatile uint8_t *)(&__MBAR[0xB1DC]))
|
||||
#define MCF_USB_EP4INSR (*(volatile uint8_t *)(&__MBAR[0xB1DD]))
|
||||
#define MCF_USB_EP4INSFR (*(volatile uint16_t*)(&__MBAR[0xB1E6]))
|
||||
#define MCF_USB_EP5OUTACR (*(volatile uint8_t *)(&__MBAR[0xB1F1]))
|
||||
#define MCF_USB_EP5OUTMPSR (*(volatile uint16_t*)(&__MBAR[0xB1F2]))
|
||||
#define MCF_USB_EP5OUTIFR (*(volatile uint8_t *)(&__MBAR[0xB1F4]))
|
||||
#define MCF_USB_EP5OUTSR (*(volatile uint8_t *)(&__MBAR[0xB1F5]))
|
||||
#define MCF_USB_EP5OUTSFR (*(volatile uint16_t*)(&__MBAR[0xB1FE]))
|
||||
#define MCF_USB_EP5INACR (*(volatile uint8_t *)(&__MBAR[0xB209]))
|
||||
#define MCF_USB_EP5INMPSR (*(volatile uint16_t*)(&__MBAR[0xB20A]))
|
||||
#define MCF_USB_EP5INIFR (*(volatile uint8_t *)(&__MBAR[0xB20C]))
|
||||
#define MCF_USB_EP5INSR (*(volatile uint8_t *)(&__MBAR[0xB20D]))
|
||||
#define MCF_USB_EP5INSFR (*(volatile uint16_t*)(&__MBAR[0xB216]))
|
||||
#define MCF_USB_EP6OUTACR (*(volatile uint8_t *)(&__MBAR[0xB221]))
|
||||
#define MCF_USB_EP6OUTMPSR (*(volatile uint16_t*)(&__MBAR[0xB222]))
|
||||
#define MCF_USB_EP6OUTIFR (*(volatile uint8_t *)(&__MBAR[0xB224]))
|
||||
#define MCF_USB_EP6OUTSR (*(volatile uint8_t *)(&__MBAR[0xB225]))
|
||||
#define MCF_USB_EP6OUTSFR (*(volatile uint16_t*)(&__MBAR[0xB22E]))
|
||||
#define MCF_USB_EP6INACR (*(volatile uint8_t *)(&__MBAR[0xB239]))
|
||||
#define MCF_USB_EP6INMPSR (*(volatile uint16_t*)(&__MBAR[0xB23A]))
|
||||
#define MCF_USB_EP6INIFR (*(volatile uint8_t *)(&__MBAR[0xB23C]))
|
||||
#define MCF_USB_EP6INSR (*(volatile uint8_t *)(&__MBAR[0xB23D]))
|
||||
#define MCF_USB_EP6INSFR (*(volatile uint16_t*)(&__MBAR[0xB246]))
|
||||
#define MCF_USB_USBSR (*(volatile uint32_t*)(&__MBAR[0xB400]))
|
||||
#define MCF_USB_USBCR (*(volatile uint32_t*)(&__MBAR[0xB404]))
|
||||
#define MCF_USB_DRAMCR (*(volatile uint32_t*)(&__MBAR[0xB408]))
|
||||
#define MCF_USB_DRAMDR (*(volatile uint32_t*)(&__MBAR[0xB40C]))
|
||||
#define MCF_USB_USBISR (*(volatile uint32_t*)(&__MBAR[0xB410]))
|
||||
#define MCF_USB_USBIMR (*(volatile uint32_t*)(&__MBAR[0xB414]))
|
||||
#define MCF_USB_EP0STAT (*(volatile uint32_t*)(&__MBAR[0xB440]))
|
||||
#define MCF_USB_EP0ISR (*(volatile uint32_t*)(&__MBAR[0xB444]))
|
||||
#define MCF_USB_EP0IMR (*(volatile uint32_t*)(&__MBAR[0xB448]))
|
||||
#define MCF_USB_EP0FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB44C]))
|
||||
#define MCF_USB_EP0FDR (*(volatile uint32_t*)(&__MBAR[0xB450]))
|
||||
#define MCF_USB_EP0FSR (*(volatile uint32_t*)(&__MBAR[0xB454]))
|
||||
#define MCF_USB_EP0FCR (*(volatile uint32_t*)(&__MBAR[0xB458]))
|
||||
#define MCF_USB_EP0FAR (*(volatile uint32_t*)(&__MBAR[0xB45C]))
|
||||
#define MCF_USB_EP0FRP (*(volatile uint32_t*)(&__MBAR[0xB460]))
|
||||
#define MCF_USB_EP0FWP (*(volatile uint32_t*)(&__MBAR[0xB464]))
|
||||
#define MCF_USB_EP0LRFP (*(volatile uint32_t*)(&__MBAR[0xB468]))
|
||||
#define MCF_USB_EP0LWFP (*(volatile uint32_t*)(&__MBAR[0xB46C]))
|
||||
#define MCF_USB_EP1STAT (*(volatile uint32_t*)(&__MBAR[0xB470]))
|
||||
#define MCF_USB_EP1ISR (*(volatile uint32_t*)(&__MBAR[0xB474]))
|
||||
#define MCF_USB_EP1IMR (*(volatile uint32_t*)(&__MBAR[0xB478]))
|
||||
#define MCF_USB_EP1FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB47C]))
|
||||
#define MCF_USB_EP1FDR (*(volatile uint32_t*)(&__MBAR[0xB480]))
|
||||
#define MCF_USB_EP1FSR (*(volatile uint32_t*)(&__MBAR[0xB484]))
|
||||
#define MCF_USB_EP1FCR (*(volatile uint32_t*)(&__MBAR[0xB488]))
|
||||
#define MCF_USB_EP1FAR (*(volatile uint32_t*)(&__MBAR[0xB48C]))
|
||||
#define MCF_USB_EP1FRP (*(volatile uint32_t*)(&__MBAR[0xB490]))
|
||||
#define MCF_USB_EP1FWP (*(volatile uint32_t*)(&__MBAR[0xB494]))
|
||||
#define MCF_USB_EP1LRFP (*(volatile uint32_t*)(&__MBAR[0xB498]))
|
||||
#define MCF_USB_EP1LWFP (*(volatile uint32_t*)(&__MBAR[0xB49C]))
|
||||
#define MCF_USB_EP2STAT (*(volatile uint32_t*)(&__MBAR[0xB4A0]))
|
||||
#define MCF_USB_EP2ISR (*(volatile uint32_t*)(&__MBAR[0xB4A4]))
|
||||
#define MCF_USB_EP2IMR (*(volatile uint32_t*)(&__MBAR[0xB4A8]))
|
||||
#define MCF_USB_EP2FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB4AC]))
|
||||
#define MCF_USB_EP2FDR (*(volatile uint32_t*)(&__MBAR[0xB4B0]))
|
||||
#define MCF_USB_EP2FSR (*(volatile uint32_t*)(&__MBAR[0xB4B4]))
|
||||
#define MCF_USB_EP2FCR (*(volatile uint32_t*)(&__MBAR[0xB4B8]))
|
||||
#define MCF_USB_EP2FAR (*(volatile uint32_t*)(&__MBAR[0xB4BC]))
|
||||
#define MCF_USB_EP2FRP (*(volatile uint32_t*)(&__MBAR[0xB4C0]))
|
||||
#define MCF_USB_EP2FWP (*(volatile uint32_t*)(&__MBAR[0xB4C4]))
|
||||
#define MCF_USB_EP2LRFP (*(volatile uint32_t*)(&__MBAR[0xB4C8]))
|
||||
#define MCF_USB_EP2LWFP (*(volatile uint32_t*)(&__MBAR[0xB4CC]))
|
||||
#define MCF_USB_EP3STAT (*(volatile uint32_t*)(&__MBAR[0xB4D0]))
|
||||
#define MCF_USB_EP3ISR (*(volatile uint32_t*)(&__MBAR[0xB4D4]))
|
||||
#define MCF_USB_EP3IMR (*(volatile uint32_t*)(&__MBAR[0xB4D8]))
|
||||
#define MCF_USB_EP3FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB4DC]))
|
||||
#define MCF_USB_EP3FDR (*(volatile uint32_t*)(&__MBAR[0xB4E0]))
|
||||
#define MCF_USB_EP3FSR (*(volatile uint32_t*)(&__MBAR[0xB4E4]))
|
||||
#define MCF_USB_EP3FCR (*(volatile uint32_t*)(&__MBAR[0xB4E8]))
|
||||
#define MCF_USB_EP3FAR (*(volatile uint32_t*)(&__MBAR[0xB4EC]))
|
||||
#define MCF_USB_EP3FRP (*(volatile uint32_t*)(&__MBAR[0xB4F0]))
|
||||
#define MCF_USB_EP3FWP (*(volatile uint32_t*)(&__MBAR[0xB4F4]))
|
||||
#define MCF_USB_EP3LRFP (*(volatile uint32_t*)(&__MBAR[0xB4F8]))
|
||||
#define MCF_USB_EP3LWFP (*(volatile uint32_t*)(&__MBAR[0xB4FC]))
|
||||
#define MCF_USB_EP4STAT (*(volatile uint32_t*)(&__MBAR[0xB500]))
|
||||
#define MCF_USB_EP4ISR (*(volatile uint32_t*)(&__MBAR[0xB504]))
|
||||
#define MCF_USB_EP4IMR (*(volatile uint32_t*)(&__MBAR[0xB508]))
|
||||
#define MCF_USB_EP4FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB50C]))
|
||||
#define MCF_USB_EP4FDR (*(volatile uint32_t*)(&__MBAR[0xB510]))
|
||||
#define MCF_USB_EP4FSR (*(volatile uint32_t*)(&__MBAR[0xB514]))
|
||||
#define MCF_USB_EP4FCR (*(volatile uint32_t*)(&__MBAR[0xB518]))
|
||||
#define MCF_USB_EP4FAR (*(volatile uint32_t*)(&__MBAR[0xB51C]))
|
||||
#define MCF_USB_EP4FRP (*(volatile uint32_t*)(&__MBAR[0xB520]))
|
||||
#define MCF_USB_EP4FWP (*(volatile uint32_t*)(&__MBAR[0xB524]))
|
||||
#define MCF_USB_EP4LRFP (*(volatile uint32_t*)(&__MBAR[0xB528]))
|
||||
#define MCF_USB_EP4LWFP (*(volatile uint32_t*)(&__MBAR[0xB52C]))
|
||||
#define MCF_USB_EP5STAT (*(volatile uint32_t*)(&__MBAR[0xB530]))
|
||||
#define MCF_USB_EP5ISR (*(volatile uint32_t*)(&__MBAR[0xB534]))
|
||||
#define MCF_USB_EP5IMR (*(volatile uint32_t*)(&__MBAR[0xB538]))
|
||||
#define MCF_USB_EP5FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB53C]))
|
||||
#define MCF_USB_EP5FDR (*(volatile uint32_t*)(&__MBAR[0xB540]))
|
||||
#define MCF_USB_EP5FSR (*(volatile uint32_t*)(&__MBAR[0xB544]))
|
||||
#define MCF_USB_EP5FCR (*(volatile uint32_t*)(&__MBAR[0xB548]))
|
||||
#define MCF_USB_EP5FAR (*(volatile uint32_t*)(&__MBAR[0xB54C]))
|
||||
#define MCF_USB_EP5FRP (*(volatile uint32_t*)(&__MBAR[0xB550]))
|
||||
#define MCF_USB_EP5FWP (*(volatile uint32_t*)(&__MBAR[0xB554]))
|
||||
#define MCF_USB_EP5LRFP (*(volatile uint32_t*)(&__MBAR[0xB558]))
|
||||
#define MCF_USB_EP5LWFP (*(volatile uint32_t*)(&__MBAR[0xB55C]))
|
||||
#define MCF_USB_EP6STAT (*(volatile uint32_t*)(&__MBAR[0xB560]))
|
||||
#define MCF_USB_EP6ISR (*(volatile uint32_t*)(&__MBAR[0xB564]))
|
||||
#define MCF_USB_EP6IMR (*(volatile uint32_t*)(&__MBAR[0xB568]))
|
||||
#define MCF_USB_EP6FRCFGR (*(volatile uint32_t*)(&__MBAR[0xB56C]))
|
||||
#define MCF_USB_EP6FDR (*(volatile uint32_t*)(&__MBAR[0xB570]))
|
||||
#define MCF_USB_EP6FSR (*(volatile uint32_t*)(&__MBAR[0xB574]))
|
||||
#define MCF_USB_EP6FCR (*(volatile uint32_t*)(&__MBAR[0xB578]))
|
||||
#define MCF_USB_EP6FAR (*(volatile uint32_t*)(&__MBAR[0xB57C]))
|
||||
#define MCF_USB_EP6FRP (*(volatile uint32_t*)(&__MBAR[0xB580]))
|
||||
#define MCF_USB_EP6FWP (*(volatile uint32_t*)(&__MBAR[0xB584]))
|
||||
#define MCF_USB_EP6LRFP (*(volatile uint32_t*)(&__MBAR[0xB588]))
|
||||
#define MCF_USB_EP6LWFP (*(volatile uint32_t*)(&__MBAR[0xB58C]))
|
||||
#define MCF_USB_IFR(x) (*(volatile uint16_t*)(&__MBAR[0xB040 + ((x)*0x2)]))
|
||||
#define MCF_USB_EPOUTACR(x) (*(volatile uint8_t *)(&__MBAR[0xB131 + ((x-1)*0x30)]))
|
||||
#define MCF_USB_EPOUTMPSR(x) (*(volatile uint16_t*)(&__MBAR[0xB132 + ((x-1)*0x30)]))
|
||||
#define MCF_USB_EPOUTIFR(x) (*(volatile uint8_t *)(&__MBAR[0xB134 + ((x-1)*0x30)]))
|
||||
#define MCF_USB_EPOUTSR(x) (*(volatile uint8_t *)(&__MBAR[0xB135 + ((x-1)*0x30)]))
|
||||
#define MCF_USB_EPOUTSFR(x) (*(volatile uint16_t*)(&__MBAR[0xB13E + ((x-1)*0x30)]))
|
||||
#define MCF_USB_EPINACR(x) (*(volatile uint8_t *)(&__MBAR[0xB149 + ((x-1)*0x30)]))
|
||||
#define MCF_USB_EPINMPSR(x) (*(volatile uint16_t*)(&__MBAR[0xB14A + ((x-1)*0x30)]))
|
||||
#define MCF_USB_EPINIFR(x) (*(volatile uint8_t *)(&__MBAR[0xB14C + ((x-1)*0x30)]))
|
||||
#define MCF_USB_EPINSR(x) (*(volatile uint8_t *)(&__MBAR[0xB14D + ((x-1)*0x30)]))
|
||||
#define MCF_USB_EPINSFR(x) (*(volatile uint16_t*)(&__MBAR[0xB156 + ((x-1)*0x30)]))
|
||||
#define MCF_USB_EPSTAT(x) (*(volatile uint32_t*)(&__MBAR[0xB440 + ((x)*0x30)]))
|
||||
#define MCF_USB_EPISR(x) (*(volatile uint32_t*)(&__MBAR[0xB444 + ((x)*0x30)]))
|
||||
#define MCF_USB_EPIMR(x) (*(volatile uint32_t*)(&__MBAR[0xB448 + ((x)*0x30)]))
|
||||
#define MCF_USB_EPFRCFGR(x) (*(volatile uint32_t*)(&__MBAR[0xB44C + ((x)*0x30)]))
|
||||
#define MCF_USB_EPFDR(x) (*(volatile uint32_t*)(&__MBAR[0xB450 + ((x)*0x30)]))
|
||||
#define MCF_USB_EPFSR(x) (*(volatile uint32_t*)(&__MBAR[0xB454 + ((x)*0x30)]))
|
||||
#define MCF_USB_EPFCR(x) (*(volatile uint32_t*)(&__MBAR[0xB458 + ((x)*0x30)]))
|
||||
#define MCF_USB_EPFAR(x) (*(volatile uint32_t*)(&__MBAR[0xB45C + ((x)*0x30)]))
|
||||
#define MCF_USB_EPFRP(x) (*(volatile uint32_t*)(&__MBAR[0xB460 + ((x)*0x30)]))
|
||||
#define MCF_USB_EPFWP(x) (*(volatile uint32_t*)(&__MBAR[0xB464 + ((x)*0x30)]))
|
||||
#define MCF_USB_EPLRFP(x) (*(volatile uint32_t*)(&__MBAR[0xB468 + ((x)*0x30)]))
|
||||
#define MCF_USB_EPLWFP(x) (*(volatile uint32_t*)(&__MBAR[0xB46C + ((x)*0x30)]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_USBAISR */
|
||||
#define MCF_USB_USBAISR_SETUP (0x1)
|
||||
#define MCF_USB_USBAISR_IN (0x2)
|
||||
#define MCF_USB_USBAISR_OUT (0x4)
|
||||
#define MCF_USB_USBAISR_EPHALT (0x8)
|
||||
#define MCF_USB_USBAISR_TRANSERR (0x10)
|
||||
#define MCF_USB_USBAISR_ACK (0x20)
|
||||
#define MCF_USB_USBAISR_CTROVFL (0x40)
|
||||
#define MCF_USB_USBAISR_EPSTALL (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_USBAIMR */
|
||||
#define MCF_USB_USBAIMR_SETUPEN (0x1)
|
||||
#define MCF_USB_USBAIMR_INEN (0x2)
|
||||
#define MCF_USB_USBAIMR_OUTEN (0x4)
|
||||
#define MCF_USB_USBAIMR_EPHALTEN (0x8)
|
||||
#define MCF_USB_USBAIMR_TRANSERREN (0x10)
|
||||
#define MCF_USB_USBAIMR_ACKEN (0x20)
|
||||
#define MCF_USB_USBAIMR_CTROVFLEN (0x40)
|
||||
#define MCF_USB_USBAIMR_EPSTALLEN (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_EPINFO */
|
||||
#define MCF_USB_EPINFO_EPDIR (0x1)
|
||||
#define MCF_USB_EPINFO_EPNUM(x) (((x)&0x7)<<0x1)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_CFGR */
|
||||
#define MCF_USB_CFGR_Configuration_Value(x) (((x)&0xFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_CFGAR */
|
||||
#define MCF_USB_CFGAR_RESERVED (0xA0)
|
||||
#define MCF_USB_CFGAR_RMTWKEUP (0xE0)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_SPEEDR */
|
||||
#define MCF_USB_SPEEDR_SPEED(x) (((x)&0x3)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_FRMNUMR */
|
||||
#define MCF_USB_FRMNUMR_FRMNUM(x) (((x)&0xFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_EPTNR */
|
||||
#define MCF_USB_EPTNR_EP1T(x) (((x)&0x3)<<0)
|
||||
#define MCF_USB_EPTNR_EP2T(x) (((x)&0x3)<<0x2)
|
||||
#define MCF_USB_EPTNR_EP3T(x) (((x)&0x3)<<0x4)
|
||||
#define MCF_USB_EPTNR_EP4T(x) (((x)&0x3)<<0x6)
|
||||
#define MCF_USB_EPTNR_EP5T(x) (((x)&0x3)<<0x8)
|
||||
#define MCF_USB_EPTNR_EP6T(x) (((x)&0x3)<<0xA)
|
||||
#define MCF_USB_EPTNR_EPnT1 (0)
|
||||
#define MCF_USB_EPTNR_EPnT2 (0x1)
|
||||
#define MCF_USB_EPTNR_EPnT3 (0x2)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_IFUR */
|
||||
#define MCF_USB_IFUR_ALTSET(x) (((x)&0xFF)<<0)
|
||||
#define MCF_USB_IFUR_IFNUM(x) (((x)&0xFF)<<0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_IFR */
|
||||
#define MCF_USB_IFR_ALTSET(x) (((x)&0xFF)<<0)
|
||||
#define MCF_USB_IFR_IFNUM(x) (((x)&0xFF)<<0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_PPCNT */
|
||||
#define MCF_USB_PPCNT_PPCNT(x) (((x)&0xFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_DPCNT */
|
||||
#define MCF_USB_DPCNT_DPCNT(x) (((x)&0xFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_CRCECNT */
|
||||
#define MCF_USB_CRCECNT_CRCECNT(x) (((x)&0xFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_BSECNT */
|
||||
#define MCF_USB_BSECNT_BSECNT(x) (((x)&0xFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_PIDECNT */
|
||||
#define MCF_USB_PIDECNT_PIDECNT(x) (((x)&0xFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_FRMECNT */
|
||||
#define MCF_USB_FRMECNT_FRMECNT(x) (((x)&0xFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_TXPCNT */
|
||||
#define MCF_USB_TXPCNT_TXPCNT(x) (((x)&0xFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_CNTOVR */
|
||||
#define MCF_USB_CNTOVR_PPCNT (0x1)
|
||||
#define MCF_USB_CNTOVR_DPCNT (0x2)
|
||||
#define MCF_USB_CNTOVR_CRCECNT (0x4)
|
||||
#define MCF_USB_CNTOVR_BSECNT (0x8)
|
||||
#define MCF_USB_CNTOVR_PIDECNT (0x10)
|
||||
#define MCF_USB_CNTOVR_FRMECNT (0x20)
|
||||
#define MCF_USB_CNTOVR_TXPCNT (0x40)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_EP0ACR */
|
||||
#define MCF_USB_EP0ACR_TTYPE(x) (((x)&0x3)<<0)
|
||||
#define MCF_USB_EP0ACR_TTYPE_CTRL (0)
|
||||
#define MCF_USB_EP0ACR_TTYPE_ISOC (0x1)
|
||||
#define MCF_USB_EP0ACR_TTYPE_BULK (0x2)
|
||||
#define MCF_USB_EP0ACR_TTYPE_INT (0x3)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_EP0MPSR */
|
||||
#define MCF_USB_EP0MPSR_MAXPKTSZ(x) (((x)&0x7FF)<<0)
|
||||
#define MCF_USB_EP0MPSR_ADDTRANS(x) (((x)&0x3)<<0xB)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_EP0IFR */
|
||||
#define MCF_USB_EP0IFR_IFNUM(x) (((x)&0xFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_EP0SR */
|
||||
#define MCF_USB_EP0SR_HALT (0x1)
|
||||
#define MCF_USB_EP0SR_ACTIVE (0x2)
|
||||
#define MCF_USB_EP0SR_PSTALL (0x4)
|
||||
#define MCF_USB_EP0SR_CCOMP (0x8)
|
||||
#define MCF_USB_EP0SR_TXZERO (0x20)
|
||||
#define MCF_USB_EP0SR_INT (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_BMRTR */
|
||||
#define MCF_USB_BMRTR_REC(x) (((x)&0x1F)<<0)
|
||||
#define MCF_USB_BMRTR_REC_DEVICE (0)
|
||||
#define MCF_USB_BMRTR_REC_INTERFACE (0x1)
|
||||
#define MCF_USB_BMRTR_REC_ENDPOINT (0x2)
|
||||
#define MCF_USB_BMRTR_REC_OTHER (0x3)
|
||||
#define MCF_USB_BMRTR_TYPE(x) (((x)&0x3)<<0x5)
|
||||
#define MCF_USB_BMRTR_TYPE_STANDARD (0)
|
||||
#define MCF_USB_BMRTR_TYPE_CLASS (0x20)
|
||||
#define MCF_USB_BMRTR_TYPE_VENDOR (0x40)
|
||||
#define MCF_USB_BMRTR_DIR (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_BRTR */
|
||||
#define MCF_USB_BRTR_BREQ(x) (((x)&0xFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_WVALUER */
|
||||
#define MCF_USB_WVALUER_WVALUE(x) (((x)&0xFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_WINDEXR */
|
||||
#define MCF_USB_WINDEXR_WINDEX(x) (((x)&0xFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_WLENGTHR */
|
||||
#define MCF_USB_WLENGTHR_WLENGTH(x) (((x)&0xFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_EPOUTACR */
|
||||
#define MCF_USB_EPOUTACR_TTYPE(x) (((x)&0x3)<<0)
|
||||
#define MCF_USB_EPOUTACR_TTYPE_ISOC (0x1)
|
||||
#define MCF_USB_EPOUTACR_TTYPE_BULK (0x2)
|
||||
#define MCF_USB_EPOUTACR_TTYPE_INT (0x3)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_EPOUTMPSR */
|
||||
#define MCF_USB_EPOUTMPSR_MAXPKTSZ(x) (((x)&0x7FF)<<0)
|
||||
#define MCF_USB_EPOUTMPSR_ADDTRANS(x) (((x)&0x3)<<0xB)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_EPOUTIFR */
|
||||
#define MCF_USB_EPOUTIFR_IFNUM(x) (((x)&0xFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_EPOUTSR */
|
||||
#define MCF_USB_EPOUTSR_HALT (0x1)
|
||||
#define MCF_USB_EPOUTSR_ACTIVE (0x2)
|
||||
#define MCF_USB_EPOUTSR_PSTALL (0x4)
|
||||
#define MCF_USB_EPOUTSR_CCOMP (0x8)
|
||||
#define MCF_USB_EPOUTSR_TXZERO (0x20)
|
||||
#define MCF_USB_EPOUTSR_INT (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_EPOUTSFR */
|
||||
#define MCF_USB_EPOUTSFR_FRMNUM(x) (((x)&0x7FF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_EPINACR */
|
||||
#define MCF_USB_EPINACR_TTYPE(x) (((x)&0x3)<<0)
|
||||
#define MCF_USB_EPINACR_TTYPE_ISOC (0x1)
|
||||
#define MCF_USB_EPINACR_TTYPE_BULK (0x2)
|
||||
#define MCF_USB_EPINACR_TTYPE_INT (0x3)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_EPINMPSR */
|
||||
#define MCF_USB_EPINMPSR_MAXPKTSZ(x) (((x)&0x7FF)<<0)
|
||||
#define MCF_USB_EPINMPSR_ADDTRANS(x) (((x)&0x3)<<0xB)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_EPINIFR */
|
||||
#define MCF_USB_EPINIFR_IFNUM(x) (((x)&0xFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_EPINSR */
|
||||
#define MCF_USB_EPINSR_HALT (0x1)
|
||||
#define MCF_USB_EPINSR_ACTIVE (0x2)
|
||||
#define MCF_USB_EPINSR_PSTALL (0x4)
|
||||
#define MCF_USB_EPINSR_CCOMP (0x8)
|
||||
#define MCF_USB_EPINSR_TXZERO (0x20)
|
||||
#define MCF_USB_EPINSR_INT (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_EPINSFR */
|
||||
#define MCF_USB_EPINSFR_FRMNUM(x) (((x)&0x7FF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_USBSR */
|
||||
#define MCF_USB_USBSR_ISOERREP(x) (((x)&0xF)<<0)
|
||||
#define MCF_USB_USBSR_SUSP (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_USBCR */
|
||||
#define MCF_USB_USBCR_RESUME (0x1)
|
||||
#define MCF_USB_USBCR_APPLOCK (0x2)
|
||||
#define MCF_USB_USBCR_RST (0x4)
|
||||
#define MCF_USB_USBCR_RAMEN (0x8)
|
||||
#define MCF_USB_USBCR_RAMSPLIT (0x20)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_DRAMCR */
|
||||
#define MCF_USB_DRAMCR_DADR(x) (((x)&0x3FF)<<0)
|
||||
#define MCF_USB_DRAMCR_DSIZE(x) (((x)&0x7FF)<<0x10)
|
||||
#define MCF_USB_DRAMCR_BSY (0x40000000)
|
||||
#define MCF_USB_DRAMCR_START (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_DRAMDR */
|
||||
#define MCF_USB_DRAMDR_DDAT(x) (((x)&0xFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_USBISR */
|
||||
#define MCF_USB_USBISR_ISOERR (0x1)
|
||||
#define MCF_USB_USBISR_FTUNLCK (0x2)
|
||||
#define MCF_USB_USBISR_SUSP (0x4)
|
||||
#define MCF_USB_USBISR_RES (0x8)
|
||||
#define MCF_USB_USBISR_UPDSOF (0x10)
|
||||
#define MCF_USB_USBISR_RSTSTOP (0x20)
|
||||
#define MCF_USB_USBISR_SOF (0x40)
|
||||
#define MCF_USB_USBISR_MSOF (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_USBIMR */
|
||||
#define MCF_USB_USBIMR_ISOERR (0x1)
|
||||
#define MCF_USB_USBIMR_FTUNLCK (0x2)
|
||||
#define MCF_USB_USBIMR_SUSP (0x4)
|
||||
#define MCF_USB_USBIMR_RES (0x8)
|
||||
#define MCF_USB_USBIMR_UPDSOF (0x10)
|
||||
#define MCF_USB_USBIMR_RSTSTOP (0x20)
|
||||
#define MCF_USB_USBIMR_SOF (0x40)
|
||||
#define MCF_USB_USBIMR_MSOF (0x80)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_EPSTAT */
|
||||
#define MCF_USB_EPSTAT_RST (0x1)
|
||||
#define MCF_USB_EPSTAT_FLUSH (0x2)
|
||||
#define MCF_USB_EPSTAT_DIR (0x80)
|
||||
#define MCF_USB_EPSTAT_BYTECNT(x) (((x)&0xFFF)<<0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_EPISR */
|
||||
#define MCF_USB_EPISR_EOF (0x1)
|
||||
#define MCF_USB_EPISR_EOT (0x4)
|
||||
#define MCF_USB_EPISR_FIFOLO (0x10)
|
||||
#define MCF_USB_EPISR_FIFOHI (0x20)
|
||||
#define MCF_USB_EPISR_ERR (0x40)
|
||||
#define MCF_USB_EPISR_EMT (0x80)
|
||||
#define MCF_USB_EPISR_FU (0x100)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_EPIMR */
|
||||
#define MCF_USB_EPIMR_EOF (0x1)
|
||||
#define MCF_USB_EPIMR_EOT (0x4)
|
||||
#define MCF_USB_EPIMR_FIFOLO (0x10)
|
||||
#define MCF_USB_EPIMR_FIFOHI (0x20)
|
||||
#define MCF_USB_EPIMR_ERR (0x40)
|
||||
#define MCF_USB_EPIMR_EMT (0x80)
|
||||
#define MCF_USB_EPIMR_FU (0x100)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_EPFRCFGR */
|
||||
#define MCF_USB_EPFRCFGR_DEPTH(x) (((x)&0x1FFF)<<0)
|
||||
#define MCF_USB_EPFRCFGR_BASE(x) (((x)&0xFFF)<<0x10)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_EPFDR */
|
||||
#define MCF_USB_EPFDR_RX_TXDATA(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_EPFSR */
|
||||
#define MCF_USB_EPFSR_EMT (0x10000)
|
||||
#define MCF_USB_EPFSR_ALRM (0x20000)
|
||||
#define MCF_USB_EPFSR_FU (0x40000)
|
||||
#define MCF_USB_EPFSR_FR (0x80000)
|
||||
#define MCF_USB_EPFSR_OF (0x100000)
|
||||
#define MCF_USB_EPFSR_UF (0x200000)
|
||||
#define MCF_USB_EPFSR_RXW (0x400000)
|
||||
#define MCF_USB_EPFSR_FAE (0x800000)
|
||||
#define MCF_USB_EPFSR_FRM(x) (((x)&0xF)<<0x18)
|
||||
#define MCF_USB_EPFSR_TXW (0x40000000)
|
||||
#define MCF_USB_EPFSR_IP (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_EPFCR */
|
||||
#define MCF_USB_EPFCR_COUNTER(x) (((x)&0xFFFF)<<0)
|
||||
#define MCF_USB_EPFCR_TXWMSK (0x40000)
|
||||
#define MCF_USB_EPFCR_OFMSK (0x80000)
|
||||
#define MCF_USB_EPFCR_UFMSK (0x100000)
|
||||
#define MCF_USB_EPFCR_RXWMSK (0x200000)
|
||||
#define MCF_USB_EPFCR_FAEMSK (0x400000)
|
||||
#define MCF_USB_EPFCR_IPMSK (0x800000)
|
||||
#define MCF_USB_EPFCR_GR(x) (((x)&0x7)<<0x18)
|
||||
#define MCF_USB_EPFCR_FRM (0x8000000)
|
||||
#define MCF_USB_EPFCR_TMR (0x10000000)
|
||||
#define MCF_USB_EPFCR_WFR (0x20000000)
|
||||
#define MCF_USB_EPFCR_SHAD (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_EPFAR */
|
||||
#define MCF_USB_EPFAR_ALRMP(x) (((x)&0xFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_EPFRP */
|
||||
#define MCF_USB_EPFRP_RP(x) (((x)&0xFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_EPFWP */
|
||||
#define MCF_USB_EPFWP_WP(x) (((x)&0xFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_EPLRFP */
|
||||
#define MCF_USB_EPLRFP_LRFP(x) (((x)&0xFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_USB_EPLWFP */
|
||||
#define MCF_USB_EPLWFP_LWFP(x) (((x)&0xFFF)<<0)
|
||||
|
||||
|
||||
#endif /* __MCF5475_USB_H__ */
|
||||
@@ -1,101 +0,0 @@
|
||||
/* Coldfire C Header File
|
||||
* Copyright Freescale Semiconductor Inc
|
||||
* All rights reserved.
|
||||
*
|
||||
* 2008/05/23 Revision: 0.81
|
||||
*
|
||||
* (c) Copyright UNIS, a.s. 1997-2008
|
||||
* UNIS, a.s.
|
||||
* Jundrovska 33
|
||||
* 624 00 Brno
|
||||
* Czech Republic
|
||||
* http : www.processorexpert.com
|
||||
* mail : info@processorexpert.com
|
||||
*/
|
||||
|
||||
#ifndef __MCF5475_XLB_H__
|
||||
#define __MCF5475_XLB_H__
|
||||
|
||||
|
||||
/*********************************************************************
|
||||
*
|
||||
* XL Bus Arbiter (XLB)
|
||||
*
|
||||
*********************************************************************/
|
||||
|
||||
/* Register read/write macros */
|
||||
#define MCF_XLB_XARB_CFG (*(volatile uint32_t*)(&_MBAR[0x240]))
|
||||
#define MCF_XLB_XARB_VER (*(volatile uint32_t*)(&_MBAR[0x244]))
|
||||
#define MCF_XLB_XARB_SR (*(volatile uint32_t*)(&_MBAR[0x248]))
|
||||
#define MCF_XLB_XARB_IMR (*(volatile uint32_t*)(&_MBAR[0x24C]))
|
||||
#define MCF_XLB_XARB_ADRCAP (*(volatile uint32_t*)(&_MBAR[0x250]))
|
||||
#define MCF_XLB_XARB_SIGCAP (*(volatile uint32_t*)(&_MBAR[0x254]))
|
||||
#define MCF_XLB_XARB_ADRTO (*(volatile uint32_t*)(&_MBAR[0x258]))
|
||||
#define MCF_XLB_XARB_DATTO (*(volatile uint32_t*)(&_MBAR[0x25C]))
|
||||
#define MCF_XLB_XARB_BUSTO (*(volatile uint32_t*)(&_MBAR[0x260]))
|
||||
#define MCF_XLB_XARB_PRIEN (*(volatile uint32_t*)(&_MBAR[0x264]))
|
||||
#define MCF_XLB_XARB_PRI (*(volatile uint32_t*)(&_MBAR[0x268]))
|
||||
|
||||
|
||||
/* Bit definitions and macros for MCF_XLB_XARB_CFG */
|
||||
#define MCF_XLB_XARB_CFG_AT (0x2)
|
||||
#define MCF_XLB_XARB_CFG_DT (0x4)
|
||||
#define MCF_XLB_XARB_CFG_BA (0x8)
|
||||
#define MCF_XLB_XARB_CFG_PM(x) (((x)&0x3)<<0x5)
|
||||
#define MCF_XLB_XARB_CFG_SP(x) (((x)&0x7)<<0x8)
|
||||
#define MCF_XLB_XARB_CFG_PLDIS (0x80000000)
|
||||
|
||||
/* Bit definitions and macros for MCF_XLB_XARB_VER */
|
||||
#define MCF_XLB_XARB_VER_VER(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_XLB_XARB_SR */
|
||||
#define MCF_XLB_XARB_SR_AT (0x1)
|
||||
#define MCF_XLB_XARB_SR_DT (0x2)
|
||||
#define MCF_XLB_XARB_SR_BA (0x4)
|
||||
#define MCF_XLB_XARB_SR_TTM (0x8)
|
||||
#define MCF_XLB_XARB_SR_ECW (0x10)
|
||||
#define MCF_XLB_XARB_SR_TTR (0x20)
|
||||
#define MCF_XLB_XARB_SR_TTA (0x40)
|
||||
#define MCF_XLB_XARB_SR_MM (0x80)
|
||||
#define MCF_XLB_XARB_SR_SEA (0x100)
|
||||
|
||||
/* Bit definitions and macros for MCF_XLB_XARB_IMR */
|
||||
#define MCF_XLB_XARB_IMR_ATE (0x1)
|
||||
#define MCF_XLB_XARB_IMR_DTE (0x2)
|
||||
#define MCF_XLB_XARB_IMR_BAE (0x4)
|
||||
#define MCF_XLB_XARB_IMR_TTME (0x8)
|
||||
#define MCF_XLB_XARB_IMR_ECWE (0x10)
|
||||
#define MCF_XLB_XARB_IMR_TTRE (0x20)
|
||||
#define MCF_XLB_XARB_IMR_TTAE (0x40)
|
||||
#define MCF_XLB_XARB_IMR_MME (0x80)
|
||||
#define MCF_XLB_XARB_IMR_SEAE (0x100)
|
||||
|
||||
/* Bit definitions and macros for MCF_XLB_XARB_ADRCAP */
|
||||
#define MCF_XLB_XARB_ADRCAP_ADRCAP(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_XLB_XARB_SIGCAP */
|
||||
#define MCF_XLB_XARB_SIGCAP_TT(x) (((x)&0x1F)<<0)
|
||||
#define MCF_XLB_XARB_SIGCAP_TBST (0x20)
|
||||
#define MCF_XLB_XARB_SIGCAP_TSIZ(x) (((x)&0x7)<<0x7)
|
||||
|
||||
/* Bit definitions and macros for MCF_XLB_XARB_ADRTO */
|
||||
#define MCF_XLB_XARB_ADRTO_ADRTO(x) (((x)&0xFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_XLB_XARB_DATTO */
|
||||
#define MCF_XLB_XARB_DATTO_DATTO(x) (((x)&0xFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_XLB_XARB_BUSTO */
|
||||
#define MCF_XLB_XARB_BUSTO_BUSTO(x) (((x)&0xFFFFFFFF)<<0)
|
||||
|
||||
/* Bit definitions and macros for MCF_XLB_XARB_PRIEN */
|
||||
#define MCF_XLB_XARB_PRIEN_M0 (0x1)
|
||||
#define MCF_XLB_XARB_PRIEN_M2 (0x4)
|
||||
#define MCF_XLB_XARB_PRIEN_M3 (0x8)
|
||||
|
||||
/* Bit definitions and macros for MCF_XLB_XARB_PRI */
|
||||
#define MCF_XLB_XARB_PRI_M0P(x) (((x)&0x7)<<0)
|
||||
#define MCF_XLB_XARB_PRI_M2P(x) (((x)&0x7)<<0x8)
|
||||
#define MCF_XLB_XARB_PRI_M3P(x) (((x)&0x7)<<0xC)
|
||||
|
||||
|
||||
#endif /* __MCF5475_XLB_H__ */
|
||||
@@ -1,12 +0,0 @@
|
||||
#ifndef _ACIA_H_
|
||||
#define _ACIA_H_
|
||||
|
||||
/*
|
||||
* ACIA registers
|
||||
*/
|
||||
#define keyctl 0xfffc00
|
||||
#define keybd 0xfffc02
|
||||
#define midictl 0xfffc04
|
||||
#define midi 0xfffc06
|
||||
|
||||
#endif /* _ACIA_H_ */
|
||||
@@ -1,85 +0,0 @@
|
||||
/*
|
||||
* File: am79c874.h
|
||||
* Purpose: Driver for the AM79C874 10/100 Ethernet PHY
|
||||
*
|
||||
* Notes:
|
||||
*/
|
||||
|
||||
#ifndef _AM79C874_H_
|
||||
#define _AM79C874_H_
|
||||
|
||||
|
||||
extern int am79c874_init(uint8_t fec_ch, uint8_t phy_addr, uint8_t speed, uint8_t duplex);
|
||||
|
||||
|
||||
/* MII Register Addresses */
|
||||
#define MII_AM79C874_CR 0 /* MII Management Control Register */
|
||||
#define MII_AM79C874_SR 1 /* MII Management Status Register */
|
||||
#define MII_AM79C874_PHYIDR1 2 /* PHY Identifier 1 Register */
|
||||
#define MII_AM79C874_PHYIDR2 3 /* PHY Identifier 2 Register */
|
||||
#define MII_AM79C874_ANAR 4 /* Auto-Negociation Advertissement Register */
|
||||
#define MII_AM79C874_ANLPAR 5 /* Auto-Negociation Link Partner Register */
|
||||
#define MII_AM79C874_ANER 6 /* Auto-Negociation Expansion Register */
|
||||
#define MII_AM79C874_ANNPTR 7 /* Next Page Advertisement Register */
|
||||
#define MII_AM79C874_MFR 16 /* Miscellaneous Feature Register */
|
||||
#define MII_AM79C874_ICSR 17 /* Interrupt/Status Register */
|
||||
#define MII_AM79C874_DR 18 /* Diagnostic Register */
|
||||
#define MII_AM79C874_PMLR 19 /* Power and Loopback Register */
|
||||
#define MII_AM79C874_MCR 21 /* ModeControl Register */
|
||||
#define MII_AM79C874_DC 23 /* Disconnect Counter */
|
||||
#define MII_AM79C874_REC 24 /* Recieve Error Counter */
|
||||
|
||||
/* Bit definitions and macros for MII_AM79C874_CR */
|
||||
#define MII_AM79C874_CR_RESET (0x8000)
|
||||
#define MII_AM79C874_CR_LOOP (0x4000)
|
||||
#define MII_AM79C874_CR_100MB (0x2000)
|
||||
#define MII_AM79C874_CR_AUTON (0x1000)
|
||||
#define MII_AM79C874_CR_POWD (0x0800)
|
||||
#define MII_AM79C874_CR_ISO (0x0400)
|
||||
#define MII_AM79C874_CR_RST_NEG (0x0200)
|
||||
#define MII_AM79C874_CR_DPLX (0x0100)
|
||||
#define MII_AM79C874_CR_COL_TST (0x0080)
|
||||
#define MII_AM79C874_CR_SPEED_MASK (0x2040)
|
||||
#define MII_AM79C874_CR_1000_MPS (0x0040)
|
||||
#define MII_AM79C874_CR_100_MPS (0x2000)
|
||||
#define MII_AM79C874_CR_10_MPS (0x0000)
|
||||
|
||||
/* Bit definitions and macros for MII_AM79C874_SR */
|
||||
#define MII_AM79C874_SR_100T4 (0x8000)
|
||||
#define MII_AM79C874_SR_100TXF (0x4000)
|
||||
#define MII_AM79C874_SR_100TXH (0x2000)
|
||||
#define MII_AM79C874_SR_10TF (0x1000)
|
||||
#define MII_AM79C874_SR_10TH (0x0800)
|
||||
#define MII_AM79C874_SR_PRE_SUP (0x0040)
|
||||
#define MII_AM79C874_SR_AUTN_COMP (0x0020)
|
||||
#define MII_AM79C874_SR_RF (0x0010)
|
||||
#define MII_AM79C874_SR_AUTN_ABLE (0x0008)
|
||||
#define MII_AM79C874_SR_LS (0x0004)
|
||||
#define MII_AM79C874_SR_JD (0x0002)
|
||||
#define MII_AM79C874_SR_EXT (0x0001)
|
||||
|
||||
/* Bit definitions and macros for MII_AM79C874_ANLPAR */
|
||||
#define MII_AM79C874_ANLPAR_NP (0x8000)
|
||||
#define MII_AM79C874_ANLPAR_ACK (0x4000)
|
||||
#define MII_AM79C874_ANLPAR_RF (0x2000)
|
||||
#define MII_AM79C874_ANLPAR_T4 (0x0200)
|
||||
#define MII_AM79C874_ANLPAR_TXFD (0x0100)
|
||||
#define MII_AM79C874_ANLPAR_TX (0x0080)
|
||||
#define MII_AM79C874_ANLPAR_10FD (0x0040)
|
||||
#define MII_AM79C874_ANLPAR_10 (0x0020)
|
||||
#define MII_AM79C874_ANLPAR_100 (0x0380)
|
||||
#define MII_AM79C874_ANLPAR_PSB_MASK (0x001F)
|
||||
#define MII_AM79C874_ANLPAR_PSB_802_3 (0x0001)
|
||||
#define MII_AM79C874_ANLPAR_PSB_802_9 (0x0002)
|
||||
|
||||
/* Bit definitions and macros for MII_AM79C874_DR */
|
||||
#define MII_AM79C874_DR_DPLX (0x0800)
|
||||
#define MII_AM79C874_DR_DATA_RATE (0x0400)
|
||||
#define MII_AM79C874_DR_RX_PASS (0x0200)
|
||||
#define MII_AM79C874_DR_RX_LOCK (0x0100)
|
||||
|
||||
#define AUTONEGLINK (MII_AM79C874_SR_AUTN_COMP | MII_AM79C874_SR_LS)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* _AM79C874_H_ */
|
||||
@@ -1,99 +0,0 @@
|
||||
/*
|
||||
* File: arp.h
|
||||
* Purpose: ARP definitions.
|
||||
*
|
||||
* Notes:
|
||||
*/
|
||||
|
||||
#ifndef _ARP_H
|
||||
#define _ARP_H
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
/*
|
||||
* This data definition is defined for Ethernet only!
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t ar_hrd;
|
||||
uint16_t ar_pro;
|
||||
uint8_t ar_hln;
|
||||
uint8_t ar_pln;
|
||||
uint16_t opcode;
|
||||
uint8_t ar_sha[6]; /* ethernet hw address */
|
||||
uint8_t ar_spa[4]; /* ip address */
|
||||
uint8_t ar_tha[6]; /* ethernet hw address */
|
||||
uint8_t ar_tpa[4]; /* ip address */
|
||||
} arp_frame_hdr;
|
||||
|
||||
#define ARP_HDR_LEN sizeof(arp_frame_hdr)
|
||||
|
||||
/*
|
||||
* ARP table entry definition. Note that this table only designed
|
||||
* with Ethernet and IP in mind.
|
||||
*/
|
||||
#define MAX_HWA_SIZE (6) /* 6 is enough for Ethernet address */
|
||||
#define MAX_PA_SIZE (4) /* 4 is enough for Protocol address */
|
||||
typedef struct
|
||||
{
|
||||
uint16_t protocol;
|
||||
uint8_t hwa_size;
|
||||
uint8_t hwa[MAX_HWA_SIZE];
|
||||
uint8_t pa_size;
|
||||
uint8_t pa[MAX_PA_SIZE];
|
||||
int longevity;
|
||||
} ARPENTRY;
|
||||
#define MAX_ARP_ENTRY (10)
|
||||
|
||||
typedef struct
|
||||
{
|
||||
unsigned int tab_size;
|
||||
ARPENTRY table[MAX_ARP_ENTRY];
|
||||
} ARP_INFO;
|
||||
|
||||
#define ARP_ENTRY_EMPTY (0)
|
||||
#define ARP_ENTRY_PERM (1)
|
||||
#define ARP_ENTRY_TEMP (2)
|
||||
|
||||
|
||||
#define ETHERNET (1)
|
||||
#define ARP_REQUEST (1)
|
||||
#define ARP_REPLY (2)
|
||||
|
||||
#define ARP_TIMEOUT (1) /* Timeout in seconds */
|
||||
|
||||
/* Protocol Header information */
|
||||
#define ARP_HDR_OFFSET ETH_HDR_LEN
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
uint8_t *
|
||||
arp_get_mypa (void);
|
||||
|
||||
uint8_t *
|
||||
arp_get_myha (void);
|
||||
|
||||
uint8_t *
|
||||
arp_get_broadcast (void);
|
||||
|
||||
void
|
||||
arp_merge (ARP_INFO *, uint16_t, int, uint8_t *, int, uint8_t *, int);
|
||||
|
||||
void
|
||||
arp_remove (ARP_INFO *, uint16_t, uint8_t *, uint8_t *);
|
||||
|
||||
void
|
||||
arp_request (NIF *, uint8_t *);
|
||||
|
||||
void
|
||||
arp_handler (NIF *, NBUF *);
|
||||
|
||||
uint8_t *
|
||||
arp_resolve (NIF *, uint16_t, uint8_t *);
|
||||
|
||||
void
|
||||
arp_init (ARP_INFO *);
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* _ARP_H */
|
||||
@@ -1,211 +0,0 @@
|
||||
/*
|
||||
* ATI PCI IDs from XFree86, kept here to make sync'ing with
|
||||
* XFree much simpler. Currently, this list is only used by
|
||||
* radeonfb
|
||||
*/
|
||||
|
||||
#define PCI_CHIP_RV380_3150 0x3150
|
||||
#define PCI_CHIP_RV380_3151 0x3151
|
||||
#define PCI_CHIP_RV380_3152 0x3152
|
||||
#define PCI_CHIP_RV380_3153 0x3153
|
||||
#define PCI_CHIP_RV380_3154 0x3154
|
||||
#define PCI_CHIP_RV380_3156 0x3156
|
||||
#define PCI_CHIP_RV380_3E50 0x3E50
|
||||
#define PCI_CHIP_RV380_3E51 0x3E51
|
||||
#define PCI_CHIP_RV380_3E52 0x3E52
|
||||
#define PCI_CHIP_RV380_3E53 0x3E53
|
||||
#define PCI_CHIP_RV380_3E54 0x3E54
|
||||
#define PCI_CHIP_RV380_3E56 0x3E56
|
||||
#define PCI_CHIP_RS100_4136 0x4136
|
||||
#define PCI_CHIP_RS200_4137 0x4137
|
||||
#define PCI_CHIP_R300_AD 0x4144
|
||||
#define PCI_CHIP_R300_AE 0x4145
|
||||
#define PCI_CHIP_R300_AF 0x4146
|
||||
#define PCI_CHIP_R300_AG 0x4147
|
||||
#define PCI_CHIP_R350_AH 0x4148
|
||||
#define PCI_CHIP_R350_AI 0x4149
|
||||
#define PCI_CHIP_R350_AJ 0x414A
|
||||
#define PCI_CHIP_R350_AK 0x414B
|
||||
#define PCI_CHIP_RV350_AP 0x4150
|
||||
#define PCI_CHIP_RV350_AQ 0x4151
|
||||
#define PCI_CHIP_RV360_AR 0x4152
|
||||
#define PCI_CHIP_RV350_AS 0x4153
|
||||
#define PCI_CHIP_RV350_AT 0x4154
|
||||
#define PCI_CHIP_RV350_AV 0x4156
|
||||
#define PCI_CHIP_MACH32 0x4158
|
||||
#define PCI_CHIP_RS250_4237 0x4237
|
||||
#define PCI_CHIP_R200_BB 0x4242
|
||||
#define PCI_CHIP_R200_BC 0x4243
|
||||
#define PCI_CHIP_RS100_4336 0x4336
|
||||
#define PCI_CHIP_RS200_4337 0x4337
|
||||
#define PCI_CHIP_MACH64CT 0x4354
|
||||
#define PCI_CHIP_MACH64CX 0x4358
|
||||
#define PCI_CHIP_RS250_4437 0x4437
|
||||
#define PCI_CHIP_MACH64ET 0x4554
|
||||
#define PCI_CHIP_MACH64GB 0x4742
|
||||
#define PCI_CHIP_MACH64GD 0x4744
|
||||
#define PCI_CHIP_MACH64GI 0x4749
|
||||
#define PCI_CHIP_MACH64GL 0x474C
|
||||
#define PCI_CHIP_MACH64GM 0x474D
|
||||
#define PCI_CHIP_MACH64GN 0x474E
|
||||
#define PCI_CHIP_MACH64GO 0x474F
|
||||
#define PCI_CHIP_MACH64GP 0x4750
|
||||
#define PCI_CHIP_MACH64GQ 0x4751
|
||||
#define PCI_CHIP_MACH64GR 0x4752
|
||||
#define PCI_CHIP_MACH64GS 0x4753
|
||||
#define PCI_CHIP_MACH64GT 0x4754
|
||||
#define PCI_CHIP_MACH64GU 0x4755
|
||||
#define PCI_CHIP_MACH64GV 0x4756
|
||||
#define PCI_CHIP_MACH64GW 0x4757
|
||||
#define PCI_CHIP_MACH64GX 0x4758
|
||||
#define PCI_CHIP_MACH64GY 0x4759
|
||||
#define PCI_CHIP_MACH64GZ 0x475A
|
||||
#define PCI_CHIP_RV250_Id 0x4964
|
||||
#define PCI_CHIP_RV250_Ie 0x4965
|
||||
#define PCI_CHIP_RV250_If 0x4966
|
||||
#define PCI_CHIP_RV250_Ig 0x4967
|
||||
#define PCI_CHIP_R420_JH 0x4A48
|
||||
#define PCI_CHIP_R420_JI 0x4A49
|
||||
#define PCI_CHIP_R420_JJ 0x4A4A
|
||||
#define PCI_CHIP_R420_JK 0x4A4B
|
||||
#define PCI_CHIP_R420_JL 0x4A4C
|
||||
#define PCI_CHIP_R420_JM 0x4A4D
|
||||
#define PCI_CHIP_R420_JN 0x4A4E
|
||||
#define PCI_CHIP_R420_JP 0x4A50
|
||||
#define PCI_CHIP_MACH64LB 0x4C42
|
||||
#define PCI_CHIP_MACH64LD 0x4C44
|
||||
#define PCI_CHIP_RAGE128LE 0x4C45
|
||||
#define PCI_CHIP_RAGE128LF 0x4C46
|
||||
#define PCI_CHIP_MACH64LG 0x4C47
|
||||
#define PCI_CHIP_MACH64LI 0x4C49
|
||||
#define PCI_CHIP_MACH64LM 0x4C4D
|
||||
#define PCI_CHIP_MACH64LN 0x4C4E
|
||||
#define PCI_CHIP_MACH64LP 0x4C50
|
||||
#define PCI_CHIP_MACH64LQ 0x4C51
|
||||
#define PCI_CHIP_MACH64LR 0x4C52
|
||||
#define PCI_CHIP_MACH64LS 0x4C53
|
||||
#define PCI_CHIP_MACH64LT 0x4C54
|
||||
#define PCI_CHIP_RADEON_LW 0x4C57
|
||||
#define PCI_CHIP_RADEON_LX 0x4C58
|
||||
#define PCI_CHIP_RADEON_LY 0x4C59
|
||||
#define PCI_CHIP_RADEON_LZ 0x4C5A
|
||||
#define PCI_CHIP_RV250_Ld 0x4C64
|
||||
#define PCI_CHIP_RV250_Le 0x4C65
|
||||
#define PCI_CHIP_RV250_Lf 0x4C66
|
||||
#define PCI_CHIP_RV250_Lg 0x4C67
|
||||
#define PCI_CHIP_RV250_Ln 0x4C6E
|
||||
#define PCI_CHIP_RAGE128MF 0x4D46
|
||||
#define PCI_CHIP_RAGE128ML 0x4D4C
|
||||
#define PCI_CHIP_R300_ND 0x4E44
|
||||
#define PCI_CHIP_R300_NE 0x4E45
|
||||
#define PCI_CHIP_R300_NF 0x4E46
|
||||
#define PCI_CHIP_R300_NG 0x4E47
|
||||
#define PCI_CHIP_R350_NH 0x4E48
|
||||
#define PCI_CHIP_R350_NI 0x4E49
|
||||
#define PCI_CHIP_R360_NJ 0x4E4A
|
||||
#define PCI_CHIP_R350_NK 0x4E4B
|
||||
#define PCI_CHIP_RV350_NP 0x4E50
|
||||
#define PCI_CHIP_RV350_NQ 0x4E51
|
||||
#define PCI_CHIP_RV350_NR 0x4E52
|
||||
#define PCI_CHIP_RV350_NS 0x4E53
|
||||
#define PCI_CHIP_RV350_NT 0x4E54
|
||||
#define PCI_CHIP_RV350_NV 0x4E56
|
||||
#define PCI_CHIP_RAGE128PA 0x5041
|
||||
#define PCI_CHIP_RAGE128PB 0x5042
|
||||
#define PCI_CHIP_RAGE128PC 0x5043
|
||||
#define PCI_CHIP_RAGE128PD 0x5044
|
||||
#define PCI_CHIP_RAGE128PE 0x5045
|
||||
#define PCI_CHIP_RAGE128PF 0x5046
|
||||
#define PCI_CHIP_RAGE128PG 0x5047
|
||||
#define PCI_CHIP_RAGE128PH 0x5048
|
||||
#define PCI_CHIP_RAGE128PI 0x5049
|
||||
#define PCI_CHIP_RAGE128PJ 0x504A
|
||||
#define PCI_CHIP_RAGE128PK 0x504B
|
||||
#define PCI_CHIP_RAGE128PL 0x504C
|
||||
#define PCI_CHIP_RAGE128PM 0x504D
|
||||
#define PCI_CHIP_RAGE128PN 0x504E
|
||||
#define PCI_CHIP_RAGE128PO 0x504F
|
||||
#define PCI_CHIP_RAGE128PP 0x5050
|
||||
#define PCI_CHIP_RAGE128PQ 0x5051
|
||||
#define PCI_CHIP_RAGE128PR 0x5052
|
||||
#define PCI_CHIP_RAGE128PS 0x5053
|
||||
#define PCI_CHIP_RAGE128PT 0x5054
|
||||
#define PCI_CHIP_RAGE128PU 0x5055
|
||||
#define PCI_CHIP_RAGE128PV 0x5056
|
||||
#define PCI_CHIP_RAGE128PW 0x5057
|
||||
#define PCI_CHIP_RAGE128PX 0x5058
|
||||
#define PCI_CHIP_RADEON_QD 0x5144
|
||||
#define PCI_CHIP_RADEON_QE 0x5145
|
||||
#define PCI_CHIP_RADEON_QF 0x5146
|
||||
#define PCI_CHIP_RADEON_QG 0x5147
|
||||
#define PCI_CHIP_R200_QH 0x5148
|
||||
#define PCI_CHIP_R200_QI 0x5149
|
||||
#define PCI_CHIP_R200_QJ 0x514A
|
||||
#define PCI_CHIP_R200_QK 0x514B
|
||||
#define PCI_CHIP_R200_QL 0x514C
|
||||
#define PCI_CHIP_R200_QM 0x514D
|
||||
#define PCI_CHIP_R200_QN 0x514E
|
||||
#define PCI_CHIP_R200_QO 0x514F
|
||||
#define PCI_CHIP_RV200_QW 0x5157
|
||||
#define PCI_CHIP_RV200_QX 0x5158
|
||||
#define PCI_CHIP_RV100_QY 0x5159
|
||||
#define PCI_CHIP_RV100_QZ 0x515A
|
||||
#define PCI_CHIP_RAGE128RE 0x5245
|
||||
#define PCI_CHIP_RAGE128RF 0x5246
|
||||
#define PCI_CHIP_RAGE128RG 0x5247
|
||||
#define PCI_CHIP_RAGE128RK 0x524B
|
||||
#define PCI_CHIP_RAGE128RL 0x524C
|
||||
#define PCI_CHIP_RAGE128SE 0x5345
|
||||
#define PCI_CHIP_RAGE128SF 0x5346
|
||||
#define PCI_CHIP_RAGE128SG 0x5347
|
||||
#define PCI_CHIP_RAGE128SH 0x5348
|
||||
#define PCI_CHIP_RAGE128SK 0x534B
|
||||
#define PCI_CHIP_RAGE128SL 0x534C
|
||||
#define PCI_CHIP_RAGE128SM 0x534D
|
||||
#define PCI_CHIP_RAGE128SN 0x534E
|
||||
#define PCI_CHIP_RAGE128TF 0x5446
|
||||
#define PCI_CHIP_RAGE128TL 0x544C
|
||||
#define PCI_CHIP_RAGE128TR 0x5452
|
||||
#define PCI_CHIP_RAGE128TS 0x5453
|
||||
#define PCI_CHIP_RAGE128TT 0x5454
|
||||
#define PCI_CHIP_RAGE128TU 0x5455
|
||||
#define PCI_CHIP_RV370_5460 0x5460
|
||||
#define PCI_CHIP_RV370_5461 0x5461
|
||||
#define PCI_CHIP_RV370_5462 0x5462
|
||||
#define PCI_CHIP_RV370_5463 0x5463
|
||||
#define PCI_CHIP_RV370_5464 0x5464
|
||||
#define PCI_CHIP_RV370_5465 0x5465
|
||||
#define PCI_CHIP_RV370_5466 0x5466
|
||||
#define PCI_CHIP_RV370_5467 0x5467
|
||||
#define PCI_CHIP_R423_UH 0x5548
|
||||
#define PCI_CHIP_R423_UI 0x5549
|
||||
#define PCI_CHIP_R423_UJ 0x554A
|
||||
#define PCI_CHIP_R423_UK 0x554B
|
||||
#define PCI_CHIP_R423_UQ 0x5551
|
||||
#define PCI_CHIP_R423_UR 0x5552
|
||||
#define PCI_CHIP_R423_UT 0x5554
|
||||
#define PCI_CHIP_MACH64VT 0x5654
|
||||
#define PCI_CHIP_MACH64VU 0x5655
|
||||
#define PCI_CHIP_MACH64VV 0x5656
|
||||
#define PCI_CHIP_RS300_5834 0x5834
|
||||
#define PCI_CHIP_RS300_5835 0x5835
|
||||
#define PCI_CHIP_RS300_5836 0x5836
|
||||
#define PCI_CHIP_RS300_5837 0x5837
|
||||
#define PCI_CHIP_RV370_5B60 0x5B60
|
||||
#define PCI_CHIP_RV370_5B61 0x5B61
|
||||
#define PCI_CHIP_RV370_5B62 0x5B62
|
||||
#define PCI_CHIP_RV370_5B63 0x5B63
|
||||
#define PCI_CHIP_RV370_5B64 0x5B64
|
||||
#define PCI_CHIP_RV370_5B65 0x5B65
|
||||
#define PCI_CHIP_RV370_5B66 0x5B66
|
||||
#define PCI_CHIP_RV370_5B67 0x5B67
|
||||
#define PCI_CHIP_RV280_5960 0x5960
|
||||
#define PCI_CHIP_RV280_5961 0x5961
|
||||
#define PCI_CHIP_RV280_5962 0x5962
|
||||
#define PCI_CHIP_RV280_5964 0x5964
|
||||
#define PCI_CHIP_RV280_5C61 0x5C61
|
||||
#define PCI_CHIP_RV280_5C63 0x5C63
|
||||
#define PCI_CHIP_R423_5D57 0x5D57
|
||||
#define PCI_CHIP_RS350_7834 0x7834
|
||||
#define PCI_CHIP_RS350_7835 0x7835
|
||||
|
||||
@@ -1,42 +0,0 @@
|
||||
/*
|
||||
*
|
||||
* This file is part of BaS_gcc.
|
||||
*
|
||||
* BaS_gcc is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* BaS_gcc is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef _BAS_PRINTF_H_
|
||||
#define _BAS_PRINTF_H_
|
||||
#include <stdarg.h>
|
||||
#include <stddef.h>
|
||||
#include "MCF5475.h"
|
||||
|
||||
extern void xvsnprintf(char *str, size_t size, const char *fmt, va_list va);
|
||||
extern void xvprintf(const char *fmt, va_list va);
|
||||
extern void xprintf(const char *fmt, ...);
|
||||
extern void xsnprintf(char *str, size_t size, const char *fmt, ...);
|
||||
extern int sprintf(char *str, const char *format, ...);
|
||||
|
||||
extern bool conoutstat(void);
|
||||
extern bool coninstat(void);
|
||||
extern void xputchar(int c);
|
||||
extern char xgetchar(void);
|
||||
|
||||
|
||||
extern void display_progress(void);
|
||||
extern void hexdump(uint8_t buffer[], int size);
|
||||
|
||||
|
||||
#endif /* _BAS_PRINTF_H_ */
|
||||
@@ -1,48 +0,0 @@
|
||||
/*
|
||||
* bas_string.h
|
||||
*
|
||||
* This file is part of BaS_gcc.
|
||||
*
|
||||
* BaS_gcc is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* BaS_gcc is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* Created on: 26.02.2013
|
||||
* Author: Markus Fröschle
|
||||
*/
|
||||
|
||||
#ifndef BAS_STRING_H_
|
||||
#define BAS_STRING_H_
|
||||
|
||||
#include <stddef.h>
|
||||
|
||||
extern int strncmp(const char *s1, const char *s2, size_t max);
|
||||
extern char *strcpy(char *dst, const char *src);
|
||||
char *strncpy(char *dst, const char *src, size_t max);
|
||||
extern int strcmp(const char *s1, const char *s2);
|
||||
extern size_t strlen(const char *str);
|
||||
extern char *strcat(char *dst, const char *src);
|
||||
extern char *strncat(char *dst, const char *src, size_t max);
|
||||
extern int atoi(const char *c);
|
||||
extern void *memcpy(void *dst, const void *src, size_t n);
|
||||
extern void *memmove(void *dst, const void *src, size_t n);
|
||||
extern void *memset(void *s, int c, size_t n);
|
||||
extern int memcmp(const void *s1, const void *s2, size_t max);
|
||||
extern void bzero(void *s, size_t n);
|
||||
|
||||
#define isdigit(c) (((c) >= '0') && ((c) <= '9'))
|
||||
#define isupper(c) ((c) >= 'A' && ((c) <= 'Z'))
|
||||
#define islower(c) ((c) >= 'a' && ((c) <= 'z'))
|
||||
#define isalpha(c) (isupper((c)) || islower(c))
|
||||
#define tolower(c) (isupper(c) ? ((c) + 'a' - 'A') : (c))
|
||||
|
||||
#endif /* BAS_STRING_H_ */
|
||||
@@ -1,35 +0,0 @@
|
||||
/*
|
||||
* bas_types.h
|
||||
*
|
||||
* Created on: 17.11.2012
|
||||
* Author: mfro
|
||||
*
|
||||
* This file is part of BaS_gcc.
|
||||
*
|
||||
* BaS_gcc is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* BaS_gcc is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* Copyright 2010 - 2012 F. Aschwanden
|
||||
* Copyright 2011 - 2012 V. Riviere
|
||||
* Copyright 2012 M. Froeschle
|
||||
*
|
||||
*/
|
||||
|
||||
#ifndef BAS_TYPES_H_
|
||||
#define BAS_TYPES_H_
|
||||
|
||||
#include <stdint.h>
|
||||
#include <stdbool.h>
|
||||
#include <stddef.h> /* for sizeof() etc. */
|
||||
|
||||
#endif /* BAS_TYPES_H_ */
|
||||
@@ -1,32 +0,0 @@
|
||||
/*
|
||||
* bas_utils.h
|
||||
*
|
||||
* This file is part of BaS_gcc.
|
||||
*
|
||||
* BaS_gcc is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* BaS_gcc is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* Created on: 26.02.2013
|
||||
* Author: Markus Fröschle
|
||||
*/
|
||||
|
||||
#ifndef _BAS_UTILS_H_
|
||||
#define _BAS_UTILS_H_
|
||||
|
||||
#define CLEAR_BIT(p,bit) p &= ~(bit)
|
||||
#define CLEAR_BIT_NO(p,nr) CLEAR_BIT(p, (1 << (nr)))
|
||||
|
||||
extern void write_pic_byte(uint8_t value);
|
||||
extern uint8_t read_pic_byte(void);
|
||||
|
||||
#endif /* _BAS_UTILS_H_ */
|
||||
@@ -1,71 +0,0 @@
|
||||
/*
|
||||
* File: bcm5222.h
|
||||
* Purpose: Driver for the BCM5222 10/100 Ethernet PHY
|
||||
*
|
||||
* Notes:
|
||||
*/
|
||||
|
||||
#ifndef _BCM5222_H_
|
||||
#define _BCM5222_H_
|
||||
|
||||
extern int bcm5222_init(uint8_t, uint8_t, uint8_t, uint8_t);
|
||||
extern void bcm5222_get_reg(uint16_t*, uint16_t*);
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
/* MII Register Addresses */
|
||||
#define BCM5222_CTRL (0x00)
|
||||
#define BCM5222_STAT (0x01)
|
||||
#define BCM5222_PHY_ID1 (0x02)
|
||||
#define BCM5222_PHY_ID2 (0x03)
|
||||
#define BCM5222_AN_ADV (0x04)
|
||||
#define BCM5222_AN_LINK_PAR (0x05)
|
||||
#define BCM5222_AN_EXP (0x06)
|
||||
#define BCM5222_AN_NPR (0x07)
|
||||
#define BCM5222_LINK_NPA (0x08)
|
||||
#define BCM5222_ACSR (0x18)
|
||||
|
||||
/* Bit definitions and macros for BCM5222_CTRL */
|
||||
#define BCM5222_CTRL_RESET (0x8000)
|
||||
#define BCM5222_CTRL_LOOP (0x4000)
|
||||
#define BCM5222_CTRL_SPEED (0x2000)
|
||||
#define BCM5222_CTRL_ANE (0x1000)
|
||||
#define BCM5222_CTRL_PD (0x0800)
|
||||
#define BCM5222_CTRL_ISOLATE (0x0400)
|
||||
#define BCM5222_CTRL_RESTART_AN (0x0200)
|
||||
#define BCM5222_CTRL_FDX (0x0100)
|
||||
#define BCM5222_CTRL_COL_TEST (0x0080)
|
||||
|
||||
|
||||
/* Bit definitions and macros for BCM5222_STAT */
|
||||
#define BCM5222_STAT_100BT4 (0x8000)
|
||||
#define BCM5222_STAT_100BTX_FDX (0x4000)
|
||||
#define BCM5222_STAT_100BTX (0x2000)
|
||||
#define BCM5222_STAT_10BT_FDX (0x1000)
|
||||
#define BCM5222_STAT_10BT (0x0800)
|
||||
#define BCM5222_STAT_NO_PREAMBLE (0x0040)
|
||||
#define BCM5222_STAT_AN_COMPLETE (0x0020)
|
||||
#define BCM5222_STAT_REMOTE_FAULT (0x0010)
|
||||
#define BCM5222_STAT_AN_ABILITY (0x0008)
|
||||
#define BCM5222_STAT_LINK (0x0004)
|
||||
#define BCM5222_STAT_JABBER (0x0002)
|
||||
#define BCM5222_STAT_EXTENDED (0x0001)
|
||||
|
||||
/* Bit definitions and macros for BCM5222_AN_ADV */
|
||||
#define BCM5222_AN_ADV_NEXT_PAGE (0x8001)
|
||||
#define BCM5222_AN_ADV_REM_FAULT (0x2001)
|
||||
#define BCM5222_AN_ADV_PAUSE (0x0401)
|
||||
#define BCM5222_AN_ADV_100BT4 (0x0201)
|
||||
#define BCM5222_AN_ADV_100BTX_FDX (0x0101)
|
||||
#define BCM5222_AN_ADV_100BTX (0x0081)
|
||||
#define BCM5222_AN_ADV_10BT_FDX (0x0041)
|
||||
#define BCM5222_AN_ADV_10BT (0x0021)
|
||||
#define BCM5222_AN_ADV_802_3 (0x0001)
|
||||
|
||||
/* Bit definitions and macros for BCM5222_ACSR */
|
||||
#define BCM5222_ACSR_100BTX (0x0002)
|
||||
#define BCM5222_ACSR_FDX (0x0001)
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#endif /* _BCM5222_H_ */
|
||||
@@ -1,69 +0,0 @@
|
||||
/*
|
||||
* File: bootp.h
|
||||
* Purpose: BOOTP definitions.
|
||||
*
|
||||
* Notes:
|
||||
*/
|
||||
|
||||
#ifndef _BOOTP_H_
|
||||
#define _BOOTP_H_
|
||||
|
||||
#define BOOTP_SERVER_PORT 67
|
||||
#define BOOTP_CLIENT_PORT 68
|
||||
|
||||
/* protocol header information */
|
||||
#define BOOTP_HDR_OFFSET (ETH_HDR_LEN + IP_HDR_SIZE + UDP_HDR_SIZE)
|
||||
|
||||
/* timeout in seconds */
|
||||
#define BOOTP_TIMEOUT 2
|
||||
|
||||
/* BOOTP connection status */
|
||||
|
||||
struct bootp_connection
|
||||
{
|
||||
bool open; /* connection established flag */
|
||||
NIF *nif; /* pointer to network interface */
|
||||
IP_ADDR server_ip; /* server IP address */
|
||||
};
|
||||
|
||||
/*
|
||||
* This data definition is defined for Ethernet only!
|
||||
*/
|
||||
struct bootp_packet
|
||||
{
|
||||
uint8_t type; /* bootp operation type */
|
||||
uint8_t htype; /* hardware type */
|
||||
uint8_t hlen; /* hardware address length */
|
||||
uint8_t hops; /* hops */
|
||||
uint32_t xid; /* transaction identifier */
|
||||
uint16_t secs; /* seconds since trying to boot */
|
||||
uint16_t flags; /* only broadcast flag in use */
|
||||
uint32_t cl_addr; /* client ip address. Set to all 0 on request */
|
||||
uint32_t yi_addr; /* this field contains the new IP */
|
||||
uint32_t gi_addr; /* gateway address */
|
||||
uint8_t ch_addr[16]; /* client hw address */
|
||||
uint8_t sname[64]; /* server name */
|
||||
uint8_t file[128]; /* name of bootfile */
|
||||
uint8_t vend[64]; /* vendor specific (see below) */
|
||||
};
|
||||
|
||||
#define BOOTP_PACKET_LEN (BOOTP_HDR_OFFSET + sizeof(struct bootp_packet))
|
||||
|
||||
/* possible values for type field */
|
||||
#define BOOTP_TYPE_BOOTREQUEST 1
|
||||
#define BOOTP_TYPE_BOOTREPLY 2
|
||||
|
||||
/* values for hardware type - we only use ethernet */
|
||||
#define BOOTP_HTYPE_ETHERNET 1
|
||||
|
||||
/* values for hlen - again only ethernet defined */
|
||||
#define BOOTP_HLEN_ETHERNET 6
|
||||
|
||||
/* values for flags - only broadcast flag in use */
|
||||
#define BOOTP_FLAGS_BROADCAST 1
|
||||
|
||||
extern void bootp_request(NIF *, uint8_t *);
|
||||
extern void bootp_handler(NIF *, NBUF *);
|
||||
//extern void bootp_init(BOOTP_INFO *);
|
||||
|
||||
#endif /* _BOOTP_H_ */
|
||||
@@ -1,89 +0,0 @@
|
||||
#ifndef _CACHE_H_
|
||||
#define _CACHE_H_
|
||||
|
||||
/*
|
||||
* cache.h
|
||||
*
|
||||
* This file is part of BaS_gcc.
|
||||
*
|
||||
* BaS_gcc is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* BaS_gcc is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* Copyright 2010 - 2012 F. Aschwanden
|
||||
* Copyright 2011 - 2012 V. Riviere
|
||||
* Copyright 2012 M. Froeschle
|
||||
*
|
||||
*/
|
||||
|
||||
#include <bas_types.h>
|
||||
|
||||
/*
|
||||
* CACR Cache Control Register
|
||||
*/
|
||||
#define CF_CACR_DEC (0x80000000) /* Data Cache Enable */
|
||||
#define CF_CACR_DW (0x40000000) /* Data default Write-protect */
|
||||
#define CF_CACR_DESB (0x20000000) /* Data Enable Store Buffer */
|
||||
#define CF_CACR_DPI (0x10000000) /* Data Disable CPUSHL Invalidate */
|
||||
#define CF_CACR_DHLCK (0x08000000) /* 1/2 Data Cache Lock Mode */
|
||||
#define CF_CACR_DDCM_00 (0x00000000) /* Cacheable writethrough imprecise */
|
||||
#define CF_CACR_DDCM_01 (0x02000000) /* Cacheable copyback */
|
||||
#define CF_CACR_DDCM_10 (0x04000000) /* Noncacheable precise */
|
||||
#define CF_CACR_DDCM_11 (0x06000000) /* Noncacheable imprecise */
|
||||
#define CF_CACR_DCINVA (0x01000000) /* Data Cache Invalidate All */
|
||||
#define CF_CACR_DDSP (0x00800000) /* Data default supervisor-protect */
|
||||
#define CF_CACR_IVO (0x00100000) /* Invalidate only */
|
||||
#define CF_CACR_BEC (0x00080000) /* Branch Cache Enable */
|
||||
#define CF_CACR_BCINVA (0x00040000) /* Branch Cache Invalidate All */
|
||||
#define CF_CACR_IEC (0x00008000) /* Instruction Cache Enable */
|
||||
#define CF_CACR_SPA (0x00004000) /* Search by Physical Address */
|
||||
#define CF_CACR_DNFB (0x00002000) /* Default cache-inhibited fill buf */
|
||||
#define CF_CACR_IDPI (0x00001000) /* Instr Disable CPUSHL Invalidate */
|
||||
#define CF_CACR_IHLCK (0x00000800) /* 1/2 Instruction Cache Lock Mode */
|
||||
#define CF_CACR_IDCM (0x00000400) /* Noncacheable Instr default mode */
|
||||
#define CF_CACR_ICINVA (0x00000100) /* Instr Cache Invalidate All */
|
||||
#define CF_CACR_IDSP (0x00000080) /* Ins default supervisor-protect */
|
||||
#define CF_CACR_EUSP (0x00000020) /* Switch stacks in user mode */
|
||||
#define CF_CACR_DF (0x00000010) /* Disable FPU */
|
||||
|
||||
#define _DCACHE_SET_MASK ((DCACHE_SIZE / 64 - 1) << CACHE_WAYS)
|
||||
#define _ICACHE_SET_MASK ((ICACHE_SIZE / 64 - 1) << CACHE_WAYS)
|
||||
#define LAST_DCACHE_ADDR _DCACHE_SET_MASK
|
||||
#define LAST_ICACHE_ADDR _ICACHE_SET_MASK
|
||||
|
||||
#define ICACHE_SIZE 0x8000 /* instruction - 32k */
|
||||
#define DCACHE_SIZE 0x8000 /* data - 32k */
|
||||
|
||||
#define CACHE_LINE_SIZE 0x0010 /* 16 bytes */
|
||||
#define CACHE_SETS 0x0200 /* 512 sets */
|
||||
#define CACHE_WAYS 0x0004 /* 4 way */
|
||||
|
||||
|
||||
#define CACHE_DISABLE_MODE (CF_CACR_DCINVA + \
|
||||
CF_CACR_BCINVA + \
|
||||
CF_CACR_ICINVA)
|
||||
|
||||
#define CACHE_INITIAL_MODE (CF_CACR_DEC + \
|
||||
CF_CACR_BEC + \
|
||||
CF_CACR_IEC + \
|
||||
CF_CACR_DESB + \
|
||||
CF_CACR_EUSP)
|
||||
|
||||
extern void flush_and_invalidate_caches(void);
|
||||
extern uint32_t cacr_get(void);
|
||||
extern void cacr_set(uint32_t);
|
||||
extern void flush_icache_range(void *address, size_t size);
|
||||
extern void flush_dcache_range(void *address, size_t size);
|
||||
extern void flush_cache_range(void *address, size_t size);
|
||||
|
||||
|
||||
#endif /* _CACHE_H_ */
|
||||
@@ -1,63 +0,0 @@
|
||||
#ifndef __CONOUT_H__
|
||||
#define __CONOUT_H__
|
||||
|
||||
#include "bas_types.h"
|
||||
|
||||
/*
|
||||
* conout.h - lowlevel color model dependent screen handling routines
|
||||
*
|
||||
*
|
||||
* Copyright (C) 2004-2016 by Authors:
|
||||
*
|
||||
* Authors:
|
||||
* MAD Martin Doering
|
||||
*
|
||||
* This file is distributed under the GPL, version 2 or at your
|
||||
* option any later version. See doc/license.txt for details.
|
||||
*/
|
||||
|
||||
|
||||
|
||||
/* Defines for cursor */
|
||||
#define M_CFLASH 0x0001 /* cursor flash 0:disabled 1:enabled */
|
||||
#define M_CSTATE 0x0002 /* cursor flash state 0:off 1:on */
|
||||
#define M_CVIS 0x0004 /* cursor visibility 0:invisible 1:visible */
|
||||
|
||||
/*
|
||||
* The visibility flag is also used as a semaphore to prevent
|
||||
* the interrupt-driven cursor blink logic from colliding with
|
||||
* escape function/sequence cursor drawing activity.
|
||||
*/
|
||||
|
||||
#define M_CEOL 0x0008 /* end of line handling 0:overwrite 1:wrap */
|
||||
#define M_REVID 0x0010 /* reverse video 0:on 1:off */
|
||||
#define M_SVPOS 0x0020 /* position saved flag. 0:false, 1:true */
|
||||
#define M_CRIT 0x0040 /* reverse video 0:on 1:off */
|
||||
|
||||
/* Color related linea variables */
|
||||
|
||||
extern int16_t v_col_bg; /* current background color */
|
||||
extern int16_t v_col_fg; /* current foreground color */
|
||||
|
||||
/* Cursor related linea variables */
|
||||
|
||||
extern uint8_t *v_cur_ad; /* current cursor address */
|
||||
extern int16_t v_cur_of; /* cursor offset */
|
||||
extern int8_t v_cur_tim; /* cursor blink timer */
|
||||
|
||||
extern int8_t v_period;
|
||||
extern int16_t disab_cnt; /* disable depth count. (>0 means disabled) */
|
||||
extern int8_t v_stat_0; /* video cell system status */
|
||||
extern int16_t sav_cur_x; /* saved cursor cell x */
|
||||
extern int16_t sav_cur_y; /* saved cursor cell y */
|
||||
|
||||
/* Prototypes */
|
||||
|
||||
extern void ascii_out(int);
|
||||
extern void move_cursor(int, int);
|
||||
extern void blank_out (int, int, int, int);
|
||||
extern void invert_cell(int, int);
|
||||
extern void scroll_up(int);
|
||||
extern void scroll_down(int);
|
||||
|
||||
#endif /* __CONOUT_H__ */
|
||||
@@ -1,16 +0,0 @@
|
||||
#ifndef DEBUG_H
|
||||
// #define DEBUG_H
|
||||
|
||||
#ifdef DEBUG
|
||||
#include "bas_types.h"
|
||||
#include "bas_printf.h"
|
||||
|
||||
#define dbg(format, arg...) do { xprintf("DEBUG (%s()): " format, __FUNCTION__, ##arg);} while(0)
|
||||
#else
|
||||
#define dbg(format, arg...) do {;} while (0)
|
||||
#endif /* DEBUG */
|
||||
#define err(format, arg...) do { xprintf("ERROR (%s()): " format, __FUNCTION__, ##arg); } while(0)
|
||||
#define inf(format, arg...) do { xprintf("" format, ##arg); } while(0)
|
||||
|
||||
#endif // DEBUG_H
|
||||
|
||||
@@ -1,91 +0,0 @@
|
||||
/*-----------------------------------------------------------------------
|
||||
/ Low level disk interface modlue include file (C)ChaN, 2012
|
||||
/-----------------------------------------------------------------------*/
|
||||
|
||||
#ifndef _DISKIO_DEFINED
|
||||
#define _DISKIO_DEFINED
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#define _USE_WRITE 1 /* 1: Enable disk_write function */
|
||||
#define _USE_IOCTL 1 /* 1: Enable disk_ioctl fucntion */
|
||||
|
||||
#include <bas_types.h>
|
||||
|
||||
|
||||
/* Status of Disk Functions */
|
||||
typedef uint8_t DSTATUS;
|
||||
|
||||
/* Results of Disk Functions */
|
||||
typedef enum {
|
||||
RES_OK = 0, /* 0: Successful */
|
||||
RES_ERROR, /* 1: R/W Error */
|
||||
RES_WRPRT, /* 2: Write Protected */
|
||||
RES_NOTRDY, /* 3: Not Ready */
|
||||
RES_PARERR /* 4: Invalid Parameter */
|
||||
} DRESULT;
|
||||
|
||||
|
||||
/*---------------------------------------*/
|
||||
/* Prototypes for disk control functions */
|
||||
|
||||
|
||||
DSTATUS disk_initialize (uint8_t);
|
||||
DSTATUS disk_reset(uint8_t);
|
||||
DSTATUS disk_status (uint8_t);
|
||||
DRESULT disk_read (uint8_t, uint8_t*, uint32_t, uint8_t);
|
||||
#if _READONLY == 0
|
||||
DRESULT disk_write (uint8_t, const uint8_t*, uint32_t, uint8_t);
|
||||
#endif
|
||||
DRESULT disk_ioctl (uint8_t, uint8_t, void*);
|
||||
|
||||
|
||||
/* Disk Status Bits (DSTATUS) */
|
||||
#define STA_NOINIT 0x01 /* Drive not initialized */
|
||||
#define STA_NODISK 0x02 /* No medium in the drive */
|
||||
#define STA_PROTECT 0x04 /* Write protected */
|
||||
|
||||
|
||||
/* Command code for disk_ioctrl fucntion */
|
||||
|
||||
/* Generic command (used by FatFs) */
|
||||
#define CTRL_SYNC 0 /* Flush disk cache (for write functions) */
|
||||
#define GET_SECTOR_COUNT 1 /* Get media size (for only f_mkfs()) */
|
||||
#define GET_SECTOR_SIZE 2 /* Get sector size (for multiple sector size (_MAX_SS >= 1024)) */
|
||||
#define GET_BLOCK_SIZE 3 /* Get erase block size (for only f_mkfs()) */
|
||||
#define CTRL_ERASE_SECTOR 4 /* Force erased a block of sectors (for only _USE_ERASE) */
|
||||
|
||||
/* Generic command (not used by FatFs) */
|
||||
#define CTRL_POWER 5 /* Get/Set power status */
|
||||
#define CTRL_LOCK 6 /* Lock/Unlock media removal */
|
||||
#define CTRL_EJECT 7 /* Eject media */
|
||||
#define CTRL_FORMAT 8 /* Create physical format on the media */
|
||||
|
||||
/* MMC/SDC specific ioctl command */
|
||||
#define MMC_GET_TYPE 10 /* Get card type */
|
||||
#define MMC_GET_CSD 11 /* Get CSD */
|
||||
#define MMC_GET_CID 12 /* Get CID */
|
||||
#define MMC_GET_OCR 13 /* Get OCR */
|
||||
#define MMC_GET_SDSTAT 14 /* Get SD status */
|
||||
|
||||
/* ATA/CF specific ioctl command */
|
||||
#define ATA_GET_REV 20 /* Get F/W revision */
|
||||
#define ATA_GET_MODEL 21 /* Get model name */
|
||||
#define ATA_GET_SN 22 /* Get serial number */
|
||||
|
||||
|
||||
/* MMC card type flags (MMC_GET_TYPE) */
|
||||
#define CT_MMC 0x01 /* MMC ver 3 */
|
||||
#define CT_SD1 0x02 /* SD ver 1 */
|
||||
#define CT_SD2 0x04 /* SD ver 2 */
|
||||
#define CT_SDC (CT_SD1 | CT_SD2) /* SD */
|
||||
#define CT_BLOCK 0x08 /* Block addressing */
|
||||
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -1,43 +0,0 @@
|
||||
/*
|
||||
* spidma.h *
|
||||
* This file is part of BaS_gcc.
|
||||
*
|
||||
* BaS_gcc is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* BaS_gcc is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* Created on: 26.02.2013
|
||||
* Author: Markus Fröschle
|
||||
*/
|
||||
|
||||
#ifndef _DMA_H_
|
||||
#define _DMA_H_
|
||||
|
||||
#include "MCF5475.h"
|
||||
#include "MCD_dma.h"
|
||||
#include "bas_string.h"
|
||||
|
||||
void *dma_memcpy(void *dst, void *src, size_t n);
|
||||
extern int dma_init(void);
|
||||
extern int dma_get_channel(int requestor);
|
||||
extern int dma_set_channel(int, void (*)(void));
|
||||
extern void dma_free_channel(int requestor);
|
||||
extern void dma_clear_channel(int channel);
|
||||
extern uint32_t dma_get_initiator(int requestor);
|
||||
extern int dma_set_initiator(int initiator);
|
||||
extern void dma_free_initiator(int initiator);
|
||||
extern void dma_irq_enable(void);
|
||||
extern void dma_irq_disable(void);
|
||||
extern bool dma_interrupt_handler(void *arg1, void *arg2);
|
||||
|
||||
|
||||
#endif /* _DMA_H_ */
|
||||
@@ -1,15 +0,0 @@
|
||||
#ifndef _DRIVER_MEM_H_
|
||||
#define _DRIVER_MEM_H_
|
||||
|
||||
#include "bas_types.h"
|
||||
|
||||
/*
|
||||
* the driver_mem module provides a block of _uncached_ memory for USB and other drivers as
|
||||
* well as some memory handling functions for it
|
||||
*/
|
||||
extern int driver_mem_init(void);
|
||||
extern void *driver_mem_alloc(uint32_t amount);
|
||||
extern int32_t driver_mem_free(void *addr);
|
||||
extern void driver_mem_release(void);
|
||||
|
||||
#endif /* _DRIVER_MEM_H_ */
|
||||
@@ -1,216 +0,0 @@
|
||||
/*
|
||||
* driver_vec.h
|
||||
*
|
||||
* Interface for exposure of BaS drivers to the OS
|
||||
*
|
||||
* This file is part of BaS_gcc.
|
||||
*
|
||||
* BaS_gcc is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* BaS_gcc is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* Created on: 24.10.2013
|
||||
* Author: Markus Fröschle
|
||||
*/
|
||||
|
||||
#ifndef _DRIVER_VEC_H_
|
||||
#define _DRIVER_VEC_H_
|
||||
|
||||
#include "xhdi_sd.h"
|
||||
#include "MCD_dma.h"
|
||||
#include "pci.h"
|
||||
#include "fb.h"
|
||||
|
||||
enum driver_type
|
||||
{
|
||||
BLOCKDEV_DRIVER,
|
||||
CHARDEV_DRIVER,
|
||||
XHDI_DRIVER,
|
||||
MCD_DRIVER,
|
||||
VIDEO_DRIVER,
|
||||
PCI_DRIVER,
|
||||
MMU_DRIVER,
|
||||
PCI_NATIVE_DRIVER,
|
||||
END_OF_DRIVERS = 0xffffffffL, /* marks end of driver list */
|
||||
};
|
||||
|
||||
struct generic_driver_interface
|
||||
{
|
||||
uint32_t (*init)(void);
|
||||
uint32_t (*read)(void *buf, size_t count);
|
||||
uint32_t (*write)(const void *buf, size_t count);
|
||||
uint32_t (*ioctl)(uint32_t request, ...);
|
||||
};
|
||||
|
||||
struct dma_driver_interface
|
||||
{
|
||||
int32_t version;
|
||||
int32_t magic;
|
||||
int (*dma_set_initiator)(int initiator);
|
||||
uint32_t (*dma_get_initiator)(int requestor);
|
||||
void (*dma_free_initiator)(int requestor);
|
||||
int (*dma_set_channel)(int requestor, void (*handler)(void));
|
||||
int (*dma_get_channel)(int requestor);
|
||||
void (*dma_free_channel)(int requestor);
|
||||
void (*dma_clear_channel)(int channel);
|
||||
int (*MCD_startDma)(long channel,
|
||||
int8_t *srcAddr, unsigned int srcIncr, int8_t *destAddr, unsigned int destIncr,
|
||||
unsigned int dmaSize, unsigned int xferSize, unsigned int initiator, int priority,
|
||||
unsigned int flags, unsigned int funcDesc);
|
||||
int32_t (*MCD_dmaStatus)(int32_t channel);
|
||||
int32_t (*MCD_XferProgrQuery)(int32_t channel, MCD_XferProg *progRep);
|
||||
int32_t (*MCD_killDma)(int32_t channel);
|
||||
int32_t (*MCD_continDma)(int32_t channel);
|
||||
int32_t (*MCD_pauseDma)(int32_t channel);
|
||||
int32_t (*MCD_resumeDma)(int32_t channel);
|
||||
int32_t (*MCD_csumQuery)(int32_t channel, uint32_t *csum);
|
||||
void *(*dma_malloc)(uint32_t amount);
|
||||
int32_t (*dma_free)(void *addr);
|
||||
};
|
||||
|
||||
struct xhdi_driver_interface
|
||||
{
|
||||
uint32_t (*xhdivec)();
|
||||
};
|
||||
|
||||
|
||||
|
||||
struct framebuffer_driver_interface
|
||||
{
|
||||
struct fb_info **framebuffer_info; /* pointer to an fb_info struct (defined in include/fb.h) */
|
||||
};
|
||||
|
||||
struct pci_bios_interface
|
||||
{
|
||||
uint32_t subjar;
|
||||
uint32_t version;
|
||||
/* Although we declare this functions as standard gcc functions (cdecl),
|
||||
* they expect parameters inside registers (fastcall) unsupported by gcc m68k.
|
||||
* Caller will take care of parameters passing convention.
|
||||
*/
|
||||
int32_t (*find_pci_device)(uint32_t id, uint16_t index);
|
||||
int32_t (*find_pci_classcode)(uint32_t class, uint16_t index);
|
||||
int32_t (*read_config_byte)(int32_t handle, uint16_t reg, uint8_t *address);
|
||||
int32_t (*read_config_word)(int32_t handle, uint16_t reg, uint16_t *address);
|
||||
int32_t (*read_config_longword)(int32_t handle, uint16_t reg, uint32_t *address);
|
||||
uint8_t (*fast_read_config_byte)(int32_t handle, uint16_t reg);
|
||||
uint16_t (*fast_read_config_word)(int32_t handle, uint16_t reg);
|
||||
uint32_t (*fast_read_config_longword)(int32_t handle, uint16_t reg);
|
||||
int32_t (*write_config_byte)(int32_t handle, uint16_t reg, uint16_t val);
|
||||
int32_t (*write_config_word)(int32_t handle, uint16_t reg, uint16_t val);
|
||||
int32_t (*write_config_longword)(int32_t handle, uint16_t reg, uint32_t val);
|
||||
int32_t (*hook_interrupt)(int32_t handle, uint32_t *routine, uint32_t *parameter);
|
||||
int32_t (*unhook_interrupt)(int32_t handle);
|
||||
int32_t (*special_cycle)(uint16_t bus, uint32_t data);
|
||||
int32_t (*get_routing)(int32_t handle);
|
||||
int32_t (*set_interrupt)(int32_t handle);
|
||||
int32_t (*get_resource)(int32_t handle);
|
||||
int32_t (*get_card_used)(int32_t handle, uint32_t *address);
|
||||
int32_t (*set_card_used)(int32_t handle, uint32_t *callback);
|
||||
int32_t (*read_mem_byte)(int32_t handle, uint32_t offset, uint8_t *address);
|
||||
int32_t (*read_mem_word)(int32_t handle, uint32_t offset, uint16_t *address);
|
||||
int32_t (*read_mem_longword)(int32_t handle, uint32_t offset, uint32_t *address);
|
||||
uint8_t (*fast_read_mem_byte)(int32_t handle, uint32_t offset);
|
||||
uint16_t (*fast_read_mem_word)(int32_t handle, uint32_t offset);
|
||||
uint32_t (*fast_read_mem_longword)(int32_t handle, uint32_t offset);
|
||||
int32_t (*write_mem_byte)(int32_t handle, uint32_t offset, uint16_t val);
|
||||
int32_t (*write_mem_word)(int32_t handle, uint32_t offset, uint16_t val);
|
||||
int32_t (*write_mem_longword)(int32_t handle, uint32_t offset, uint32_t val);
|
||||
int32_t (*read_io_byte)(int32_t handle, uint32_t offset, uint8_t *address);
|
||||
int32_t (*read_io_word)(int32_t handle, uint32_t offset, uint16_t *address);
|
||||
int32_t (*read_io_longword)(int32_t handle, uint32_t offset, uint32_t *address);
|
||||
uint8_t (*fast_read_io_byte)(int32_t handle, uint32_t offset);
|
||||
uint16_t (*fast_read_io_word)(int32_t handle, uint32_t offset);
|
||||
uint32_t (*fast_read_io_longword)(int32_t handle, uint32_t offset);
|
||||
int32_t (*write_io_byte)(int32_t handle, uint32_t offset, uint16_t val);
|
||||
int32_t (*write_io_word)(int32_t handle, uint32_t offset, uint16_t val);
|
||||
int32_t (*write_io_longword)(int32_t handle, uint32_t offset, uint32_t val);
|
||||
int32_t (*get_machine_id)(void);
|
||||
int32_t (*get_pagesize)(void);
|
||||
int32_t (*virt_to_bus)(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer);
|
||||
int32_t (*bus_to_virt)(int32_t handle, uint32_t address, PCI_CONV_ADR *pointer);
|
||||
int32_t (*virt_to_phys)(uint32_t address, PCI_CONV_ADR *pointer);
|
||||
int32_t (*phys_to_virt)(uint32_t address, PCI_CONV_ADR *pointer);
|
||||
// int32_t reserved[2];
|
||||
};
|
||||
|
||||
struct mmu_driver_interface
|
||||
{
|
||||
uint32_t (*map_page_locked)(uint32_t address, uint32_t length, int asid);
|
||||
uint32_t (*unlock_page)(uint32_t address, uint32_t length, int asid);
|
||||
uint32_t (*report_locked_pages)(uint32_t *num_itlb, uint32_t *num_dtlb);
|
||||
uint32_t (*report_pagesize)(void);
|
||||
};
|
||||
|
||||
struct pci_native_driver_interface_0_1
|
||||
{
|
||||
uint32_t (*pci_read_config_longword)(int32_t handle, int offset);
|
||||
uint16_t (*pci_read_config_word)(int32_t handle, int offset);
|
||||
uint8_t (*pci_read_config_byte)(int32_t handle, int offset);
|
||||
|
||||
int32_t (*pci_write_config_longword)(int32_t handle, int offset, uint32_t value);
|
||||
int32_t (*pci_write_config_word)(int32_t handle, int offset, uint16_t value);
|
||||
int32_t (*pci_write_config_byte)(int32_t handle, int offset, uint8_t value);
|
||||
int32_t (*pci_hook_interrupt)(int32_t handle, void *handler, void *parameter);
|
||||
int32_t (*pci_unhook_interrupt)(int32_t handle);
|
||||
|
||||
struct pci_rd * (*pci_get_resource)(int32_t handle);
|
||||
};
|
||||
|
||||
struct pci_native_driver_interface
|
||||
{
|
||||
uint32_t (*pci_read_config_longword)(int32_t handle, int offset);
|
||||
uint16_t (*pci_read_config_word)(int32_t handle, int offset);
|
||||
uint8_t (*pci_read_config_byte)(int32_t handle, int offset);
|
||||
|
||||
int32_t (*pci_write_config_longword)(int32_t handle, int offset, uint32_t value);
|
||||
int32_t (*pci_write_config_word)(int32_t handle, int offset, uint16_t value);
|
||||
int32_t (*pci_write_config_byte)(int32_t handle, int offset, uint8_t value);
|
||||
int32_t (*pci_hook_interrupt)(int32_t handle, void *handler, void *parameter);
|
||||
int32_t (*pci_unhook_interrupt)(int32_t handle);
|
||||
int32_t (*pci_find_device)(uint16_t device_id, uint16_t vendor_id, int index);
|
||||
int32_t (*pci_find_classcode)(uint32_t classcode, int index);
|
||||
struct pci_rd * (*pci_get_resource)(int32_t handle);
|
||||
};
|
||||
|
||||
union interface
|
||||
{
|
||||
struct generic_driver_interface *gdi;
|
||||
struct xhdi_driver_interface *xhdi;
|
||||
struct dma_driver_interface *dma;
|
||||
struct framebuffer_driver_interface *fb;
|
||||
struct pci_bios_interface *pci;
|
||||
struct mmu_driver_interface *mmu;
|
||||
struct pci_native_driver_interface_0_1 *pci_native_0_1;
|
||||
struct pci_native_driver_interface *pci_native;
|
||||
};
|
||||
|
||||
struct generic_interface
|
||||
{
|
||||
enum driver_type type;
|
||||
char name[16];
|
||||
char description[64];
|
||||
int version;
|
||||
int revision;
|
||||
union interface interface;
|
||||
};
|
||||
|
||||
struct driver_table
|
||||
{
|
||||
uint32_t bas_version;
|
||||
uint32_t bas_revision;
|
||||
void (*remove_handler)(void); /* calling this will disable the BaS' hook into trap #0 */
|
||||
struct generic_interface *interfaces;
|
||||
};
|
||||
|
||||
|
||||
#endif /* _DRIVER_VEC_H_ */
|
||||
@@ -1,138 +0,0 @@
|
||||
/*
|
||||
* edid.h - EDID/DDC Header
|
||||
*
|
||||
* Based on:
|
||||
* 1. XFree86 4.3.0, edid.h
|
||||
* Copyright 1998 by Egbert Eich <Egbert.Eich@Physik.TU-Darmstadt.DE>
|
||||
*
|
||||
* 2. John Fremlin <vii@users.sourceforge.net> and
|
||||
* Ani Joshi <ajoshi@unixbox.com>
|
||||
*
|
||||
* DDC is a Trademark of VESA (Video Electronics Standard Association).
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU General Public
|
||||
* License. See the file COPYING in the main directory of this archive
|
||||
* for more details.
|
||||
*/
|
||||
|
||||
#ifndef __EDID_H__
|
||||
#define __EDID_H__
|
||||
|
||||
#define EDID_LENGTH 0x80
|
||||
#define EDID_HEADER 0x00
|
||||
#define EDID_HEADER_END 0x07
|
||||
|
||||
#define ID_MANUFACTURER_NAME 0x08
|
||||
#define ID_MANUFACTURER_NAME_END 0x09
|
||||
#define ID_MODEL 0x0a
|
||||
|
||||
#define ID_SERIAL_NUMBER 0x0c
|
||||
|
||||
#define MANUFACTURE_WEEK 0x10
|
||||
#define MANUFACTURE_YEAR 0x11
|
||||
|
||||
#define EDID_STRUCT_VERSION 0x12
|
||||
#define EDID_STRUCT_REVISION 0x13
|
||||
|
||||
#define EDID_STRUCT_DISPLAY 0x14
|
||||
|
||||
#define DPMS_FLAGS 0x18
|
||||
#define ESTABLISHED_TIMING_1 0x23
|
||||
#define ESTABLISHED_TIMING_2 0x24
|
||||
#define MANUFACTURERS_TIMINGS 0x25
|
||||
|
||||
/* standard timings supported */
|
||||
#define STD_TIMING 8
|
||||
#define STD_TIMING_DESCRIPTION_SIZE 2
|
||||
#define STD_TIMING_DESCRIPTIONS_START 0x26
|
||||
|
||||
#define DETAILED_TIMING_DESCRIPTIONS_START 0x36
|
||||
#define DETAILED_TIMING_DESCRIPTION_SIZE 18
|
||||
#define NO_DETAILED_TIMING_DESCRIPTIONS 4
|
||||
|
||||
#define DETAILED_TIMING_DESCRIPTION_1 0x36
|
||||
#define DETAILED_TIMING_DESCRIPTION_2 0x48
|
||||
#define DETAILED_TIMING_DESCRIPTION_3 0x5a
|
||||
#define DETAILED_TIMING_DESCRIPTION_4 0x6c
|
||||
|
||||
#define DESCRIPTOR_DATA 5
|
||||
|
||||
#define UPPER_NIBBLE( x ) \
|
||||
(((128|64|32|16) & (x)) >> 4)
|
||||
|
||||
#define LOWER_NIBBLE( x ) \
|
||||
((1|2|4|8) & (x))
|
||||
|
||||
#define COMBINE_HI_8LO( hi, lo ) \
|
||||
( (((unsigned)hi) << 8) | (unsigned)lo )
|
||||
|
||||
#define COMBINE_HI_4LO( hi, lo ) \
|
||||
( (((unsigned)hi) << 4) | (unsigned)lo )
|
||||
|
||||
#define PIXEL_CLOCK_LO (unsigned)block[ 0 ]
|
||||
#define PIXEL_CLOCK_HI (unsigned)block[ 1 ]
|
||||
#define PIXEL_CLOCK (COMBINE_HI_8LO( PIXEL_CLOCK_HI,PIXEL_CLOCK_LO )*10000)
|
||||
#define H_ACTIVE_LO (unsigned)block[ 2 ]
|
||||
#define H_BLANKING_LO (unsigned)block[ 3 ]
|
||||
#define H_ACTIVE_HI UPPER_NIBBLE( (unsigned)block[ 4 ] )
|
||||
#define H_ACTIVE COMBINE_HI_8LO( H_ACTIVE_HI, H_ACTIVE_LO )
|
||||
#define H_BLANKING_HI LOWER_NIBBLE( (unsigned)block[ 4 ] )
|
||||
#define H_BLANKING COMBINE_HI_8LO( H_BLANKING_HI, H_BLANKING_LO )
|
||||
|
||||
#define V_ACTIVE_LO (unsigned)block[ 5 ]
|
||||
#define V_BLANKING_LO (unsigned)block[ 6 ]
|
||||
#define V_ACTIVE_HI UPPER_NIBBLE( (unsigned)block[ 7 ] )
|
||||
#define V_ACTIVE COMBINE_HI_8LO( V_ACTIVE_HI, V_ACTIVE_LO )
|
||||
#define V_BLANKING_HI LOWER_NIBBLE( (unsigned)block[ 7 ] )
|
||||
#define V_BLANKING COMBINE_HI_8LO( V_BLANKING_HI, V_BLANKING_LO )
|
||||
|
||||
#define H_SYNC_OFFSET_LO (unsigned)block[ 8 ]
|
||||
#define H_SYNC_WIDTH_LO (unsigned)block[ 9 ]
|
||||
|
||||
#define V_SYNC_OFFSET_LO UPPER_NIBBLE( (unsigned)block[ 10 ] )
|
||||
#define V_SYNC_WIDTH_LO LOWER_NIBBLE( (unsigned)block[ 10 ] )
|
||||
|
||||
#define V_SYNC_WIDTH_HI ((unsigned)block[ 11 ] & (1|2))
|
||||
#define V_SYNC_OFFSET_HI (((unsigned)block[ 11 ] & (4|8)) >> 2)
|
||||
|
||||
#define H_SYNC_WIDTH_HI (((unsigned)block[ 11 ] & (16|32)) >> 4)
|
||||
#define H_SYNC_OFFSET_HI (((unsigned)block[ 11 ] & (64|128)) >> 6)
|
||||
|
||||
#define V_SYNC_WIDTH COMBINE_HI_4LO( V_SYNC_WIDTH_HI, V_SYNC_WIDTH_LO )
|
||||
#define V_SYNC_OFFSET COMBINE_HI_4LO( V_SYNC_OFFSET_HI, V_SYNC_OFFSET_LO )
|
||||
|
||||
#define H_SYNC_WIDTH COMBINE_HI_4LO( H_SYNC_WIDTH_HI, H_SYNC_WIDTH_LO )
|
||||
#define H_SYNC_OFFSET COMBINE_HI_4LO( H_SYNC_OFFSET_HI, H_SYNC_OFFSET_LO )
|
||||
|
||||
#define H_SIZE_LO (unsigned)block[ 12 ]
|
||||
#define V_SIZE_LO (unsigned)block[ 13 ]
|
||||
|
||||
#define H_SIZE_HI UPPER_NIBBLE( (unsigned)block[ 14 ] )
|
||||
#define V_SIZE_HI LOWER_NIBBLE( (unsigned)block[ 14 ] )
|
||||
|
||||
#define H_SIZE COMBINE_HI_8LO( H_SIZE_HI, H_SIZE_LO )
|
||||
#define V_SIZE COMBINE_HI_8LO( V_SIZE_HI, V_SIZE_LO )
|
||||
|
||||
#define H_BORDER (unsigned)block[ 15 ]
|
||||
#define V_BORDER (unsigned)block[ 16 ]
|
||||
|
||||
#define FLAGS (unsigned)block[ 17 ]
|
||||
|
||||
#define INTERLACED (FLAGS&128)
|
||||
#define SYNC_TYPE (FLAGS&3<<3) /* bits 4,3 */
|
||||
#define SYNC_SEPARATE (3<<3)
|
||||
#define HSYNC_POSITIVE (FLAGS & 4)
|
||||
#define VSYNC_POSITIVE (FLAGS & 2)
|
||||
|
||||
#define V_MIN_RATE block[ 5 ]
|
||||
#define V_MAX_RATE block[ 6 ]
|
||||
#define H_MIN_RATE block[ 7 ]
|
||||
#define H_MAX_RATE block[ 8 ]
|
||||
#define MAX_PIXEL_CLOCK (((int)block[ 9 ]) * 10)
|
||||
#define GTF_SUPPORT block[10]
|
||||
|
||||
#define DPMS_ACTIVE_OFF (1 << 5)
|
||||
#define DPMS_SUSPEND (1 << 6)
|
||||
#define DPMS_STANDBY (1 << 7)
|
||||
|
||||
#endif /* __EDID_H__ */
|
||||
@@ -1,211 +0,0 @@
|
||||
/*-
|
||||
* Copyright (c) 2007-2008, Juniper Networks, Inc.
|
||||
* Copyright (c) 2008, Michael Trimarchi <trimarchimichael@yahoo.it>
|
||||
* All rights reserved.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation version 2 of
|
||||
* the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*/
|
||||
|
||||
#ifndef USB_EHCI_H
|
||||
#define USB_EHCI_H
|
||||
|
||||
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 5
|
||||
|
||||
/* (shifted) direction/type/recipient from the USB 2.0 spec, table 9.2 */
|
||||
#define DeviceRequest \
|
||||
((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8)
|
||||
|
||||
#define DeviceOutRequest \
|
||||
((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_DEVICE) << 8)
|
||||
|
||||
#define InterfaceRequest \
|
||||
((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
|
||||
|
||||
#define EndpointRequest \
|
||||
((USB_DIR_IN | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
|
||||
|
||||
#define EndpointOutRequest \
|
||||
((USB_DIR_OUT | USB_TYPE_STANDARD | USB_RECIP_INTERFACE) << 8)
|
||||
|
||||
/*
|
||||
* Register Space.
|
||||
*/
|
||||
struct ehci_hccr
|
||||
{
|
||||
uint32_t cr_capbase;
|
||||
#define HC_LENGTH(p) (((p) >> 0) & 0x00ff)
|
||||
#define HC_VERSION(p) (((p) >> 16) & 0xffff)
|
||||
uint32_t cr_hcsparams;
|
||||
#define HCS_PPC(p) ((p) & (1 << 4))
|
||||
#define HCS_INDICATOR(p) ((p) & (1 << 16)) /* Port indicators */
|
||||
#define HCS_N_PORTS(p) (((p) >> 0) & 0xf)
|
||||
uint32_t cr_hccparams;
|
||||
uint8_t cr_hcsp_portrt[8];
|
||||
} __attribute__ ((packed));
|
||||
|
||||
struct ehci_hcor
|
||||
{
|
||||
uint32_t or_usbcmd;
|
||||
#define CMD_PARK (1 << 11) /* enable "park" */
|
||||
#define CMD_PARK_CNT(c) (((c) >> 8) & 3) /* how many transfers to park */
|
||||
#define CMD_ASE (1 << 5) /* async schedule enable */
|
||||
#define CMD_LRESET (1 << 7) /* partial reset */
|
||||
#define CMD_IAAD (1 << 5) /* "doorbell" interrupt */
|
||||
#define CMD_PSE (1 << 4) /* periodic schedule enable */
|
||||
#define CMD_RESET (1 << 1) /* reset HC not bus */
|
||||
#define CMD_RUN (1 << 0) /* start/stop HC */
|
||||
uint32_t or_usbsts;
|
||||
#define STD_ASS (1 << 15)
|
||||
#define STS_PSSTAT (1 << 14)
|
||||
#define STS_RECL (1 << 13)
|
||||
#define STS_HALT (1 << 12)
|
||||
#define STS_IAA (1 << 5)
|
||||
#define STS_HSE (1 << 4)
|
||||
#define STS_FLR (1 << 3)
|
||||
#define STS_PCD (1 << 2)
|
||||
#define STS_USBERRINT (1 << 1)
|
||||
#define STS_USBINT (1 << 0)
|
||||
uint32_t or_usbintr;
|
||||
#define INTR_IAAE (1 << 5)
|
||||
#define INTR_HSEE (1 << 4)
|
||||
#define INTR_FLRE (1 << 3)
|
||||
#define INTR_PCDE (1 << 2)
|
||||
#define INTR_USBERRINTE (1 << 1)
|
||||
#define INTR_USBINTE (1 << 0)
|
||||
uint32_t or_frindex;
|
||||
uint32_t or_ctrldssegment;
|
||||
uint32_t or_periodiclistbase;
|
||||
uint32_t or_asynclistaddr;
|
||||
uint32_t _reserved_[9];
|
||||
uint32_t or_configflag;
|
||||
#define FLAG_CF (1 << 0) /* true: we'll support "high speed" */
|
||||
uint32_t or_portsc[CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS];
|
||||
uint32_t or_systune;
|
||||
} __attribute__ ((packed));
|
||||
|
||||
#define USBMODE 0x68 /* USB Device mode */
|
||||
#define USBMODE_SDIS (1 << 3) /* Stream disable */
|
||||
#define USBMODE_BE (1 << 2) /* BE/LE endiannes select */
|
||||
#define USBMODE_CM_HC (3 << 0) /* host controller mode */
|
||||
#define USBMODE_CM_IDLE (0 << 0) /* idle state */
|
||||
|
||||
/* Interface descriptor */
|
||||
struct usb_linux_interface_descriptor
|
||||
{
|
||||
unsigned char bLength;
|
||||
unsigned char bDescriptorType;
|
||||
unsigned char bInterfaceNumber;
|
||||
unsigned char bAlternateSetting;
|
||||
unsigned char bNumEndpoints;
|
||||
unsigned char bInterfaceClass;
|
||||
unsigned char bInterfaceSubClass;
|
||||
unsigned char bInterfaceProtocol;
|
||||
unsigned char iInterface;
|
||||
} __attribute__ ((packed));
|
||||
|
||||
/* Configuration descriptor information.. */
|
||||
struct usb_linux_config_descriptor
|
||||
{
|
||||
unsigned char bLength;
|
||||
unsigned char bDescriptorType;
|
||||
unsigned short wTotalLength;
|
||||
unsigned char bNumInterfaces;
|
||||
unsigned char bConfigurationValue;
|
||||
unsigned char iConfiguration;
|
||||
unsigned char bmAttributes;
|
||||
unsigned char MaxPower;
|
||||
} __attribute__ ((packed));
|
||||
|
||||
#if defined CONFIG_EHCI_DESC_BIG_ENDIAN
|
||||
#define ehci_readl(x) (*((volatile uint32_t *)(x)))
|
||||
#define ehci_writel(a, b) (*((volatile uint32_t *)(a)) = ((volatile uint32_t) b))
|
||||
#else
|
||||
#define ehci_readl(x) swpl((*((volatile uint32_t *)(x))))
|
||||
#define ehci_writel(a, b) (*((volatile uint32_t *)(a)) = swpl(((volatile uint32_t) b)))
|
||||
#endif
|
||||
|
||||
#if defined CONFIG_EHCI_MMIO_BIG_ENDIAN
|
||||
#define hc32_to_cpu(x) be32_to_cpu((x))
|
||||
#define cpu_to_hc32(x) cpu_to_be32((x))
|
||||
#else
|
||||
#define hc32_to_cpu(x) swpl((x))
|
||||
#define cpu_to_hc32(x) swpl((x))
|
||||
#endif
|
||||
|
||||
#define EHCI_PS_WKOC_E (1 << 22) /* RW wake on over current */
|
||||
#define EHCI_PS_WKDSCNNT_E (1 << 21) /* RW wake on disconnect */
|
||||
#define EHCI_PS_WKCNNT_E (1 << 20) /* RW wake on connect */
|
||||
#define EHCI_PS_PO (1 << 13) /* RW port owner */
|
||||
#define EHCI_PS_PP (1 << 12) /* RW,RO port power */
|
||||
#define EHCI_PS_LS (3 << 10) /* RO line status */
|
||||
#define EHCI_PS_PR (1 << 8) /* RW port reset */
|
||||
#define EHCI_PS_SUSP (1 << 7) /* RW suspend */
|
||||
#define EHCI_PS_FPR (1 << 6) /* RW force port resume */
|
||||
#define EHCI_PS_OCC (1 << 5) /* RWC over current change */
|
||||
#define EHCI_PS_OCA (1 << 4) /* RO over current active */
|
||||
#define EHCI_PS_PEC (1 << 3) /* RWC port enable change */
|
||||
#define EHCI_PS_PE (1 << 2) /* RW port enable */
|
||||
#define EHCI_PS_CSC (1 << 1) /* RWC connect status change */
|
||||
#define EHCI_PS_CS (1 << 0) /* RO connect status */
|
||||
#define EHCI_PS_CLEAR (EHCI_PS_OCC | EHCI_PS_PEC | EHCI_PS_CSC)
|
||||
|
||||
#define EHCI_PS_IS_LOWSPEED(x) (((x) & EHCI_PS_LS) == (1 << 10))
|
||||
|
||||
/*
|
||||
* Schedule Interface Space.
|
||||
*
|
||||
* IMPORTANT: Software must ensure that no interface data structure
|
||||
* reachable by the EHCI host controller spans a 4K page boundary!
|
||||
*
|
||||
* Periodic transfers (i.e. isochronous and interrupt transfers) are
|
||||
* not supported.
|
||||
*/
|
||||
|
||||
/* Queue Element Transfer Descriptor (qTD). */
|
||||
struct qTD
|
||||
{
|
||||
uint32_t qt_next;
|
||||
#define QT_NEXT_TERMINATE 1
|
||||
uint32_t qt_altnext;
|
||||
uint32_t qt_token;
|
||||
uint32_t qt_buffer[5];
|
||||
};
|
||||
|
||||
/* Queue Head (QH). */
|
||||
struct QH
|
||||
{
|
||||
uint32_t qh_link;
|
||||
#define QH_LINK_TERMINATE 1
|
||||
#define QH_LINK_TYPE_ITD 0
|
||||
#define QH_LINK_TYPE_QH 2
|
||||
#define QH_LINK_TYPE_SITD 4
|
||||
#define QH_LINK_TYPE_FSTN 6
|
||||
uint32_t qh_endpt1;
|
||||
uint32_t qh_endpt2;
|
||||
uint32_t qh_curtd;
|
||||
struct qTD qh_overlay;
|
||||
/*
|
||||
* Add dummy fill value to make the size of this struct
|
||||
* aligned to 32 bytes
|
||||
*/
|
||||
uint8_t fill[16];
|
||||
};
|
||||
|
||||
/* Low level init functions */
|
||||
int ehci_hcd_init(void);
|
||||
int ehci_hcd_stop(void);
|
||||
|
||||
#endif /* USB_EHCI_H */
|
||||
@@ -1,57 +0,0 @@
|
||||
/*
|
||||
* File: eth.h
|
||||
* Purpose: Definitions for Ethernet Frames.
|
||||
*
|
||||
* Modifications:
|
||||
*/
|
||||
|
||||
#ifndef _ETH_H
|
||||
#define _ETH_H
|
||||
|
||||
#include "bas_types.h"
|
||||
|
||||
/*******************************************************************/
|
||||
|
||||
/* Ethernet standard lengths in bytes*/
|
||||
#define ETH_ADDR_LEN (6)
|
||||
#define ETH_TYPE_LEN (2)
|
||||
#define ETH_CRC_LEN (4)
|
||||
#define ETH_MAX_DATA (1500)
|
||||
#define ETH_MIN_DATA (46)
|
||||
#define ETH_HDR_LEN (ETH_ADDR_LEN * 2 + ETH_TYPE_LEN)
|
||||
|
||||
/* Defined Ethernet Frame Types */
|
||||
#define ETH_FRM_IP (0x0800)
|
||||
#define ETH_FRM_ARP (0x0806)
|
||||
#define ETH_FRM_RARP (0x8035)
|
||||
#define ETH_FRM_TEST (0xA5A5)
|
||||
|
||||
/* Maximum and Minimum Ethernet Frame Sizes */
|
||||
#define ETH_MAX_FRM (ETH_HDR_LEN + ETH_MAX_DATA + ETH_CRC_LEN)
|
||||
#define ETH_MIN_FRM (ETH_HDR_LEN + ETH_MIN_DATA + ETH_CRC_LEN)
|
||||
#define ETH_MTU (ETH_HDR_LEN + ETH_MAX_DATA)
|
||||
|
||||
/* Ethernet Addresses */
|
||||
typedef uint8_t ETH_ADDR[ETH_ADDR_LEN];
|
||||
|
||||
/* 16-bit Ethernet Frame Type, ie. Protocol */
|
||||
typedef uint16_t ETH_FRM_TYPE;
|
||||
|
||||
/* Ethernet Frame Header definition */
|
||||
typedef struct
|
||||
{
|
||||
ETH_ADDR dest;
|
||||
ETH_ADDR src;
|
||||
ETH_FRM_TYPE type;
|
||||
} ETH_HDR;
|
||||
|
||||
/* Ethernet Frame definition */
|
||||
typedef struct
|
||||
{
|
||||
ETH_HDR head;
|
||||
uint8_t* data;
|
||||
} ETH_FRAME;
|
||||
|
||||
/*******************************************************************/
|
||||
|
||||
#endif /* _ETH_H */
|
||||
@@ -1,8 +0,0 @@
|
||||
#ifndef _EXCEPTIONS_H_
|
||||
#define _EXCEPTIONS_H_
|
||||
|
||||
#include <bas_types.h>
|
||||
|
||||
extern uint32_t set_ipl(uint32_t ipl);
|
||||
|
||||
#endif /* _EXCEPTIONS_H_ */
|
||||
@@ -1,569 +0,0 @@
|
||||
#ifndef _FB_H
|
||||
#define _FB_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/* Definitions of frame buffers */
|
||||
|
||||
#define FB_MAJOR 29
|
||||
#define FB_MAX 32 /* sufficient for now */
|
||||
|
||||
/* ioctls 0x46 is 'F' */
|
||||
#define FBIOGET_VSCREENINFO 0x4600
|
||||
#define FBIOPUT_VSCREENINFO 0x4601
|
||||
#define FBIOGET_FSCREENINFO 0x4602
|
||||
#define FBIOPAN_DISPLAY 0x4606
|
||||
#define FBIOBLANK 0x4611 /* arg: 0 or vesa level + 1 */
|
||||
#define FBIO_ALLOC 0x4613
|
||||
#define FBIO_FREE 0x4614
|
||||
|
||||
/* picture format */
|
||||
#define PICT_FORMAT(bpp, type, a, r, g, b) (((bpp) << 24) | ((type) << 16) | ((a) << 12) | ((r) << 8) | ((g) << 4) | ((b)))
|
||||
|
||||
/* gray/color formats use a visual index instead of argb */
|
||||
#define PICT_VISFORMAT(bpp, type, vi) (((bpp) << 24) | ((type) << 16) | ((vi)))
|
||||
#define PICT_FORMAT_BPP(f) (((f) >> 24) )
|
||||
#define PICT_FORMAT_TYPE(f) (((f) >> 16) & 0xff)
|
||||
#define PICT_FORMAT_A(f) (((f) >> 12) & 0x0f)
|
||||
#define PICT_FORMAT_R(f) (((f) >> 8) & 0x0f)
|
||||
#define PICT_FORMAT_G(f) (((f) >> 4) & 0x0f)
|
||||
#define PICT_FORMAT_B(f) (((f) ) & 0x0f)
|
||||
#define PICT_FORMAT_RGB(f) (((f) ) & 0xfff)
|
||||
#define PICT_FORMAT_VIS(f) (((f) ) & 0xffff)
|
||||
|
||||
#define PICT_TYPE_OTHER 0
|
||||
#define PICT_TYPE_A 1
|
||||
#define PICT_TYPE_ARGB 2
|
||||
#define PICT_TYPE_ABGR 3
|
||||
#define PICT_TYPE_COLOR 4
|
||||
#define PICT_TYPE_GRAY 5
|
||||
#define PICT_FORMAT_COLOR(f) (PICT_FORMAT_TYPE(f) & 2)
|
||||
|
||||
/* 32bpp formats */
|
||||
#define PICT_a8r8g8b8 PICT_FORMAT(32, PICT_TYPE_ARGB, 8, 8, 8, 8)
|
||||
#define PICT_x8r8g8b8 PICT_FORMAT(32, PICT_TYPE_ARGB, 0, 8, 8, 8)
|
||||
#define PICT_a8b8g8r8 PICT_FORMAT(32, PICT_TYPE_ABGR, 8, 8, 8, 8)
|
||||
#define PICT_x8b8g8r8 PICT_FORMAT(32, PICT_TYPE_ABGR, 0, 8, 8, 8)
|
||||
|
||||
/* 24bpp formats */
|
||||
#define PICT_r8g8b8 PICT_FORMAT(24, PICT_TYPE_ARGB, 0, 8, 8, 8)
|
||||
#define PICT_b8g8r8 PICT_FORMAT(24, PICT_TYPE_ABGR, 0, 8, 8, 8)
|
||||
|
||||
/* 16bpp formats */
|
||||
#define PICT_r5g6b5 PICT_FORMAT(16, PICT_TYPE_ARGB, 0, 5, 6, 5)
|
||||
#define PICT_b5g6r5 PICT_FORMAT(16, PICT_TYPE_ABGR, 0, 5, 6, 5)
|
||||
#define PICT_a1r5g5b5 PICT_FORMAT(16, PICT_TYPE_ARGB, 1, 5, 5, 5)
|
||||
#define PICT_x1r5g5b5 PICT_FORMAT(16, PICT_TYPE_ARGB, 0, 5, 5, 5)
|
||||
#define PICT_a1b5g5r5 PICT_FORMAT(16, PICT_TYPE_ABGR, 1, 5, 5, 5)
|
||||
#define PICT_x1b5g5r5 PICT_FORMAT(16, PICT_TYPE_ABGR, 0, 5, 5, 5)
|
||||
#define PICT_a4r4g4b4 PICT_FORMAT(16, PICT_TYPE_ARGB, 4, 4, 4, 4)
|
||||
#define PICT_x4r4g4b4 PICT_FORMAT(16, PICT_TYPE_ARGB, 4, 4, 4, 4)
|
||||
#define PICT_a4b4g4r4 PICT_FORMAT(16, PICT_TYPE_ARGB, 4, 4, 4, 4)
|
||||
#define PICT_x4b4g4r4 PICT_FORMAT(16, PICT_TYPE_ARGB, 4, 4, 4, 4)
|
||||
|
||||
/* 8bpp formats */
|
||||
#define PICT_a8 PICT_FORMAT(8, PICT_TYPE_A, 8, 0, 0, 0)
|
||||
#define PICT_r3g3b2 PICT_FORMAT(8, PICT_TYPE_ARGB, 0, 3, 3, 2)
|
||||
#define PICT_b2g3r3 PICT_FORMAT(8, PICT_TYPE_ABGR, 0, 3, 3, 2)
|
||||
#define PICT_a2r2g2b2 PICT_FORMAT(8, PICT_TYPE_ARGB, 2, 2, 2, 2)
|
||||
#define PICT_a2b2g2r2 PICT_FORMAT(8, PICT_TYPE_ABGR, 2, 2, 2, 2)
|
||||
#define PICT_c8 PICT_FORMAT(8, PICT_TYPE_COLOR, 0, 0, 0, 0)
|
||||
#define PICT_g8 PICT_FORMAT(8, PICT_TYPE_GRAY, 0, 0, 0, 0)
|
||||
|
||||
/* fVDI */
|
||||
#define MODE_EMUL_MONO_FLAG 1
|
||||
#define MODE_VESA_FLAG 2 /* for modedb.c */
|
||||
|
||||
struct mode_option
|
||||
{
|
||||
short used; /* Whether the mode option was used or not. */
|
||||
short width;
|
||||
short height;
|
||||
short bpp;
|
||||
short freq;
|
||||
short flags;
|
||||
};
|
||||
|
||||
extern struct mode_option resolution; /* fVDI */
|
||||
|
||||
#define FB_TYPE_PACKED_PIXELS 0 /* Packed Pixels */
|
||||
#define FB_TYPE_PLANES 1 /* Non interleaved planes */
|
||||
#define FB_TYPE_INTERLEAVED_PLANES 2 /* Interleaved planes */
|
||||
#define FB_TYPE_TEXT 3 /* Text/attributes */
|
||||
#define FB_TYPE_VGA_PLANES 4 /* EGA/VGA planes */
|
||||
|
||||
#define FB_AUX_TEXT_MDA 0 /* Monochrome text */
|
||||
#define FB_AUX_TEXT_CGA 1 /* CGA/EGA/VGA Color text */
|
||||
#define FB_AUX_TEXT_S3_MMIO 2 /* S3 MMIO fasttext */
|
||||
#define FB_AUX_TEXT_MGA_STEP16 3 /* MGA Millenium I: text, attr, 14 reserved bytes */
|
||||
#define FB_AUX_TEXT_MGA_STEP8 4 /* other MGAs: text, attr, 6 reserved bytes */
|
||||
|
||||
#define FB_AUX_VGA_PLANES_VGA4 0 /* 16 color planes (EGA/VGA) */
|
||||
#define FB_AUX_VGA_PLANES_CFB4 1 /* CFB4 in planes (VGA) */
|
||||
#define FB_AUX_VGA_PLANES_CFB8 2 /* CFB8 in planes (VGA) */
|
||||
|
||||
#define FB_VISUAL_MONO01 0 /* Monochr. 1=Black 0=White */
|
||||
#define FB_VISUAL_MONO10 1 /* Monochr. 1=White 0=Black */
|
||||
#define FB_VISUAL_TRUECOLOR 2 /* True color */
|
||||
#define FB_VISUAL_PSEUDOCOLOR 3 /* Pseudo color (like atari) */
|
||||
#define FB_VISUAL_DIRECTCOLOR 4 /* Direct color */
|
||||
#define FB_VISUAL_STATIC_PSEUDOCOLOR 5 /* Pseudo color readonly */
|
||||
|
||||
#define FB_ACCEL_NONE 0 /* no hardware accelerator */
|
||||
#define FB_ACCEL_ATARIBLITT 1 /* Atari Blitter */
|
||||
#define FB_ACCEL_AMIGABLITT 2 /* Amiga Blitter */
|
||||
#define FB_ACCEL_S3_TRIO64 3 /* Cybervision64 (S3 Trio64) */
|
||||
#define FB_ACCEL_NCR_77C32BLT 4 /* RetinaZ3 (NCR 77C32BLT) */
|
||||
#define FB_ACCEL_S3_VIRGE 5 /* Cybervision64/3D (S3 ViRGE) */
|
||||
#define FB_ACCEL_ATI_MACH64GX 6 /* ATI Mach 64GX family */
|
||||
#define FB_ACCEL_DEC_TGA 7 /* DEC 21030 TGA */
|
||||
#define FB_ACCEL_ATI_MACH64CT 8 /* ATI Mach 64CT family */
|
||||
#define FB_ACCEL_ATI_MACH64VT 9 /* ATI Mach 64CT family VT class */
|
||||
#define FB_ACCEL_ATI_MACH64GT 10 /* ATI Mach 64CT family GT class */
|
||||
#define FB_ACCEL_SUN_CREATOR 11 /* Sun Creator/Creator3D */
|
||||
#define FB_ACCEL_SUN_CGSIX 12 /* Sun cg6 */
|
||||
#define FB_ACCEL_SUN_LEO 13 /* Sun leo/zx */
|
||||
#define FB_ACCEL_IMS_TWINTURBO 14 /* IMS Twin Turbo */
|
||||
#define FB_ACCEL_3DLABS_PERMEDIA2 15 /* 3Dlabs Permedia 2 */
|
||||
#define FB_ACCEL_MATROX_MGA2064W 16 /* Matrox MGA2064W (Millenium) */
|
||||
#define FB_ACCEL_MATROX_MGA1064SG 17 /* Matrox MGA1064SG (Mystique) */
|
||||
#define FB_ACCEL_MATROX_MGA2164W 18 /* Matrox MGA2164W (Millenium II) */
|
||||
#define FB_ACCEL_MATROX_MGA2164W_AGP 19 /* Matrox MGA2164W (Millenium II) */
|
||||
#define FB_ACCEL_MATROX_MGAG100 20 /* Matrox G100 (Productiva G100) */
|
||||
#define FB_ACCEL_MATROX_MGAG200 21 /* Matrox G200 (Myst, Mill, ...) */
|
||||
#define FB_ACCEL_SUN_CG14 22 /* Sun cgfourteen */
|
||||
#define FB_ACCEL_SUN_BWTWO 23 /* Sun bwtwo */
|
||||
#define FB_ACCEL_SUN_CGTHREE 24 /* Sun cgthree */
|
||||
#define FB_ACCEL_SUN_TCX 25 /* Sun tcx */
|
||||
#define FB_ACCEL_MATROX_MGAG400 26 /* Matrox G400 */
|
||||
#define FB_ACCEL_NV3 27 /* nVidia RIVA 128 */
|
||||
#define FB_ACCEL_NV4 28 /* nVidia RIVA TNT */
|
||||
#define FB_ACCEL_NV5 29 /* nVidia RIVA TNT2 */
|
||||
#define FB_ACCEL_CT_6555x 30 /* C&T 6555x */
|
||||
#define FB_ACCEL_3DFX_BANSHEE 31 /* 3Dfx Banshee */
|
||||
#define FB_ACCEL_ATI_RAGE128 32 /* ATI Rage128 family */
|
||||
#define FB_ACCEL_IGS_CYBER2000 33 /* CyberPro 2000 */
|
||||
#define FB_ACCEL_IGS_CYBER2010 34 /* CyberPro 2010 */
|
||||
#define FB_ACCEL_IGS_CYBER5000 35 /* CyberPro 5000 */
|
||||
#define FB_ACCEL_SIS_GLAMOUR 36 /* SiS 300/630/540 */
|
||||
#define FB_ACCEL_3DLABS_PERMEDIA3 37 /* 3Dlabs Permedia 3 */
|
||||
#define FB_ACCEL_ATI_RADEON 38 /* ATI Radeon family */
|
||||
#define FB_ACCEL_I810 39 /* Intel 810/815 */
|
||||
#define FB_ACCEL_SIS_GLAMOUR_2 40 /* SiS 315, 650, 740 */
|
||||
#define FB_ACCEL_SIS_XABRE 41 /* SiS 330 ("Xabre") */
|
||||
#define FB_ACCEL_I830 42 /* Intel 830M/845G/85x/865G */
|
||||
#define FB_ACCEL_NV_10 43 /* nVidia Arch 10 */
|
||||
#define FB_ACCEL_NV_20 44 /* nVidia Arch 20 */
|
||||
#define FB_ACCEL_NV_30 45 /* nVidia Arch 30 */
|
||||
#define FB_ACCEL_NV_40 46 /* nVidia Arch 40 */
|
||||
#define FB_ACCEL_NEOMAGIC_NM2070 90 /* NeoMagic NM2070 */
|
||||
#define FB_ACCEL_NEOMAGIC_NM2090 91 /* NeoMagic NM2090 */
|
||||
#define FB_ACCEL_NEOMAGIC_NM2093 92 /* NeoMagic NM2093 */
|
||||
#define FB_ACCEL_NEOMAGIC_NM2097 93 /* NeoMagic NM2097 */
|
||||
#define FB_ACCEL_NEOMAGIC_NM2160 94 /* NeoMagic NM2160 */
|
||||
#define FB_ACCEL_NEOMAGIC_NM2200 95 /* NeoMagic NM2200 */
|
||||
#define FB_ACCEL_NEOMAGIC_NM2230 96 /* NeoMagic NM2230 */
|
||||
#define FB_ACCEL_NEOMAGIC_NM2360 97 /* NeoMagic NM2360 */
|
||||
#define FB_ACCEL_NEOMAGIC_NM2380 98 /* NeoMagic NM2380 */
|
||||
|
||||
#define FB_ACCEL_SAVAGE4 0x80 /* S3 Savage4 */
|
||||
#define FB_ACCEL_SAVAGE3D 0x81 /* S3 Savage3D */
|
||||
#define FB_ACCEL_SAVAGE3D_MV 0x82 /* S3 Savage3D-MV */
|
||||
#define FB_ACCEL_SAVAGE2000 0x83 /* S3 Savage2000 */
|
||||
#define FB_ACCEL_SAVAGE_MX_MV 0x84 /* S3 Savage/MX-MV */
|
||||
#define FB_ACCEL_SAVAGE_MX 0x85 /* S3 Savage/MX */
|
||||
#define FB_ACCEL_SAVAGE_IX_MV 0x86 /* S3 Savage/IX-MV */
|
||||
#define FB_ACCEL_SAVAGE_IX 0x87 /* S3 Savage/IX */
|
||||
#define FB_ACCEL_PROSAVAGE_PM 0x88 /* S3 ProSavage PM133 */
|
||||
#define FB_ACCEL_PROSAVAGE_KM 0x89 /* S3 ProSavage KM133 */
|
||||
#define FB_ACCEL_S3TWISTER_P 0x8a /* S3 Twister */
|
||||
#define FB_ACCEL_S3TWISTER_K 0x8b /* S3 TwisterK */
|
||||
#define FB_ACCEL_SUPERSAVAGE 0x8c /* S3 Supersavage */
|
||||
#define FB_ACCEL_PROSAVAGE_DDR 0x8d /* S3 ProSavage DDR */
|
||||
#define FB_ACCEL_PROSAVAGE_DDRK 0x8e /* S3 ProSavage DDR-K */
|
||||
|
||||
struct fb_fix_screeninfo
|
||||
{
|
||||
char id[16]; /* identification string eg "TT Builtin" */
|
||||
uint32_t smem_start; /* Start of frame buffer mem */
|
||||
/* (physical address) */
|
||||
uint32_t smem_len; /* Length of frame buffer mem */
|
||||
uint32_t type; /* see FB_TYPE_* */
|
||||
uint32_t type_aux; /* Interleave for interleaved Planes */
|
||||
uint32_t visual; /* see FB_VISUAL_* */
|
||||
uint16_t xpanstep; /* zero if no hardware panning */
|
||||
uint16_t ypanstep; /* zero if no hardware panning */
|
||||
uint16_t ywrapstep; /* zero if no hardware ywrap */
|
||||
uint32_t line_length; /* length of a line in bytes */
|
||||
uint32_t mmio_start; /* Start of Memory Mapped I/O */
|
||||
/* (physical address) */
|
||||
uint32_t mmio_len; /* Length of Memory Mapped I/O */
|
||||
uint32_t accel; /* Indicate to driver which */
|
||||
/* specific chip/card we have */
|
||||
uint16_t reserved[3]; /* Reserved for future compatibility */
|
||||
};
|
||||
|
||||
/* Interpretation of offset for color fields: All offsets are from the right,
|
||||
* inside a "pixel" value, which is exactly 'bits_per_pixel' wide (means: you
|
||||
* can use the offset as right argument to <<). A pixel afterwards is a bit
|
||||
* stream and is written to video memory as that unmodified. This implies
|
||||
* big-endian byte order if bits_per_pixel is greater than 8.
|
||||
*/
|
||||
struct fb_bitfield
|
||||
{
|
||||
uint32_t offset; /* beginning of bitfield */
|
||||
uint32_t length; /* length of bitfield */
|
||||
uint32_t msb_right; /* != 0 : Most significant bit is */
|
||||
/* right */
|
||||
};
|
||||
|
||||
#define FB_NONSTD_HAM 1 /* Hold-And-Modify (HAM) */
|
||||
|
||||
#define FB_ACTIVATE_NOW 0 /* set values immediately (or vbl)*/
|
||||
#define FB_ACTIVATE_NXTOPEN 1 /* activate on next open */
|
||||
#define FB_ACTIVATE_TEST 2 /* don't set, round up impossible */
|
||||
#define FB_ACTIVATE_MASK 15
|
||||
/* values */
|
||||
#define FB_ACTIVATE_VBL 16 /* activate values on next vbl */
|
||||
#define FB_CHANGE_CMAP_VBL 32 /* change colormap on vbl */
|
||||
#define FB_ACTIVATE_ALL 64 /* change all VCs on this fb */
|
||||
#define FB_ACTIVATE_FORCE 128 /* force apply even when no change*/
|
||||
#define FB_ACTIVATE_INV_MODE 256 /* invalidate videomode */
|
||||
|
||||
#define FB_ACCELF_TEXT 1 /* (OBSOLETE) see fb_info.flags and vc_mode */
|
||||
|
||||
#define FB_SYNC_HOR_HIGH_ACT 1 /* horizontal sync high active */
|
||||
#define FB_SYNC_VERT_HIGH_ACT 2 /* vertical sync high active */
|
||||
#define FB_SYNC_EXT 4 /* external sync */
|
||||
#define FB_SYNC_COMP_HIGH_ACT 8 /* composite sync high active */
|
||||
#define FB_SYNC_BROADCAST 16 /* broadcast video timings */
|
||||
/* vtotal = 144d/288n/576i => PAL */
|
||||
/* vtotal = 121d/242n/484i => NTSC */
|
||||
#define FB_SYNC_ON_GREEN 32 /* sync on green */
|
||||
|
||||
#define FB_VMODE_NONINTERLACED 0 /* non interlaced */
|
||||
#define FB_VMODE_INTERLACED 1 /* interlaced */
|
||||
#define FB_VMODE_DOUBLE 2 /* double scan */
|
||||
#define FB_VMODE_MASK 255
|
||||
|
||||
#define FB_VMODE_YWRAP 256 /* ywrap instead of panning */
|
||||
#define FB_VMODE_SMOOTH_XPAN 512 /* smooth xpan possible (internally used) */
|
||||
#define FB_VMODE_CONUPDATE 512 /* don't update x/yoffset */
|
||||
|
||||
#define PICOS2KHZ(a) (1000000000UL / (a))
|
||||
#define KHZ2PICOS(a) (1000000000UL / (a))
|
||||
|
||||
struct fb_var_screeninfo
|
||||
{
|
||||
uint32_t xres; /* visible resolution */
|
||||
uint32_t yres;
|
||||
uint32_t xres_virtual; /* virtual resolution */
|
||||
uint32_t yres_virtual;
|
||||
uint32_t xoffset; /* offset from virtual to visible */
|
||||
uint32_t yoffset; /* resolution */
|
||||
|
||||
uint32_t bits_per_pixel; /* guess what */
|
||||
uint32_t grayscale; /* != 0 Graylevels instead of colors */
|
||||
|
||||
struct fb_bitfield red; /* bitfield in fb mem if true color, */
|
||||
struct fb_bitfield green; /* else only length is significant */
|
||||
struct fb_bitfield blue;
|
||||
struct fb_bitfield transp; /* transparency */
|
||||
|
||||
uint32_t nonstd; /* != 0 Non standard pixel format */
|
||||
|
||||
uint32_t activate; /* see FB_ACTIVATE_* */
|
||||
|
||||
uint32_t height; /* height of picture in mm */
|
||||
uint32_t width; /* width of picture in mm */
|
||||
|
||||
uint32_t accel_flags; /* (OBSOLETE) see fb_info.flags */
|
||||
|
||||
/* Timing: All values in pixclocks, except pixclock (of course) */
|
||||
uint32_t pixclock; /* pixel clock in ps (pico seconds) */
|
||||
uint32_t left_margin; /* time from sync to picture */
|
||||
uint32_t right_margin; /* time from picture to sync */
|
||||
uint32_t upper_margin; /* time from sync to picture */
|
||||
uint32_t lower_margin;
|
||||
uint32_t hsync_len; /* length of horizontal sync */
|
||||
uint32_t vsync_len; /* length of vertical sync */
|
||||
uint32_t sync; /* see FB_SYNC_* */
|
||||
uint32_t vmode; /* see FB_VMODE_* */
|
||||
uint32_t rotate; /* angle we rotate counter clockwise */
|
||||
uint32_t refresh;
|
||||
uint32_t reserved[4]; /* Reserved for future compatibility */
|
||||
};
|
||||
|
||||
/* VESA Blanking Levels */
|
||||
#define VESA_NO_BLANKING 0
|
||||
#define VESA_VSYNC_SUSPEND 1
|
||||
#define VESA_HSYNC_SUSPEND 2
|
||||
#define VESA_POWERDOWN 3
|
||||
|
||||
enum
|
||||
{
|
||||
/* screen: unblanked, hsync: on, vsync: on */
|
||||
FB_BLANK_UNBLANK = VESA_NO_BLANKING,
|
||||
/* screen: blanked, hsync: on, vsync: on */
|
||||
FB_BLANK_NORMAL = VESA_NO_BLANKING + 1,
|
||||
/* screen: blanked, hsync: on, vsync: off */
|
||||
FB_BLANK_VSYNC_SUSPEND = VESA_VSYNC_SUSPEND + 1,
|
||||
/* screen: blanked, hsync: off, vsync: on */
|
||||
FB_BLANK_HSYNC_SUSPEND = VESA_HSYNC_SUSPEND + 1,
|
||||
/* screen: blanked, hsync: off, vsync: off */
|
||||
FB_BLANK_POWERDOWN = VESA_POWERDOWN + 1
|
||||
};
|
||||
|
||||
#define FB_VBLANK_VBLANKING 0x001 /* currently in a vertical blank */
|
||||
#define FB_VBLANK_HBLANKING 0x002 /* currently in a horizontal blank */
|
||||
#define FB_VBLANK_HAVE_VBLANK 0x004 /* vertical blanks can be detected */
|
||||
#define FB_VBLANK_HAVE_HBLANK 0x008 /* horizontal blanks can be detected */
|
||||
#define FB_VBLANK_HAVE_COUNT 0x010 /* global retrace counter is available */
|
||||
#define FB_VBLANK_HAVE_VCOUNT 0x020 /* the vcount field is valid */
|
||||
#define FB_VBLANK_HAVE_HCOUNT 0x040 /* the hcount field is valid */
|
||||
#define FB_VBLANK_VSYNCING 0x080 /* currently in a vsync */
|
||||
#define FB_VBLANK_HAVE_VSYNC 0x100 /* verical syncs can be detected */
|
||||
|
||||
struct fb_vblank
|
||||
{
|
||||
uint32_t flags; /* FB_VBLANK flags */
|
||||
uint32_t count; /* counter of retraces since boot */
|
||||
uint32_t vcount; /* current scanline position */
|
||||
uint32_t hcount; /* current scandot position */
|
||||
uint32_t reserved[4]; /* reserved for future compatibility */
|
||||
};
|
||||
|
||||
struct vm_area_struct;
|
||||
struct fb_info;
|
||||
struct device;
|
||||
struct file;
|
||||
|
||||
/* Definitions below are used in the parsed monitor specs */
|
||||
#define FB_DPMS_ACTIVE_OFF 1
|
||||
#define FB_DPMS_SUSPEND 2
|
||||
#define FB_DPMS_STANDBY 4
|
||||
|
||||
#define FB_DISP_DDI 1
|
||||
#define FB_DISP_ANA_700_300 2
|
||||
#define FB_DISP_ANA_714_286 4
|
||||
#define FB_DISP_ANA_1000_400 8
|
||||
#define FB_DISP_ANA_700_000 16
|
||||
|
||||
#define FB_DISP_MONO 32
|
||||
#define FB_DISP_RGB 64
|
||||
#define FB_DISP_MULTI 128
|
||||
#define FB_DISP_UNKNOWN 256
|
||||
|
||||
#define FB_SIGNAL_NONE 0
|
||||
#define FB_SIGNAL_BLANK_BLANK 1
|
||||
#define FB_SIGNAL_SEPARATE 2
|
||||
#define FB_SIGNAL_COMPOSITE 4
|
||||
#define FB_SIGNAL_SYNC_ON_GREEN 8
|
||||
#define FB_SIGNAL_SERRATION_ON 16
|
||||
|
||||
#define FB_MISC_PRIM_COLOR 1
|
||||
#define FB_MISC_1ST_DETAIL 2 /* First Detailed Timing is preferred */
|
||||
|
||||
struct fb_chroma
|
||||
{
|
||||
uint32_t redx; /* in fraction of 1024 */
|
||||
uint32_t greenx;
|
||||
uint32_t bluex;
|
||||
uint32_t whitex;
|
||||
uint32_t redy;
|
||||
uint32_t greeny;
|
||||
uint32_t bluey;
|
||||
uint32_t whitey;
|
||||
};
|
||||
|
||||
struct fb_monspecs
|
||||
{
|
||||
struct fb_chroma chroma;
|
||||
struct fb_videomode *modedb; /* mode database */
|
||||
uint8_t manufacturer[4]; /* Manufacturer */
|
||||
uint8_t monitor[14]; /* Monitor String */
|
||||
uint8_t serial_no[14]; /* Serial Number */
|
||||
uint8_t ascii[14]; /* ? */
|
||||
uint32_t modedb_len; /* mode database length */
|
||||
uint32_t model; /* Monitor Model */
|
||||
uint32_t serial; /* Serial Number - Integer */
|
||||
uint32_t year; /* Year manufactured */
|
||||
uint32_t week; /* Week Manufactured */
|
||||
uint32_t hfmin; /* hfreq lower limit (Hz) */
|
||||
uint32_t hfmax; /* hfreq upper limit (Hz) */
|
||||
uint32_t dclkmin; /* pixelclock lower limit (Hz) */
|
||||
uint32_t dclkmax; /* pixelclock upper limit (Hz) */
|
||||
uint16_t input; /* display type - see FB_DISP_* */
|
||||
uint16_t dpms; /* DPMS support - see FB_DPMS_ */
|
||||
uint16_t signal; /* Signal Type - see FB_SIGNAL_* */
|
||||
uint16_t vfmin; /* vfreq lower limit (Hz) */
|
||||
uint16_t vfmax; /* vfreq upper limit (Hz) */
|
||||
uint16_t gamma; /* Gamma - in fractions of 100 */
|
||||
uint16_t gtf : 1; /* supports GTF */
|
||||
uint16_t misc; /* Misc flags - see FB_MISC_* */
|
||||
uint8_t version; /* EDID version... */
|
||||
uint8_t revision; /* ...and revision */
|
||||
uint8_t max_x; /* Maximum horizontal size (cm) */
|
||||
uint8_t max_y; /* Maximum vertical size (cm) */
|
||||
};
|
||||
|
||||
struct fb_ops
|
||||
{
|
||||
/* checks var and eventually tweaks if to something supported,
|
||||
* DO NOT MODIFY PAR */
|
||||
int32_t (*fb_check_var)(struct fb_var_screeninfo *var, struct fb_info *info);
|
||||
|
||||
/* set the video mode according to info->var */
|
||||
int32_t (*fb_set_par)(struct fb_info *info);
|
||||
|
||||
/* set color register */
|
||||
int32_t (*fb_setcolreg)(uint32_t regno, uint32_t red, uint32_t green,
|
||||
uint32_t blue, uint32_t transp, struct fb_info *info);
|
||||
|
||||
/* pan display */
|
||||
int32_t (*fb_pan_display)(struct fb_var_screeninfo *var, struct fb_info *info);
|
||||
|
||||
/* blank display */
|
||||
int32_t (*fb_blank)(int32_t blank, struct fb_info *info);
|
||||
|
||||
/* wait for blit idle */
|
||||
int32_t (*fb_sync)(struct fb_info *info);
|
||||
|
||||
/* perform fb specific ioctl */
|
||||
int32_t (*fb_ioctl)(uint32_t cmd, uint32_t arg, struct fb_info *info);
|
||||
|
||||
/*
|
||||
* Build the modedb for head 1 (head 2 will come later), check panel infos
|
||||
* from either BIOS or EDID, and pick up the default mode
|
||||
*/
|
||||
void (*fb_check_modes)(struct fb_info *info, struct mode_option *resolution);
|
||||
|
||||
/* Accel functions */
|
||||
#define DEGREES_0 0
|
||||
#define DEGREES_90 1
|
||||
#define DEGREES_180 2
|
||||
#define DEGREES_270 3
|
||||
#define OMIT_LAST 1
|
||||
void (*SetupForSolidFill)(struct fb_info *info, int32_t color, int32_t rop, uint32_t planemask);
|
||||
void (*SubsequentSolidFillRect)(struct fb_info *info, int32_t x, int32_t y, int32_t w, int32_t h);
|
||||
void (*SetupForSolidLine)(struct fb_info *info, int32_t color, int32_t rop, uint32_t planemask);
|
||||
void (*SubsequentSolidHorVertLine)(struct fb_info *info, int32_t x, int32_t y, int32_t len, int32_t dir);
|
||||
void (*SubsequentSolidTwoPointLine)(struct fb_info *info, int32_t xa, int32_t ya, int32_t xb, int32_t yb, int32_t flags);
|
||||
void (*SetupForDashedLine)(struct fb_info *info, int32_t fg, int32_t bg, int32_t rop, uint32_t planemask, int32_t length, uint8_t *pattern);
|
||||
void (*SubsequentDashedTwoPointLine)(struct fb_info *info, int32_t xa, int32_t ya, int32_t xb, int32_t yb, int32_t flags, int32_t phase);
|
||||
void (*SetupForScreenToScreenCopy)(struct fb_info *info, int32_t xdir, int32_t ydir, int32_t rop, uint32_t planemask, int32_t trans_color);
|
||||
void (*SubsequentScreenToScreenCopy)(struct fb_info *info, int32_t xa, int32_t ya, int32_t xb, int32_t yb, int32_t w, int32_t h);
|
||||
void (*ScreenToScreenCopy)(struct fb_info *info, int32_t xa, int32_t ya, int32_t xb, int32_t yb, int32_t w, int32_t h, int32_t rop);
|
||||
void (*SetupForMono8x8PatternFill)(struct fb_info *info, int32_t patternx, int32_t patterny, int32_t fg, int32_t bg, int32_t rop, uint32_t planemask);
|
||||
void (*SubsequentMono8x8PatternFillRect)(struct fb_info *info, int32_t patternx, int32_t patterny, int32_t x, int32_t y, int32_t w, int32_t h);
|
||||
void (*SetupForScanlineCPUToScreenColorExpandFill)(struct fb_info *info, int32_t fg, int32_t bg, int32_t rop, uint32_t planemask);
|
||||
void (*SubsequentScanlineCPUToScreenColorExpandFill)(struct fb_info *info, int32_t x, int32_t y, int32_t w, int32_t h, int32_t skipleft);
|
||||
void (*SubsequentScanline)(struct fb_info *info, uint32_t *buf);
|
||||
void (*SetupForScanlineImageWrite)(struct fb_info *info, int32_t rop, uint32_t planemask, int32_t trans_color, int32_t bpp);
|
||||
void (*SubsequentScanlineImageWriteRect)(struct fb_info *info, int32_t x, int32_t y, int32_t w, int32_t h, int32_t skipleft);
|
||||
void (*SetClippingRectangle)(struct fb_info *info, int32_t xa, int32_t ya, int32_t xb, int32_t yb);
|
||||
void (*DisableClipping)(struct fb_info *info);
|
||||
int (*SetupForCPUToScreenAlphaTexture)(struct fb_info *info,
|
||||
int32_t op, uint16_t red, uint16_t green, uint16_t blue, uint16_t alpha,
|
||||
uint32_t maskFormat, uint32_t dstFormat, uint8_t *alphaPtr, int32_t alphaPitch,
|
||||
int32_t width, int32_t height, int32_t flags);
|
||||
int32_t (*SetupForCPUToScreenTexture)(struct fb_info *info, int32_t op, uint32_t srcFormat, uint32_t dstFormat, uint8_t *texPtr, int32_t texPitch, int32_t width, int32_t height, int32_t flags);
|
||||
void (*SubsequentCPUToScreenTexture)(struct fb_info *info, int32_t dstx, int32_t dsty, int32_t srcx, int32_t srcy, int32_t width, int32_t height);
|
||||
/* Cursor functions */
|
||||
void (*SetCursorColors)(struct fb_info *info, int32_t bg, int32_t fg);
|
||||
void (*SetCursorPosition)(struct fb_info *info, int32_t x, int32_t y);
|
||||
void (*LoadCursorImage)(struct fb_info *info, uint16_t *mask, uint16_t *data, int32_t zoom);
|
||||
void (*HideCursor)(struct fb_info *info);
|
||||
void (*ShowCursor)(struct fb_info *info);
|
||||
long (*CursorInit)(struct fb_info *info);
|
||||
void (*WaitVbl)(struct fb_info *info);
|
||||
};
|
||||
|
||||
struct fb_info
|
||||
{
|
||||
struct fb_var_screeninfo var; /* Current var */
|
||||
struct fb_fix_screeninfo fix; /* Current fix */
|
||||
struct fb_monspecs monspecs; /* Current Monitor specs */
|
||||
struct fb_videomode *mode; /* current mode */
|
||||
char *screen_base; /* virtual address */
|
||||
uint32_t screen_size;
|
||||
char *ram_base; /* base vram */
|
||||
uint32_t ram_size; /* vram size */
|
||||
char *screen_mono;
|
||||
long update_mono;
|
||||
struct fb_ops *fbops;
|
||||
void *par; /* device dependent */
|
||||
};
|
||||
|
||||
/* fbmem.c */
|
||||
extern int fb_pan_display(struct fb_info *info, struct fb_var_screeninfo *var);
|
||||
extern int fb_set_var(struct fb_info *info, struct fb_var_screeninfo *var);
|
||||
extern int fb_blank(struct fb_info *info, int blank);
|
||||
extern int fb_ioctl(struct fb_info *info, uint32_t cmd, uint32_t arg);
|
||||
extern struct fb_info *framebuffer_alloc(uint32_t size);
|
||||
extern void framebuffer_release(struct fb_info *info);
|
||||
|
||||
/* offscreen.c */
|
||||
extern long offscreen_free(struct fb_info *info, void *addr);
|
||||
extern long offscreen_alloc(struct fb_info *info, long amount);
|
||||
extern long offscren_reserved(struct fb_info *info);
|
||||
extern void offscreen_init(struct fb_info *info);
|
||||
|
||||
/* fbmon.c */
|
||||
#define FB_MAXTIMINGS 0
|
||||
#define FB_VSYNCTIMINGS 1
|
||||
#define FB_HSYNCTIMINGS 2
|
||||
#define FB_DCLKTIMINGS 3
|
||||
#define FB_IGNOREMON 0x100
|
||||
|
||||
#define FB_MODE_IS_UNKNOWN 0
|
||||
#define FB_MODE_IS_DETAILED 1
|
||||
#define FB_MODE_IS_STANDARD 2
|
||||
#define FB_MODE_IS_VESA 4
|
||||
#define FB_MODE_IS_CALCULATED 8
|
||||
#define FB_MODE_IS_FIRST 16
|
||||
#define FB_MODE_IS_FROM_VAR 32
|
||||
|
||||
extern void fb_destroy_modedb(struct fb_videomode *modedb);
|
||||
extern int fb_parse_edid(uint8_t *edid, struct fb_var_screeninfo *var);
|
||||
extern void fb_edid_to_monspecs(uint8_t *edid, struct fb_monspecs *specs);
|
||||
extern int32_t fb_get_mode(int32_t flags, uint32_t val, struct fb_var_screeninfo *var, struct fb_info *info);
|
||||
extern int32_t fb_validate_mode(const struct fb_var_screeninfo *var, struct fb_info *info);
|
||||
|
||||
/* modedb.c */
|
||||
#define VESA_MODEDB_SIZE 34
|
||||
extern int fb_find_mode(struct fb_var_screeninfo *var,
|
||||
struct fb_info *info, struct mode_option *resolution ,
|
||||
const struct fb_videomode *db, unsigned int dbsize,
|
||||
const struct fb_videomode *default_mode, unsigned int default_bpp);
|
||||
extern void fb_var_to_videomode(struct fb_videomode *mode, struct fb_var_screeninfo *var);
|
||||
extern void fb_videomode_to_var(struct fb_var_screeninfo *var, struct fb_videomode *mode);
|
||||
extern int fb_mode_is_equal(struct fb_videomode *mode1, struct fb_videomode *mode2);
|
||||
|
||||
struct fb_videomode
|
||||
{
|
||||
uint16_t refresh; /* optional */
|
||||
uint16_t xres;
|
||||
uint16_t yres;
|
||||
uint32_t pixclock;
|
||||
uint16_t left_margin;
|
||||
uint16_t right_margin;
|
||||
uint16_t upper_margin;
|
||||
uint16_t lower_margin;
|
||||
uint16_t hsync_len;
|
||||
uint16_t vsync_len;
|
||||
uint16_t sync;
|
||||
uint16_t vmode;
|
||||
uint16_t flag;
|
||||
};
|
||||
|
||||
extern const struct fb_videomode vesa_modes[];
|
||||
|
||||
extern void start_timeout(void);
|
||||
extern int32_t end_timeout(long msec);
|
||||
extern void mdelay(long msec);
|
||||
extern void install_vbl_timer(void *func, int32_t remove);
|
||||
extern void uninstall_vbl_timer(void *func);
|
||||
|
||||
extern struct fb_info *info_fvdi;
|
||||
#endif /* _FB_H */
|
||||
@@ -1,96 +0,0 @@
|
||||
/*
|
||||
* File: fec.h
|
||||
* Purpose: Driver for the Fast Ethernet Controller (FEC)
|
||||
*
|
||||
* Notes:
|
||||
*/
|
||||
|
||||
#ifndef _FEC_H_
|
||||
#define _FEC_H_
|
||||
|
||||
/********************************************************************/
|
||||
/* MII Speed Settings */
|
||||
#define FEC_MII_10BASE_T 0
|
||||
#define FEC_MII_100BASE_TX 1
|
||||
|
||||
/* MII Duplex Settings */
|
||||
#define FEC_MII_HALF_DUPLEX 0
|
||||
#define FEC_MII_FULL_DUPLEX 1
|
||||
|
||||
/* Timeout for MII communications */
|
||||
#define FEC_MII_TIMEOUT 0x10000
|
||||
|
||||
/* External Interface Modes */
|
||||
#define FEC_MODE_7WIRE 0
|
||||
#define FEC_MODE_MII 1
|
||||
#define FEC_MODE_LOOPBACK 2 /* Internal Loopback */
|
||||
|
||||
/*
|
||||
* FEC Event Log
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
int total; /* total count of errors */
|
||||
int hberr; /* heartbeat error */
|
||||
int babr; /* babbling receiver */
|
||||
int babt; /* babbling transmitter */
|
||||
int gra; /* graceful stop complete */
|
||||
int txf; /* transmit frame */
|
||||
int mii; /* MII */
|
||||
int lc; /* late collision */
|
||||
int rl; /* collision retry limit */
|
||||
int xfun; /* transmit FIFO underrrun */
|
||||
int xferr; /* transmit FIFO error */
|
||||
int rferr; /* receive FIFO error */
|
||||
int dtxf; /* DMA transmit frame */
|
||||
int drxf; /* DMA receive frame */
|
||||
int rfsw_inv; /* Invalid bit in RFSW */
|
||||
int rfsw_l; /* RFSW Last in Frame */
|
||||
int rfsw_m; /* RFSW Miss */
|
||||
int rfsw_bc; /* RFSW Broadcast */
|
||||
int rfsw_mc; /* RFSW Multicast */
|
||||
int rfsw_lg; /* RFSW Length Violation */
|
||||
int rfsw_no; /* RFSW Non-octet */
|
||||
int rfsw_cr; /* RFSW Bad CRC */
|
||||
int rfsw_ov; /* RFSW Overflow */
|
||||
int rfsw_tr; /* RFSW Truncated */
|
||||
} FEC_EVENT_LOG;
|
||||
|
||||
|
||||
extern int fec_mii_write(uint8_t , uint8_t , uint8_t , uint16_t );
|
||||
extern int fec_mii_read(uint8_t , uint8_t , uint8_t , uint16_t *);
|
||||
extern void fec_mii_init(uint8_t, uint32_t);
|
||||
extern void fec_mib_init(uint8_t);
|
||||
extern void fec_mib_dump(uint8_t);
|
||||
extern void fec_log_init(uint8_t);
|
||||
extern void fec_log_dump(uint8_t);
|
||||
extern void fec_debug_dump(uint8_t);
|
||||
extern void fec_duplex (uint8_t, uint8_t);
|
||||
extern uint8_t fec_hash_address(const uint8_t *);
|
||||
extern void fec_set_address (uint8_t ch, const uint8_t *);
|
||||
extern void fec_reset (uint8_t);
|
||||
extern void fec_init(uint8_t ch, uint8_t mode, const uint8_t *pa);
|
||||
extern void fec_rx_start(uint8_t, int8_t *);
|
||||
extern void fec_rx_restart(uint8_t);
|
||||
extern void fec_rx_stop (uint8_t);
|
||||
extern void fec_rx_frame(uint8_t, NIF *);
|
||||
extern void fec0_rx_frame(void);
|
||||
extern void fec1_rx_frame(void);
|
||||
extern void fec_tx_start(uint8_t, int8_t *);
|
||||
extern void fec_tx_restart(uint8_t);
|
||||
extern void fec_tx_stop (uint8_t);
|
||||
extern void fec0_tx_frame(void);
|
||||
extern void fec1_tx_frame(void);
|
||||
extern int fec_send(uint8_t, NIF *, uint8_t *, uint8_t *, uint16_t , NBUF *);
|
||||
extern int fec0_send(NIF *, uint8_t *, uint8_t *, uint16_t , NBUF *);
|
||||
extern int fec1_send(NIF *, uint8_t *, uint8_t *, uint16_t , NBUF *);
|
||||
extern void fec_irq_enable(uint8_t, uint8_t, uint8_t);
|
||||
extern void fec_irq_disable(uint8_t);
|
||||
extern void fec_interrupt_handler(uint8_t);
|
||||
extern bool fec0_interrupt_handler(void *, void *);
|
||||
extern bool fec1_interrupt_handler(void *, void *);
|
||||
extern void fec_eth_setup(uint8_t, uint8_t, uint8_t, uint8_t, const uint8_t *);
|
||||
extern void fec_eth_reset(uint8_t);
|
||||
extern void fec_eth_stop(uint8_t);
|
||||
|
||||
#endif /* _FEC_H_ */
|
||||
@@ -1,93 +0,0 @@
|
||||
/*
|
||||
* File: fecbd.h
|
||||
* Purpose:
|
||||
*
|
||||
* Purpose: Provide a simple buffer management driver
|
||||
*/
|
||||
|
||||
#ifndef _FECBD_H_
|
||||
#define _FECBD_H_
|
||||
|
||||
#include "bas_types.h"
|
||||
|
||||
/********************************************************************/
|
||||
|
||||
#define Rx 1
|
||||
#define Tx 0
|
||||
|
||||
/*
|
||||
* Buffer sizes in bytes
|
||||
*/
|
||||
#ifndef RX_BUF_SZ
|
||||
#define RX_BUF_SZ NBUF_SZ
|
||||
#endif
|
||||
#ifndef TX_BUF_SZ
|
||||
#define TX_BUF_SZ NBUF_SZ
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Number of Rx and Tx Buffers and Buffer Descriptors
|
||||
*/
|
||||
#ifndef NRXBD
|
||||
#define NRXBD 20
|
||||
#endif
|
||||
#ifndef NTXBD
|
||||
#define NTXBD 20
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Buffer Descriptor Format
|
||||
*/
|
||||
typedef struct
|
||||
{
|
||||
uint16_t status; /* control and status */
|
||||
uint16_t length; /* transfer length */
|
||||
uint8_t *data; /* buffer address */
|
||||
} FECBD;
|
||||
|
||||
/*
|
||||
* Bit level definitions for status field of buffer descriptors
|
||||
*/
|
||||
#define TX_BD_R 0x8000
|
||||
#define TX_BD_TO1 0x4000
|
||||
#define TX_BD_W 0x2000
|
||||
#define TX_BD_TO2 0x1000
|
||||
#define TX_BD_INTERRUPT 0x1000 /* MCF547x/8x Only */
|
||||
#define TX_BD_L 0x0800
|
||||
#define TX_BD_TC 0x0400
|
||||
#define TX_BD_DEF 0x0200 /* MCF5272 Only */
|
||||
#define TX_BD_ABC 0x0200
|
||||
#define TX_BD_HB 0x0100 /* MCF5272 Only */
|
||||
#define TX_BD_LC 0x0080 /* MCF5272 Only */
|
||||
#define TX_BD_RL 0x0040 /* MCF5272 Only */
|
||||
#define TX_BD_UN 0x0002 /* MCF5272 Only */
|
||||
#define TX_BD_CSL 0x0001 /* MCF5272 Only */
|
||||
|
||||
#define RX_BD_E 0x8000
|
||||
#define RX_BD_R01 0x4000
|
||||
#define RX_BD_W 0x2000
|
||||
#define RX_BD_R02 0x1000
|
||||
#define RX_BD_INTERRUPT 0x1000 /* MCF547x/8x Only */
|
||||
#define RX_BD_L 0x0800
|
||||
#define RX_BD_M 0x0100
|
||||
#define RX_BD_BC 0x0080
|
||||
#define RX_BD_MC 0x0040
|
||||
#define RX_BD_LG 0x0020
|
||||
#define RX_BD_NO 0x0010
|
||||
#define RX_BD_CR 0x0004
|
||||
#define RX_BD_OV 0x0002
|
||||
#define RX_BD_TR 0x0001
|
||||
#define RX_BD_ERROR (RX_BD_NO | RX_BD_CR | RX_BD_OV | RX_BD_TR)
|
||||
|
||||
/*
|
||||
* Functions provided in fec_bd.c
|
||||
*/
|
||||
extern void fecbd_init(uint8_t);
|
||||
extern uint32_t fecbd_get_start(uint8_t, uint8_t);
|
||||
extern FECBD *fecbd_rx_alloc(uint8_t);
|
||||
extern FECBD *fecbd_tx_alloc(uint8_t);
|
||||
extern FECBD *fecbd_tx_free(uint8_t);
|
||||
|
||||
/*******************************************************************/
|
||||
|
||||
#endif /* _FECBD_H_ */
|
||||
@@ -1,337 +0,0 @@
|
||||
/*---------------------------------------------------------------------------/
|
||||
/ FatFs - FAT file system module include file R0.09a (C)ChaN, 2012
|
||||
/----------------------------------------------------------------------------/
|
||||
/ FatFs module is a generic FAT file system module for small embedded systems.
|
||||
/ This is a free software that opened for education, research and commercial
|
||||
/ developments under license policy of following terms.
|
||||
/
|
||||
/ Copyright (C) 2012, ChaN, all right reserved.
|
||||
/
|
||||
/ * The FatFs module is a free software and there is NO WARRANTY.
|
||||
/ * No restriction on use. You can use, modify and redistribute it for
|
||||
/ personal, non-profit or commercial product UNDER YOUR RESPONSIBILITY.
|
||||
/ * Redistributions of source code must retain the above copyright notice.
|
||||
/
|
||||
/----------------------------------------------------------------------------*/
|
||||
|
||||
#ifndef _FATFS
|
||||
#define _FATFS 4004 /* Revision ID */
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include <bas_types.h>
|
||||
#include <ffconf.h> /* FatFs configuration options */
|
||||
|
||||
#if _FATFS != _FFCONF
|
||||
#error Wrong configuration file (ffconf.h).
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
/* Definitions of volume management */
|
||||
|
||||
#if _MULTI_PARTITION /* Multiple partition configuration */
|
||||
typedef struct {
|
||||
uint8_t pd; /* Physical drive number */
|
||||
uint8_t pt; /* Partition: 0:Auto detect, 1-4:Forced partition) */
|
||||
} PARTITION;
|
||||
extern PARTITION VolToPart[]; /* Volume - Partition resolution table */
|
||||
#define LD2PD(vol) (VolToPart[vol].pd) /* Get physical drive number */
|
||||
#define LD2PT(vol) (VolToPart[vol].pt) /* Get partition index */
|
||||
|
||||
#else /* Single partition configuration */
|
||||
#define LD2PD(vol) (uint8_t)(vol) /* Each logical drive is bound to the same physical drive number */
|
||||
#define LD2PT(vol) 0 /* Always mounts the 1st partition or in SFD */
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
/* Type of path name strings on FatFs API */
|
||||
|
||||
#if _LFN_UNICODE /* Unicode string */
|
||||
#if !_USE_LFN
|
||||
#error _LFN_UNICODE must be 0 in non-LFN cfg.
|
||||
#endif
|
||||
#ifndef _INC_TCHAR
|
||||
typedef uint16_t TCHAR;
|
||||
#define _T(x) L ## x
|
||||
#define _TEXT(x) L ## x
|
||||
#endif
|
||||
|
||||
#else /* ANSI/OEM string */
|
||||
#ifndef _INC_TCHAR
|
||||
typedef char TCHAR;
|
||||
#define _T(x) x
|
||||
#define _TEXT(x) x
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
/* File system object structure (FATFS) */
|
||||
|
||||
typedef struct {
|
||||
uint8_t fs_type; /* FAT sub-type (0:Not mounted) */
|
||||
uint8_t drv; /* Physical drive number */
|
||||
uint8_t csize; /* Sectors per cluster (1,2,4...128) */
|
||||
uint8_t n_fats; /* Number of FAT copies (1,2) */
|
||||
uint8_t wflag; /* win[] dirty flag (1:must be written back) */
|
||||
uint8_t fsi_flag; /* fsinfo dirty flag (1:must be written back) */
|
||||
uint16_t id; /* File system mount ID */
|
||||
uint16_t n_rootdir; /* Number of root directory entries (FAT12/16) */
|
||||
#if _MAX_SS != 512
|
||||
uint16_t ssize; /* Bytes per sector (512, 1024, 2048 or 4096) */
|
||||
#endif
|
||||
#if _FS_REENTRANT
|
||||
_SYNC_t sobj; /* Identifier of sync object */
|
||||
#endif
|
||||
#if !_FS_READONLY
|
||||
uint32_t last_clust; /* Last allocated cluster */
|
||||
uint32_t free_clust; /* Number of free clusters */
|
||||
uint32_t fsi_sector; /* fsinfo sector (FAT32) */
|
||||
#endif
|
||||
#if _FS_RPATH
|
||||
uint32_t cdir; /* Current directory start cluster (0:root) */
|
||||
#endif
|
||||
uint32_t n_fatent; /* Number of FAT entries (= number of clusters + 2) */
|
||||
uint32_t fsize; /* Sectors per FAT */
|
||||
uint32_t fatbase; /* FAT start sector */
|
||||
uint32_t dirbase; /* Root directory start sector (FAT32:Cluster#) */
|
||||
uint32_t database; /* Data start sector */
|
||||
uint32_t winsect; /* Current sector appearing in the win[] */
|
||||
uint8_t win[_MAX_SS]; /* Disk access window for Directory, FAT (and Data on tiny cfg) */
|
||||
} FATFS;
|
||||
|
||||
|
||||
|
||||
/* File object structure (FIL) */
|
||||
|
||||
typedef struct {
|
||||
FATFS* fs; /* Pointer to the related file system object */
|
||||
uint16_t id; /* File system mount ID of the related file system object */
|
||||
uint8_t flag; /* File status flags */
|
||||
uint8_t pad1;
|
||||
uint32_t fptr; /* File read/write pointer (0ed on file open) */
|
||||
uint32_t fsize; /* File size */
|
||||
uint32_t sclust; /* File data start cluster (0:no data cluster, always 0 when fsize is 0) */
|
||||
uint32_t clust; /* Current cluster of fpter */
|
||||
uint32_t dsect; /* Current data sector of fpter */
|
||||
#if !_FS_READONLY
|
||||
uint32_t dir_sect; /* Sector containing the directory entry */
|
||||
uint8_t* dir_ptr; /* Pointer to the directory entry in the window */
|
||||
#endif
|
||||
#if _USE_FASTSEEK
|
||||
uint32_t* cltbl; /* Pointer to the cluster link map table (null on file open) */
|
||||
#endif
|
||||
#if _FS_LOCK
|
||||
uint32_t lockid; /* File lock ID (index of file semaphore table Files[]) */
|
||||
#endif
|
||||
#if !_FS_TINY
|
||||
uint8_t buf[_MAX_SS]; /* File data read/write buffer */
|
||||
#endif
|
||||
} FIL;
|
||||
|
||||
|
||||
|
||||
/* Directory object structure (DIR) */
|
||||
|
||||
typedef struct {
|
||||
FATFS* fs; /* Pointer to the owner file system object */
|
||||
uint16_t id; /* Owner file system mount ID */
|
||||
uint16_t index; /* Current read/write index number */
|
||||
uint32_t sclust; /* Table start cluster (0:Root dir) */
|
||||
uint32_t clust; /* Current cluster */
|
||||
uint32_t sect; /* Current sector */
|
||||
uint8_t* dir; /* Pointer to the current SFN entry in the win[] */
|
||||
uint8_t* fn; /* Pointer to the SFN (in/out) {file[8],ext[3],status[1]} */
|
||||
#if _USE_LFN
|
||||
uint16_t* lfn; /* Pointer to the LFN working buffer */
|
||||
uint16_t lfn_idx; /* Last matched LFN index number (0xFFFF:No LFN) */
|
||||
#endif
|
||||
} DIR;
|
||||
|
||||
|
||||
|
||||
/* File status structure (FILINFO) */
|
||||
|
||||
typedef struct {
|
||||
uint32_t fsize; /* File size */
|
||||
uint16_t fdate; /* Last modified date */
|
||||
uint16_t ftime; /* Last modified time */
|
||||
uint8_t fattrib; /* Attribute */
|
||||
TCHAR fname[13]; /* Short file name (8.3 format) */
|
||||
#if _USE_LFN
|
||||
TCHAR* lfname; /* Pointer to the LFN buffer */
|
||||
uint32_t lfsize; /* Size of LFN buffer in TCHAR */
|
||||
#endif
|
||||
} FILINFO;
|
||||
|
||||
|
||||
|
||||
/* File function return code (FRESULT) */
|
||||
|
||||
typedef enum {
|
||||
FR_OK = 0, /* (0) Succeeded */
|
||||
FR_DISK_ERR, /* (1) A hard error occurred in the low level disk I/O layer */
|
||||
FR_INT_ERR, /* (2) Assertion failed */
|
||||
FR_NOT_READY, /* (3) The physical drive cannot work */
|
||||
FR_NO_FILE, /* (4) Could not find the file */
|
||||
FR_NO_PATH, /* (5) Could not find the path */
|
||||
FR_INVALID_NAME, /* (6) The path name format is invalid */
|
||||
FR_DENIED, /* (7) Access denied due to prohibited access or directory full */
|
||||
FR_EXIST, /* (8) Access denied due to prohibited access */
|
||||
FR_INVALID_OBJECT, /* (9) The file/directory object is invalid */
|
||||
FR_WRITE_PROTECTED, /* (10) The physical drive is write protected */
|
||||
FR_INVALID_DRIVE, /* (11) The logical drive number is invalid */
|
||||
FR_NOT_ENABLED, /* (12) The volume has no work area */
|
||||
FR_NO_FILESYSTEM, /* (13) There is no valid FAT volume */
|
||||
FR_MKFS_ABORTED, /* (14) The f_mkfs() aborted due to any parameter error */
|
||||
FR_TIMEOUT, /* (15) Could not get a grant to access the volume within defined period */
|
||||
FR_LOCKED, /* (16) The operation is rejected according to the file sharing policy */
|
||||
FR_NOT_ENOUGH_CORE, /* (17) LFN working buffer could not be allocated */
|
||||
FR_TOO_MANY_OPEN_FILES, /* (18) Number of open files > _FS_SHARE */
|
||||
FR_INVALID_PARAMETER /* (19) Given parameter is invalid */
|
||||
} FRESULT;
|
||||
|
||||
|
||||
|
||||
/*--------------------------------------------------------------*/
|
||||
/* FatFs module application interface */
|
||||
|
||||
FRESULT f_mount (uint8_t, FATFS*); /* Mount/Unmount a logical drive */
|
||||
FRESULT f_open (FIL*, const TCHAR*, uint8_t); /* Open or create a file */
|
||||
FRESULT f_read (FIL*, void*, uint32_t, uint32_t*); /* Read data from a file */
|
||||
FRESULT f_lseek (FIL*, uint32_t); /* Move file pointer of a file object */
|
||||
FRESULT f_close (FIL*); /* Close an open file object */
|
||||
FRESULT f_opendir (DIR*, const char*); /* Open an existing directory */
|
||||
FRESULT f_readdir (DIR*, FILINFO*); /* Read a directory item */
|
||||
FRESULT f_stat (const TCHAR*, FILINFO*); /* Get file status */
|
||||
FRESULT f_write (FIL*, const void*, uint32_t, uint32_t*); /* Write data to a file */
|
||||
FRESULT f_getfree (const TCHAR*, uint32_t*, FATFS**); /* Get number of free clusters on the drive */
|
||||
FRESULT f_truncate (FIL*); /* Truncate file */
|
||||
FRESULT f_sync (FIL*); /* Flush cached data of a writing file */
|
||||
FRESULT f_unlink (const TCHAR*); /* Delete an existing file or directory */
|
||||
FRESULT f_mkdir (const TCHAR*); /* Create a new directory */
|
||||
FRESULT f_chmod (const TCHAR*, uint8_t, uint8_t); /* Change attribute of the file/dir */
|
||||
FRESULT f_utime (const TCHAR*, const FILINFO*); /* Change times-tamp of the file/dir */
|
||||
FRESULT f_rename (const TCHAR*, const TCHAR*); /* Rename/Move a file or directory */
|
||||
FRESULT f_chdrive (uint8_t); /* Change current drive */
|
||||
FRESULT f_chdir (const TCHAR*); /* Change current directory */
|
||||
FRESULT f_getcwd (TCHAR*, uint32_t); /* Get current directory */
|
||||
FRESULT f_forward (FIL*, uint32_t(*)(const uint8_t*,uint32_t), uint32_t, uint32_t*); /* Forward data to the stream */
|
||||
FRESULT f_mkfs (uint8_t, uint8_t, uint32_t); /* Create a file system on the drive */
|
||||
FRESULT f_fdisk (uint8_t, const uint32_t[], void*); /* Divide a physical drive into some partitions */
|
||||
int f_putc (TCHAR, FIL*); /* Put a character to the file */
|
||||
int f_puts (const TCHAR*, FIL*); /* Put a string to the file */
|
||||
int f_printf (FIL*, const TCHAR*, ...); /* Put a formatted string to the file */
|
||||
TCHAR* f_gets (TCHAR*, int, FIL*); /* Get a string from the file */
|
||||
|
||||
#define f_eof(fp) (((fp)->fptr == (fp)->fsize) ? 1 : 0)
|
||||
#define f_error(fp) (((fp)->flag & FA__ERROR) ? 1 : 0)
|
||||
#define f_tell(fp) ((fp)->fptr)
|
||||
#define f_size(fp) ((fp)->fsize)
|
||||
|
||||
#ifndef EOF
|
||||
#define EOF (-1)
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
/*--------------------------------------------------------------*/
|
||||
/* Additional user defined functions */
|
||||
|
||||
/* RTC function */
|
||||
#if !_FS_READONLY
|
||||
uint32_t get_fattime (void);
|
||||
#endif
|
||||
|
||||
/* Unicode support functions */
|
||||
#if _USE_LFN /* Unicode - OEM code conversion */
|
||||
uint16_t ff_convert (uint16_t, uint32_t); /* OEM-Unicode bidirectional conversion */
|
||||
uint16_t ff_wtoupper (uint16_t); /* Unicode upper-case conversion */
|
||||
#if _USE_LFN == 3 /* Memory functions */
|
||||
void* ff_memalloc (uint32_t); /* Allocate memory block */
|
||||
void ff_memfree (void*); /* Free memory block */
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/* Sync functions */
|
||||
#if _FS_REENTRANT
|
||||
int ff_cre_syncobj (uint8_t, _SYNC_t*);/* Create a sync object */
|
||||
int ff_req_grant (_SYNC_t); /* Lock sync object */
|
||||
void ff_rel_grant (_SYNC_t); /* Unlock sync object */
|
||||
int ff_del_syncobj (_SYNC_t); /* Delete a sync object */
|
||||
#endif
|
||||
|
||||
|
||||
|
||||
|
||||
/*--------------------------------------------------------------*/
|
||||
/* Flags and offset address */
|
||||
|
||||
|
||||
/* File access control and file status flags (FIL.flag) */
|
||||
|
||||
#define FA_READ 0x01
|
||||
#define FA_OPEN_EXISTING 0x00
|
||||
#define FA__ERROR 0x80
|
||||
|
||||
#if !_FS_READONLY
|
||||
#define FA_WRITE 0x02
|
||||
#define FA_CREATE_NEW 0x04
|
||||
#define FA_CREATE_ALWAYS 0x08
|
||||
#define FA_OPEN_ALWAYS 0x10
|
||||
#define FA__WRITTEN 0x20
|
||||
#define FA__DIRTY 0x40
|
||||
#endif
|
||||
|
||||
|
||||
/* FAT sub type (FATFS.fs_type) */
|
||||
|
||||
#define FS_FAT12 1
|
||||
#define FS_FAT16 2
|
||||
#define FS_FAT32 3
|
||||
|
||||
|
||||
/* File attribute bits for directory entry */
|
||||
|
||||
#define AM_RDO 0x01 /* Read only */
|
||||
#define AM_HID 0x02 /* Hidden */
|
||||
#define AM_SYS 0x04 /* System */
|
||||
#define AM_VOL 0x08 /* Volume label */
|
||||
#define AM_LFN 0x0F /* LFN entry */
|
||||
#define AM_DIR 0x10 /* Directory */
|
||||
#define AM_ARC 0x20 /* Archive */
|
||||
#define AM_MASK 0x3F /* Mask of defined bits */
|
||||
|
||||
|
||||
/* Fast seek feature */
|
||||
#define CREATE_LINKMAP 0xFFFFFFFF
|
||||
|
||||
|
||||
|
||||
/*--------------------------------*/
|
||||
/* Multi-byte word access macros */
|
||||
|
||||
#if _WORD_ACCESS == 1 /* Enable word access to the FAT structure */
|
||||
#define LD_WORD(ptr) (uint16_t)(* (uint16_t *)(uint8_t *)(ptr))
|
||||
#define LD_DWORD(ptr) (uint32_t)(* (uint32_t *)(uint8_t *)(ptr))
|
||||
#define ST_WORD(ptr,val) *(uint16_t *) (uint8_t *)(ptr) = (uint16_t)(val)
|
||||
#define ST_DWORD(ptr,val) *(uint32_t *) (uint8_t *)(ptr) = (uint32_t)(val)
|
||||
#else /* Use byte-by-byte access to the FAT structure */
|
||||
#define LD_WORD(ptr) (uint16_t)(((uint16_t)*((uint8_t *)(ptr) + 1) << 8) | (uint16_t) *(uint8_t *)(ptr))
|
||||
#define LD_DWORD(ptr) (uint32_t)(((uint32_t)*((uint8_t *)(ptr) + 3) << 24) | ((uint32_t)*((uint8_t*)(ptr) + 2) << 16) | ((uint16_t) *((uint8_t*)(ptr) + 1) << 8) | *(uint8_t*)(ptr))
|
||||
#define ST_WORD(ptr,val) *(uint8_t *)(ptr) = (uint8_t)(val); *((uint8_t *)(ptr) + 1) = (uint8_t)((uint16_t)(val) >> 8)
|
||||
#define ST_DWORD(ptr,val) *(uint8_t *)(ptr) = (uint8_t)(val); *((uint8_t *)(ptr) + 1) = (uint8_t)((uint16_t)(val) >> 8); *((uint8_t*)(ptr) + 2) = (uint8_t)((uint32_t)(val) >> 16); *((uint8_t *)(ptr) + 3) = (uint8_t)((uint32_t)(val) >> 24)
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* _FATFS */
|
||||
@@ -1,190 +0,0 @@
|
||||
/*---------------------------------------------------------------------------/
|
||||
/ FatFs - FAT file system module configuration file R0.09a (C)ChaN, 2012
|
||||
/----------------------------------------------------------------------------/
|
||||
/
|
||||
/ CAUTION! Do not forget to make clean the project after any changes to
|
||||
/ the configuration options.
|
||||
/
|
||||
/----------------------------------------------------------------------------*/
|
||||
#ifndef _FFCONF
|
||||
#define _FFCONF 4004 /* Revision ID */
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------/
|
||||
/ Functions and Buffer Configurations
|
||||
/----------------------------------------------------------------------------*/
|
||||
|
||||
#define _FS_TINY 0 /* 0:Normal or 1:Tiny */
|
||||
/* When _FS_TINY is set to 1, FatFs uses the sector buffer in the file system
|
||||
/ object instead of the sector buffer in the individual file object for file
|
||||
/ data transfer. This reduces memory consumption 512 bytes each file object. */
|
||||
|
||||
|
||||
#define _FS_READONLY 0 /* 0:Read/Write or 1:Read only */
|
||||
/* Setting _FS_READONLY to 1 defines read only configuration. This removes
|
||||
/ writing functions, f_write, f_sync, f_unlink, f_mkdir, f_chmod, f_rename,
|
||||
/ f_truncate and useless f_getfree. */
|
||||
|
||||
|
||||
#define _FS_MINIMIZE 0 /* 0 to 3 */
|
||||
/* The _FS_MINIMIZE option defines minimization level to remove some functions.
|
||||
/
|
||||
/ 0: Full function.
|
||||
/ 1: f_stat, f_getfree, f_unlink, f_mkdir, f_chmod, f_truncate and f_rename
|
||||
/ are removed.
|
||||
/ 2: f_opendir and f_readdir are removed in addition to 1.
|
||||
/ 3: f_lseek is removed in addition to 2. */
|
||||
|
||||
|
||||
#define _USE_STRFUNC 1 /* 0:Disable or 1-2:Enable */
|
||||
/* To enable string functions, set _USE_STRFUNC to 1 or 2. */
|
||||
|
||||
|
||||
#define _USE_MKFS 0 /* 0:Disable or 1:Enable */
|
||||
/* To enable f_mkfs function, set _USE_MKFS to 1 and set _FS_READONLY to 0 */
|
||||
|
||||
|
||||
#define _USE_FORWARD 0 /* 0:Disable or 1:Enable */
|
||||
/* To enable f_forward function, set _USE_FORWARD to 1 and set _FS_TINY to 1. */
|
||||
|
||||
|
||||
#define _USE_FASTSEEK 0 /* 0:Disable or 1:Enable */
|
||||
/* To enable fast seek feature, set _USE_FASTSEEK to 1. */
|
||||
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------/
|
||||
/ Locale and Namespace Configurations
|
||||
/----------------------------------------------------------------------------*/
|
||||
|
||||
#define _CODE_PAGE 858
|
||||
/* The _CODE_PAGE specifies the OEM code page to be used on the target system.
|
||||
/ Incorrect setting of the code page can cause a file open failure.
|
||||
/
|
||||
/ 932 - Japanese Shift-JIS (DBCS, OEM, Windows)
|
||||
/ 936 - Simplified Chinese GBK (DBCS, OEM, Windows)
|
||||
/ 949 - Korean (DBCS, OEM, Windows)
|
||||
/ 950 - Traditional Chinese Big5 (DBCS, OEM, Windows)
|
||||
/ 1250 - Central Europe (Windows)
|
||||
/ 1251 - Cyrillic (Windows)
|
||||
/ 1252 - Latin 1 (Windows)
|
||||
/ 1253 - Greek (Windows)
|
||||
/ 1254 - Turkish (Windows)
|
||||
/ 1255 - Hebrew (Windows)
|
||||
/ 1256 - Arabic (Windows)
|
||||
/ 1257 - Baltic (Windows)
|
||||
/ 1258 - Vietnam (OEM, Windows)
|
||||
/ 437 - U.S. (OEM)
|
||||
/ 720 - Arabic (OEM)
|
||||
/ 737 - Greek (OEM)
|
||||
/ 775 - Baltic (OEM)
|
||||
/ 850 - Multilingual Latin 1 (OEM)
|
||||
/ 858 - Multilingual Latin 1 + Euro (OEM)
|
||||
/ 852 - Latin 2 (OEM)
|
||||
/ 855 - Cyrillic (OEM)
|
||||
/ 866 - Russian (OEM)
|
||||
/ 857 - Turkish (OEM)
|
||||
/ 862 - Hebrew (OEM)
|
||||
/ 874 - Thai (OEM, Windows)
|
||||
/ 1 - ASCII only (Valid for non LFN cfg.)
|
||||
*/
|
||||
|
||||
|
||||
#define _USE_LFN 0 /* 0 to 3 */
|
||||
#define _MAX_LFN 255 /* Maximum LFN length to handle (12 to 255) */
|
||||
/* The _USE_LFN option switches the LFN support.
|
||||
/
|
||||
/ 0: Disable LFN feature. _MAX_LFN and _LFN_UNICODE have no effect.
|
||||
/ 1: Enable LFN with static working buffer on the BSS. Always NOT reentrant.
|
||||
/ 2: Enable LFN with dynamic working buffer on the STACK.
|
||||
/ 3: Enable LFN with dynamic working buffer on the HEAP.
|
||||
/
|
||||
/ The LFN working buffer occupies (_MAX_LFN + 1) * 2 bytes. To enable LFN,
|
||||
/ Unicode handling functions ff_convert() and ff_wtoupper() must be added
|
||||
/ to the project. When enable to use heap, memory control functions
|
||||
/ ff_memalloc() and ff_memfree() must be added to the project. */
|
||||
|
||||
|
||||
#define _LFN_UNICODE 0 /* 0:ANSI/OEM or 1:Unicode */
|
||||
/* To switch the character code set on FatFs API to Unicode,
|
||||
/ enable LFN feature and set _LFN_UNICODE to 1. */
|
||||
|
||||
|
||||
#define _FS_RPATH 0 /* 0 to 2 */
|
||||
/* The _FS_RPATH option configures relative path feature.
|
||||
/
|
||||
/ 0: Disable relative path feature and remove related functions.
|
||||
/ 1: Enable relative path. f_chdrive() and f_chdir() are available.
|
||||
/ 2: f_getcwd() is available in addition to 1.
|
||||
/
|
||||
/ Note that output of the f_readdir fnction is affected by this option. */
|
||||
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------/
|
||||
/ Physical Drive Configurations
|
||||
/----------------------------------------------------------------------------*/
|
||||
|
||||
#define _VOLUMES 1
|
||||
/* Number of volumes (logical drives) to be used. */
|
||||
|
||||
|
||||
#define _MAX_SS 512 /* 512, 1024, 2048 or 4096 */
|
||||
/* Maximum sector size to be handled.
|
||||
/ Always set 512 for memory card and hard disk but a larger value may be
|
||||
/ required for on-board flash memory, floppy disk and optical disk.
|
||||
/ When _MAX_SS is larger than 512, it configures FatFs to variable sector size
|
||||
/ and GET_SECTOR_SIZE command must be implememted to the disk_ioctl function. */
|
||||
|
||||
|
||||
#define _MULTI_PARTITION 0 /* 0:Single partition, 1/2:Enable multiple partition */
|
||||
/* When set to 0, each volume is bound to the same physical drive number and
|
||||
/ it can mount only first primaly partition. When it is set to 1, each volume
|
||||
/ is tied to the partitions listed in VolToPart[]. */
|
||||
|
||||
|
||||
#define _USE_ERASE 0 /* 0:Disable or 1:Enable */
|
||||
/* To enable sector erase feature, set _USE_ERASE to 1. CTRL_ERASE_SECTOR command
|
||||
/ should be added to the disk_ioctl functio. */
|
||||
|
||||
|
||||
|
||||
/*---------------------------------------------------------------------------/
|
||||
/ System Configurations
|
||||
/----------------------------------------------------------------------------*/
|
||||
|
||||
#define _WORD_ACCESS 0 /* 0 or 1 */
|
||||
/* Set 0 first and it is always compatible with all platforms. The _WORD_ACCESS
|
||||
/ option defines which access method is used to the word data on the FAT volume.
|
||||
/
|
||||
/ 0: Byte-by-byte access.
|
||||
/ 1: Word access. Do not choose this unless following condition is met.
|
||||
/
|
||||
/ When the byte order on the memory is big-endian or address miss-aligned word
|
||||
/ access results incorrect behavior, the _WORD_ACCESS must be set to 0.
|
||||
/ If it is not the case, the value can also be set to 1 to improve the
|
||||
/ performance and code size.
|
||||
*/
|
||||
|
||||
|
||||
/* A header file that defines sync object types on the O/S, such as
|
||||
/ windows.h, ucos_ii.h and semphr.h, must be included prior to ff.h. */
|
||||
|
||||
#define _FS_REENTRANT 0 /* 0:Disable or 1:Enable */
|
||||
#define _FS_TIMEOUT 1000 /* Timeout period in unit of time ticks */
|
||||
#define _SYNC_t HANDLE /* O/S dependent type of sync object. e.g. HANDLE, OS_EVENT*, ID and etc.. */
|
||||
|
||||
/* The _FS_REENTRANT option switches the reentrancy (thread safe) of the FatFs module.
|
||||
/
|
||||
/ 0: Disable reentrancy. _SYNC_t and _FS_TIMEOUT have no effect.
|
||||
/ 1: Enable reentrancy. Also user provided synchronization handlers,
|
||||
/ ff_req_grant, ff_rel_grant, ff_del_syncobj and ff_cre_syncobj
|
||||
/ function must be added to the project. */
|
||||
|
||||
|
||||
#define _FS_LOCK 0 /* 0:Disable or >=1:Enable */
|
||||
/* To enable file lock control feature, set _FS_LOCK to 1 or greater.
|
||||
The value defines how many files can be opened simultaneously. */
|
||||
|
||||
|
||||
#endif /* _FFCONFIG */
|
||||
@@ -1,51 +0,0 @@
|
||||
#ifndef _FIREBEE_H_
|
||||
#define _FIREBEE_H_
|
||||
|
||||
/*
|
||||
* firebee.h
|
||||
*
|
||||
* preprocessor definitions for the Firebee machine. This file should contain nothing but preprocessor
|
||||
* definition that evaluate to numbers. It is intended for use in C sources as well as in linker control
|
||||
* files, so care must be taken to not break the syntax of either one.
|
||||
*
|
||||
* This file is part of BaS_gcc.
|
||||
*
|
||||
* BaS_gcc is free software: you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation, either version 3 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* BaS_gcc is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with BaS_gcc. If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
* Created on: 26.02.2013
|
||||
* Author: Markus Fröschle
|
||||
*/
|
||||
|
||||
#define SYSCLK 132000 /* NOTE: 132 _is_ correct. 133 _is_ wrong. Do not change! */
|
||||
|
||||
#define BOOTFLASH_BASE_ADDRESS 0xE0000000
|
||||
#define BOOTFLASH_SIZE 0x800000 /* FireBee has 8 MByte Flash */
|
||||
#define BOOTFLASH_BAM (BOOTFLASH_SIZE - 1)
|
||||
|
||||
#define SDRAM_START 0x00000000 /* start at address 0 */
|
||||
#define SDRAM_SIZE 0x20000000 /* 512 MB on the Firebee */
|
||||
|
||||
#ifdef COMPILE_RAM
|
||||
#define TARGET_ADDRESS (SDRAM_START + SDRAM_SIZE - 0x200000)
|
||||
#else
|
||||
#define TARGET_ADDRESS BOOTFLASH_BASE_ADDRESS
|
||||
#define BFL_TARGET_ADDRESS 0x0100000 /* load address for basflash */
|
||||
|
||||
#endif /* COMPILE_RAM */
|
||||
|
||||
#define DRIVER_MEM_BUFFER_SIZE 0x100000
|
||||
|
||||
#define EMUTOS_BASE_ADDRESS 0xe0600000
|
||||
|
||||
#endif /* _FIREBEE_H_ */
|
||||
@@ -1,100 +0,0 @@
|
||||
/*
|
||||
* font.h - font specific definitions
|
||||
*
|
||||
* Copyright (c) 2001 Lineo, Inc.
|
||||
* Copyright (c) 2004 by Authors:
|
||||
*
|
||||
* Authors:
|
||||
* MAD Martin Doering
|
||||
*
|
||||
* This file is distributed under the GPL, version 2 or at your
|
||||
* option any later version. See doc/license.txt for details.
|
||||
*/
|
||||
|
||||
#ifndef FONT_H
|
||||
#define FONT_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/* font header flags */
|
||||
|
||||
#define F_DEFAULT 1 /* this is the default font (face and size) */
|
||||
#define F_HORZ_OFF 2 /* there are left and right offset tables */
|
||||
#define F_STDFORM 4 /* is the font in standard format */
|
||||
#define F_MONOSPACE 8 /* is the font monospaced */
|
||||
|
||||
/* font style bits */
|
||||
|
||||
#define F_THICKEN 1
|
||||
#define F_LIGHT 2
|
||||
#define F_SKEW 4
|
||||
#define F_UNDER 8
|
||||
#define F_OUTLINE 16
|
||||
#define F_SHADOW 32
|
||||
|
||||
/* font specific linea variables */
|
||||
|
||||
extern const uint16_t *v_fnt_ad; /* address of current monospace font */
|
||||
extern const uint16_t *v_off_ad; /* address of font offset table */
|
||||
extern uint16_t v_fnt_nd; /* ascii code of last cell in font */
|
||||
extern uint16_t v_fnt_st; /* ascii code of first cell in font */
|
||||
extern uint16_t v_fnt_wr; /* font cell wrap */
|
||||
|
||||
/* character cell specific linea variables */
|
||||
|
||||
extern uint16_t v_cel_ht; /* cell height (width is 8) */
|
||||
extern uint16_t v_cel_mx; /* needed by MiNT: columns on the screen minus 1 */
|
||||
extern uint16_t v_cel_my; /* needed by MiNT: rows on the screen minus 1 */
|
||||
extern uint16_t v_cel_wr; /* needed by MiNT: length (in int8_ts) of a line of characters */
|
||||
|
||||
/*
|
||||
* font_ring is a struct of four pointers, each of which points to
|
||||
* a list of font headers linked together to form a string.
|
||||
*/
|
||||
|
||||
extern struct font_head *font_ring[4]; /* Ring of available fonts */
|
||||
extern int16_t font_count; /* all three fonts and NULL */
|
||||
|
||||
/* the font header descibes a font */
|
||||
|
||||
struct font_head {
|
||||
int16_t font_id;
|
||||
int16_t point;
|
||||
int8_t name[32];
|
||||
uint16_t first_ade;
|
||||
uint16_t last_ade;
|
||||
uint16_t top;
|
||||
uint16_t ascent;
|
||||
uint16_t half;
|
||||
uint16_t descent;
|
||||
uint16_t bottom;
|
||||
uint16_t max_char_width;
|
||||
uint16_t max_cell_width;
|
||||
uint16_t left_offset; /* amount character slants left when skewed */
|
||||
uint16_t right_offset; /* amount character slants right */
|
||||
uint16_t thicken; /* number of pixels to smear */
|
||||
uint16_t ul_size; /* size of the underline */
|
||||
uint16_t lighten; /* mask to and with to lighten */
|
||||
uint16_t skew; /* mask for skewing */
|
||||
uint16_t flags;
|
||||
|
||||
const uint8_t *hor_table; /* horizontal offsets */
|
||||
const uint16_t *off_table; /* character offsets */
|
||||
const uint16_t *dat_table; /* character definitions */
|
||||
uint16_t form_width;
|
||||
uint16_t form_height;
|
||||
|
||||
struct font_head *next_font;/* pointer to next font */
|
||||
uint16_t font_seg;
|
||||
};
|
||||
|
||||
|
||||
|
||||
/* prototypes */
|
||||
|
||||
void font_init(void); /* initialize BIOS font ring */
|
||||
void font_set_default(void); /* choose the default font */
|
||||
|
||||
extern struct font_head *fnt;
|
||||
|
||||
#endif /* FONT_H */
|
||||
@@ -1,55 +0,0 @@
|
||||
/* ------------------------------------------------------------------------- */
|
||||
/* i2c-algo-bit.h i2c driver algorithms for bit-shift adapters */
|
||||
/* ------------------------------------------------------------------------- */
|
||||
/* Copyright (C) 1995-99 Simon G. Vogl
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
/* With some changes from Ky<4B>sti M<>lkki <kmalkki@cc.hut.fi> and even
|
||||
Frodo Looijaard <frodol@dds.nl> */
|
||||
|
||||
/* $Id: i2c-algo-bit.h,v 1.1.1.1 2012/08/16 18:43:05 mfro Exp $ */
|
||||
|
||||
#ifndef I2C_ALGO_BIT_H
|
||||
#define I2C_ALGO_BIT_H
|
||||
|
||||
/* --- Defines for bit-adapters --------------------------------------- */
|
||||
/*
|
||||
* This struct contains the hw-dependent functions of bit-style adapters to
|
||||
* manipulate the line states, and to init any hw-specific features. This is
|
||||
* only used if you have more than one hw-type of adapter running.
|
||||
*/
|
||||
struct i2c_algo_bit_data
|
||||
{
|
||||
void *data; /* private data for lowlevel routines */
|
||||
void (*setsda) (void *data, int state);
|
||||
void (*setscl) (void *data, int state);
|
||||
int (*getsda) (void *data);
|
||||
int (*getscl) (void *data);
|
||||
|
||||
/* local settings */
|
||||
int udelay; /* half-clock-cycle time in microsecs */
|
||||
/* i.e. clock is (500 / udelay) KHz */
|
||||
int mdelay; /* in millisecs, unused */
|
||||
int timeout; /* in jiffies */
|
||||
};
|
||||
|
||||
#define I2C_BIT_ADAP_MAX 16
|
||||
|
||||
int i2c_bit_add_bus(struct i2c_adapter *);
|
||||
int i2c_bit_del_bus(struct i2c_adapter *);
|
||||
|
||||
#endif /* I2C_ALGO_BIT_H */
|
||||
@@ -1,97 +0,0 @@
|
||||
/* ------------------------------------------------------------------------- */
|
||||
/* */
|
||||
/* i2c.h - definitions for the i2c-bus interface */
|
||||
/* */
|
||||
/* ------------------------------------------------------------------------- */
|
||||
/* Copyright (C) 1995-2000 Simon G. Vogl
|
||||
|
||||
This program is free software; you can redistribute it and/or modify
|
||||
it under the terms of the GNU General Public License as published by
|
||||
the Free Software Foundation; either version 2 of the License, or
|
||||
(at your option) any later version.
|
||||
|
||||
This program is distributed in the hope that it will be useful,
|
||||
but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
GNU General Public License for more details.
|
||||
|
||||
You should have received a copy of the GNU General Public License
|
||||
along with this program; if not, write to the Free Software
|
||||
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
|
||||
/* ------------------------------------------------------------------------- */
|
||||
|
||||
/* With some changes from Ky<4B>sti M<>lkki <kmalkki@cc.hut.fi> and
|
||||
Frodo Looijaard <frodol@dds.nl> */
|
||||
|
||||
/* $Id: i2c.h,v 1.1.1.1 2012/08/16 18:43:05 mfro Exp $ */
|
||||
|
||||
#ifndef _I2C_H
|
||||
#define _I2C_H
|
||||
|
||||
#include "bas_types.h"
|
||||
|
||||
/* --- General options ------------------------------------------------ */
|
||||
|
||||
struct i2c_msg;
|
||||
struct i2c_algorithm;
|
||||
struct i2c_adapter;
|
||||
|
||||
/* Transfer num messages.
|
||||
*/
|
||||
extern int i2c_transfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num);
|
||||
|
||||
/*
|
||||
* The following structs are for those who like to implement new bus drivers:
|
||||
* i2c_algorithm is the interface to a class of hardware solutions which can
|
||||
* be addressed using the same bus algorithms - i.e. bit-banging or the PCF8584
|
||||
* to name two of the most common.
|
||||
*/
|
||||
struct i2c_algorithm
|
||||
{
|
||||
unsigned int id;
|
||||
int (*master_xfer)(struct i2c_adapter *adap,struct i2c_msg *msgs, int num);
|
||||
/* --- ioctl like call to set div. parameters. */
|
||||
int (*algo_control)(struct i2c_adapter *, unsigned int, unsigned long);
|
||||
};
|
||||
|
||||
/*
|
||||
* i2c_adapter is the structure used to identify a physical i2c bus along
|
||||
* with the access algorithms necessary to access it.
|
||||
*/
|
||||
struct i2c_adapter
|
||||
{
|
||||
struct i2c_algorithm *algo; /* the algorithm to access the bus */
|
||||
void *algo_data;
|
||||
int timeout;
|
||||
int retries;
|
||||
int nr;
|
||||
};
|
||||
|
||||
/*
|
||||
* I2C Message - used for pure i2c transaction, also from /dev interface
|
||||
*/
|
||||
struct i2c_msg
|
||||
{
|
||||
unsigned short addr; /* slave address */
|
||||
unsigned short flags;
|
||||
#define I2C_M_TEN 0x10 /* we have a ten bit chip address */
|
||||
#define I2C_M_RD 0x01
|
||||
#define I2C_M_NOSTART 0x4000
|
||||
#define I2C_M_REV_DIR_ADDR 0x2000
|
||||
#define I2C_M_IGNORE_NAK 0x1000
|
||||
#define I2C_M_NO_RD_ACK 0x0800
|
||||
unsigned short len; /* msg length */
|
||||
unsigned char *buf; /* pointer to msg data */
|
||||
};
|
||||
|
||||
/*
|
||||
extern void i2c_init(void);
|
||||
extern void i2c_set_frequency(int hz);
|
||||
extern int i2c_read(int address, char *data, int lengt, bool repeated);
|
||||
extern int i2c_read_byte(int ack);
|
||||
extern int i2c_write(int address, const char *data, int length, bool repeated);
|
||||
extern int i2c_write_byte(int data);
|
||||
extern void i2c_start(void);
|
||||
extern void i2c_stop(void);
|
||||
*/
|
||||
#endif /* _I2C_H */
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user