Firebee/BaS_gcc
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added more diagnostics

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This commit is contained in:
Markus Fröschle
2013-11-11 21:14:37 +00:00
parent b2677b5c8e
commit bd4f85b07d
5 changed files with 136 additions and 11 deletions
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7
.gdbinit
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@@ -1,8 +1,9 @@
#set disassemble-next-line on
define tr
target remote | m68k-bdm-gdbserver pipe /dev/bdmcf3
#target remote | m68k-bdm-gdbserver pipe /dev/tblcf3
monitor bdm-reset
#target remote | m68k-bdm-gdbserver pipe /dev/bdmcf3
target remote | m68k-bdm-gdbserver pipe /dev/tblcf3
#target dbug /dev/ttyS0
#monitor bdm-reset
end
define tbtr
target remote | m68k-bdm-gdbserver pipe /dev/tblcf3

1
bas_firebee.bdm
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@@ -69,3 +69,4 @@ dump-register SR
dump-register CACR
dump-register MBAR
execute
wait

27
include/pci.h
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@@ -77,6 +77,33 @@
#define PVPDAD 0x4E /* PCI Vital Product Data Address */
#define PVPDATA 0x50 /* PCI VPD Data */
/*
* bit definitions for PCICSR lower half (Command Register)
*/
#define PCICSR_IO (1 << 0) /* if set: device responds to I/O space accesses */
#define PCICSR_MEMORY (1 << 1) /* if set: device responds to memory space accesses */
#define PCICSR_MASTER (1 << 2) /* if set: device is master */
#define PCICSR_SPECIAL (1 << 3) /* if set: device reacts on special cycles */
#define PCICSR_MEMWI (1 << 4) /* if set: device deals with memory write and invalidate */
#define PCICSR_VGA_SNOOP (1 << 5) /* if set: capable of palette snoop */
#define PCICSR_PERR (1 << 6) /* if set: reacts to parity errors */
#define PCICSR_STEPPING (1 << 7) /* if set: stepping enabled */
#define PCICSR_SERR (1 << 8) /* if set: SERR pin enabled */
#define PCICSR_FAST_BTOB_E (1 << 9) /* if set: fast back-to-back enabled */
/*
* bit definitions for PCICSR upper half (Status Register)
*/
#define PCICSR_66MHZ (1 << 5) /* 66 MHz capable */
#define PCICSR_UDF (1 << 6) /* UDF supported */
#define PCICSR_FAST_BTOB (1 << 7) /* Fast back-to-back enabled */
#define PCICSR_DPARITY_ERROR (1 << 8) /* data parity error detected */
#define PCICSR_T_ABORT_S (1 << 11) /* target abort signaled */
#define PCICSR_T_ABORT_R (1 << 12) /* target abort received */
#define PCICSR_M_ABORT_R (1 << 13) /* master abort received */
#define PCICSR_S_ERROR_S (1 << 14) /* system error signaled */
#define PCICSR_PARITY_ERR (1 << 15) /* data parity error */
/* Header type 1 (PCI-to-PCI bridges) */
#define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
#define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */

10
mcf5474.gdb
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@@ -4,16 +4,16 @@
define addresses
set $vbr = 0x00000000
monitor bdm-ctl-set 0x0801 0x00000000
#monitor bdm-ctl-set 0x0801 0x00000000
set $mbar = 0xFF000000
monitor bdm-ctl-set 0x0C0F 0xFF000000
#monitor bdm-ctl-set 0x0C0F 0xFF000000
set $rambar0 = 0xFF100000
monitor bdm-ctl-set 0x0C04 0xFF100007
#monitor bdm-ctl-set 0x0C04 0xFF100007
set $rambar1 = 0xFF101000
monitor bdm-ctl-set 0x0C05 0xFF101001
#monitor bdm-ctl-set 0x0C05 0xFF101001
end
#
@@ -61,6 +61,6 @@ define ib
setup-dram
end
tr
ib
tr
load

102
sources/pci.c
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@@ -174,7 +174,7 @@ uint32_t pci_read_config_longword(int32_t handle, int offset)
value = * (volatile uint32_t *) PCI_IO_OFFSET; /* access device */
/* finish PCI configuration access special cycle (allow regular PCI accesses) */
//MCF_PCI_PCICAR &= ~MCF_PCI_PCICAR_E;
MCF_PCI_PCICAR &= ~MCF_PCI_PCICAR_E;
pci_config_wait();
@@ -223,12 +223,102 @@ int32_t pci_write_config_longword(int32_t handle, int offset, uint32_t value)
pci_config_wait();
/* finish configuration space access cycle */
//MCF_PCI_PCICAR &= ~MCF_PCI_PCICAR_E;
MCF_PCI_PCICAR &= ~MCF_PCI_PCICAR_E;
pci_config_wait();
return PCI_SUCCESSFUL;
}
/*
* write a 16-bit value to config space. Must be in little-endian format
*/
int32_t pci_write_config_word(int32_t handle, int offset, uint16_t value)
{
uint16_t bus = PCI_BUS_FROM_HANDLE(handle);
uint16_t device = PCI_DEVICE_FROM_HANDLE(handle);
uint16_t function = PCI_FUNCTION_FROM_HANDLE(handle);
/* initiate PCI configuration access to device */
MCF_PCI_PCICAR = MCF_PCI_PCICAR_E | /* enable configuration access special cycle */
MCF_PCI_PCICAR_BUSNUM(bus) |
MCF_PCI_PCICAR_DEVNUM(device) |
MCF_PCI_PCICAR_FUNCNUM(function) |
MCF_PCI_PCICAR_DWORD(offset / 4);
pci_config_wait();
* (volatile uint16_t *) (PCI_IO_OFFSET + offset % 2) = value;
pci_config_wait();
/* finish configuration space access cycle */
MCF_PCI_PCICAR &= ~MCF_PCI_PCICAR_E;
return PCI_SUCCESSFUL;
}
/*
* write a single byte to config space
*/
int32_t pci_write_config_byte(int32_t handle, int offset, uint8_t value)
{
MCF_PCI_PCICAR = MCF_PCI_PCICAR_E |
MCF_PCI_PCICAR_BUSNUM(PCI_BUS_FROM_HANDLE(handle)) |
MCF_PCI_PCICAR_DEVNUM(PCI_DEVICE_FROM_HANDLE(handle)) |
MCF_PCI_PCICAR_FUNCNUM(PCI_FUNCTION_FROM_HANDLE(handle)) |
MCF_PCI_PCICAR_DWORD(offset / 4);
pci_config_wait();
* (volatile uint8_t *) (PCI_IO_OFFSET + offset % 4) = value;
pci_config_wait();
/* finish configuration space access cycle */
MCF_PCI_PCICAR &= ~MCF_PCI_PCICAR_E;
return PCI_SUCCESSFUL;
}
void pci_print_device_abilities(int32_t handle)
{
uint16_t value;
uint16_t saved_value;
saved_value = pci_read_config_word(handle, PCICSR);
pci_write_config_word(handle, PCICSR, 0xffff);
value = swpw(pci_read_config_word(handle, PCICSR));
xprintf("IO: %1d MEM: %1d MSTR:%1d SPCC: %1d MEMW: %1d VGAS: %1d PERR: %1d STEP: %1d SERR: %1d FBTB: %1d\r\n",
value & PCICSR_IO ? 1 : 0,
value & PCICSR_MEMORY ? 1 : 0,
value & PCICSR_MASTER ? 1 : 0,
value & PCICSR_SPECIAL ? 1 : 0,
value & PCICSR_MEMWI ? 1 : 0,
value & PCICSR_VGA_SNOOP ? 1 : 0,
value & PCICSR_PERR ? 1 : 0,
value & PCICSR_STEPPING ? 1 : 0,
value & PCICSR_SERR ? 1 : 0,
value & PCICSR_FAST_BTOB_E ? 1 : 0);
pci_write_config_word(handle, PCICSR, saved_value);
}
void pci_print_device_config(int32_t handle)
{
uint16_t value;
value = swpw(pci_read_config_word(handle, PCICSR + 2));
xprintf("66M: %1d UDF: %1d FB2B:%1d PERR: %1d TABR: %1d DABR: %1d SERR: %1d PPER: %1d\r\n",
value & PCICSR_66MHZ ? 1 : 0,
value & PCICSR_UDF ? 1 : 0,
value & PCICSR_FAST_BTOB ? 1 : 0,
value & PCICSR_DPARITY_ERROR ? 1 : 0,
value & PCICSR_T_ABORT_S ? 1 : 0,
value & PCICSR_T_ABORT_R ? 1 : 0,
value & PCICSR_M_ABORT_R ? 1 : 0,
value & PCICSR_S_ERROR_S ? 1 : 0,
value & PCICSR_PARITY_ERR ? 1 : 0);
}
/*
* pci_get_resource
*
@@ -465,7 +555,11 @@ static void pci_device_config(uint16_t bus, uint16_t device, uint16_t function)
/*
* enable device memory or I/O access
*/
pci_write_config_longword(handle, PCICSR, swpw(command_register));
xprintf("PCICSR of card 0x%02x = 0x%04x\r\n", handle, swpw(pci_read_config_word(handle, PCICSR)));
pci_write_config_byte(handle, PCICSR, (uint8_t) command_register);
xprintf("PCICSR of card 0x%02x = 0x%04x\r\n", handle, swpw(pci_read_config_word(handle, PCICSR)));
pci_print_device_abilities(handle);
pci_print_device_config(handle);
}
static void pci_bridge_config(uint16_t bus, uint16_t device, uint16_t function)
@@ -478,6 +572,8 @@ static void pci_bridge_config(uint16_t bus, uint16_t device, uint16_t function)
return;
}
handle = PCI_HANDLE(bus, device, function);
pci_print_device_abilities(handle);
pci_print_device_config(handle);
pci_write_config_longword(handle, PCIBAR0, 0x40000000);
pci_write_config_longword(handle, PCIBAR1, 0x0);
pci_write_config_longword(handle, PCICSR, 0x146);