Moved source_fa into trunk

FireBee/trunk/usb/store/host/aranym/aranym-hcd.c

@@ -0,0 +1,150 @@
+/*
+	NatFeat USB host chip emulator
+
+	ARAnyM (C) 2010 David Gálvez
+
+	This program is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	This program is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with this program; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+/*--- Include ---*/
+
+#include <stdlib.h>
+#include <string.h>
+
+#include <mint/cookie.h>
+#include <mint/osbind.h>
+
+#include "nf_ops.h"
+#include "usbhost_nfapi.h"
+#include "../../config.h"
+#include "../../asm-m68k/io.h"
+#include "../../usb.h"
+#include "../../debug.h"
+
+/*--- Defines ---*/
+
+#ifndef EINVFN
+#define EINVFN	-32
+#endif
+
+#ifndef DEV_CONSOLE
+#define DEV_CONSOLE	2
+#endif
+
+#define DRIVER_NAME	"ARAnyM USB host chip emulator"
+#define VERSION	"v0.1"
+
+
+/*--- Functions prototypes ---*/
+
+static void press_any_key(void);
+
+
+/*--- Local variables ---*/
+
+static struct nf_ops *nfOps;
+static unsigned long nfUsbHostId;
+
+
+/*--- Functions ---*/
+
+
+static void press_any_key(void)
+{
+
+	(void) Cconws("- Press any key to continue -\r\n");
+	while (Bconstat(DEV_CONSOLE) == 0) { };
+}
+
+
+/* --- Transfer functions -------------------------------------------------- */
+
+int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+		   int len, int interval)
+{
+	int r;
+
+	r = nfOps->call(USBHOST(USBHOST_SUBMIT_INT_MSG), dev, pipe, buffer, len, interval);
+
+	return 0;
+}
+
+int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+		       int len, struct devrequest *setup)
+{
+	int r;
+
+	r = nfOps->call(USBHOST(USBHOST_SUBMIT_CONTROL_MSG), dev, pipe, buffer, len, setup);
+
+	return r;
+}
+
+int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+		    int len)
+{
+	int r;
+
+	r = nfOps->call(USBHOST(USBHOST_SUBMIT_BULK_MSG), dev, pipe, buffer, len);
+
+	return 0;
+}
+
+/* --- Init functions ------------------------------------------------------ */
+
+int usb_lowlevel_init(void)
+{
+	int r;
+
+	(void) Cconws(
+		"\033p " DRIVER_NAME " " VERSION " \033q\r\n"
+		"Copyright (c) ARAnyM Development Team, " __DATE__ "\r\n"
+	);
+
+	nfOps = nf_init();
+	if (!nfOps) {
+		(void) Cconws("__NF cookie not present on this system\r\n");
+		press_any_key();
+		return 0;
+	}
+	
+	nfUsbHostId=nfOps->get_id("USBHOST");
+	if (nfUsbHostId == 0) {
+		(void) Cconws("NF USBHOST functions not present on this system\r\n");
+		press_any_key();
+	}
+
+	/* List present devices */
+
+	r = nfOps->call(USBHOST(USBHOST_LOWLEVEL_INIT));
+
+	if (!r) 
+		(void) Cconws(" USB Init \r\n");
+	else
+		(void) Cconws(" Couldn't init aranym host chip emulator \r\n");
+
+	return 0;
+
+}
+
+int usb_lowlevel_stop(void)
+{
+	int r;
+
+	r = nfOps->call(USBHOST(USBHOST_LOWLEVEL_STOP));
+
+	return 0;
+
+}
+

FireBee/trunk/usb/store/host/aranym/natfeat.c

@@ -0,0 +1,118 @@
+/*
+ * ARAnyM native features interface.
+ * (c) 2005-2008 ARAnyM development team
+ *
+ * In 2006 updated with FreeMiNT headers and code.
+ * In 2008 converted from "__NF" cookie to direct usage of NF instructions
+ *
+ **/
+
+/*
+ * Copied from FreeMiNT source tree where Native Features were added recently
+ * 
+ * Copyright 2003 Frank Naumann <fnaumann@freemint.de>
+ * All rights reserved.
+ * 
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ * 
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ * 
+ * 
+ * Author: Frank Naumann <fnaumann@freemint.de>
+ * Started: 2003-12-13
+ * 
+ */
+
+# include <compiler.h>
+# include <mint/osbind.h>
+# include "nf_ops.h"
+
+
+#define ARANYM 1
+# ifdef ARANYM
+
+
+static unsigned long nf_get_id_instr = 0x73004e75UL;
+static unsigned long nf_call_instr = 0x73014e75UL;
+
+static struct nf_ops _nf_ops = { (void*)&nf_get_id_instr, (void*)&nf_call_instr }; 
+static struct nf_ops *nf_ops = 0UL; 
+
+extern int detect_native_features(void);
+
+struct nf_ops *
+nf_init(void)
+{
+	if (Supexec(detect_native_features))
+	{
+		nf_ops = &_nf_ops;
+		return nf_ops;
+	}
+	
+	return 0UL;
+}
+
+
+const char *
+nf_name(void)
+{
+	static char buf[64] = "Unknown emulator";
+	
+	if (nf_ops)
+	{
+		static int done = 0;
+		
+		if (!done)
+		{
+			long nfid_name = nf_ops->get_id("NF_NAME");
+			
+			if (nfid_name)
+				nf_ops->call(nfid_name, buf, sizeof(buf));
+			
+			done = 1;
+		}
+	}
+        
+	return buf;
+}
+
+int
+nf_debug(const char *msg)
+{
+	if (nf_ops)
+	{
+		long nfid_stderr = nf_ops->get_id("NF_STDERR");
+		
+		if (nfid_stderr)
+		{
+			nf_ops->call(nfid_stderr, msg);
+			return 1;
+		}
+	}
+	
+	return 0;
+}
+
+void
+nf_shutdown(void)
+{
+	if (nf_ops)
+	{
+		long shutdown_id = nf_ops->get_id("NF_SHUTDOWN");
+		
+		if (shutdown_id)
+        		nf_ops->call(shutdown_id);
+	}
+}
+
+# endif

FireBee/trunk/usb/store/host/aranym/natfeat_asm.S

@@ -0,0 +1,76 @@
+/*
+ * ARAnyM native features interface.
+ * (c) 2005-2008 ARAnyM development team
+ *
+ * In 2006 updated with FreeMiNT headers and code.
+ * In 2008 converted from "__NF" cookie to direct usage of NF instructions
+ *
+ **/
+
+/*
+ * Copied from FreeMiNT source tree where Native Features were added recently
+ *
+ * Copyright 2003 Frank Naumann <fnaumann@freemint.de>
+ * All rights reserved.
+ * 
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ * 
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ * 
+ * 
+ * Author: Frank Naumann <fnaumann@freemint.de>
+ * Started: 2003-12-13
+ * 
+ * please send suggestions, patches or bug reports to me or
+ * the MiNT mailing list
+ * 
+ */
+
+#define ARANYM 1
+# ifdef ARANYM
+
+	.text
+
+	.globl	_detect_native_features
+
+/* 
+ * NatFeats test (routine retuns TRUE/FALSE (1/0) in D0)
+ */
+_detect_native_features:
+
+	clr.l	d0			// assume no NatFeats available
+	move.l	sp,a1			// save the ssp
+	move.l	(0x0010).w,a0		// illegal instruction vector
+	move.l	#fail_natfeat,(0x0010).w
+
+	nop				// flush pipelines (for 68040+)
+
+	pea	(nf_version_name).w(pc)
+	subq.l	#4,sp
+	dc.w	0x7300			// Jump to NATFEAT_ID
+	tst.l	d0
+	beq.s	fail_natfeat
+	moveq	#1,d0			// NatFeats detected
+
+fail_natfeat:
+	move.l	a1,sp
+	move.l	a0,(0x0010).w
+
+	nop				// flush pipelines (for 68040+)
+
+	rts
+
+nf_version_name:
+	.ascii	"NF_VERSION\0"
+
+# endif

FireBee/trunk/usb/store/host/aranym/nf_ops.h

@@ -0,0 +1,63 @@
+/*
+ * $Id: nf_ops.h,v 1.2 2006-01-31 16:21:22 standa Exp $
+ * 
+ * ARAnyM Native Features suite.
+ *
+ * This file was taken from FreeMiNT.
+ * 
+ * Copyright 2003 Frank Naumann <fnaumann@freemint.de>
+ * All rights reserved.
+ * 
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ * 
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ * 
+ * 
+ * Author: Frank Naumann <fnaumann@freemint.de>
+ * Started: 2003-12-14
+ * 
+ * Please send suggestions, patches or bug reports to me or
+ * the MiNT mailing list.
+ * 
+ */
+
+# ifndef _m68k_nf_ops_h
+# define _m68k_nf_ops_h
+
+#include <compiler.h>	/* for __CDECL */
+
+
+struct nf_ops
+{
+	long __CDECL (*get_id)(const char *);
+	long __CDECL (*call)(long id, ...);
+	long res[3];
+};
+
+
+/**
+ * Use this function to intialize Native Features.
+ *
+ * @return the pointer to 'struct nf_ops' or NULL when
+ *         not available.
+ **/
+struct nf_ops *nf_init(void);
+
+
+/* basic set native feature functions */
+const char *nf_name(void);
+int  nf_debug(const char *msg);
+void nf_shutdown(void);
+
+
+# endif /* _m68k_nf_ops_h */

FireBee/trunk/usb/store/host/aranym/usbhost_nfapi.h

@@ -0,0 +1,40 @@
+/*
+	NatFeat USB Host chip emulator
+
+	ARAnyM (C) 2010 David Gálvez
+
+	This program is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	This program is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with this program; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+*/
+
+#ifndef _USBHOST_NFAPI_H
+#define _USBHOST_NFAPI_H
+
+/* if you change anything in the enum {} below you have to increase 
+   this ARAUSBHOST_NFAPI_VERSION!
+*/
+#define ARAUSBHOST_NFAPI_VERSION	0x00000000
+
+enum {
+	GET_VERSION = 0,	/* no parameters, return NFAPI_VERSION in d0 */
+	USBHOST_LOWLEVEL_INIT,
+	USBHOST_LOWLEVEL_STOP,
+	USBHOST_SUBMIT_CONTROL_MSG,
+	USBHOST_SUBMIT_INT_MSG,
+	USBHOST_SUBMIT_BULK_MSG
+};
+
+#define USBHOST(a)	(nfUsbHostId + a)
+
+#endif /* _USBHOST_NFAPI_H */

FireBee/trunk/usb/store/host/ethernat/isp116x.h

@@ -0,0 +1,542 @@
+/*
+ * Modified for Atari-EtherNat by David Gálvez 2010
+ *
+ * ISP116x register declarations and HCD data structures
+ *
+ * Copyright (C) 2007 Rodolfo Giometti <giometti@linux.it>
+ * Copyright (C) 2007 Eurotech S.p.A. <info@eurotech.it>
+ * Copyright (C) 2005 Olav Kongas <ok@artecdesign.ee>
+ * Portions:
+ * Copyright (C) 2004 Lothar Wassmann
+ * Copyright (C) 2004 Psion Teklogix
+ * Copyright (C) 2004 David Brownell
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ETHERNAT_ISP116X_H
+#define _ETHERNAT_ISP116X_H
+
+
+#define ERR(fmt, args...)	printf("isp116x: %s: " fmt "\n\r" , __FUNCTION__ , ## args)
+#define WARN(fmt, args...)	printf("isp116x: %s: " fmt "\n\r" , __FUNCTION__ , ## args)
+#define INFO(fmt, args...)	printf("isp116x: " fmt "\n\r" , ## args)
+
+/* ------------------------------------------------------------------------- */
+
+/* us of 1ms frame */
+#define  MAX_LOAD_LIMIT		850
+
+/* Full speed: max # of bytes to transfer for a single urb
+   at a time must be < 1024 && must be multiple of 64.
+   832 allows transfering 4kiB within 5 frames. */
+#define MAX_TRANSFER_SIZE_FULLSPEED	832
+
+/* Low speed: there is no reason to schedule in very big
+   chunks; often the requested long transfers are for
+   string descriptors containing short strings. */
+#define MAX_TRANSFER_SIZE_LOWSPEED	64
+
+/* Bytetime (us), a rough indication of how much time it
+   would take to transfer a byte of useful data over USB */
+#define BYTE_TIME_FULLSPEED	1
+#define BYTE_TIME_LOWSPEED	20
+
+/* Buffer sizes */
+#define ISP116x_BUF_SIZE	4096
+#define ISP116x_ITL_BUFSIZE	0
+#define ISP116x_ATL_BUFSIZE	((ISP116x_BUF_SIZE) - 2*(ISP116x_ITL_BUFSIZE))
+
+#define ISP116x_WRITE_OFFSET	0x80
+
+/* --- ISP116x address registers in EtherNAT --------------------------------*/
+
+#define ISP116X_HCD_ADDR	0x80000016
+#define ISP116X_HCD_DATA	0x80000012
+#define ETHERNAT_CPLD_CR	0x80000023   /* 0x80000023 - 1 */
+
+/* --- ISP116x registers/bits ---------------------------------------------- */
+
+#define	HCREVISION	0x00
+#define	HCCONTROL	0x01
+#define		HCCONTROL_HCFS	(3 << 6)	/* host controller
+						   functional state */
+#define		HCCONTROL_USB_RESET	(0 << 6)
+#define		HCCONTROL_USB_RESUME	(1 << 6)
+#define		HCCONTROL_USB_OPER	(2 << 6)
+#define		HCCONTROL_USB_SUSPEND	(3 << 6)
+#define		HCCONTROL_RWC	(1 << 9)	/* remote wakeup connected */
+#define		HCCONTROL_RWE	(1 << 10)	/* remote wakeup enable */
+#define	HCCMDSTAT	0x02
+#define		HCCMDSTAT_HCR	(1 << 0)	/* host controller reset */
+#define		HCCMDSTAT_SOC	(3 << 16)	/* scheduling overrun count */
+#define	HCINTSTAT	0x03
+#define		HCINT_SO	(1 << 0)	/* scheduling overrun */
+#define		HCINT_WDH	(1 << 1)	/* writeback of done_head */
+#define		HCINT_SF	(1 << 2)	/* start frame */
+#define		HCINT_RD	(1 << 3)	/* resume detect */
+#define		HCINT_UE	(1 << 4)	/* unrecoverable error */
+#define		HCINT_FNO	(1 << 5)	/* frame number overflow */
+#define		HCINT_RHSC	(1 << 6)	/* root hub status change */
+#define		HCINT_OC	(1 << 30)	/* ownership change */
+#define		HCINT_MIE	(1 << 31)	/* master interrupt enable */
+#define	HCINTENB	0x04
+#define	HCINTDIS	0x05
+#define	HCFMINTVL	0x0d
+#define	HCFMREM		0x0e
+#define	HCFMNUM		0x0f
+#define	HCLSTHRESH	0x11
+#define	HCRHDESCA	0x12
+#define		RH_A_NDP	(0x3 << 0)	/* # downstream ports */
+#define		RH_A_PSM	(1 << 8)	/* power switching mode */
+#define		RH_A_NPS	(1 << 9)	/* no power switching */
+#define		RH_A_DT		(1 << 10)	/* device type (mbz) */
+#define		RH_A_OCPM	(1 << 11)	/* overcurrent protection
+						   mode */
+#define		RH_A_NOCP	(1 << 12)	/* no overcurrent protection */
+#define		RH_A_POTPGT	(0xff << 24)	/* power on -> power good
+						   time */
+#define	HCRHDESCB	0x13
+#define		RH_B_DR		(0xffff << 0)	/* device removable flags */
+#define		RH_B_PPCM	(0xffff << 16)	/* port power control mask */
+#define	HCRHSTATUS	0x14
+#define		RH_HS_LPS	(1 << 0)	/* local power status */
+#define		RH_HS_OCI	(1 << 1)	/* over current indicator */
+#define		RH_HS_DRWE	(1 << 15)	/* device remote wakeup
+						   enable */
+#define		RH_HS_LPSC	(1 << 16)	/* local power status change */
+#define		RH_HS_OCIC	(1 << 17)	/* over current indicator
+						   change */
+#define		RH_HS_CRWE	(1 << 31)	/* clear remote wakeup
+						   enable */
+#define	HCRHPORT1	0x15
+#define		RH_PS_CCS	(1 << 0)	/* current connect status */
+#define		RH_PS_PES	(1 << 1)	/* port enable status */
+#define		RH_PS_PSS	(1 << 2)	/* port suspend status */
+#define		RH_PS_POCI	(1 << 3)	/* port over current
+						   indicator */
+#define		RH_PS_PRS	(1 << 4)	/* port reset status */
+#define		RH_PS_PPS	(1 << 8)	/* port power status */
+#define		RH_PS_LSDA	(1 << 9)	/* low speed device attached */
+#define		RH_PS_CSC	(1 << 16)	/* connect status change */
+#define		RH_PS_PESC	(1 << 17)	/* port enable status change */
+#define		RH_PS_PSSC	(1 << 18)	/* port suspend status
+						   change */
+#define		RH_PS_OCIC	(1 << 19)	/* over current indicator
+						   change */
+#define		RH_PS_PRSC	(1 << 20)	/* port reset status change */
+#define		HCRHPORT_CLRMASK	(0x1f << 16)
+#define	HCRHPORT2	0x16
+#define	HCHWCFG		0x20
+#define		HCHWCFG_15KRSEL		(1 << 12)
+#define		HCHWCFG_CLKNOTSTOP	(1 << 11)
+#define		HCHWCFG_ANALOG_OC	(1 << 10)
+#define		HCHWCFG_DACK_MODE	(1 << 8)
+#define		HCHWCFG_EOT_POL		(1 << 7)
+#define		HCHWCFG_DACK_POL	(1 << 6)
+#define		HCHWCFG_DREQ_POL	(1 << 5)
+#define		HCHWCFG_DBWIDTH_MASK	(0x03 << 3)
+#define		HCHWCFG_DBWIDTH(n)	(((n) << 3) & HCHWCFG_DBWIDTH_MASK)
+#define		HCHWCFG_INT_POL		(1 << 2)
+#define		HCHWCFG_INT_TRIGGER	(1 << 1)
+#define		HCHWCFG_INT_ENABLE	(1 << 0)
+#define	HCDMACFG	0x21
+#define		HCDMACFG_BURST_LEN_MASK	(0x03 << 5)
+#define		HCDMACFG_BURST_LEN(n)	(((n) << 5) & HCDMACFG_BURST_LEN_MASK)
+#define		HCDMACFG_BURST_LEN_1	HCDMACFG_BURST_LEN(0)
+#define		HCDMACFG_BURST_LEN_4	HCDMACFG_BURST_LEN(1)
+#define		HCDMACFG_BURST_LEN_8	HCDMACFG_BURST_LEN(2)
+#define		HCDMACFG_DMA_ENABLE	(1 << 4)
+#define		HCDMACFG_BUF_TYPE_MASK	(0x07 << 1)
+#define		HCDMACFG_CTR_SEL	(1 << 2)
+#define		HCDMACFG_ITLATL_SEL	(1 << 1)
+#define		HCDMACFG_DMA_RW_SELECT	(1 << 0)
+#define	HCXFERCTR	0x22
+#define	HCuPINT		0x24
+#define		HCuPINT_SOF		(1 << 0)
+#define		HCuPINT_ATL		(1 << 1)
+#define		HCuPINT_AIIEOT		(1 << 2)
+#define		HCuPINT_OPR		(1 << 4)
+#define		HCuPINT_SUSP		(1 << 5)
+#define		HCuPINT_CLKRDY		(1 << 6)
+#define	HCuPINTENB	0x25
+#define	HCCHIPID	0x27
+#define		HCCHIPID_MASK		0xff00
+#define		HCCHIPID_MAGIC		0x6100
+#define	HCSCRATCH	0x28
+#define	HCSWRES		0x29
+#define		HCSWRES_MAGIC		0x00f6
+#define	HCITLBUFLEN	0x2a
+#define	HCATLBUFLEN	0x2b
+#define	HCBUFSTAT	0x2c
+#define		HCBUFSTAT_ITL0_FULL	(1 << 0)
+#define		HCBUFSTAT_ITL1_FULL	(1 << 1)
+#define		HCBUFSTAT_ATL_FULL	(1 << 2)
+#define		HCBUFSTAT_ITL0_DONE	(1 << 3)
+#define		HCBUFSTAT_ITL1_DONE	(1 << 4)
+#define		HCBUFSTAT_ATL_DONE	(1 << 5)
+#define	HCRDITL0LEN	0x2d
+#define	HCRDITL1LEN	0x2e
+#define	HCITLPORT	0x40
+#define	HCATLPORT	0x41
+
+/* PTD accessor macros. */
+#define PTD_GET_COUNT(p)	(((p)->count & PTD_COUNT_MSK) >> 0)
+#define PTD_COUNT(v)		(((v) << 0) & PTD_COUNT_MSK)
+#define PTD_GET_TOGGLE(p)	(((p)->count & PTD_TOGGLE_MSK) >> 10)
+#define PTD_TOGGLE(v)		(((v) << 10) & PTD_TOGGLE_MSK)
+#define PTD_GET_ACTIVE(p)	(((p)->count & PTD_ACTIVE_MSK) >> 11)
+#define PTD_ACTIVE(v)		(((v) << 11) & PTD_ACTIVE_MSK)
+#define PTD_GET_CC(p)		(((p)->count & PTD_CC_MSK) >> 12)
+#define PTD_CC(v)		(((v) << 12) & PTD_CC_MSK)
+#define PTD_GET_MPS(p)		(((p)->mps & PTD_MPS_MSK) >> 0)
+#define PTD_MPS(v)		(((v) << 0) & PTD_MPS_MSK)
+#define PTD_GET_SPD(p)		(((p)->mps & PTD_SPD_MSK) >> 10)
+#define PTD_SPD(v)		(((v) << 10) & PTD_SPD_MSK)
+#define PTD_GET_LAST(p)		(((p)->mps & PTD_LAST_MSK) >> 11)
+#define PTD_LAST(v)		(((v) << 11) & PTD_LAST_MSK)
+#define PTD_GET_EP(p)		(((p)->mps & PTD_EP_MSK) >> 12)
+#define PTD_EP(v)		(((v) << 12) & PTD_EP_MSK)
+#define PTD_GET_LEN(p)		(((p)->len & PTD_LEN_MSK) >> 0)
+#define PTD_LEN(v)		(((v) << 0) & PTD_LEN_MSK)
+#define PTD_GET_DIR(p)		(((p)->len & PTD_DIR_MSK) >> 10)
+#define PTD_DIR(v)		(((v) << 10) & PTD_DIR_MSK)
+#define PTD_GET_B5_5(p)		(((p)->len & PTD_B5_5_MSK) >> 13)
+#define PTD_B5_5(v)		(((v) << 13) & PTD_B5_5_MSK)
+#define PTD_GET_FA(p)		(((p)->faddr & PTD_FA_MSK) >> 0)
+#define PTD_FA(v)		(((v) << 0) & PTD_FA_MSK)
+#define PTD_GET_FMT(p)		(((p)->faddr & PTD_FMT_MSK) >> 7)
+#define PTD_FMT(v)		(((v) << 7) & PTD_FMT_MSK)
+
+/*  Hardware transfer status codes -- CC from ptd->count */
+#define TD_CC_NOERROR      0x00
+#define TD_CC_CRC          0x01
+#define TD_CC_BITSTUFFING  0x02
+#define TD_CC_DATATOGGLEM  0x03
+#define TD_CC_STALL        0x04
+#define TD_DEVNOTRESP      0x05
+#define TD_PIDCHECKFAIL    0x06
+#define TD_UNEXPECTEDPID   0x07
+#define TD_DATAOVERRUN     0x08
+#define TD_DATAUNDERRUN    0x09
+    /* 0x0A, 0x0B reserved for hardware */
+#define TD_BUFFEROVERRUN   0x0C
+#define TD_BUFFERUNDERRUN  0x0D
+    /* 0x0E, 0x0F reserved for HCD */
+#define TD_NOTACCESSED     0x0F
+
+/* ------------------------------------------------------------------------- */
+
+#define	LOG2_PERIODIC_SIZE	5	/* arbitrary; this matches OHCI */
+#define	PERIODIC_SIZE		(1 << LOG2_PERIODIC_SIZE)
+
+/* Philips transfer descriptor */
+struct ptd {
+	u16 count;
+#define	PTD_COUNT_MSK	(0x3ff << 0)
+#define	PTD_TOGGLE_MSK	(1 << 10)
+#define	PTD_ACTIVE_MSK	(1 << 11)
+#define	PTD_CC_MSK	(0xf << 12)
+	u16 mps;
+#define	PTD_MPS_MSK	(0x3ff << 0)
+#define	PTD_SPD_MSK	(1 << 10)
+#define	PTD_LAST_MSK	(1 << 11)
+#define	PTD_EP_MSK	(0xf << 12)
+	u16 len;
+#define	PTD_LEN_MSK	(0x3ff << 0)
+#define	PTD_DIR_MSK	(3 << 10)
+#define	PTD_DIR_SETUP	(0)
+#define	PTD_DIR_OUT	(1)
+#define	PTD_DIR_IN	(2)
+#define	PTD_B5_5_MSK	(1 << 13)
+	u16 faddr;
+#define	PTD_FA_MSK	(0x7f << 0)
+#define	PTD_FMT_MSK	(1 << 7)
+} __attribute__ ((packed, aligned(2)));
+
+struct isp116x_ep {
+	struct usb_device *udev;
+	struct ptd ptd;
+
+	u8 maxpacket;
+	u8 epnum;
+	u8 nextpid;
+
+	u16 length;		/* of current packet */
+	unsigned char *data;	/* to databuf */
+
+	u16 error_count;
+};
+
+/* URB struct */
+#define N_URB_TD		48
+#define URB_DEL			1
+typedef struct {
+	struct isp116x_ep *ed;
+	void *transfer_buffer;	/* (in) associated data buffer */
+	int actual_length;	/* (return) actual transfer length */
+	unsigned long pipe;	/* (in) pipe information */
+#if 0
+	int state;
+#endif
+} urb_priv_t;
+
+struct isp116x_platform_data {
+	/* Enable internal resistors on downstream ports */
+	unsigned sel15Kres:1;
+	/* On-chip overcurrent detection */
+	unsigned oc_enable:1;
+	/* Enable wakeup by devices on usb bus (e.g. wakeup
+	   by attachment/detachment or by device activity
+	   such as moving a mouse). When chosen, this option
+	   prevents stopping internal clock, increasing
+	   thereby power consumption in suspended state. */
+	unsigned remote_wakeup_enable:1;
+};
+
+struct isp116x {
+	u16 *addr_reg;
+	u16 *data_reg;
+
+	struct isp116x_platform_data *board;
+
+	struct dentry *dentry;
+	unsigned long stat1, stat2, stat4, stat8, stat16;
+
+	/* Status flags */
+	unsigned disabled:1;
+	unsigned sleeping:1;
+
+	/* Root hub registers */
+	u32 rhdesca;
+	u32 rhdescb;
+	u32 rhstatus;
+	u32 rhport[2];
+
+	/* Schedule for the current frame */
+	struct isp116x_ep *atl_active;
+	int atl_buflen;
+	int atl_bufshrt;
+	int atl_last_dir;
+	int atl_finishing;
+};
+
+/* ------------------------------------------------- */
+
+/* Inter-io delay (ns). The chip is picky about access timings; it
+ * expects at least:
+ * 150ns delay between consecutive accesses to DATA_REG,
+ * 300ns delay between access to ADDR_REG and DATA_REG
+ * OE, WE MUST NOT be changed during these intervals
+ */
+#if defined(UDELAY)
+#define	isp116x_delay(h,d)	udelay(d)
+#else
+#define	isp116x_delay(h,d)	do {} while (0)
+#endif
+
+#include "../../super.h"	/*
+	 		 * Functions to call supervisor mode
+		 	 * Super() in TOS is buggy
+			 */
+
+u32 p;	
+			 
+static inline void isp116x_write_addr(struct isp116x *isp116x, unsigned reg)
+{
+//	p = SuperFromUser( );
+	__raw_writew(reg & 0xff, isp116x->addr_reg );
+	isp116x_delay(isp116x, UDELAY);
+//	SuperToUser( p );
+}
+
+static inline void isp116x_write_data16(struct isp116x *isp116x, u16 val)
+{
+//	p = SuperFromUser( );
+	writew(val, isp116x->data_reg);
+	isp116x_delay(isp116x, UDELAY);
+//	SuperToUser( p );
+}
+
+static inline void isp116x_raw_write_data16(struct isp116x *isp116x, u16 val)
+{
+//	p = SuperFromUser( );
+	__raw_writew(val, isp116x->data_reg);
+	isp116x_delay(isp116x, UDELAY);
+//	SuperToUser( p );
+}
+
+static inline u16 isp116x_read_data16(struct isp116x *isp116x)
+{
+	u16 val;
+//	p = SuperFromUser( );
+	val = readw(isp116x->data_reg);
+	isp116x_delay(isp116x, UDELAY);
+//	SuperToUser( p );
+	return val;
+}
+
+static inline u16 isp116x_raw_read_data16(struct isp116x *isp116x)
+{
+	u16 val;
+//	p = SuperFromUser( );
+	val = __raw_readw(isp116x->data_reg);
+	isp116x_delay(isp116x, UDELAY);
+//	SuperToUser( p );
+	return val;
+}
+
+
+static inline void isp116x_write_data32(struct isp116x *isp116x, u32 val)
+{
+//	p = SuperFromUser( );
+	writew(val & 0xffff, isp116x->data_reg);
+	isp116x_delay(isp116x, UDELAY);
+	writew(val >> 16, isp116x->data_reg);
+	isp116x_delay(isp116x, UDELAY);
+//	SuperToUser( p );
+}
+
+/*
+ * Added for EtherNat, to write HC registers without swaping them
+ * EtherNat already swap them by hardware (i suppose.....)
+ */
+static inline void isp116x_raw_write_data32(struct isp116x *isp116x, u32 val)
+{
+//	p = SuperFromUser( );
+	__raw_writew(val & 0xffff, isp116x->data_reg);
+	isp116x_delay(isp116x, UDELAY);
+	__raw_writew(val >> 16, isp116x->data_reg);
+	isp116x_delay(isp116x, UDELAY);
+//	SuperToUser( p );
+}
+/***********************************************/
+
+static inline u32 isp116x_read_data32(struct isp116x *isp116x)
+{
+	u32 val;
+//	p = SuperFromUser( );
+	val = (u32) readw(isp116x->data_reg);
+	isp116x_delay(isp116x, UDELAY);
+	val |= ((u32) readw(isp116x->data_reg)) << 16;
+	isp116x_delay(isp116x, UDELAY);
+//	SuperToUser( p );
+	return val;
+}
+
+/*
+ * Added for EtherNat, to read HC registers without swaping them
+ * EtherNat already swap them by hardware (i suppose.....)
+ */
+static inline u32 isp116x_raw_read_data32(struct isp116x *isp116x)
+{
+	u32 val;
+//	p = SuperFromUser( );
+	val = (u32) __raw_readw(isp116x->data_reg);
+	isp116x_delay(isp116x, UDELAY);
+	val |= ((u32) __raw_readw(isp116x->data_reg)) << 16;
+	isp116x_delay(isp116x, UDELAY);
+//	SuperToUser( p );
+	return val;
+}
+/*******************************************************************/
+
+/* Let's keep register access functions out of line. Hint:
+   we wait at least 150 ns at every access.
+*/
+
+/* with EtherNat use raw_read to avoid swaping bytes*/
+
+static u16 isp116x_read_reg16(struct isp116x *isp116x, unsigned reg)
+{
+	isp116x_write_addr(isp116x, reg);
+	return isp116x_raw_read_data16(isp116x);
+}
+
+static u32 isp116x_read_reg32(struct isp116x *isp116x, unsigned reg)
+{
+	isp116x_write_addr(isp116x, reg);
+	return isp116x_raw_read_data32(isp116x);
+}
+
+static void isp116x_write_reg16(struct isp116x *isp116x, unsigned reg,
+				unsigned val)
+{
+	isp116x_write_addr(isp116x, reg | ISP116x_WRITE_OFFSET);
+	isp116x_raw_write_data16(isp116x, (u16) (val & 0xffff));
+}
+
+/* with Etehrnat used raw_write to avoid swaping bytes by software */
+static void isp116x_write_reg32(struct isp116x *isp116x, unsigned reg,
+				unsigned val)
+{
+	isp116x_write_addr(isp116x, reg | ISP116x_WRITE_OFFSET);
+	isp116x_raw_write_data32(isp116x, (u32) val);
+}
+
+/* --- USB HUB constants (not OHCI-specific; see hub.h) -------------------- */
+
+/* destination of request */
+#define RH_INTERFACE               0x01
+#define RH_ENDPOINT                0x02
+#define RH_OTHER                   0x03
+
+#define RH_CLASS                   0x20
+#define RH_VENDOR                  0x40
+
+/* Requests: bRequest << 8 | bmRequestType */
+#define RH_GET_STATUS           0x0080
+#define RH_CLEAR_FEATURE        0x0100
+#define RH_SET_FEATURE          0x0300
+#define RH_SET_ADDRESS          0x0500
+#define RH_GET_DESCRIPTOR       0x0680
+#define RH_SET_DESCRIPTOR       0x0700
+#define RH_GET_CONFIGURATION    0x0880
+#define RH_SET_CONFIGURATION    0x0900
+#define RH_GET_STATE            0x0280
+#define RH_GET_INTERFACE        0x0A80
+#define RH_SET_INTERFACE        0x0B00
+#define RH_SYNC_FRAME           0x0C80
+/* Our Vendor Specific Request */
+#define RH_SET_EP               0x2000
+
+/* Hub port features */
+#define RH_PORT_CONNECTION         0x00
+#define RH_PORT_ENABLE             0x01
+#define RH_PORT_SUSPEND            0x02
+#define RH_PORT_OVER_CURRENT       0x03
+#define RH_PORT_RESET              0x04
+#define RH_PORT_POWER              0x08
+#define RH_PORT_LOW_SPEED          0x09
+
+#define RH_C_PORT_CONNECTION       0x10
+#define RH_C_PORT_ENABLE           0x11
+#define RH_C_PORT_SUSPEND          0x12
+#define RH_C_PORT_OVER_CURRENT     0x13
+#define RH_C_PORT_RESET            0x14
+
+/* Hub features */
+#define RH_C_HUB_LOCAL_POWER       0x00
+#define RH_C_HUB_OVER_CURRENT      0x01
+
+#define RH_DEVICE_REMOTE_WAKEUP    0x00
+#define RH_ENDPOINT_STALL          0x01
+
+#define RH_ACK                     0x01
+#define RH_REQ_ERR                 -1
+#define RH_NACK                    0x00
+
+#endif /* _ETHERNAT_ISP116X_H */

FireBee/trunk/usb/store/host/netusbee/isp116x.h

@@ -0,0 +1,596 @@
+/*
+ * Modified for Atari-NetUSBee by David Gálvez 2010
+ *
+ * ISP116x register declarations and HCD data structures
+ *
+ * Copyright (C) 2007 Rodolfo Giometti <giometti@linux.it>
+ * Copyright (C) 2007 Eurotech S.p.A. <info@eurotech.it>
+ * Copyright (C) 2005 Olav Kongas <ok@artecdesign.ee>
+ * Portions:
+ * Copyright (C) 2004 Lothar Wassmann
+ * Copyright (C) 2004 Psion Teklogix
+ * Copyright (C) 2004 David Brownell
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _NETUSBEE_ISP116X_H
+#define _NETUSBEE_ISP116X_H
+
+
+#define ERR(fmt, args...)	printf("isp116x: %s: " fmt "\n\r" , __FUNCTION__ , ## args)
+#define WARN(fmt, args...)	printf("isp116x: %s: " fmt "\n\r" , __FUNCTION__ , ## args)
+#define INFO(fmt, args...)	printf("isp116x: " fmt "\n\r" , ## args)
+
+/* ------------------------------------------------------------------------- */
+
+/* us of 1ms frame */
+#define  MAX_LOAD_LIMIT		850
+
+/* Full speed: max # of bytes to transfer for a single urb
+   at a time must be < 1024 && must be multiple of 64.
+   832 allows transfering 4kiB within 5 frames. */
+#define MAX_TRANSFER_SIZE_FULLSPEED	832
+
+/* Low speed: there is no reason to schedule in very big
+   chunks; often the requested long transfers are for
+   string descriptors containing short strings. */
+#define MAX_TRANSFER_SIZE_LOWSPEED	64
+
+/* Bytetime (us), a rough indication of how much time it
+   would take to transfer a byte of useful data over USB */
+#define BYTE_TIME_FULLSPEED	1
+#define BYTE_TIME_LOWSPEED	20
+
+/* Buffer sizes */
+#define ISP116x_BUF_SIZE	4096
+#define ISP116x_ITL_BUFSIZE	0
+#define ISP116x_ATL_BUFSIZE	((ISP116x_BUF_SIZE) - 2*(ISP116x_ITL_BUFSIZE))
+
+#define ISP116x_WRITE_OFFSET	0x80
+
+
+/* --- ISP116x address registers in Netusbee --------------------------------*/
+
+#define ISP116X_HCD_ADDR_BEE	0x00FBC000
+#define ISP116X_HCD_DATA_BEE	0x00FA0000
+
+
+/* --- ISP116x registers/bits ---------------------------------------------- */
+
+#define	HCREVISION	0x00
+#define	HCCONTROL	0x01
+#define		HCCONTROL_HCFS	(3 << 6)	/* host controller
+						   functional state */
+#define		HCCONTROL_USB_RESET	(0 << 6)
+#define		HCCONTROL_USB_RESUME	(1 << 6)
+#define		HCCONTROL_USB_OPER	(2 << 6)
+#define		HCCONTROL_USB_SUSPEND	(3 << 6)
+#define		HCCONTROL_RWC	(1 << 9)	/* remote wakeup connected */
+#define		HCCONTROL_RWE	(1 << 10)	/* remote wakeup enable */
+#define	HCCMDSTAT	0x02
+#define		HCCMDSTAT_HCR	(1 << 0)	/* host controller reset */
+#define		HCCMDSTAT_SOC	(3 << 16)	/* scheduling overrun count */
+#define	HCINTSTAT	0x03
+#define		HCINT_SO	(1 << 0)	/* scheduling overrun */
+#define		HCINT_WDH	(1 << 1)	/* writeback of done_head */
+#define		HCINT_SF	(1 << 2)	/* start frame */
+#define		HCINT_RD	(1 << 3)	/* resume detect */
+#define		HCINT_UE	(1 << 4)	/* unrecoverable error */
+#define		HCINT_FNO	(1 << 5)	/* frame number overflow */
+#define		HCINT_RHSC	(1 << 6)	/* root hub status change */
+#define		HCINT_OC	(1 << 30)	/* ownership change */
+#define		HCINT_MIE	(1 << 31)	/* master interrupt enable */
+#define	HCINTENB	0x04
+#define	HCINTDIS	0x05
+#define	HCFMINTVL	0x0d
+#define	HCFMREM		0x0e
+#define	HCFMNUM		0x0f
+#define	HCLSTHRESH	0x11
+#define	HCRHDESCA	0x12
+#define		RH_A_NDP	(0x3 << 0)	/* # downstream ports */
+#define		RH_A_PSM	(1 << 8)	/* power switching mode */
+#define		RH_A_NPS	(1 << 9)	/* no power switching */
+#define		RH_A_DT		(1 << 10)	/* device type (mbz) */
+#define		RH_A_OCPM	(1 << 11)	/* overcurrent protection
+						   mode */
+#define		RH_A_NOCP	(1 << 12)	/* no overcurrent protection */
+#define		RH_A_POTPGT	(0xff << 24)	/* power on -> power good
+						   time */
+#define	HCRHDESCB	0x13
+#define		RH_B_DR		(0xffff << 0)	/* device removable flags */
+#define		RH_B_PPCM	(0xffff << 16)	/* port power control mask */
+#define	HCRHSTATUS	0x14
+#define		RH_HS_LPS	(1 << 0)	/* local power status */
+#define		RH_HS_OCI	(1 << 1)	/* over current indicator */
+#define		RH_HS_DRWE	(1 << 15)	/* device remote wakeup
+						   enable */
+#define		RH_HS_LPSC	(1 << 16)	/* local power status change */
+#define		RH_HS_OCIC	(1 << 17)	/* over current indicator
+						   change */
+#define		RH_HS_CRWE	(1 << 31)	/* clear remote wakeup
+						   enable */
+#define	HCRHPORT1	0x15
+#define		RH_PS_CCS	(1 << 0)	/* current connect status */
+#define		RH_PS_PES	(1 << 1)	/* port enable status */
+#define		RH_PS_PSS	(1 << 2)	/* port suspend status */
+#define		RH_PS_POCI	(1 << 3)	/* port over current
+						   indicator */
+#define		RH_PS_PRS	(1 << 4)	/* port reset status */
+#define		RH_PS_PPS	(1 << 8)	/* port power status */
+#define		RH_PS_LSDA	(1 << 9)	/* low speed device attached */
+#define		RH_PS_CSC	(1 << 16)	/* connect status change */
+#define		RH_PS_PESC	(1 << 17)	/* port enable status change */
+#define		RH_PS_PSSC	(1 << 18)	/* port suspend status
+						   change */
+#define		RH_PS_OCIC	(1 << 19)	/* over current indicator
+						   change */
+#define		RH_PS_PRSC	(1 << 20)	/* port reset status change */
+#define		HCRHPORT_CLRMASK	(0x1f << 16)
+#define	HCRHPORT2	0x16
+#define	HCHWCFG		0x20
+#define		HCHWCFG_15KRSEL		(1 << 12)
+#define		HCHWCFG_CLKNOTSTOP	(1 << 11)
+#define		HCHWCFG_ANALOG_OC	(1 << 10)
+#define		HCHWCFG_DACK_MODE	(1 << 8)
+#define		HCHWCFG_EOT_POL		(1 << 7)
+#define		HCHWCFG_DACK_POL	(1 << 6)
+#define		HCHWCFG_DREQ_POL	(1 << 5)
+#define		HCHWCFG_DBWIDTH_MASK	(0x03 << 3)
+#define		HCHWCFG_DBWIDTH(n)	(((n) << 3) & HCHWCFG_DBWIDTH_MASK)
+#define		HCHWCFG_INT_POL		(1 << 2)
+#define		HCHWCFG_INT_TRIGGER	(1 << 1)
+#define		HCHWCFG_INT_ENABLE	(1 << 0)
+#define	HCDMACFG	0x21
+#define		HCDMACFG_BURST_LEN_MASK	(0x03 << 5)
+#define		HCDMACFG_BURST_LEN(n)	(((n) << 5) & HCDMACFG_BURST_LEN_MASK)
+#define		HCDMACFG_BURST_LEN_1	HCDMACFG_BURST_LEN(0)
+#define		HCDMACFG_BURST_LEN_4	HCDMACFG_BURST_LEN(1)
+#define		HCDMACFG_BURST_LEN_8	HCDMACFG_BURST_LEN(2)
+#define		HCDMACFG_DMA_ENABLE	(1 << 4)
+#define		HCDMACFG_BUF_TYPE_MASK	(0x07 << 1)
+#define		HCDMACFG_CTR_SEL	(1 << 2)
+#define		HCDMACFG_ITLATL_SEL	(1 << 1)
+#define		HCDMACFG_DMA_RW_SELECT	(1 << 0)
+#define	HCXFERCTR	0x22
+#define	HCuPINT		0x24
+#define		HCuPINT_SOF		(1 << 0)
+#define		HCuPINT_ATL		(1 << 1)
+#define		HCuPINT_AIIEOT		(1 << 2)
+#define		HCuPINT_OPR		(1 << 4)
+#define		HCuPINT_SUSP		(1 << 5)
+#define		HCuPINT_CLKRDY		(1 << 6)
+#define	HCuPINTENB	0x25
+#define	HCCHIPID	0x27
+#define		HCCHIPID_MASK		0xff00
+#define		HCCHIPID_MAGIC		0x6100
+#define	HCSCRATCH	0x28
+#define	HCSWRES		0x29
+#define		HCSWRES_MAGIC		0x00f6
+#define	HCITLBUFLEN	0x2a
+#define	HCATLBUFLEN	0x2b
+#define	HCBUFSTAT	0x2c
+#define		HCBUFSTAT_ITL0_FULL	(1 << 0)
+#define		HCBUFSTAT_ITL1_FULL	(1 << 1)
+#define		HCBUFSTAT_ATL_FULL	(1 << 2)
+#define		HCBUFSTAT_ITL0_DONE	(1 << 3)
+#define		HCBUFSTAT_ITL1_DONE	(1 << 4)
+#define		HCBUFSTAT_ATL_DONE	(1 << 5)
+#define	HCRDITL0LEN	0x2d
+#define	HCRDITL1LEN	0x2e
+#define	HCITLPORT	0x40
+#define	HCATLPORT	0x41
+
+/* PTD accessor macros. */
+#define PTD_GET_COUNT(p)	(((p)->count & PTD_COUNT_MSK) >> 0)
+#define PTD_COUNT(v)		(((v) << 0) & PTD_COUNT_MSK)
+#define PTD_GET_TOGGLE(p)	(((p)->count & PTD_TOGGLE_MSK) >> 10)
+#define PTD_TOGGLE(v)		(((v) << 10) & PTD_TOGGLE_MSK)
+#define PTD_GET_ACTIVE(p)	(((p)->count & PTD_ACTIVE_MSK) >> 11)
+#define PTD_ACTIVE(v)		(((v) << 11) & PTD_ACTIVE_MSK)
+#define PTD_GET_CC(p)		(((p)->count & PTD_CC_MSK) >> 12)
+#define PTD_CC(v)		(((v) << 12) & PTD_CC_MSK)
+#define PTD_GET_MPS(p)		(((p)->mps & PTD_MPS_MSK) >> 0)
+#define PTD_MPS(v)		(((v) << 0) & PTD_MPS_MSK)
+#define PTD_GET_SPD(p)		(((p)->mps & PTD_SPD_MSK) >> 10)
+#define PTD_SPD(v)		(((v) << 10) & PTD_SPD_MSK)
+#define PTD_GET_LAST(p)		(((p)->mps & PTD_LAST_MSK) >> 11)
+#define PTD_LAST(v)		(((v) << 11) & PTD_LAST_MSK)
+#define PTD_GET_EP(p)		(((p)->mps & PTD_EP_MSK) >> 12)
+#define PTD_EP(v)		(((v) << 12) & PTD_EP_MSK)
+#define PTD_GET_LEN(p)		(((p)->len & PTD_LEN_MSK) >> 0)
+#define PTD_LEN(v)		(((v) << 0) & PTD_LEN_MSK)
+#define PTD_GET_DIR(p)		(((p)->len & PTD_DIR_MSK) >> 10)
+#define PTD_DIR(v)		(((v) << 10) & PTD_DIR_MSK)
+#define PTD_GET_B5_5(p)		(((p)->len & PTD_B5_5_MSK) >> 13)
+#define PTD_B5_5(v)		(((v) << 13) & PTD_B5_5_MSK)
+#define PTD_GET_FA(p)		(((p)->faddr & PTD_FA_MSK) >> 0)
+#define PTD_FA(v)		(((v) << 0) & PTD_FA_MSK)
+#define PTD_GET_FMT(p)		(((p)->faddr & PTD_FMT_MSK) >> 7)
+#define PTD_FMT(v)		(((v) << 7) & PTD_FMT_MSK)
+
+/*  Hardware transfer status codes -- CC from ptd->count */
+#define TD_CC_NOERROR      0x00
+#define TD_CC_CRC          0x01
+#define TD_CC_BITSTUFFING  0x02
+#define TD_CC_DATATOGGLEM  0x03
+#define TD_CC_STALL        0x04
+#define TD_DEVNOTRESP      0x05
+#define TD_PIDCHECKFAIL    0x06
+#define TD_UNEXPECTEDPID   0x07
+#define TD_DATAOVERRUN     0x08
+#define TD_DATAUNDERRUN    0x09
+    /* 0x0A, 0x0B reserved for hardware */
+#define TD_BUFFEROVERRUN   0x0C
+#define TD_BUFFERUNDERRUN  0x0D
+    /* 0x0E, 0x0F reserved for HCD */
+#define TD_NOTACCESSED     0x0F
+
+/* ------------------------------------------------------------------------- */
+
+#define	LOG2_PERIODIC_SIZE	5	/* arbitrary; this matches OHCI */
+#define	PERIODIC_SIZE		(1 << LOG2_PERIODIC_SIZE)
+
+/* Philips transfer descriptor */
+struct ptd {
+	u16 count;
+#define	PTD_COUNT_MSK	(0x3ff << 0)
+#define	PTD_TOGGLE_MSK	(1 << 10)
+#define	PTD_ACTIVE_MSK	(1 << 11)
+#define	PTD_CC_MSK	(0xf << 12)
+	u16 mps;
+#define	PTD_MPS_MSK	(0x3ff << 0)
+#define	PTD_SPD_MSK	(1 << 10)
+#define	PTD_LAST_MSK	(1 << 11)
+#define	PTD_EP_MSK	(0xf << 12)
+	u16 len;
+#define	PTD_LEN_MSK	(0x3ff << 0)
+#define	PTD_DIR_MSK	(3 << 10)
+#define	PTD_DIR_SETUP	(0)
+#define	PTD_DIR_OUT	(1)
+#define	PTD_DIR_IN	(2)
+#define	PTD_B5_5_MSK	(1 << 13)
+	u16 faddr;
+#define	PTD_FA_MSK	(0x7f << 0)
+#define	PTD_FMT_MSK	(1 << 7)
+} __attribute__ ((packed, aligned(2)));
+
+struct isp116x_ep {
+	struct usb_device *udev;
+	struct ptd ptd;
+
+	u8 maxpacket;
+	u8 epnum;
+	u8 nextpid;
+
+	u16 length;		/* of current packet */
+	unsigned char *data;	/* to databuf */
+
+	u16 error_count;
+};
+
+/* URB struct */
+#define N_URB_TD		48
+#define URB_DEL			1
+typedef struct {
+	struct isp116x_ep *ed;
+	void *transfer_buffer;	/* (in) associated data buffer */
+	int actual_length;	/* (return) actual transfer length */
+	unsigned long pipe;	/* (in) pipe information */
+#if 0
+	int state;
+#endif
+} urb_priv_t;
+
+struct isp116x_platform_data {
+	/* Enable internal resistors on downstream ports */
+	unsigned sel15Kres:1;
+	/* On-chip overcurrent detection */
+	unsigned oc_enable:1;
+	/* Enable wakeup by devices on usb bus (e.g. wakeup
+	   by attachment/detachment or by device activity
+	   such as moving a mouse). When chosen, this option
+	   prevents stopping internal clock, increasing
+	   thereby power consumption in suspended state. */
+	unsigned remote_wakeup_enable:1;
+};
+
+struct isp116x {
+	u16 *addr_reg;
+	u16 *data_reg;
+
+	struct isp116x_platform_data *board;
+
+	struct dentry *dentry;
+	unsigned long stat1, stat2, stat4, stat8, stat16;
+
+	/* Status flags */
+	unsigned disabled:1;
+	unsigned sleeping:1;
+
+	/* Root hub registers */
+	u32 rhdesca;
+	u32 rhdescb;
+	u32 rhstatus;
+	u32 rhport[2];
+
+	/* Schedule for the current frame */
+	struct isp116x_ep *atl_active;
+	int atl_buflen;
+	int atl_bufshrt;
+	int atl_last_dir;
+	int atl_finishing;
+};
+
+/* ------------------------------------------------- */
+
+/* Inter-io delay (ns). The chip is picky about access timings; it
+ * expects at least:
+ * 150ns delay between consecutive accesses to DATA_REG,
+ * 300ns delay between access to ADDR_REG and DATA_REG
+ * OE, WE MUST NOT be changed during these intervals
+ */
+#if defined(UDELAY)
+#define	isp116x_delay(h,d)	udelay(d)
+#else
+#define	isp116x_delay(h,d)	do {} while (0)
+#endif
+
+#include "../../super.h"	/*
+	 		 	* Functions to call supervisor mode
+		 	 	* Super() in in TOS is buggy
+			 	*/
+
+			 
+static inline void isp116x_write_addr(struct isp116x *isp116x, unsigned reg)
+{
+	u16 dumm;
+	u32 p = 0;
+	if ( !(Super (SUP_INQUIRE)))
+		p = SuperFromUser( );
+	isp116x->data_reg = (u16*)(ISP116X_HCD_DATA_BEE + ((reg & 0x00ff)<<1)); 
+	dumm = __raw_readw( isp116x->data_reg  );
+	isp116x->addr_reg = (u16*)ISP116X_HCD_ADDR_BEE;
+	dumm = __raw_readw( isp116x->addr_reg  );
+	isp116x_delay(isp116x, UDELAY);
+	if ((Super (SUP_INQUIRE)) && (p))
+		SuperToUser( p );
+//	ERR ( "data_reg: %x \n\r", isp116x->data_reg);
+//	ERR ( "addr_reg: %x \n\r", isp116x->addr_reg);
+}
+
+static inline void isp116x_write_data16(struct isp116x *isp116x, u16 val)
+{
+	u16 dumm;
+	u32 p = 0;
+	if ( !(Super (SUP_INQUIRE)))
+		p = SuperFromUser( );
+	isp116x->data_reg = (u16*)(ISP116X_HCD_DATA_BEE + ((val & 0xff00)>>7) ); 
+	dumm = __raw_readw(isp116x->data_reg);
+	isp116x->addr_reg = (u16*)((ISP116X_HCD_ADDR_BEE - 0x4000) + ((val & 0x00ff)<<1));
+	dumm = __raw_readw(isp116x->addr_reg);
+	isp116x_delay(isp116x, UDELAY);
+	if ((Super (SUP_INQUIRE)) && (p))
+		SuperToUser( p );
+//	ERR ( "data_reg: %x \n\r", isp116x->data_reg);
+//	ERR ( "addr_reg: %x \n\r", isp116x->addr_reg);
+}
+
+static inline void isp116x_raw_write_data16(struct isp116x *isp116x, u16 val)
+{
+	u16 dumm;
+	u32 p = 0;
+	if ( !(Super (SUP_INQUIRE)))
+		p = SuperFromUser( );
+	isp116x->data_reg = (u16*)(ISP116X_HCD_DATA_BEE + ((val & 0x00ff)<<1));
+	dumm = __raw_readw(isp116x->data_reg);
+	isp116x->addr_reg =  (u16*)((ISP116X_HCD_ADDR_BEE - 0x4000) + ((val & 0xff00)>>7)); 
+	dumm = __raw_readw(isp116x->addr_reg);
+	isp116x_delay(isp116x, UDELAY);
+	if ((Super (SUP_INQUIRE)) && (p))
+		SuperToUser( p );
+//	ERR ( "data_reg: %x \n\r", isp116x->data_reg);
+//	ERR ( "addr_reg: %x \n\r", isp116x->addr_reg);
+}
+
+
+static inline u16 isp116x_read_data16(struct isp116x *isp116x)
+{
+	u16 val;
+	u32 p = 0;
+	if ( !(Super (SUP_INQUIRE)))
+		p = SuperFromUser( );
+	isp116x->data_reg = (u16*)(ISP116X_HCD_DATA_BEE + 0x8000);
+	val = readw(isp116x->data_reg );
+	isp116x_delay(isp116x, UDELAY);
+	if ((Super (SUP_INQUIRE)) && (p))
+		SuperToUser( p );
+	return val;
+}
+
+
+static inline u16 isp116x_raw_read_data16(struct isp116x *isp116x)
+{
+	u16 val;
+	u32 p = 0;
+	if ( !(Super (SUP_INQUIRE)))
+		p = SuperFromUser( );
+	isp116x->data_reg = (u16*)(ISP116X_HCD_DATA_BEE + 0x8000);
+	val = __raw_readw(isp116x->data_reg );
+	isp116x_delay(isp116x, UDELAY);
+	if ((Super (SUP_INQUIRE)) && (p))
+		SuperToUser( p );
+//	ERR ( "data_reg: %x value: %x\n\r", isp116x->data_reg, val );
+	return val;
+}
+
+#if 0 /* We don't use it anymore */
+static inline void isp116x_write_data32(struct isp116x *isp116x, u32 val)
+{
+//	p = SuperFromUser( );
+	writew(val & 0xffff, isp116x->data_reg);
+	isp116x_delay(isp116x, UDELAY);
+	writew(val >> 16, isp116x->data_reg);
+	isp116x_delay(isp116x, UDELAY);
+//	SuperToUser( p );
+}
+#endif
+
+/*
+ * Added for NetUSBee, to write HC registers without swaping them
+ * NetUSBee already swap them by hardware (i suppose.....)
+ */
+static inline void isp116x_raw_write_data32(struct isp116x *isp116x, u32 val)
+{
+	u16 dumm;
+	u32 p = 0;
+	if ( !(Super (SUP_INQUIRE)))
+		p = SuperFromUser( );
+	isp116x->data_reg =  (u16*)(ISP116X_HCD_DATA_BEE + ((val & 0x000000ff)<<1) ); 
+	dumm = __raw_readw(isp116x->data_reg);
+	isp116x->addr_reg = (u16*)((ISP116X_HCD_ADDR_BEE - 0x4000) + ((val & 0x0000ff00)>>7)); 
+	dumm = __raw_readw(isp116x->addr_reg);
+	isp116x_delay(isp116x, UDELAY);
+	isp116x->data_reg = (u16*)(ISP116X_HCD_DATA_BEE + ((val & 0x00ff0000)>>15));
+	dumm = __raw_readw(isp116x->data_reg);
+	isp116x->addr_reg = (u16*)((ISP116X_HCD_ADDR_BEE - 0x4000) + ((val & 0xff000000)>>23) );
+	dumm = __raw_readw(isp116x->addr_reg);
+	isp116x_delay(isp116x, UDELAY);
+	if ((Super (SUP_INQUIRE)) && (p))
+		SuperToUser( p );
+}
+/***********************************************/
+
+#if 0 /* We don't use it */
+static inline u32 isp116x_read_data32(struct isp116x *isp116x)
+{
+	u32 val;
+	p = SuperFromUser( );
+	val = (u32) readw(isp116x->data_reg);
+	isp116x_delay(isp116x, UDELAY);
+	val |= ((u32) readw(isp116x->data_reg)) << 16;
+	isp116x_delay(isp116x, UDELAY);
+	SuperToUser( p );
+	return val;
+}
+#endif
+
+/*
+ * Added for NetUSBee, to read HC registers without swaping them
+ * NetUSBee already swap them by hardware (i suppose.....)
+ */
+static inline u32 isp116x_raw_read_data32(struct isp116x *isp116x)
+{
+	u32 val;
+	u32 p = 0;
+	if ( !(Super (SUP_INQUIRE)))
+		p = SuperFromUser( );
+	isp116x->data_reg = (u16*)(ISP116X_HCD_DATA_BEE + 0x8000);
+	val = (u32) __raw_readw(isp116x->data_reg );
+	isp116x_delay(isp116x, UDELAY);
+	val |= ((u32) __raw_readw(isp116x->data_reg )) << 16;
+	isp116x_delay(isp116x, UDELAY);
+	if ((Super (SUP_INQUIRE)) && (p))
+		SuperToUser( p );
+	return val;
+}
+/*******************************************************************/
+
+/* Let's keep register access functions out of line. Hint:
+   we wait at least 150 ns at every access.
+*/
+
+/* with NetUSBee use raw_read to avoid swaping bytes*/
+
+static u16 isp116x_read_reg16(struct isp116x *isp116x, unsigned reg)
+{
+	isp116x_write_addr(isp116x, reg);
+	return isp116x_raw_read_data16(isp116x);
+}
+
+static u32 isp116x_read_reg32(struct isp116x *isp116x, unsigned reg)
+{
+	isp116x_write_addr(isp116x, reg);
+	return isp116x_raw_read_data32(isp116x);
+}
+
+static void isp116x_write_reg16(struct isp116x *isp116x, unsigned reg,
+				unsigned val)
+{
+	isp116x_write_addr(isp116x, reg | ISP116x_WRITE_OFFSET);
+	isp116x_raw_write_data16(isp116x, (u16) (val & 0xffff));
+}
+
+/* with NetUSBee used raw_write to avoid swaping bytes by software */
+static void isp116x_write_reg32(struct isp116x *isp116x, unsigned reg,
+				unsigned val)
+{
+	isp116x_write_addr(isp116x, reg | ISP116x_WRITE_OFFSET);
+	isp116x_raw_write_data32(isp116x, (u32) val);
+}
+
+/* --- USB HUB constants (not OHCI-specific; see hub.h) -------------------- */
+
+/* destination of request */
+#define RH_INTERFACE               0x01
+#define RH_ENDPOINT                0x02
+#define RH_OTHER                   0x03
+
+#define RH_CLASS                   0x20
+#define RH_VENDOR                  0x40
+
+/* Requests: bRequest << 8 | bmRequestType */
+#define RH_GET_STATUS           0x0080
+#define RH_CLEAR_FEATURE        0x0100
+#define RH_SET_FEATURE          0x0300
+#define RH_SET_ADDRESS          0x0500
+#define RH_GET_DESCRIPTOR       0x0680
+#define RH_SET_DESCRIPTOR       0x0700
+#define RH_GET_CONFIGURATION    0x0880
+#define RH_SET_CONFIGURATION    0x0900
+#define RH_GET_STATE            0x0280
+#define RH_GET_INTERFACE        0x0A80
+#define RH_SET_INTERFACE        0x0B00
+#define RH_SYNC_FRAME           0x0C80
+/* Our Vendor Specific Request */
+#define RH_SET_EP               0x2000
+
+/* Hub port features */
+#define RH_PORT_CONNECTION         0x00
+#define RH_PORT_ENABLE             0x01
+#define RH_PORT_SUSPEND            0x02
+#define RH_PORT_OVER_CURRENT       0x03
+#define RH_PORT_RESET              0x04
+#define RH_PORT_POWER              0x08
+#define RH_PORT_LOW_SPEED          0x09
+
+#define RH_C_PORT_CONNECTION       0x10
+#define RH_C_PORT_ENABLE           0x11
+#define RH_C_PORT_SUSPEND          0x12
+#define RH_C_PORT_OVER_CURRENT     0x13
+#define RH_C_PORT_RESET            0x14
+
+/* Hub features */
+#define RH_C_HUB_LOCAL_POWER       0x00
+#define RH_C_HUB_OVER_CURRENT      0x01
+
+#define RH_DEVICE_REMOTE_WAKEUP    0x00
+#define RH_ENDPOINT_STALL          0x01
+
+#define RH_ACK                     0x01
+#define RH_REQ_ERR                 -1
+#define RH_NACK                    0x00
+
+#endif /* _NETUSBEE_ISP116X_H */

FireBee/trunk/usb/store/host/ohci-pci/ltoa.c

@@ -0,0 +1,38 @@
+/*
+ * File:        ltoa.c
+ * Purpose:     Function normally found in a standard C lib.
+ *
+ * Notes:       This supports ASCII only!!!
+ */
+
+void ltoa(char *buf, long n, unsigned long base)
+{
+	unsigned long un;
+	char *tmp, ch;
+	un = n;
+	if((base == 10) && (n < 0))
+	{
+		*buf++ = '-';
+		un = -n;
+	}
+	tmp = buf;
+	do
+	{
+		ch = un % base;
+		un = un / base;
+		if(ch <= 9)
+			ch += '0';
+		else
+			ch += 'a' - 10;
+		*tmp++ = ch;
+	}
+	while(un);
+	*tmp = '\0';
+	while(tmp > buf)
+	{
+		ch = *buf;
+		*buf++ = *--tmp;
+		*tmp = ch;
+	}
+}
+

FireBee/trunk/usb/store/host/ohci-pci/mod_devicetable.h

@@ -0,0 +1,165 @@
+#ifndef MOD_DEVICETABLE_H
+#define MOD_DEVICETABLE_H
+
+#define PCI_ANY_ID (~0)
+
+struct pci_device_id {
+	unsigned long vendor, device;		/* Vendor and device ID or PCI_ANY_ID*/
+	unsigned long subvendor, subdevice;	/* Subsystem ID's or PCI_ANY_ID */
+	unsigned long class, class_mask;	/* (class,subclass,prog-if) triplet */
+	unsigned long driver_data;	/* Data private to the driver */
+};
+
+#define IEEE1394_MATCH_VENDOR_ID	0x0001
+#define IEEE1394_MATCH_MODEL_ID		0x0002
+#define IEEE1394_MATCH_SPECIFIER_ID	0x0004
+#define IEEE1394_MATCH_VERSION		0x0008
+
+struct ieee1394_device_id {
+	unsigned long match_flags;
+	unsigned long vendor_id;
+	unsigned long model_id;
+	unsigned long specifier_id;
+	unsigned long version;
+	unsigned long driver_data;
+};
+
+/*
+ * Device table entry for "new style" table-driven USB drivers.
+ * User mode code can read these tables to choose which modules to load.
+ * Declare the table as a MODULE_DEVICE_TABLE.
+ *
+ * A probe() parameter will point to a matching entry from this table.
+ * Use the driver_info field for each match to hold information tied
+ * to that match:  device quirks, etc.
+ *
+ * Terminate the driver's table with an all-zeroes entry.
+ * Use the flag values to control which fields are compared.
+ */
+
+/**
+ * struct usb_device_id - identifies USB devices for probing and hotplugging
+ * @match_flags: Bit mask controlling of the other fields are used to match
+ *	against new devices.  Any field except for driver_info may be used,
+ *	although some only make sense in conjunction with other fields.
+ *	This is usually set by a USB_DEVICE_*() macro, which sets all
+ *	other fields in this structure except for driver_info.
+ * @idVendor: USB vendor ID for a device; numbers are assigned
+ *	by the USB forum to its members.
+ * @idProduct: Vendor-assigned product ID.
+ * @bcdDevice_lo: Low end of range of vendor-assigned product version numbers.
+ *	This is also used to identify individual product versions, for
+ *	a range consisting of a single device.
+ * @bcdDevice_hi: High end of version number range.  The range of product
+ *	versions is inclusive.
+ * @bDeviceClass: Class of device; numbers are assigned
+ *	by the USB forum.  Products may choose to implement classes,
+ *	or be vendor-specific.  Device classes specify behavior of all
+ *	the interfaces on a devices.
+ * @bDeviceSubClass: Subclass of device; associated with bDeviceClass.
+ * @bDeviceProtocol: Protocol of device; associated with bDeviceClass.
+ * @bInterfaceClass: Class of interface; numbers are assigned
+ *	by the USB forum.  Products may choose to implement classes,
+ *	or be vendor-specific.  Interface classes specify behavior only
+ *	of a given interface; other interfaces may support other classes.
+ * @bInterfaceSubClass: Subclass of interface; associated with bInterfaceClass.
+ * @bInterfaceProtocol: Protocol of interface; associated with bInterfaceClass.
+ * @driver_info: Holds information used by the driver.  Usually it holds
+ *	a pointer to a descriptor understood by the driver, or perhaps
+ *	device flags.
+ *
+ * In most cases, drivers will create a table of device IDs by using
+ * USB_DEVICE(), or similar macros designed for that purpose.
+ * They will then export it to userspace using MODULE_DEVICE_TABLE(),
+ * and provide it to the USB core through their usb_driver structure.
+ *
+ * See the usb_match_id() function for information about how matches are
+ * performed.  Briefly, you will normally use one of several macros to help
+ * construct these entries.  Each entry you provide will either identify
+ * one or more specific products, or will identify a class of products
+ * which have agreed to behave the same.  You should put the more specific
+ * matches towards the beginning of your table, so that driver_info can
+ * record quirks of specific products.
+ */
+struct usb_device_id {
+	/* which fields to match against? */
+	unsigned short		match_flags;
+
+	/* Used for product specific matches; range is inclusive */
+	unsigned short		idVendor;
+	unsigned short		idProduct;
+	unsigned short		bcdDevice_lo;
+	unsigned short		bcdDevice_hi;
+
+	/* Used for device class matches */
+	unsigned char		bDeviceClass;
+	unsigned char		bDeviceSubClass;
+	unsigned char		bDeviceProtocol;
+
+	/* Used for interface class matches */
+	unsigned char		bInterfaceClass;
+	unsigned char		bInterfaceSubClass;
+	unsigned char		bInterfaceProtocol;
+
+	/* not matched against */
+	unsigned long	driver_info;
+};
+
+/* Some useful macros to use to create struct usb_device_id */
+#define USB_DEVICE_ID_MATCH_VENDOR		0x0001
+#define USB_DEVICE_ID_MATCH_PRODUCT		0x0002
+#define USB_DEVICE_ID_MATCH_DEV_LO		0x0004
+#define USB_DEVICE_ID_MATCH_DEV_HI		0x0008
+#define USB_DEVICE_ID_MATCH_DEV_CLASS		0x0010
+#define USB_DEVICE_ID_MATCH_DEV_SUBCLASS	0x0020
+#define USB_DEVICE_ID_MATCH_DEV_PROTOCOL	0x0040
+#define USB_DEVICE_ID_MATCH_INT_CLASS		0x0080
+#define USB_DEVICE_ID_MATCH_INT_SUBCLASS	0x0100
+#define USB_DEVICE_ID_MATCH_INT_PROTOCOL	0x0200
+
+/* s390 CCW devices */
+struct ccw_device_id {
+	unsigned short	match_flags;	/* which fields to match against */
+
+	unsigned short	cu_type;	/* control unit type     */
+	unsigned short	dev_type;	/* device type           */
+	unsigned char	cu_model;	/* control unit model    */
+	unsigned char	dev_model;	/* device model          */
+
+	unsigned long driver_info;
+};
+
+#define CCW_DEVICE_ID_MATCH_CU_TYPE		0x01
+#define CCW_DEVICE_ID_MATCH_CU_MODEL		0x02
+#define CCW_DEVICE_ID_MATCH_DEVICE_TYPE		0x04
+#define CCW_DEVICE_ID_MATCH_DEVICE_MODEL	0x08
+
+
+#define PNP_ID_LEN	8
+#define PNP_MAX_DEVICES	8
+
+struct pnp_device_id {
+	unsigned char id[PNP_ID_LEN];
+	unsigned long driver_data;
+};
+
+struct pnp_card_device_id {
+	unsigned char id[PNP_ID_LEN];
+	unsigned long driver_data;
+	struct {
+		unsigned char id[PNP_ID_LEN];
+	} devs[PNP_MAX_DEVICES];
+};
+
+
+#define SERIO_ANY	0xff
+
+struct serio_device_id {
+	unsigned char type;
+	unsigned char extra;
+	unsigned char id;
+	unsigned char proto;
+};
+
+
+#endif /* MOD_DEVICETABLE_H */

FireBee/trunk/usb/store/host/ohci-pci/ohci.h

@@ -0,0 +1,457 @@
+/*
+ * URB OHCI HCD (Host Controller Driver) for USB.
+ *
+ * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
+ * (C) Copyright 2000-2001 David Brownell <dbrownell@users.sourceforge.net>
+ *
+ * usb-ohci.h
+ */
+
+static int cc_to_error[16] = {
+
+/* mapping of the OHCI CC status to error codes */
+	/* No  Error  */	       0,
+	/* CRC Error  */	       USB_ST_CRC_ERR,
+	/* Bit Stuff  */	       USB_ST_BIT_ERR,
+	/* Data Togg  */	       USB_ST_CRC_ERR,
+	/* Stall      */	       USB_ST_STALLED,
+	/* DevNotResp */	       -1,
+	/* PIDCheck   */	       USB_ST_BIT_ERR,
+	/* UnExpPID   */	       USB_ST_BIT_ERR,
+	/* DataOver   */	       USB_ST_BUF_ERR,
+	/* DataUnder  */	       USB_ST_BUF_ERR,
+	/* reservd    */	       -1,
+	/* reservd    */	       -1,
+	/* BufferOver */	       USB_ST_BUF_ERR,
+	/* BuffUnder  */	       USB_ST_BUF_ERR,
+	/* Not Access */	       -1,
+	/* Not Access */	       -1
+};
+
+static const char *cc_to_string[16] = {
+	"No Error",
+	"CRC: Last data packet from endpoint contained a CRC error.",
+	"BITSTUFFING: Last data packet from endpoint contained a bit stuffing violation",
+	"DATATOGGLEMISMATCH: Last packet from endpoint had data toggle PID that did not match the expected value.",
+	"STALL: TD was moved to the Done Queue because the endpoint returned a STALL PID",
+	"DEVICENOTRESPONDING: Device did not respond to token (IN) or did not provide a handshake (OUT)",
+	"PIDCHECKFAILURE: Check bits on PID from endpoint failed on data PID (IN) or handshake (OUT)",
+	"UNEXPECTEDPID: Receive PID was not valid when encountered or PID value is not defined.",
+	"DATAOVERRUN: The amount of data returned by the endpoint exceeded either the size of the maximum data packet allowed from the endpoint (found in MaximumPacketSize field of ED) or the remaining buffer size.",
+	"DATAUNDERRUN: The endpoint returned less than MaximumPacketSize and that amount was not sufficient to fill the specified buffer",
+	"reserved1",
+	"reserved2",
+	"BUFFEROVERRUN: During an IN, HC received data from endpoint faster than it could be written to system memory",
+	"BUFFERUNDERRUN: During an OUT, HC could not retrieve data from system memory fast enough to keep up with data USB data rate.",
+	"NOT ACCESSED: This code is set by software before the TD is placed on a list to be processed by the HC.(1)",
+	"NOT ACCESSED: This code is set by software before the TD is placed on a list to be processed by the HC.(2)",
+};
+
+/* ED States */
+
+#define ED_NEW		0x00
+#define ED_UNLINK	0x01
+#define ED_OPER		0x02
+#define ED_DEL		0x04
+#define ED_URB_DEL	0x08
+
+/* usb_ohci_ed */
+struct ed {
+	__u32 hwINFO;
+	__u32 hwTailP;
+	__u32 hwHeadP;
+	__u32 hwNextED;
+
+	struct ed *ed_prev;
+	__u8 int_period;
+	__u8 int_branch;
+	__u8 int_load;
+	__u8 int_interval;
+	__u8 state;
+	__u8 type;
+	__u16 last_iso;
+	struct ed *ed_rm_list;
+
+	struct usb_device *usb_dev;
+	void *purb;
+	__u32 unused[2];
+} __attribute__((aligned(16)));
+typedef struct ed ed_t;
+
+
+/* TD info field */
+#define TD_CC	    0xf0000000
+#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f)
+#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28)
+#define TD_EC	    0x0C000000
+#define TD_T	    0x03000000
+#define TD_T_DATA0  0x02000000
+#define TD_T_DATA1  0x03000000
+#define TD_T_TOGGLE 0x00000000
+#define TD_R	    0x00040000
+#define TD_DI	    0x00E00000
+#define TD_DI_SET(X) (((X) & 0x07)<< 21)
+#define TD_DP	    0x00180000
+#define TD_DP_SETUP 0x00000000
+#define TD_DP_IN    0x00100000
+#define TD_DP_OUT   0x00080000
+
+#define TD_ISO	    0x00010000
+#define TD_DEL	    0x00020000
+
+/* CC Codes */
+#define TD_CC_NOERROR	   0x00
+#define TD_CC_CRC	   0x01
+#define TD_CC_BITSTUFFING  0x02
+#define TD_CC_DATATOGGLEM  0x03
+#define TD_CC_STALL	   0x04
+#define TD_DEVNOTRESP	   0x05
+#define TD_PIDCHECKFAIL	   0x06
+#define TD_UNEXPECTEDPID   0x07
+#define TD_DATAOVERRUN	   0x08
+#define TD_DATAUNDERRUN	   0x09
+#define TD_BUFFEROVERRUN   0x0C
+#define TD_BUFFERUNDERRUN  0x0D
+#define TD_NOTACCESSED	   0x0F
+
+
+#define MAXPSW 1
+
+struct td {
+	__u32 hwINFO;
+	__u32 hwCBP;		/* Current Buffer Pointer */
+	__u32 hwNextTD;		/* Next TD Pointer */
+	__u32 hwBE;		/* Memory Buffer End Pointer */
+
+	__u16 hwPSW[MAXPSW];
+	__u8 unused;
+	__u8 index;
+	struct ed *ed;
+	struct td *next_dl_td;
+	struct usb_device *usb_dev;
+	int transfer_len;
+	__u32 data;
+
+	__u32 unused2[2];
+} __attribute__((aligned(32)));
+typedef struct td td_t;
+
+#define OHCI_ED_SKIP	(1 << 14)
+
+/*
+ * The HCCA (Host Controller Communications Area) is a 256 byte
+ * structure defined in the OHCI spec. that the host controller is
+ * told the base address of.  It must be 256-byte aligned.
+ */
+
+#define NUM_INTS 32	/* part of the OHCI standard */
+struct ohci_hcca {
+	__u32	int_table[NUM_INTS];	/* Interrupt ED table */
+#if defined(CONFIG_MPC5200)
+	__u16	pad1;			/* set to 0 on each frame_no change */
+	__u16	frame_no;		/* current frame number */
+#else
+	__u16	frame_no;		/* current frame number */
+	__u16	pad1;			/* set to 0 on each frame_no change */
+#endif
+	__u32	done_head;		/* info returned for an interrupt */
+	u8		reserved_for_hc[116];
+} __attribute__((aligned(256)));
+
+
+/*
+ * Maximum number of root hub ports.
+ */
+#ifndef CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS
+# error "CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS undefined!"
+#endif
+
+/*
+ * This is the structure of the OHCI controller's memory mapped I/O
+ * region.  This is Memory Mapped I/O.	You must use the readl() and
+ * writel() macros defined in asm/io.h to access these!!
+ */
+struct ohci_regs {
+	/* control and status registers */
+	__u32	revision;
+	__u32	control;
+	__u32	cmdstatus;
+	__u32	intrstatus;
+	__u32	intrenable;
+	__u32	intrdisable;
+	/* memory pointers */
+	__u32	hcca;
+	__u32	ed_periodcurrent;
+	__u32	ed_controlhead;
+	__u32	ed_controlcurrent;
+	__u32	ed_bulkhead;
+	__u32	ed_bulkcurrent;
+	__u32	donehead;
+	/* frame counters */
+	__u32	fminterval;
+	__u32	fmremaining;
+	__u32	fmnumber;
+	__u32	periodicstart;
+	__u32	lsthresh;
+	/* Root hub ports */
+	struct	ohci_roothub_regs {
+		__u32	a;
+		__u32	b;
+		__u32	status;
+		__u32	portstatus[CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS];
+	} roothub;
+} __attribute__((aligned(32)));
+
+/* Some EHCI controls */
+#define EHCI_USBCMD_OFF		0x20
+#define EHCI_USBCMD_HCRESET	(1 << 1)
+
+/* OHCI CONTROL AND STATUS REGISTER MASKS */
+
+/*
+ * HcControl (control) register masks
+ */
+#define OHCI_CTRL_CBSR	(3 << 0)	/* control/bulk service ratio */
+#define OHCI_CTRL_PLE	(1 << 2)	/* periodic list enable */
+#define OHCI_CTRL_IE	(1 << 3)	/* isochronous enable */
+#define OHCI_CTRL_CLE	(1 << 4)	/* control list enable */
+#define OHCI_CTRL_BLE	(1 << 5)	/* bulk list enable */
+#define OHCI_CTRL_HCFS	(3 << 6)	/* host controller functional state */
+#define OHCI_CTRL_IR	(1 << 8)	/* interrupt routing */
+#define OHCI_CTRL_RWC	(1 << 9)	/* remote wakeup connected */
+#define OHCI_CTRL_RWE	(1 << 10)	/* remote wakeup enable */
+
+/* pre-shifted values for HCFS */
+#	define OHCI_USB_RESET	(0 << 6)
+#	define OHCI_USB_RESUME	(1 << 6)
+#	define OHCI_USB_OPER	(2 << 6)
+#	define OHCI_USB_SUSPEND (3 << 6)
+
+/*
+ * HcCommandStatus (cmdstatus) register masks
+ */
+#define OHCI_HCR	(1 << 0)	/* host controller reset */
+#define OHCI_CLF	(1 << 1)	/* control list filled */
+#define OHCI_BLF	(1 << 2)	/* bulk list filled */
+#define OHCI_OCR	(1 << 3)	/* ownership change request */
+#define OHCI_SOC	(3 << 16)	/* scheduling overrun count */
+
+/*
+ * masks used with interrupt registers:
+ * HcInterruptStatus (intrstatus)
+ * HcInterruptEnable (intrenable)
+ * HcInterruptDisable (intrdisable)
+ */
+#define OHCI_INTR_SO	(1 << 0)	/* scheduling overrun */
+#define OHCI_INTR_WDH	(1 << 1)	/* writeback of done_head */
+#define OHCI_INTR_SF	(1 << 2)	/* start frame */
+#define OHCI_INTR_RD	(1 << 3)	/* resume detect */
+#define OHCI_INTR_UE	(1 << 4)	/* unrecoverable error */
+#define OHCI_INTR_FNO	(1 << 5)	/* frame number overflow */
+#define OHCI_INTR_RHSC	(1 << 6)	/* root hub status change */
+#define OHCI_INTR_OC	(1 << 30)	/* ownership change */
+#define OHCI_INTR_MIE	(1 << 31)	/* master interrupt enable */
+
+
+/* Virtual Root HUB */
+struct virt_root_hub {
+	int devnum; /* Address of Root Hub endpoint */
+	void *dev;  /* was urb */
+	void *int_addr;
+	int send;
+	int interval;
+};
+
+/* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */
+
+/* destination of request */
+#define RH_INTERFACE		   0x01
+#define RH_ENDPOINT		   0x02
+#define RH_OTHER		   0x03
+
+#define RH_CLASS		   0x20
+#define RH_VENDOR		   0x40
+
+/* Requests: bRequest << 8 | bmRequestType */
+#define RH_GET_STATUS		0x0080
+#define RH_CLEAR_FEATURE	0x0100
+#define RH_SET_FEATURE		0x0300
+#define RH_SET_ADDRESS		0x0500
+#define RH_GET_DESCRIPTOR	0x0680
+#define RH_SET_DESCRIPTOR	0x0700
+#define RH_GET_CONFIGURATION	0x0880
+#define RH_SET_CONFIGURATION	0x0900
+#define RH_GET_STATE		0x0280
+#define RH_GET_INTERFACE	0x0A80
+#define RH_SET_INTERFACE	0x0B00
+#define RH_SYNC_FRAME		0x0C80
+/* Our Vendor Specific Request */
+#define RH_SET_EP		0x2000
+
+
+/* Hub port features */
+#define RH_PORT_CONNECTION	   0x00
+#define RH_PORT_ENABLE		   0x01
+#define RH_PORT_SUSPEND		   0x02
+#define RH_PORT_OVER_CURRENT	   0x03
+#define RH_PORT_RESET		   0x04
+#define RH_PORT_POWER		   0x08
+#define RH_PORT_LOW_SPEED	   0x09
+
+#define RH_C_PORT_CONNECTION	   0x10
+#define RH_C_PORT_ENABLE	   0x11
+#define RH_C_PORT_SUSPEND	   0x12
+#define RH_C_PORT_OVER_CURRENT	   0x13
+#define RH_C_PORT_RESET		   0x14
+
+/* Hub features */
+#define RH_C_HUB_LOCAL_POWER	   0x00
+#define RH_C_HUB_OVER_CURRENT	   0x01
+
+#define RH_DEVICE_REMOTE_WAKEUP	   0x00
+#define RH_ENDPOINT_STALL	   0x01
+
+#define RH_ACK			   0x01
+#define RH_REQ_ERR		   -1
+#define RH_NACK			   0x00
+
+
+/* OHCI ROOT HUB REGISTER MASKS */
+
+/* roothub.portstatus [i] bits */
+#define RH_PS_CCS	     0x00000001		/* current connect status */
+#define RH_PS_PES	     0x00000002		/* port enable status*/
+#define RH_PS_PSS	     0x00000004		/* port suspend status */
+#define RH_PS_POCI	     0x00000008		/* port over current indicator */
+#define RH_PS_PRS	     0x00000010		/* port reset status */
+#define RH_PS_PPS	     0x00000100		/* port power status */
+#define RH_PS_LSDA	     0x00000200		/* low speed device attached */
+#define RH_PS_CSC	     0x00010000		/* connect status change */
+#define RH_PS_PESC	     0x00020000		/* port enable status change */
+#define RH_PS_PSSC	     0x00040000		/* port suspend status change */
+#define RH_PS_OCIC	     0x00080000		/* over current indicator change */
+#define RH_PS_PRSC	     0x00100000		/* port reset status change */
+
+/* roothub.status bits */
+#define RH_HS_LPS	     0x00000001		/* local power status */
+#define RH_HS_OCI	     0x00000002		/* over current indicator */
+#define RH_HS_DRWE	     0x00008000		/* device remote wakeup enable */
+#define RH_HS_LPSC	     0x00010000		/* local power status change */
+#define RH_HS_OCIC	     0x00020000		/* over current indicator change */
+#define RH_HS_CRWE	     0x80000000		/* clear remote wakeup enable */
+
+/* roothub.b masks */
+#define RH_B_DR		0x0000ffff		/* device removable flags */
+#define RH_B_PPCM	0xffff0000		/* port power control mask */
+
+/* roothub.a masks */
+#define RH_A_NDP	(0xff << 0)		/* number of downstream ports */
+#define RH_A_PSM	(1 << 8)		/* power switching mode */
+#define RH_A_NPS	(1 << 9)		/* no power switching */
+#define RH_A_DT		(1 << 10)		/* device type (mbz) */
+#define RH_A_OCPM	(1 << 11)		/* over current protection mode */
+#define RH_A_NOCP	(1 << 12)		/* no over current protection */
+#define RH_A_POTPGT	(0xff << 24)		/* power on to power good time */
+
+/* urb */
+#define N_URB_TD 48
+typedef struct
+{
+	ed_t *ed;
+	__u16 length;	/* number of tds associated with this request */
+	__u16 td_cnt;	/* number of tds already serviced */
+	struct usb_device *dev;
+	int   state;
+	unsigned long pipe;
+	void *transfer_buffer;
+	int transfer_buffer_length;
+	int interval;
+	int actual_length;
+	int finished;
+	td_t *td[N_URB_TD];	/* list pointer to all corresponding TDs associated with this request */
+} urb_priv_t;
+#define URB_DEL 1
+
+#define NUM_EDS 8		/* num of preallocated endpoint descriptors */
+
+struct ohci_device {
+	ed_t	ed[NUM_EDS];
+	int ed_cnt;
+};
+
+/*
+ * This is the full ohci controller description
+ *
+ * Note how the "proper" USB information is just
+ * a subset of what the full implementation needs. (Linus)
+ */
+
+typedef struct ohci {
+	long handle;              /* PCI BIOS */
+	int big_endian;           /* PCI BIOS */
+	struct ohci_hcca *hcca_unaligned;
+	struct ohci_hcca *hcca;		/* hcca */
+	td_t *td_unaligned;
+	struct ohci_device *ohci_dev_unaligned;
+	/* this allocates EDs for all possible endpoints */
+	struct ohci_device *ohci_dev;
+	/*dma_addr_t hcca_dma;*/
+
+	int irq;
+	int disabled;			/* e.g. got a UE, we're hung */
+	int sleeping;
+	unsigned long flags;		/* for HC bugs */
+
+	unsigned long dma_offset;
+	struct ohci_regs *regs; /* OHCI controller's memory */
+
+	int ohci_int_load[32];	 /* load of the 32 Interrupt Chains (for load balancing)*/
+	ed_t *ed_rm_list[2];	 /* lists of all endpoints to be removed */
+	ed_t *ed_bulktail;	 /* last endpoint of bulk list */
+	ed_t *ed_controltail;	 /* last endpoint of control list */
+	int intrstatus;
+	__u32 hc_control;		/* copy of the hc control reg */
+	struct usb_device *dev[32];
+	struct virt_root_hub rh;
+
+	const char	*slot_name;
+} ohci_t;
+
+/* hcd */
+/* endpoint */
+static int ep_link(ohci_t * ohci, ed_t * ed);
+static int ep_unlink(ohci_t * ohci, ed_t * ed);
+static ed_t * ep_add_ed(struct usb_device * usb_dev, unsigned long pipe,
+		int interval, int load);
+
+/*-------------------------------------------------------------------------*/
+
+/* we need more TDs than EDs */
+#define NUM_TD 64
+
+/* pointers to aligned storage */
+td_t *ptd;
+
+/* TDs ... */
+static inline struct td *td_alloc(struct usb_device *usb_dev)
+{
+	int i;
+	struct td	*td;
+	td = NULL;
+	for(i = 0; i < NUM_TD; i++)
+	{
+		if(ptd[i].usb_dev == NULL)
+		{
+			td = &ptd[i];
+			td->usb_dev = usb_dev;
+			break;
+		}
+	}
+	return td;
+}
+
+static inline void ed_free(struct ed *ed)
+{
+	ed->usb_dev = NULL;
+}
+

FireBee/trunk/usb/store/host/ohci-pci/pcixbios.h

@@ -0,0 +1,342 @@
+/* TOS 4.04 Xbios PCI for the CT60 board
+*  Didier Mequignon 2005, e-mail: aniplay@wanadoo.fr
+*
+*  This library is free software; you can redistribute it and/or
+*  modify it under the terms of the GNU Lesser General Public
+*  License as published by the Free Software Foundation; either
+*  version 2.1 of the License, or (at your option) any later version.
+*
+*  This library is distributed in the hope that it will be useful,
+*  but WITHOUT ANY WARRANTY; without even the implied warranty of
+*  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+*  Lesser General Public License for more details.
+*
+*  You should have received a copy of the GNU Lesser General Public
+*  License along with this library; if not, write to the Free Software
+*  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+*/
+
+#ifndef	_OHCI_PCI_PCIXBIOS_H
+#define	_OHCI_PCI_PCIXBIOS_H
+
+#define PCIIDR                0x00   /* PCI Configuration ID Register       */
+#define PCICSR                0x04   /* PCI Command/Status Register         */
+#define PCICR                 0x04   /* PCI Command Register                */
+#define PCISR                 0x06   /* PCI Status Register                 */
+#define PCIREV                0x08   /* PCI Revision ID Register            */
+#define PCICCR                0x09   /* PCI Class Code Register             */
+#define PCICLSR               0x0C   /* PCI Cache Line Size Register        */
+#define PCILTR                0x0D   /* PCI Latency Timer Register          */
+#define PCIHTR                0x0E   /* PCI Header Type Register            */
+#define PCIBISTR              0x0F   /* PCI Build-In Self Test Register     */
+#define PCIBAR0               0x10   /* PCI Base Address Register for Memory
+                                        Accesses to Local, Runtime, and DMA */
+#define PCIBAR1               0x14   /* PCI Base Address Register for I/O
+                                        Accesses to Local, Runtime, and DMA */
+#define PCIBAR2               0x18   /* PCI Base Address Register for Memory
+                                        Accesses to Local Address Space 0   */
+#define PCIBAR3               0x1C   /* PCI Base Address Register for Memory
+                                        Accesses to Local Address Space 1   */ 
+#define PCIBAR4               0x20   /* PCI Base Address Register, reserved */
+#define PCIBAR5               0x24   /* PCI Base Address Register, reserved */
+#define PCICIS                0x28   /* PCI Cardbus CIS Pointer, not support*/
+#define PCISVID               0x2C   /* PCI Subsystem Vendor ID             */
+#define PCISID                0x2E   /* PCI Subsystem ID                    */
+#define PCIERBAR              0x30   /* PCI Expansion ROM Base Register     */
+#define CAP_PTR               0x34   /* New Capability Pointer              */
+#define PCIILR                0x3C   /* PCI Interrupt Line Register         */
+#define PCIIPR                0x3D   /* PCI Interrupt Pin Register          */
+#define PCIMGR                0x3E   /* PCI Min_Gnt Register                */
+#define PCIMLR                0x3F   /* PCI Max_Lat Register                */
+#define PMCAPID               0x40   /* Power Management Capability ID      */
+#define PMNEXT                0x41   /* Power Management Next Capability
+                                        Pointer                             */
+#define PMC                   0x42   /* Power Management Capabilities       */
+#define PMCSR                 0x44   /* Power Management Control/Status     */
+#define PMCSR_BSE             0x46   /* PMCSR Bridge Support Extensions     */
+#define PMDATA                0x47   /* Power Management Data               */
+#define HS_CNTL               0x48   /* Hot Swap Control                    */
+#define HS_NEXT               0x49   /* Hot Swap Next Capability Pointer    */
+#define HS_CSR                0x4A   /* Hot Swap Control/Status             */
+#define PVPDCNTL              0x4C   /* PCI Vital Product Data Control      */
+#define PVPD_NEXT             0x4D   /* PCI Vital Product Data Next
+                                        Capability Pointer                  */
+#define PVPDAD                0x4E   /* PCI Vital Product Data Address      */
+#define PVPDATA               0x50   /* PCI VPD Data                        */
+
+typedef struct
+{
+  unsigned long *subcookie;
+  unsigned long version;
+  long routine[45];
+} PCI_COOKIE;
+
+typedef struct                       /* structure of resource descriptor    */
+{
+	unsigned short next;               /* length of the following structure   */
+	unsigned short flags;              /* type of resource and misc. flags    */
+	unsigned long start;               /* start-address of resource           */
+	unsigned long length;              /* length of resource                  */
+	unsigned long offset;              /* offset PCI to phys. CPU Address     */
+	unsigned long dmaoffset;           /* offset for DMA-transfers            */
+} PCI_RSC_DESC;
+
+typedef struct                       /* structure of address conversion     */
+{
+	unsigned long adr;                 /* calculated address (CPU<->PCI)      */
+	unsigned long len;                 /* length of memory range              */
+} PCI_CONV_ADR;
+
+/******************************************************************************/
+/*                          PCI-BIOS Error Codes                              */
+/******************************************************************************/
+#define PCI_SUCCESSFUL            0  /* everything's fine         */
+#define PCI_FUNC_NOT_SUPPORTED   -2  /* function not supported    */
+#define PCI_BAD_VENDOR_ID        -3  /* wrong Vendor ID           */
+#define PCI_DEVICE_NOT_FOUND     -4  /* PCI-Device not found      */
+#define PCI_BAD_REGISTER_NUMBER  -5  /* wrong register number     */
+#define PCI_SET_FAILED           -6  /* reserved for later use    */
+#define PCI_BUFFER_TOO_SMALL     -7  /* reserved for later use    */
+#define PCI_GENERAL_ERROR        -8  /* general BIOS error code   */
+#define PCI_BAD_HANDLE           -9  /* wrong/unknown PCI-handle  */
+
+/******************************************************************************/
+/*                      Flags used in Resource-Descriptor                     */
+/******************************************************************************/
+#define FLG_IO        0x4000         /* Ressource in IO range               */
+#define FLG_LAST      0x8000         /* last ressource                      */
+#define FLG_8BIT      0x0100         /* 8 bit accesses allowed              */
+#define FLG_16BIT     0x0200         /* 16 bit accesses allowed             */
+#define FLG_32BIT     0x0400         /* 32 bit accesses allowed             */
+#define FLG_ENDMASK   0x000F         /* mask for byte ordering              */
+
+/******************************************************************************/
+/*                 Values used in FLG_ENDMASK for Byte Ordering               */
+/******************************************************************************/
+#define ORD_MOTOROLA       0         /* Motorola (big endian)               */
+#define ORD_INTEL_AS       1         /* Intel (little endian), addr.swapped */
+#define ORD_INTEL_LS       2         /* Intel (little endian), lane swapped */
+#define ORD_UNKNOWN       15         /* unknown (BIOS-calls allowed only)   */
+
+/******************************************************************************/
+/*                   Status Info used in Device-Descriptor                    */
+/******************************************************************************/
+#define DEVICE_FREE        0         /* Device is not used                  */
+#define DEVICE_USED        1         /* Device is used by another driver    */
+#define DEVICE_CALLBACK    2         /* used, but driver can be cancelled   */
+#define DEVICE_AVAILABLE   3         /* used, not available                 */
+#define NO_DEVICE         -1         /* no device detected                  */
+
+/******************************************************************************/
+/*                            Callback-Routine                                */
+/******************************************************************************/
+ #define GET_DRIVER_ID      0        /* CB-Routine 0: Get Driver ID         */
+ #define REMOVE_DRIVER      1        /* CB-Routine 1: Remove Driver         */
+
+/******************************************************************************/
+/*                              Functions                                     */
+/******************************************************************************/
+//#ifndef OSBIND_CLOBBER_LIST
+//#define OSBIND_CLOBBER_LIST
+//#endif
+
+#ifndef trap_14_wlw
+#define trap_14_wlw(n, a, b)	\
+__extension__	\
+({	\
+	register long retvalue __asm__("d0");	\
+	long  _a = (long) (a);	\
+	short _b = (short) (b);	\
+	\
+	__asm__ volatile (	\
+		"movw	%3,sp@-\n\t"	\
+		"movl	%2,sp@-\n\t"	\
+		"movw	%1,sp@-\n\t"	\
+		"trap	#14\n\t"	\
+		"lea	sp@(8),sp"	\
+		: "=r"(retvalue)	\
+		: "g"(n), "r"(_a), "r"(_b)	\
+	);	\
+	retvalue;	\
+})
+#endif
+#ifndef trap_14_wll
+#define trap_14_wll(n, a, b)	\
+__extension__	\
+({	\
+	register long retvalue __asm__("d0");	\
+	long _a = (long) (a);	\
+	long _b = (long) (b);	\
+	\
+	__asm__ volatile (	\
+		"movl	%3,sp@-\n\t"	\
+		"movl	%2,sp@-\n\t"	\
+		"movw	%1,sp@-\n\t"	\
+		"trap	#14\n\t"	\
+		"lea	sp@(10),sp"	\
+		: "=r"(retvalue)	\
+		: "g"(n), "r"(_a), "r"(_b)	\
+	);	\
+	retvalue;	\
+})
+#endif
+#ifndef trap_14_wlww
+#define trap_14_wlww(n, a, b, c)	\
+__extension__	\
+({	\
+	register long retvalue __asm__("d0");	\
+	long  _a = (long) (a);	\
+	short _b = (short) (b);	\
+	short  _c = (short) (c);	\
+	\
+	__asm__ volatile (	\
+		"movl	%4,sp@-\n\t"	\
+		"movw	%3,sp@-\n\t"	\
+		"movw	%2,sp@-\n\t"	\
+		"movw	%1,sp@-\n\t"	\
+		"trap	#14\n\t"	\
+		"lea	sp@(10),sp"	\
+		: "=r"(retvalue)	\
+		: "g"(n), "r"(_a), "r"(_b), "r"(_c)	\
+	);	\
+	retvalue;	\
+})
+#endif
+#ifndef trap_14_wlwl
+#define trap_14_wlwl(n, a, b, c)	\
+__extension__	\
+({	\
+	register long retvalue __asm__("d0");	\
+	long  _a = (long) (a);	\
+	short _b = (short) (b);	\
+	long  _c = (long) (c);	\
+	\
+	__asm__ volatile (	\
+		"movl	%4,sp@-\n\t"	\
+		"movw	%3,sp@-\n\t"	\
+		"movl	%2,sp@-\n\t"	\
+		"movw	%1,sp@-\n\t"	\
+		"trap	#14\n\t"	\
+		"lea	sp@(12),sp"	\
+		: "=r"(retvalue)	\
+		: "g"(n), "r"(_a), "r"(_b), "r"(_c)	\
+	);	\
+	retvalue;	\
+})
+#endif
+#ifndef trap_14_wlll
+#define trap_14_wlll(n, a, b, c)	\
+__extension__	\
+({	\
+	register long retvalue __asm__("d0");	\
+	long  _a = (long) (a);	\
+	long  _b = (long) (b);	\
+	long  _c = (long) (c);	\
+	\
+	__asm__ volatile (	\
+		"movl	%4,sp@-\n\t"	\
+		"movl	%3,sp@-\n\t"	\
+		"movl	%2,sp@-\n\t"	\
+		"movw	%1,sp@-\n\t"	\
+		"trap	#14\n\t"	\
+		"lea	sp@(14),sp"	\
+		: "=r"(retvalue)	\
+		: "g"(n), "r"(_a), "r"(_b), "r"(_c)	\
+	);	\
+	retvalue;	\
+})
+#endif
+
+#define find_pci_device(id,index) (long)trap_14_wlw((short)(300),(unsigned long)(id),(unsigned short)(index))
+#define find_pci_classcode(classcode,index) (long)trap_14_wlw((short)(301),(unsigned long)(classcode),(unsigned short)(index))
+#define read_config_byte(handle,reg,address) (long)trap_14_wlwl((short)(302),(long)(handle),(unsigned short)(reg),(unsigned char *)(address))
+#define read_config_word(handle,reg,address) (long)trap_14_wlwl((short)(303),(long)(handle),(unsigned short)(reg),(unsigned short *)(address))
+#define read_config_longword(handle,reg,address) (long)trap_14_wlwl((short)(304),(long)(handle),(unsigned short)(reg),(unsigned long *)(address))
+#define fast_read_config_byte(handle,reg) (unsigned char)trap_14_wlw((short)(305),(long)(handle),(unsigned short)(reg))
+#define fast_read_config_word(handle,reg) (unsigned short)trap_14_wlw((short)(306),(long)(handle),(unsigned short)(reg))
+#define fast_read_config_longword(handle,reg) (unsigned long)trap_14_wlw((short)(307),(long)(handle),(unsigned short)(reg))
+#define write_config_byte(handle,reg,data) (long)trap_14_wlww((short)(308),(long)(handle),(unsigned short)(reg),(unsigned short)(data))
+#define write_config_word(handle,reg,data) (long)trap_14_wlww((short)(309),(long)(handle),(unsigned short)(reg),(unsigned short)(data))
+#define write_config_longword(handle,reg,data) (long)trap_14_wlwl((short)(310),(long)(handle),(unsigned short)(reg),(unsigned long)(data))
+#define hook_interrupt(handle,routine,parameter) (long)trap_14_wlll((short)(311),(long)(handle),(unsigned long *)(routine),(unsigned long *)(parameter))
+#define unhook_interrupt(handle) (long)trap_14_wl((short)(312),(long)(handle))
+#define special_cycle(bus_number,special_cycle) (long)trap_14_wwl((short)(313),(unsigned short)(bus_number),(unsigned long)(special_cycle))
+#define get_routing(handle) (long)trap_14_wl((short)(314),(long)(handle))
+#define set_interrupt(handle,mode) (long)trap_14_wlw((short)(315),(long)(handle),(short)(mode))
+#define get_resource(handle) (long)trap_14_wl((short)(316),(long)(handle))
+#define get_card_used(handle,callback) (long)trap_14_wll((short)(317),(long)(handle),(long *)(address))
+#define set_card_used(handle,callback) (long)trap_14_wll((short)(318),(long)(handle),(long *)(callback))
+#define read_mem_byte(handle,offset,address) (long)trap_14_wlll((short)(319),(long)(handle),(unsigned long)(offset),(unsigned char *)(address))
+#define read_mem_word(handle,offset,address) (long)trap_14_wlll((short)(320),(unsigned long)(offset),(unsigned short *)(address))
+#define read_mem_longword(handle,offset,address) (long)trap_14_wlll((short)(321),(unsigned long)(offset),(unsigned long *)(address))
+#define fast_read_mem_byte(handle,offset) (unsigned char)trap_14_wll((short)(322),(long)(handle),(unsigned long)(offset))
+#define fast_read_mem_word(handle,offset) (unsigned short)trap_14_wll((short)(323),(long)(handle),(unsigned long)(offset))
+#define fast_read_mem_longword(handle,offset) (unsigned long)trap_14_wll((short)(324),(long)(handle),(unsigned long)(offset))
+#define write_mem_byte(handle,offset,data) (long)trap_14_wllw((short)(325),(long)(handle),(unsigned long)(offset),(unsigned short)(data))
+#define write_mem_word(handle,offset,data) (long)trap_14_wllw((short)(326),(long)(handle),(unsigned long)(offset),(unsigned short)(data))
+#define write_mem_longword(handle,offset,data) (long)trap_14_wlll((short)(327),(long)(handle),(unsigned long)(offset),(unsigned long)(data))
+#define read_io_byte(handle,offset,address) (long)trap_14_wlll((short)(328),(long)(handle),(unsigned long)(offset),(unsigned char *)(address))
+#define read_io_word(handle,offset,address) (long)trap_14_wlll((short)(329),(long)(handle),(unsigned long)(offset),(unsigned short *)(address))
+#define read_io_longword(handle,offset,address) (long)trap_14_wlll((short)(330),(long)(handle),(unsigned long)(offset),(unsigned long *)(address))
+#define fast_read_io_byte(handle,offset) (unsigned char)trap_14_wll((short)(331),(long)(handle),(unsigned long)(offset))
+#define fast_read_io_word(handle,offset) (unsigned short)trap_14_wll((short)(332),(long)(handle),(unsigned long)(offset))
+#define fast_read_io_longword(handle,offset) (unsigned long)trap_14_wll((short)(333),(long)(handle),(unsigned long)(offset))
+#define write_io_byte(handle,offset,data) (long)trap_14_wllw((short)(334),(long)(handle),(unsigned long)(offset),(unsigned short)(data))
+#define write_io_word(handle,offset,data) (long)trap_14_wllw((short)(335),(long)(handle),(unsigned long)(offset),(unsigned short)(data))
+#define write_io_longword(handle,offset,data) (long)trap_14_wlll((short)(336),(long)(handle),(unsigned long)(offset),(unsigned long)(data))
+#define get_machine_id() (long)trap_14_w((short)(337))
+#define get_pagesize() (long)trap_14_w((short)(338))
+#define virt_to_bus(handle,address,pointer) (long)trap_14_wlll((short)(339),(long)(handle),(unsigned long)(address),(unsigned long *)(pointer))
+#define bus_to_virt(handle,address,pointer) (long)trap_14_wlll((short)(340),(long)(handle),(unsigned long)(address),(unsigned long *)(pointer))
+#define virt_to_phys(address,pointer) (long)trap_14_wll((short)(341),(unsigned long)(address),(unsigned long *)(pointer))
+#define phys_to_virt(address,pointer) (long)trap_14_wll((short)(342),(unsigned long)(address),(unsigned long *)(pointer))
+#define dma_setbuffer(pci_address,local_address,size) (long)trap_14_wlll((short)(350),(unsigned long)(pci_address),(unsigned long)(local_address),(unsigned long)(size))
+#define dma_buffoper(mode) (long)trap_14_ww((short)(351),(short)(mode))
+#define read_mailbox(mailbox,pointer)  (long)trap_14_wwl((short)(352),(short)(mailbox),(unsigned long *)(pointer))
+#define write_mailbox(mailbox,data) (long)trap_14_wwl((short)(353),(short)(mailbox),(unsigned long)(data))
+
+extern long Find_pci_device(unsigned long id, unsigned short index);
+extern long Find_pci_classcode(unsigned long class, unsigned short index);
+extern long Read_config_byte(long handle, unsigned short reg, unsigned char *address);
+extern long Read_config_word(long handle, unsigned short reg, unsigned short *address);
+extern long Read_config_longword(long handle, unsigned short reg, unsigned long *address);
+extern unsigned char Fast_read_config_byte(long handle, unsigned short reg);
+extern unsigned short Fast_read_config_word(long handle, unsigned short reg);
+extern unsigned long Fast_read_config_longword(long handle, unsigned short reg);
+extern long Write_config_byte(long handle, unsigned short reg, unsigned short val);
+extern long Write_config_word(long handle, unsigned short reg, unsigned short val);
+extern long Write_config_longword(long handle, unsigned short reg, unsigned long val);
+extern long Hook_interrupt(long handle, unsigned long *routine, unsigned long *parameter);
+extern long Unhook_interrupt(long handle);
+extern long Special_cycle(unsigned short bus, unsigned long data);
+extern long Get_routing(long handle);
+extern long Set_interrupt(long handle);
+extern long Get_resource(long handle);
+extern long Get_card_used(long handle, unsigned long *address);
+extern long Set_card_used(long handle, unsigned long *callback);
+extern long Read_mem_byte(long handle, unsigned long offset, unsigned char *address);
+extern long Read_mem_word(long handle, unsigned long offset, unsigned short *address);
+extern long Read_mem_longword(long handle, unsigned long offset, unsigned long *address);
+extern unsigned char Fast_read_mem_byte(long handle, unsigned long offset);
+extern unsigned short Fast_read_mem_word(long handle, unsigned long offset);
+extern unsigned long Fast_read_mem_longword(long handle, unsigned long offset);
+extern long Write_mem_byte(long handle, unsigned long offset, unsigned short val);
+extern long Write_mem_word(long handle, unsigned long offset, unsigned short val);
+extern long Write_mem_longword(long handle, unsigned long offset, unsigned long val);
+extern long Read_io_byte(long handle, unsigned long offset, unsigned char *address);
+extern long Read_io_word(long handle, unsigned long offset, unsigned short *address);
+extern long Read_io_longword(long handle, unsigned long offset, unsigned long *address);
+extern unsigned char Fast_read_io_byte(long handle, unsigned long offset);
+extern unsigned short Fast_read_io_word(long handle, unsigned long offset);
+extern unsigned long Fast_read_io_longword(long handle, unsigned long offset);
+extern long Write_io_byte(long handle, unsigned long offset, unsigned short val);
+extern long Write_io_word(long handle, unsigned long offset, unsigned short val);
+extern long Write_io_longword(long handle, unsigned long offset, unsigned long val);
+extern long Get_machine_id(void);
+extern long Get_pagesize(void);
+extern long Virt_to_bus(long handle, unsigned long address, PCI_CONV_ADR *pointer);
+extern long Bus_to_virt(long handle, unsigned long address, PCI_CONV_ADR *pointer);
+extern long Virt_to_phys(unsigned long address, PCI_CONV_ADR *pointer);
+extern long Phys_to_virt(unsigned long address, PCI_CONV_ADR *pointer);
+
+#endif