commit 595201538ba9e880566d35bbd00627fd9efdda30
Author: David Gálvez <dgalvez75@gmail.com>
Date:   Mon Jan 3 08:10:50 2011 +0000

    Moved source_fa into trunk

diff --git a/FireBee/Flash/BaS_15_12_10.S19 b/FireBee/Flash/BaS_15_12_10.S19
new file mode 100644
index 0000000..27a561c
--- /dev/null
+++ b/FireBee/Flash/BaS_15_12_10.S19
@@ -0,0 +1,362 @@
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diff --git a/FireBee/Flash/BaS_15_12_10.zip b/FireBee/Flash/BaS_15_12_10.zip
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diff --git a/FireBee/Flash/emutos2.s19 b/FireBee/Flash/emutos2.s19
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diff --git a/FireBee/MLAB/firebee1/Makefile b/FireBee/MLAB/firebee1/Makefile
new file mode 100644
index 0000000..ed2943c
--- /dev/null
+++ b/FireBee/MLAB/firebee1/Makefile
@@ -0,0 +1,19 @@
+# MPLAB IDE generated this makefile for use with GNU make.
+# Project: firebee1.mcp
+# Date: Sun Oct 04 21:22:09 2009
+
+AS = mpasmwin.exe
+CC = mcc18.exe
+LD = mplink.exe
+AR = mplib.exe
+RM = rm
+
+firebee1.cof : firebee1.o
+	$(LD) "..\MPASM Suite\LKR\18f4520i.lkr" "firebee1.o" /z__MPLAB_BUILD=1 /o"firebee1.cof" /M"firebee1.map" /W
+
+firebee1.o : firebee1.asm ../../../Programme/Microchip/MPASM\ Suite/P18f4520.inc
+	"C:\Programme\Microchip\MPASM Suite\MPASMWIN.exe" /q /p18F4520 "firebee1.asm" /l"firebee1.lst" /e"firebee1.err" /o"firebee1.o"
+
+clean : 
+	$(RM) "firebee1.o" "firebee1.ERR" "firebee1.lst" "firebee1.cof" "firebee1.hex"
+
diff --git a/FireBee/MLAB/firebee1/NMakefile b/FireBee/MLAB/firebee1/NMakefile
new file mode 100644
index 0000000..f0a9e54
--- /dev/null
+++ b/FireBee/MLAB/firebee1/NMakefile
@@ -0,0 +1,19 @@
+# MPLAB IDE generated this makefile for use with Microsoft `nmake'.
+# Project: firebee1.mcp
+# Date: Sun Oct 04 21:22:09 2009
+
+AS = mpasmwin.exe
+CC = mcc18.exe
+LD = mplink.exe
+AR = mplib.exe
+RM = del
+
+"firebee1.cof" : "firebee1.o"
+	$(LD) "..\MPASM Suite\LKR\18f4520i.lkr" "firebee1.o" /z__MPLAB_BUILD=1 /o"firebee1.cof" /M"firebee1.map" /W
+
+"firebee1.o" : "firebee1.asm" "..\..\..\Programme\Microchip\MPASM Suite\P18f4520.inc"
+	"C:\Programme\Microchip\MPASM Suite\MPASMWIN.exe" /q /p18F4520 "firebee1.asm" /l"firebee1.lst" /e"firebee1.err" /o"firebee1.o"
+
+"clean" : 
+	$(RM) "firebee1.o" "firebee1.ERR" "firebee1.lst" "firebee1.cof" "firebee1.hex"
+
diff --git a/FireBee/MLAB/firebee1/PS2Atari_v1_4.asm b/FireBee/MLAB/firebee1/PS2Atari_v1_4.asm
new file mode 100644
index 0000000..ee6c087
--- /dev/null
+++ b/FireBee/MLAB/firebee1/PS2Atari_v1_4.asm
@@ -0,0 +1,619 @@
+;*****************************************************************************
+;                           PS2Atari_v1_4.asm                                *
+;     PS2 PC mouse to Atari / Amiga mouse converter by Tom Kirk March 2010   *
+;			      Version 1.3                                    *
+;*****************************************************************************
+;                                                                            *
+;   Enables a PS2 PC mouse to be used with Atari / Amiga computers using     *
+;     the circuit in circuit.bmp with a PIC16F84(A)/C84 micrcontroller.      *
+;                                                                            *
+;	          Assembled using Microchip MPLAB and MPASM.                 *
+;               Disable case sensitivity under build options.                *
+;                                                                            *
+;*****************************************************************************
+;                           Version 1.4 July 2010                            *
+;                Unused Pin RA4 now correctly set as an imput.		     *
+;            (Pin is tied to +5V on PCB for easier PCB routing.)	     *
+;	     My oversight when transfering from prototype to PCB.	     *
+;                    Thanks to Luciano for informing me.                     *
+;                         						     * 
+;		           Version 1.3 March 2010                            *
+;  Corrected a bug in button routine preventing both buttons being active    *
+;                together under certain conditions.                          *
+;             Thanks to Oliver Fleischmann for informing me.                 *
+;     (Can't believe it taken 6 Years for this bug to show itself!!)         *
+;                                                                            *  
+;                          Version 1.2 June 07                               *	
+;           Changed left/right button outputs to fake open collector.        *
+;   Needed to stop conflits when using a joystick pluged into other port.    *
+;                                                                            *
+;                          Version 1.1 August 04                             *	
+;	                  Added support for Amiga.                           *
+;                                                                            *
+;*****************************************************************************
+
+
+	; list directive to define processor
+	list		p=16F84A
+
+	; processor specific variable definitions
+	#include	<p16F84A.inc>
+
+	; define config bits	
+	__CONFIG _CP_OFF & _WDT_OFF & _PWRTE_ON & _XT_OSC  
+
+	;4 MHz Clock
+ 
+;************************ Input output usage ********************
+
+; RA0 Atari / Amiga select i/p
+; RA1 PS2 mouse data
+; RA2 PS2 mouse clock
+; RA3 Not used
+; RA4 Not used
+
+; RB0 Atari XA / Amiga XA o/p
+; RB1 Atari XB / Amiga YB o/p
+; RB2 Atari YA / Amiga YA o/p
+; RB3 Atari YB / Amiga XB o/p
+; RB4 Left button o/p
+; RB5 Right button o/p
+; RB6 Not used
+; RB7 Not used
+
+;*******************************************************************
+
+
+;********** I/O port equates **************
+
+
+ps2data	equ	1	;ps2 mouse data signal
+ps2clk	equ	2	;ps2 mouse clock signal
+
+
+;********** User register equates *********
+
+temp    equ     0ch     ;Temporary storage
+byte1	equ	0dh	;Byte 1 store
+byte2	equ	0eh	;Byte 2 store
+byte3	equ	0fh	;Byte 3 store
+xinc	equ	010h	;last x increment read
+yinc	equ	011h	;last y increment read
+xlow	equ	012h	;low byte of 16 bit x counter
+xhigh	equ	013h	;high byte of 16 bit x counter
+ylow	equ	014h	;low byte of 16 bit y counter
+yhigh	equ	015h	;high byte of 16 bit y counter
+xpat	equ	016h	;x pattern position
+ypat	equ	017h	;y pattern position
+bcnt    equ     018h    ;bit counter
+brec    equ     019h    ;byte received
+timer	equ	01ah	;timer counter
+parity	equ	01bh	;parity store
+flag	equ	01ch	;flag bits	(bit 0 = ack error flag)
+			;	 	(bit 1 = parity error flag)
+			;	   	(bit 2 = middle button pressed flag)
+			;		(bit 3 = middle state flag)
+			;		(bit 4 = left button flag)
+ 
+;*****************************************************************************************
+
+;***** initialise program *******
+
+reset	clrwdt
+        bcf     status,rp0      ;set page0
+        clrf    intcon          ;disable interupts
+        bsf     status,rp0
+        movlw   084h            ;set tmr0 to int clk,prescale/32
+        movwf   option_reg
+        bcf     status,rp0
+        clrf    porta           ;all porta outputs will be low when enabled
+        movlw   0h		;set mouse buttons and x y start levels
+        movwf   portb
+        bsf     status,rp0
+        movlw   017h            ;set porta bit 3 as an unused output
+        movwf   trisa
+        movlw   030h            ;set portb bit 4 and 5 as inputs (left/right button o/ps open collector)
+        movwf   trisb
+        bcf     status,rp0
+
+        clrf    byte1		;set start up values 
+        clrf    byte2
+        clrf    byte3
+        clrf    xinc
+        clrf    yinc
+        clrf    xlow
+        clrf    xhigh
+        clrf    ylow
+        clrf    yhigh
+        clrf    xpat
+        clrf    ypat
+	clrf	flag
+
+
+;***************** set up ps2 mouse *********************
+
+
+start	call	ps2read		;read power up self test report
+	btfsc	flag,1		;parity error?
+	goto	restart		;yes so jump
+	movlw	0aah		;correct ?
+	subwf	brec,w
+	btfss	status,z
+	goto	restart		;no so jump	
+	
+	call	ps2read		;read power up pc mouse id
+	btfsc	flag,1		;parity error?
+	goto	restart		;yes so jump
+	movlw	0h		;correct ?
+	subwf	brec,w
+	btfss	status,z
+	goto	restart		;no so jump	
+	
+restart	movlw	0ffh		;send reset pc mouse command
+	call	ps2wri
+	btfsc	flag,0		;ack bit?
+	goto	restart		;no so jump
+	
+	call	ps2read		;ack returned
+	btfsc	flag,1		;parity error?
+	goto	restart		;yes so jump
+	movlw	0fah		;correct ?
+	subwf	brec,w
+	btfss	status,z
+	goto	restart		;no so jump	
+	
+	call	ps2read		;read self test report
+	btfsc	flag,1		;parity error?
+	goto	restart		;yes so jump
+	movlw	0aah		;correct ?
+	subwf	brec,w
+	btfss	status,z
+	goto	restart		;no so jump	
+	
+	call	ps2read		;read pc mouse id
+	btfsc	flag,1		;parity error?
+	goto	restart		;yes so jump
+	movlw	0h		;correct ?
+	subwf	brec,w
+	btfss	status,z
+	goto	restart		;no so jump	
+
+	movlw	0f4h		;send enable reporting command
+	call	ps2wri
+	btfsc	flag,0		;ack bit?
+	goto	restart		;no so jump
+	
+	call	ps2read		;ack returned
+	btfsc	flag,1		;parity error?
+	goto	restart		;yes so jump
+	movlw	0fah		;correct ?
+	subwf	brec,w
+	btfss	status,z
+	goto	restart	
+
+	movlw	0f3h		;send set sample rate command
+	call	ps2wri
+	btfsc	flag,0		;ack bit?
+	goto	restart		;no so jump
+	
+	call	ps2read		;ack returned
+	btfsc	flag,1		;parity error?
+	goto	restart		;yes so jump
+	movlw	0fah		;correct ?
+	subwf	brec,w
+	btfss	status,z
+	goto	restart	
+
+	movlw	028h		;send sample rate (40)
+	call	ps2wri
+	btfsc	flag,0		;ack bit?
+	goto	restart		;no so jump
+	
+	call	ps2read		;ack returned
+	btfsc	flag,1		;parity error?
+	goto	restart		;yes so jump
+	movlw	0fah		;correct ?
+	subwf	brec,w
+	btfss	status,z
+	goto	restart	
+
+;******************* Main program loop ****************************
+
+main	call    ps2read         ;read 3 byte pc mouse packet
+	btfsc	flag,1		;parity error?
+	goto	restart		;yes so jump
+	movf    brec,w
+        movwf   byte1
+        call    ps2read
+	btfsc	flag,1		;parity error?
+	goto	restart		;yes so jump
+        movf    brec,w
+        movwf   byte2
+        call    ps2read
+	btfsc	flag,1		;parity error?
+	goto	restart		;yes so jump
+        movf    brec,w
+        movwf   byte3
+
+;adjust the 16 bit x counter
+
+	clrf	temp		;use temp as high byte		
+	btfsc	byte1,4		;extend sign bit into high byte
+	decf	temp,f
+		
+	movf	byte2,w		;add low bytes
+	addwf	xlow,f
+	btfsc	status,c	;add carry to high
+	incf	xhigh,f
+	movf	temp,w		;add high bytes
+	addwf	xhigh,f	
+
+;adjust the 16 bit y counter
+
+	clrf	temp		;use temp as high byte		
+	btfsc	byte1,5		;extend sign bit into high byte
+	decf	temp,f
+		
+	movf	byte3,w		;add low bytes
+	addwf	ylow,f
+	btfsc	status,c	;add carry to high
+	incf	yhigh,f
+	movf	temp,w		;add high bytes
+	addwf	yhigh,f
+
+;left button
+
+	btfss	byte1,0		;is the left pc mouse button pressed
+	goto	lbutt		;no so jump
+	bsf	flag,4		;set left button flag
+	goto	nbutt
+lbutt	bcf	flag,4		;reset left button flag
+
+;right button
+
+nbutt	btfss	byte1,1		;is the right pc mouse button pressed
+	goto	rbutt		;no so jump
+	bcf	portb,5		;set right button as pressed
+	bsf	status,rp0	;by setting pin as a low output
+	bcf	trisb,5		
+	bcf	status,rp0	
+        goto    mbut
+rbutt	bsf	status,rp0	;set right button as not pressed
+	bsf	trisb,5		;by setting pin as an input
+	bcf	status,rp0	
+
+;middle button
+
+mbut	btfss	byte1,2		;check if middle button pressed		 
+	goto	mbutt		;jump if not
+	btfsc	flag,2		;check middle button pressed flag
+	goto	mbex		;set so jump
+	movlw	08h		;toggle middle state flag
+	xorwf	flag,f
+	bsf	flag,2		;set middle button pressed flag
+	goto	mbex	
+
+mbutt	btfss	flag,2
+	goto	mbex
+	bcf	flag,2		;reset middle button pressed flag
+mbex
+
+	btfsc	flag,3		;check middle state flag 
+	goto	setlb		;jump if set
+	btfsc	flag,4		;check left button flag
+	goto	setlb		;jump if set
+	bsf	status,rp0	;no flags set so set left buuton not pressed
+        bsf	trisb,4		;by setting pin as an input
+	bcf	status,rp0	
+	goto    main
+setlb	bcf	portb,4		;set left button pressed
+	bsf	status,rp0	;by setting pin as a low output
+	bcf	trisb,4
+	bcf	status,rp0	
+	goto	main
+
+
+;***************************** Subs *****************************************
+
+;***** Read a byte from the ps2 mouse ******
+
+ps2read btfss   porta,ps2data   ;data low ?
+        goto    ps2r1           ;yes so start reading data
+        call    trans           ;no so do emulated mouse move
+        clrf    tmr0            ;clear rtcc before delay
+
+oned    btfss   porta,ps2data   ;data low ?
+        goto    ps2r1           ;yes so start reading data
+        movlw   0dh             ;delay between emulated mouse moves
+        subwf   tmr0,w
+        btfss   status,z
+        goto    oned            ;not done so jump
+        goto    ps2read         ;check again
+
+ps2r1	call	wlow		;wait until clock goes low for start bit
+	
+	call	whigh		;wait until clock is high		
+
+	movlw	08h		;read 8 data bits
+	movwf	bcnt
+	clrf	parity		;clear parity counter
+
+ps2r2   call	wlow		;wait until clock is low
+	bcf	status,c	;clear carry flag
+	btfss   porta,ps2data   ;data bit set ?
+        goto	ps2r3		;no so jump
+	incf	parity,f	;yes so inc the parity counter
+	bsf	status,c	;set carry bit
+ps2r3	rrf	brec,f          ;shift carry into destination
+
+        call    whigh           ;wait until clock is high
+	
+        decfsz  bcnt,f          ;finished the 8 bits?
+        goto    ps2r2           ;no so do again
+
+	call	wlow		;for the parity bit
+	btfsc   porta,ps2data   ;parity bit set?
+        incf	parity,f	;yes so inc the parity counter	
+	bcf	flag,1		;clear flag (no error)
+	btfss	parity,0	;check calculated parity
+	bsf	flag,1		;set flag (parity error!)
+	call	whigh
+	
+	call	wlow		;for the stop bit
+	call	whigh
+
+        return			;and exit
+	
+;***** Write a byte to the ps2 mouse ******
+
+ps2wri	movwf	brec		;speed not important at this point so 
+	movwf	temp		;calculate parity seperate for sake of
+	movlw	08h		;clarity
+	movwf	bcnt
+	clrf	parity
+ps2w1	rrf	temp,f		;shift bit into carry
+	movlw	01h		;preset for bit set
+	btfss	status,c	;test carry
+	clrw			;bit zero so no addition
+	addwf	parity,f	;update parity
+	decfsz	bcnt,f		;any more bits to do?
+	goto	ps2w1		;yes so jump
+	comf	parity,f	;only intrested in bit 0.
+				;parity bit is complement of bit 0
+
+	movlw	08h		;bit count to 8
+	movwf	bcnt
+
+	call	clkl		;set clock low
+	
+	movlw	021h		;wait 100 uS
+	movwf	temp
+ps2ww	decfsz	temp,f
+	goto	ps2ww	
+
+	call	datl		;set data low
+	nop			;wait 5 uS
+	nop
+	nop
+	nop
+	nop
+	call	clkh		;set clock high
+		
+ps2w2	call	wlow		;wait for clock to go low
+	rrf	brec,f		;rotate bit into carry for testing
+	btfss	status,c
+	goto	ps2w3		;jump if bit is low
+	call	dath		;set data high
+	goto	ps2w4
+ps2w3	call	datl		;set data low
+ps2w4	call	whigh		;wait for clock to go high
+
+	decfsz	bcnt,f		;any more bits to send?
+	goto	ps2w2		;yes so jump	
+	
+	call	wlow		;wait for clock to go low
+	btfss	parity,0	;send parity bit
+	goto	ps2w5
+	call	dath
+	goto	ps2w6
+ps2w5	call	datl
+ps2w6	call	whigh
+	
+	call	wlow		;send stop bit
+	call	dath
+	call	whigh	
+
+	call	wlow		;read ack from mouse
+	bcf	flag,0
+	btfsc	porta,ps2data
+	bsf	flag,0
+	call	whigh
+
+	return
+
+
+;******* wait for ps2 clock to go low **********
+
+wlow	btfsc	porta,ps2clk
+	goto	wlow
+	return		
+
+
+;******* wait for ps2 clock to go high **********
+
+whigh	btfss	porta,ps2clk
+	goto	whigh
+	return		
+
+
+;******* set ps2 clock low *********************
+
+clkl	bsf	status,rp0
+	bcf	trisa,ps2clk
+	bcf	status,rp0
+	return
+
+
+;******* set ps2 clock high ********************
+
+clkh	bsf	status,rp0
+	bsf	trisa,ps2clk
+	bcf	status,rp0
+	return
+
+
+;******* set ps2 data low *********************
+
+datl	bsf	status,rp0
+	bcf	trisa,ps2data
+	bcf	status,rp0
+	return
+
+
+;******* set ps2 data high *********************
+
+dath	bsf	status,rp0
+	bsf	trisa,ps2data
+	bcf	status,rp0
+	return
+
+
+
+;********* emulate mouse move ***************************
+
+;move the emulated mouse by one step in the x direction if needed  
+
+trans   movf    xlow,w          ;is the x counter zero?
+	iorwf	xhigh,w
+	btfsc	status,z
+	goto	ymove		;no so jump to y direction
+	
+	btfsc	xhigh,7		;is the x counter positive or negative?
+	goto	xneg		;jump if negative
+	
+	incf	xpat,f		;increment the pattern list position
+	movlw	04h		;test if end of pattern list
+	subwf	xpat,w
+	btfsc	status,z
+	clrf	xpat		;end of pattern list so reset
+	movlw	0ffh		;subtract 1 from the 16 bit counter by adding ffffh
+	addwf	xlow,f
+	btfsc	status,c	;add carry to high byte
+	incf	xhigh,f			 
+	addwf	xhigh,f
+	goto	ymove		;exit to y direction
+
+xneg	decf	xpat,f		;decrement the pattern list position
+	movlw	0ffh		;test if end of pattern list
+	subwf	xpat,w
+	btfss	status,z
+	goto	xno	
+	movlw	03h		;end of pattern list so reset
+	movwf	xpat
+xno	movlw	01h		;add 1 to the 16 bit counter
+	addwf	xlow,f
+	btfsc	status,c	;add carry to high byte
+	incf	xhigh,f			 
+
+;move the emulated mouse by one step in the y direction if needed  
+	
+ymove	movf	ylow,w		;is the y counter zero? 
+	iorwf	yhigh,w
+	btfsc	status,z
+	goto	out		;no so jump to output pattern
+	
+	btfsc	yhigh,7		;is the y counter positive or negative?
+	goto	yneg		;jump if negative
+	
+        incf    ypat,f          ;increment the pattern list position
+	movlw	04h		;test if end of pattern list
+	subwf	ypat,w
+	btfsc	status,z
+	clrf	ypat		;end of pattern list so reset
+	movlw   0ffh            ;subtract 1 from the 16 bit counter by adding ffffh
+	addwf	ylow,f
+	btfsc	status,c	;add carry to high byte
+	incf	yhigh,f			 
+	addwf	yhigh,f
+	goto	out		;exit to output pattern
+
+yneg    decf    ypat,f          ;decrement the pattern list position
+	movlw	0ffh		;test if end of pattern list
+	subwf	ypat,w
+	btfss	status,z
+	goto	yno
+	movlw	03h		;end of pattern list so reset
+        movwf	ypat
+yno	movlw   01h             ;add 1 to the 16 bit counter
+	addwf	ylow,f
+	btfsc	status,c	;add carry to high byte
+	incf	yhigh,f		
+
+;output new x and y patterns 	
+
+out	btfsc	porta,0		;test if set for atari
+	goto	amiga
+
+	movf	xpat,w		;get the x pattern bits
+	bsf	pclath,1	;set page 2
+	call	pattx
+	movwf	temp		;store the pattern in temp
+	movf	ypat,w		;get the y pattern bits
+	call	patty
+	clrf	pclath		;set page 0
+	iorwf	temp,f		;store the pattern in temp
+	
+	goto	outpat
+
+amiga	movf	xpat,w		;get the x pattern bits
+	bsf	pclath,1	;set page 2
+	call	apatx
+	movwf	temp		;store the pattern in temp
+	movf	ypat,w		;get the y pattern bits
+	call	apaty
+	clrf	pclath		;set page 0
+	iorwf	temp,f		;store the pattern in temp
+	
+outpat	movf	temp,w		;get patterns
+        andlw   0fh             ;ensure high nibble stays zero
+	movwf	portb		;ouput patterns
+
+	
+	return
+
+
+;*************** pattern lists **************
+
+	org	0200h
+
+;atari patterns
+pattx	addwf	pcl,f
+	retlw	0
+	retlw	1
+	retlw	3
+	retlw	2
+
+patty	addwf	pcl,f
+        retlw   0
+        retlw   4
+        retlw   0ch
+        retlw   8
+	
+;amiga patterns
+apatx	addwf	pcl,f
+	retlw	0
+	retlw	1
+	retlw	9
+	retlw	8
+
+apaty	addwf	pcl,f
+        retlw   0
+        retlw   4
+        retlw   6
+        retlw   2
+
+;*******************************************************************************
+
+	END
+
+
diff --git a/FireBee/MLAB/firebee1/Thumbs.db b/FireBee/MLAB/firebee1/Thumbs.db
new file mode 100644
index 0000000..5c84dfb
Binary files /dev/null and b/FireBee/MLAB/firebee1/Thumbs.db differ
diff --git a/FireBee/MLAB/firebee1/circuit.bmp b/FireBee/MLAB/firebee1/circuit.bmp
new file mode 100644
index 0000000..10c587c
Binary files /dev/null and b/FireBee/MLAB/firebee1/circuit.bmp differ
diff --git a/FireBee/MLAB/firebee1/firebee1.asm b/FireBee/MLAB/firebee1/firebee1.asm
new file mode 100644
index 0000000..cc1d11a
--- /dev/null
+++ b/FireBee/MLAB/firebee1/firebee1.asm
@@ -0,0 +1,845 @@
+;**********************************************************
+;*  firebee1 PIC18F4321 MAIN FILE
+;**********************************************************
+;*  CREATED BY FREDI ASCHWANDEN
+;*  DATE 22.9.2009
+;**********************************************************
+	list PE=18f4520				;EXTENDED INSTRUCTION SET
+	include "P18f4520.inc"
+;------------------------ Equates --------------------------;
+;Register addresses
+;BANK 0
+SECS           		equ    	0x00
+SECS_ALARM			EQU		0x01
+MINS         		equ    	0x02
+MINS_ALRAM			EQU		0x03
+HOURS           	equ    	0x04
+HOURS_ALARM			EQU		0x05
+DAY_OF_WEEK			EQU		0x06
+DAYS				EQU		0x07
+MONTHS				EQU		0x08
+YEARS				EQU		0x09		;offset vom 1968
+REGA				EQU		0x0A
+REGB				EQU		0x0B
+REGC				EQU		0x0C
+REGD				EQU		0x0D
+RTC_RAM				EQU		0x0E		; bis 0x3F
+free				equ		0x40
+TICKS           	equ    	0x41		;125MS
+TASTE_ON_TIME		EQU		0x42
+TASTE_OFF_TIME		EQU		0x43
+POWER_ON_TIME		EQU		0x44
+AD_KANAL			EQU		0x45
+U_ERR				EQU		0x46		;SPANNUNGSFEHLER WENN BIT 0=1, BIT1=1 WARTEN AUF GELADEN
+U_ERR_TIME			EQU		0x47		;ZEIT SEIT SPANNUNGSFEHLER
+U_POWER_IN			EQU		0x48		;SPANNUNG POWER IN 1V CA. 6E
+RX_B				EQU		0x49		;RECEIVED BYT
+RX_STATUS			EQU		0x4A		;STATUS: 0x00=WAIT AUF MCF COMMANDO, 0x82=EMPFANGE 64BYT FROM RTC
+TX_STATUS			EQU		0x4B		;STATUS: 0x00=WAIT 0x81=SENDE 64BYT FROM RTC
+GO_SUB				EQU		0x4C		;WENN GLEICH 0xFB DANN SUBROUTINE AUSFÜHREN
+GO_INT				EQU		0x4D		;WENN GLEICH 0xFB DANN SUBROUTINE AUSFÜHREN
+EAPIR1				EQU		0x4E		;INTERRUPT ACTIV UND ENABLE
+EAPIR2				EQU		0x4F		;INTERRUPT ACTIV UND ENABLE
+;BANK 1 AB 0x100
+RX_BUFFER			EQU		0x100		;0x80 BYT BUFFER BIS 0x17F BANK
+TX_BUFFER			EQU		0x180		;0X80 BYT BUFFER BIS 0x1FF BANK
+
+;--------------------------------------------------------------
+SEND_RTC_TIME		EQU		.2			;0.25 SEC (EINHEIT IST EIN TICK = 128MS
+RESET_ON_TIME		EQU		.2			;0.25 SEC (EINHEIT IST EIN TICK = 128MS
+RESET_OFF_TIME		EQU		.4			;0.5 SEC (EINHEIT IST EIN TICK = 128MS
+OFF_TIME			EQU		.20			;2.5 SEC (EINHEIT IST EIN TICK = 128MS
+ON_TIME				EQU		.2			;0.25 SEC (EINHEIT IST EIN TICK = 128MS
+TIMER_HB			EQU		.240		;256- (32768Hz PRO 1/8SEC = 4096TICKS/256) => 256-16=240 (resp 256-16/4 (wenn osco) = 252)
+TIME_MAX			EQU		.160		;MAXIMALTIME
+U_ERR_PW_AUS		EQU		.5			;5 SEC
+;SERIEL
+SYNC1				EQU		0FFh
+SYNC1_DATA			EQU		'A';
+SYNC2				EQU		0FEh
+SYNC2_DATA			EQU		'C';
+SYNC3				EQU		0FDh	
+SYNC3_DATA			EQU		'P';
+SYNC4				EQU		0FCh
+SYNC4_DATA			EQU		'F';
+REQ_RTCD_FROM_PIC	EQU		01h			;RTC AND NVRAM DATEN VOM PIC ANFORDERN
+RTCD_FROM_PIC		EQU		81h			;RTC AND NVRAM DATEN HEADER UND STATUS
+REQ_RTCD_FROM_MCF	EQU		02h			;RTC AND NVRAM DATEN VOM MCF ANFORDERN
+RTCD_FROM_MCF		EQU		82h			;RTC AND NVRAM DATEN HEADER UND STATUS
+U_MIN_TO_MCF		EQU		03h			;UNTERSPANNUNGSMITTEILUNG AN PROCESSOR
+EXT_SUB_GO			EQU		04h			;SERIELL CODE UM SUBROUTINEN/INTERRUPTS ZU AKTIVIEREN
+EXT_SUB_STOP		EQU		05h			;SERIELL CODE UM SUBROUTINEN/INTERRUPTS ZU STOPPEN
+CLK_SLEEP	   		EQU		B'00010010'		;125kHz intern, SLEEP MODE
+CLK_ACTIV	   		EQU		B'01110010'		;inTernal CLK=8MHz, SLEEP MODE, SLEEP MODE
+EXT_CODE			EQU		0xFB		;CODE FÜR EXTERNE SUBROUTINEN/INTERRUPTS AUSFÜHREN (FireBee!)
+EXTERN_INT_ADR		EQU		0x2000		;HIER MUSS 0xFB STEHEN WENN EXTERNE INTERRUPTS AUSFÜHRBAR
+EXTERN_INTERRUPTS	EQU		0x2002		;STARTPUNKT EXTERNE SUBROUTINES
+EXTERN_SUB_ADR		EQU		0x2010		;HIER MUSS 0xFB STEHEN WENN EXTERNE SUBROUTINES AUSFÜHRBAR
+EXTERN_SUBROUTINES	EQU		0x2012		;STARTPUNKT EXTERNE SUBROUTINES
+REQ_BLOCK			EQU		0xA0		;BLOCK DATEN LESEN -> CODE UND 3 BYTS ADRESSE = TOTAL 4 BYTES
+READ_BLOCK			EQU		0xA1		;PROGRAMM BLOCK PIC->MCF -> CODE, 3 BYTS ADRESSE UND 64 BYTS DATEN = TOTAL 68 BYTES
+WRITE_BLOCK			EQU		0xA2		;PROGRAMM BLOCK MCF->PIC -> CODE, 3 BYTS ADRESSE UND 64 BYTS DATEN = TOTAL 68 BYTES
+PRG_OK_PIC			EQU		0x22		;PROGRAMMIERUNG BLOCK FERTIG
+;**********************************************************************************************"""""""""""""
+; Start at the reset vector
+Reset_Vector code 0x000 
+	BRA 	KALT_START
+;--------------------------------------------------------------
+HIGH_INT_VEC code 	0x0008
+ 	GOTO	0x18
+	
+LOW_INT_VEC	code 	0x0018
+INT_HANDLER
+	CLRF	BSR					;IMMER ACCESS BANK
+;SETZEN GRUPPE 1
+	MOVFF	PIE1,EAPIR1			;INTERRUPTS HOLEN
+	MOVF	PIR1,0				;MASKE
+	ANDWF	EAPIR1				;ACTIVE SETZEN
+	BTFSC	EAPIR1,TMR1IF 		;uhr interrupt?
+	BRA		RTC_ISR				;ja->
+	BTFSC	EAPIR1,ADIF			;AD INTERRUTP?
+	BRA		AD_ISR				;JA->
+ 	BTFSC	EAPIR1,TXIF			;seriell TX?
+ 	BRA		TX_ISR				;JA->
+ 	BTFSC	EAPIR1,RCIF			;seriell RX?
+ 	BRA		RX_ISR				;JA->
+
+;SETZEN GRUPPE 2
+	MOVFF	PIE2,EAPIR2			;INTERRUPTS HOLEN
+	MOVF	PIR2,0				;MASKE
+	ANDWF	EAPIR2				;ACTIVE SETZEN
+
+ 	BTFSC	EAPIR2,HLVDIF		;UNDER/OVERVOLTAGE DETECT
+ 	BRA		HLVD_ISR			;JA->
+	RETFIE
+
+;TESTEN UND SETZEN GRUPPE 1
+	MOVFF	PIE1,EAPIR1			;INTERRUPTS HOLEN
+	MOVF	PIR1,0				;MASKE
+	ANDWF	EAPIR1				;ACTIVE SETZEN
+	TSTFSZ	EAPIR1
+	BRA		INT_HANDLER
+;TESTEN UND SETZEN GRUPPE 2
+	MOVFF	PIE2,EAPIR2			;INTERRUPTS HOLEN
+	MOVF	PIR2,0				;MASKE
+	ANDWF	EAPIR2				;ACTIVE SETZEN
+	TSTFSZ	EAPIR2
+	BRA		INT_HANDLER
+
+	MOVLW	EXT_CODE			;GO EXTERNE SUBROUTINEN AKTIV?
+	CPFSEQ	GO_INT				;SKIP WENN JA
+	RETFIE
+	GOTO	EXTERN_INTERRUPTS	;REGISTER SICHERN UND STARTEN
+;**********************************************************************************************"""""""""""""
+	; Start application beyond vector area
+	CODE	0x0100
+KALT_START
+;RESET MODE
+	CLRF	BSR					;BANK 0
+;ALLE INT AUS UND RÜCKSETZEN
+	CLRF	INTCON				;alle INTERRUPT AUS
+	CLRF	RCON				;INT PRIORITY AUS
+	CLRF	PIE1				;MASK DISABLE
+	CLRF	PIE2
+	CLRF	PIR1				;INT ACT AUS
+	CLRF	PIR2
+	CLRF	IPR1				;LOW PRIORITY
+	CLRF	IPR2
+	; clock 
+; 	MOVLW	B'01000000'			;32MHZ
+; 	MOVWF	OSCTUNE
+	CLRF	OSCTUNE
+;CLOCK
+   	MOVLW	CLK_ACTIV
+   	MOVWF	OSCCON
+	; div init
+;SET PORT A: **7:#master/0.409*5V0 **6:PIC_AMKB_RX **5:PIC_SWTICH **4:HIGH_CHARGE_CURRENT **3:2V5 *2:3V3/2 **1:1V25 **0:POWER_IN/11
+	CLRF	PORTA				;#master(7)=0, REST=0
+	MOVLW	B'11111111'			;DIRECTION: alles auf Input 
+	MOVWF	TRISA
+;SET PORT B: **7:PGD **6:PGC **5:PGM **4:PIN_INT,1V5 **3:GAME PORT PIN10 **2:GAME PORT PIN11 **1:GAME PORT PIN6 **0: GAME PORT PIN5
+	CLRF	PORTB				;ALLES AUF 0
+	MOVWF	TRISB
+;SET PORT C: **7: PIC_RX **6:PIC_TX **5:AMKB_TX **4:GAME PORT PIN4 **3:GAME PORT PIN12 **2:GAME PORT PIN13 **1+0: OCS 32K768Hz
+	CLRF	PORTC
+	MOVWF	TRISC
+;SET PORT D: **7:#RSTI **6:GAME PORT PIN3 **5:PS2 KB CLK **4:PS2 MS CLK **3:PS2 KB DATA **2:MS DATA **1:TASTER **0:POWER ON/OFF (0=ON)
+; SET TASTE UND POWER
+	CLRF	PORTD				;ALLES AUF 0
+	MOVWF	TRISD				;ALLES AUF INPUT
+;SET PORT E: **3:#MCLR **2:#PCI_RESET **1:PCI 3V3 **0:PIC LED (0=ON)
+	MOVLW	B'00000001'			;LED OFF
+	CLRF	PORTE				;ALLES AUF 0
+	MOVWF	TRISE				;ALLES AUF INPUT
+;--------------------------
+;  set OVERvoltage detekt 
+	MOVLW	B'10011011'			;INT WENN ÜBER 3.9V
+	MOVWF	HLVDCON	
+	MOVLW	B'00000011'			;ERRORS ON, WAIT AUF LADEN
+	MOVWF	U_ERR
+	MOVLW	.20					;SEIT 20SEC ERROR 			 
+	MOVWF	U_ERR_TIME			;SETZEN
+ 	BSF 	PIE2,HLVDIE 		;Enable interrupt
+;INTIALISIERUNGSPROGAMME
+	CALL	LADESTROM			;LADESTROM EINSTELLEN
+;UHR initialisieren
+	MOVLW 	TIMER_HB			;Preload TMR1 register 
+	MOVWF 	TMR1H 				;
+	CLRF 	TMR1L				;=0
+	MOVLW	B'00001111'			; 8 BIT, osc1 enable, TIMER MODE, TIMMER ENABLE
+	MOVWF 	T1CON 				; SET
+	CLRF	TICKS				; 1/8 sec register
+	CLRF 	SECS				; Initialize timekeeping registers
+	CLRF 	MINS 				;
+	MOVLW	.12
+	MOVWF 	HOURS
+	MOVLW	.1
+	MOVWF	DAY_OF_WEEK
+	MOVLW	.1
+	MOVWF	DAYS
+	MOVLW	.8
+	MOVWF	MONTHS
+	MOVLW	.42
+	MOVWF	YEARS				;MONTAG 19.7.2010 12:00:00 (JAHR-1968)
+	CLRF	TASTE_ON_TIME
+	CLRF	TASTE_OFF_TIME
+	CLRF	POWER_ON_TIME
+	BSF 	PIE1,TMR1IE 		;Enable Timer1 interrupt
+;AD WANDLER INITIALISIEREN
+	CLRF	AD_KANAL			;BEI 0 BEGINNEN
+	CLRF	ADCON0				;AD MOUDUL AUS
+	MOVLW	B'00001001'			;VREF=VDD,ANALOG INPUT AN0-AN5
+	MOVWF	ADCON1
+	MOVLW	B'00000000'			;LINKSSBÜNDIG,0 TAD,CLOCK=Fosc/2
+	MOVWF	ADCON2
+; 	BSF		PIE1,ADIE			;INTERRUPT ENABLE
+	CLRF	U_POWER_IN			;WERT AUF 0 VOLT
+; seriell initialisieren
+	CLRF	SPBRGH
+	MOVLW	.16
+	MOVWF	SPBRG				;BAUDE RATE = 115K
+	MOVLW	B'00000100'			;TX AUS, ASYNC HIGH SPEED
+ 	MOVWF	TXSTA
+	MOVLW	B'10010000'			;SERIEL EIN,RX EIN,
+ 	MOVWF	RCSTA
+	MOVLW	B'00001000'			;16BIT BRG, RISING EDGE INTERRUPT
+ 	MOVWF	BAUDCON				;SETZEN
+;EXTERNER SUBROUTINES
+	CLRF	GO_SUB
+; interrupts
+	CLRF	INTCON3				;EXTER INTERRUPT AUS, low priority
+	MOVLW	B'11110000'			;PORT B PULLUPS AUS, EXT INT ON RISING EDGE, TMR0 AND BPIP Low priority
+	MOVWF	INTCON2
+	MOVLW	B'11000000'			;global on, PERIPHERAL INT on
+ 	MOVWF	INTCON
+;CLOCK
+   	MOVLW	CLK_SLEEP			;GEHT JETZT IN SLEEP MODE
+   	MOVWF	OSCCON
+;-------------------------------------------------------------------------
+;---------------------------- MAIN LOOP -------------------------------------------------
+;-------------------------------------------------------------------------
+MAIN						
+	MOVLW	EXT_CODE			;GO EXTERNE SUBROUTINEN AKTIV?
+	CPFSEQ	GO_SUB				;SKIP WENN JA
+	BRA		WARTEN				;SONST WARTEN
+	CALL	MAIN2,1				;REGISTER SICHERN UND STARTEN
+WARTEN
+	BTFSC	TRISD,RD0			;SKIP IF POWER ON
+ 	SLEEP						;SLEPP BIS ZUM NÄCHSTEN INTERRUPT
+	BRA	MAIN
+MAIN2
+	CALL	EXTERN_SUBROUTINES	;EXTERNE SUBROUTINEN AUSFÜHREN AN STELLE 0 MUSS 0xFA STEHEN SONST UNGÜLTIG
+	RETURN	1					;RETURN MIT REGISTER ZURÜCK
+;**********************************************************************************************"""""""""""""
+;--------------------------- subroutines -------------------------------------------------
+;**********************************************************************************************"""""""""""""
+;POWER ON/OFF 
+POWER_EIN
+;CLOCK
+   	MOVLW	CLK_ACTIV
+   	MOVWF	OSCCON
+
+	BCF		TRISA,RA7			;CLOCK EINSCHALTEN
+	BCF		TRISD,RD7			;#RSTI AKTIVIEREN = LOW
+	BCF		TRISB,RB4			;PIC_INT AKTIVIEREN
+	BCF		TRISD,RD0			;POWER ON
+	BRA		LS_ON_POWER			;LADESTROM EINSTELLEN
+POWER_AUS
+;CLOCK
+   	MOVLW	CLK_SLEEP
+   	MOVWF	OSCCON
+
+	BSF		TRISD,RD0			;POWER OFF
+	BSF		TRISD,RD7			;#RSTI DEAKTIVIEREN
+	BSF		TRISB,RB4			;PIC INT DEAKTIVIEREN
+	BSF		TRISA,RA7			;CLOCK DEAKTIVIEREN
+	CLRF	POWER_ON_TIME		;RÜCKSETZEN
+	BRA		LS_OFF_POWER		;LADESTROM EINSTELLEN
+;LADESTROM EINSTELLEN ----------------------------
+LADESTROM
+	BTFSC	TRISD,RD0			; ONPOWER?
+	BRA		LS_OFF_POWER		; NEIN->
+LS_ON_POWER						;GROSSER LADESTROM 5A
+	BCF		TRISA,RA4			;10K ON
+	RETURN
+LS_OFF_POWER					;KLEINER LADESTROM_MIN 1.85A
+	BSF		TRISA,RA4			;10K OFF
+	RETURN
+;---------------------------------------------------
+;SERIELL AUS/EIN
+SERIAL_OFF
+	BCF		TXSTA,TXEN			;TX AUS
+	BCF 	PIE1,RCIE 			;DISABLE RX interrupt
+	BCF 	PIR1,RCIF 			;CLEAR RX interrupt
+	BCF 	PIE1,TXIE			;DISABLE TX interrupt
+	BCF 	PIR1,TXIF			;CLEAR TX interrupt
+	RETURN
+SERIAL_ON
+	BTFSC	TXSTA,TXEN			;SCHON EIN?
+	RETURN						;JA->
+	BSF		TXSTA,TXEN			;TX EIN
+	MOVLW	SYNC1
+	MOVWF	RX_STATUS			;AUF SYNC WARTEN
+	CLRF	TX_STATUS
+	MOVFF	RCREG,RX_B			;RCREG LEEREN
+	MOVFF	RCREG,RX_B			;RCREG LEEREN
+	BCF 	PIR1,TXIF			;CLEAR TX interrupt
+	BCF		PIR1,RCIF			;INTERRUPT RX FLAG LÖSCHEN
+	BSF 	PIE1,RCIE 			;ENABLE RX interrupt
+	NOP
+	RETURN
+;---------------------------------------------------------------------
+; TASTENDRUCK
+TASTE
+	BTFSS	PORTD,RD1			;TASTE GEDRÜCKT?
+	BRA		TG_JA				;->JA
+;TASTE NICHT GEDRÜCKT ODER LOSGELASSEN
+	CLRF	TASTE_ON_TIME		;RÜCKSETZEN
+
+	MOVLW	TIME_MAX			;MAX
+	CPFSGT	TASTE_OFF_TIME		;LÄNGER?
+	INCF	TASTE_OFF_TIME		;NEIN ERHÖHEN
+
+	MOVLW	RESET_OFF_TIME		;2SEC
+	CPFSGT	POWER_ON_TIME		;LÄNGER?
+	RETURN						;NEIN->
+;RESET AUFHEBEN
+	BSF		TRISD,RD7			;JA -> #RSTI DEAKTIVIEREN =HIGH
+	CALL	SERIAL_ON			;SERIELL EINSCHALTEN
+	RETURN
+;TASTE GEDRÜCKT
+TG_JA
+	MOVLW	OFF_TIME+1
+	CPFSLT	TASTE_ON_TIME		;KÜRZER ALS ONTIME+1
+	RETURN						;NEIN->FERTIG
+	BTFSC	TRISD,RD0			;ONPOWER?
+	BRA		TG_OFF_POWER		;NEIN->
+TG_ON_POWER
+	MOVLW	SEND_RTC_TIME		;ZEIT FÜR RTC REQ FROM MCF HOLEN?
+	CPFSEQ	TASTE_ON_TIME		;TEST
+	BRA		TG_ON_POWER2		;NEIN->
+SEND_RTC_REG
+	MOVLW	REQ_RTCD_FROM_MCF
+	MOVWF	TXREG				;SENDEN
+	BRA		TG_END;			
+TG_ON_POWER2
+	MOVLW	RESET_ON_TIME		;
+	CPFSLT	TASTE_ON_TIME		;KÜRZER?
+	BRA		RESETEN
+TG_ON_POWER3
+	MOVLW	OFF_TIME
+	CPFSLT	TASTE_ON_TIME		;KÜRZER ON/OFF TIME?
+	CALL	POWER_AUS			;NEIN->POWER OFF
+	BRA		TG_END
+TG_OFF_POWER
+	MOVLW	ON_TIME
+	CPFSLT	TASTE_ON_TIME		;KÜRZER ALS ON/OFF TIME?
+	CALL	POWER_EIN			;NEIN->POWER ON
+TG_END
+	CLRF	TASTE_OFF_TIME		;RÜCKSETZEN
+	INCF	TASTE_ON_TIME		;ERHÖHEN 
+	RETURN
+RESETEN
+	BCF		TRISD,RD7			;NEIN-> #RSTI AKTIVIEREN =LOW  -->>>RESET
+	CALL	SERIAL_OFF			;SERIELL DEAKTIVIEREN
+	BRA		TG_ON_POWER3
+;**********************************************************************************************"""""""""""""
+;----------------------------------------- INTERRUPTS 
+;**********************************************************************************************"""""""""""""
+; SERIELL INTERRUPTS
+;**********************************************************************************************"""""""""""""
+;TX
+TX_ISR							;TRANSMIT
+	MOVLW	RTCD_FROM_PIC		;RTC DATEN SENDEN?
+	CPFSEQ	TX_STATUS			;SKIP JA
+	BRA		TX_ISR1				;NEIN->
+	MOVFF	POSTINC0,TXREG		;BYT SENDEN
+	MOVLW	0x3F				;SCHON LETZTES BYTS?
+	CPFSGT	FSR0L				;SKIP WENN FERTIG
+	RETFIE						;NEIN WEITERE SENDEN
+TX_ISR_FERTIG
+	CLRF	TX_STATUS
+	BCF 	PIE1,TXIE 			;SONST DISABLE interrupt
+	BCF		PIR1,TXIF			;INTERRUPT FLAG LÖSCHEN
+	RETFIE
+TX_ISR1
+	MOVLW	READ_BLOCK			;READ BLOCK?
+	CPFSEQ	TX_STATUS			;SKIP JA
+	BRA		TX_ISR2				;NEIN->
+	MOVFF	POSTINC0,TXREG		;BYT SENDEN
+	MOVLW	0xC3				;SCHON LETZTES BYTS?
+	CPFSGT	FSR0L				;SKIP WENN FERTIG
+	RETFIE						;NEIN WEITERE SENDEN
+TX_ISR2
+	BRA 	TX_ISR_FERTIG
+;**********************************************************************************************"""""""""""""
+;RX
+RX_ISR							; BYT RECEIVED
+	MOVFF	RCREG,RX_B			; BYT HOLEN	
+;   	MOVFF	RX_B,TXREG			; ECHO
+	MOVLW	SYNC4				;IM SYNC STATUS?
+	CPFSLT	RX_STATUS			;SKIP WENN NEIN
+	BRA		RX_SYNC_START		;JA -> ZUERST SYNC EMPFANGEN
+;---------------
+	MOVLW	RTCD_FROM_MCF		; DATEN VOM MCF CODE 0x82? 
+	CPFSEQ	RX_STATUS			; WENN JA-> SKIP
+	BRA		RX_ISR1				; NEIN->
+;64 BYT EMPFANGEN -------------------------------------
+	MOVFF	RX_B,POSTINC1		;HOLEN -> (CNT+)
+	MOVLW	0x3F				;64 BYT ÜBERTRAGEN?
+	CPFSLT	FSR1L				;NEIN ->SKIP
+	CLRF	RX_STATUS			;JA FERTIG
+	RETFIE	
+;-------------------------------------------------------------------------------------
+RX_ISR1
+	CPFSEQ	RX_B				;BLOCK HEADER 0X82?
+	BRA		RX_ISR2				;NEIN->
+	MOVWF	RX_STATUS			;STATUS SETZEN = EMPFANGENES BYT
+	LFSR	1,.0				;BYT COUNTER AUF O
+	RETFIE
+RX_ISR2
+	MOVLW	REQ_RTCD_FROM_PIC	;DATEN SENDEN?
+	CPFSEQ	RX_B				;SKIP WENN JA
+	BRA		RX_ISR3				;SONST NEXT
+;BLOCK HEADER UND 64 BYT SENDEN -----------------------------------------
+	LFSR	0,.0
+	BCF		PIR1,TXIF			;INTERRUPT FLAG LÖSCHEN
+	BSF 	PIE1,TXIE 			;Enable interrupt
+	MOVLW	RTCD_FROM_PIC
+	MOVWF	TX_STATUS			;STATUS SETZEN		
+	MOVWF	TXREG				;BLOCK HEADER = 0X81
+	CLRF	RX_STATUS			;STATUS RÜCKSETZEN
+	RETFIE						;UND WEG
+;-------------------------------------------------------------------------------------
+RX_ISR3
+	MOVLW	EXT_SUB_GO			;EXT SUB FREIGEBEN?
+	CPFSEQ	RX_B
+	BRA		RX_ISR4				;NEIN->	
+;EXT SUBS FREIGEBEN --------------------------------------------------------------			
+	MOVLW	(EXTERN_INT_ADR & 0xFF0000)>>16
+	MOVWF	TBLPTRU
+	MOVLW	(EXTERN_INT_ADR & 0x00FF00)>>8
+	MOVWF	TBLPTRH
+	MOVLW	(EXTERN_INT_ADR & 0x0000FF)
+	MOVWF	TBLPTRL				;ADRESSE SETZEN
+	TBLRD*						;WERT HOLEN (MUSS 0xFB SEIN SONST UNGÜLTIG)
+	MOVFF	TABLAT,GO_INT		;EXTERNE SUBROUTINES AKTIVIEREN WENN OK
+	MOVLW	(EXTERN_SUB_ADR & 0xFF0000)>>16
+	MOVWF	TBLPTRU
+	MOVLW	(EXTERN_SUB_ADR & 0x00FF00)>>8
+	MOVWF	TBLPTRH
+	MOVLW	(EXTERN_SUB_ADR & 0x0000FF)
+	MOVWF	TBLPTRL				;ADRESSE SETZEN
+	TBLRD*						;WERT HOLEN (MUSS 0xFB SEIN SONST UNGÜLTIG)
+	MOVFF	TABLAT,GO_SUB		;EXTERNE SUBROUTINES AKTIVIEREN WENN OK
+	CLRF	RX_STATUS			;STATUS RÜCKSETZEN
+	RETFIE						;UND WEG
+;-------------------------------------------------------------------------------------
+RX_ISR4
+	MOVLW	EXT_SUB_STOP		;EXT SUB STOPPEN?
+	CPFSEQ	RX_B
+	BRA		RX_ISR5				;NEIN->	
+;EXT SUBS STOPPEN --------------------------------------------------------------
+	CLRF	GO_INT				;STOPPEN			
+	CLRF	GO_SUB				;STOPPEN			
+	CLRF	RX_STATUS			;STATUS RÜCKSETZEN
+	RETFIE						;UND WEG
+;-------------------------------------------------------------------------------------
+RX_ISR5
+	MOVLW	REQ_BLOCK			;REQ BLOCK?
+	CPFSEQ	RX_B
+	BRA		RX_ISR6				;NEIN->
+;REQ BLOCK ----------------------------------------------------------------
+	MOVWF	RX_STATUS			;STATUS SETZEN = EMPFANGENES BYT
+	LFSR	1,TX_BUFFER			;BYT COUNTER AUF TX_BUFFER -> GLEICH EINTRAGEN
+	RETFIE
+RX_ISR6
+	CPFSEQ	RX_STATUS			;REQ BLOCK ADRESSE EMPFANGFEN?
+	BRA		RX_ISR7				;NEIN->
+;3 BYT EMPFANGEN -------------------------------------
+	MOVFF	RX_B,POSTINC1		;HOLEN -> (CNT+)
+	MOVLW	0x82				;3 BYT ÜBERTRAGEN? (BUFFER BEGINNT BEI 0x180
+	CPFSLT	FSR1L				;NEIN ->SKIP
+	BRA		RX_RB3BOK
+	RETFIE	
+RX_RB3BOK
+	LFSR	1,TX_BUFFER			;BYT RX COUNTER AUF TX_BUFFER 
+	MOVFF	POSTINC1,TBLPTRU	;ADRESSE EINTRAGEN
+	MOVFF	POSTINC1,TBLPTRH
+	MOVFF	POSTINC1,TBLPTRL
+	MOVLW	0xC2				;67 BYT ÜBERTRAGEN?  (BUFFER BEGINNT BEI 0x180
+RX_RB3B2
+	TBLRD	*+					;LESEN UND NEXT
+	MOVFF	TABLAT,POSTINC1		;UND EINTRAGEN
+	CPFSEQ	FSR1L				;WENN FERTIG ->SKIP
+	BRA		RX_RB3B2			;SONST LOOP
+;BLOCK HEADER  3 BYTS ADRESSE UND 64 BYT SENDEN STARTEN -----------------------------------------
+	LFSR	0,TX_BUFFER			;TX COUNTER AUF TX_BUFFER 
+	BCF		PIR1,TXIF			;INTERRUPT FLAG LÖSCHEN
+	BSF 	PIE1,TXIE 			;Enable interrupt
+	MOVLW	READ_BLOCK			;CODE HEADER 0xA1
+	MOVWF	TX_STATUS			;STATUS SETZEN		
+	MOVWF	TXREG				;BLOCK HEADER = 0XA1
+	CLRF	RX_STATUS			;STATUS RÜCKSETZEN
+	RETFIE						;UND WEG
+;-------------------------------------------------------------------------------------
+RX_ISR7	
+	MOVLW	WRITE_BLOCK			;WRITE BLOCK 0xA2 BYT EMPFANGEN?
+	CPFSEQ	RX_STATUS			;WENN JA-> SKIP
+	BRA		RX_ISR8				;NEIN->
+;WRITE BLOCK ----------------------------------------------------------------------------
+;67 BYT EMPFANGEN -------------------------------------
+	MOVFF	RX_B,POSTINC1		;HOLEN -> (CNT+)
+	MOVLW	0x42				;67 BYT ÜBERTRAGEN?
+	CPFSLT	FSR1L				;WENN FERTIG ->SKIP
+	RETFIE
+; ADRESSE UND DATEN SIND DA -> PROGRAMMING FLASH
+	LFSR	1,RX_BUFFER			;BYT COUNTER AUF RX BUFFER
+	MOVFF 	POSTINC1,TBLPTRU	;TABLE POINTER SETZEN
+	MOVLW	(EXTERN_INT_ADR & 0xFF0000)>>16
+	CPFSLT	TBLPTRU				;TEST OB WENIGER ALS ERLAUBT
+	BRA		NO_PROG				;JA->
+	MOVFF 	POSTINC1,TBLPTRH	;TABLE POINTER SETZEN
+	MOVLW	(EXTERN_INT_ADR & 0x00FF00)>>8
+	CPFSLT	TBLPTRU				;TEST OB WENIGER ALS ERLAUBT
+	BRA		NO_PROG				;JA->
+	MOVFF 	POSTINC1,TBLPTRL	;TABLE POINTER SETZEN 
+;EREASE BLOCK
+	BSF 	EECON1,EEPGD	 	; point to Flash program memory
+	BCF		EECON1,CFGS 		; access Flash program memory
+	BSF 	EECON1,WREN	 		; enable write to memory
+	BSF 	EECON1,FREE 		; enable Row Erase operation
+	MOVLW 	55h
+	MOVWF 	EECON2 				; write 55h
+	MOVLW 	0AAh				; write 0AAh
+	MOVWF 	EECON2 
+	BSF 	EECON1,WR 			; start erase (CPU stall)
+	MOVLW	0x42				;67 BYT 
+WRITE_WORD_TO_HREGS
+	MOVFF 	POSTINC1,TABLAT 	; get byte of buffer data
+	TBLWT+* 					; write data, perform a short write to internal TBLWT holding register.
+	CPFSLT	FSR1L				;SCHON BEI 67 BYTES?
+	BRA 	WRITE_WORD_TO_HREGS	;NEIN->LOOP
+PROGRAM_MEMORY
+	BSF 	EECON1,EEPGD 		; point to Flash program memory
+	BCF 	EECON1,CFGS 		; access Flash program memory
+	BSF 	EECON1,WREN 		; enable write to memory
+	MOVLW 	55h
+	MOVWF 	EECON2 				; write 55h
+	MOVLW 	0AAh
+	MOVWF 	EECON2 				; write 0AAh
+	BSF 	EECON1,WR 			; start program (CPU stall)
+	BCF 	EECON1,WREN 		; disable write to memory
+NO_PROG
+	CLRF	RX_STATUS			;AUF NORMLA SCHALTEN
+	RETFIE						;UND FERTIG
+;WRITE BLOCK SETZEN?
+RX_ISR8	
+	CPFSEQ	RX_B				;BLOCK HEADER COMMANDOE 0XA2?
+	BRA		RX_ISR9				;NEIN->
+	MOVWF	RX_STATUS			;STATUS SETZEN = EMPFANGENES BYT
+	LFSR	1,RX_BUFFER			;BYT COUNTER AUF RX BUFFER
+	RETFIE
+;-------------------------------------------------------------------------------------
+RX_ISR9
+	CLRF	RX_STATUS
+	RETFIE
+;-------------------------------------------------------------------------------------
+;SYNC ABWARTEN UND WENN DA "OK!" SENDEN ----------------------------------------------------
+;-------------------------------------------------------------------------------------
+RX_SYNC_START
+	MOVLW	SYNC1
+	CPFSEQ	RX_STATUS
+	BRA		RX_SYNC2
+	MOVLW	SYNC1_DATA
+	CPFSEQ	RX_B
+	BRA		NON_SYNC
+	MOVLW	SYNC2
+	MOVWF	RX_STATUS
+	RETFIE
+NON_SYNC
+	MOVLW	SYNC1
+	MOVWF	RX_STATUS
+	RETFIE
+RX_SYNC2						;TEST AUF SYNC UND DATA 2
+	MOVLW	SYNC2
+	CPFSEQ	RX_STATUS
+	BRA		RX_SYNC3			;NICHT SYNC 2
+	MOVLW	SYNC2_DATA
+	CPFSEQ	RX_B
+	BRA		NON_SYNC
+	MOVLW	SYNC3
+	MOVWF	RX_STATUS
+	RETFIE
+RX_SYNC3						;TEST AUF SYNC UND DATA 3
+	MOVLW	SYNC3
+	CPFSEQ	RX_STATUS
+	BRA		RX_SYNC4			;NICHT SYNC 3
+	MOVLW	SYNC3_DATA
+	CPFSEQ	RX_B
+	BRA		NON_SYNC
+	MOVLW	SYNC4
+	MOVWF	RX_STATUS
+	RETFIE
+RX_SYNC4						;TEST AUF SYNC UND DATA 4
+	MOVLW	SYNC4
+	CPFSEQ	RX_STATUS
+	BRA		NON_SYNC			;WIEDER VON VORN
+	MOVLW	SYNC4_DATA
+	CPFSEQ	RX_B				;SKIP OK
+	BRA		NON_SYNC			;NICHT SYNC4 DATA 
+RX_WAIT1
+	BTFSS	TXSTA,TRMT
+	BRA		RX_WAIT1
+	MOVLW	'O'					;SENDE OK!
+	MOVWF	TXREG;
+RX_WAIT2
+	BTFSS	TXSTA,TRMT
+	BRA		RX_WAIT2
+	MOVLW	'K'					;SENDE OK!
+	MOVWF	TXREG;
+RX_WAIT3
+	BTFSS	TXSTA,TRMT
+	BRA		RX_WAIT3
+	MOVLW	'!'
+	MOVWF	TXREG;
+	CLRF	RX_STATUS			;OK START NORMAL
+	RETFIE
+;**********************************************************************************************"""""""""""""
+;SPANNUNGSÜBERWACHUNGS INTERRUPT
+HLVD_ISR
+	BTFSS	U_ERR,1				;WARTEN AUF GELADEN?
+	BRA	HLVD_LE				;NEIN UNTERSPANNUNG DETEKT->
+	BCF		U_ERR,0				;SPANNUNGSFEHLER AUS
+	BCF		U_ERR,1				;WARTEN AUF GELADEN=AUS
+	MOVLW	U_ERR_PW_AUS+2		;POWER AUS ÜBERSPRINGEN
+	MOVWF	U_ERR_TIME			;ZEIT SETZEN 
+	MOVLW	B'00010111'			;INT WENN UNTER 3.12V
+	MOVWF	HLVDCON	
+WAIT_LVDOK:
+	BTFSS	HLVDCON,IVRST		;ABWARTEN BIS AENDERUNG AKTIV
+	BRA		WAIT_LVDOK
+	BCF		PIR2,HLVDIF			;INTERRUPT FLAG LÖSCHEN
+	RETFIE	
+HLVD_LE							;UNTERSPANNUNG
+	BSF		U_ERR,0				;ERROR SETZEN
+	BSF		U_ERR,1				;WARTEN AUF GELADEN SETZEN
+	CLRF	U_ERR_TIME			;RÜCKSETZEN
+;MESSAGE AN PROCESSOR
+	MOVLW	U_MIN_TO_MCF
+	MOVWF	TXREG				;SENDEN
+
+	MOVLW	B'10011010'			;INT WENN ÜBER 3.7V
+	MOVWF	HLVDCON	
+	BRA		WAIT_LVDOK
+;**********************************************************************************************"""""""""""""
+;A/D INTERRUPT
+AD_ISR
+	BCF		PIR1,ADIF			;CLEAR INTERRUPT PENDIG
+	RETFIE						;RETURN
+;*************************************************************************************************************
+; uhr interrupt ALLE 1/8 SEC
+RTC_ISR
+;UHR WIEDER RÜCKSETZEN UND AKTIVIEREN
+	MOVLW	TIMER_HB		;WIEDER AUF STARTWERT
+	MOVWF	TMR1H			;SETZEN
+	BCF		PIR1,TMR1IF		;INTERRUPT FLAG LÖSCHEN
+	BSF		PORTB,RB4		;PIC INT HIGH --------
+	BSF		TRISE,RE0		;LED=OFF
+	BCF		PORTB,RB4		;PIC INT = LOW
+	BTFSC	TRISD,RD0		;POWER OFF?
+	BRA		POWER_OFF_I		;JA->
+; POWER IS ON: 
+; BLINKEN 4X/SEC WENN RESET
+	BTFSC	TRISD,RD7		;RESET AKTIV?
+	BRA 	PINGS			;NEIN->
+	BTFSC 	TICKS,0			;UNGERADE TICKS?
+	BCF		TRISE,RE0		;NEIN->LED=ON
+	BRA	PINGS			
+POWER_OFF_I
+	MOVLW	.3				
+	ANDWF	SECS,0			;4 SEKUNDEN AUSMASKIEREN
+	BNZ		PINGS			;NICHT MODULO4 ->
+	MOVLW	.7
+	CPFSEQ	TICKS			;7. TICK?
+	BRA	POWER_OFF_I2	;NEIN->
+	BCF		TRISE,RE0		;JA->LED=ON
+POWER_OFF_I2
+	MOVLW	.30				; WENIGER ALS 30 SEC SEIT LETZTEM SPANNUNGSFEHLER?
+	CPFSLT	U_ERR_TIME
+	BRA	PINGS			;NEIN->
+	MOVLW	.5
+	CPFSEQ	TICKS			;5. TICK?
+	BRA	PINGS			;NEIN->
+	BCF		TRISE,RE0		;JA->LED=ON
+PINGS
+	CALL	TASTE			;UP TASTE
+; TASTE LOSGELASSEN?
+	MOVLW	RESET_OFF_TIME
+	CPFSGT	TASTE_OFF_TIME	;TASTE LÄNGER ALS 2 SEC LOSGELASSEN?
+	BRA		PINGW			;NEIN->
+	BSF 	TRISD,RD7	 	;JA-> #RSTI INAKTIV =HIGH
+	BTFSS	TRISD,RD0		;POWER ON?
+	CALL	SERIAL_ON		;ja->SERIELL EINSCHALTEN
+;--TICKS=125MS
+PINGW
+	INCF	TICKS			;inc ticks
+	BTFSS	TRISD,RD0		;POWER ON?
+	BRA		PINGS2			;JA->
+	MOVLW	20
+	CPFSLT	U_POWER_IN		;LADEGERÄT ANGESCHLOSSEN?
+	BRA		PINGS2			;->JA LED HELLER
+	MOVLW	TIME_MAX		;>=MAXIMALZEIT?
+	CPFSLT	U_ERR_TIME		;SEIT SPANNUNGSFEHLER
+	BSF		TRISE,RE0		;JA -> LED OFF
+PINGS2
+	MOVLW	.7				; 7?
+	CPFSGT	TICKS			
+	RETFIE					; NEIN ->RETURN
+SEKUNDEN
+;led blinken POWER ON-----------------------------------------
+	BTFSS	TRISD,RD0		;POWER ON?
+	BCF		TRISE,RE0		;JA -> LED_ON
+;TIMER U_ERR ERHÖHEN
+	MOVLW	TIME_MAX		;>=MAXIMALZEIT?
+	CPFSGT	U_ERR_TIME		;SEIT SPANNUNGSFEHLER
+	INCF	U_ERR_TIME		;NEIN ERHÖHEN
+;SPANNUNGSFEHLER BEARBEITEN ----------------------------------------
+	MOVLW	U_ERR_PW_AUS	;POWER AUS ZEIT?
+	CPFSEQ 	U_ERR_TIME		;
+	BRA		SEK_NPA			;NEIN
+	CALL 	POWER_AUS		;JA AUSSCHALTEN
+;--------------------------------------------------------
+SEK_NPA
+;SPANNUNG POWER IN MESSEN
+	MOVLW	B'00000001'			;KANAL 0, AD ON
+	MOVWF	ADCON0				; 
+	BSF		ADCON0,1			;GO
+SEK_2
+	BTFSC	ADCON0,1			;FERTIG?
+	BRA		SEK_2				;NEIN
+	MOVFF	ADRESH,U_POWER_IN	;OK WERT EINTRAGEN
+
+;SPANNUNG 2V5 MESSEN -> U_ERR TIMER NICHT ERHÖHEN WENN ÜBER 3.2V RESP. WIEDER -1
+	BTFSC	TRISD,RD0			;POWER ON?
+	BRA		SEK_4				;NEIN NICHT MESSEN
+
+	MOVLW	B'00001101'			;KANAL 3, AD ON
+	MOVWF	ADCON0				; 
+	BSF		ADCON0,1			;GO
+SEK_3
+	BTFSC	ADCON0,1			;FERTIG?
+	BRA		SEK_3				;NEIN
+	MOVLW	.200				;UNTER 3.2V -> WENN WERT ÜBER 78%
+	CPFSLT 	ADRESH				;JA ->
+	BRA		SEK_4				;SONST WEITER
+;TIMER U_ERR ERHÖHEN
+	BTFSS	U_ERR,0				;SPANNUNGSERROR?
+	BRA		SEK_4				;NEIN
+	MOVLW	TIME_MAX			;>=MAXIMALZEIT?
+	CPFSGT	U_ERR_TIME			;SEIT SPANNUNGSFEHLER
+	DECF	U_ERR_TIME			;NEIN -> -1
+;-------------------------------------------------------------
+SEK_4
+	CLRF	TICKS
+	INCF 	SECS	 		; Increment seconds
+	MOVLW 	.59 			; 60 seconds elapsed?
+	CPFSGT 	SECS
+	RETFIE	 				;RETURN
+MINUTEN
+	CLRF 	SECS 			; Clear seconds
+	INCF 	MINS	 		; Increment minutes
+	MOVLW 	.59 			; 60 minutes elapsed?
+	CPFSGT 	MINS
+	RETFIE 					;RETURN 
+STUNDEN
+	CLRF 	MINS 			; clear minutes
+	INCF 	HOURS	 		; Increment hours
+	MOVLW 	.23 			; 24 hours elapsed?
+	CPFSGT 	HOURS
+	RETFIE	 				;RETURN 
+TAGE_UND_TAG_DER_WOCHE
+	CLRF 	HOURS 			; Reset hours
+	MOVLW	.7
+	CPFSLT	DAY_OF_WEEK
+	CLRF	DAY_OF_WEEK
+	INCF	DAY_OF_WEEK
+	INCF	DAYS
+	MOVLW	.28				
+	CPFSGT	DAYS
+	RETFIE	 				;RETURN 
+MEHR_ALS_28_TAGE
+	MOVLW	.2
+	CPFSEQ	MONTHS			;FEB?
+	BRA		NOT_FEB			;NEIN->
+FEB
+	MOVLW	.3
+	ANDWF	YEARS,0			;SCHALTJAHR
+	BNZ		NEXT_MONTH		;NEIN->
+SCHALTJAHR
+	MOVLW	.29
+	CPFSGT	DAYS
+	RETFIE	 				;RETURN 
+NEXT_MONTH
+	MOVLW	.1
+	MOVWF	DAYS
+	INCF	MONTHS
+	MOVLW	12
+	CPFSGT	MONTHS
+	RETFIE	 				;RETURN 
+YEAR	
+	MOVLW	.1
+	MOVWF	MONTHS
+	INCF	YEARS
+	RETFIE	 				;RETURN 
+NOT_FEB
+	MOVLW	.30
+	CPFSGT	DAYS
+	RETFIE	 			
+MEHR_ALS_30_TAGE
+	MOVLW	.4				;APRIL?
+	CPFSEQ	MONTHS			;SKIP
+	BRA		NOT_APRIL 
+	BRA		NEXT_MONTH		;APRIL->
+NOT_APRIL
+	MOVLW	.6				;JUNI?
+	CPFSEQ	MONTHS
+	BRA		NOT_JUNI 
+	BRA		NEXT_MONTH		;JUNI->
+NOT_JUNI
+	MOVLW	.9				;SEPTEMBER?
+	CPFSEQ	MONTHS	 
+	BRA		NOT_SEP 
+	BRA		NEXT_MONTH		;SEPTEMBER->	 
+NOT_SEP
+	MOVLW	.11				;NOVEMBER?
+	CPFSEQ	MONTHS			;SKIP
+	RETFIE					;SIND MONATE MIT 31 TAGEN-> 
+	BRA		NEXT_MONTH		;SONST NOVEMBER->
+;**********************************************************************************************"""""""""""""
+; ENDE MAIN 
+;**********************************************************************************************"""""""""""""
+;**********************************************************************************************"""""""""""""
+; EXTERN_SUBOUTINES FOGEN AB 0x1000 DIE SPÄTER EINPROGRAMMIERT WERDEN
+;**********************************************************************************************"""""""""""""
+	end
diff --git a/FireBee/MLAB/firebee1/firebee1.cof b/FireBee/MLAB/firebee1/firebee1.cof
new file mode 100644
index 0000000..d3b53d4
Binary files /dev/null and b/FireBee/MLAB/firebee1/firebee1.cof differ
diff --git a/FireBee/MLAB/firebee1/firebee1.err b/FireBee/MLAB/firebee1/firebee1.err
new file mode 100644
index 0000000..e69de29
diff --git a/FireBee/MLAB/firebee1/firebee1.hex b/FireBee/MLAB/firebee1/firebee1.hex
new file mode 100644
index 0000000..bef9bef
--- /dev/null
+++ b/FireBee/MLAB/firebee1/firebee1.hex
@@ -0,0 +1,82 @@
+:020000040000FA
+:020000007FD0AF
+:020002000000FC
+:040008000CEF00F009
+:08001800E06A9DCF4EF09E50FE
+:100020004E174EB115D24EBD11D24EB918D14EBB9E
+:100030002BD1A0CF4FF0A1504F174FB5F3D11000E7
+:100040009DCF4EF09E504E174E67E6D7A0CF4FF093
+:10005000A1504F174F67E0D7FB0E4D63100001EF23
+:0200600010F09E
+:10010000E06AF26AD06A9D6AA06A9E6AA16A9F6AE2
+:10011000A26A9B6A720ED36E806AFF0E926E816A2B
+:10012000936E826A946E836A956E010E846A966EEF
+:100130009B0ED26E030E466F140E476FA084E9EC3F
+:1001400000F0F00ECF6ECE6A0F0ECD6E416B006BDD
+:10015000026B0C0E046F010E066F010E076F080E86
+:10016000086F2A0E096F426B436B446B9D80456B91
+:10017000C26A090EC16E000EC06E486BB06A100EE6
+:10018000AF6E040EAC6E900EAB6E080EB86E4C6B7C
+:10019000F06AF00EF16EC00EF26E120ED36EFB0E10
+:1001A0004C6302D0D7ED00F095B00300F8D709EC0E
+:1001B00010F01300720ED36E929E959E93989590B8
+:1001C0000AD0120ED36E9580958E9388928E446BD2
+:1001D00004D095B002D09298120092881200AC9A86
+:1001E0009D9A9E9A9D989E981200ACBA1200AC8A75
+:1001F000FF0E4A6F4B6BAECF49F0AECF49F09E98E1
+:100200009E9A9D8A0000120083A20BD0426BA00E22
+:100210004365432B040E44651200958EF5EC00F007
+:100220001200150E4261120095B00ED0020E42630C
+:1002300003D0020EAD6E0CD0020E42610CD0140E33
+:100240004261E1EC00F004D0020E4261DAEC00F011
+:10025000436B422B1200959EEFEC00F0F0D7810E1D
+:100260004B6309D0EECFADFF3F0EE96410004B6B3E
+:100270009D989E981000A10E4B6305D0EECFADFF68
+:10028000C30EE9641000F3D7AECF49F0FC0E4A610B
+:1002900097D0820E4A6306D049C0E6FF3F0EE16068
+:1002A0004A6B1000496304D04A6F10EE00F0100052
+:1002B000010E496309D000EE00F09E989D88810EE2
+:1002C0004B6FAD6E4A6B1000040E496314D0000EE4
+:1002D000F86E200EF76E000EF66E0800F5CF4DF0AA
+:1002E000000EF86E200EF76E100EF66E0800F5CFB9
+:1002F0004CF04A6B1000050E496304D04D6B4C6BFB
+:100300004A6B1000A00E496304D04A6F11EE80F0D2
+:1003100010004A631DD049C0E6FF820EE16001D0A3
+:10032000100011EE80F0E6CFF8FFE6CFF7FFE6CF42
+:10033000F6FFC20E0900F5CFE6FFE162FBD701EE42
+:1003400080F09E989D88A10E4B6FAD6E4A6B100099
+:10035000A20E4A632DD049C0E6FF420EE1601000B4
+:1003600011EE00F0E6CFF8FF000EF8601FD0E6CFE8
+:10037000F7FF200EF8601AD0E6CFF6FFA68EA69CF7
+:10038000A684A688550EA76EAA0EA76EA682420E58
+:10039000E6CFF5FF0F00E160FBD7A68EA69CA684F2
+:1003A000550EA76EAA0EA76EA682A6944A6B1000E1
+:1003B000496304D04A6F11EE00F010004A6B100040
+:1003C000FF0E4A6309D0410E496303D0FE0E4A6F07
+:1003D0001000FF0E4A6F1000FE0E4A6306D0430E57
+:1003E0004963F7D7FD0E4A6F1000FD0E4A6306D031
+:1003F000500E4963EED7FC0E4A6F1000FC0E4A63A4
+:10040000E8D7460E4963E5D7ACA2FED74F0EAD6ED6
+:10041000ACA2FED74B0EAD6EACA2FED7210EAD6ED8
+:100420004A6B100046A30AD046914693070E476FC9
+:10043000170ED26ED2AAFED7A19410004681468331
+:10044000476B030EAD6E9A0ED26EF4D79E9C1000D1
+:10045000F00ECF6E9E9081889680819895B005D0E1
+:1004600095BE11D041B196900ED0030E00150BE150
+:10047000070E416301D096901E0E476104D0050E11
+:10048000416301D0969004EC01F0040E436504D062
+:10049000958E95A0F5EC00F0412B95A006D0200E8E
+:1004A000486103D0A00E47619680070E4165100099
+:1004B00095A09690A00E4765472B050E476302D086
+:1004C000E1EC00F0010EC26EC282C2B2FED7C4CF10
+:1004D00048F095B00DD00D0EC26EC282C2B2FED7EA
+:1004E000C80EC46005D046A103D0A00E47654707DB
+:1004F000416B002B3B0E00651000006B022B3B0E86
+:1005000002651000026B042B170E04651000046BCB
+:10051000070E0661066B062B072B1C0E07651000E5
+:10052000020E086310D0030E091503E11D0E0765C6
+:100530001000010E076F082B120E08651000010E47
+:10054000086F092B10001E0E07651000040E0863CB
+:1005500001D0EFD7060E086301D0EBD7090E086370
+:0C05600001D0E7D70B0E08631000E3D7B2
+:00000001FF
diff --git a/FireBee/MLAB/firebee1/firebee1.lst b/FireBee/MLAB/firebee1/firebee1.lst
new file mode 100644
index 0000000..8b08d7e
--- /dev/null
+++ b/FireBee/MLAB/firebee1/firebee1.lst
@@ -0,0 +1,1979 @@
+MPASM  5.35                      FIREBEE1.ASM   10-1-2010  13:06:42         PAGE  1
+
+
+LOC  OBJECT CODE     LINE SOURCE TEXT
+  VALUE
+
+                      00001 ;**********************************************************
+                      00002 ;*  firebee1 PIC18F4321 MAIN FILE
+                      00003 ;**********************************************************
+                      00004 ;*  CREATED BY FREDI ASCHWANDEN
+                      00005 ;*  DATE 22.9.2009
+                      00006 ;**********************************************************
+                      00007         list PE=18f4520                         ;EXTENDED INSTRUCTION SET
+                      00008         include "P18f4520.inc"
+                      00001         LIST
+                      00002 
+                      00003 ;==========================================================================
+                      00004 ;  MPASM PIC18F4520 processor include
+                      00005 ; 
+                      00006 ;  (c) Copyright 1999-2007 Microchip Technology, All rights reserved
+                      00007 ;==========================================================================
+                      00008 
+                      01336         LIST
+                      00009 ;------------------------ Equates --------------------------;
+                      00010 ;Register addresses
+                      00011 ;BANK 0
+  00000000            00012 SECS                    equ     0x00
+  00000001            00013 SECS_ALARM                      EQU             0x01
+  00000002            00014 MINS                    equ     0x02
+  00000003            00015 MINS_ALRAM                      EQU             0x03
+  00000004            00016 HOURS                   equ     0x04
+  00000005            00017 HOURS_ALARM                     EQU             0x05
+  00000006            00018 DAY_OF_WEEK                     EQU             0x06
+  00000007            00019 DAYS                            EQU             0x07
+  00000008            00020 MONTHS                          EQU             0x08
+  00000009            00021 YEARS                           EQU             0x09            ;offset vom 1968
+  0000000A            00022 REGA                            EQU             0x0A
+  0000000B            00023 REGB                            EQU             0x0B
+  0000000C            00024 REGC                            EQU             0x0C
+  0000000D            00025 REGD                            EQU             0x0D
+  0000000E            00026 RTC_RAM                         EQU             0x0E            ; bis 0x3F
+  00000040            00027 free                            equ             0x40
+  00000041            00028 TICKS                   equ     0x41            ;125MS
+  00000042            00029 TASTE_ON_TIME           EQU             0x42
+  00000043            00030 TASTE_OFF_TIME          EQU             0x43
+  00000044            00031 POWER_ON_TIME           EQU             0x44
+  00000045            00032 AD_KANAL                        EQU             0x45
+  00000046            00033 U_ERR                           EQU             0x46            ;SPANNUNGSFEHLER WENN BIT 0=1, BIT1=1 WA
+                            RTEN AUF GELADEN
+  00000047            00034 U_ERR_TIME                      EQU             0x47            ;ZEIT SEIT SPANNUNGSFEHLER
+  00000048            00035 U_POWER_IN                      EQU             0x48            ;SPANNUNG POWER IN 1V CA. 6E
+  00000049            00036 RX_B                            EQU             0x49            ;RECEIVED BYT
+  0000004A            00037 RX_STATUS                       EQU             0x4A            ;STATUS: 0x00=WAIT AUF MCF COMMANDO, 0x8
+                            2=EMPFANGE 64BYT FROM RTC
+  0000004B            00038 TX_STATUS                       EQU             0x4B            ;STATUS: 0x00=WAIT 0x81=SENDE 64BYT FROM
+                             RTC
+  0000004C            00039 GO_SUB                          EQU             0x4C            ;WENN GLEICH 0xFB DANN SUBROUTINE AUSFÜH
+                            REN
+  0000004D            00040 GO_INT                          EQU             0x4D            ;WENN GLEICH 0xFB DANN SUBROUTINE AUSFÜH
+MPASM  5.35                      FIREBEE1.ASM   10-1-2010  13:06:42         PAGE  2
+
+
+LOC  OBJECT CODE     LINE SOURCE TEXT
+  VALUE
+
+                            REN
+  0000004E            00041 EAPIR1                          EQU             0x4E            ;INTERRUPT ACTIV UND ENABLE
+  0000004F            00042 EAPIR2                          EQU             0x4F            ;INTERRUPT ACTIV UND ENABLE
+                      00043 ;BANK 1 AB 0x100
+  00000100            00044 RX_BUFFER                       EQU             0x100           ;0x80 BYT BUFFER BIS 0x17F BANK
+  00000180            00045 TX_BUFFER                       EQU             0x180           ;0X80 BYT BUFFER BIS 0x1FF BANK
+                      00046 
+                      00047 ;--------------------------------------------------------------
+  00000002            00048 SEND_RTC_TIME           EQU             .2                      ;0.25 SEC (EINHEIT IST EIN TICK = 128MS
+  00000002            00049 RESET_ON_TIME           EQU             .2                      ;0.25 SEC (EINHEIT IST EIN TICK = 128MS
+  00000004            00050 RESET_OFF_TIME          EQU             .4                      ;0.5 SEC (EINHEIT IST EIN TICK = 128MS
+  00000014            00051 OFF_TIME                        EQU             .20                     ;2.5 SEC (EINHEIT IST EIN TICK =
+                             128MS
+  00000002            00052 ON_TIME                         EQU             .2                      ;0.25 SEC (EINHEIT IST EIN TICK 
+                            = 128MS
+  000000F0            00053 TIMER_HB                        EQU             .240            ;256- (32768Hz PRO 1/8SEC = 4096TICKS/25
+                            6) => 256-16=240 (resp 256-16/4 (wenn osco) = 252)
+  000000A0            00054 TIME_MAX                        EQU             .160            ;MAXIMALTIME
+  00000005            00055 U_ERR_PW_AUS            EQU             .5                      ;5 SEC
+                      00056 ;SERIEL
+  000000FF            00057 SYNC1                           EQU             0FFh
+  00000041            00058 SYNC1_DATA                      EQU             'A';
+  000000FE            00059 SYNC2                           EQU             0FEh
+  00000043            00060 SYNC2_DATA                      EQU             'C';
+  000000FD            00061 SYNC3                           EQU             0FDh    
+  00000050            00062 SYNC3_DATA                      EQU             'P';
+  000000FC            00063 SYNC4                           EQU             0FCh
+  00000046            00064 SYNC4_DATA                      EQU             'F';
+  00000001            00065 REQ_RTCD_FROM_PIC       EQU             01h                     ;RTC AND NVRAM DATEN VOM PIC ANFORDERN
+  00000081            00066 RTCD_FROM_PIC           EQU             81h                     ;RTC AND NVRAM DATEN HEADER UND STATUS
+  00000002            00067 REQ_RTCD_FROM_MCF       EQU             02h                     ;RTC AND NVRAM DATEN VOM MCF ANFORDERN
+  00000082            00068 RTCD_FROM_MCF           EQU             82h                     ;RTC AND NVRAM DATEN HEADER UND STATUS
+  00000003            00069 U_MIN_TO_MCF            EQU             03h                     ;UNTERSPANNUNGSMITTEILUNG AN PROCESSOR
+  00000004            00070 EXT_SUB_GO                      EQU             04h                     ;SERIELL CODE UM SUBROUTINEN/INT
+                            ERRUPTS ZU AKTIVIEREN
+  00000005            00071 EXT_SUB_STOP            EQU             05h                     ;SERIELL CODE UM SUBROUTINEN/INTERRUPTS 
+                            ZU STOPPEN
+  00000012            00072 CLK_SLEEP                       EQU             B'00010010'             ;125kHz intern, SLEEP MODE
+  00000072            00073 CLK_ACTIV                       EQU             B'01110010'             ;inTernal CLK=8MHz, SLEEP MODE, 
+                            SLEEP MODE
+  000000FB            00074 EXT_CODE                        EQU             0xFB            ;CODE FÜR EXTERNE SUBROUTINEN/INTERRUPTS
+                             AUSFÜHREN (FireBee!)
+  00002000            00075 EXTERN_INT_ADR          EQU             0x2000          ;HIER MUSS 0xFB STEHEN WENN EXTERNE INTERRUPTS A
+                            USFÜHRBAR
+  00002002            00076 EXTERN_INTERRUPTS       EQU             0x2002          ;STARTPUNKT EXTERNE SUBROUTINES
+  00002010            00077 EXTERN_SUB_ADR          EQU             0x2010          ;HIER MUSS 0xFB STEHEN WENN EXTERNE SUBROUTINES 
+                            AUSFÜHRBAR
+  00002012            00078 EXTERN_SUBROUTINES      EQU             0x2012          ;STARTPUNKT EXTERNE SUBROUTINES
+  000000A0            00079 REQ_BLOCK                       EQU             0xA0            ;BLOCK DATEN LESEN -> CODE UND 3 BYTS AD
+                            RESSE = TOTAL 4 BYTES
+  000000A1            00080 READ_BLOCK                      EQU             0xA1            ;PROGRAMM BLOCK PIC->MCF -> CODE, 3 BYTS
+                             ADRESSE UND 64 BYTS DATEN = TOTAL 68 BYTES
+  000000A2            00081 WRITE_BLOCK                     EQU             0xA2            ;PROGRAMM BLOCK MCF->PIC -> CODE, 3 BYTS
+MPASM  5.35                      FIREBEE1.ASM   10-1-2010  13:06:42         PAGE  3
+
+
+LOC  OBJECT CODE     LINE SOURCE TEXT
+  VALUE
+
+                             ADRESSE UND 64 BYTS DATEN = TOTAL 68 BYTES
+  00000022            00082 PRG_OK_PIC                      EQU             0x22            ;PROGRAMMIERUNG BLOCK FERTIG
+                      00083 ;**********************************************************************************************"""""""""
+                            """"
+                      00084 ; Start at the reset vector
+                      00085 Reset_Vector code 0x000 
+000000 D???           00086         BRA     KALT_START
+                      00087 ;--------------------------------------------------------------
+                      00088 HIGH_INT_VEC code       0x0008
+000008 EF0C F000      00089         GOTO    0x18
+                      00090         
+                      00091 LOW_INT_VEC     code    0x0018
+000018                00092 INT_HANDLER
+000018 6AE0           00093         CLRF    BSR                                     ;IMMER ACCESS BANK
+                      00094 ;SETZEN GRUPPE 1
+00001A CF9D F04E      00095         MOVFF   PIE1,EAPIR1                     ;INTERRUPTS HOLEN
+00001E 509E           00096         MOVF    PIR1,0                          ;MASKE
+000020 174E           00097         ANDWF   EAPIR1                          ;ACTIVE SETZEN
+000022 B14E           00098         BTFSC   EAPIR1,TMR1IF           ;uhr interrupt?
+000024 D???           00099         BRA             RTC_ISR                         ;ja->
+000026 BD4E           00100         BTFSC   EAPIR1,ADIF                     ;AD INTERRUTP?
+000028 D???           00101         BRA             AD_ISR                          ;JA->
+00002A B94E           00102         BTFSC   EAPIR1,TXIF                     ;seriell TX?
+00002C D???           00103         BRA             TX_ISR                          ;JA->
+00002E BB4E           00104         BTFSC   EAPIR1,RCIF                     ;seriell RX?
+000030 D???           00105         BRA             RX_ISR                          ;JA->
+                      00106 
+                      00107 ;SETZEN GRUPPE 2
+000032 CFA0 F04F      00108         MOVFF   PIE2,EAPIR2                     ;INTERRUPTS HOLEN
+000036 50A1           00109         MOVF    PIR2,0                          ;MASKE
+000038 174F           00110         ANDWF   EAPIR2                          ;ACTIVE SETZEN
+                      00111 
+00003A B54F           00112         BTFSC   EAPIR2,HLVDIF           ;UNDER/OVERVOLTAGE DETECT
+00003C D???           00113         BRA             HLVD_ISR                        ;JA->
+00003E 0010           00114         RETFIE
+                      00115 
+                      00116 ;TESTEN UND SETZEN GRUPPE 1
+000040 CF9D F04E      00117         MOVFF   PIE1,EAPIR1                     ;INTERRUPTS HOLEN
+000044 509E           00118         MOVF    PIR1,0                          ;MASKE
+000046 174E           00119         ANDWF   EAPIR1                          ;ACTIVE SETZEN
+000048 674E           00120         TSTFSZ  EAPIR1
+00004A D???           00121         BRA             INT_HANDLER
+                      00122 ;TESTEN UND SETZEN GRUPPE 2
+00004C CFA0 F04F      00123         MOVFF   PIE2,EAPIR2                     ;INTERRUPTS HOLEN
+000050 50A1           00124         MOVF    PIR2,0                          ;MASKE
+000052 174F           00125         ANDWF   EAPIR2                          ;ACTIVE SETZEN
+000054 674F           00126         TSTFSZ  EAPIR2
+000056 D???           00127         BRA             INT_HANDLER
+                      00128 
+000058 0EFB           00129         MOVLW   EXT_CODE                        ;GO EXTERNE SUBROUTINEN AKTIV?
+00005A 634D           00130         CPFSEQ  GO_INT                          ;SKIP WENN JA
+00005C 0010           00131         RETFIE
+00005E EF01 F010      00132         GOTO    EXTERN_INTERRUPTS       ;REGISTER SICHERN UND STARTEN
+MPASM  5.35                      FIREBEE1.ASM   10-1-2010  13:06:42         PAGE  4
+
+
+LOC  OBJECT CODE     LINE SOURCE TEXT
+  VALUE
+
+                      00133 ;**********************************************************************************************"""""""""
+                            """"
+                      00134         ; Start application beyond vector area
+                      00135         CODE    0x0100
+000100                00136 KALT_START
+                      00137 ;RESET MODE
+000100 6AE0           00138         CLRF    BSR                                     ;BANK 0
+                      00139 ;ALLE INT AUS UND RÜCKSETZEN
+000102 6AF2           00140         CLRF    INTCON                          ;alle INTERRUPT AUS
+000104 6AD0           00141         CLRF    RCON                            ;INT PRIORITY AUS
+000106 6A9D           00142         CLRF    PIE1                            ;MASK DISABLE
+000108 6AA0           00143         CLRF    PIE2
+00010A 6A9E           00144         CLRF    PIR1                            ;INT ACT AUS
+00010C 6AA1           00145         CLRF    PIR2
+00010E 6A9F           00146         CLRF    IPR1                            ;LOW PRIORITY
+000110 6AA2           00147         CLRF    IPR2
+                      00148         ; clock 
+                      00149 ;       MOVLW   B'01000000'                     ;32MHZ
+                      00150 ;       MOVWF   OSCTUNE
+000112 6A9B           00151         CLRF    OSCTUNE
+                      00152 ;CLOCK
+000114 0E72           00153         MOVLW   CLK_ACTIV
+000116 6ED3           00154         MOVWF   OSCCON
+                      00155         ; div init
+                      00156 ;SET PORT A: **7:#master/0.409*5V0 **6:PIC_AMKB_RX **5:PIC_SWTICH **4:HIGH_CHARGE_CURRENT **3:2V5 *2:3V3
+                            /2 **1:1V25 **0:POWER_IN/11
+000118 6A80           00157         CLRF    PORTA                           ;#master(7)=0, REST=0
+00011A 0EFF           00158         MOVLW   B'11111111'                     ;DIRECTION: alles auf Input 
+00011C 6E92           00159         MOVWF   TRISA
+                      00160 ;SET PORT B: **7:PGD **6:PGC **5:PGM **4:PIN_INT,1V5 **3:GAME PORT PIN10 **2:GAME PORT PIN11 **1:GAME PO
+                            RT PIN6 **0: GAME PORT PIN5
+00011E 6A81           00161         CLRF    PORTB                           ;ALLES AUF 0
+000120 6E93           00162         MOVWF   TRISB
+                      00163 ;SET PORT C: **7: PIC_RX **6:PIC_TX **5:AMKB_TX **4:GAME PORT PIN4 **3:GAME PORT PIN12 **2:GAME PORT PIN
+                            13 **1+0: OCS 32K768Hz
+000122 6A82           00164         CLRF    PORTC
+000124 6E94           00165         MOVWF   TRISC
+                      00166 ;SET PORT D: **7:#RSTI **6:GAME PORT PIN3 **5:PS2 KB CLK **4:PS2 MS CLK **3:PS2 KB DATA **2:MS DATA **1:
+                            TASTER **0:POWER ON/OFF (0=ON)
+                      00167 ; SET TASTE UND POWER
+000126 6A83           00168         CLRF    PORTD                           ;ALLES AUF 0
+000128 6E95           00169         MOVWF   TRISD                           ;ALLES AUF INPUT
+                      00170 ;SET PORT E: **3:#MCLR **2:#PCI_RESET **1:PCI 3V3 **0:PIC LED (0=ON)
+00012A 0E01           00171         MOVLW   B'00000001'                     ;LED OFF
+00012C 6A84           00172         CLRF    PORTE                           ;ALLES AUF 0
+00012E 6E96           00173         MOVWF   TRISE                           ;ALLES AUF INPUT
+                      00174 ;--------------------------
+                      00175 ;  set OVERvoltage detekt 
+000130 0E9B           00176         MOVLW   B'10011011'                     ;INT WENN ÜBER 3.9V
+000132 6ED2           00177         MOVWF   HLVDCON 
+000134 0E03           00178         MOVLW   B'00000011'                     ;ERRORS ON, WAIT AUF LADEN
+000136 6F46           00179         MOVWF   U_ERR
+000138 0E14           00180         MOVLW   .20                                     ;SEIT 20SEC ERROR                        
+MPASM  5.35                      FIREBEE1.ASM   10-1-2010  13:06:42         PAGE  5
+
+
+LOC  OBJECT CODE     LINE SOURCE TEXT
+  VALUE
+
+00013A 6F47           00181         MOVWF   U_ERR_TIME                      ;SETZEN
+00013C 84A0           00182         BSF     PIE2,HLVDIE             ;Enable interrupt
+                      00183 ;INTIALISIERUNGSPROGAMME
+00013E EC?? F???      00184         CALL    LADESTROM                       ;LADESTROM EINSTELLEN
+                      00185 ;UHR initialisieren
+000142 0EF0           00186         MOVLW   TIMER_HB                        ;Preload TMR1 register 
+000144 6ECF           00187         MOVWF   TMR1H                           ;
+000146 6ACE           00188         CLRF    TMR1L                           ;=0
+000148 0E0F           00189         MOVLW   B'00001111'                     ; 8 BIT, osc1 enable, TIMER MODE, TIMMER ENABLE
+00014A 6ECD           00190         MOVWF   T1CON                           ; SET
+00014C 6B41           00191         CLRF    TICKS                           ; 1/8 sec register
+00014E 6B00           00192         CLRF    SECS                            ; Initialize timekeeping registers
+000150 6B02           00193         CLRF    MINS                            ;
+000152 0E0C           00194         MOVLW   .12
+000154 6F04           00195         MOVWF   HOURS
+000156 0E01           00196         MOVLW   .1
+000158 6F06           00197         MOVWF   DAY_OF_WEEK
+00015A 0E01           00198         MOVLW   .1
+00015C 6F07           00199         MOVWF   DAYS
+00015E 0E08           00200         MOVLW   .8
+000160 6F08           00201         MOVWF   MONTHS
+000162 0E2A           00202         MOVLW   .42
+000164 6F09           00203         MOVWF   YEARS                           ;MONTAG 19.7.2010 12:00:00 (JAHR-1968)
+000166 6B42           00204         CLRF    TASTE_ON_TIME
+000168 6B43           00205         CLRF    TASTE_OFF_TIME
+00016A 6B44           00206         CLRF    POWER_ON_TIME
+00016C 809D           00207         BSF     PIE1,TMR1IE             ;Enable Timer1 interrupt
+                      00208 ;AD WANDLER INITIALISIEREN
+00016E 6B45           00209         CLRF    AD_KANAL                        ;BEI 0 BEGINNEN
+000170 6AC2           00210         CLRF    ADCON0                          ;AD MOUDUL AUS
+000172 0E09           00211         MOVLW   B'00001001'                     ;VREF=VDD,ANALOG INPUT AN0-AN5
+000174 6EC1           00212         MOVWF   ADCON1
+000176 0E00           00213         MOVLW   B'00000000'                     ;LINKSSBÜNDIG,0 TAD,CLOCK=Fosc/2
+000178 6EC0           00214         MOVWF   ADCON2
+                      00215 ;       BSF             PIE1,ADIE                       ;INTERRUPT ENABLE
+00017A 6B48           00216         CLRF    U_POWER_IN                      ;WERT AUF 0 VOLT
+                      00217 ; seriell initialisieren
+00017C 6AB0           00218         CLRF    SPBRGH
+00017E 0E10           00219         MOVLW   .16
+000180 6EAF           00220         MOVWF   SPBRG                           ;BAUDE RATE = 115K
+000182 0E04           00221         MOVLW   B'00000100'                     ;TX AUS, ASYNC HIGH SPEED
+000184 6EAC           00222         MOVWF   TXSTA
+000186 0E90           00223         MOVLW   B'10010000'                     ;SERIEL EIN,RX EIN,
+000188 6EAB           00224         MOVWF   RCSTA
+00018A 0E08           00225         MOVLW   B'00001000'                     ;16BIT BRG, RISING EDGE INTERRUPT
+00018C 6EB8           00226         MOVWF   BAUDCON                         ;SETZEN
+                      00227 ;EXTERNER SUBROUTINES
+00018E 6B4C           00228         CLRF    GO_SUB
+                      00229 ; interrupts
+000190 6AF0           00230         CLRF    INTCON3                         ;EXTER INTERRUPT AUS, low priority
+000192 0EF0           00231         MOVLW   B'11110000'                     ;PORT B PULLUPS AUS, EXT INT ON RISING EDGE, TMR0 AND BP
+                            IP Low priority
+000194 6EF1           00232         MOVWF   INTCON2
+MPASM  5.35                      FIREBEE1.ASM   10-1-2010  13:06:42         PAGE  6
+
+
+LOC  OBJECT CODE     LINE SOURCE TEXT
+  VALUE
+
+000196 0EC0           00233         MOVLW   B'11000000'                     ;global on, PERIPHERAL INT on
+000198 6EF2           00234         MOVWF   INTCON
+                      00235 ;CLOCK
+00019A 0E12           00236         MOVLW   CLK_SLEEP                       ;GEHT JETZT IN SLEEP MODE
+00019C 6ED3           00237         MOVWF   OSCCON
+                      00238 ;-------------------------------------------------------------------------
+                      00239 ;---------------------------- MAIN LOOP -------------------------------------------------
+                      00240 ;-------------------------------------------------------------------------
+00019E                00241 MAIN                                            
+00019E 0EFB           00242         MOVLW   EXT_CODE                        ;GO EXTERNE SUBROUTINEN AKTIV?
+0001A0 634C           00243         CPFSEQ  GO_SUB                          ;SKIP WENN JA
+0001A2 D???           00244         BRA             WARTEN                          ;SONST WARTEN
+0001A4 ED00 F000      00245         CALL    MAIN2,1                         ;REGISTER SICHERN UND STARTEN
+0001A8                00246 WARTEN
+0001A8 B095           00247         BTFSC   TRISD,RD0                       ;SKIP IF POWER ON
+0001AA 0003           00248         SLEEP                                           ;SLEPP BIS ZUM NÄCHSTEN INTERRUPT
+0001AC D???           00249         BRA     MAIN
+0001AE                00250 MAIN2
+0001AE EC09 F010      00251         CALL    EXTERN_SUBROUTINES      ;EXTERNE SUBROUTINEN AUSFÜHREN AN STELLE 0 MUSS 0xFA STEHEN SONS
+                            T UNGÜLTIG
+0001B2 0013           00252         RETURN  1                                       ;RETURN MIT REGISTER ZURÜCK
+                      00253 ;**********************************************************************************************"""""""""
+                            """"
+                      00254 ;--------------------------- subroutines -------------------------------------------------
+                      00255 ;**********************************************************************************************"""""""""
+                            """"
+                      00256 ;POWER ON/OFF 
+0001B4                00257 POWER_EIN
+                      00258 ;CLOCK
+0001B4 0E72           00259         MOVLW   CLK_ACTIV
+0001B6 6ED3           00260         MOVWF   OSCCON
+                      00261 
+0001B8 9E92           00262         BCF             TRISA,RA7                       ;CLOCK EINSCHALTEN
+0001BA 9E95           00263         BCF             TRISD,RD7                       ;#RSTI AKTIVIEREN = LOW
+0001BC 9893           00264         BCF             TRISB,RB4                       ;PIC_INT AKTIVIEREN
+0001BE 9095           00265         BCF             TRISD,RD0                       ;POWER ON
+0001C0 D???           00266         BRA             LS_ON_POWER                     ;LADESTROM EINSTELLEN
+0001C2                00267 POWER_AUS
+                      00268 ;CLOCK
+0001C2 0E12           00269         MOVLW   CLK_SLEEP
+0001C4 6ED3           00270         MOVWF   OSCCON
+                      00271 
+0001C6 8095           00272         BSF             TRISD,RD0                       ;POWER OFF
+0001C8 8E95           00273         BSF             TRISD,RD7                       ;#RSTI DEAKTIVIEREN
+0001CA 8893           00274         BSF             TRISB,RB4                       ;PIC INT DEAKTIVIEREN
+0001CC 8E92           00275         BSF             TRISA,RA7                       ;CLOCK DEAKTIVIEREN
+0001CE 6B44           00276         CLRF    POWER_ON_TIME           ;RÜCKSETZEN
+0001D0 D???           00277         BRA             LS_OFF_POWER            ;LADESTROM EINSTELLEN
+                      00278 ;LADESTROM EINSTELLEN ----------------------------
+0001D2                00279 LADESTROM
+0001D2 B095           00280         BTFSC   TRISD,RD0                       ; ONPOWER?
+0001D4 D???           00281         BRA             LS_OFF_POWER            ; NEIN->
+0001D6                00282 LS_ON_POWER                                             ;GROSSER LADESTROM 5A
+MPASM  5.35                      FIREBEE1.ASM   10-1-2010  13:06:42         PAGE  7
+
+
+LOC  OBJECT CODE     LINE SOURCE TEXT
+  VALUE
+
+0001D6 9892           00283         BCF             TRISA,RA4                       ;10K ON
+0001D8 0012           00284         RETURN
+0001DA                00285 LS_OFF_POWER                                    ;KLEINER LADESTROM_MIN 1.85A
+0001DA 8892           00286         BSF             TRISA,RA4                       ;10K OFF
+0001DC 0012           00287         RETURN
+                      00288 ;---------------------------------------------------
+                      00289 ;SERIELL AUS/EIN
+0001DE                00290 SERIAL_OFF
+0001DE 9AAC           00291         BCF             TXSTA,TXEN                      ;TX AUS
+0001E0 9A9D           00292         BCF     PIE1,RCIE                       ;DISABLE RX interrupt
+0001E2 9A9E           00293         BCF     PIR1,RCIF                       ;CLEAR RX interrupt
+0001E4 989D           00294         BCF     PIE1,TXIE                       ;DISABLE TX interrupt
+0001E6 989E           00295         BCF     PIR1,TXIF                       ;CLEAR TX interrupt
+0001E8 0012           00296         RETURN
+0001EA                00297 SERIAL_ON
+0001EA BAAC           00298         BTFSC   TXSTA,TXEN                      ;SCHON EIN?
+0001EC 0012           00299         RETURN                                          ;JA->
+0001EE 8AAC           00300         BSF             TXSTA,TXEN                      ;TX EIN
+0001F0 0EFF           00301         MOVLW   SYNC1
+0001F2 6F4A           00302         MOVWF   RX_STATUS                       ;AUF SYNC WARTEN
+0001F4 6B4B           00303         CLRF    TX_STATUS
+0001F6 CFAE F049      00304         MOVFF   RCREG,RX_B                      ;RCREG LEEREN
+0001FA CFAE F049      00305         MOVFF   RCREG,RX_B                      ;RCREG LEEREN
+0001FE 989E           00306         BCF     PIR1,TXIF                       ;CLEAR TX interrupt
+000200 9A9E           00307         BCF             PIR1,RCIF                       ;INTERRUPT RX FLAG LÖSCHEN
+000202 8A9D           00308         BSF     PIE1,RCIE                       ;ENABLE RX interrupt
+000204 0000           00309         NOP
+000206 0012           00310         RETURN
+                      00311 ;---------------------------------------------------------------------
+                      00312 ; TASTENDRUCK
+000208                00313 TASTE
+000208 A283           00314         BTFSS   PORTD,RD1                       ;TASTE GEDRÜCKT?
+00020A D???           00315         BRA             TG_JA                           ;->JA
+                      00316 ;TASTE NICHT GEDRÜCKT ODER LOSGELASSEN
+00020C 6B42           00317         CLRF    TASTE_ON_TIME           ;RÜCKSETZEN
+                      00318 
+00020E 0EA0           00319         MOVLW   TIME_MAX                        ;MAX
+000210 6543           00320         CPFSGT  TASTE_OFF_TIME          ;LÄNGER?
+000212 2B43           00321         INCF    TASTE_OFF_TIME          ;NEIN ERHÖHEN
+                      00322 
+000214 0E04           00323         MOVLW   RESET_OFF_TIME          ;2SEC
+000216 6544           00324         CPFSGT  POWER_ON_TIME           ;LÄNGER?
+000218 0012           00325         RETURN                                          ;NEIN->
+                      00326 ;RESET AUFHEBEN
+00021A 8E95           00327         BSF             TRISD,RD7                       ;JA -> #RSTI DEAKTIVIEREN =HIGH
+00021C EC?? F???      00328         CALL    SERIAL_ON                       ;SERIELL EINSCHALTEN
+000220 0012           00329         RETURN
+                      00330 ;TASTE GEDRÜCKT
+000222                00331 TG_JA
+000222 0E15           00332         MOVLW   OFF_TIME+1
+000224 6142           00333         CPFSLT  TASTE_ON_TIME           ;KÜRZER ALS ONTIME+1
+000226 0012           00334         RETURN                                          ;NEIN->FERTIG
+000228 B095           00335         BTFSC   TRISD,RD0                       ;ONPOWER?
+MPASM  5.35                      FIREBEE1.ASM   10-1-2010  13:06:42         PAGE  8
+
+
+LOC  OBJECT CODE     LINE SOURCE TEXT
+  VALUE
+
+00022A D???           00336         BRA             TG_OFF_POWER            ;NEIN->
+00022C                00337 TG_ON_POWER
+00022C 0E02           00338         MOVLW   SEND_RTC_TIME           ;ZEIT FÜR RTC REQ FROM MCF HOLEN?
+00022E 6342           00339         CPFSEQ  TASTE_ON_TIME           ;TEST
+000230 D???           00340         BRA             TG_ON_POWER2            ;NEIN->
+000232                00341 SEND_RTC_REG
+000232 0E02           00342         MOVLW   REQ_RTCD_FROM_MCF
+000234 6EAD           00343         MOVWF   TXREG                           ;SENDEN
+000236 D???           00344         BRA             TG_END;                 
+000238                00345 TG_ON_POWER2
+000238 0E02           00346         MOVLW   RESET_ON_TIME           ;
+00023A 6142           00347         CPFSLT  TASTE_ON_TIME           ;KÜRZER?
+00023C D???           00348         BRA             RESETEN
+00023E                00349 TG_ON_POWER3
+00023E 0E14           00350         MOVLW   OFF_TIME
+000240 6142           00351         CPFSLT  TASTE_ON_TIME           ;KÜRZER ON/OFF TIME?
+000242 EC?? F???      00352         CALL    POWER_AUS                       ;NEIN->POWER OFF
+000246 D???           00353         BRA             TG_END
+000248                00354 TG_OFF_POWER
+000248 0E02           00355         MOVLW   ON_TIME
+00024A 6142           00356         CPFSLT  TASTE_ON_TIME           ;KÜRZER ALS ON/OFF TIME?
+00024C EC?? F???      00357         CALL    POWER_EIN                       ;NEIN->POWER ON
+000250                00358 TG_END
+000250 6B43           00359         CLRF    TASTE_OFF_TIME          ;RÜCKSETZEN
+000252 2B42           00360         INCF    TASTE_ON_TIME           ;ERHÖHEN 
+000254 0012           00361         RETURN
+000256                00362 RESETEN
+000256 9E95           00363         BCF             TRISD,RD7                       ;NEIN-> #RSTI AKTIVIEREN =LOW  -->>>RESET
+000258 EC?? F???      00364         CALL    SERIAL_OFF                      ;SERIELL DEAKTIVIEREN
+00025C D???           00365         BRA             TG_ON_POWER3
+                      00366 ;**********************************************************************************************"""""""""
+                            """"
+                      00367 ;----------------------------------------- INTERRUPTS 
+                      00368 ;**********************************************************************************************"""""""""
+                            """"
+                      00369 ; SERIELL INTERRUPTS
+                      00370 ;**********************************************************************************************"""""""""
+                            """"
+                      00371 ;TX
+00025E                00372 TX_ISR                                                  ;TRANSMIT
+00025E 0E81           00373         MOVLW   RTCD_FROM_PIC           ;RTC DATEN SENDEN?
+000260 634B           00374         CPFSEQ  TX_STATUS                       ;SKIP JA
+000262 D???           00375         BRA             TX_ISR1                         ;NEIN->
+000264 CFEE FFAD      00376         MOVFF   POSTINC0,TXREG          ;BYT SENDEN
+000268 0E3F           00377         MOVLW   0x3F                            ;SCHON LETZTES BYTS?
+00026A 64E9           00378         CPFSGT  FSR0L                           ;SKIP WENN FERTIG
+00026C 0010           00379         RETFIE                                          ;NEIN WEITERE SENDEN
+00026E                00380 TX_ISR_FERTIG
+00026E 6B4B           00381         CLRF    TX_STATUS
+000270 989D           00382         BCF     PIE1,TXIE                       ;SONST DISABLE interrupt
+000272 989E           00383         BCF             PIR1,TXIF                       ;INTERRUPT FLAG LÖSCHEN
+000274 0010           00384         RETFIE
+000276                00385 TX_ISR1
+MPASM  5.35                      FIREBEE1.ASM   10-1-2010  13:06:42         PAGE  9
+
+
+LOC  OBJECT CODE     LINE SOURCE TEXT
+  VALUE
+
+000276 0EA1           00386         MOVLW   READ_BLOCK                      ;READ BLOCK?
+000278 634B           00387         CPFSEQ  TX_STATUS                       ;SKIP JA
+00027A D???           00388         BRA             TX_ISR2                         ;NEIN->
+00027C CFEE FFAD      00389         MOVFF   POSTINC0,TXREG          ;BYT SENDEN
+000280 0EC3           00390         MOVLW   0xC3                            ;SCHON LETZTES BYTS?
+000282 64E9           00391         CPFSGT  FSR0L                           ;SKIP WENN FERTIG
+000284 0010           00392         RETFIE                                          ;NEIN WEITERE SENDEN
+000286                00393 TX_ISR2
+000286 D???           00394         BRA     TX_ISR_FERTIG
+                      00395 ;**********************************************************************************************"""""""""
+                            """"
+                      00396 ;RX
+000288                00397 RX_ISR                                                  ; BYT RECEIVED
+000288 CFAE F049      00398         MOVFF   RCREG,RX_B                      ; BYT HOLEN     
+                      00399 ;       MOVFF   RX_B,TXREG                      ; ECHO
+00028C 0EFC           00400         MOVLW   SYNC4                           ;IM SYNC STATUS?
+00028E 614A           00401         CPFSLT  RX_STATUS                       ;SKIP WENN NEIN
+000290 D???           00402         BRA             RX_SYNC_START           ;JA -> ZUERST SYNC EMPFANGEN
+                      00403 ;---------------
+000292 0E82           00404         MOVLW   RTCD_FROM_MCF           ; DATEN VOM MCF CODE 0x82? 
+000294 634A           00405         CPFSEQ  RX_STATUS                       ; WENN JA-> SKIP
+000296 D???           00406         BRA             RX_ISR1                         ; NEIN->
+                      00407 ;64 BYT EMPFANGEN -------------------------------------
+000298 C049 FFE6      00408         MOVFF   RX_B,POSTINC1           ;HOLEN -> (CNT+)
+00029C 0E3F           00409         MOVLW   0x3F                            ;64 BYT ÜBERTRAGEN?
+00029E 60E1           00410         CPFSLT  FSR1L                           ;NEIN ->SKIP
+0002A0 6B4A           00411         CLRF    RX_STATUS                       ;JA FERTIG
+0002A2 0010           00412         RETFIE  
+                      00413 ;-------------------------------------------------------------------------------------
+0002A4                00414 RX_ISR1
+0002A4 6349           00415         CPFSEQ  RX_B                            ;BLOCK HEADER 0X82?
+0002A6 D???           00416         BRA             RX_ISR2                         ;NEIN->
+0002A8 6F4A           00417         MOVWF   RX_STATUS                       ;STATUS SETZEN = EMPFANGENES BYT
+0002AA EE10 F000      00418         LFSR    1,.0                            ;BYT COUNTER AUF O
+0002AE 0010           00419         RETFIE
+0002B0                00420 RX_ISR2
+0002B0 0E01           00421         MOVLW   REQ_RTCD_FROM_PIC       ;DATEN SENDEN?
+0002B2 6349           00422         CPFSEQ  RX_B                            ;SKIP WENN JA
+0002B4 D???           00423         BRA             RX_ISR3                         ;SONST NEXT
+                      00424 ;BLOCK HEADER UND 64 BYT SENDEN -----------------------------------------
+0002B6 EE00 F000      00425         LFSR    0,.0
+0002BA 989E           00426         BCF             PIR1,TXIF                       ;INTERRUPT FLAG LÖSCHEN
+0002BC 889D           00427         BSF     PIE1,TXIE                       ;Enable interrupt
+0002BE 0E81           00428         MOVLW   RTCD_FROM_PIC
+0002C0 6F4B           00429         MOVWF   TX_STATUS                       ;STATUS SETZEN          
+0002C2 6EAD           00430         MOVWF   TXREG                           ;BLOCK HEADER = 0X81
+0002C4 6B4A           00431         CLRF    RX_STATUS                       ;STATUS RÜCKSETZEN
+0002C6 0010           00432         RETFIE                                          ;UND WEG
+                      00433 ;-------------------------------------------------------------------------------------
+0002C8                00434 RX_ISR3
+0002C8 0E04           00435         MOVLW   EXT_SUB_GO                      ;EXT SUB FREIGEBEN?
+0002CA 6349           00436         CPFSEQ  RX_B
+0002CC D???           00437         BRA             RX_ISR4                         ;NEIN-> 
+MPASM  5.35                      FIREBEE1.ASM   10-1-2010  13:06:42         PAGE 10
+
+
+LOC  OBJECT CODE     LINE SOURCE TEXT
+  VALUE
+
+                      00438 ;EXT SUBS FREIGEBEN --------------------------------------------------------------                      
+0002CE 0E00           00439         MOVLW   (EXTERN_INT_ADR & 0xFF0000)>>16
+0002D0 6EF8           00440         MOVWF   TBLPTRU
+0002D2 0E20           00441         MOVLW   (EXTERN_INT_ADR & 0x00FF00)>>8
+0002D4 6EF7           00442         MOVWF   TBLPTRH
+0002D6 0E00           00443         MOVLW   (EXTERN_INT_ADR & 0x0000FF)
+0002D8 6EF6           00444         MOVWF   TBLPTRL                         ;ADRESSE SETZEN
+0002DA 0008           00445         TBLRD*                                          ;WERT HOLEN (MUSS 0xFB SEIN SONST UNGÜLTIG)
+0002DC CFF5 F04D      00446         MOVFF   TABLAT,GO_INT           ;EXTERNE SUBROUTINES AKTIVIEREN WENN OK
+0002E0 0E00           00447         MOVLW   (EXTERN_SUB_ADR & 0xFF0000)>>16
+0002E2 6EF8           00448         MOVWF   TBLPTRU
+0002E4 0E20           00449         MOVLW   (EXTERN_SUB_ADR & 0x00FF00)>>8
+0002E6 6EF7           00450         MOVWF   TBLPTRH
+0002E8 0E10           00451         MOVLW   (EXTERN_SUB_ADR & 0x0000FF)
+0002EA 6EF6           00452         MOVWF   TBLPTRL                         ;ADRESSE SETZEN
+0002EC 0008           00453         TBLRD*                                          ;WERT HOLEN (MUSS 0xFB SEIN SONST UNGÜLTIG)
+0002EE CFF5 F04C      00454         MOVFF   TABLAT,GO_SUB           ;EXTERNE SUBROUTINES AKTIVIEREN WENN OK
+0002F2 6B4A           00455         CLRF    RX_STATUS                       ;STATUS RÜCKSETZEN
+0002F4 0010           00456         RETFIE                                          ;UND WEG
+                      00457 ;-------------------------------------------------------------------------------------
+0002F6                00458 RX_ISR4
+0002F6 0E05           00459         MOVLW   EXT_SUB_STOP            ;EXT SUB STOPPEN?
+0002F8 6349           00460         CPFSEQ  RX_B
+0002FA D???           00461         BRA             RX_ISR5                         ;NEIN-> 
+                      00462 ;EXT SUBS STOPPEN --------------------------------------------------------------
+0002FC 6B4D           00463         CLRF    GO_INT                          ;STOPPEN                        
+0002FE 6B4C           00464         CLRF    GO_SUB                          ;STOPPEN                        
+000300 6B4A           00465         CLRF    RX_STATUS                       ;STATUS RÜCKSETZEN
+000302 0010           00466         RETFIE                                          ;UND WEG
+                      00467 ;-------------------------------------------------------------------------------------
+000304                00468 RX_ISR5
+000304 0EA0           00469         MOVLW   REQ_BLOCK                       ;REQ BLOCK?
+000306 6349           00470         CPFSEQ  RX_B
+000308 D???           00471         BRA             RX_ISR6                         ;NEIN->
+                      00472 ;REQ BLOCK ----------------------------------------------------------------
+00030A 6F4A           00473         MOVWF   RX_STATUS                       ;STATUS SETZEN = EMPFANGENES BYT
+00030C EE11 F080      00474         LFSR    1,TX_BUFFER                     ;BYT COUNTER AUF TX_BUFFER -> GLEICH EINTRAGEN
+000310 0010           00475         RETFIE
+000312                00476 RX_ISR6
+000312 634A           00477         CPFSEQ  RX_STATUS                       ;REQ BLOCK ADRESSE EMPFANGFEN?
+000314 D???           00478         BRA             RX_ISR7                         ;NEIN->
+                      00479 ;3 BYT EMPFANGEN -------------------------------------
+000316 C049 FFE6      00480         MOVFF   RX_B,POSTINC1           ;HOLEN -> (CNT+)
+00031A 0E82           00481         MOVLW   0x82                            ;3 BYT ÜBERTRAGEN? (BUFFER BEGINNT BEI 0x180
+00031C 60E1           00482         CPFSLT  FSR1L                           ;NEIN ->SKIP
+00031E D???           00483         BRA             RX_RB3BOK
+000320 0010           00484         RETFIE  
+000322                00485 RX_RB3BOK
+000322 EE11 F080      00486         LFSR    1,TX_BUFFER                     ;BYT RX COUNTER AUF TX_BUFFER 
+000326 CFE6 FFF8      00487         MOVFF   POSTINC1,TBLPTRU        ;ADRESSE EINTRAGEN
+00032A CFE6 FFF7      00488         MOVFF   POSTINC1,TBLPTRH
+00032E CFE6 FFF6      00489         MOVFF   POSTINC1,TBLPTRL
+000332 0EC2           00490         MOVLW   0xC2                            ;67 BYT ÜBERTRAGEN?  (BUFFER BEGINNT BEI 0x180
+MPASM  5.35                      FIREBEE1.ASM   10-1-2010  13:06:42         PAGE 11
+
+
+LOC  OBJECT CODE     LINE SOURCE TEXT
+  VALUE
+
+000334                00491 RX_RB3B2
+000334 0009           00492         TBLRD   *+                                      ;LESEN UND NEXT
+000336 CFF5 FFE6      00493         MOVFF   TABLAT,POSTINC1         ;UND EINTRAGEN
+00033A 62E1           00494         CPFSEQ  FSR1L                           ;WENN FERTIG ->SKIP
+00033C D???           00495         BRA             RX_RB3B2                        ;SONST LOOP
+                      00496 ;BLOCK HEADER  3 BYTS ADRESSE UND 64 BYT SENDEN STARTEN -----------------------------------------
+00033E EE01 F080      00497         LFSR    0,TX_BUFFER                     ;TX COUNTER AUF TX_BUFFER 
+000342 989E           00498         BCF             PIR1,TXIF                       ;INTERRUPT FLAG LÖSCHEN
+000344 889D           00499         BSF     PIE1,TXIE                       ;Enable interrupt
+000346 0EA1           00500         MOVLW   READ_BLOCK                      ;CODE HEADER 0xA1
+000348 6F4B           00501         MOVWF   TX_STATUS                       ;STATUS SETZEN          
+00034A 6EAD           00502         MOVWF   TXREG                           ;BLOCK HEADER = 0XA1
+00034C 6B4A           00503         CLRF    RX_STATUS                       ;STATUS RÜCKSETZEN
+00034E 0010           00504         RETFIE                                          ;UND WEG
+                      00505 ;-------------------------------------------------------------------------------------
+000350                00506 RX_ISR7 
+000350 0EA2           00507         MOVLW   WRITE_BLOCK                     ;WRITE BLOCK 0xA2 BYT EMPFANGEN?
+000352 634A           00508         CPFSEQ  RX_STATUS                       ;WENN JA-> SKIP
+000354 D???           00509         BRA             RX_ISR8                         ;NEIN->
+                      00510 ;WRITE BLOCK ----------------------------------------------------------------------------
+                      00511 ;67 BYT EMPFANGEN -------------------------------------
+000356 C049 FFE6      00512         MOVFF   RX_B,POSTINC1           ;HOLEN -> (CNT+)
+00035A 0E42           00513         MOVLW   0x42                            ;67 BYT ÜBERTRAGEN?
+00035C 60E1           00514         CPFSLT  FSR1L                           ;WENN FERTIG ->SKIP
+00035E 0010           00515         RETFIE
+                      00516 ; ADRESSE UND DATEN SIND DA -> PROGRAMMING FLASH
+000360 EE11 F000      00517         LFSR    1,RX_BUFFER                     ;BYT COUNTER AUF RX BUFFER
+000364 CFE6 FFF8      00518         MOVFF   POSTINC1,TBLPTRU        ;TABLE POINTER SETZEN
+000368 0E00           00519         MOVLW   (EXTERN_INT_ADR & 0xFF0000)>>16
+00036A 60F8           00520         CPFSLT  TBLPTRU                         ;TEST OB WENIGER ALS ERLAUBT
+00036C D???           00521         BRA             NO_PROG                         ;JA->
+00036E CFE6 FFF7      00522         MOVFF   POSTINC1,TBLPTRH        ;TABLE POINTER SETZEN
+000372 0E20           00523         MOVLW   (EXTERN_INT_ADR & 0x00FF00)>>8
+000374 60F8           00524         CPFSLT  TBLPTRU                         ;TEST OB WENIGER ALS ERLAUBT
+000376 D???           00525         BRA             NO_PROG                         ;JA->
+000378 CFE6 FFF6      00526         MOVFF   POSTINC1,TBLPTRL        ;TABLE POINTER SETZEN 
+                      00527 ;EREASE BLOCK
+00037C 8EA6           00528         BSF     EECON1,EEPGD            ; point to Flash program memory
+00037E 9CA6           00529         BCF             EECON1,CFGS             ; access Flash program memory
+000380 84A6           00530         BSF     EECON1,WREN                     ; enable write to memory
+000382 88A6           00531         BSF     EECON1,FREE             ; enable Row Erase operation
+000384 0E55           00532         MOVLW   55h
+000386 6EA7           00533         MOVWF   EECON2                          ; write 55h
+000388 0EAA           00534         MOVLW   0AAh                            ; write 0AAh
+00038A 6EA7           00535         MOVWF   EECON2 
+00038C 82A6           00536         BSF     EECON1,WR                       ; start erase (CPU stall)
+00038E 0E42           00537         MOVLW   0x42                            ;67 BYT 
+000390                00538 WRITE_WORD_TO_HREGS
+000390 CFE6 FFF5      00539         MOVFF   POSTINC1,TABLAT         ; get byte of buffer data
+000394 000F           00540         TBLWT+*                                         ; write data, perform a short write to internal 
+                            TBLWT holding register.
+000396 60E1           00541         CPFSLT  FSR1L                           ;SCHON BEI 67 BYTES?
+000398 D???           00542         BRA     WRITE_WORD_TO_HREGS     ;NEIN->LOOP
+MPASM  5.35                      FIREBEE1.ASM   10-1-2010  13:06:42         PAGE 12
+
+
+LOC  OBJECT CODE     LINE SOURCE TEXT
+  VALUE
+
+00039A                00543 PROGRAM_MEMORY
+00039A 8EA6           00544         BSF     EECON1,EEPGD            ; point to Flash program memory
+00039C 9CA6           00545         BCF     EECON1,CFGS             ; access Flash program memory
+00039E 84A6           00546         BSF     EECON1,WREN             ; enable write to memory
+0003A0 0E55           00547         MOVLW   55h
+0003A2 6EA7           00548         MOVWF   EECON2                          ; write 55h
+0003A4 0EAA           00549         MOVLW   0AAh
+0003A6 6EA7           00550         MOVWF   EECON2                          ; write 0AAh
+0003A8 82A6           00551         BSF     EECON1,WR                       ; start program (CPU stall)
+0003AA 94A6           00552         BCF     EECON1,WREN             ; disable write to memory
+0003AC                00553 NO_PROG
+0003AC 6B4A           00554         CLRF    RX_STATUS                       ;AUF NORMLA SCHALTEN
+0003AE 0010           00555         RETFIE                                          ;UND FERTIG
+                      00556 ;WRITE BLOCK SETZEN?
+0003B0                00557 RX_ISR8 
+0003B0 6349           00558         CPFSEQ  RX_B                            ;BLOCK HEADER COMMANDOE 0XA2?
+0003B2 D???           00559         BRA             RX_ISR9                         ;NEIN->
+0003B4 6F4A           00560         MOVWF   RX_STATUS                       ;STATUS SETZEN = EMPFANGENES BYT
+0003B6 EE11 F000      00561         LFSR    1,RX_BUFFER                     ;BYT COUNTER AUF RX BUFFER
+0003BA 0010           00562         RETFIE
+                      00563 ;-------------------------------------------------------------------------------------
+0003BC                00564 RX_ISR9
+0003BC 6B4A           00565         CLRF    RX_STATUS
+0003BE 0010           00566         RETFIE
+                      00567 ;-------------------------------------------------------------------------------------
+                      00568 ;SYNC ABWARTEN UND WENN DA "OK!" SENDEN ----------------------------------------------------
+                      00569 ;-------------------------------------------------------------------------------------
+0003C0                00570 RX_SYNC_START
+0003C0 0EFF           00571         MOVLW   SYNC1
+0003C2 634A           00572         CPFSEQ  RX_STATUS
+0003C4 D???           00573         BRA             RX_SYNC2
+0003C6 0E41           00574         MOVLW   SYNC1_DATA
+0003C8 6349           00575         CPFSEQ  RX_B
+0003CA D???           00576         BRA             NON_SYNC
+0003CC 0EFE           00577         MOVLW   SYNC2
+0003CE 6F4A           00578         MOVWF   RX_STATUS
+0003D0 0010           00579         RETFIE
+0003D2                00580 NON_SYNC
+0003D2 0EFF           00581         MOVLW   SYNC1
+0003D4 6F4A           00582         MOVWF   RX_STATUS
+0003D6 0010           00583         RETFIE
+0003D8                00584 RX_SYNC2                                                ;TEST AUF SYNC UND DATA 2
+0003D8 0EFE           00585         MOVLW   SYNC2
+0003DA 634A           00586         CPFSEQ  RX_STATUS
+0003DC D???           00587         BRA             RX_SYNC3                        ;NICHT SYNC 2
+0003DE 0E43           00588         MOVLW   SYNC2_DATA
+0003E0 6349           00589         CPFSEQ  RX_B
+0003E2 D???           00590         BRA             NON_SYNC
+0003E4 0EFD           00591         MOVLW   SYNC3
+0003E6 6F4A           00592         MOVWF   RX_STATUS
+0003E8 0010           00593         RETFIE
+0003EA                00594 RX_SYNC3                                                ;TEST AUF SYNC UND DATA 3
+0003EA 0EFD           00595         MOVLW   SYNC3
+MPASM  5.35                      FIREBEE1.ASM   10-1-2010  13:06:42         PAGE 13
+
+
+LOC  OBJECT CODE     LINE SOURCE TEXT
+  VALUE
+
+0003EC 634A           00596         CPFSEQ  RX_STATUS
+0003EE D???           00597         BRA             RX_SYNC4                        ;NICHT SYNC 3
+0003F0 0E50           00598         MOVLW   SYNC3_DATA
+0003F2 6349           00599         CPFSEQ  RX_B
+0003F4 D???           00600         BRA             NON_SYNC
+0003F6 0EFC           00601         MOVLW   SYNC4
+0003F8 6F4A           00602         MOVWF   RX_STATUS
+0003FA 0010           00603         RETFIE
+0003FC                00604 RX_SYNC4                                                ;TEST AUF SYNC UND DATA 4
+0003FC 0EFC           00605         MOVLW   SYNC4
+0003FE 634A           00606         CPFSEQ  RX_STATUS
+000400 D???           00607         BRA             NON_SYNC                        ;WIEDER VON VORN
+000402 0E46           00608         MOVLW   SYNC4_DATA
+000404 6349           00609         CPFSEQ  RX_B                            ;SKIP OK
+000406 D???           00610         BRA             NON_SYNC                        ;NICHT SYNC4 DATA 
+000408                00611 RX_WAIT1
+000408 A2AC           00612         BTFSS   TXSTA,TRMT
+00040A D???           00613         BRA             RX_WAIT1
+00040C 0E4F           00614         MOVLW   'O'                                     ;SENDE OK!
+00040E 6EAD           00615         MOVWF   TXREG;
+000410                00616 RX_WAIT2
+000410 A2AC           00617         BTFSS   TXSTA,TRMT
+000412 D???           00618         BRA             RX_WAIT2
+000414 0E4B           00619         MOVLW   'K'                                     ;SENDE OK!
+000416 6EAD           00620         MOVWF   TXREG;
+000418                00621 RX_WAIT3
+000418 A2AC           00622         BTFSS   TXSTA,TRMT
+00041A D???           00623         BRA             RX_WAIT3
+00041C 0E21           00624         MOVLW   '!'
+00041E 6EAD           00625         MOVWF   TXREG;
+000420 6B4A           00626         CLRF    RX_STATUS                       ;OK START NORMAL
+000422 0010           00627         RETFIE
+                      00628 ;**********************************************************************************************"""""""""
+                            """"
+                      00629 ;SPANNUNGSÜBERWACHUNGS INTERRUPT
+000424                00630 HLVD_ISR
+000424 A346           00631         BTFSS   U_ERR,1                         ;WARTEN AUF GELADEN?
+000426 D???           00632         BRA     HLVD_LE                         ;NEIN UNTERSPANNUNG DETEKT->
+000428 9146           00633         BCF             U_ERR,0                         ;SPANNUNGSFEHLER AUS
+00042A 9346           00634         BCF             U_ERR,1                         ;WARTEN AUF GELADEN=AUS
+00042C 0E07           00635         MOVLW   U_ERR_PW_AUS+2          ;POWER AUS ÜBERSPRINGEN
+00042E 6F47           00636         MOVWF   U_ERR_TIME                      ;ZEIT SETZEN 
+000430 0E17           00637         MOVLW   B'00010111'                     ;INT WENN UNTER 3.12V
+000432 6ED2           00638         MOVWF   HLVDCON 
+000434                00639 WAIT_LVDOK:
+000434 AAD2           00640         BTFSS   HLVDCON,IVRST           ;ABWARTEN BIS AENDERUNG AKTIV
+000436 D???           00641         BRA             WAIT_LVDOK
+000438 94A1           00642         BCF             PIR2,HLVDIF                     ;INTERRUPT FLAG LÖSCHEN
+00043A 0010           00643         RETFIE  
+00043C                00644 HLVD_LE                                                 ;UNTERSPANNUNG
+00043C 8146           00645         BSF             U_ERR,0                         ;ERROR SETZEN
+00043E 8346           00646         BSF             U_ERR,1                         ;WARTEN AUF GELADEN SETZEN
+000440 6B47           00647         CLRF    U_ERR_TIME                      ;RÜCKSETZEN
+MPASM  5.35                      FIREBEE1.ASM   10-1-2010  13:06:42         PAGE 14
+
+
+LOC  OBJECT CODE     LINE SOURCE TEXT
+  VALUE
+
+                      00648 ;MESSAGE AN PROCESSOR
+000442 0E03           00649         MOVLW   U_MIN_TO_MCF
+000444 6EAD           00650         MOVWF   TXREG                           ;SENDEN
+                      00651 
+000446 0E9A           00652         MOVLW   B'10011010'                     ;INT WENN ÜBER 3.7V
+000448 6ED2           00653         MOVWF   HLVDCON 
+00044A D???           00654         BRA             WAIT_LVDOK
+                      00655 ;**********************************************************************************************"""""""""
+                            """"
+                      00656 ;A/D INTERRUPT
+00044C                00657 AD_ISR
+00044C 9C9E           00658         BCF             PIR1,ADIF                       ;CLEAR INTERRUPT PENDIG
+00044E 0010           00659         RETFIE                                          ;RETURN
+                      00660 ;*******************************************************************************************************
+                            ******
+                      00661 ; uhr interrupt ALLE 1/8 SEC
+000450                00662 RTC_ISR
+                      00663 ;UHR WIEDER RÜCKSETZEN UND AKTIVIEREN
+000450 0EF0           00664         MOVLW   TIMER_HB                ;WIEDER AUF STARTWERT
+000452 6ECF           00665         MOVWF   TMR1H                   ;SETZEN
+000454 909E           00666         BCF             PIR1,TMR1IF             ;INTERRUPT FLAG LÖSCHEN
+000456 8881           00667         BSF             PORTB,RB4               ;PIC INT HIGH --------
+000458 8096           00668         BSF             TRISE,RE0               ;LED=OFF
+00045A 9881           00669         BCF             PORTB,RB4               ;PIC INT = LOW
+00045C B095           00670         BTFSC   TRISD,RD0               ;POWER OFF?
+00045E D???           00671         BRA             POWER_OFF_I             ;JA->
+                      00672 ; POWER IS ON: 
+                      00673 ; BLINKEN 4X/SEC WENN RESET
+000460 BE95           00674         BTFSC   TRISD,RD7               ;RESET AKTIV?
+000462 D???           00675         BRA     PINGS                   ;NEIN->
+000464 B141           00676         BTFSC   TICKS,0                 ;UNGERADE TICKS?
+000466 9096           00677         BCF             TRISE,RE0               ;NEIN->LED=ON
+000468 D???           00678         BRA     PINGS                   
+00046A                00679 POWER_OFF_I
+00046A 0E03           00680         MOVLW   .3                              
+00046C 1500           00681         ANDWF   SECS,0                  ;4 SEKUNDEN AUSMASKIEREN
+00046E E1??           00682         BNZ             PINGS                   ;NICHT MODULO4 ->
+000470 0E07           00683         MOVLW   .7
+000472 6341           00684         CPFSEQ  TICKS                   ;7. TICK?
+000474 D???           00685         BRA     POWER_OFF_I2    ;NEIN->
+000476 9096           00686         BCF             TRISE,RE0               ;JA->LED=ON
+000478                00687 POWER_OFF_I2
+000478 0E1E           00688         MOVLW   .30                             ; WENIGER ALS 30 SEC SEIT LETZTEM SPANNUNGSFEHLER?
+00047A 6147           00689         CPFSLT  U_ERR_TIME
+00047C D???           00690         BRA     PINGS                   ;NEIN->
+00047E 0E05           00691         MOVLW   .5
+000480 6341           00692         CPFSEQ  TICKS                   ;5. TICK?
+000482 D???           00693         BRA     PINGS                   ;NEIN->
+000484 9096           00694         BCF             TRISE,RE0               ;JA->LED=ON
+000486                00695 PINGS
+000486 EC?? F???      00696         CALL    TASTE                   ;UP TASTE
+                      00697 ; TASTE LOSGELASSEN?
+00048A 0E04           00698         MOVLW   RESET_OFF_TIME
+MPASM  5.35                      FIREBEE1.ASM   10-1-2010  13:06:42         PAGE 15
+
+
+LOC  OBJECT CODE     LINE SOURCE TEXT
+  VALUE
+
+00048C 6543           00699         CPFSGT  TASTE_OFF_TIME  ;TASTE LÄNGER ALS 2 SEC LOSGELASSEN?
+00048E D???           00700         BRA             PINGW                   ;NEIN->
+000490 8E95           00701         BSF     TRISD,RD7               ;JA-> #RSTI INAKTIV =HIGH
+000492 A095           00702         BTFSS   TRISD,RD0               ;POWER ON?
+000494 EC?? F???      00703         CALL    SERIAL_ON               ;ja->SERIELL EINSCHALTEN
+                      00704 ;--TICKS=125MS
+000498                00705 PINGW
+000498 2B41           00706         INCF    TICKS                   ;inc ticks
+00049A A095           00707         BTFSS   TRISD,RD0               ;POWER ON?
+00049C D???           00708         BRA             PINGS2                  ;JA->
+00049E 0E20           00709         MOVLW   20
+0004A0 6148           00710         CPFSLT  U_POWER_IN              ;LADEGERÄT ANGESCHLOSSEN?
+0004A2 D???           00711         BRA             PINGS2                  ;->JA LED HELLER
+0004A4 0EA0           00712         MOVLW   TIME_MAX                ;>=MAXIMALZEIT?
+0004A6 6147           00713         CPFSLT  U_ERR_TIME              ;SEIT SPANNUNGSFEHLER
+0004A8 8096           00714         BSF             TRISE,RE0               ;JA -> LED OFF
+0004AA                00715 PINGS2
+0004AA 0E07           00716         MOVLW   .7                              ; 7?
+0004AC 6541           00717         CPFSGT  TICKS                   
+0004AE 0010           00718         RETFIE                                  ; NEIN ->RETURN
+0004B0                00719 SEKUNDEN
+                      00720 ;led blinken POWER ON-----------------------------------------
+0004B0 A095           00721         BTFSS   TRISD,RD0               ;POWER ON?
+0004B2 9096           00722         BCF             TRISE,RE0               ;JA -> LED_ON
+                      00723 ;TIMER U_ERR ERHÖHEN
+0004B4 0EA0           00724         MOVLW   TIME_MAX                ;>=MAXIMALZEIT?
+0004B6 6547           00725         CPFSGT  U_ERR_TIME              ;SEIT SPANNUNGSFEHLER
+0004B8 2B47           00726         INCF    U_ERR_TIME              ;NEIN ERHÖHEN
+                      00727 ;SPANNUNGSFEHLER BEARBEITEN ----------------------------------------
+0004BA 0E05           00728         MOVLW   U_ERR_PW_AUS    ;POWER AUS ZEIT?
+0004BC 6347           00729         CPFSEQ  U_ERR_TIME              ;
+0004BE D???           00730         BRA             SEK_NPA                 ;NEIN
+0004C0 EC?? F???      00731         CALL    POWER_AUS               ;JA AUSSCHALTEN
+                      00732 ;--------------------------------------------------------
+0004C4                00733 SEK_NPA
+                      00734 ;SPANNUNG POWER IN MESSEN
+0004C4 0E01           00735         MOVLW   B'00000001'                     ;KANAL 0, AD ON
+0004C6 6EC2           00736         MOVWF   ADCON0                          ; 
+0004C8 82C2           00737         BSF             ADCON0,1                        ;GO
+0004CA                00738 SEK_2
+0004CA B2C2           00739         BTFSC   ADCON0,1                        ;FERTIG?
+0004CC D???           00740         BRA             SEK_2                           ;NEIN
+0004CE CFC4 F048      00741         MOVFF   ADRESH,U_POWER_IN       ;OK WERT EINTRAGEN
+                      00742 
+                      00743 ;SPANNUNG 2V5 MESSEN -> U_ERR TIMER NICHT ERHÖHEN WENN ÜBER 3.2V RESP. WIEDER -1
+0004D2 B095           00744         BTFSC   TRISD,RD0                       ;POWER ON?
+0004D4 D???           00745         BRA             SEK_4                           ;NEIN NICHT MESSEN
+                      00746 
+0004D6 0E0D           00747         MOVLW   B'00001101'                     ;KANAL 3, AD ON
+0004D8 6EC2           00748         MOVWF   ADCON0                          ; 
+0004DA 82C2           00749         BSF             ADCON0,1                        ;GO
+0004DC                00750 SEK_3
+0004DC B2C2           00751         BTFSC   ADCON0,1                        ;FERTIG?
+MPASM  5.35                      FIREBEE1.ASM   10-1-2010  13:06:42         PAGE 16
+
+
+LOC  OBJECT CODE     LINE SOURCE TEXT
+  VALUE
+
+0004DE D???           00752         BRA             SEK_3                           ;NEIN
+0004E0 0EC8           00753         MOVLW   .200                            ;UNTER 3.2V -> WENN WERT ÜBER 78%
+0004E2 60C4           00754         CPFSLT  ADRESH                          ;JA ->
+0004E4 D???           00755         BRA             SEK_4                           ;SONST WEITER
+                      00756 ;TIMER U_ERR ERHÖHEN
+0004E6 A146           00757         BTFSS   U_ERR,0                         ;SPANNUNGSERROR?
+0004E8 D???           00758         BRA             SEK_4                           ;NEIN
+0004EA 0EA0           00759         MOVLW   TIME_MAX                        ;>=MAXIMALZEIT?
+0004EC 6547           00760         CPFSGT  U_ERR_TIME                      ;SEIT SPANNUNGSFEHLER
+0004EE 0747           00761         DECF    U_ERR_TIME                      ;NEIN -> -1
+                      00762 ;-------------------------------------------------------------
+0004F0                00763 SEK_4
+0004F0 6B41           00764         CLRF    TICKS
+0004F2 2B00           00765         INCF    SECS                    ; Increment seconds
+0004F4 0E3B           00766         MOVLW   .59                     ; 60 seconds elapsed?
+0004F6 6500           00767         CPFSGT  SECS
+0004F8 0010           00768         RETFIE                                  ;RETURN
+0004FA                00769 MINUTEN
+0004FA 6B00           00770         CLRF    SECS                    ; Clear seconds
+0004FC 2B02           00771         INCF    MINS                    ; Increment minutes
+0004FE 0E3B           00772         MOVLW   .59                     ; 60 minutes elapsed?
+000500 6502           00773         CPFSGT  MINS
+000502 0010           00774         RETFIE                                  ;RETURN 
+000504                00775 STUNDEN
+000504 6B02           00776         CLRF    MINS                    ; clear minutes
+000506 2B04           00777         INCF    HOURS                   ; Increment hours
+000508 0E17           00778         MOVLW   .23                     ; 24 hours elapsed?
+00050A 6504           00779         CPFSGT  HOURS
+00050C 0010           00780         RETFIE                                  ;RETURN 
+00050E                00781 TAGE_UND_TAG_DER_WOCHE
+00050E 6B04           00782         CLRF    HOURS                   ; Reset hours
+000510 0E07           00783         MOVLW   .7
+000512 6106           00784         CPFSLT  DAY_OF_WEEK
+000514 6B06           00785         CLRF    DAY_OF_WEEK
+000516 2B06           00786         INCF    DAY_OF_WEEK
+000518 2B07           00787         INCF    DAYS
+00051A 0E1C           00788         MOVLW   .28                             
+00051C 6507           00789         CPFSGT  DAYS
+00051E 0010           00790         RETFIE                                  ;RETURN 
+000520                00791 MEHR_ALS_28_TAGE
+000520 0E02           00792         MOVLW   .2
+000522 6308           00793         CPFSEQ  MONTHS                  ;FEB?
+000524 D???           00794         BRA             NOT_FEB                 ;NEIN->
+000526                00795 FEB
+000526 0E03           00796         MOVLW   .3
+000528 1509           00797         ANDWF   YEARS,0                 ;SCHALTJAHR
+00052A E1??           00798         BNZ             NEXT_MONTH              ;NEIN->
+00052C                00799 SCHALTJAHR
+00052C 0E1D           00800         MOVLW   .29
+00052E 6507           00801         CPFSGT  DAYS
+000530 0010           00802         RETFIE                                  ;RETURN 
+000532                00803 NEXT_MONTH
+000532 0E01           00804         MOVLW   .1
+MPASM  5.35                      FIREBEE1.ASM   10-1-2010  13:06:42         PAGE 17
+
+
+LOC  OBJECT CODE     LINE SOURCE TEXT
+  VALUE
+
+000534 6F07           00805         MOVWF   DAYS
+000536 2B08           00806         INCF    MONTHS
+000538 0E12           00807         MOVLW   12
+00053A 6508           00808         CPFSGT  MONTHS
+00053C 0010           00809         RETFIE                                  ;RETURN 
+00053E                00810 YEAR    
+00053E 0E01           00811         MOVLW   .1
+000540 6F08           00812         MOVWF   MONTHS
+000542 2B09           00813         INCF    YEARS
+000544 0010           00814         RETFIE                                  ;RETURN 
+000546                00815 NOT_FEB
+000546 0E1E           00816         MOVLW   .30
+000548 6507           00817         CPFSGT  DAYS
+00054A 0010           00818         RETFIE                          
+00054C                00819 MEHR_ALS_30_TAGE
+00054C 0E04           00820         MOVLW   .4                              ;APRIL?
+00054E 6308           00821         CPFSEQ  MONTHS                  ;SKIP
+000550 D???           00822         BRA             NOT_APRIL 
+000552 D???           00823         BRA             NEXT_MONTH              ;APRIL->
+000554                00824 NOT_APRIL
+000554 0E06           00825         MOVLW   .6                              ;JUNI?
+000556 6308           00826         CPFSEQ  MONTHS
+000558 D???           00827         BRA             NOT_JUNI 
+00055A D???           00828         BRA             NEXT_MONTH              ;JUNI->
+00055C                00829 NOT_JUNI
+00055C 0E09           00830         MOVLW   .9                              ;SEPTEMBER?
+00055E 6308           00831         CPFSEQ  MONTHS   
+000560 D???           00832         BRA             NOT_SEP 
+000562 D???           00833         BRA             NEXT_MONTH              ;SEPTEMBER->     
+000564                00834 NOT_SEP
+000564 0E0B           00835         MOVLW   .11                             ;NOVEMBER?
+000566 6308           00836         CPFSEQ  MONTHS                  ;SKIP
+000568 0010           00837         RETFIE                                  ;SIND MONATE MIT 31 TAGEN-> 
+00056A D???           00838         BRA             NEXT_MONTH              ;SONST NOVEMBER->
+                      00839 ;**********************************************************************************************"""""""""
+                            """"
+                      00840 ; ENDE MAIN 
+                      00841 ;**********************************************************************************************"""""""""
+                            """"
+                      00842 ;**********************************************************************************************"""""""""
+                            """"
+                      00843 ; EXTERN_SUBOUTINES FOGEN AB 0x1000 DIE SPÄTER EINPROGRAMMIERT WERDEN
+                      00844 ;**********************************************************************************************"""""""""
+                            """"
+                      00845         end
+MPASM  5.35                      FIREBEE1.ASM   10-1-2010  13:06:42         PAGE 18
+
+
+SYMBOL TABLE
+  LABEL                             VALUE 
+
+A                                 00000000
+ABDEN                             00000000
+ABDOVF                            00000007
+ACCESS                            00000000
+ACKDT                             00000005
+ACKEN                             00000004
+ACKSTAT                           00000006
+ACQT0                             00000003
+ACQT1                             00000004
+ACQT2                             00000005
+ADCON0                            00000FC2
+ADCON1                            00000FC1
+ADCON2                            00000FC0
+ADCS0                             00000000
+ADCS1                             00000001
+ADCS2                             00000002
+ADDEN                             00000003
+ADEN                              00000003
+ADFM                              00000007
+ADIE                              00000006
+ADIF                              00000006
+ADIP                              00000006
+ADON                              00000000
+ADRES                             00000FC3
+ADRESH                            00000FC4
+ADRESL                            00000FC3
+AD_ISR                            0000044C
+AD_KANAL                          00000045
+AN0                               00000000
+AN1                               00000001
+AN10                              00000001
+AN11                              00000004
+AN12                              00000000
+AN2                               00000002
+AN3                               00000003
+AN4                               00000005
+AN5                               00000000
+AN6                               00000001
+AN7                               00000002
+AN8                               00000002
+AN9                               00000003
+BANKED                            00000001
+BAUDCON                           00000FB8
+BAUDCTL                           00000FB8
+BCLIE                             00000003
+BCLIF                             00000003
+BCLIP                             00000003
+BF                                00000000
+BGST                              00000005
+BOR                               00000000
+BRG16                             00000003
+BRGH                              00000002
+BSR                               00000FE0
+MPASM  5.35                      FIREBEE1.ASM   10-1-2010  13:06:42         PAGE 19
+
+
+SYMBOL TABLE
+  LABEL                             VALUE 
+
+C                                 00000000
+C1INV                             00000004
+C1OUT                             00000006
+C2INV                             00000005
+C2OUT                             00000007
+CCP1                              00000002
+CCP1CON                           00000FBD
+CCP1IE                            00000002
+CCP1IF                            00000002
+CCP1IP                            00000002
+CCP1M0                            00000000
+CCP1M1                            00000001
+CCP1M2                            00000002
+CCP1M3                            00000003
+CCP1X                             00000005
+CCP1Y                             00000004
+CCP2CON                           00000FBA
+CCP2IE                            00000000
+CCP2IF                            00000000
+CCP2IP                            00000000
+CCP2M0                            00000000
+CCP2M1                            00000001
+CCP2M2                            00000002
+CCP2M3                            00000003
+CCP2X                             00000005
+CCP2Y                             00000004
+CCP2_PORTB                        00000003
+CCP2_PORTC                        00000001
+CCPR1                             00000FBE
+CCPR1H                            00000FBF
+CCPR1L                            00000FBE
+CCPR2                             00000FBB
+CCPR2H                            00000FBC
+CCPR2L                            00000FBB
+CFGS                              00000006
+CHS0                              00000002
+CHS1                              00000003
+CHS2                              00000004
+CHS3                              00000005
+CIS                               00000003
+CK                                00000006
+CKE                               00000006
+CKP                               00000004
+CLKI                              00000007
+CLKO                              00000006
+CLK_ACTIV                         00000072
+CLK_SLEEP                         00000012
+CM0                               00000000
+CM1                               00000001
+CM2                               00000002
+CMCON                             00000FB4
+CMIE                              00000006
+CMIF                              00000006
+MPASM  5.35                      FIREBEE1.ASM   10-1-2010  13:06:42         PAGE 20
+
+
+SYMBOL TABLE
+  LABEL                             VALUE 
+
+CMIP                              00000006
+CREN                              00000004
+CS                                00000002
+CSRC                              00000007
+CVR0                              00000000
+CVR1                              00000001
+CVR2                              00000002
+CVR3                              00000003
+CVRCON                            00000FB5
+CVREF                             00000002
+CVREN                             00000007
+CVROE                             00000006
+CVRR                              00000005
+CVRSS                             00000004
+D                                 00000005
+DAYS                              00000007
+DAY_OF_WEEK                       00000006
+DC                                00000001
+DC1B0                             00000004
+DC1B1                             00000005
+DC2B0                             00000004
+DC2B1                             00000005
+DDRA                              TRISA
+DDRB                              TRISB
+DDRC                              TRISC
+DDRD                              TRISD
+DDRE                              TRISE
+DONE                              00000001
+D_A                               00000005
+EAPIR1                            0000004E
+EAPIR2                            0000004F
+ECCP1AS                           00000FB6
+ECCPAS0                           00000004
+ECCPAS1                           00000005
+ECCPAS2                           00000006
+ECCPASE                           00000007
+EEADR                             00000FA9
+EECON1                            00000FA6
+EECON2                            00000FA7
+EEDATA                            00000FA8
+EEIE                              00000004
+EEIF                              00000004
+EEIP                              00000004
+EEPGD                             00000007
+EXTERN_INTERRUPTS                 00002002
+EXTERN_INT_ADR                    00002000
+EXTERN_SUBROUTINES                00002012
+EXTERN_SUB_ADR                    00002010
+EXT_CODE                          000000FB
+EXT_SUB_GO                        00000004
+EXT_SUB_STOP                      00000005
+FAST                              00000001
+FEB                               00000526
+MPASM  5.35                      FIREBEE1.ASM   10-1-2010  13:06:42         PAGE 21
+
+
+SYMBOL TABLE
+  LABEL                             VALUE 
+
+FERR                              00000002
+FLTS                              00000002
+FREE                              00000004
+FSR0                              00000000
+FSR0H                             00000FEA
+FSR0L                             00000FE9
+FSR1                              00000001
+FSR1H                             00000FE2
+FSR1L                             00000FE1
+FSR2                              00000002
+FSR2H                             00000FDA
+FSR2L                             00000FD9
+GCEN                              00000007
+GIE                               00000007
+GIEH                              00000007
+GIEL                              00000006
+GO                                00000001
+GO_DONE                           00000001
+GO_INT                            0000004D
+GO_SUB                            0000004C
+HLVDCON                           00000FD2
+HLVDEN                            00000004
+HLVDIE                            00000002
+HLVDIF                            00000002
+HLVDIP                            00000002
+HLVDL0                            00000000
+HLVDL1                            00000001
+HLVDL2                            00000002
+HLVDL3                            00000003
+HLVD_ISR                          00000424
+HLVD_LE                           0000043C
+HOURS                             00000004
+HOURS_ALARM                       00000005
+IBF                               00000007
+IBOV                              00000005
+IDLEN                             00000007
+INDF0                             00000FEF
+INDF1                             00000FE7
+INDF2                             00000FDF
+INT0                              00000000
+INT0E                             00000004
+INT0F                             00000001
+INT0IE                            00000004
+INT0IF                            00000001
+INT1                              00000001
+INT1E                             00000003
+INT1F                             00000000
+INT1IE                            00000003
+INT1IF                            00000000
+INT1IP                            00000006
+INT1P                             00000006
+INT2                              00000002
+INT2E                             00000004
+MPASM  5.35                      FIREBEE1.ASM   10-1-2010  13:06:42         PAGE 22
+
+
+SYMBOL TABLE
+  LABEL                             VALUE 
+
+INT2F                             00000001
+INT2IE                            00000004
+INT2IF                            00000001
+INT2IP                            00000007
+INT2P                             00000007
+INTCON                            00000FF2
+INTCON2                           00000FF1
+INTCON3                           00000FF0
+INTEDG0                           00000006
+INTEDG1                           00000005
+INTEDG2                           00000004
+INTSRC                            00000007
+INT_HANDLER                       00000018
+IOFS                              00000002
+IPEN                              00000007
+IPR1                              00000F9F
+IPR2                              00000FA2
+IRCF0                             00000004
+IRCF1                             00000005
+IRCF2                             00000006
+IRVST                             00000005
+IVRST                             00000005
+KALT_START                        00000100
+KBI0                              00000004
+KBI1                              00000005
+KBI2                              00000006
+KBI3                              00000007
+LADESTROM                         000001D2
+LATA                              00000F89
+LATA0                             00000000
+LATA1                             00000001
+LATA2                             00000002
+LATA3                             00000003
+LATA4                             00000004
+LATA5                             00000005
+LATA6                             00000006
+LATA7                             00000007
+LATB                              00000F8A
+LATB0                             00000000
+LATB1                             00000001
+LATB2                             00000002
+LATB3                             00000003
+LATB4                             00000004
+LATB5                             00000005
+LATB6                             00000006
+LATB7                             00000007
+LATC                              00000F8B
+LATC0                             00000000
+LATC1                             00000001
+LATC2                             00000002
+LATC3                             00000003
+LATC4                             00000004
+LATC5                             00000005
+MPASM  5.35                      FIREBEE1.ASM   10-1-2010  13:06:42         PAGE 23
+
+
+SYMBOL TABLE
+  LABEL                             VALUE 
+
+LATC6                             00000006
+LATC7                             00000007
+LATD                              00000F8C
+LATD0                             00000000
+LATD1                             00000001
+LATD2                             00000002
+LATD3                             00000003
+LATD4                             00000004
+LATD5                             00000005
+LATD6                             00000006
+LATD7                             00000007
+LATE                              00000F8D
+LATE0                             00000000
+LATE1                             00000001
+LATE2                             00000002
+LS_OFF_POWER                      000001DA
+LS_ON_POWER                       000001D6
+LVDCON                            00000FD2
+LVDEN                             00000004
+LVDIE                             00000002
+LVDIF                             00000002
+LVDIN                             00000005
+LVDIP                             00000002
+LVDL0                             00000000
+LVDL1                             00000001
+LVDL2                             00000002
+LVDL3                             00000003
+LVV0                              00000000
+LVV1                              00000001
+LVV2                              00000002
+LVV3                              00000003
+MAIN                              0000019E
+MAIN2                             000001AE
+MCLR                              00000003
+MEHR_ALS_28_TAGE                  00000520
+MEHR_ALS_30_TAGE                  0000054C
+MINS                              00000002
+MINS_ALRAM                        00000003
+MINUTEN                           000004FA
+MONTHS                            00000008
+N                                 00000004
+NEXT_MONTH                        00000532
+NON_SYNC                          000003D2
+NOT_A                             00000005
+NOT_ADDRESS                       00000005
+NOT_APRIL                         00000554
+NOT_BOR                           00000000
+NOT_CS                            00000002
+NOT_DONE                          00000001
+NOT_FEB                           00000546
+NOT_JUNI                          0000055C
+NOT_MCLR                          00000003
+NOT_PD                            00000002
+MPASM  5.35                      FIREBEE1.ASM   10-1-2010  13:06:42         PAGE 24
+
+
+SYMBOL TABLE
+  LABEL                             VALUE 
+
+NOT_POR                           00000001
+NOT_RBPU                          00000007
+NOT_RD                            00000000
+NOT_RI                            00000004
+NOT_SEP                           00000564
+NOT_SS                            00000005
+NOT_T1SYNC                        00000002
+NOT_T3SYNC                        00000002
+NOT_TO                            00000003
+NOT_W                             00000002
+NOT_WR                            00000001
+NOT_WRITE                         00000002
+NO_PROG                           000003AC
+OBF                               00000006
+OERR                              00000001
+OFF_TIME                          00000014
+ON_TIME                           00000002
+OSC1                              00000007
+OSC2                              00000006
+OSCCON                            00000FD3
+OSCFIE                            00000007
+OSCFIF                            00000007
+OSCFIP                            00000007
+OSCTUNE                           00000F9B
+OSTS                              00000003
+OV                                00000003
+P                                 00000004
+P1B                               00000005
+P1C                               00000006
+P1D                               00000007
+P1M0                              00000006
+P1M1                              00000007
+PC                                00000FF9
+PCFG0                             00000000
+PCFG1                             00000001
+PCFG2                             00000002
+PCFG3                             00000003
+PCL                               00000FF9
+PCLATH                            00000FFA
+PCLATU                            00000FFB
+PD                                00000002
+PDC0                              00000000
+PDC1                              00000001
+PDC2                              00000002
+PDC3                              00000003
+PDC4                              00000004
+PDC5                              00000005
+PDC6                              00000006
+PEIE                              00000006
+PEN                               00000002
+PGC                               00000006
+PGD                               00000007
+PGM                               00000005
+MPASM  5.35                      FIREBEE1.ASM   10-1-2010  13:06:42         PAGE 25
+
+
+SYMBOL TABLE
+  LABEL                             VALUE 
+
+PIE1                              00000F9D
+PIE2                              00000FA0
+PINGS                             00000486
+PINGS2                            000004AA
+PINGW                             00000498
+PIR1                              00000F9E
+PIR2                              00000FA1
+PLLEN                             00000006
+PLUSW0                            00000FEB
+PLUSW1                            00000FE3
+PLUSW2                            00000FDB
+POR                               00000001
+PORTA                             00000F80
+PORTB                             00000F81
+PORTC                             00000F82
+PORTD                             00000F83
+PORTE                             00000F84
+POSTDEC0                          00000FED
+POSTDEC1                          00000FE5
+POSTDEC2                          00000FDD
+POSTINC0                          00000FEE
+POSTINC1                          00000FE6
+POSTINC2                          00000FDE
+POWER_AUS                         000001C2
+POWER_EIN                         000001B4
+POWER_OFF_I                       0000046A
+POWER_OFF_I2                      00000478
+POWER_ON_TIME                     00000044
+PR2                               00000FCB
+PREINC0                           00000FEC
+PREINC1                           00000FE4
+PREINC2                           00000FDC
+PRG_OK_PIC                        00000022
+PROD                              00000FF3
+PRODH                             00000FF4
+PRODL                             00000FF3
+PROGRAM_MEMORY                    0000039A
+PRSEN                             00000007
+PSA                               00000003
+PSP0                              00000000
+PSP1                              00000001
+PSP2                              00000002
+PSP3                              00000003
+PSP4                              00000004
+PSP5                              00000005
+PSP6                              00000006
+PSP7                              00000007
+PSPIE                             00000007
+PSPIF                             00000007
+PSPIP                             00000007
+PSPMODE                           00000004
+PSSAC0                            00000002
+PSSAC1                            00000003
+MPASM  5.35                      FIREBEE1.ASM   10-1-2010  13:06:42         PAGE 26
+
+
+SYMBOL TABLE
+  LABEL                             VALUE 
+
+PSSBD0                            00000000
+PSSBD1                            00000001
+PWM1CON                           00000FB7
+R                                 00000002
+RA0                               00000000
+RA1                               00000001
+RA2                               00000002
+RA3                               00000003
+RA4                               00000004
+RA5                               00000005
+RA6                               00000006
+RA7                               00000007
+RB0                               00000000
+RB1                               00000001
+RB2                               00000002
+RB3                               00000003
+RB4                               00000004
+RB5                               00000005
+RB6                               00000006
+RB7                               00000007
+RBIE                              00000003
+RBIF                              00000000
+RBIP                              00000000
+RBPU                              00000007
+RC0                               00000000
+RC1                               00000001
+RC2                               00000002
+RC3                               00000003
+RC4                               00000004
+RC5                               00000005
+RC6                               00000006
+RC7                               00000007
+RCEN                              00000003
+RCIDL                             00000006
+RCIE                              00000005
+RCIF                              00000005
+RCIP                              00000005
+RCMT                              00000006
+RCON                              00000FD0
+RCREG                             00000FAE
+RCSTA                             00000FAB
+RD                                00000000
+RD0                               00000000
+RD1                               00000001
+RD16                              00000007
+RD2                               00000002
+RD3                               00000003
+RD4                               00000004
+RD5                               00000005
+RD6                               00000006
+RD7                               00000007
+RE0                               00000000
+RE1                               00000001
+MPASM  5.35                      FIREBEE1.ASM   10-1-2010  13:06:42         PAGE 27
+
+
+SYMBOL TABLE
+  LABEL                             VALUE 
+
+RE2                               00000002
+RE3                               00000003
+READ_BLOCK                        000000A1
+REGA                              0000000A
+REGB                              0000000B
+REGC                              0000000C
+REGD                              0000000D
+REQ_BLOCK                         000000A0
+REQ_RTCD_FROM_MCF                 00000002
+REQ_RTCD_FROM_PIC                 00000001
+RESETEN                           00000256
+RESET_OFF_TIME                    00000004
+RESET_ON_TIME                     00000002
+RI                                00000004
+RSEN                              00000001
+RTCD_FROM_MCF                     00000082
+RTCD_FROM_PIC                     00000081
+RTC_ISR                           00000450
+RTC_RAM                           0000000E
+RX                                00000007
+RX9                               00000006
+RX9D                              00000000
+RXDTP                             00000005
+RX_B                              00000049
+RX_BUFFER                         00000100
+RX_ISR                            00000288
+RX_ISR1                           000002A4
+RX_ISR2                           000002B0
+RX_ISR3                           000002C8
+RX_ISR4                           000002F6
+RX_ISR5                           00000304
+RX_ISR6                           00000312
+RX_ISR7                           00000350
+RX_ISR8                           000003B0
+RX_ISR9                           000003BC
+RX_RB3B2                          00000334
+RX_RB3BOK                         00000322
+RX_STATUS                         0000004A
+RX_SYNC2                          000003D8
+RX_SYNC3                          000003EA
+RX_SYNC4                          000003FC
+RX_SYNC_START                     000003C0
+RX_WAIT1                          00000408
+RX_WAIT2                          00000410
+RX_WAIT3                          00000418
+R_W                               00000002
+S                                 00000003
+SBOREN                            00000006
+SCHALTJAHR                        0000052C
+SCK                               00000003
+SCKP                              00000004
+SCL                               00000003
+SCS0                              00000000
+MPASM  5.35                      FIREBEE1.ASM   10-1-2010  13:06:42         PAGE 28
+
+
+SYMBOL TABLE
+  LABEL                             VALUE 
+
+SCS1                              00000001
+SDA                               00000004
+SDI                               00000004
+SDO                               00000005
+SECS                              00000000
+SECS_ALARM                        00000001
+SEKUNDEN                          000004B0
+SEK_2                             000004CA
+SEK_3                             000004DC
+SEK_4                             000004F0
+SEK_NPA                           000004C4
+SEN                               00000000
+SENDB                             00000003
+SEND_RTC_REG                      00000232
+SEND_RTC_TIME                     00000002
+SERIAL_OFF                        000001DE
+SERIAL_ON                         000001EA
+SMP                               00000007
+SP0                               00000000
+SP1                               00000001
+SP2                               00000002
+SP3                               00000003
+SP4                               00000004
+SPBRG                             00000FAF
+SPBRGH                            00000FB0
+SPEN                              00000007
+SREN                              00000005
+SS                                00000005
+SSPADD                            00000FC8
+SSPBUF                            00000FC9
+SSPCON1                           00000FC6
+SSPCON2                           00000FC5
+SSPEN                             00000005
+SSPIE                             00000003
+SSPIF                             00000003
+SSPIP                             00000003
+SSPM0                             00000000
+SSPM1                             00000001
+SSPM2                             00000002
+SSPM3                             00000003
+SSPOV                             00000006
+SSPSTAT                           00000FC7
+STATUS                            00000FD8
+STKFUL                            00000007
+STKOVF                            00000007
+STKPTR                            00000FFC
+STKUNF                            00000006
+STUNDEN                           00000504
+SWDTE                             00000000
+SWDTEN                            00000000
+SYNC                              00000004
+SYNC1                             000000FF
+SYNC1_DATA                        00000041
+MPASM  5.35                      FIREBEE1.ASM   10-1-2010  13:06:42         PAGE 29
+
+
+SYMBOL TABLE
+  LABEL                             VALUE 
+
+SYNC2                             000000FE
+SYNC2_DATA                        00000043
+SYNC3                             000000FD
+SYNC3_DATA                        00000050
+SYNC4                             000000FC
+SYNC4_DATA                        00000046
+T08BIT                            00000006
+T0CKI                             00000004
+T0CON                             00000FD5
+T0CS                              00000005
+T0IE                              00000005
+T0IF                              00000002
+T0PS0                             00000000
+T0PS1                             00000001
+T0PS2                             00000002
+T0SE                              00000004
+T13CKI                            00000000
+T1CKI                             00000000
+T1CKPS0                           00000004
+T1CKPS1                           00000005
+T1CON                             00000FCD
+T1OSCEN                           00000003
+T1OSI                             00000001
+T1OSO                             00000000
+T1RUN                             00000006
+T1SYNC                            00000002
+T2CKPS0                           00000000
+T2CKPS1                           00000001
+T2CON                             00000FCA
+T2OUTPS0                          00000003
+T2OUTPS1                          00000004
+T2OUTPS2                          00000005
+T2OUTPS3                          00000006
+T3CCP1                            00000003
+T3CCP2                            00000006
+T3CKPS0                           00000004
+T3CKPS1                           00000005
+T3CON                             00000FB1
+T3SYNC                            00000002
+TABLAT                            00000FF5
+TAGE_UND_TAG_DER_WOCHE            0000050E
+TASTE                             00000208
+TASTE_OFF_TIME                    00000043
+TASTE_ON_TIME                     00000042
+TBLPTR                            00000FF6
+TBLPTRH                           00000FF7
+TBLPTRL                           00000FF6
+TBLPTRU                           00000FF8
+TG_END                            00000250
+TG_JA                             00000222
+TG_OFF_POWER                      00000248
+TG_ON_POWER                       0000022C
+TG_ON_POWER2                      00000238
+MPASM  5.35                      FIREBEE1.ASM   10-1-2010  13:06:42         PAGE 30
+
+
+SYMBOL TABLE
+  LABEL                             VALUE 
+
+TG_ON_POWER3                      0000023E
+TICKS                             00000041
+TIMER_HB                          000000F0
+TIME_MAX                          000000A0
+TMR0H                             00000FD7
+TMR0IE                            00000005
+TMR0IF                            00000002
+TMR0IP                            00000002
+TMR0L                             00000FD6
+TMR0ON                            00000007
+TMR1CS                            00000001
+TMR1H                             00000FCF
+TMR1IE                            00000000
+TMR1IF                            00000000
+TMR1IP                            00000000
+TMR1L                             00000FCE
+TMR1ON                            00000000
+TMR2                              00000FCC
+TMR2IE                            00000001
+TMR2IF                            00000001
+TMR2IP                            00000001
+TMR2ON                            00000002
+TMR3CS                            00000001
+TMR3H                             00000FB3
+TMR3IE                            00000001
+TMR3IF                            00000001
+TMR3IP                            00000001
+TMR3L                             00000FB2
+TMR3ON                            00000000
+TO                                00000003
+TOS                               00000FFD
+TOSH                              00000FFE
+TOSL                              00000FFD
+TOSU                              00000FFF
+TRISA                             00000F92
+TRISA0                            00000000
+TRISA1                            00000001
+TRISA2                            00000002
+TRISA3                            00000003
+TRISA4                            00000004
+TRISA5                            00000005
+TRISA6                            00000006
+TRISA7                            00000007
+TRISB                             00000F93
+TRISB0                            00000000
+TRISB1                            00000001
+TRISB2                            00000002
+TRISB3                            00000003
+TRISB4                            00000004
+TRISB5                            00000005
+TRISB6                            00000006
+TRISB7                            00000007
+TRISC                             00000F94
+MPASM  5.35                      FIREBEE1.ASM   10-1-2010  13:06:42         PAGE 31
+
+
+SYMBOL TABLE
+  LABEL                             VALUE 
+
+TRISC0                            00000000
+TRISC1                            00000001
+TRISC2                            00000002
+TRISC3                            00000003
+TRISC4                            00000004
+TRISC5                            00000005
+TRISC6                            00000006
+TRISC7                            00000007
+TRISD                             00000F95
+TRISD0                            00000000
+TRISD1                            00000001
+TRISD2                            00000002
+TRISD3                            00000003
+TRISD4                            00000004
+TRISD5                            00000005
+TRISD6                            00000006
+TRISD7                            00000007
+TRISE                             00000F96
+TRISE0                            00000000
+TRISE1                            00000001
+TRISE2                            00000002
+TRMT                              00000001
+TUN0                              00000000
+TUN1                              00000001
+TUN2                              00000002
+TUN3                              00000003
+TUN4                              00000004
+TX                                00000006
+TX9                               00000006
+TX9D                              00000000
+TXCKP                             00000004
+TXEN                              00000005
+TXIE                              00000004
+TXIF                              00000004
+TXIP                              00000004
+TXREG                             00000FAD
+TXSTA                             00000FAC
+TX_BUFFER                         00000180
+TX_ISR                            0000025E
+TX_ISR1                           00000276
+TX_ISR2                           00000286
+TX_ISR_FERTIG                     0000026E
+TX_STATUS                         0000004B
+UA                                00000001
+U_ERR                             00000046
+U_ERR_PW_AUS                      00000005
+U_ERR_TIME                        00000047
+U_MIN_TO_MCF                      00000003
+U_POWER_IN                        00000048
+VCFG0                             00000004
+VCFG1                             00000005
+VDIRMAG                           00000007
+VPP                               00000003
+MPASM  5.35                      FIREBEE1.ASM   10-1-2010  13:06:42         PAGE 32
+
+
+SYMBOL TABLE
+  LABEL                             VALUE 
+
+VREFN                             00000002
+VREFP                             00000003
+W                                 00000000
+WAIT_LVDOK                        00000434
+WARTEN                            000001A8
+WCOL                              00000007
+WDTCON                            00000FD1
+WR                                00000001
+WREG                              00000FE8
+WREN                              00000002
+WRERR                             00000003
+WRITE_BLOCK                       000000A2
+WRITE_WORD_TO_HREGS               00000390
+WUE                               00000001
+YEAR                              0000053E
+YEARS                             00000009
+Z                                 00000002
+_BOREN_NOSLP_2L                   000000FD
+_BOREN_OFF_2L                     000000F9
+_BOREN_ON_2L                      000000FB
+_BOREN_SBORDIS_2L                 000000FF
+_BORV_0_2L                        000000E7
+_BORV_1_2L                        000000EF
+_BORV_2_2L                        000000F7
+_BORV_3_2L                        000000FF
+_CCP2MX_PORTBE_3H                 000000FE
+_CCP2MX_PORTC_3H                  000000FF
+_CONFIG1H                         00300001
+_CONFIG2H                         00300003
+_CONFIG2L                         00300002
+_CONFIG3H                         00300005
+_CONFIG4L                         00300006
+_CONFIG5H                         00300009
+_CONFIG5L                         00300008
+_CONFIG6H                         0030000B
+_CONFIG6L                         0030000A
+_CONFIG7H                         0030000D
+_CONFIG7L                         0030000C
+_CP0_OFF_5L                       000000FF
+_CP0_ON_5L                        000000FE
+_CP1_OFF_5L                       000000FF
+_CP1_ON_5L                        000000FD
+_CP2_OFF_5L                       000000FF
+_CP2_ON_5L                        000000FB
+_CP3_OFF_5L                       000000FF
+_CP3_ON_5L                        000000F7
+_CPB_OFF_5H                       000000FF
+_CPB_ON_5H                        000000BF
+_CPD_OFF_5H                       000000FF
+_CPD_ON_5H                        0000007F
+_DEBUG_OFF_4L                     000000FF
+_DEBUG_ON_4L                      0000007F
+_DEVID1                           003FFFFE
+MPASM  5.35                      FIREBEE1.ASM   10-1-2010  13:06:42         PAGE 33
+
+
+SYMBOL TABLE
+  LABEL                             VALUE 
+
+_DEVID2                           003FFFFF
+_EBTR0_OFF_7L                     000000FF
+_EBTR0_ON_7L                      000000FE
+_EBTR1_OFF_7L                     000000FF
+_EBTR1_ON_7L                      000000FD
+_EBTR2_OFF_7L                     000000FF
+_EBTR2_ON_7L                      000000FB
+_EBTR3_OFF_7L                     000000FF
+_EBTR3_ON_7L                      000000F7
+_EBTRB_OFF_7H                     000000FF
+_EBTRB_ON_7H                      000000BF
+_FCMEN_OFF_1H                     000000BF
+_FCMEN_ON_1H                      000000FF
+_IDLOC0                           00200000
+_IDLOC1                           00200001
+_IDLOC2                           00200002
+_IDLOC3                           00200003
+_IDLOC4                           00200004
+_IDLOC5                           00200005
+_IDLOC6                           00200006
+_IDLOC7                           00200007
+_IESO_OFF_1H                      0000007F
+_IESO_ON_1H                       000000FF
+_LPT1OSC_OFF_3H                   000000FB
+_LPT1OSC_ON_3H                    000000FF
+_LVP_OFF_4L                       000000FB
+_LVP_ON_4L                        000000FF
+_MCLRE_OFF_3H                     0000007F
+_MCLRE_ON_3H                      000000FF
+_OSC_ECIO6_1H                     000000F5
+_OSC_EC_1H                        000000F4
+_OSC_HSPLL_1H                     000000F6
+_OSC_HS_1H                        000000F2
+_OSC_INTIO67_1H                   000000F8
+_OSC_INTIO7_1H                    000000F9
+_OSC_LP_1H                        000000F0
+_OSC_RCIO6_1H                     000000F7
+_OSC_RC_1H                        000000F3
+_OSC_XT_1H                        000000F1
+_PBADEN_OFF_3H                    000000FD
+_PBADEN_ON_3H                     000000FF
+_PWRT_OFF_2L                      000000FF
+_PWRT_ON_2L                       000000FE
+_STVREN_OFF_4L                    000000FE
+_STVREN_ON_4L                     000000FF
+_WDTPS_1024_2H                    000000F5
+_WDTPS_128_2H                     000000EF
+_WDTPS_16384_2H                   000000FD
+_WDTPS_16_2H                      000000E9
+_WDTPS_1_2H                       000000E1
+_WDTPS_2048_2H                    000000F7
+_WDTPS_256_2H                     000000F1
+_WDTPS_2_2H                       000000E3
+MPASM  5.35                      FIREBEE1.ASM   10-1-2010  13:06:42         PAGE 34
+
+
+SYMBOL TABLE
+  LABEL                             VALUE 
+
+_WDTPS_32768_2H                   000000FF
+_WDTPS_32_2H                      000000EB
+_WDTPS_4096_2H                    000000F9
+_WDTPS_4_2H                       000000E5
+_WDTPS_512_2H                     000000F3
+_WDTPS_64_2H                      000000ED
+_WDTPS_8192_2H                    000000FB
+_WDTPS_8_2H                       000000E7
+_WDT_OFF_2H                       000000FE
+_WDT_ON_2H                        000000FF
+_WRT0_OFF_6L                      000000FF
+_WRT0_ON_6L                       000000FE
+_WRT1_OFF_6L                      000000FF
+_WRT1_ON_6L                       000000FD
+_WRT2_OFF_6L                      000000FF
+_WRT2_ON_6L                       000000FB
+_WRT3_OFF_6L                      000000FF
+_WRT3_ON_6L                       000000F7
+_WRTB_OFF_6H                      000000FF
+_WRTB_ON_6H                       000000BF
+_WRTC_OFF_6H                      000000FF
+_WRTC_ON_6H                       000000DF
+_WRTD_OFF_6H                      000000FF
+_WRTD_ON_6H                       0000007F
+_XINST_OFF_4L                     000000BF
+_XINST_ON_4L                      000000FF
+__18F4520                         00000001
+free                              00000040
+
+Errors   :     0
+Warnings :     0 reported,     0 suppressed
+Messages :     0 reported,     0 suppressed
+
+
\ No newline at end of file
diff --git a/FireBee/MLAB/firebee1/firebee1.map b/FireBee/MLAB/firebee1/firebee1.map
new file mode 100644
index 0000000..678b3b3
--- /dev/null
+++ b/FireBee/MLAB/firebee1/firebee1.map
@@ -0,0 +1,188 @@
+MPLINK 4.35, Linker
+Linker Map File - Created Fri Oct 01 13:06:43 2010
+
+                                 Section Info
+                  Section       Type    Address   Location Size(Bytes)
+                ---------  ---------  ---------  ---------  ---------
+             Reset_Vector       code   0x000000    program   0x000002
+                   .cinit    romdata   0x000002    program   0x000002
+             HIGH_INT_VEC       code   0x000008    program   0x000004
+              LOW_INT_VEC       code   0x000018    program   0x00004a
+                    .code       code   0x000100    program   0x00046c
+
+
+
+                              Program Memory Usage 
+                               Start         End      
+                           ---------   ---------      
+                            0x000000    0x000003      
+                            0x000008    0x00000b      
+                            0x000018    0x000061      
+                            0x000100    0x00056b      
+            1214 out of 33048 program addresses used, program memory utilization is 3%
+
+
+
+                              Symbols - Sorted by Name
+                     Name    Address   Location    Storage File                     
+                ---------  ---------  ---------  --------- ---------                
+                   AD_ISR   0x00044c    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                      FEB   0x000526    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                 HLVD_ISR   0x000424    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                  HLVD_LE   0x00043c    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+              INT_HANDLER   0x000018    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+               KALT_START   0x000100    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                LADESTROM   0x0001d2    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+             LS_OFF_POWER   0x0001da    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+              LS_ON_POWER   0x0001d6    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                     MAIN   0x00019e    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                    MAIN2   0x0001ae    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+         MEHR_ALS_28_TAGE   0x000520    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+         MEHR_ALS_30_TAGE   0x00054c    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                  MINUTEN   0x0004fa    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+               NEXT_MONTH   0x000532    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                 NON_SYNC   0x0003d2    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                NOT_APRIL   0x000554    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                  NOT_FEB   0x000546    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                 NOT_JUNI   0x00055c    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                  NOT_SEP   0x000564    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                  NO_PROG   0x0003ac    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                    PINGS   0x000486    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                   PINGS2   0x0004aa    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                    PINGW   0x000498    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                POWER_AUS   0x0001c2    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                POWER_EIN   0x0001b4    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+              POWER_OFF_I   0x00046a    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+             POWER_OFF_I2   0x000478    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+           PROGRAM_MEMORY   0x00039a    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                  RESETEN   0x000256    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                  RTC_ISR   0x000450    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                   RX_ISR   0x000288    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                  RX_ISR1   0x0002a4    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                  RX_ISR2   0x0002b0    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                  RX_ISR3   0x0002c8    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                  RX_ISR4   0x0002f6    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                  RX_ISR5   0x000304    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                  RX_ISR6   0x000312    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                  RX_ISR7   0x000350    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                  RX_ISR8   0x0003b0    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                  RX_ISR9   0x0003bc    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                 RX_RB3B2   0x000334    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                RX_RB3BOK   0x000322    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                 RX_SYNC2   0x0003d8    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                 RX_SYNC3   0x0003ea    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                 RX_SYNC4   0x0003fc    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+            RX_SYNC_START   0x0003c0    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                 RX_WAIT1   0x000408    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                 RX_WAIT2   0x000410    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                 RX_WAIT3   0x000418    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+               SCHALTJAHR   0x00052c    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                 SEKUNDEN   0x0004b0    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                    SEK_2   0x0004ca    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                    SEK_3   0x0004dc    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                    SEK_4   0x0004f0    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                  SEK_NPA   0x0004c4    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+             SEND_RTC_REG   0x000232    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+               SERIAL_OFF   0x0001de    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                SERIAL_ON   0x0001ea    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                  STUNDEN   0x000504    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+   TAGE_UND_TAG_DER_WOCHE   0x00050e    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                    TASTE   0x000208    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                   TG_END   0x000250    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                    TG_JA   0x000222    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+             TG_OFF_POWER   0x000248    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+              TG_ON_POWER   0x00022c    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+             TG_ON_POWER2   0x000238    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+             TG_ON_POWER3   0x00023e    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                   TX_ISR   0x00025e    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                  TX_ISR1   0x000276    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                  TX_ISR2   0x000286    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+            TX_ISR_FERTIG   0x00026e    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+               WAIT_LVDOK   0x000434    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                   WARTEN   0x0001a8    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+      WRITE_WORD_TO_HREGS   0x000390    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                     YEAR   0x00053e    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+
+
+
+                              Symbols - Sorted by Address
+                     Name    Address   Location    Storage File                     
+                ---------  ---------  ---------  --------- ---------                
+              INT_HANDLER   0x000018    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+               KALT_START   0x000100    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                     MAIN   0x00019e    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                   WARTEN   0x0001a8    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                    MAIN2   0x0001ae    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                POWER_EIN   0x0001b4    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                POWER_AUS   0x0001c2    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                LADESTROM   0x0001d2    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+              LS_ON_POWER   0x0001d6    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+             LS_OFF_POWER   0x0001da    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+               SERIAL_OFF   0x0001de    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                SERIAL_ON   0x0001ea    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                    TASTE   0x000208    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                    TG_JA   0x000222    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+              TG_ON_POWER   0x00022c    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+             SEND_RTC_REG   0x000232    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+             TG_ON_POWER2   0x000238    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+             TG_ON_POWER3   0x00023e    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+             TG_OFF_POWER   0x000248    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                   TG_END   0x000250    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                  RESETEN   0x000256    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                   TX_ISR   0x00025e    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+            TX_ISR_FERTIG   0x00026e    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                  TX_ISR1   0x000276    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                  TX_ISR2   0x000286    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                   RX_ISR   0x000288    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                  RX_ISR1   0x0002a4    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                  RX_ISR2   0x0002b0    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                  RX_ISR3   0x0002c8    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                  RX_ISR4   0x0002f6    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                  RX_ISR5   0x000304    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                  RX_ISR6   0x000312    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                RX_RB3BOK   0x000322    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                 RX_RB3B2   0x000334    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                  RX_ISR7   0x000350    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+      WRITE_WORD_TO_HREGS   0x000390    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+           PROGRAM_MEMORY   0x00039a    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                  NO_PROG   0x0003ac    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                  RX_ISR8   0x0003b0    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                  RX_ISR9   0x0003bc    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+            RX_SYNC_START   0x0003c0    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                 NON_SYNC   0x0003d2    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                 RX_SYNC2   0x0003d8    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                 RX_SYNC3   0x0003ea    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                 RX_SYNC4   0x0003fc    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                 RX_WAIT1   0x000408    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                 RX_WAIT2   0x000410    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                 RX_WAIT3   0x000418    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                 HLVD_ISR   0x000424    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+               WAIT_LVDOK   0x000434    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                  HLVD_LE   0x00043c    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                   AD_ISR   0x00044c    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                  RTC_ISR   0x000450    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+              POWER_OFF_I   0x00046a    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+             POWER_OFF_I2   0x000478    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                    PINGS   0x000486    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                    PINGW   0x000498    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                   PINGS2   0x0004aa    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                 SEKUNDEN   0x0004b0    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                  SEK_NPA   0x0004c4    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                    SEK_2   0x0004ca    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                    SEK_3   0x0004dc    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                    SEK_4   0x0004f0    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                  MINUTEN   0x0004fa    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                  STUNDEN   0x000504    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+   TAGE_UND_TAG_DER_WOCHE   0x00050e    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+         MEHR_ALS_28_TAGE   0x000520    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                      FEB   0x000526    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+               SCHALTJAHR   0x00052c    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+               NEXT_MONTH   0x000532    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                     YEAR   0x00053e    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                  NOT_FEB   0x000546    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+         MEHR_ALS_30_TAGE   0x00054c    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                NOT_APRIL   0x000554    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                 NOT_JUNI   0x00055c    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+                  NOT_SEP   0x000564    program     static C:\FireBee\MLAB\firebee1\firebee1.asm
+
+
diff --git a/FireBee/MLAB/firebee1/firebee1.mcp b/FireBee/MLAB/firebee1/firebee1.mcp
new file mode 100644
index 0000000..45e7dcc
--- /dev/null
+++ b/FireBee/MLAB/firebee1/firebee1.mcp
@@ -0,0 +1,53 @@
+[HEADER]
+magic_cookie={66E99B07-E706-4689-9E80-9B2582898A13}
+file_version=1.0
+device=PIC18F4520
+[PATH_INFO]
+BuildDirPolicy=BuildDirIsProjectDir
+dir_src=
+dir_bin=
+dir_tmp=
+dir_sin=
+dir_inc=
+dir_lib=
+dir_lkr=
+[CAT_FILTERS]
+filter_src=*.asm
+filter_inc=*.h;*.inc
+filter_obj=*.o
+filter_lib=*.lib
+filter_lkr=*.lkr
+[CAT_SUBFOLDERS]
+subfolder_src=
+subfolder_inc=
+subfolder_obj=
+subfolder_lib=
+subfolder_lkr=
+[FILE_SUBFOLDERS]
+file_000=.
+file_001=.
+[GENERATED_FILES]
+file_000=no
+file_001=no
+[OTHER_FILES]
+file_000=no
+file_001=no
+[FILE_INFO]
+file_000=firebee1.asm
+file_001=C:\Program Files (x86)\Microchip\MPASM Suite\LKR\18f4520_g.lkr
+[SUITE_INFO]
+suite_guid={6B3DAA78-59C1-46DD-B6AA-DBDAE4E06484}
+suite_state=
+[TOOL_SETTINGS]
+TS{DD2213A8-6310-47B1-8376-9430CDFC013F}=
+TS{BFD27FBA-4A02-4C0E-A5E5-B812F3E7707C}=/o"$(BINDIR_)$(TARGETBASE).cof" /M"$(BINDIR_)$(TARGETBASE).map" /W
+TS{ADE93A55-C7C7-4D4D-A4BA-59305F7D0391}=
+[INSTRUMENTED_TRACE]
+enable=0
+transport=0
+format=0
+[CUSTOM_BUILD]
+Pre-Build=
+Pre-BuildEnabled=1
+Post-Build=
+Post-BuildEnabled=1
diff --git a/FireBee/MLAB/firebee1/firebee1.mcs b/FireBee/MLAB/firebee1/firebee1.mcs
new file mode 100644
index 0000000..242fa7b
--- /dev/null
+++ b/FireBee/MLAB/firebee1/firebee1.mcs
@@ -0,0 +1,71 @@
+[Header]
+MagicCookie={0b13fe8c-dfe0-40eb-8900-6712719559a7}
+Version=1.0
+[File000]
+Location=C:\FireBee\MLAB\firebee1\firebee1.o
+Folder=Intermediary
+DeviceName=PIC18F4520
+LanguageToolSuiteID={6B3DAA78-59C1-46DD-B6AA-DBDAE4E06484}
+LanguageToolID={49D3CA3F-D9A3-4518-9943-226A347E8CC7}
+LanguageToolLocation=C:\Program Files (x86)\Microchip\MPASM Suite\MPASMWIN.exe
+PPAD=$(BINDIR)||$(TMPDIR)||$(AINDIR)||$(INCDIR)||$(LIBDIR)||$(LKRDIR)||
+SOLK=<src>|firebee1.asm||<obj>||<lib>||<lkr>|C:\Program Files (x86)\Microchip\MPASM Suite\LKR\18f4520_g.lkr||
+SuiteArgsString=
+ToolArgsString=
+TraceCmdString=
+DebugOptions=
+[File001]
+Location=C:\FireBee\MLAB\firebee1\firebee1.err
+Folder=Intermediary
+DeviceName=PIC18F4520
+LanguageToolSuiteID={6B3DAA78-59C1-46DD-B6AA-DBDAE4E06484}
+LanguageToolID={49D3CA3F-D9A3-4518-9943-226A347E8CC7}
+LanguageToolLocation=C:\Program Files (x86)\Microchip\MPASM Suite\MPASMWIN.exe
+PPAD=$(BINDIR)||$(TMPDIR)||$(AINDIR)||$(INCDIR)||$(LIBDIR)||$(LKRDIR)||
+SOLK=<src>|firebee1.asm||<obj>||<lib>||<lkr>|C:\Program Files (x86)\Microchip\MPASM Suite\LKR\18f4520_g.lkr||
+SuiteArgsString=
+ToolArgsString=
+TraceCmdString=
+DebugOptions=
+[File002]
+Location=C:\FireBee\MLAB\firebee1\firebee1.lst
+Folder=Output
+DeviceName=PIC18F4520
+LanguageToolSuiteID={6B3DAA78-59C1-46DD-B6AA-DBDAE4E06484}
+LanguageToolID={49D3CA3F-D9A3-4518-9943-226A347E8CC7}
+LanguageToolLocation=C:\Program Files (x86)\Microchip\MPASM Suite\MPASMWIN.exe
+PPAD=$(BINDIR)||$(TMPDIR)||$(AINDIR)||$(INCDIR)||$(LIBDIR)||$(LKRDIR)||
+SOLK=<src>|firebee1.asm||<obj>||<lib>||<lkr>|C:\Program Files (x86)\Microchip\MPASM Suite\LKR\18f4520_g.lkr||
+SuiteArgsString=
+ToolArgsString=
+TraceCmdString=
+DebugOptions=
+[File003]
+Location=C:\FireBee\MLAB\firebee1\firebee1.cof
+Folder=Output
+DeviceName=PIC18F4520
+LanguageToolSuiteID={6B3DAA78-59C1-46DD-B6AA-DBDAE4E06484}
+LanguageToolID={96C98149-AA1B-4CF9-B967-FAE79CAB663C}
+LanguageToolLocation=C:\Program Files (x86)\Microchip\MPASM Suite\mplink.exe
+PPAD=$(BINDIR)||$(TMPDIR)||$(AINDIR)||$(INCDIR)||$(LIBDIR)||$(LKRDIR)||
+SOLK=<src>|firebee1.asm||<obj>||<lib>||<lkr>|C:\Program Files (x86)\Microchip\MPASM Suite\LKR\18f4520_g.lkr||
+SuiteArgsString=
+ToolArgsString=/o"$(BINDIR_)$(TARGETBASE).cof" /M"$(BINDIR_)$(TARGETBASE).map" /W
+TraceCmdString=
+DebugOptions=
+[File004]
+Location=C:\FireBee\MLAB\firebee1\firebee1.hex
+Folder=Output
+DeviceName=PIC18F4520
+LanguageToolSuiteID={6B3DAA78-59C1-46DD-B6AA-DBDAE4E06484}
+LanguageToolID={96C98149-AA1B-4CF9-B967-FAE79CAB663C}
+LanguageToolLocation=C:\Program Files (x86)\Microchip\MPASM Suite\mplink.exe
+PPAD=$(BINDIR)||$(TMPDIR)||$(AINDIR)||$(INCDIR)||$(LIBDIR)||$(LKRDIR)||
+SOLK=<src>|firebee1.asm||<obj>||<lib>||<lkr>|C:\Program Files (x86)\Microchip\MPASM Suite\LKR\18f4520_g.lkr||
+SuiteArgsString=
+ToolArgsString=/o"$(BINDIR_)$(TARGETBASE).cof" /M"$(BINDIR_)$(TARGETBASE).map" /W
+TraceCmdString=
+DebugOptions=
+[TOOL_LOC_STAMPS]
+tool_loc{49D3CA3F-D9A3-4518-9943-226A347E8CC7}=C:\Program Files (x86)\Microchip\MPASM Suite\MPASMWIN.exe
+tool_loc{96C98149-AA1B-4CF9-B967-FAE79CAB663C}=C:\Program Files (x86)\Microchip\MPASM Suite\mplink.exe
diff --git a/FireBee/MLAB/firebee1/firebee1.mcw b/FireBee/MLAB/firebee1/firebee1.mcw
new file mode 100644
index 0000000..74deeeb
Binary files /dev/null and b/FireBee/MLAB/firebee1/firebee1.mcw differ
diff --git a/FireBee/MLAB/firebee1/firebeei1.map b/FireBee/MLAB/firebee1/firebeei1.map
new file mode 100644
index 0000000..e12b3b5
--- /dev/null
+++ b/FireBee/MLAB/firebee1/firebeei1.map
@@ -0,0 +1,156 @@
+MPLINK 4.33, Linker
+Linker Map File - Created Mon Jan 11 14:35:58 2010
+
+                                 Section Info
+                  Section       Type    Address   Location Size(Bytes)
+                ---------  ---------  ---------  ---------  ---------
+             Reset_Vector       code   0x000000    program   0x000004
+                   .cinit    romdata   0x000004    program   0x000002
+              LOW_INT_VEC       code   0x000018    program   0x00004a
+                    .code       code   0x000100    program   0x00033c
+
+
+
+                              Program Memory Usage 
+                               Start         End      
+                           ---------   ---------      
+                            0x000000    0x000005      
+                            0x000018    0x000061      
+                            0x000100    0x00043b      
+            908 out of 33048 program addresses used, program memory utilization is 2%
+
+
+
+                              Symbols - Sorted by Name
+                     Name    Address   Location    Storage File                     
+                ---------  ---------  ---------  --------- ---------                
+                   AD_ISR   0x000326    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                      FEB   0x0003ee    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                 HLVD_ISR   0x000300    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                  HLVD_LE   0x00031a    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+              INT_HANDLER   0x00001e    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+             INT_HANDLER2   0x00002e    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+               KALT_START   0x000100    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                LADESTROM   0x0001d2    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+             LS_OFF_POWER   0x0001de    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+              LS_ON_POWER   0x0001d8    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                     MAIN   0x00019e    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+         MEHR_ALS_28_TAGE   0x0003e6    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+         MEHR_ALS_30_TAGE   0x000414    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                  MINUTEN   0x0003c0    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+               NEXT_MONTH   0x0003fa    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                 NON_SYNC   0x0002ae    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                NOT_APRIL   0x00041e    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                  NOT_FEB   0x00040e    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                 NOT_JUNI   0x000428    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                  NOT_SEP   0x000432    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                    PINGS   0x000368    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                   PINGS2   0x000380    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                POWER_AUS   0x0001c0    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                POWER_EIN   0x0001a6    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+              POWER_OFF_I   0x000346    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+             POWER_OFF_I2   0x000356    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                   RC_ISR   0x000256    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                  RC_ISR1   0x000268    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                  RC_ISR2   0x000274    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                   RC_RFM   0x000290    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                  RC_RRFP   0x000280    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                 RC_SYNC2   0x0002b4    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                 RC_SYNC3   0x0002c6    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                 RC_SYNC4   0x0002d8    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+            RC_SYNC_START   0x00029c    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                 RC_UNBEK   0x00027c    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                 RC_WAIT1   0x0002e4    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                 RC_WAIT2   0x0002ec    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                 RC_WAIT3   0x0002f4    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                  RESETEN   0x000232    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                  RTC_ISR   0x000326    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+               SCHALTJAHR   0x0003f4    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                 SEKUNDEN   0x000386    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                    SEK_2   0x0003ac    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                  SEK_NPA   0x00039c    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+             SEND_RTC_REG   0x00020c    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                  STUNDEN   0x0003ca    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+   TAGE_UND_TAG_DER_WOCHE   0x0003d4    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                    TASTE   0x0001e4    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                   TG_END   0x00022c    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                    TG_JA   0x0001fa    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+             TG_OFF_POWER   0x000224    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+              TG_ON_POWER   0x000206    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+             TG_ON_POWER2   0x000212    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+             TG_ON_POWER3   0x000218    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                   TX_ISR   0x00023c    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                  TX_ISR1   0x000254    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+            TX_ISR_FERTIG   0x00024c    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+               WAIT_LVDOK   0x000312    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                   WARTEN   0x0001a0    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                     YEAR   0x000406    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+
+
+
+                              Symbols - Sorted by Address
+                     Name    Address   Location    Storage File                     
+                ---------  ---------  ---------  --------- ---------                
+              INT_HANDLER   0x00001e    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+             INT_HANDLER2   0x00002e    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+               KALT_START   0x000100    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                     MAIN   0x00019e    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                   WARTEN   0x0001a0    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                POWER_EIN   0x0001a6    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                POWER_AUS   0x0001c0    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                LADESTROM   0x0001d2    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+              LS_ON_POWER   0x0001d8    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+             LS_OFF_POWER   0x0001de    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                    TASTE   0x0001e4    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                    TG_JA   0x0001fa    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+              TG_ON_POWER   0x000206    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+             SEND_RTC_REG   0x00020c    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+             TG_ON_POWER2   0x000212    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+             TG_ON_POWER3   0x000218    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+             TG_OFF_POWER   0x000224    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                   TG_END   0x00022c    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                  RESETEN   0x000232    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                   TX_ISR   0x00023c    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+            TX_ISR_FERTIG   0x00024c    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                  TX_ISR1   0x000254    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                   RC_ISR   0x000256    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                  RC_ISR1   0x000268    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                  RC_ISR2   0x000274    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                 RC_UNBEK   0x00027c    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                  RC_RRFP   0x000280    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                   RC_RFM   0x000290    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+            RC_SYNC_START   0x00029c    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                 NON_SYNC   0x0002ae    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                 RC_SYNC2   0x0002b4    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                 RC_SYNC3   0x0002c6    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                 RC_SYNC4   0x0002d8    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                 RC_WAIT1   0x0002e4    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                 RC_WAIT2   0x0002ec    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                 RC_WAIT3   0x0002f4    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                 HLVD_ISR   0x000300    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+               WAIT_LVDOK   0x000312    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                  HLVD_LE   0x00031a    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                  RTC_ISR   0x000326    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                   AD_ISR   0x000326    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+              POWER_OFF_I   0x000346    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+             POWER_OFF_I2   0x000356    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                    PINGS   0x000368    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                   PINGS2   0x000380    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                 SEKUNDEN   0x000386    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                  SEK_NPA   0x00039c    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                    SEK_2   0x0003ac    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                  MINUTEN   0x0003c0    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                  STUNDEN   0x0003ca    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+   TAGE_UND_TAG_DER_WOCHE   0x0003d4    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+         MEHR_ALS_28_TAGE   0x0003e6    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                      FEB   0x0003ee    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+               SCHALTJAHR   0x0003f4    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+               NEXT_MONTH   0x0003fa    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                     YEAR   0x000406    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                  NOT_FEB   0x00040e    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+         MEHR_ALS_30_TAGE   0x000414    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                NOT_APRIL   0x00041e    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                 NOT_JUNI   0x000428    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+                  NOT_SEP   0x000432    program     static C:\firebee\MLAB\firebee1\firebee1.asm
+
+
diff --git a/FireBee/MLAB/firebee1/readme.txt b/FireBee/MLAB/firebee1/readme.txt
new file mode 100644
index 0000000..4f5b8f3
--- /dev/null
+++ b/FireBee/MLAB/firebee1/readme.txt
@@ -0,0 +1,125 @@
+	PS2 -> Atari /Amiga Mouse Adapter
+        ~~~~~~~~~~~~~~~~~~~~~~~
+
+
+	Version 1.4 July 2010
+
+
+Due to the short supply of mice for the Atari computers I decided to build an adapter that would allow me to use a serial mouse on my Atari, but even these are getting a bit old now, so I got the soldering iron out again and here's the result. A PS2 Mouse adapter for the Atari. It supports a standard PS2 mouse with 2 or 3 buttons and can also be used with the Microsoft optical IntelliMouse that comes with a USB to PS2 adapter. The middle button on the PS2 mouse is used as a left click and hold function for easy selection. Click the middle button again to release. Now for the bad news, for some reason Microsoft mice don't support the middle button in standard PS2 mode. :-(
+
+Please don't shout at me all you Atari users but as an added feature if you change a link then the adapter can be used with an Amiga as well.
+
+
+All files, programs etc contained in this archive are copright 2010 by Tom Kirk. Personal use is allowed but any commercial use is not allowed. Please feel free to use my work but don't rip me off. 
+
+
+
+	Files in this archive.
+        ~~~~~~~~~~~~~~~~~~~~~~
+
+readme.txt		This text file
+circuit.bmp		Picture of circuit in bitmap format
+PS2Atari_v1_4.hex	Object code of the PIC16F84 program in Intel hex
+PS2Atari_v1_4.asm	Source code of the PIC16F84 program
+pcbtop.bmp		Top layer of the PCB in bitmap format
+pcbbot.bmp		Bottom layer of the PCB in bitmap format
+
+
+
+	Technical Details.
+	~~~~~~~~~~~~~~~~~~
+	
+When the PS2 mouse is moved or a button changes state a packet of data is sent, my circuit decodes this data and then simulates the Atari mouse.
+
+The circuit consists of a single microcontroller that contains a program to do the conversion. The circuit is shown in the file circuit.bmp
+
+The microcontroller (PIC) can be either a PIC16C84 or PIC16F84 or PIC16F84A.
+ 
+The PIC (IC1) needs to be programmed with the program.
+The program is supplied in two forms PS2Atari_v1_4.hex is an object code file in Intel hex and can be read by most programmers capable of programming the PIC
+
+PS2Atari_v1_4.asm is the source code of the program and can be assembled with the free MPLAB / MPASM software from Microchip if you wish to create your own object file. Note needs "Disable case sensitivity" under build options setting in MPLAB to assemble without errors.  
+
+The PIC should be programmed with oscillator as XT, watchdog disabled, powerup timer enabled and code protection off. (No point code protecting a freely available program.)
+
+The source code and object code is compatible with all the PIC microcontrollers listed above. 
+
+I've built mine using a printed circuit board but it's small enough to be built using a small piece of stripboard.
+
+On my PCB I have a 6 pin mini din socket at one end and a 9 pin D type socket at the other. I can then use a standard port extender lead to connect to the Atari. I've found that a 9 pin PC serial extension lead can also be used for this as well if you remove the fastening screws.
+
+If you decide to build one on a piece of stripboard it will be easier to use cable mounted sockets as PCB types don't fit onto a stripboard.
+
+Once built the board can be mounted into a small plastic box.
+
+No special software is required on the Atari and it will work with all software.
+Your favourite mouse accelerator program may be used if required.
+
+
+
+	Parts list.
+	~~~~~~~~~~~
+
+IC1	PIC16F84A or PIC16F84 or PIC16C84
+
+Fi1	4 MHz Ceramic resonator
+
+R1	10K
+R2	10K 
+
+C1	4.7 uF
+C2	0.1 uF
+
+All capacitors should be rated at 16V or more.
+
+CN1	6 pin mini din PCB mounting socket
+CN2	9 Pin D type PCB mounting socket
+
+
+JP1	3 pin header and 2 way link
+
+
+If building on a piece of stripboard I suggest using cable mounting types of connectors and use a small piece of multicore cable between the sockets and the stripboard. You will find the PCB sockets do not fit on a piece of stripboard. 
+
+If you don't need the switchable Atari/Amiga support forget the 3 pin header and just use a wire link instead.
+
+
+
+	History.
+	~~~~~~~~
+
+Version 1.4 July 2010
+Unused Pin RA4 now correctly set as an imput.
+(Pin is tied to +5V on PCB for easier PCB routing.)
+My oversight when transfering from prototype to PCB.
+Thanks to Luciano for informing me.
+
+Version 1.3 Released March 2010 
+Corrected a bug in button routine preventing both buttons being active together under certain conditions.
+Thanks to Oliver Fleischmann for informing me.
+(Can't believe it taken 6 Years for this bug to show itself!!)
+
+Version 1.2 Released March 2009
+Changed left/right button outputs to fake open collector.
+Needed to stop conflits when using a joystick pluged into other port.
+
+Version 1.1 Released September 2004.
+Added support for the Amiga and added the middle button support.
+
+Version 1.0 Never released.
+My original version for the Atari only.
+
+
+
+	Help.
+	~~~~~
+
+If you need further information or help then contact me at tgkirk@aol.com  
+
+Please allow a few days for a reply as I have other commitments as well.
+
+		Tom Kirk        July 2010
+
+P.S. 	I also have on my web site a Playstation controller to Atari adapter and a PC viewer for Atari format picture files.
+	
+	http://www.tgkirk.110mb.com 
diff --git a/FireBee/trunk/usb/store/asm-m68k/byteorder.h b/FireBee/trunk/usb/store/asm-m68k/byteorder.h
new file mode 100644
index 0000000..3d4f13c
--- /dev/null
+++ b/FireBee/trunk/usb/store/asm-m68k/byteorder.h
@@ -0,0 +1,107 @@
+/*
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _M68K_BYTEORDER_H
+#define _M68K_BYTEORDER_H
+
+#include "types.h"
+
+#ifdef __GNUC__
+#define __sw16(x) \
+	((__u16)( \
+		(((__u16)(x) & (__u16)0x00ffU) << 8) | \
+		(((__u16)(x) & (__u16)0xff00U) >> 8) ))
+#define __sw32(x) \
+	((__u32)( \
+		(((__u32)(x)) << 24) | \
+		(((__u32)(x) & (__u32)0x0000ff00UL) <<  8) | \
+		(((__u32)(x) & (__u32)0x00ff0000UL) >>  8) | \
+		(((__u32)(x)) >> 24) ))
+
+extern __inline__ unsigned ld_le16(const volatile unsigned short *addr)
+{
+	unsigned result = *addr;
+	return __sw16(result);
+}
+
+extern __inline__ void st_le16(volatile unsigned short *addr,
+			       const unsigned val)
+{
+	*addr = __sw16(val);
+}
+
+extern __inline__ unsigned ld_le32(const volatile unsigned *addr)
+{
+	unsigned result = *addr;
+	return __sw32(result);
+}
+
+extern __inline__ void st_le32(volatile unsigned *addr, const unsigned val)
+{
+	*addr = __sw32(val);
+}
+
+#if 0
+/* alas, egcs sounds like it has a bug in this code that doesn't use the
+   inline asm correctly, and can cause file corruption. Until I hear that
+   it's fixed, I can live without the extra speed. I hope. */
+#if !(__GNUC__ >= 2 && __GNUC_MINOR__ >= 90)
+#if 0
+#  define __arch_swab16(x) ld_le16(&x)
+#  define __arch_swab32(x) ld_le32(&x)
+#else
+static __inline__ __attribute__ ((const))
+__u16 ___arch__swab16(__u16 value)
+{
+	return __sw16(value);
+}
+
+static __inline__ __attribute__ ((const))
+__u32 ___arch__swab32(__u32 value)
+{
+	return __sw32(value);
+}
+
+#define __arch__swab32(x) ___arch__swab32(x)
+#define __arch__swab16(x) ___arch__swab16(x)
+#endif				/* 0 */
+
+#endif
+
+/* The same, but returns converted value from the location pointer by addr. */
+#define __arch__swab16p(addr) ld_le16(addr)
+#define __arch__swab32p(addr) ld_le32(addr)
+
+/* The same, but do the conversion in situ, ie. put the value back to addr. */
+#define __arch__swab16s(addr) st_le16(addr,*addr)
+#define __arch__swab32s(addr) st_le32(addr,*addr)
+#endif
+
+#endif				/* __GNUC__ */
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+#define __BYTEORDER_HAS_U64__
+#endif
+#include "byteorder/big_endian.h"
+
+#endif				/* _M68K_BYTEORDER_H */
diff --git a/FireBee/trunk/usb/store/asm-m68k/byteorder/big_endian.h b/FireBee/trunk/usb/store/asm-m68k/byteorder/big_endian.h
new file mode 100644
index 0000000..fbdea2c
--- /dev/null
+++ b/FireBee/trunk/usb/store/asm-m68k/byteorder/big_endian.h
@@ -0,0 +1,69 @@
+#ifndef _LINUX_BYTEORDER_BIG_ENDIAN_H
+#define _LINUX_BYTEORDER_BIG_ENDIAN_H
+
+#ifndef __BIG_ENDIAN
+#define __BIG_ENDIAN 4321
+#endif
+#ifndef __BIG_ENDIAN_BITFIELD
+#define __BIG_ENDIAN_BITFIELD
+#endif
+#define	__BYTE_ORDER	__BIG_ENDIAN
+
+#include "swab.h"
+
+#define __constant_htonl(x) ((__u32)(x))
+#define __constant_ntohl(x) ((__u32)(x))
+#define __constant_htons(x) ((__u16)(x))
+#define __constant_ntohs(x) ((__u16)(x))
+#define __constant_cpu_to_le64(x) ___swab64((x))
+#define __constant_le64_to_cpu(x) ___swab64((x))
+#define __constant_cpu_to_le32(x) ___swab32((x))
+#define __constant_le32_to_cpu(x) ___swab32((x))
+#define __constant_cpu_to_le16(x) ___swab16((x))
+#define __constant_le16_to_cpu(x) ___swab16((x))
+#define __constant_cpu_to_be64(x) ((__u64)(x))
+#define __constant_be64_to_cpu(x) ((__u64)(x))
+#define __constant_cpu_to_be32(x) ((__u32)(x))
+#define __constant_be32_to_cpu(x) ((__u32)(x))
+#define __constant_cpu_to_be16(x) ((__u16)(x))
+#define __constant_be16_to_cpu(x) ((__u16)(x))
+#define __cpu_to_le64(x) __swab64((x))
+#define __le64_to_cpu(x) __swab64((x))
+#define __cpu_to_le32(x) __swab32((x))
+#define __le32_to_cpu(x) __swab32((x))
+#define __cpu_to_le16(x) __swab16((x))
+#define __le16_to_cpu(x) __swab16((x))
+#define __cpu_to_be64(x) ((__u64)(x))
+#define __be64_to_cpu(x) ((__u64)(x))
+#define __cpu_to_be32(x) ((__u32)(x))
+#define __be32_to_cpu(x) ((__u32)(x))
+#define __cpu_to_be16(x) ((__u16)(x))
+#define __be16_to_cpu(x) ((__u16)(x))
+#define __cpu_to_le64p(x) __swab64p((x))
+#define __le64_to_cpup(x) __swab64p((x))
+#define __cpu_to_le32p(x) __swab32p((x))
+#define __le32_to_cpup(x) __swab32p((x))
+#define __cpu_to_le16p(x) __swab16p((x))
+#define __le16_to_cpup(x) __swab16p((x))
+#define __cpu_to_be64p(x) (*(__u64*)(x))
+#define __be64_to_cpup(x) (*(__u64*)(x))
+#define __cpu_to_be32p(x) (*(__u32*)(x))
+#define __be32_to_cpup(x) (*(__u32*)(x))
+#define __cpu_to_be16p(x) (*(__u16*)(x))
+#define __be16_to_cpup(x) (*(__u16*)(x))
+#define __cpu_to_le64s(x) __swab64s((x))
+#define __le64_to_cpus(x) __swab64s((x))
+#define __cpu_to_le32s(x) __swab32s((x))
+#define __le32_to_cpus(x) __swab32s((x))
+#define __cpu_to_le16s(x) __swab16s((x))
+#define __le16_to_cpus(x) __swab16s((x))
+#define __cpu_to_be64s(x) do {} while (0)
+#define __be64_to_cpus(x) do {} while (0)
+#define __cpu_to_be32s(x) do {} while (0)
+#define __be32_to_cpus(x) do {} while (0)
+#define __cpu_to_be16s(x) do {} while (0)
+#define __be16_to_cpus(x) do {} while (0)
+
+#include "generic.h"
+
+#endif /* _LINUX_BYTEORDER_BIG_ENDIAN_H */
diff --git a/FireBee/trunk/usb/store/asm-m68k/byteorder/generic.h b/FireBee/trunk/usb/store/asm-m68k/byteorder/generic.h
new file mode 100644
index 0000000..e3db5cc
--- /dev/null
+++ b/FireBee/trunk/usb/store/asm-m68k/byteorder/generic.h
@@ -0,0 +1,180 @@
+#ifndef _LINUX_BYTEORDER_GENERIC_H
+#define _LINUX_BYTEORDER_GENERIC_H
+
+/*
+ * linux/byteorder_generic.h
+ * Generic Byte-reordering support
+ *
+ * Francois-Rene Rideau <fare@tunes.org> 19970707
+ *    gathered all the good ideas from all asm-foo/byteorder.h into one file,
+ *    cleaned them up.
+ *    I hope it is compliant with non-GCC compilers.
+ *    I decided to put __BYTEORDER_HAS_U64__ in byteorder.h,
+ *    because I wasn't sure it would be ok to put it in types.h
+ *    Upgraded it to 2.1.43
+ * Francois-Rene Rideau <fare@tunes.org> 19971012
+ *    Upgraded it to 2.1.57
+ *    to please Linus T., replaced huge #ifdef's between little/big endian
+ *    by nestedly #include'd files.
+ * Francois-Rene Rideau <fare@tunes.org> 19971205
+ *    Made it to 2.1.71; now a facelift:
+ *    Put files under include/linux/byteorder/
+ *    Split swab from generic support.
+ *
+ * TODO:
+ *   = Regular kernel maintainers could also replace all these manual
+ *    byteswap macros that remain, disseminated among drivers,
+ *    after some grep or the sources...
+ *   = Linus might want to rename all these macros and files to fit his taste,
+ *    to fit his personal naming scheme.
+ *   = it seems that a few drivers would also appreciate
+ *    nybble swapping support...
+ *   = every architecture could add their byteswap macro in asm/byteorder.h
+ *    see how some architectures already do (i386, alpha, ppc, etc)
+ *   = cpu_to_beXX and beXX_to_cpu might some day need to be well
+ *    distinguished throughout the kernel. This is not the case currently,
+ *    since little endian, big endian, and pdp endian machines needn't it.
+ *    But this might be the case for, say, a port of Linux to 20/21 bit
+ *    architectures (and F21 Linux addict around?).
+ */
+
+/*
+ * The following macros are to be defined by <asm/byteorder.h>:
+ *
+ * Conversion of long and short int between network and host format
+ *	ntohl(__u32 x)
+ *	ntohs(__u16 x)
+ *	htonl(__u32 x)
+ *	htons(__u16 x)
+ * It seems that some programs (which? where? or perhaps a standard? POSIX?)
+ * might like the above to be functions, not macros (why?).
+ * if that's true, then detect them, and take measures.
+ * Anyway, the measure is: define only ___ntohl as a macro instead,
+ * and in a separate file, have
+ * unsigned long inline ntohl(x){return ___ntohl(x);}
+ *
+ * The same for constant arguments
+ *	__constant_ntohl(__u32 x)
+ *	__constant_ntohs(__u16 x)
+ *	__constant_htonl(__u32 x)
+ *	__constant_htons(__u16 x)
+ *
+ * Conversion of XX-bit integers (16- 32- or 64-)
+ * between native CPU format and little/big endian format
+ * 64-bit stuff only defined for proper architectures
+ *	cpu_to_[bl]eXX(__uXX x)
+ *	[bl]eXX_to_cpu(__uXX x)
+ *
+ * The same, but takes a pointer to the value to convert
+ *	cpu_to_[bl]eXXp(__uXX x)
+ *	[bl]eXX_to_cpup(__uXX x)
+ *
+ * The same, but change in situ
+ *	cpu_to_[bl]eXXs(__uXX x)
+ *	[bl]eXX_to_cpus(__uXX x)
+ *
+ * See asm-foo/byteorder.h for examples of how to provide
+ * architecture-optimized versions
+ *
+ */
+
+
+//#if defined(__KERNEL__)
+/*
+ * inside the kernel, we can use nicknames;
+ * outside of it, we must avoid POSIX namespace pollution...
+ */
+#define cpu_to_le64 __cpu_to_le64
+#define le64_to_cpu __le64_to_cpu
+#define cpu_to_le32 __cpu_to_le32
+#define le32_to_cpu __le32_to_cpu
+#define cpu_to_le16 __cpu_to_le16
+#define le16_to_cpu __le16_to_cpu
+#define cpu_to_be64 __cpu_to_be64
+#define be64_to_cpu __be64_to_cpu
+#define cpu_to_be32 __cpu_to_be32
+#define be32_to_cpu __be32_to_cpu
+#define cpu_to_be16 __cpu_to_be16
+#define be16_to_cpu __be16_to_cpu
+#define cpu_to_le64p __cpu_to_le64p
+#define le64_to_cpup __le64_to_cpup
+#define cpu_to_le32p __cpu_to_le32p
+#define le32_to_cpup __le32_to_cpup
+#define cpu_to_le16p __cpu_to_le16p
+#define le16_to_cpup __le16_to_cpup
+#define cpu_to_be64p __cpu_to_be64p
+#define be64_to_cpup __be64_to_cpup
+#define cpu_to_be32p __cpu_to_be32p
+#define be32_to_cpup __be32_to_cpup
+#define cpu_to_be16p __cpu_to_be16p
+#define be16_to_cpup __be16_to_cpup
+#define cpu_to_le64s __cpu_to_le64s
+#define le64_to_cpus __le64_to_cpus
+#define cpu_to_le32s __cpu_to_le32s
+#define le32_to_cpus __le32_to_cpus
+#define cpu_to_le16s __cpu_to_le16s
+#define le16_to_cpus __le16_to_cpus
+#define cpu_to_be64s __cpu_to_be64s
+#define be64_to_cpus __be64_to_cpus
+#define cpu_to_be32s __cpu_to_be32s
+#define be32_to_cpus __be32_to_cpus
+#define cpu_to_be16s __cpu_to_be16s
+#define be16_to_cpus __be16_to_cpus
+//#endif
+
+
+/*
+ * Handle ntohl and suches. These have various compatibility
+ * issues - like we want to give the prototype even though we
+ * also have a macro for them in case some strange program
+ * wants to take the address of the thing or something..
+ *
+ * Note that these used to return a "long" in libc5, even though
+ * long is often 64-bit these days.. Thus the casts.
+ *
+ * They have to be macros in order to do the constant folding
+ * correctly - if the argument passed into a inline function
+ * it is no longer constant according to gcc..
+ */
+
+#undef ntohl
+#undef ntohs
+#undef htonl
+#undef htons
+
+/*
+ * Do the prototypes. Somebody might want to take the
+ * address or some such sick thing..
+ */
+#if defined(__KERNEL__) || (defined (__GLIBC__) && __GLIBC__ >= 2)
+extern __u32			ntohl(__u32);
+extern __u32			htonl(__u32);
+#else
+extern unsigned long int	ntohl(unsigned long int);
+extern unsigned long int	htonl(unsigned long int);
+#endif
+extern unsigned short int	ntohs(unsigned short int);
+extern unsigned short int	htons(unsigned short int);
+
+
+#if defined(__GNUC__) && (__GNUC__ >= 2)
+
+#define ___htonl(x) __cpu_to_be32(x)
+#define ___htons(x) __cpu_to_be16(x)
+#define ___ntohl(x) __be32_to_cpu(x)
+#define ___ntohs(x) __be16_to_cpu(x)
+
+#if defined(__KERNEL__) || (defined (__GLIBC__) && __GLIBC__ >= 2)
+#define htonl(x) ___htonl(x)
+#define ntohl(x) ___ntohl(x)
+#else
+#define htonl(x) ((unsigned long)___htonl(x))
+#define ntohl(x) ((unsigned long)___ntohl(x))
+#endif
+#define htons(x) ___htons(x)
+#define ntohs(x) ___ntohs(x)
+
+#endif /* OPTIMIZE */
+
+
+#endif /* _LINUX_BYTEORDER_GENERIC_H */
diff --git a/FireBee/trunk/usb/store/asm-m68k/byteorder/little_endian.h b/FireBee/trunk/usb/store/asm-m68k/byteorder/little_endian.h
new file mode 100644
index 0000000..b6c67eb
--- /dev/null
+++ b/FireBee/trunk/usb/store/asm-m68k/byteorder/little_endian.h
@@ -0,0 +1,69 @@
+#ifndef _LINUX_BYTEORDER_LITTLE_ENDIAN_H
+#define _LINUX_BYTEORDER_LITTLE_ENDIAN_H
+
+#ifndef __LITTLE_ENDIAN
+#define __LITTLE_ENDIAN 1234
+#endif
+#ifndef __LITTLE_ENDIAN_BITFIELD
+#define __LITTLE_ENDIAN_BITFIELD
+#endif
+#define	__BYTE_ORDER	__LITTLE_ENDIAN
+
+#include "swab.h"
+
+#define __constant_htonl(x) ___constant_swab32((x))
+#define __constant_ntohl(x) ___constant_swab32((x))
+#define __constant_htons(x) ___constant_swab16((x))
+#define __constant_ntohs(x) ___constant_swab16((x))
+#define __constant_cpu_to_le64(x) ((__u64)(x))
+#define __constant_le64_to_cpu(x) ((__u64)(x))
+#define __constant_cpu_to_le32(x) ((__u32)(x))
+#define __constant_le32_to_cpu(x) ((__u32)(x))
+#define __constant_cpu_to_le16(x) ((__u16)(x))
+#define __constant_le16_to_cpu(x) ((__u16)(x))
+#define __constant_cpu_to_be64(x) ___constant_swab64((x))
+#define __constant_be64_to_cpu(x) ___constant_swab64((x))
+#define __constant_cpu_to_be32(x) ___constant_swab32((x))
+#define __constant_be32_to_cpu(x) ___constant_swab32((x))
+#define __constant_cpu_to_be16(x) ___constant_swab16((x))
+#define __constant_be16_to_cpu(x) ___constant_swab16((x))
+#define __cpu_to_le64(x) ((__u64)(x))
+#define __le64_to_cpu(x) ((__u64)(x))
+#define __cpu_to_le32(x) ((__u32)(x))
+#define __le32_to_cpu(x) ((__u32)(x))
+#define __cpu_to_le16(x) ((__u16)(x))
+#define __le16_to_cpu(x) ((__u16)(x))
+#define __cpu_to_be64(x) __swab64((x))
+#define __be64_to_cpu(x) __swab64((x))
+#define __cpu_to_be32(x) __swab32((x))
+#define __be32_to_cpu(x) __swab32((x))
+#define __cpu_to_be16(x) __swab16((x))
+#define __be16_to_cpu(x) __swab16((x))
+#define __cpu_to_le64p(x) (*(__u64*)(x))
+#define __le64_to_cpup(x) (*(__u64*)(x))
+#define __cpu_to_le32p(x) (*(__u32*)(x))
+#define __le32_to_cpup(x) (*(__u32*)(x))
+#define __cpu_to_le16p(x) (*(__u16*)(x))
+#define __le16_to_cpup(x) (*(__u16*)(x))
+#define __cpu_to_be64p(x) __swab64p((x))
+#define __be64_to_cpup(x) __swab64p((x))
+#define __cpu_to_be32p(x) __swab32p((x))
+#define __be32_to_cpup(x) __swab32p((x))
+#define __cpu_to_be16p(x) __swab16p((x))
+#define __be16_to_cpup(x) __swab16p((x))
+#define __cpu_to_le64s(x) do {} while (0)
+#define __le64_to_cpus(x) do {} while (0)
+#define __cpu_to_le32s(x) do {} while (0)
+#define __le32_to_cpus(x) do {} while (0)
+#define __cpu_to_le16s(x) do {} while (0)
+#define __le16_to_cpus(x) do {} while (0)
+#define __cpu_to_be64s(x) __swab64s((x))
+#define __be64_to_cpus(x) __swab64s((x))
+#define __cpu_to_be32s(x) __swab32s((x))
+#define __be32_to_cpus(x) __swab32s((x))
+#define __cpu_to_be16s(x) __swab16s((x))
+#define __be16_to_cpus(x) __swab16s((x))
+
+#include "generic.h"
+
+#endif /* _LINUX_BYTEORDER_LITTLE_ENDIAN_H */
diff --git a/FireBee/trunk/usb/store/asm-m68k/byteorder/swab.h b/FireBee/trunk/usb/store/asm-m68k/byteorder/swab.h
new file mode 100644
index 0000000..d3394b0
--- /dev/null
+++ b/FireBee/trunk/usb/store/asm-m68k/byteorder/swab.h
@@ -0,0 +1,158 @@
+#ifndef _LINUX_BYTEORDER_SWAB_H
+#define _LINUX_BYTEORDER_SWAB_H
+
+/*
+ * linux/byteorder/swab.h
+ * Byte-swapping, independently from CPU endianness
+ *	swabXX[ps]?(foo)
+ *
+ * Francois-Rene Rideau <fare@tunes.org> 19971205
+ *    separated swab functions from cpu_to_XX,
+ *    to clean up support for bizarre-endian architectures.
+ *
+ * See asm-i386/byteorder.h and suches for examples of how to provide
+ * architecture-dependent optimized versions
+ *
+ */
+
+/* casts are necessary for constants, because we never know how for sure
+ * how U/UL/ULL map to __u16, __u32, __u64. At least not in a portable way.
+ */
+#define ___swab16(x) \
+	((__u16)( \
+		(((__u16)(x) & (__u16)0x00ffU) << 8) | \
+		(((__u16)(x) & (__u16)0xff00U) >> 8) ))
+#define ___swab32(x) \
+	((__u32)( \
+		(((__u32)(x) & (__u32)0x000000ffUL) << 24) | \
+		(((__u32)(x) & (__u32)0x0000ff00UL) <<  8) | \
+		(((__u32)(x) & (__u32)0x00ff0000UL) >>  8) | \
+		(((__u32)(x) & (__u32)0xff000000UL) >> 24) ))
+#define ___swab64(x) \
+	((__u64)( \
+		(__u64)(((__u64)(x) & (__u64)0x00000000000000ffULL) << 56) | \
+		(__u64)(((__u64)(x) & (__u64)0x000000000000ff00ULL) << 40) | \
+		(__u64)(((__u64)(x) & (__u64)0x0000000000ff0000ULL) << 24) | \
+		(__u64)(((__u64)(x) & (__u64)0x00000000ff000000ULL) <<  8) | \
+		(__u64)(((__u64)(x) & (__u64)0x000000ff00000000ULL) >>  8) | \
+		(__u64)(((__u64)(x) & (__u64)0x0000ff0000000000ULL) >> 24) | \
+		(__u64)(((__u64)(x) & (__u64)0x00ff000000000000ULL) >> 40) | \
+		(__u64)(((__u64)(x) & (__u64)0xff00000000000000ULL) >> 56) ))
+
+/*
+ * provide defaults when no architecture-specific optimization is detected
+ */
+#ifndef __arch__swab16
+#  define __arch__swab16(x) ___swab16(x)
+#endif
+#ifndef __arch__swab32
+#  define __arch__swab32(x) ___swab32(x)
+#endif
+#ifndef __arch__swab64
+#  define __arch__swab64(x) ___swab64(x)
+#endif
+
+#ifndef __arch__swab16p
+#  define __arch__swab16p(x) __swab16(*(x))
+#endif
+#ifndef __arch__swab32p
+#  define __arch__swab32p(x) __swab32(*(x))
+#endif
+#ifndef __arch__swab64p
+#  define __arch__swab64p(x) __swab64(*(x))
+#endif
+
+#ifndef __arch__swab16s
+#  define __arch__swab16s(x) do { *(x) = __swab16p((x)); } while (0)
+#endif
+#ifndef __arch__swab32s
+#  define __arch__swab32s(x) do { *(x) = __swab32p((x)); } while (0)
+#endif
+#ifndef __arch__swab64s
+#  define __arch__swab64s(x) do { *(x) = __swab64p((x)); } while (0)
+#endif
+
+
+/*
+ * Allow constant folding
+ */
+#if defined(__GNUC__) && (__GNUC__ >= 2) && defined(__OPTIMIZE__)
+#  define __swab16(x) \
+(__builtin_constant_p((__u16)(x)) ? \
+ ___swab16((x)) : \
+ __fswab16((x)))
+#  define __swab32(x) \
+(__builtin_constant_p((__u32)(x)) ? \
+ ___swab32((x)) : \
+ __fswab32((x)))
+#  define __swab64(x) \
+(__builtin_constant_p((__u64)(x)) ? \
+ ___swab64((x)) : \
+ __fswab64((x)))
+#else
+#  define __swab16(x) __fswab16(x)
+#  define __swab32(x) __fswab32(x)
+#  define __swab64(x) __fswab64(x)
+#endif /* OPTIMIZE */
+
+
+static __inline__ __attribute__((const)) __u16 __fswab16(__u16 x)
+{
+	return __arch__swab16(x);
+}
+static __inline__ __u16 __swab16p(__u16 *x)
+{
+	return __arch__swab16p(x);
+}
+static __inline__ void __swab16s(__u16 *addr)
+{
+	__arch__swab16s(addr);
+}
+
+static __inline__ __attribute__((const)) __u32 __fswab32(__u32 x)
+{
+	return __arch__swab32(x);
+}
+static __inline__ __u32 __swab32p(__u32 *x)
+{
+	return __arch__swab32p(x);
+}
+static __inline__ void __swab32s(__u32 *addr)
+{
+	__arch__swab32s(addr);
+}
+
+#ifdef __BYTEORDER_HAS_U64__
+static __inline__ __attribute__((const)) __u64 __fswab64(__u64 x)
+{
+#  ifdef __SWAB_64_THRU_32__
+	__u32 h = x >> 32;
+	__u32 l = x & ((1ULL<<32)-1);
+	return (((__u64)__swab32(l)) << 32) | ((__u64)(__swab32(h)));
+#  else
+	return __arch__swab64(x);
+#  endif
+}
+static __inline__ __u64 __swab64p(__u64 *x)
+{
+	return __arch__swab64p(x);
+}
+static __inline__ void __swab64s(__u64 *addr)
+{
+	__arch__swab64s(addr);
+}
+#endif /* __BYTEORDER_HAS_U64__ */
+
+//#if defined(__KERNEL__)
+#define swab16 __swab16
+#define swab32 __swab32
+#define swab64 __swab64
+#define swab16p __swab16p
+#define swab32p __swab32p
+#define swab64p __swab64p
+#define swab16s __swab16s
+#define swab32s __swab32s
+#define swab64s __swab64s
+//#endif
+
+#endif /* _LINUX_BYTEORDER_SWAB_H */
diff --git a/FireBee/trunk/usb/store/asm-m68k/io.h b/FireBee/trunk/usb/store/asm-m68k/io.h
new file mode 100644
index 0000000..3c6455d
--- /dev/null
+++ b/FireBee/trunk/usb/store/asm-m68k/io.h
@@ -0,0 +1,263 @@
+/*
+ * IO header file
+ *
+ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
+ * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef __ASM_M68K_IO_H__
+#define __ASM_M68K_IO_H__
+
+#include "byteorder.h"
+
+#define __raw_readb(addr) (*(volatile u8 *)(addr))
+#define __raw_readw(addr) (*(volatile u16 *)(addr))
+#define __raw_readl(addr) (*(volatile u32 *)(addr))
+
+#define __raw_writeb(b,addr) ((*(volatile u8 *) (addr)) = (b))
+#define __raw_writew(w,addr) ((*(volatile u16 *) (addr)) = (w))
+#define __raw_writel(l,addr) ((*(volatile u32 *) (addr)) = (l))
+
+#define readb(addr)		in_8((volatile u8 *)(addr))
+#define writeb(b,addr)		out_8((volatile u8 *)(addr), (b))
+#if !defined(__BIG_ENDIAN)
+//#if defined(__BIG_ENDIAN)
+#define readw(addr)		(*(volatile u16 *) (addr))
+#define readl(addr)		(*(volatile u32 *) (addr))
+#define writew(b,addr)		((*(volatile u16 *) (addr)) = (b))
+#define writel(b,addr)		((*(volatile u32 *) (addr)) = (b))
+#else				/* Galvez: in_le16() does the swap reading 
+				 * twice from fifo (register), when reading 
+				 * from fifo once the value is changed by the new one */
+#define readw(addr)		ld_le16((volatile u16 *)(addr))   /* instead of in_le16((volatile u16 *)(addr))*/
+#define readl(addr)		in_le32((volatile u32 *)(addr))
+#define writew(b,addr)		out_le16((volatile u16 *)(addr),(b))
+#define writel(b,addr)		out_le32((volatile u32 *)(addr),(b))
+#endif
+
+/*
+ * The insw/outsw/insl/outsl macros don't do byte-swapping.
+ * They are only used in practice for transferring buffers which
+ * are arrays of bytes, and byte-swapping is not appropriate in
+ * that case.  - paulus
+ */
+#define insb(port, buf, ns)	_insb((u8 *)((port)+_IO_BASE), (buf), (ns))
+#define outsb(port, buf, ns)	_outsb((u8 *)((port)+_IO_BASE), (buf), (ns))
+#define insw(port, buf, ns)	_insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
+#define outsw(port, buf, ns)	_outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
+#define insl(port, buf, nl)	_insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
+#define outsl(port, buf, nl)	_outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
+
+#define inb(port)		in_8((u8 *)((port)+_IO_BASE))
+#define outb(val, port)		out_8((u8 *)((port)+_IO_BASE), (val))
+#if !defined(__BIG_ENDIAN)
+//#if defined(__BIG_ENDIAN)
+#define inw(port)		in_be16((u16 *)((port)+_IO_BASE))
+#define outw(val, port)		out_be16((u16 *)((port)+_IO_BASE), (val))
+#define inl(port)		in_be32((u32 *)((port)+_IO_BASE))
+#define outl(val, port)		out_be32((u32 *)((port)+_IO_BASE), (val))
+#else
+#define inw(port)		in_le16((u16 *)((port)+_IO_BASE))
+#define outw(val, port)		out_le16((u16 *)((port)+_IO_BASE), (val))
+#define inl(port)		in_le32((u32 *)((port)+_IO_BASE))
+#define outl(val, port)		out_le32((u32 *)((port)+_IO_BASE), (val))
+#endif
+
+extern inline void _insb(volatile u8 * port, void *buf, int ns)
+{
+	u8 *data = (u8 *) buf;
+	while (ns--)
+		*data++ = *port;
+}
+
+extern inline void _outsb(volatile u8 * port, const void *buf, int ns)
+{
+	u8 *data = (u8 *) buf;
+	while (ns--)
+		*port = *data++;
+}
+
+extern inline void _insw(volatile u16 * port, void *buf, int ns)
+{
+	u16 *data = (u16 *) buf;
+	while (ns--)
+		*data++ = __sw16(*port);
+}
+
+extern inline void _outsw(volatile u16 * port, const void *buf, int ns)
+{
+	u16 *data = (u16 *) buf;
+	while (ns--) {
+		*port = __sw16(*data);
+		data++;
+	}
+}
+
+extern inline void _insl(volatile u32 * port, void *buf, int nl)
+{
+	u32 *data = (u32 *) buf;
+	while (nl--)
+		*data++ = __sw32(*port);
+}
+
+extern inline void _outsl(volatile u32 * port, const void *buf, int nl)
+{
+	u32 *data = (u32 *) buf;
+	while (nl--) {
+		*port = __sw32(*data);
+		data++;
+	}
+}
+
+extern inline void _insw_ns(volatile u16 * port, void *buf, int ns)
+{
+	u16 *data = (u16 *) buf;
+	while (ns--)
+		*data++ = *port;
+}
+
+extern inline void _outsw_ns(volatile u16 * port, const void *buf, int ns)
+{
+	u16 *data = (u16 *) buf;
+	while (ns--) {
+		*port = *data++;
+	}
+}
+
+extern inline void _insl_ns(volatile u32 * port, void *buf, int nl)
+{
+	u32 *data = (u32 *) buf;
+	while (nl--)
+		*data++ = *port;
+}
+
+extern inline void _outsl_ns(volatile u32 * port, const void *buf, int nl)
+{
+	u32 *data = (u32 *) buf;
+	while (nl--) {
+		*port = *data;
+		data++;
+	}
+}
+
+/*
+ * The *_ns versions below don't do byte-swapping.
+ * Neither do the standard versions now, these are just here
+ * for older code.
+ */
+#define insw_ns(port, buf, ns)	_insw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
+#define outsw_ns(port, buf, ns)	_outsw_ns((u16 *)((port)+_IO_BASE), (buf), (ns))
+#define insl_ns(port, buf, nl)	_insl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
+#define outsl_ns(port, buf, nl)	_outsl_ns((u32 *)((port)+_IO_BASE), (buf), (nl))
+
+#define IO_SPACE_LIMIT ~0
+
+/*
+ * 8, 16 and 32 bit, big and little endian I/O operations, with barrier.
+ */
+extern inline int in_8(volatile u8 * addr)
+{
+	return (int)*addr;
+}
+
+extern inline void out_8(volatile u8 * addr, int val)
+{
+	*addr = (u8) val;
+}
+
+extern inline int in_le16(volatile u16 * addr)
+{
+	return __sw16(*addr);
+}
+
+extern inline int in_be16(volatile u16 * addr)
+{
+	return (*addr & 0xFFFF);
+}
+
+extern inline void out_le16(volatile u16 * addr, int val)
+{
+	*addr = __sw16(val);
+}
+
+extern inline void out_be16(volatile u16 * addr, int val)
+{
+	*addr = (u16) val;
+}
+
+extern inline unsigned in_le32(volatile u32 * addr)
+{
+	return __sw32(*addr);
+}
+
+extern inline unsigned in_be32(volatile u32 * addr)
+{
+	return (*addr);
+}
+
+extern inline void out_le32(volatile unsigned *addr, int val)
+{
+	*addr = __sw32(val);
+}
+
+extern inline void out_be32(volatile unsigned *addr, int val)
+{
+	*addr = val;
+}
+
+static inline void sync(void)
+{
+	/* This sync function is for PowerPC or other architecture instruction
+	 * ColdFire does not have this instruction. Dummy function, added for
+	 * compatibility (CFI driver)
+	 */
+}
+
+/*
+ * Given a physical address and a length, return a virtual address
+ * that can be used to access the memory range with the caching
+ * properties specified by "flags".
+ */
+#define MAP_NOCACHE	(0)
+#define MAP_WRCOMBINE	(0)
+#define MAP_WRBACK	(0)
+#define MAP_WRTHROUGH	(0)
+
+static inline void *map_physmem(phys_addr_t paddr, unsigned long len,
+				unsigned long flags)
+{
+	return (void *)paddr;
+}
+
+/*
+ * Take down a mapping set up by map_physmem().
+ */
+static inline void unmap_physmem(void *vaddr, unsigned long flags)
+{
+
+}
+
+static inline phys_addr_t virt_to_phys(void * vaddr)
+{
+	return (phys_addr_t)(vaddr);
+}
+
+#endif				/* __ASM_M68K_IO_H__ */
diff --git a/FireBee/trunk/usb/store/asm-m68k/types.h b/FireBee/trunk/usb/store/asm-m68k/types.h
new file mode 100644
index 0000000..42ff2a6
--- /dev/null
+++ b/FireBee/trunk/usb/store/asm-m68k/types.h
@@ -0,0 +1,53 @@
+#ifndef _M68K_TYPES_H
+#define _M68K_TYPES_H
+
+#ifndef __ASSEMBLY__
+
+typedef unsigned short umode_t;
+
+typedef __signed__ char __s8;
+typedef unsigned char __u8;
+
+typedef __signed__ short __s16;
+typedef unsigned short __u16;
+
+typedef __signed__ int __s32;
+typedef unsigned int __u32;
+
+#if defined(__GNUC__)
+__extension__ typedef __signed__ long long __s64;
+__extension__ typedef unsigned long long __u64;
+#endif
+
+typedef struct {
+	__u32 u[4];
+} __attribute__((aligned(16))) vector128;
+
+//#ifdef __KERNEL__
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+typedef signed char s8;
+typedef unsigned char u8;
+
+typedef signed short s16;
+typedef unsigned short u16;
+
+typedef signed int s32;
+typedef unsigned int u32;
+
+typedef signed long long s64;
+typedef unsigned long long u64;
+
+#define BITS_PER_LONG 32
+
+/* DMA addresses are 32-bits wide */
+typedef u32 dma_addr_t;
+
+typedef unsigned long phys_addr_t;
+typedef unsigned long phys_size_t;
+
+//#endif /* __KERNEL__ */
+#endif /* __ASSEMBLY__ */
+
+#endif
diff --git a/FireBee/trunk/usb/store/bios.S b/FireBee/trunk/usb/store/bios.S
new file mode 100644
index 0000000..fb83a92
--- /dev/null
+++ b/FireBee/trunk/usb/store/bios.S
@@ -0,0 +1,1378 @@
+/* TOS 4.04 Xbios dispatcher for the CT60/CTPCI boards
+ * and USB-disk / Ram-Disk utility
+ * Didier Mequignon 2005-2009, e-mail: aniplay@wanadoo.fr
+ *
+ * Modified to be used as an application by David Gálvez 2010.
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+ 
+
+ 
+#include "config.h"
+#include "vars.h"
+
+#define old_pun_ptr 	0x516
+
+#undef pun_ptr
+#define pun_ptr pun_ptr_usb
+
+.global	_max_logical_drive
+
+#define MAX_LOGICAL_DRIVE	_max_logical_drive
+
+.chip 68040
+
+.global ___mint
+
+#if defined(CONFIG_USB_UHCI) || defined(CONFIG_USB_OHCI) || defined(CONFIG_USB_EHCI) || \
+	defined(CONFIG_USB_ISP116X_HCD) || defined(CONFIG_USB_ARANYM_HCD)
+#ifdef CONFIG_USB_STORAGE
+	.global _install_usb_stor,_usb_stor_read,_usb_stor_write,_usb_1st_disk_drive,_SuperFromUser, _SuperTouser
+#endif /* CONFIG_USB_STORAGE */
+#endif /* CONFIG_USB_UHCI || CONFIG_USB_OHCI || CONFIG_USB_EHCI || CONFIG_USB_ISP116X_HCD */
+
+
+
+#if defined(CONFIG_USB_KEYBOARD) || (CONFIG_USB_MOUSE)
+.global _asm_set_ipl
+.global _call_ikbdvec,_call_mousevec
+#endif
+
+#ifdef DEBUG_BIOS_LAYER
+	.global display_string,hex_long,hex_word,hex_byte,display_char,wait_key,_debug
+#endif
+
+	.data
+
+/* XHDI */
+
+#define XH_DL_SECSIZ 0 // maximal sector size (BIOS level)
+#define XH_DL_MINFAT 1 // minimal number of FATs
+#define XH_DL_MAXFAT 2 // maximal number of FATs
+#define XH_DL_MINSPC 3 // sectors per cluster minimal
+#define XH_DL_MAXSPC 4 // sectors per cluster maximal
+#define XH_DL_CLUSTS 5 // maximal number of clusters of a 16 bit FAT
+#define XH_DL_MAXSEC 6 // maximal number of sectors
+#define XH_DL_DRIVES 7 // maximal number of BIOS drives supported by the DOS
+
+	
+/* AHDI */
+
+#define PUN_DEV           0x1F /* device number of HD */
+#define PUN_UNIT          0x07 /* Unit number */
+#define PUN_SCSI          0x08 /* 1=SCSI 0=ACSI */
+#define PUN_IDE           0x10 /* Falcon IDE */
+#define PUN_USB           0x20 /* USB */
+#define PUN_REMOVABLE     0x40 /* Removable media */
+#define PUN_VALID         0x80 /* zero if valid */
+
+#define pinfo_puns      0  // 2 bytes
+#define pinfo_pun       2  // 32 bytes
+#define pinfo_pstart   34  // 32 x 4 bytes
+#define pinfo_cookie  162  // 4 bytes
+#define pinfo_cookptr 166  // 4 bytes
+#define pinfo_vernum  170  // 2 bytes
+#define pinfo_maxsiz  172  // 2 bytes
+#define pinfo_ptype   174  // 32 x 4 bytes
+#define pinfo_psize   302  // 32 x 4 bytes
+#define pinfo_flags   430  // 32 x 2 bytes, internal use: B15:swap, B7:change, B0:bootable
+#define pinfo_bpb     494  // 32 x 32 bytes
+#define pinfo_devnum 1518  // 32 bytes 
+#define pinfo_size   1550
+
+
+#if 1//#ifdef DEBUG_BIOS_LAYER
+//debug1:	.asciz "XBIOS #0x"
+//debug2:	.asciz "Setscreen 0x"
+debug3:	.asciz "hdv_rw 0x"
+debug4:	.ascii "hdv_bpb"
+	.byte 13,10,0
+debug5:	.ascii "hdv_mediach"
+	.byte 13,10,0
+//debug6:	.asciz "Vsetmode 0x"
+//debug7:	.asciz "ValidMode 0x"
+//debug8:	.asciz "Gettime 0x
+debug132:	.asciz "XHDI XHReadWrite 0x"
+debug133:	.ascii "XHDI XHInqTarget2"
+	.byte 13,10,0
+debug134:	.ascii "XHDI XHInqDev"
+	.byte 13,10,0
+debug135:	.ascii "XHDI XHInqDriver"
+	.byte 13,10,0
+debug136:	.ascii "XHDI XHInqDev2"
+	.byte 13,10,0
+debug137:	.ascii "XHDI XHDOSLimits"
+	.byte 13,10,0
+debug138:	.ascii "GALVEZ DEBUG"		/* Galvez: DEBUG */
+	.byte 13,10,0
+debug139:	.ascii "XHDI XHReadWrite"	/* Galvez: DEBUG */
+	.byte 13,10,0
+	.align 2
+#endif
+
+
+//	dc.l 0x58425241          // XBRA
+//	dc.l 0x5F504349          // _PCI
+//	dc.l 0                   // cannot store here because we are in flash
+
+
+
+text_color:
+
+	moveq #0,D0
+	move.w 0x3E86,D0         // number of planes
+	cmp.l #2,D0
+	bls.s .black_and_white
+	pea (A0)
+	move.w #9,-(SP)
+	trap #1                  // Cconws
+	addq.l #6,SP
+.black_and_white:
+	rts
+	
+#if defined(CONFIG_USB_KEYBOARD) || (CONFIG_USB_MOUSE)
+_asm_set_ipl:
+	link A6,#-8
+	movem.l D6-D7,(SP)
+	move.w SR,D7            //  current SR 
+	move.l D7,D0            //  prepare return value
+	and.l #0x0700,D0        // mask out IPL 
+	lsr.l #8,D0             // IPL 
+	move.l 8(A6),D6         // get argument 
+	and.l #7,D6             // least significant three bits 
+	lsl.l #8,D6             // move over to make mask 
+	and.l #0x0000F8FF,D7    // zero out current IPL 
+	or.l D6,D7              // place new IPL in SR 
+	move.w D7,SR
+	movem.l (SP),D6-D7
+	lea 8(SP),SP
+	unlk A6
+	rts
+	
+_call_ikbdvec:
+
+	lea -24(SP),SP
+	movem.l D0-D2/A0-A2,(SP)
+	move.l 28(SP),D0         // ikbd code 
+	move.l 32(SP),A0         // iorec 
+	and.l #0xFF,D0
+	move.l 0x1132,A2         // ikbdvec 
+	jsr (A2)
+	movem.l (SP),D0-D2/A0-A2
+	lea 24(SP),SP
+	rts
+
+_call_mousevec:
+
+	lea -24(SP),SP
+	movem.l D0-D2/A0-A2,(SP)
+	move.l 28(SP),A0         // data 
+	move.l 32(SP),A2
+	move.l (A2),A2           // mousevec 
+	jsr (A2)
+	movem.l (SP),D0-D2/A0-A2
+	lea 24(SP),SP
+	rts
+#endif
+
+install_xbra:	// A0: handler, D0: vector, D1: ID 
+
+	lea -28(SP),SP
+	movem.l D1-D3/A0-A3,(SP)
+	moveq #0,D3
+	move.w D0,D3             // vector
+	move.l A0,A3             // handler
+	move.l D1,-(SP)
+	move.w #3,-(SP)          // TT ram if possible
+	move.l #18,-(SP)         // size
+	move.w #0x44,-(SP)       // Mxalloc
+	trap #1 
+	addq.l #8,SP
+	move.l (SP)+,D1
+	tst.l D0
+	beq.s .error_xbra
+	move.l D0,A0
+	move.l #0x58425241,(A0)+ // XBRA
+	move.l D1,(A0)+
+	clr.l (A0)+	
+	move.w #0x4EF9,(A0)+     // JMP
+	move.l A3,(A0)+          // handler
+	lea -10(A0),A0
+
+	cpusha BC
+
+	move.l D3,A1
+	move.l (A1),D0
+	move.l D0,(A0)+          // old vector
+	move.l A0,(A1)           // JMP, new vector
+.error_xbra:
+	tst.l D0
+	movem.l (SP),D1-D3/A0-A3
+	lea 28(SP),SP
+	rts
+#if defined(CONFIG_USB_UHCI) || defined(CONFIG_USB_OHCI) || defined(CONFIG_USB_EHCI) || \
+	defined(CONFIG_USB_ISP116X_HCD) || defined(CONFIG_USB_ARANYM_HCD)
+#ifdef CONFIG_USB_STORAGE
+_install_usb_stor:
+	lea -32(SP),SP
+	movem.l D1-D4/A0-A3,(SP)
+	move.l 36(SP),D0         // dev_num
+	cmp.l #PUN_DEV,D0
+	bhi .no_pinfo            // error
+	move.l 40(SP),D2         // part_type
+	move.l D2,D1
+	and.l #0xFFFFFF,D1       // ID
+	// GEMDOS
+	cmp.l #0x47454D,D1       // GEM up to 16M
+	beq.s .partition_ok
+	cmp.l #0x42474D,D1       // BGM over 16M
+	beq.s .partition_ok
+	cmp.l #0x524157,D1       // RAW
+	beq.s .partition_ok
+	// DOS 1:FAT12, 0xB/0xC:FAT32
+	cmp.l #0x4,D2            // FAT16 up to 32M
+	beq.s .partition_ok
+	cmp.l #0x6,D2            // FAT16 over 32M
+	beq.s .partition_ok
+	tst.l ___mint		// Galvez: NOT MiNT? then go out
+	beq .invalid_partition_type
+	cmp.l #0xE,D2            // WIN95 FAT16
+	beq .partition_ok
+	cmp.l #0xB,D2		// FAT32
+	beq.s .partition_ok
+	cmp.l #0xC,D2		// FAT32
+	bne .partition_ok
+	cmp.l #0x81,D2		// MINIX
+	bne .partition_ok
+	cmp.l #0x83,D2		// EXT2/LNX
+	bne .partition_ok
+.partition_ok:
+	move.l old_pun_ptr,A2	// Galvez: we need it to update hd driver pun struct
+	move.l pun_ptr,D0
+	bne.s .pinfo_ok
+	move.w #3,-(SP)          // TT ram if possible
+	move.l #pinfo_size,-(SP)
+	move.w #0x44,-(SP)       // Mxalloc
+	trap #1 
+	addq.l #8,SP
+	move.l D0,pun_ptr
+	beq.s .no_pinfo
+	move.l D0,A3
+	clr.w pinfo_puns(A3)
+	move.w #0x0300,D0
+	move.w D0,pinfo_vernum(A3)
+	move.w #0x4000,D0
+	move.w D0,pinfo_maxsiz(A3)
+	lea pinfo_pun(A3),A0
+	moveq #-1,D0
+	move.w D0,(A0)+          // drives A/B
+	move.l D0,(A0)+
+	move.l D0,(A0)+
+	move.l D0,(A0)+
+	move.l D0,(A0)+
+	move.l D0,(A0)+
+	move.l D0,(A0)+
+	move.l D0,(A0)+
+	move.w D0,(A0)
+	lea pinfo_pstart(A3),A0
+	lea pinfo_size(A3),A1
+.clrpun:
+	clr.w -(A1)
+	cmp.l A0,A1
+	bgt.s .clrpun
+	move.l A3,D0             // pun_ptr 
+.pinfo_ok:
+	move.l D0,A3             // pun_ptr 
+	moveq #2,D4              // drive C 
+	move.l _drvbits,D0
+.search_empty_drive_usb:
+	btst D4,D0
+	beq.s .drive_not_exist_usb
+	addq.l #1,D4
+	cmp.l #MAX_LOGICAL_DRIVE,D4
+	bcs.s .search_empty_drive_usb
+	bra .drive_full_usb          // all drives already used 
+.no_pinfo:
+	moveq #0,D0              // not installed 
+	bra .end_usb_disk
+.drive_not_exist_usb:
+	move.w pinfo_puns(A3),D0
+	addq.l #1,D0
+	move.w D0,pinfo_puns(A3)
+	moveq #0,D0
+	bset #7,D0               // changed
+	lea pinfo_flags(A3),A0
+	move.l D0,(A0,D4.l*4)    // B15:swap, B7:change, B0:bootable
+	lea pinfo_psize(A3),A0
+	move.l 48(SP),D3         // part_size
+	move.l 44(SP),D1         // part_offset
+	move.l 40(SP),D2         // part_type
+	move.l 36(SP),D0         // dev_num
+	move.b D0,pinfo_devnum(A3,D4.l)
+	move.l D2,pinfo_ptype(A3,D4.l*4)
+	move.l D4,D2
+	or.l #PUN_USB,D2
+	move.b D2,pinfo_pun(A3,D4.l)
+	cmp.l #15,D4			// Galvez: update AHDI pun struct:
+	bgt .ahdi_part_num_limit	// Galvez: if logical part. > 16
+	move.b D2,pinfo_pun(A2,D4.l)	// Galvez: don't update pun struct,
+	move.w D0,-(SP)			// Galvez: to avoid corruption.
+	move.w pinfo_puns(A2),D0	// Galvez: update hd driver pun stuct
+	addq.l #1,D0			// Galvez: othewise MiNT only handles 16MB
+	move.w D0,pinfo_puns(A2)	// Galvez: when not using XHDI
+	move.w (SP)+,D0			// Galvez: see BLOCK_IO.c (MiNT sources)
+.ahdi_part_num_limit:			
+	move.l D3,(A0,D4.l*4)    // size
+	move.l D1,pinfo_pstart(A3,D4.l*4)	
+	move.l _dskbufp,A0 
+	move.l A0,-(SP)          // buffer
+	move.l #1,-(SP)          // blkcnt	
+	move.l D1,-(SP)          // blknr
+	move.l D0,-(SP)          // devnum
+	jsr _usb_stor_read
+	lea 16(SP),SP
+	tst.l D0
+	beq .end_usb_disk        // read error
+	tst.l _usb_1st_disk_drive
+	bne .usb_1st_drive_ok    // hdv vectors installed
+	move.l D4,_usb_1st_disk_drive
+	move.w SR,D0
+	move.w D0,-(SP)
+	or.l #0x700,D0           // mask interrupts
+	move.w D0,SR
+	move.l #0x5F555342,D1    // _USB
+	lea det_hdv_bpb_usb(PC),A0
+	move.w #hdv_bpb,D0
+	bsr install_xbra
+	move.l D0,old_hdv_bpb_usb
+	lea det_hdv_rw_usb(PC),A0
+	move.w #hdv_rw,D0
+	bsr install_xbra	
+	move.l D0,old_hdv_rw_usb
+	lea det_hdv_mediach_usb(PC),A0
+	move.w #hdv_mediach,D0
+	bsr install_xbra
+	move.l D0,old_hdv_mediach_usb
+	move.l cookie,D0
+	beq.s .no_cookie_jar
+	move.l D0,A0
+	move.l #0x58484449,D1    // XHDI
+.find_cookie_jar:
+	tst.l (A0)
+	beq.s .cookie_slot_free
+	cmp.l (A0),D1
+	beq.s .cookie_found
+	addq.l #8,A0
+	bra.s .find_cookie_jar
+.cookie_found:
+	move.l 4(A0),D0
+	move.l D0,old_xhdi
+	lea xhdi(PC),A1
+	clr.l -(SP)              	// XHGetVersion
+	move.l D0,A0
+	jsr (A0)
+	addq.l #4,SP
+	move.l D0,old_xhdi_version
+	move.l A1,-(SP)			
+	move.w #9,-(SP)			// Galvez: XHNewCookie
+	jsr (A0)
+	add.l #6,SP
+	tst.l D0
+	beq.s .no_cookie_jar
+	move.l A1,4(A0)			// Galvez: Replace cookie "by-hand"			
+	bra.s .no_cookie_jar
+.cookie_slot_free:
+	move.l 4(A0),12(A0)      // copy size
+	lea xhdi(PC),A1
+	move.l A1,(A0)+
+	clr.l (A0)
+	clr.l old_xhdi
+	move.l #0x120,D0         //  protocol version
+	move.l D0,old_xhdi_version
+.no_cookie_jar:
+	move.w (SP)+,D0
+	move.w D0,SR		// restore interrupts
+.usb_1st_drive_ok:
+	move.l _dskbufp,A0       // boot sector 
+	lea pinfo_bpb(A3),A1
+	move.l D4,D2             // logical drive 
+	asl.l #5,D2              // * 32 
+	add.l D2,A1
+	moveq #0,D2
+	move.b 0xC(A0),D2
+	asl.l #8,D2
+	move.b 0xB(A0),D2        // BPS 
+	move.w D2,(A1)           // sector size 
+	moveq #0,D1
+	move.b 0xD(A0),D1        // SPC 
+	move.w D1,2(A1)          // cluster size in sectors 
+	move.w D1,D0
+	mulu D2,D0	
+	move.w D0,4(A1)          // cluster size in bytes 
+	moveq #0,D0
+	move.b 0x12(A0),D0
+	asl.l #8,D0
+	move.b 0x11(A0),D0       // NDIRS 
+	asl.l #5,D0              // * 32 
+
+	divu D2,D0               // / sector size 
+
+	move.w D0,6(A1)          // size directory in sectors 
+	moveq #0,D2
+	move.b 0x17(A0),D2
+	asl.l #8,D2
+	move.b 0x16(A0),D2       // SPF 
+	move.w D2,8(A1)          // FAT size 
+	moveq #0,D0
+	move.b 0xF(A0),D0
+	asl.l #8,D0
+	move.b 0xE(A0),D0        // RES 
+	move.l D0,D3
+	add.l D2,D3              // + FAT size 
+	move.w D3,10(A1)         // 1st sector of FAT2  
+	moveq #0,D3
+	move.b 0x10(A0),D3       // NFATS 
+	mulu D2,D3               // * FAT size 
+	add.l D0,D3              // + RES 
+	moveq #0,D0
+	move.w 6(A1),D0          // size directory in sectors 
+	add.l D3,D0
+	move.w D0,12(A1)         // 1st data sector 
+	moveq #0,D2
+	move.b 0x14(A0),D2
+	asl.l #8,D2
+	move.b 0x13(A0),D2       // NSECTS 
+	bne.s .nsects_ok_usb
+	lea pinfo_psize(A3),A2
+	move.l (A2,D4.w*4),D2    // partition size in sectors 
+	sub.l D0,D2              // - 1st data sector 
+.nsects_ok_usb:
+	divu D1,D2
+
+	move.w D2,14(A1)         // total clusters 
+	moveq #1,D0 
+	move.w D0,16(A1)         // FAT 16 
+	clr.w 18(A1)
+	clr.l 20(A1)
+	clr.l 24(A1)
+	clr.l 28(A1)	
+	move.l _drvbits,D0
+	bset D4,D0
+	move.l D0,_drvbits
+	moveq #2,D0              // drive C 
+	cmp.l D4,D0
+	bne.s .no_set_drive_usb
+	move.w D0,_bootdev
+	move.w D0,-(SP)
+	move.w #0xE,-(SP)        // Dsetdrv 
+	trap #1
+	addq.l #4,SP
+.no_set_drive_usb:
+	move.l 36(SP),D0         // devnum        
+	movem.l 52(SP),A1/A2/A3  // vendor / revision / product
+	move.l product_name,A0      // save product name pointer for XHDI
+#if DEBUG_BIOS_LAYER	
+	move.l D0, -(SP)
+	move.b D4,D0
+	jsr hex_byte		/* Galvez: DEBUG device */	
+	move.l (SP)+,D0
+#endif
+	move.l A3,(A0,D4.l*4)
+	bsr display_drive_usb
+	pea message2b(PC)
+	move.w #9,-(SP)
+	trap #1                  // Cconws
+	addq.l #6,SP
+	moveq #0x41,D0           // A
+	add.l D4,D0
+	move.w D0,-(SP)
+	move.w #2,-(SP)
+	trap #1                  // Cconout
+	addq.l #4,SP
+	pea crlf(PC)
+	move.w #9,-(SP)
+	trap #1                  // Cconws
+	addq.l #6,SP
+	move.l D4,D0             // OK
+	bra.s .end_usb_disk
+.invalid_partition_type:
+	pea error4(PC)
+	bra.s .display_error_usb
+.drive_full_usb:
+	pea error2(PC)
+.display_error_usb:
+	move.l 36+4(SP),D0       // devnum 
+        movem.l 52+4(SP),A1/A2/A3 // vendor / revision / product 
+	bsr display_drive_usb
+	move.w #0x2C,-(SP)
+	move.w #2,-(SP)
+	trap #1                  // Cconout 
+	addq.l #4,SP
+	move.w #0x20,-(SP)
+	move.w #2,-(SP)
+	trap #1                  // Cconout 
+	addq.l #4,SP
+	move.w #9,-(SP)
+	trap #1                  // Cconws 
+	addq.l #6,SP
+	moveq #0,D0              // not installed 
+.end_usb_disk:
+	movem.l (SP),D1-D4/A0-A3
+	lea 32(SP),SP
+	rts
+
+display_drive_usb:
+
+	move.l A1,-(SP)
+	moveq #0x30,D1
+	add.l D1,D0	            // dev_num 
+	move.w D0,-(SP)         
+	lea blue(PC),A0
+	bsr text_color
+	pea message2(PC)         // USB-disk installed 
+	move.w #9,-(SP)
+	trap #1                  // Cconws 
+	addq.l #6,SP
+	move.w #2,-(SP)
+	trap #1                  // Cconout 
+	addq.l #4,SP
+	move.w #0x2E,-(SP)
+	move.w #2,-(SP)
+	trap #1                  // Cconout 
+	addq.l #4,SP
+	move.w #0x30,-(SP)
+	move.w #2,-(SP)
+	trap #1                  // Cconout 
+	addq.l #4,SP
+	lea black(PC),A0
+	bsr text_color
+	move.w #0x20,-(SP)
+	move.w #2,-(SP)
+	trap #1                  // Cconout 
+	addq.l #4,SP
+	move.w #9,-(SP)
+	trap #1                  // Cconws 
+	addq.l #6,SP    
+	move.w #0x20,-(SP)
+	move.w #2,-(SP)
+	trap #1                  // Cconout 
+	addq.l #4,SP
+        move.l A2,-(SP)
+	move.w #9,-(SP)
+	trap #1                  // Cconws 
+	addq.l #6,SP             
+	move.w #0x20,-(SP)
+	move.w #2,-(SP)
+	trap #1                  // Cconout 
+	addq.l #4,SP
+        move.l A3,-(SP)
+	move.w #9,-(SP)
+	trap #1                  // Cconws 
+	addq.l #6,SP
+	rts
+
+det_hdv_bpb_usb:
+	move.l A0,-(SP)
+	move.l pun_ptr,A0
+ 	moveq #0,D0
+	move.w 4+4(SP),D0        // drive
+	cmp.l _usb_1st_disk_drive,D0
+	bcs.s .dhbu2
+	cmp.l #MAX_LOGICAL_DRIVE,D0
+	bcc.s .dhbu2
+	tst.b pinfo_pun(A0,D0.l)
+	bpl.s .dhbu1
+.dhbu2:
+	move.l (SP)+,A0
+	moveq #0,D0
+	move.l old_hdv_bpb_usb,-(SP)
+	rts
+.dhbu1:
+	move.l D1,-(SP)
+	move.l pinfo_ptype(A0,D0.l*4),D1
+	and.l #0xFFFFFF,D1
+	cmp.l #0x524157,D1       // RAW
+	beq.s .dhbu4
+	cmp.l #0x81,D1       	 // MINIX
+	beq.s .dhbu4
+	cmp.l #0x83,D1       	 // EXT2/LNX
+	bne.s .dhbu3
+.dhbu4:
+	move.l (SP)+,D1
+	move.l (SP)+,A0
+	moveq #0,D0
+	rts	
+.dhbu3:
+	lea pinfo_bpb(A0),A0
+	asl.l #5,D0              // * 32
+	add.l A0,D0
+#if DEBUG_BIOS_LAYER
+	move.l D0,-(SP)
+	moveq #0x30,D0
+	jsr display_char
+	moveq #0x78,D0
+	jsr display_char
+	move.l (SP),D0
+	jsr hex_long
+	moveq #0x20,D0
+	jsr display_char
+	lea debug4(PC),A0
+	jsr display_string
+	move.l (SP)+,D0
+#endif
+	move.l (SP)+,D1
+	move.l (SP)+,A0
+	rts
+
+det_hdv_rw_usb:
+
+	lea -28(SP),SP
+	movem.l D1-D4/A0-A2,(SP)
+#if DEBUG_BIOS_LAYER
+	lea debug3(PC),A0
+	jsr display_string	
+	move.w 4+28(SP),D0       // rwflag
+	jsr hex_word
+	moveq #0x20,D0
+	jsr display_char
+	moveq #0x30,D0
+	jsr display_char
+	moveq #0x78,D0
+	jsr display_char
+	move.l 6+28(SP),D0       // buffer
+	jsr hex_long
+	moveq #0x20,D0
+	jsr display_char
+	moveq #0x30,D0
+	jsr display_char
+	moveq #0x78,D0
+	jsr display_char
+	move.w 10+28(SP),D0      // num sectors
+	jsr hex_word
+	moveq #0x20,D0
+	jsr display_char
+	moveq #0x30,D0
+	jsr display_char
+	moveq #0x78,D0
+	jsr display_char
+	move.w 12+28(SP),D0      // logical sector
+	jsr hex_word
+	moveq #0x20,D0
+	jsr display_char
+	moveq #0x30,D0
+	jsr display_char
+	moveq #0x78,D0
+	jsr display_char
+	move.w 16+28(SP),D0      // Galvez: logical sector (lrecno)
+	jsr hex_long
+	moveq #0x20,D0
+	jsr display_char
+	moveq #0x30,D0
+	jsr display_char
+	moveq #0x78,D0
+	jsr display_char
+	move.w 14+28(SP),D0      // drive
+	jsr hex_word
+	moveq #13,D0
+	jsr display_char
+	moveq #10,D0
+	jsr display_char
+#endif
+	btst #3,5+28(SP)         // rwflag
+	bne.s .dhru8             // physical
+	move.l pun_ptr,A0
+ 	moveq #0,D0
+	move.w 14+28(SP),D0      // drive
+	cmp.l _usb_1st_disk_drive,D0
+	bcs.s .dhru8
+	cmp.l #MAX_LOGICAL_DRIVE,D0
+	bcc.s .dhru8
+	moveq #0,D4
+	move.b pinfo_pun(A0,D0.l),D4
+	bpl.s .dhru1             // valid
+.dhru8:
+	movem.l (SP),D1-D4/A0-A2
+	lea 28(SP),SP
+	moveq #0,D0
+	move.l old_hdv_rw_usb,-(SP)
+	rts
+.dhru1:
+	move.l D4,D2
+	and.l #PUN_USB,D2
+	beq.s .dhru8             // not USB
+	and.l #PUN_DEV,D4
+	moveq #0,D2
+	move.w 12+28(SP),D2      // logical sector
+	cmp.w #0xffff,D2         // Galvez: check recno <> -1
+	bne.s .dhru6		
+	move.l 16+28(SP),D2      // logical sector
+.dhru6:
+	tst.l D2
+	bmi .dhru2               // negative logical sector
+	move.l 6+28(SP),D1       // buffer
+	beq .dhru4               // no buffer
+	move.l pinfo_pstart(A0,D0.l*4),D3
+	move.l pinfo_devnum(A0,D0.l),D4	 // devnum in the USB bus
+	lea pinfo_bpb(A0),A0
+	asl.l #5,D0              // * 32
+	add.l D0,A0
+	move.w 14(A0),D0         // total clusters
+	mulu.w 2(A0),D0          // cluster size in sectors
+	cmp.l D0,D2              // logical sector to hight
+	bcc .dhru2
+	moveq #0,D0
+	move.w (A0),D0           // sector size
+	lsr.l #8,D0
+	lsr.l #1,D0              // / 512
+	move.l D1,A0             // buffer
+	move.w 10+28(SP),D1      // num sectors
+	beq .dhru4               // no sectors
+	mulu D0,D1
+	mulu.l D0,D2
+	add.l D3,D2              // start sector
+	move.l D1,D3             // count
+	btst #0,5+28(SP)         // rwflag
+	beq.s .dhru7             // read
+	// write
+	tst.l D2                 // logical sector
+	beq.s .dhru2             // root sector
+	move.l A0,-(SP)          // buffer
+	move.l D3,-(SP)          // blkcnt	
+	move.l D2,-(SP)          // blknr
+	move.l D4,-(SP)          // USB devnum 
+	jsr _usb_stor_write
+	bra.s .dhru5
+.dhru2:
+	moveq #-1,D0             // error
+	bra.s .dhru3
+.dhru4:
+	moveq #0,D0              // OK
+	bra.s .dhru3
+.dhru7:
+	move.l A0,-(SP)          // buffer
+	move.l D3,-(SP)          // blkcnt	
+	move.l D2,-(SP)          // blknr
+	move.l D4,-(SP)          // USB devnum
+	jsr _usb_stor_read
+.dhru5:
+	lea 16(SP),SP
+	tst.l D0
+	seq.b D0
+	ext.w D0
+	ext.l D0
+	bclr #0,D0               // OK or device not responding -2
+.dhru3:
+	movem.l (SP),D1-D4/A0-A2
+	lea 28(SP),SP
+ 	rts
+
+det_hdv_mediach_usb:
+
+	move.l A0,-(SP)
+	move.l pun_ptr,A0
+ 	moveq #0,D0
+	move.w 4+4(SP),D0        // drive
+	cmp.l _usb_1st_disk_drive,D0
+	bcs.s .dhmu2
+	cmp.l #MAX_LOGICAL_DRIVE,D0
+	bcc.s .dhmu2
+	tst.b pinfo_pun(A0,D0.l)
+	bpl.s .dhmu1
+.dhmu2:
+	move.l (SP)+,A0
+	moveq #0,D0
+	move.l old_hdv_mediach_usb,-(SP)
+	rts
+.dhmu1:
+#if 0 // #if DEBUG_BIOS_LAYER
+	move.l A0,-(SP)
+	lea debug5(PC),A0
+	jsr display_string
+	move.l (SP)+,A0
+#endif
+	lea pinfo_flags(A0),A0
+	add.l D0,A0
+	add.l D0,A0
+	bclr #7,1(A0)
+	sne.b D0
+	and.l #2,D0
+	move.l (SP)+,A0
+	rts
+
+	// XHDI
+	
+	dc.l 0x27011992
+	
+xhdi:
+	link A6,#0
+	movem.l D1-A5,-(SP)
+	moveq #0,D1
+	move.w 8(A6),D1
+
+	move.w D1,D0
+#if DEBUG_BIOS_LAYER	
+	move.w D0, -(SP)
+	jsr hex_word		/* Galvez: DEBUG. XHDI function */
+	move.w (SP)+,D0
+#endif	
+	moveq #-32,D0            // invalid function
+	cmp.l #18,d1
+	bcc.s .bad_xhdi
+	move.w SR,D0             // supervisor only
+	moveq #-1,d0             // error
+	move.w tab_xhdi(PC,D1.l*2),D1
+	jsr tab_xhdi(PC,D1.W)
+	
+.bad_xhdi:
+	movem.l (SP)+,D1-A5
+	unlk A6
+	rts
+#if DEBUG_BIOS_LAYER
+debug:
+	lea debug138(PC),A0
+	jsr display_string
+	rts
+#endif
+	
+tab_xhdi:
+	dc.w XHGetVersion-tab_xhdi    // 0
+	dc.w XHInqTarget-tab_xhdi     // 1
+	dc.w XHReserve-tab_xhdi       // 2
+	dc.w XHLock-tab_xhdi          // 3
+	dc.w XHStop-tab_xhdi          // 4
+	dc.w XHEject-tab_xhdi         // 5
+	dc.w XHDrvMap-tab_xhdi        // 6
+	dc.w XHInqDev-tab_xhdi        // 7
+	dc.w XHInqDriver-tab_xhdi     // 8
+	dc.w XHNewCookie-tab_xhdi     // 9
+	dc.w XHReadWrite-tab_xhdi     // 10
+	dc.w XHInqTarget2-tab_xhdi    // 11
+	dc.w XHInqDev2-tab_xhdi       // 12
+	dc.w XHDriverSpecial-tab_xhdi // 13
+	dc.w XHGetCapacity-tab_xhdi   // 14
+	dc.w XHMediumChanged-tab_xhdi // 15
+	dc.w XHMiNTInfo-tab_xhdi      // 16
+	dc.w XHDOSLimits-tab_xhdi     // 17
+	
+XHGetVersion:
+#if DEBUG_BIOS_LAYER
+	move.l A0,-(SP)
+	lea debug138(PC),A0
+	jsr display_string
+	move.l (SP)+,A0
+#endif
+	move.l #0x120,D0         //  protocol version
+	move.l old_xhdi_version,D1
+	cmp.l D1,D0
+	bcs.s .xv1
+	move.l D1,D0             // minimum version
+.xv1:	
+	rts
+	
+XHInqTarget:
+
+	moveq #32,D2             // stringlen
+	bra.s .xi1
+	
+XHInqTarget2:
+
+#if DEBUG_BIOS_LAYER
+	move.l A0,-(SP)
+	lea debug133(PC),A0
+	jsr display_string
+	move.l (SP)+,A0
+#endif
+	move.w 26(A6),D2         // stringlen
+.xi1:
+	tst.w 12(A6)             // minor
+	bne.s .xi2
+	moveq #0,D0
+	move.w 10(A6),D0         // major
+	cmp.w #PUN_USB,D0
+	bcs.s .xi2
+	cmp.w #PUN_USB+PUN_DEV,D0
+	bls.s .xi3
+.xi2:
+	tst.l old_xhdi
+	beq.s .xi7
+	moveq #-15,D0            // unknown device
+	rts
+.xi7:
+	move.l old_xhdi,-(SP)
+	rts
+.xi3:
+	tst.l 14(A6)
+	beq.s .xi8
+	move.l 14(A6),A0
+	move.l #512,(A0)
+.xi8:
+	tst.l 18(A6)
+	beq.s .xi9
+	move.l 18(A6),A0	 // flags
+	move.l #0x00000002,(A0)  // removable
+.xi9:
+	move.l 22(A6),D1         // product_name
+	beq.s .xi6		 // no pointer
+	move.l D1,A0
+
+	and.b #PUN_DEV,D0
+	move.l product_name,A1
+	move.l (A1,D0.l*4),D0    // Galvez: D0 should be the bios drive number			
+	beq.s .xi6               // no pointer
+	move.l D0,A1
+.xi5:
+	move.b (A1)+,(A0)+
+	beq.s .xi4
+	subq.w #1,D2
+	bpl.s .xi5		// Galvez: test
+.xi4:
+	clr.b -1(A0)
+.xi6:
+	moveq #0,D0
+	rts
+
+XHReserve:
+XHLock:
+XHStop:
+XHEject:
+
+	tst.l old_xhdi
+	beq.s .xnu1
+	moveq #0,D0
+	rts
+.xnu1:
+	move.l old_xhdi,-(SP)
+	rts
+	
+XHDrvMap:
+
+	move.l _drvbits,D0
+	rts
+
+XHInqDev:
+
+#if DEBUG_BIOS_LAYER
+	lea debug134(PC),A0
+	jsr display_string
+#endif
+	
+	move.l pun_ptr,A0
+ 	moveq #0,D0
+	move.w 10(A6),D0         // bios_device
+	cmp.l _usb_1st_disk_drive,D0
+	bcs.s .xd2
+	cmp.l #MAX_LOGICAL_DRIVE,D0
+	bcc.s .xd2
+	moveq #0,D1
+	move.b pinfo_pun(A0,D0.l),D1
+	bpl.s .xd1
+.xd2:	
+
+	tst.l old_xhdi
+	beq.s .xd3
+	moveq #-46,D0            // invalid drive number
+		
+	rts
+.xd3:
+	move.l old_xhdi,-(SP)
+	rts
+.xd1:	
+	move.l D1,D2
+	and.l #PUN_USB+PUN_DEV,D2
+	beq.s .xd2
+	tst.l 12(A6)
+	beq.s .xd4
+	move.l 12(A6),A1         // major
+	move.w D1,(A1)
+.xd4:
+	tst.l 16(A6)
+	beq.s .xd5
+	move.l 16(A6),A1         // minor
+	clr.w (A1)
+.xd5:
+	tst.l 20(A6)
+	beq.s .xd6
+	move.l pinfo_pstart(A0,D0.l*4),D1
+	move.l 20(A6),A1         // start_sector
+	move.l D1,(A1)
+.xd6:
+	lea pinfo_bpb(A0),A0
+	asl.l #5,D0              // * 32
+	add.l A0,D0
+	tst.l 24(A6)
+	beq.s .xd7
+	move.l 24(A6),A1         // bpb
+	move.l D0,(A1)
+.xd7:
+	moveq #0,D0
+	rts
+
+XHInqDriver:
+
+#if DEBUG_BIOS_LAYER
+	lea debug135(PC),A0
+	jsr display_string
+#endif	
+	move.l pun_ptr,A0
+ 	moveq #0,D0
+	move.w 10(A6),D0         // bios_device
+	cmp.l _usb_1st_disk_drive,D0
+	bcs.s .xdr2
+	cmp.l #MAX_LOGICAL_DRIVE,D0
+	bcc.s .xdr2
+	moveq #0,D1
+	move.b pinfo_pun(A0,D0.l),D1
+	bpl.s .xdr1
+.xdr2:	
+	tst.l old_xhdi
+	beq.s .xdr8
+	moveq #-46,D0            // invalid drive number
+	rts
+.xdr8:
+	move.l old_xhdi,-(SP)
+	rts
+.xdr1:
+	move.l D1,D0
+	and.l #PUN_USB,D0
+	beq.s .xdr2
+	move.l 12(A6),D0         // name, 17 characters
+	beq.s .xdr3
+	move.l D0,A1
+	lea message1(PC),A0
+	moveq #17,D1
+.xdr6:
+	move.b (A0)+,D0
+	beq.s .xdr7
+	move.b D0,(A1)+
+	subq.l #1,D1
+	bpl.s .xdr6
+.xdr7:
+	clr.b (A1)
+.xdr3:
+	move.l 16(A6),D0         // version, 7 characters
+	beq.s .xdr4
+	move.l D0,A1
+	move.b #0x34,(A1)+       // ??? TOS 4.04
+	move.b #0x2E,(A1)+
+	move.b #0x30,(A1)+
+	move.b #0x34,(A1)+
+	clr.b (A1)
+.xdr4:
+	move.l 20(A6),D0         // company, 17 characters
+	beq.s .xdr5
+	move.l D0,A1
+	clr.b (A1)
+.xdr5:
+	move.l 24(A6),A1         // ahdi_version
+	move.w pinfo_vernum(A0),(A1)
+	move.l 28(A6),A1         // maxIPL
+	moveq #5,D0
+	move.w D0,(A1)	
+	moveq #0,D0
+	rts
+
+XHReadWrite:                      // read / write physical sectors
+#if DEBUG_BIOS_LAYER
+	lea debug139(PC),A0
+	jsr display_string
+#endif	
+
+	tst.w 12(A6)             // minor
+	bne.s .xr4
+	moveq #0,D4
+	move.w 10(A6),D4         // major
+	cmp.l #PUN_USB,D4
+	bcs.s .xr4
+	cmp.l #PUN_USB+PUN_DEV,D4
+	bls.s .xr1
+.xr4:
+	tst.l old_xhdi
+	beq.s .xr6
+	moveq #-15,D0            // unknown device
+	rts
+.xr6:
+	move.l old_xhdi,-(SP)
+	rts
+.xr1:
+#if DEBUG_BIOS_LAYER
+	lea debug132(PC),A0
+	jsr display_string
+	move.w 14(A6),D0         // rwflag
+	jsr hex_word
+	moveq #0x20,D0
+	jsr display_char
+	moveq #0x30,D0
+	jsr display_char
+	moveq #0x78,D0
+	jsr display_char
+	move.l 24(A6),D0         // buffer
+	jsr hex_long
+	moveq #0x20,D0
+	jsr display_char
+	moveq #0x30,D0
+	jsr display_char
+	moveq #0x78,D0
+	jsr display_char
+	move.w 20(A6),D0         // num sectors
+	jsr hex_word
+	moveq #0x20,D0
+	jsr display_char
+	moveq #0x30,D0
+	jsr display_char
+	moveq #0x78,D0
+	jsr display_char
+	move.l 16(A6),D0         // logical sector
+	jsr hex_long
+	moveq #13,D0
+	jsr display_char
+	moveq #10,D0
+	jsr display_char	
+#endif
+	move.l 22(A6),A0         // buffer
+	moveq #0,D3
+	move.w 20(A6),D3         // count
+	beq .xr2                 // no sectors
+        move.l 16(A6),D2         // start sector
+	btst #0,15(A6)           // rwflag
+	beq.s .xr7               // read
+	// write
+	move.l A0,-(SP)          // buffer
+	move.l D3,-(SP)          // blkcnt	
+	move.l D2,-(SP)          // blknr
+	move.l D4,D0             // major
+	and.l #PUN_DEV,D0
+	move.l pun_ptr,A0	
+	move.b pinfo_devnum(A0,D0.l),D0 // devnum in the USB bus
+	move.l D0,-(SP)          // USB devnum
+	jsr _usb_stor_write
+	bra.s .xr5
+.xr2:
+	moveq #-1,D0             // error
+	bra.s .xr3
+.xr7:
+	move.l A0,-(SP)          // buffer
+	move.l D3,-(SP)          // blkcnt	
+	move.l D2,-(SP)          // blknr
+	move.l D4,D0             // major
+	and.l #PUN_DEV,D0
+	move.l pun_ptr,A0	
+	move.b pinfo_devnum(A0,D0.l),D0 // devnum in the USB bus
+	move.l D0,-(SP)          // USB devnum
+	jsr _usb_stor_read
+.xr5:
+	lea 16(SP),SP
+	tst.l D0
+	seq.b D0
+	ext.w D0
+	ext.l D0
+	bclr #0,D0               // OK or device not responding -2
+.xr3:
+ 	rts
+
+XHInqDev2:
+
+#if DEBUG_BIOS_LAYER
+	lea debug136(PC),A0
+	jsr display_string	// Galvez: changed bsr by jsr to avoid linker error
+#endif
+	move.l pun_ptr,A0
+ 	moveq #0,D0
+	move.w 10(A6),D0         // bios_device
+	cmp.l _usb_1st_disk_drive,D0
+	bcs.s .xdd2
+	cmp.l #MAX_LOGICAL_DRIVE,D0
+	bcc.s .xdd2
+	moveq #0,D1
+	move.b pinfo_pun(A0,D0.l),D1
+	bpl.s .xdd1
+.xdd2:	
+	tst.l old_xhdi
+	beq.s .xdd4
+	moveq #-46,D0            // invalid drive number
+	rts
+.xdd4:
+	move.l old_xhdi,-(SP)
+	rts
+.xdd1:	
+	move.w D1,D2
+	and.b #PUN_USB+PUN_DEV,D2
+	beq.s .xdd2
+	tst.l 12(A6)
+	beq.s .xdd5
+	move.l 12(A6),A1         // major
+	move.w D2,(A1)
+.xdd5:
+	tst.l 16(A6)
+	beq.s .xdd6
+	move.l 16(A6),A1         // minor
+	clr.w (A1)
+.xdd6:
+	tst.l 20(A6)
+	beq.s .xdd7
+	move.l pinfo_pstart(A0,D0.l*4),D1
+	move.l 20(A6),A1         // start_sector
+	move.l D1,(A1)
+.xdd7:
+	tst.l 24(A6)
+	beq.s .xdd8
+	lea pinfo_bpb(A0),A2
+	move.l D0,D1
+	asl.l #5,D1              // * 32
+	add.l A2,D1
+	move.l 24(A6),A1         // bpb
+	move.l D1,(A1)
+.xdd8:
+	tst.l 28(A6)
+	beq.s .xdd9
+	move.l 28(A6),A1         // blocks
+	lea pinfo_psize(A0),A2
+	move.l (A2,D0.l*4),(A1)
+.xdd9:
+	tst.l 32(A6)
+	beq.s .xdd10
+	move.l 32(A6),A1         // partid
+	clr.l (A1)
+	move.b pinfo_ptype+3(A0,D0.l*4),D1   
+	move.w #0x0044,(A1)          		// NULL+ 'D'
+	move.b D1,2(A1)
+.xdd10:
+	moveq #0,D0
+	rts
+ 
+XHDriverSpecial:
+XHGetCapacity:
+XHMediumChanged:
+XHMiNTInfo:
+XHNewCookie:
+
+	tst.l old_xhdi
+	beq.s .xn1
+	moveq #-32,D0            //  invalid function number 
+	rts
+.xn1:
+	move.l old_xhdi,-(SP)
+	rts
+
+XHDOSLimits:
+
+	tst.l old_xhdi
+	bne.s .xn1
+#if DEBUG_BIOS_LAYER
+	lea debug137(PC),A0
+	jsr display_string
+#endif
+	moveq #0,D0
+	move.w 10(A6),D0         // which
+	cmp.l #XH_DL_SECSIZ,D0   // maximal sector size (BIOS level)
+	bne.s .xl1
+	move.l #0x4000,D0
+	rts	
+.xl1:
+	cmp.l #XH_DL_MINFAT,D0   // minimal number of FATs
+	bne.s .xl2
+	moveq #1,D0
+	rts
+.xl2:
+	cmp.l #XH_DL_MAXFAT,D0   // maximal number of FATs
+	bne.s .xl3
+	moveq #2,D0
+	rts
+.xl3:
+	cmp.l #XH_DL_MINSPC,D0   // sectors per cluster minimal
+	bne.s .xl4
+	moveq #2,D0
+	rts
+.xl4:
+	cmp.l #XH_DL_MAXSPC,D0   // sectors per cluster maximal
+	bne.s .xl5
+#ifdef COLDFIRE
+	moveq #64,D0             // for this Coldfire version of BDOS, else 2
+#else
+	moveq #2,D0
+#endif
+	rts
+.xl5:
+	cmp.l #XH_DL_CLUSTS,D0   // maximal number of clusters of a 16 bit FAT
+	bne.s .xl6
+	move.l #0x8000,D0
+	rts	
+.xl6:
+	cmp.l #XH_DL_MAXSEC,D0   // maximal number of sectors
+	bne.S .xl7
+#ifdef COLDFIRE
+	move.l #0x200000,D0      // for this Coldfire version of BDOS, else 0x10000
+#else
+	move.l #0x10000,D0
+#endif
+	rts
+.xl7:
+	cmp.l #XH_DL_DRIVES,D0   // maximal number of BIOS drives supported by the DOS
+	bne.s .xl8
+	moveq #16,D0
+	rts
+.xl8:
+	moveq #-32,D0            // invalid function number 
+	rts
+
+	
+
+
+#endif /* CONFIG_USB_STORAGE */
+#endif /* CONFIG_USB_UHCI || CONFIG_USB_OHCI || CONFIG_USB_EHCI || CONFIG_USB_ISP116X_HCD */
+
+
+#if defined(CONFIG_USB_UHCI) || defined(CONFIG_USB_OHCI) || defined(CONFIG_USB_EHCI) || \
+	defined(CONFIG_USB_ISP116X_HCD) || defined(CONFIG_USB_ARANYM_HCD)
+#ifdef CONFIG_USB_STORAGE
+message1:	.ascii "TOS4.04 "
+message2:	.asciz "USB  "
+message2b:	.asciz ", disk installed in "
+#endif
+#endif
+
+crlf:	.byte 13,10,0
+error:	.asciz "No ram-disk installed, "
+error1:	.ascii "no enough radeon memory"
+	.byte 13,10,0
+error2:	.ascii "all drives already used"
+	.byte 13,10,0
+error3:	.ascii "error disk name"
+	.byte 13,10,0
+error4:	.ascii "partition type not supported"
+	.byte 13,10,0
+blue:	.byte 0x1B,0x62,0x34,0
+black:	.byte 0x1B,0x62,0x3F,0
+
+	.align 2
+
+#if defined(CONFIG_USB_UHCI) || defined(CONFIG_USB_OHCI) || defined(CONFIG_USB_EHCI) \
+	|| defined(CONFIG_USB_ISP116X_HCD) || defined(CONFIG_USB_ARANYM_HCD)
+#ifdef CONFIG_USB_STORAGE
+
+	.lcomm pun_ptr_usb,4
+	.lcomm user_sp,4
+
+	.lcomm _usb_1st_disk_drive,4
+	.lcomm old_hdv_bpb_usb,4
+	.lcomm old_hdv_rw_usb,4
+	.lcomm old_hdv_mediach_usb,4
+	.lcomm old_xhdi,4
+	.lcomm old_xhdi_version,4
+	.lcomm product_name,4*(PUN_DEV+1)
+#endif /* CONFIG_USB_STORAGE */
+#endif /* CONFIG_USB_UHCI || CONFIG_USB_OHCI || CONFIG_USB_EHCI || CONFIG_USB_ISP116X_HCD */
+
+
diff --git a/FireBee/trunk/usb/store/cmd_usb.c b/FireBee/trunk/usb/store/cmd_usb.c
new file mode 100644
index 0000000..9c6b3da
--- /dev/null
+++ b/FireBee/trunk/usb/store/cmd_usb.c
@@ -0,0 +1,731 @@
+/*
+ * Modified for Atari by David Gálvez 2010
+ * Modified for Atari by Didier Mequignon 2009
+ *
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland
+ *
+ * Most of this source has been derived from the Linux USB
+ * project.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+ 
+
+#include "config.h"
+#include "asm-m68k/byteorder.h"
+#include "usb.h"
+
+
+//#undef RESET_START_STOP_CMDS
+//#define RESET_START_STOP_CMDS
+
+#ifdef CONFIG_USB_STORAGE
+static int usb_stor_curr_dev = -1; /* current device */
+#endif
+
+#ifdef PCI_XBIOS
+extern short pci_init(void);
+#endif
+
+/* some display routines (info command) */
+char *usb_get_class_desc(unsigned char dclass)
+{
+	switch (dclass) {
+	case USB_CLASS_PER_INTERFACE:
+		return "See Interface";
+	case USB_CLASS_AUDIO:
+		return "Audio";
+	case USB_CLASS_COMM:
+		return "Communication";
+	case USB_CLASS_HID:
+		return "Human Interface";
+	case USB_CLASS_PRINTER:
+		return "Printer";
+	case USB_CLASS_MASS_STORAGE:
+		return "Mass Storage";
+	case USB_CLASS_HUB:
+		return "Hub";
+	case USB_CLASS_DATA:
+		return "CDC Data";
+	case USB_CLASS_VENDOR_SPEC:
+		return "Vendor specific";
+	default:
+		return "";
+	}
+}
+
+void usb_display_class_sub(unsigned char dclass, unsigned char subclass,
+			   unsigned char proto)
+{
+	switch (dclass) {
+	case USB_CLASS_PER_INTERFACE:
+		printf("See Interface");
+		break;
+	case USB_CLASS_HID:
+		printf("Human Interface, Subclass: ");
+		switch (subclass) {
+		case USB_SUB_HID_NONE:
+			printf("None");
+			break;
+		case USB_SUB_HID_BOOT:
+			printf("Boot ");
+			switch (proto) {
+			case USB_PROT_HID_NONE:
+				printf("None");
+				break;
+			case USB_PROT_HID_KEYBOARD:
+				printf("Keyboard");
+				break;
+			case USB_PROT_HID_MOUSE:
+				printf("Mouse");
+				break;
+			default:
+				printf("reserved");
+				break;
+			}
+			break;
+		default:
+			printf("reserved");
+			break;
+		}
+		break;
+	case USB_CLASS_MASS_STORAGE:
+		printf("Mass Storage, ");
+		switch (subclass) {
+		case US_SC_RBC:
+			printf("RBC ");
+			break;
+		case US_SC_8020:
+			printf("SFF-8020i (ATAPI)");
+			break;
+		case US_SC_QIC:
+			printf("QIC-157 (Tape)");
+			break;
+		case US_SC_UFI:
+			printf("UFI");
+			break;
+		case US_SC_8070:
+			printf("SFF-8070");
+			break;
+		case US_SC_SCSI:
+			printf("Transp. SCSI");
+			break;
+		default:
+			printf("reserved");
+			break;
+		}
+		printf(", ");
+		switch (proto) {
+		case US_PR_CB:
+			printf("Command/Bulk");
+			break;
+		case US_PR_CBI:
+			printf("Command/Bulk/Int");
+			break;
+		case US_PR_BULK:
+			printf("Bulk only");
+			break;
+		default:
+			printf("reserved");
+			break;
+		}
+		break;
+	default:
+		printf("%s", usb_get_class_desc(dclass));
+		break;
+	}
+}
+
+void usb_display_string(struct usb_device *dev, int idx)
+{
+	char buffer[256];
+	if (idx != 0) {
+		if (usb_string(dev, idx, &buffer[0], 256) > 0)
+			printf("String: \"%s\"", buffer);
+	}
+}
+
+void usb_display_desc(struct usb_device *dev)
+{
+	if (dev->descriptor.bDescriptorType == USB_DT_DEVICE) {
+		printf("%d: %s,  USB Revision %x.%x\n", dev->devnum,
+		usb_get_class_desc(dev->config.if_desc[0].bInterfaceClass),
+				   (dev->descriptor.bcdUSB>>8) & 0xff,
+				   dev->descriptor.bcdUSB & 0xff);
+
+		if (strlen(dev->mf) || strlen(dev->prod) ||
+		    strlen(dev->serial))
+			printf(" - %s %s %s\n", dev->mf, dev->prod,
+				dev->serial);
+		if (dev->descriptor.bDeviceClass) {
+			printf(" - Class: ");
+			usb_display_class_sub(dev->descriptor.bDeviceClass,
+					      dev->descriptor.bDeviceSubClass,
+					      dev->descriptor.bDeviceProtocol);
+			printf("\n");
+		} else {
+			printf(" - Class: (from Interface) %s\n",
+			       usb_get_class_desc(
+				dev->config.if_desc[0].bInterfaceClass));
+		}
+		printf(" - PacketSize: %d  Configurations: %d\n",
+			dev->descriptor.bMaxPacketSize0,
+			dev->descriptor.bNumConfigurations);
+		printf(" - Vendor: 0x%04x  Product 0x%04x Version %d.%d\n",
+			dev->descriptor.idVendor, dev->descriptor.idProduct,
+			(dev->descriptor.bcdDevice>>8) & 0xff,
+			dev->descriptor.bcdDevice & 0xff);
+	}
+
+}
+
+void usb_display_conf_desc(struct usb_config_descriptor *config,
+			   struct usb_device *dev)
+{
+	printf("   Configuration: %d\n", config->bConfigurationValue);
+	printf("   - Interfaces: %d %s%s%dmA\n", config->bNumInterfaces,
+	       (config->bmAttributes & 0x40) ? "Self Powered " : "Bus Powered ",
+	       (config->bmAttributes & 0x20) ? "Remote Wakeup " : "",
+		config->MaxPower*2);
+	if (config->iConfiguration) {
+		printf("   - ");
+		usb_display_string(dev, config->iConfiguration);
+		printf("\n");
+	}
+}
+
+void usb_display_if_desc(struct usb_interface_descriptor *ifdesc,
+			 struct usb_device *dev)
+{
+	printf("     Interface: %d\n", ifdesc->bInterfaceNumber);
+	printf("     - Alternate Setting %d, Endpoints: %d\n",
+		ifdesc->bAlternateSetting, ifdesc->bNumEndpoints);
+	printf("     - Class ");
+	usb_display_class_sub(ifdesc->bInterfaceClass,
+		ifdesc->bInterfaceSubClass, ifdesc->bInterfaceProtocol);
+	printf("\n");
+	if (ifdesc->iInterface) {
+		printf("     - ");
+		usb_display_string(dev, ifdesc->iInterface);
+		printf("\n");
+	}
+}
+
+void usb_display_ep_desc(struct usb_endpoint_descriptor *epdesc)
+{
+	printf("     - Endpoint %d %s ", epdesc->bEndpointAddress & 0xf,
+		(epdesc->bEndpointAddress & 0x80) ? "In" : "Out");
+	switch ((epdesc->bmAttributes & 0x03)) {
+	case 0:
+		printf("Control");
+		break;
+	case 1:
+		printf("Isochronous");
+		break;
+	case 2:
+		printf("Bulk");
+		break;
+	case 3:
+		printf("Interrupt");
+		break;
+	}
+	printf(" MaxPacket %d", epdesc->wMaxPacketSize);
+	if ((epdesc->bmAttributes & 0x03) == 0x3)
+		printf(" Interval %dms", epdesc->bInterval);
+	printf("\n");
+}
+
+/* main routine to diasplay the configs, interfaces and endpoints */
+void usb_display_config(struct usb_device *dev)
+{
+	struct usb_config_descriptor *config;
+	struct usb_interface_descriptor *ifdesc;
+	struct usb_endpoint_descriptor *epdesc;
+	int i, ii;
+
+	config = &dev->config;
+	usb_display_conf_desc(config, dev);
+	for (i = 0; i < config->no_of_if; i++) {
+		ifdesc = &config->if_desc[i];
+		usb_display_if_desc(ifdesc, dev);
+		for (ii = 0; ii < ifdesc->no_of_ep; ii++) {
+			epdesc = &ifdesc->ep_desc[ii];
+			usb_display_ep_desc(epdesc);
+		}
+	}
+	printf("\n");
+}
+
+static inline char *portspeed(int speed)
+{
+	if (speed == USB_SPEED_HIGH)
+		return "480 Mb/s";
+	else if (speed == USB_SPEED_LOW)
+		return "1.5 Mb/s";
+	else
+		return "12 Mb/s";
+}
+
+/* shows the device tree recursively */
+void usb_show_tree_graph(struct usb_device *dev, char *pre)
+{
+	int i, idx;
+	int has_child, last_child, port;
+
+	idx = strlen(pre);
+	printf(" %s", pre);
+	/* check if the device has connected children */
+	has_child = 0;
+	for (i = 0; i < dev->maxchild; i++) {
+		if (dev->children[i] != NULL)
+			has_child = 1;
+	}
+	/* check if we are the last one */
+	last_child = 1;
+	if (dev->parent != NULL) {
+		for (i = 0; i < dev->parent->maxchild; i++) {
+			/* search for children */
+			if (dev->parent->children[i] == dev) {
+				/* found our pointer, see if we have a
+				 * little sister
+				 */
+				port = i;
+				while (i++ < dev->parent->maxchild) {
+					if (dev->parent->children[i] != NULL) {
+						/* found a sister */
+						last_child = 0;
+						break;
+					} /* if */
+				} /* while */
+			} /* device found */
+		} /* for all children of the parent */
+		printf("\b+-");
+		/* correct last child */
+		if (last_child)
+			pre[idx-1] = ' ';
+	} /* if not root hub */
+	else
+		printf(" ");
+	printf("%d ", dev->devnum);
+	pre[idx++] = ' ';
+	pre[idx++] = has_child ? '|' : ' ';
+	pre[idx] = 0;
+	printf(" %s (%s, %dmA)\n", usb_get_class_desc(
+					dev->config.if_desc[0].bInterfaceClass),
+					portspeed(dev->speed),
+					dev->config.MaxPower * 2);
+	if (strlen(dev->mf) || strlen(dev->prod) || strlen(dev->serial))
+		printf(" %s  %s %s %s\n", pre, dev->mf, dev->prod, dev->serial);
+	printf(" %s\n", pre);
+	if (dev->maxchild > 0) {
+		for (i = 0; i < dev->maxchild; i++) {
+			if (dev->children[i] != NULL) {
+				usb_show_tree_graph(dev->children[i], pre);
+				pre[idx] = 0;
+			}
+		}
+	}
+}
+
+/* main routine for the tree command */
+void usb_show_tree(struct usb_device *dev)
+{
+	char preamble[32];
+
+	memset(preamble, 0, 32);
+	usb_show_tree_graph(dev, &preamble[0]);
+}
+
+
+/******************************************************************************
+ * usb boot command intepreter. Derived from diskboot
+ */
+#if 0
+#ifdef CONFIG_USB_STORAGE
+int do_usbboot(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
+{
+	char *boot_device = NULL;
+	char *ep;
+	int dev, part = 1, rcode;
+	ulong addr, cnt;
+	disk_partition_t info;
+	image_header_t *hdr;
+	block_dev_desc_t *stor_dev;
+#if defined(CONFIG_FIT)
+	const void *fit_hdr = NULL;
+#endif
+
+	switch (argc) {
+	case 1:
+		addr = CONFIG_SYS_LOAD_ADDR;
+		boot_device = getenv("bootdevice");
+		break;
+	case 2:
+		addr = strtoul(argv[1], NULL, 16);
+		boot_device = getenv("bootdevice");
+		break;
+	case 3:
+		addr = strtoul(argv[1], NULL, 16);
+		boot_device = argv[2];
+		break;
+	default:
+//		cmd_usage(cmdtp);
+		return 1;
+	}
+
+	if (!boot_device) {
+		puts("\n** No boot device **\n");
+		return 1;
+	}
+
+	dev = strtoul(boot_device, &ep, 16);
+	stor_dev = usb_stor_get_dev(dev);
+	if (stor_dev->type == DEV_TYPE_UNKNOWN) {
+		printf("\n** Device %d not available\n", dev);
+		return 1;
+	}
+	if (stor_dev->block_read == NULL) {
+		printf("storage device not initialized. Use usb scan\n");
+		return 1;
+	}
+	if (*ep) {
+		if (*ep != ':') {
+			puts("\n** Invalid boot device, use `dev[:part]' **\n");
+			return 1;
+		}
+		part = strtoul(++ep, NULL, 16);
+	}
+
+	if (get_partition_info(stor_dev, part, &info)) {
+		/* try to boot raw .... */
+		strncpy((char *)&info.type[0], BOOT_PART_TYPE,
+			sizeof(BOOT_PART_TYPE));
+		strncpy((char *)&info.name[0], "Raw", 4);
+		info.start = 0;
+		info.blksz = 0x200;
+		info.size = 2880;
+		printf("error reading partinfo...try to boot raw\n");
+	}
+	if ((strncmp((char *)info.type, BOOT_PART_TYPE,
+	    sizeof(info.type)) != 0) &&
+	    (strncmp((char *)info.type, BOOT_PART_COMP,
+	    sizeof(info.type)) != 0)) {
+		printf("\n** Invalid partition type \"%.32s\""
+			" (expect \"" BOOT_PART_TYPE "\")\n",
+			info.type);
+		return 1;
+	}
+	printf("\nLoading from USB device %d, partition %d: "
+		"Name: %.32s  Type: %.32s\n",
+		dev, part, info.name, info.type);
+
+	debug("First Block: %ld,  # of blocks: %ld, Block Size: %ld\n",
+		info.start, info.size, info.blksz);
+
+	if (stor_dev->block_read(dev, info.start, 1, (ulong *)addr) != 1) {
+		printf("** Read error on %d:%d\n", dev, part);
+		return 1;
+	}
+
+	switch (genimg_get_format((void *)addr)) {
+	case IMAGE_FORMAT_LEGACY:
+//		hdr = (image_header_t *)addr;
+
+//		if (!image_check_hcrc(hdr)) {
+//			puts("\n** Bad Header Checksum **\n");
+			return 1;
+		}
+
+//		image_print_contents(hdr);
+
+//		cnt = image_get_image_size(hdr);
+		break;
+#if defined(CONFIG_FIT)
+	case IMAGE_FORMAT_FIT:
+		fit_hdr = (const void *)addr;
+		puts("Fit image detected...\n");
+
+		cnt = fit_get_size(fit_hdr);
+		break;
+#endif
+	default:
+		puts("** Unknown image type\n");
+		return 1;
+	}
+
+	cnt += info.blksz - 1;
+	cnt /= info.blksz;
+	cnt -= 1;
+
+	if (stor_dev->block_read(dev, info.start+1, cnt,
+		      (ulong *)(addr+info.blksz)) != cnt) {
+		printf("\n** Read error on %d:%d\n", dev, part);
+		return 1;
+	}
+
+#if defined(CONFIG_FIT)
+	/* This cannot be done earlier, we need complete FIT image in RAM
+	 * first
+	 */
+	if (genimg_get_format((void *)addr) == IMAGE_FORMAT_FIT) {
+		if (!fit_check_format(fit_hdr)) {
+			puts("** Bad FIT image format\n");
+			return 1;
+		}
+		fit_print_contents(fit_hdr);
+	}
+#endif
+
+	/* Loading ok, update default load address */
+	load_addr = addr;
+
+	flush_cache(addr, (cnt+1)*info.blksz);
+
+	/* Check if we should attempt an auto-start */
+	if (((ep = getenv("autostart")) != NULL) && (strcmp(ep, "yes") == 0)) {
+		char *local_args[2];
+		extern int do_bootm(cmd_tbl_t *, int, int, char *[]);
+		local_args[0] = argv[0];
+		local_args[1] = NULL;
+		printf("Automatic boot of image at addr 0x%08lX ...\n", addr);
+		rcode = do_bootm(cmdtp, 0, 1, local_args);
+		return rcode;
+	}
+	return 0;
+}
+#endif
+#endif /* CONFIG_USB_STORAGE */
+
+
+/******************************************************************************
+ * usb command intepreter
+ */
+int do_usb(int argc, char **argv)
+{
+
+	int i;
+	struct usb_device *dev = NULL;
+	
+#ifdef CONFIG_USB_STORAGE
+	block_dev_desc_t *stor_dev;
+#endif
+	extern char usb_started;
+
+	if ((strncmp(argv[1], "reset", 5) == 0) ||
+		 (strncmp(argv[1], "start", 5) == 0)) {
+		usb_stop();
+		printf("(Re)start USB...\n");
+#ifdef PCI_XBIOS
+		i = pci_init();
+#else
+		if (usb_init() >= 0)
+			i = 1;
+#endif
+
+#ifdef CONFIG_USB_STORAGE
+		/* try to recognize storage devices immediately */
+		if (i == 1)
+			usb_stor_curr_dev = usb_stor_scan( );
+#endif
+		return 0;
+	}
+	if (strncmp(argv[1], "stop", 4) == 0) {
+#ifdef CONFIG_USB_KEYBOARD
+		if (argc == 2) {
+			if (usb_kbd_deregister() != 0) {
+				printf("USB not stopped: usbkbd still"
+					" using USB\n");
+				return 1;
+			}
+		} else {
+			/* forced stop, switch console in to serial */
+			usb_kbd_deregister();
+		}
+#endif
+		printf("stopping USB..\n");
+		usb_stop();
+		return 0;
+	}
+	if (!usb_started) {
+		printf("USB is stopped. Please issue 'usb start' first.\n");
+		return 1;
+	}
+
+	if (strncmp(argv[1], "tree", 4) == 0) {
+		printf("\nDevice Tree:\n");
+		usb_show_tree(usb_get_dev_index(0));
+		return 0;
+	}
+	if (strncmp(argv[1], "inf", 3) == 0)
+	{
+		int d1;
+		if (argc == 2) 
+		{
+			for (d1 = 0; d1 < USB_MAX_DEVICE; d1++) {
+				dev = usb_get_dev_index(d1);
+				if (dev == NULL)
+					break;
+				usb_display_desc(dev);
+				usb_display_config(dev);
+			}
+			return 0;
+		} else 
+		{
+			int d2;
+			
+			i = strtoul(argv[2], NULL, 16);
+			printf("config for device %d\n", i);
+			for (d2 = 0; d2 < USB_MAX_DEVICE; d2++) {
+				dev = usb_get_dev_index(d2);
+				if (dev == NULL)
+					break;
+				if (dev->devnum == i)
+					break;
+			}
+			if (dev == NULL) {
+				printf("*** NO Device avaiable ***\n");
+				return 0;
+			} else {
+				usb_display_desc(dev);
+				usb_display_config(dev);
+			}
+		}
+		return 0;
+	}
+#ifdef CONFIG_USB_STORAGE
+	if (strncmp(argv[1], "stor", 4) == 0)
+		return usb_stor_info();
+#if 0
+	if (strncmp(argv[1], "part", 4) == 0) {
+		int devno, ok = 0;
+		if (argc == 2) {
+			for (devno = 0; devno < USB_MAX_STOR_DEV; ++devno) {
+				stor_dev = usb_stor_get_dev(devno);
+				if (stor_dev->type != DEV_TYPE_UNKNOWN) {
+					ok++;
+					if (devno)
+						printf("\n");
+					printf("print_part of %x\n", devno);
+					print_part(stor_dev);
+				}
+			}
+		} else {
+			devno = strtoul(argv[2], NULL, 16);
+			stor_dev = usb_stor_get_dev(devno);
+			if (stor_dev->type != DEV_TYPE_UNKNOWN) {
+				ok++;
+				printf("print_part of %x\n", devno);
+				print_part(stor_dev);
+			}
+		}
+		if (!ok) {
+			printf("\nno USB devices available\n");
+			return 1;
+		}
+		return 0;
+	}
+#endif
+	if (strcmp(argv[1], "read") == 0) {
+		if (usb_stor_curr_dev < 0) {
+			printf("no current device selected\n");
+			return 1;
+		}
+		if (argc == 5) {
+			unsigned long addr = strtoul(argv[2], NULL, 16);
+			unsigned long blk  = strtoul(argv[3], NULL, 16);
+			unsigned long cnt  = strtoul(argv[4], NULL, 16);
+			unsigned long n;
+			printf("\nUSB read: device %d block # %ld, count %ld"
+				" ... ", usb_stor_curr_dev, blk, cnt);
+			stor_dev = usb_stor_get_dev(usb_stor_curr_dev);
+			n = stor_dev->block_read(usb_stor_curr_dev, blk, cnt,
+						 (unsigned long *)addr);
+			printf("%ld blocks read: %s\n", n,
+				(n == cnt) ? "OK" : "ERROR");
+			if (n == cnt)
+				return 0;
+			return 1;
+		}
+	}
+	if (strncmp(argv[1], "dev", 3) == 0) {
+		if (argc == 3) {
+			int device = (int)strtoul(argv[2], NULL, 10);
+			printf("\nUSB device %d: ", device);
+			if (device >= USB_MAX_STOR_DEV) {
+				printf("unknown device\n");
+				return 1;
+			}
+			printf("\n    Device %d: ", device);
+			stor_dev = usb_stor_get_dev(device);
+			dev_print(stor_dev);
+			if (stor_dev->type == DEV_TYPE_UNKNOWN)
+				return 1;
+			usb_stor_curr_dev = device;
+			printf("... is now current device\n");
+			return 0;
+		} else {
+			printf("\nUSB device %d: ", usb_stor_curr_dev);
+			stor_dev = usb_stor_get_dev(usb_stor_curr_dev);
+			dev_print(stor_dev);
+			if (stor_dev->type == DEV_TYPE_UNKNOWN)
+				return 1;
+			return 0;
+		}
+		return 0;
+	}
+#endif /* CONFIG_USB_STORAGE */
+//	cmd_usage(cmdtp);
+	return 1;
+}
+#if 0
+#ifdef CONFIG_USB_STORAGE
+U_BOOT_CMD(
+	usb,	5,	1,	do_usb,
+	"USB sub-system",
+	"reset - reset (rescan) USB controller\n"
+	"usb stop [f]  - stop USB [f]=force stop\n"
+	"usb tree  - show USB device tree\n"
+	"usb info [dev] - show available USB devices\n"
+	"usb storage  - show details of USB storage devices\n"
+	"usb dev [dev] - show or set current USB storage device\n"
+	"usb part [dev] - print partition table of one or all USB storage"
+	" devices\n"
+	"usb read addr blk# cnt - read `cnt' blocks starting at block `blk#'\n"
+	"    to memory address `addr'"
+);
+
+
+U_BOOT_CMD(
+	usbboot,	3,	1,	do_usbboot,
+	"boot from USB device",
+	"loadAddr dev:part"
+);
+
+#else
+U_BOOT_CMD(
+	usb,	5,	1,	do_usb,
+	"USB sub-system",
+	"reset - reset (rescan) USB controller\n"
+	"usb  tree  - show USB device tree\n"
+	"usb  info [dev] - show available USB devices"
+);
+#endif
+#endif
diff --git a/FireBee/trunk/usb/store/compile.txt b/FireBee/trunk/usb/store/compile.txt
new file mode 100644
index 0000000..c14b6bd
--- /dev/null
+++ b/FireBee/trunk/usb/store/compile.txt
@@ -0,0 +1,6 @@
+I have used gcc 4.4.3 native version and gcc 4.4.3 cross-compiler version to
+compile these sources.
+There are 4 targets "make ethernat", "make netusbee", "make aranym", "make ohci-pci".
+If you use cross-compiler add "CROSS=yes" to the commands above.
+Before compiling "ohci-pci" target you must "make clean" if you have been compiling the other targets before.
+"make all" compiles the 4 targets.
diff --git a/FireBee/trunk/usb/store/config.h b/FireBee/trunk/usb/store/config.h
new file mode 100644
index 0000000..ce5464f
--- /dev/null
+++ b/FireBee/trunk/usb/store/config.h
@@ -0,0 +1,54 @@
+#ifndef _CONFIG_H
+#define _CONFIG_H
+
+//#define ARCH m68k
+//#define COLDFIRE      /* Besides change one(first) .chip in detxbios.S 68060 or 5200 */
+//#define CONFIG_USB_ISP116X_HCD
+//#define SUPERVISOR
+/* Change .chip in detxbios.S 68060 or 5200 */
+
+/*----- USB -----*/
+//#define CONFIG_LEGACY_USB_INIT_SEQ
+#define CONFIG_USB_STORAGE
+//#define CONFIG_USB_KEYBOARD
+//#define CONFIG_USB_MOUSE
+//#define CONFIG_USB_INTERRUPT_POLLING
+#define CONFIG_USB_ARANYM_HCD
+/*----- ISP116x-HCD ------*/
+#define ISP116X_HCD_USE_UDELAY
+#define ISP116X_HCD_USE_EXTRA_DELAY
+//#define ISP116X_HCD_SEL15kRES
+//#define ISP116X_HCD_OC_ENABLE
+//#define ISP116X_HCD_REMOTE_WAKEUP_ENABLE
+/*----- OHCI-HCI -----*/
+#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	1
+#define CONFIG_USB_OHCI
+//#define PCI_XBIOS	/* Defined in the makefile */
+
+
+/*----- DEBUG -----*/
+/* You should activate global debug, 
+ * #define DEBUG_GLOBAL 1 to turn on 
+ * #define DEBUG_GLOBAL 0 to turn off
+ * After global debug is enable 
+ * you can activate the debug independently 
+ * in each layer where debug is possible
+ */
+
+#define DEBUG_GLOBAL 1
+#if DEBUG_GLOBAL
+/* Define only one of the three debug posibilities below */
+#define DEBUG_TO_FILE 1
+#define DEBUG_TO_ARANYM 0	/* NOTE: No arguments are passed to the printf function */
+#define DEBUG_TO_CONSOLE 0
+
+/* Define which local layer you want on */
+#define DEBUG_HOST_LAYER	0
+#define DEBUG_USB_LAYER		0
+#define DEBUG_HUB_LAYER		0
+#define DEBUG_STORAGE_LAYER	0
+#define DEBUG_XHDI_LAYER	0
+#define DEBUG_BIOS_LAYER	0	/* NOTE: Always to console */
+
+#endif
+#endif /* _CONFIG_H */
diff --git a/FireBee/trunk/usb/store/debug.c b/FireBee/trunk/usb/store/debug.c
new file mode 100644
index 0000000..a2a1a86
--- /dev/null
+++ b/FireBee/trunk/usb/store/debug.c
@@ -0,0 +1,64 @@
+/* 
+ * debug.c
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include "config.h"
+
+#include <stdio.h>
+#include <stdarg.h>
+#include <string.h>
+
+
+#if  DEBUG_TO_FILE
+static FILE *debug_handle = NULL;
+
+
+void
+debug_init(char *file)
+{
+	char filename[20] = "";
+
+	strcpy(filename, file);
+		
+	debug_handle = fopen(filename, "a");
+		
+	if (debug_handle != NULL)
+		setvbuf (debug_handle, NULL, _IONBF, 0);
+}
+
+
+void debug_exit(void)
+{
+	if (debug_handle != NULL && debug_handle != stdout)
+		fclose(debug_handle);
+	debug_handle = NULL;
+}
+
+
+void debug(char *FormatString, ...)
+{
+	va_list arg_ptr;
+
+	va_start(arg_ptr, FormatString);
+	vfprintf(debug_handle, FormatString, arg_ptr);
+	va_end(arg_ptr);
+	fflush(debug_handle);
+	
+}
+#endif
+
+
diff --git a/FireBee/trunk/usb/store/debug.h b/FireBee/trunk/usb/store/debug.h
new file mode 100644
index 0000000..e64b59e
--- /dev/null
+++ b/FireBee/trunk/usb/store/debug.h
@@ -0,0 +1,97 @@
+/*
+ * debug.h
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef _DEBUG_H
+#define _DEBUG_H
+
+#include "config.h"
+#include "host/aranym/nf_ops.h"
+
+void debug_init ( char *file);
+void debug_exit ( void );
+void debug (char *FormatString, ...);
+
+/* You should activate global debug in config.h, uncommenting the #define DEBUG line */
+/* After global debug is enable you can activate them independly in each file */ 
+
+
+#if DEBUG_GLOBAL
+#if DEBUG_TO_FILE
+#define DEBUG(fmt, args...)	debug_init("usb.log"); \
+				debug( "%s: "fmt"\n\r" , __FUNCTION__, ##args); \
+				debug_exit( )
+#endif /* DEBUG_TO_FILE */
+
+#if DEBUG_TO_ARANYM
+#define	DEBUG(fmt, args...)	nf_debug(fmt )
+#endif /* DEBUG_TO_ARANYM */
+
+#if DEBUG_TO_CONSOLE
+#define DEBUG(fmt, args...)	printf("%s: "fmt"\n\r" , __FUNCTION__, ##args)
+#endif /* DEBUG_TO_CONSOLE */
+
+/* This allows control debug messages independenly for different layers */
+#if DEBUG_HOST_LAYER
+#define DEBUG_HOST(fmt, args...)	DEBUG(fmt, ##args)
+#else
+#define DEBUG_HOST(fmt, args...)	{}
+#endif
+#if DEBUG_USB_LAYER
+#define DEBUG_USB(fmt, args...)		DEBUG(fmt, ##args)
+#else
+#define DEBUG_USB(fmt, args...)		{}
+#endif
+#if DEBUG_HUB_LAYER
+#define DEBUG_HUB(fmt, args...)		DEBUG(fmt, ##args)
+#else
+#define DEBUG_HUB(fmt, args...)		{}
+#endif
+#if DEBUG_STORAGE_LAYER
+#define DEBUG_STORAGE(fmt, args...)	DEBUG(fmt, ##args)
+#else
+#define DEBUG_STORAGE(fmt, args...)	{}
+#endif
+#if DEBUG_XHDI_LAYER
+#define DEBUG_XHDI(fmt, args...)	DEBUG(fmt, ##args)
+#else
+#define DEBUG_XHDI(fmt, args...)	{}
+#endif
+
+#else
+#define DEBUG(fmt, args...) 	{}
+#if DEBUG_HOST_LAYER
+#define DEBUG_HOST(fmt, args...)	DEBUG(fmt, ##args)
+#endif
+#define DEBUG(fmt, args...) 	{}
+#if DEBUG_USB_LAYER
+#define DEBUG_USB(fmt, args...)		DEBUG(fmt, ##args)
+#endif
+#if DEBUG_HUB_LAYER
+#define DEBUG_HUB(fmt, args...)		DEBUG(fmt, ##args)
+#endif
+#if DEBUG_STORAGE_LAYER
+#define DEBUG_STORAGE(fmt, args...)	DEBUG(fmt, ##args)
+#endif
+#if DEBUG_XHDI_LAYER
+#define DEBUG_XHDI(fmt, args...)	DEBUG(fmt, ##args)
+#endif
+
+#endif  /* DEBUG_GLOBAL */
+
+
+#endif /* _DEBUG_H */
diff --git a/FireBee/trunk/usb/store/debug2.S b/FireBee/trunk/usb/store/debug2.S
new file mode 100644
index 0000000..0c8dd8a
--- /dev/null
+++ b/FireBee/trunk/usb/store/debug2.S
@@ -0,0 +1,840 @@
+/*  Debug the CT60
+ * 
+ * Didier Mequignon, 2003-2006, e-mail: aniplay@wanadoo.fr
+ *
+ *  This library is free software; you can redistribute it and/or
+ *  modify it under the terms of the GNU Lesser General Public
+ *  License as published by the Free Software Foundation; either
+ *  version 2.1 of the License, or (at your option) any later version.
+ *
+ *  This library is distributed in the hope that it will be useful,
+ *  but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ *  Lesser General Public License for more details.
+ *
+ *  You should have received a copy of the GNU Lesser General Public
+ *  License along with this library; if not, write to the Free Software
+ *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+	.chip 68040
+	.globl	exception
+	
+#ifdef COLDFIRE
+	.globl	null
+	
+#include "fire.h"
+#endif
+
+#include "vars.h"
+
+#define DEBUG
+
+#ifdef DEBUG
+	.global display_string,hex_long,hex_word,hex_byte,display_char,wait_key,_debug
+#endif
+
+	.text
+	
+#ifdef COLDFIRE
+
+null:
+	clr.l 0x380        // not valid
+	move.l SP,0x3C0
+	move.l A6,0x3BC
+	lea 0x384,A6
+	movem.l D0-D7/A0-A5,(A6)
+	clr.l 0x3C8        // USP
+	moveq #-1,D1
+#endif
+
+exception:
+
+	clr.l memvalid
+	lea.l mess1(PC),A0
+	bsr display_string
+#ifdef COLDFIRE
+	ext.l D1
+	addq.l #1,D1
+	move.l D1,D7       // vector number
+#else
+	addq.w #1,D1
+	move.w D1,D7       // vector number
+#endif
+	moveq #0,D0
+	move.w D7,D0
+#ifdef COLDFIRE
+	.chip 68060
+	divu #10,D0
+	.chip 5200
+	move.l D0,D1
+	and.l #7,D0
+	beq.s .ex1
+	or.l #0x30,D0
+	bsr display_char
+.ex1:
+	swap D1
+	move.w D1,D0
+	or.l #0x30,D0
+#else
+	divu #10,D0
+	and.w #7,D0
+	beq.s .ex1
+	or.w #0x30,D0
+	bsr display_char
+.ex1:
+	swap d0
+	or.w #0x30,D0
+#endif
+	bsr display_char
+	moveq #0x3A,D0
+	bsr display_char
+	moveq #0x20,D0
+	bsr display_char
+	lea.l tab_mess_exc(PC),A0
+	move.w D7,D0
+	bsr display_tab
+	moveq #13,D0
+	bsr display_char
+	moveq #10,D0
+	bsr display_char
+#ifdef COLDFIRE
+	tst.w D7
+	beq .ex0
+#endif
+	lea.l mess2(PC),A0 // SR
+	bsr display_string
+#ifdef COLDFIRE
+	move.w save_sr,D0  // SR
+#else
+	move.l 0x3C0,A0    //SSP
+	move.w (A0),D0
+#endif
+	bsr hex_word       // SR
+	lea.l mess3(PC),A0
+	bsr display_string
+#ifdef COLDFIRE
+	move.w save_sr,D2  // SR
+	and.l #0xB71F,D2
+#else
+	move.l 0x3C0,A0    //SSP
+	move.w (A0),D2     // SR
+	and.w #0xB71F,D2
+#endif
+	lea.l tab_status(PC),A1
+	moveq #15,D1
+.ex5:
+		btst.l D1,D2
+		beq.s .ex6
+		moveq #0,D0
+		move.b (A1,D1),D0
+		move.w D0,D3
+#ifdef COLDFIRE
+		and.l #0xF8,D3
+		cmp.l #0x30,D3
+#else
+		and.w #0xF8,D3
+		cmp.w #0x30,D3
+#endif
+		bne.s .ex4
+		move.w D0,-(SP)
+		moveq #0x49,D0 // I
+		bsr display_char
+		move.w (SP)+,D0
+.ex4:
+		bsr display_char
+		moveq #0x20,D0
+		bsr display_char
+.ex6:
+#ifdef COLDFIRE
+	subq.l #1,D1
+	bpl.s .ex5
+.ex0:
+#else
+	dbf D1,.ex5
+#endif
+	lea.l mess4(PC),A0 // PC
+	bsr display_string
+#ifdef COLDFIRE
+	move.l save_pc,D0  // PC
+#else
+	move.l 0x3C0,A0    // SSP
+	move.l 2(A0),D0    // PC
+#endif
+	bsr hex_long
+	lea.l mess10(PC),A0 // Basepage
+	bsr display_string
+	move.l 0x6EE4,D0
+	bsr hex_long
+#ifdef COLDFIRE
+	tst.w D7
+	beq .ex2
+#endif
+	lea.l mess5(PC),A0 // CACR
+	bsr display_string  
+#ifdef COLDFIRE
+	.chip 68060
+	movec.l CACR,D0    // from value stored in the CF68KLIB
+	.chip 5200
+	bsr hex_long
+	cmp.l #2,D7
+	bne.s .ex2
+	lea.l mess6(PC),A0 // address fault
+	bsr display_string
+	move.l address_fault,D0 // from value stored in the CF68KLIB
+	bsr hex_long
+#else /* ATARI - CT60 */
+	movec.l CACR,D0
+	bsr hex_long
+	cmp.w #2,D7
+	beq.s .ex3         // Acces Fault
+	cmp.w #3,D7
+	beq.s .ex3         // Adress Error
+	cmp.w #5,D7
+	beq.s .ex3         // Zero Divide
+	cmp.w #9,D7
+	bne .ex2           // <> Trace
+.ex3:
+	lea.l mess6(PC),A0 // address fault
+	bsr display_string
+	move.l 0x3C0,A0    // SSP
+	move.l 8(A0),D0    // address fault
+	bsr hex_long
+	cmp.w #2,D7
+	bne .ex2           // <> Acces Fault
+	lea.l mess7(PC),A0 // FSLW
+	bsr display_string
+	move.l 0x3C0,A0    // SSP
+	move.l 12(A0),D0   // FSLW
+	bsr hex_long
+	lea.l mess3(PC),A0
+	bsr display_string
+	moveq #13,D0
+	bsr display_char
+	moveq #10,D0
+	bsr display_char
+	move.l 0x3C0,A0  // SSP
+	move.l 12(A0),D2 // FSLW
+	and.l #0x0BFFFFFD,D2
+	lea.l tab_fslw1(PC),A1
+	lea.l tab_fslw2(PC),A2
+	lea.l tab_fslw3(PC),A3
+	moveq #31,D1
+	moveq #0,D3
+.ex13:
+		btst.l D1,D2
+		beq.s .ex14
+		moveq #0,D0
+		move.b (A1,D3),D0
+		bsr display_char
+		moveq #0,D0
+		move.b (A2,D3),D0
+		cmp.b #0x20,D0
+		beq.s .ex12
+		bsr display_char
+		moveq #0,D0
+		move.b (A3,D3),D0
+		cmp.b #0x20,D0
+		beq.s .ex12
+		bsr display_char
+.ex12:
+		moveq #0x20,D0
+		bsr display_char
+.ex14:
+		addq.w #1,D3
+	dbf D1,.ex13
+#endif /* COLDFIRE */
+.ex2:
+	lea.l mess8(PC),A0 // SSP
+	bsr display_string
+	move.l 0x3C0,D0    // SSP
+	bsr hex_long
+	lea.l mess9(PC),A0 // USP
+	bsr display_string
+	move.l 0x3C8,D0    // USP
+	bsr hex_long
+	lea.l 0x384,A1     // registers
+	lea.l 32(A1),A2
+	moveq #7,D1
+.ex8:
+		moveq #13,D0
+		bsr display_char
+		moveq #10,D0
+		bsr display_char
+		moveq #0x44,D0
+		bsr display_char
+		moveq #7,D0
+#ifdef COLDFIRE
+		sub.l D1,D0
+		or.l #0x30,D0
+#else
+		sub.w D1,D0
+		or.w #0x30,D0
+#endif
+		move.w D0,-(SP)
+		bsr display_nb
+		move.l (A1),D0
+		bsr hex_long // data registers
+		moveq #0x20,D0
+		bsr display_char
+		tst.w D1
+		beq.s .ex9
+		moveq #0x41,D0
+		bsr display_char
+		move.w (SP),D0
+		bsr display_nb
+		move.l (A2),D0
+		bsr hex_long // address registers
+		moveq #0x20,D0
+		bsr display_char
+.ex9:		
+		addq.l #2,SP
+		addq.l #4,A1
+		addq.l #4,A2
+#ifdef COLDFIRE
+	subq.l #1,D1
+	bpl.s .ex8
+#else
+	dbf D1,.ex8
+#endif
+	moveq #13,D0
+	bsr display_char
+.loop_wait_key:
+#ifdef COLDFIRE
+#ifdef DEBUG
+		move.w #1,-(SP)          // AUX
+#else
+		move.w #2,-(SP)          // CON
+#endif
+#else
+		move.w #2,-(SP)          // CON
+#endif
+		move.w #2,-(SP)          // Bconin
+		trap #13
+		addq.l #4,SP
+		ext.l D0
+		move.l D0,-(SP)
+		move.l #0x5F504349,D0 
+		lea 0xED0000,A0          // 128 KB
+		cmp.l (A0),D0            // _PCI
+		beq.s .pci_drivers
+		lea 0xEC0000,A0          // 192 KB
+		cmp.l (A0),D0            // _PCI
+		beq.s .pci_drivers
+		lea 0xEB0000,A0          // 256 KB
+		cmp.l (A0),D0            // _PCI
+		beq.s .pci_drivers
+		lea 0xEA0000,A0          // 320 KB
+		cmp.l (A0),D0            // _PCI
+		bne.s .no_pci_drivers
+.pci_drivers:
+		jsr 40(A0)               // drivers PCI in flash, add dbug (68k disassembler)
+		move.l D0,(SP)
+		bne .no_pci_drivers
+		addq.l #4,SP
+		bra.s .loop_wait_key
+.no_pci_drivers:
+		move.l (SP)+,D0
+#ifdef COLDFIRE
+		and.l #0xFF,D0
+		cmp.l #0x6D,D0     // m
+#else
+		cmp.b #0x6D,D0     // m
+#endif
+		beq.s .memory_dump
+#ifdef COLDFIRE
+		cmp.l #0x70,D0     // p
+#else
+		cmp.b #0x70,D0     // p
+#endif
+		beq.s .patch_memory
+#ifdef DEBUG
+#ifdef COLDFIRE
+		cmp.l #0x20,D0
+#else
+		cmp.b #0x20,D0
+#endif	
+		bne .loop_wait_key
+		lea mess14(PC),A0
+		bsr display_string
+#endif
+		rts
+.memory_dump:
+		lea mess11(PC),A0  // memory dump
+		bsr display_string
+		bsr get_hex_value	
+		move.l D0,A0
+		bsr dump
+		bra .loop_wait_key
+.patch_memory:
+		lea mess12(PC),A0  // patch memory
+		bsr display_string
+		bsr get_hex_value
+		move.l D0,A1
+		lea mess13(PC),A0  // value
+		bsr display_string		
+		bsr get_hex_value
+		cmp.l #0x100,D0
+		bcc.s .word_value
+		move.b D0,(A1)
+		lea crlf(PC),A0
+		bsr display_string
+		move.l A1,D0
+		bsr hex_long
+		moveq #0x20,D0
+		bsr display_char
+		move.b (A1),D0
+		bsr hex_byte
+		bra .loop_wait_key
+.word_value:
+		cmp.l #0x10000,D0
+		bcc.s .long_value
+		move.w D0,(A1)
+		lea crlf(PC),A0
+		bsr display_string
+		move.l A1,D0
+		bsr hex_long
+		moveq #0x20,D0
+		bsr display_char
+		move.w (A1),D0
+		bsr hex_word	
+		bra .loop_wait_key
+.long_value:
+		move.l D0,(A1)
+		lea crlf(PC),A0
+		bsr display_string
+		move.l A1,D0
+		bsr hex_long
+		moveq #0x20,D0
+		bsr display_char
+		move.l (A1),D0
+		bsr hex_long
+	bra .loop_wait_key
+	
+display_nb:
+
+	bsr display_char
+	moveq #0x3A,D0
+	bsr display_char
+	moveq #0x24,D0
+	bsr display_char
+	rts
+	
+display_tab:
+
+#ifdef COLDFIRE
+	move.l D1,-(SP)
+#endif
+	move.w D0,-(SP)
+	moveq #0,D0
+.dt1:
+#ifdef COLDFIRE
+		move.b (A0),D1
+		extb.l D1
+		cmp.l #-1,D1
+		beq.s .dt3
+		moveq #0,D1
+		move.w (SP),D1
+		cmp.l D1,D0
+#else
+		cmp.b #-1,(A0)
+		beq.s .dt3
+		cmp.w (SP),D0
+#endif
+		beq.s .dt4
+.dt2:
+		tst.b (A0)+
+		bne.s .dt2
+#ifdef COLDFIRE
+		addq.l #1,D0
+#else
+		addq.w #1,D0
+#endif
+	bra.s .dt1
+.dt4:
+	bsr display_string
+.dt3:
+
+	addq.l #2,SP
+#ifdef COLDFIRE
+	move.l (SP)+,D1
+#endif
+	rts
+		
+hex_long:
+	move.l D0,-(SP)
+	swap D0
+	bsr.s hex_word
+	move.l (SP)+,D0
+hex_word:
+	move.w D0,-(SP)
+#ifdef COLDFIRE
+	lsr.l #8,D0          
+	bsr.s hex_byte     
+	move.w (SP)+,D0
+hex_byte:
+	move.w D0,-(SP)
+	lsr.l #4,D0
+	bsr.s hex_char      
+	move.w (SP)+,D0      
+hex_char:
+	and.l #0xF,D0      
+	or.l #0x30,D0      
+	cmp.l #0x3A,D0     
+	bcs.s display_char  
+	addq.l #7,D0
+	    
+display_char:
+	and.l #0xFF,D0
+#ifdef DEBUG /* warning !!! If serial mouse */
+	move.l D1,-(SP)
+.wait_uart:
+	move.b MCF_UART_USR0,D1
+	and.l  #MCF_UART_USR_TXRDY,D1
+	beq.s .wait_uart
+	move.b D0,MCF_UART_UTB0 // send the character
+	move.l (SP)+,D1
+#else
+	lea -24(SP),SP     
+	movem.l D0-D2/A0-A2,(SP)
+	move.w D0,-(sp)
+	move.w #2,-(SP)
+	move.w #3,-(SP)       // Bconout
+	trap #13
+	addq.l #6,SP
+	movem.l (SP),D0-D2/A0-A2
+	lea 24(SP),SP
+#endif /* DEBUG */
+	rts
+#else  /* ATARI */
+	lsr.w #8,D0          
+	bsr.s hex_byte     
+	move.w (SP)+,D0
+hex_byte:
+	move.w D0,-(SP)
+	lsr.b #4,D0        
+	bsr.s hex_char      
+	move.w (SP)+,D0      
+hex_char:
+	and.b #0xF,D0      
+	or.b #0x30,D0      
+	cmp.b #0x3A,D0     
+	bcs.s display_char  
+	addq.b #7,D0   
+	    
+display_char:
+	and.w #0xFF,D0  
+	movem.l D0-D2/A0-A2,-(SP)
+	move.w D0,-(sp)
+	move.w #2,-(SP)
+	move.w #3,-(SP)       // Bconout
+	trap #13
+	addq.l #6,SP
+	movem.l (SP)+,D0-D2/A0-A2
+	rts
+#endif /* COLDFIRE */
+	
+display_string:
+
+#ifdef COLDFIRE
+	move.l D0,-(SP)
+	move.l A0,-(SP)
+#else
+	movem.l D0/A0,-(SP)
+#endif
+.os2:
+	move.b (A0)+,D0
+	beq.s .os1
+	bsr display_char
+	bra.s .os2
+.os1:
+#ifdef COLDFIRE
+	move.l (SP)+,A0
+	move.l (SP)+,D0
+#else
+	movem.l (SP)+,D0/A0
+#endif
+	rts
+	
+get_hex_value:
+
+#ifdef COLDFIRE
+	lea -56(SP),SP
+	movem.l D1-A5,(SP)
+	link A6,#-8
+	moveq #0,D7
+.loop_get_value:
+#ifdef DEBUG
+		move.w #1,-(SP)          // AUX
+#else
+		move.w #2,-(SP)          // CON
+#endif
+		move.w #2,-(SP)          // Bconin
+		trap #13
+		addq.l #4,SP
+		and.l #0xFF,D0
+		cmp.l #13,D0
+		beq.s .conv_get_value
+		cmp.l #8,D0
+		bne.s .not_backspace
+		tst.w D7
+		ble.s .loop_get_value
+		bsr display_char
+		subq.l #1,D7
+		bra.s .loop_get_value
+.not_backspace:
+		cmp.l #0x30,D0
+		bcs.s .loop_get_value
+		cmp.l #0x39,D0
+		bls.s .number_value
+		cmp.l #0x41,D0
+		bcs.s .loop_get_value
+		cmp.l #0x46,D0
+		bls.s .letter_value
+		cmp.l #0x61,D0
+		bcs.s .loop_get_value
+		cmp.l #0x66,D0
+		bhi.s .loop_get_value
+.letter_value:
+		bsr display_char
+		and.l #0x0F,D0
+		add.l #9,D0
+		bra.s .store_value		
+.number_value:
+		bsr display_char
+		and.l #0x0F,D0
+.store_value:
+		move.b D0,-8(A6,D7)
+		addq.l #1,D7
+	cmp.l #8,D7
+	bcs .loop_get_value
+.conv_get_value:
+	moveq #0,D0
+	subq.l #1,D7
+	bmi.s .end_get_value
+	moveq #0,D6
+.loop_value:
+		asl.l #4,D0
+		moveq #0,D1
+		move.b -8(A6,D6),D1 
+		or.l D1,D0
+		addq.l #1,D6
+	subq.l #1,D7
+	bpl.s  .loop_value		
+.end_get_value:	
+	tst.l D0
+	unlk A6
+	movem.l (SP),D1-A5
+	lea 56(SP),SP
+#else /* ATARI */
+	movem.l D1-A5,-(SP)
+	link A6,#-8
+	moveq #0,D7
+.loop_get_value:
+		move.w #2,-(SP)          // CON
+		move.w #2,-(SP)          // Bconin
+		trap #13
+		addq.l #4,SP
+		cmp.b #13,D0
+		beq.s .conv_get_value
+		cmp.b #8,D0
+		bne.s .not_backspace
+		tst.w D7
+		ble.s .loop_get_value
+		bsr display_char
+		subq.w #1,D7
+		bra.s .loop_get_value
+.not_backspace:
+		cmp.b #0x30,D0
+		bcs.s .loop_get_value
+		cmp.b #0x39,D0
+		bls.s .number_value
+		cmp.b #0x41,D0
+		bcs.s .loop_get_value
+		cmp.b #0x46,D0
+		bls.s .letter_value
+		cmp.b #0x61,D0
+		bcs.s .loop_get_value
+		cmp.b #0x66,D0
+		bhi.s .loop_get_value
+.letter_value:
+		bsr display_char
+		and.b #0x0F,D0
+		add.b #9,D0
+		bra.s .store_value		
+.number_value:
+		bsr display_char
+		and.b #0x0F,D0
+.store_value:
+		move.b D0,-8(A6,D7)
+		addq.w #1,D7
+	cmp.w #8,D7
+	bcs.s .loop_get_value
+.conv_get_value:
+	moveq #0,D0
+	subq.w #1,D7
+	bmi.s .end_get_value
+	moveq #0,D6
+.loop_value:
+		asl.l #4,D0
+		or.b -8(A6,D6),D0
+		addq.w #1,D6
+	dbf D7,.loop_value		
+.end_get_value:	
+	tst.l D0
+	unlk A6
+	movem.l (SP)+,D1-A5
+#endif /* COLDFIRE */
+	rts
+	
+dump:
+
+#ifdef COLDFIRE
+	lea -20(SP),SP
+	movem.l D0-D2/A0-A1,(SP)
+#else
+	movem.l D0-D2/A0-A1,-(SP)
+#endif
+	move.l A0,A1
+	moveq #3,D1
+.loop_dump1:
+		lea crlf(PC),A0
+		bsr display_string
+		move.l A1,D0
+		bsr hex_long
+		moveq #0x20,D0
+		bsr display_char		
+		moveq #15,D2
+.loop_dump2:
+			move.b (A1)+,D0
+			bsr hex_byte
+			moveq #0x20,D0
+			bsr display_char
+#ifdef COLDFIRE
+		subq.l #1,D2
+		bpl.s .loop_dump2
+#else
+		dbf D2,.loop_dump2
+#endif
+		lea -16(A1),A1
+		moveq #15,D2
+.loop_dump3:
+			move.b (A1)+,D0
+#ifdef COLDFIRE
+			and.l #0xFF,D0
+			cmp.l #0x20,D0
+			bcs.s .dump_bad_char
+			cmp.l #0x7F,D0
+#else
+			cmp.b #0x20,D0
+			bcs.s .dump_bad_char
+			cmp.b #0x7F,D0
+#endif
+			bcs.s .dump_ok
+.dump_bad_char:
+			moveq #0x2E,D0
+.dump_ok:
+			bsr display_char
+#ifdef COLDFIRE
+		subq.l #1,D2
+		bpl.s .loop_dump3
+	subq.l #1,D1
+	bpl.s .loop_dump1
+	movem.l (SP),D0-D2/A0-A1
+	lea 20(SP),SP
+#else
+		dbf D2,.loop_dump3
+	dbf D1,.loop_dump1
+	movem.l (SP)+,D0-D2/A0-A1
+#endif
+	rts
+	
+crlf:	.byte 13,10,0
+mess1:	.byte 13,10
+	.asciz "EXCEPTION PROCESSING "
+mess2:	.byte 13,10
+	.asciz "Status Register (SR): $"
+mess3:	.asciz ", bits to 1: "
+mess4:	.byte 13,10
+	.asciz "Program Counter (PC): $"
+mess5:	.byte 13,10
+	.asciz "Cache Register (CACR): $"
+mess6:	.byte 13,10
+	.asciz "Address Fault: $"	
+mess7:	.byte 13,10
+	.asciz "Fault Status Word (FSLW): "
+mess8:	.byte 13,10
+	.asciz "Supervisor Stack (SSP): $"
+mess9:	.byte 13,10
+	.asciz "User Stack (USP): $"
+mess10:	.byte 13,10
+	.asciz "Basepage: $"
+mess11:	.byte 13,10	
+	.asciz "Memory dump (hex) ? "
+mess12:	.byte 13,10	
+	.asciz "Patch memory (hex) ? "
+mess13:	.byte 13,10	
+	.asciz "Value (hex) ? "
+mess14:	.byte 13,10	
+	.ascii "Pterm"
+	.byte 13,10,0
+ 
+tab_mess_exc:
+#ifdef COLDFIRE
+	.asciz "Null (jump or call)"
+#else
+	.byte 0
+#endif
+	.byte 0
+	.asciz "Access Fault"
+	.asciz "Address Error"
+	.asciz "Illegal Instruction"
+	.asciz "Integer Zero Divide"
+	.byte 0
+	.byte 0
+	.asciz "Privilege Violation"
+	.asciz "Trace"
+	.asciz "Line A"
+	.asciz "Line F"
+	.asciz "Emulator Interrupt"
+	.byte 0
+	.asciz "Format Error"
+	.asciz "Uninitialised Interrupt"
+	.byte 0
+	.byte 0
+	.byte 0
+	.byte 0
+	.byte 0
+	.byte 0
+	.byte 0
+	.byte 0
+	.asciz "Spurious Interrupt"
+	.asciz "Interrupt level 1"
+	.asciz "Interrupt level 2" 
+	.asciz "Interrupt level 3" 
+	.asciz "Interrupt level 4"
+	.asciz "Interrupt level 5" 
+	.asciz "Interrupt level 6"
+	.asciz "Interrupt level 7"
+	.asciz "Trap #0"
+	.asciz "Trap #1"
+	.asciz "Trap #2"
+	.asciz "Trap #3"
+	.asciz "Trap #4"
+	.asciz "Trap #5"
+	.asciz "Trap #6"
+	.asciz "Trap #7"
+	.asciz "Trap #8"
+	.asciz "Trap #9"
+	.asciz "Trap #10"
+	.asciz "Trap #11"
+	.asciz "Trap #12"
+	.asciz "Trap #13"
+	.asciz "Trap #14"
+	.asciz "Trap #15"
+	.byte -1
+
+tab_status:	.ascii "CVZNX   012 MS T"
+
+tab_fslw1:	.ascii "    M LRWSSTTTTTIPSPPIPSWTRWTB S"
+tab_fslw2:	.ascii "    A K  ZZTTMMMOBBTTLFPPWEETP S"
+tab_fslw3:	.ascii "         1010210 EEAB    E  RE E"
diff --git a/FireBee/trunk/usb/store/host/aranym/aranym-hcd.c b/FireBee/trunk/usb/store/host/aranym/aranym-hcd.c
new file mode 100644
index 0000000..fe3dbb9
--- /dev/null
+++ b/FireBee/trunk/usb/store/host/aranym/aranym-hcd.c
@@ -0,0 +1,150 @@
+/*
+	NatFeat USB host chip emulator
+
+	ARAnyM (C) 2010 David Gálvez
+
+	This program is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	This program is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with this program; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+/*--- Include ---*/
+
+#include <stdlib.h>
+#include <string.h>
+
+#include <mint/cookie.h>
+#include <mint/osbind.h>
+
+#include "nf_ops.h"
+#include "usbhost_nfapi.h"
+#include "../../config.h"
+#include "../../asm-m68k/io.h"
+#include "../../usb.h"
+#include "../../debug.h"
+
+/*--- Defines ---*/
+
+#ifndef EINVFN
+#define EINVFN	-32
+#endif
+
+#ifndef DEV_CONSOLE
+#define DEV_CONSOLE	2
+#endif
+
+#define DRIVER_NAME	"ARAnyM USB host chip emulator"
+#define VERSION	"v0.1"
+
+
+/*--- Functions prototypes ---*/
+
+static void press_any_key(void);
+
+
+/*--- Local variables ---*/
+
+static struct nf_ops *nfOps;
+static unsigned long nfUsbHostId;
+
+
+/*--- Functions ---*/
+
+
+static void press_any_key(void)
+{
+
+	(void) Cconws("- Press any key to continue -\r\n");
+	while (Bconstat(DEV_CONSOLE) == 0) { };
+}
+
+
+/* --- Transfer functions -------------------------------------------------- */
+
+int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+		   int len, int interval)
+{
+	int r;
+
+	r = nfOps->call(USBHOST(USBHOST_SUBMIT_INT_MSG), dev, pipe, buffer, len, interval);
+
+	return 0;
+}
+
+int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+		       int len, struct devrequest *setup)
+{
+	int r;
+
+	r = nfOps->call(USBHOST(USBHOST_SUBMIT_CONTROL_MSG), dev, pipe, buffer, len, setup);
+
+	return r;
+}
+
+int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+		    int len)
+{
+	int r;
+
+	r = nfOps->call(USBHOST(USBHOST_SUBMIT_BULK_MSG), dev, pipe, buffer, len);
+
+	return 0;
+}
+
+/* --- Init functions ------------------------------------------------------ */
+
+int usb_lowlevel_init(void)
+{
+	int r;
+
+	(void) Cconws(
+		"\033p " DRIVER_NAME " " VERSION " \033q\r\n"
+		"Copyright (c) ARAnyM Development Team, " __DATE__ "\r\n"
+	);
+
+	nfOps = nf_init();
+	if (!nfOps) {
+		(void) Cconws("__NF cookie not present on this system\r\n");
+		press_any_key();
+		return 0;
+	}
+	
+	nfUsbHostId=nfOps->get_id("USBHOST");
+	if (nfUsbHostId == 0) {
+		(void) Cconws("NF USBHOST functions not present on this system\r\n");
+		press_any_key();
+	}
+
+	/* List present devices */
+
+	r = nfOps->call(USBHOST(USBHOST_LOWLEVEL_INIT));
+
+	if (!r) 
+		(void) Cconws(" USB Init \r\n");
+	else
+		(void) Cconws(" Couldn't init aranym host chip emulator \r\n");
+
+	return 0;
+
+}
+
+int usb_lowlevel_stop(void)
+{
+	int r;
+
+	r = nfOps->call(USBHOST(USBHOST_LOWLEVEL_STOP));
+
+	return 0;
+
+}
+
diff --git a/FireBee/trunk/usb/store/host/aranym/natfeat.c b/FireBee/trunk/usb/store/host/aranym/natfeat.c
new file mode 100644
index 0000000..93edd30
--- /dev/null
+++ b/FireBee/trunk/usb/store/host/aranym/natfeat.c
@@ -0,0 +1,118 @@
+/*
+ * ARAnyM native features interface.
+ * (c) 2005-2008 ARAnyM development team
+ *
+ * In 2006 updated with FreeMiNT headers and code.
+ * In 2008 converted from "__NF" cookie to direct usage of NF instructions
+ *
+ **/
+
+/*
+ * Copied from FreeMiNT source tree where Native Features were added recently
+ * 
+ * Copyright 2003 Frank Naumann <fnaumann@freemint.de>
+ * All rights reserved.
+ * 
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ * 
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ * 
+ * 
+ * Author: Frank Naumann <fnaumann@freemint.de>
+ * Started: 2003-12-13
+ * 
+ */
+
+# include <compiler.h>
+# include <mint/osbind.h>
+# include "nf_ops.h"
+
+
+#define ARANYM 1
+# ifdef ARANYM
+
+
+static unsigned long nf_get_id_instr = 0x73004e75UL;
+static unsigned long nf_call_instr = 0x73014e75UL;
+
+static struct nf_ops _nf_ops = { (void*)&nf_get_id_instr, (void*)&nf_call_instr }; 
+static struct nf_ops *nf_ops = 0UL; 
+
+extern int detect_native_features(void);
+
+struct nf_ops *
+nf_init(void)
+{
+	if (Supexec(detect_native_features))
+	{
+		nf_ops = &_nf_ops;
+		return nf_ops;
+	}
+	
+	return 0UL;
+}
+
+
+const char *
+nf_name(void)
+{
+	static char buf[64] = "Unknown emulator";
+	
+	if (nf_ops)
+	{
+		static int done = 0;
+		
+		if (!done)
+		{
+			long nfid_name = nf_ops->get_id("NF_NAME");
+			
+			if (nfid_name)
+				nf_ops->call(nfid_name, buf, sizeof(buf));
+			
+			done = 1;
+		}
+	}
+        
+	return buf;
+}
+
+int
+nf_debug(const char *msg)
+{
+	if (nf_ops)
+	{
+		long nfid_stderr = nf_ops->get_id("NF_STDERR");
+		
+		if (nfid_stderr)
+		{
+			nf_ops->call(nfid_stderr, msg);
+			return 1;
+		}
+	}
+	
+	return 0;
+}
+
+void
+nf_shutdown(void)
+{
+	if (nf_ops)
+	{
+		long shutdown_id = nf_ops->get_id("NF_SHUTDOWN");
+		
+		if (shutdown_id)
+        		nf_ops->call(shutdown_id);
+	}
+}
+
+# endif
diff --git a/FireBee/trunk/usb/store/host/aranym/natfeat_asm.S b/FireBee/trunk/usb/store/host/aranym/natfeat_asm.S
new file mode 100644
index 0000000..e1b75b3
--- /dev/null
+++ b/FireBee/trunk/usb/store/host/aranym/natfeat_asm.S
@@ -0,0 +1,76 @@
+/*
+ * ARAnyM native features interface.
+ * (c) 2005-2008 ARAnyM development team
+ *
+ * In 2006 updated with FreeMiNT headers and code.
+ * In 2008 converted from "__NF" cookie to direct usage of NF instructions
+ *
+ **/
+
+/*
+ * Copied from FreeMiNT source tree where Native Features were added recently
+ *
+ * Copyright 2003 Frank Naumann <fnaumann@freemint.de>
+ * All rights reserved.
+ * 
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ * 
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ * 
+ * 
+ * Author: Frank Naumann <fnaumann@freemint.de>
+ * Started: 2003-12-13
+ * 
+ * please send suggestions, patches or bug reports to me or
+ * the MiNT mailing list
+ * 
+ */
+
+#define ARANYM 1
+# ifdef ARANYM
+
+	.text
+
+	.globl	_detect_native_features
+
+/* 
+ * NatFeats test (routine retuns TRUE/FALSE (1/0) in D0)
+ */
+_detect_native_features:
+
+	clr.l	d0			// assume no NatFeats available
+	move.l	sp,a1			// save the ssp
+	move.l	(0x0010).w,a0		// illegal instruction vector
+	move.l	#fail_natfeat,(0x0010).w
+
+	nop				// flush pipelines (for 68040+)
+
+	pea	(nf_version_name).w(pc)
+	subq.l	#4,sp
+	dc.w	0x7300			// Jump to NATFEAT_ID
+	tst.l	d0
+	beq.s	fail_natfeat
+	moveq	#1,d0			// NatFeats detected
+
+fail_natfeat:
+	move.l	a1,sp
+	move.l	a0,(0x0010).w
+
+	nop				// flush pipelines (for 68040+)
+
+	rts
+
+nf_version_name:
+	.ascii	"NF_VERSION\0"
+
+# endif
diff --git a/FireBee/trunk/usb/store/host/aranym/nf_ops.h b/FireBee/trunk/usb/store/host/aranym/nf_ops.h
new file mode 100644
index 0000000..b8d1e79
--- /dev/null
+++ b/FireBee/trunk/usb/store/host/aranym/nf_ops.h
@@ -0,0 +1,63 @@
+/*
+ * $Id: nf_ops.h,v 1.2 2006-01-31 16:21:22 standa Exp $
+ * 
+ * ARAnyM Native Features suite.
+ *
+ * This file was taken from FreeMiNT.
+ * 
+ * Copyright 2003 Frank Naumann <fnaumann@freemint.de>
+ * All rights reserved.
+ * 
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ * 
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ * 
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ * 
+ * 
+ * Author: Frank Naumann <fnaumann@freemint.de>
+ * Started: 2003-12-14
+ * 
+ * Please send suggestions, patches or bug reports to me or
+ * the MiNT mailing list.
+ * 
+ */
+
+# ifndef _m68k_nf_ops_h
+# define _m68k_nf_ops_h
+
+#include <compiler.h>	/* for __CDECL */
+
+
+struct nf_ops
+{
+	long __CDECL (*get_id)(const char *);
+	long __CDECL (*call)(long id, ...);
+	long res[3];
+};
+
+
+/**
+ * Use this function to intialize Native Features.
+ *
+ * @return the pointer to 'struct nf_ops' or NULL when
+ *         not available.
+ **/
+struct nf_ops *nf_init(void);
+
+
+/* basic set native feature functions */
+const char *nf_name(void);
+int  nf_debug(const char *msg);
+void nf_shutdown(void);
+
+
+# endif /* _m68k_nf_ops_h */
diff --git a/FireBee/trunk/usb/store/host/aranym/usbhost_nfapi.h b/FireBee/trunk/usb/store/host/aranym/usbhost_nfapi.h
new file mode 100644
index 0000000..e8ffa2e
--- /dev/null
+++ b/FireBee/trunk/usb/store/host/aranym/usbhost_nfapi.h
@@ -0,0 +1,40 @@
+/*
+	NatFeat USB Host chip emulator
+
+	ARAnyM (C) 2010 David Gálvez
+
+	This program is free software; you can redistribute it and/or modify
+	it under the terms of the GNU General Public License as published by
+	the Free Software Foundation; either version 2 of the License, or
+	(at your option) any later version.
+
+	This program is distributed in the hope that it will be useful,
+	but WITHOUT ANY WARRANTY; without even the implied warranty of
+	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+	GNU General Public License for more details.
+
+	You should have received a copy of the GNU General Public License
+	along with this program; if not, write to the Free Software
+	Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+*/
+
+#ifndef _USBHOST_NFAPI_H
+#define _USBHOST_NFAPI_H
+
+/* if you change anything in the enum {} below you have to increase 
+   this ARAUSBHOST_NFAPI_VERSION!
+*/
+#define ARAUSBHOST_NFAPI_VERSION	0x00000000
+
+enum {
+	GET_VERSION = 0,	/* no parameters, return NFAPI_VERSION in d0 */
+	USBHOST_LOWLEVEL_INIT,
+	USBHOST_LOWLEVEL_STOP,
+	USBHOST_SUBMIT_CONTROL_MSG,
+	USBHOST_SUBMIT_INT_MSG,
+	USBHOST_SUBMIT_BULK_MSG
+};
+
+#define USBHOST(a)	(nfUsbHostId + a)
+
+#endif /* _USBHOST_NFAPI_H */
diff --git a/FireBee/trunk/usb/store/host/ethernat/isp116x-hcd.c b/FireBee/trunk/usb/store/host/ethernat/isp116x-hcd.c
new file mode 100644
index 0000000..fbfa611
--- /dev/null
+++ b/FireBee/trunk/usb/store/host/ethernat/isp116x-hcd.c
@@ -0,0 +1,1583 @@
+/*
+ * Modified for Atari-EtherNat by David Gálvez 2010
+ *
+ * ISP116x HCD (Host Controller Driver) for u-boot.
+ *
+ * Copyright (C) 2006-2007 Rodolfo Giometti <giometti@linux.it>
+ * Copyright (C) 2006-2007 Eurotech S.p.A. <info@eurotech.it>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ *
+ * Derived in part from the SL811 HCD driver "u-boot/drivers/usb/sl811_usb.c"
+ * (original copyright message follows):
+ *
+ *    (C) Copyright 2004
+ *    Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ *    This code is based on linux driver for sl811hs chip, source at
+ *    drivers/usb/host/sl811.c:
+ *
+ *    SL811 Host Controller Interface driver for USB.
+ *
+ *    Copyright (c) 2003/06, Courage Co., Ltd.
+ *
+ *    Based on:
+ *         1.uhci.c by Linus Torvalds, Johannes Erdfelt, Randy Dunlap,
+ *           Georg Acher, Deti Fliegl, Thomas Sailer, Roman Weissgaerber,
+ *           Adam Richter, Gregory P. Smith;
+ *         2.Original SL811 driver (hc_sl811.o) by Pei Liu <pbl@cypress.com>
+ *         3.Rewrited as sl811.o by Yin Aihua <yinah:couragetech.com.cn>
+ *
+ *    [[GNU/GPL disclaimer]]
+ *
+ * and in part from AU1x00 OHCI HCD driver "u-boot/cpu/mips/au1x00_usb_ohci.c"
+ * (original copyright message follows):
+ *
+ *    URB OHCI HCD (Host Controller Driver) for USB on the AU1x00.
+ *
+ *    (C) Copyright 2003
+ *    Gary Jennejohn, DENX Software Engineering <garyj@denx.de>
+ *
+ *    [[GNU/GPL disclaimer]]
+ *
+ *    Note: Part of this code has been derived from linux
+ */
+#include "../../config.h"
+#include "../../asm-m68k/io.h"
+#include "../../usb.h"
+#include "../../debug.h"
+
+void udelay(unsigned long usec);
+
+//extern void boot_printf(const char *fmt, ...);
+
+
+/*
+ * ISP116x chips require certain delays between accesses to its
+ * registers. The following timing options exist.
+ *
+ * 1. Configure your memory controller (the best)
+ * 2. Use ndelay (easiest, poorest). For that, enable the following macro.
+ *
+ * Value is in microseconds.
+ */
+#ifdef ISP116X_HCD_USE_UDELAY
+#define UDELAY		1
+#endif
+
+/*
+ * On some (slowly?) machines an extra delay after data packing into
+ * controller's FIFOs is required, * otherwise you may get the following
+ * error:
+ *
+ *   uboot> usb start
+ *   (Re)start USB...
+ *   USB:   scanning bus for devices... isp116x: isp116x_submit_job: CTL:TIMEOUT
+ *   isp116x: isp116x_submit_job: ****** FIFO not ready! ******
+ *
+ *         USB device not responding, giving up (status=4)
+ *         isp116x: isp116x_submit_job: ****** FIFO not empty! ******
+ *         isp116x: isp116x_submit_job: ****** FIFO not empty! ******
+ *         isp116x: isp116x_submit_job: ****** FIFO not empty! ******
+ *         3 USB Device(s) found
+ *                scanning bus for storage devices... 0 Storage Device(s) found
+ *
+ * Value is in milliseconds.
+ */
+#ifdef ISP116X_HCD_USE_EXTRA_DELAY
+#define EXTRA_DELAY	2
+#endif
+
+/*
+ * Enable the following defines if you wish enable extra debugging messages.
+ * Normal debug messages controlled from config.h.
+ */
+
+//#define TRACE			/* enable tracing code */
+//#define VERBOSE		/* verbose debugging messages */
+
+#include "isp116x.h"
+
+#define DRIVER_VERSION	"08 Jan 2007"
+static const char hcd_name[] = "isp116x-hcd";
+
+struct isp116x isp116x_dev;
+struct isp116x_platform_data isp116x_board;
+static int got_rhsc;		/* root hub status change */
+struct usb_device *devgone;	/* device which was disconnected */
+static int rh_devnum;		/* address of Root Hub endpoint */
+
+/* ------------------------------------------------------------------------- */
+
+#define ALIGN(x,a)	(((x)+(a)-1UL)&~((a)-1UL))
+#define min1_t(type,x,y)	\
+	({ type __x = (x); type __y = (y); __x < __y ? __x : __y; })
+
+/* Galvez: added to avoid shadow warnings */
+#define min2_t(type,x,y)	\
+	({ type __a = (x); type __b = (y); __a < __b ? __a : __b; })
+
+/* ------------------------------------------------------------------------- */
+
+
+static int isp116x_reset(struct isp116x *isp116x);
+
+/* --- Debugging functions ------------------------------------------------- */
+
+#define isp116x_show_reg(d, r) {				\
+	if ((r) < 0x20) {					\
+		DEBUG_HOST("%-12s[%02x]: %08x", #r,			\
+			r, isp116x_read_reg32(d, r));		\
+	} else {						\
+		DEBUG_HOST("%-12s[%02x]:     %04x", #r,		\
+			r, isp116x_read_reg16(d, r));		\
+	}							\
+}
+
+#define isp116x_show_regs(d) {					\
+	isp116x_show_reg(d, HCREVISION);			\
+	isp116x_show_reg(d, HCCONTROL);				\
+	isp116x_show_reg(d, HCCMDSTAT);				\
+	isp116x_show_reg(d, HCINTSTAT);				\
+	isp116x_show_reg(d, HCINTENB);				\
+	isp116x_show_reg(d, HCFMINTVL);				\
+	isp116x_show_reg(d, HCFMREM);				\
+	isp116x_show_reg(d, HCFMNUM);				\
+	isp116x_show_reg(d, HCLSTHRESH);			\
+	isp116x_show_reg(d, HCRHDESCA);				\
+	isp116x_show_reg(d, HCRHDESCB);				\
+	isp116x_show_reg(d, HCRHSTATUS);			\
+	isp116x_show_reg(d, HCRHPORT1);				\
+	isp116x_show_reg(d, HCRHPORT2);				\
+	isp116x_show_reg(d, HCHWCFG);				\
+	isp116x_show_reg(d, HCDMACFG);				\
+	isp116x_show_reg(d, HCXFERCTR);				\
+	isp116x_show_reg(d, HCuPINT);				\
+	isp116x_show_reg(d, HCuPINTENB);			\
+	isp116x_show_reg(d, HCCHIPID);				\
+	isp116x_show_reg(d, HCSCRATCH);				\
+	isp116x_show_reg(d, HCITLBUFLEN);			\
+	isp116x_show_reg(d, HCATLBUFLEN);			\
+	isp116x_show_reg(d, HCBUFSTAT);				\
+	isp116x_show_reg(d, HCRDITL0LEN);			\
+	isp116x_show_reg(d, HCRDITL1LEN);			\
+}
+
+#if defined(TRACE)
+
+static int isp116x_get_current_frame_number(struct usb_device *usb_dev)
+{
+	struct isp116x *isp116x = &isp116x_dev;
+
+	return isp116x_read_reg32(isp116x, HCFMNUM);
+}
+
+static void dump_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+		     int len, char *str)
+{
+#if defined(VERBOSE)
+	int i;
+#endif
+	DEBUG_HOST("%s URB:[%4x] dev:%2ld,ep:%2ld-%c,type:%s,len:%d stat:%#lx",
+	    str,
+	    isp116x_get_current_frame_number(dev),
+	    usb_pipedevice(pipe),
+	    usb_pipeendpoint(pipe),
+	    usb_pipeout(pipe) ? 'O' : 'I',
+	    usb_pipetype(pipe) < 2 ?
+	    (usb_pipeint(pipe) ?
+	     "INTR" : "ISOC") :
+	    (usb_pipecontrol(pipe) ? "CTRL" : "BULK"), len, dev->status);
+#if defined(VERBOSE)
+	debug_init("usb.log");
+	if (len > 0 && buffer) {
+		debug(__FILE__ ": data(%d):", len);
+		for (i = 0; i < 16 && i < len; i++)
+			debug(" %02x", ((__u8 *) buffer)[i]);
+		debug("%s\r\n", i < len ? "..." : "");
+	}
+	debug_exit();
+#endif
+}
+
+#define PTD_DIR_STR(ptd)  ({char __c;		\
+	switch(PTD_GET_DIR(ptd)){		\
+	case 0:  __c = 's'; break;		\
+	case 1:  __c = 'o'; break;		\
+	default: __c = 'i'; break;		\
+	}; __c;})
+
+/*
+  Dump PTD info. The code documents the format
+  perfectly, right :)
+*/
+static inline void dump_ptd(struct ptd *ptd)
+{
+#if defined(VERBOSE)
+	int k;
+#endif
+
+	DEBUG_HOST("PTD(ext) : cc:%x %d%c%d %d,%d,%d t:%x %x%x%x",
+	    PTD_GET_CC(ptd),
+	    PTD_GET_FA(ptd), PTD_DIR_STR(ptd), PTD_GET_EP(ptd),
+	    PTD_GET_COUNT(ptd), PTD_GET_LEN(ptd), PTD_GET_MPS(ptd),
+	    PTD_GET_TOGGLE(ptd),
+	    PTD_GET_ACTIVE(ptd), PTD_GET_SPD(ptd), PTD_GET_LAST(ptd));
+#if defined(VERBOSE)
+	debug_init("usb.log");
+	debug("isp116x: %s: PTD(byte): ", __FUNCTION__);
+	for (k = 0; k < sizeof(struct ptd); ++k) {
+		debug("%02x ", ((u8 *) ptd)[k]);
+	}
+	debug("\n\r");
+	debug_exit();
+#endif
+}
+
+static inline void dump_ptd_data(struct ptd *ptd, u8 * buf, int type)
+{
+#if defined(VERBOSE)
+	int k;
+	
+	debug_init("usb.log");
+	if (type == 0 /* 0ut data */ ) {
+		debug("isp116x: %s: out data: ", __FUNCTION__);
+		for (k = 0; k < PTD_GET_LEN(ptd); ++k) {
+			debug("%02x ", ((u8 *) buf)[k]);
+		}
+		debug("\n\r");
+	}
+	if (type == 1 /* 1n data */ ) {
+		debug("isp116x: %s: in data: ", __FUNCTION__);
+		for (k = 0; k < PTD_GET_COUNT(ptd); ++k) {
+			debug("%02x ", ((u8 *) buf)[k]);
+		}
+		debug("\n\r");
+	}
+	
+	debug_exit();
+	
+	if (PTD_GET_LAST(ptd)) {
+		DEBUG_HOST("--- last PTD ---");
+	}
+#endif
+}
+
+#else
+
+#define dump_msg(dev, pipe, buffer, len, str)			do { } while (0)
+#define dump_pkt(dev, pipe, buffer, len, setup, str, small)	do {} while (0)
+
+#define dump_ptd(ptd)			do {} while (0)
+#define dump_ptd_data(ptd, buf, type)	do {} while (0)
+
+#endif
+
+/* --- Virtual Root Hub ---------------------------------------------------- */
+
+/* Device descriptor */
+static __u8 root_hub_dev_des[] = {
+	0x12,			/*  __u8  bLength; */
+	0x01,			/*  __u8  bDescriptorType; Device */
+	0x10,			/*  __u16 bcdUSB; v1.1 */
+	0x01,
+	0x09,			/*  __u8  bDeviceClass; HUB_CLASSCODE */
+	0x00,			/*  __u8  bDeviceSubClass; */
+	0x00,			/*  __u8  bDeviceProtocol; */
+	0x08,			/*  __u8  bMaxPacketSize0; 8 Bytes */
+	0x00,			/*  __u16 idVendor; */
+	0x00,
+	0x00,			/*  __u16 idProduct; */
+	0x00,
+	0x00,			/*  __u16 bcdDevice; */
+	0x00,
+	0x00,			/*  __u8  iManufacturer; */
+	0x01,			/*  __u8  iProduct; */
+	0x00,			/*  __u8  iSerialNumber; */
+	0x01			/*  __u8  bNumConfigurations; */
+};
+
+/* Configuration descriptor */
+static __u8 root_hub_config_des[] = {
+	0x09,			/*  __u8  bLength; */
+	0x02,			/*  __u8  bDescriptorType; Configuration */
+	0x19,			/*  __u16 wTotalLength; */
+	0x00,
+	0x01,			/*  __u8  bNumInterfaces; */
+	0x01,			/*  __u8  bConfigurationValue; */
+	0x00,			/*  __u8  iConfiguration; */
+	0x40,			/*  __u8  bmAttributes;
+				   Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
+	0x00,			/*  __u8  MaxPower; */
+
+	/* interface */
+	0x09,			/*  __u8  if_bLength; */
+	0x04,			/*  __u8  if_bDescriptorType; Interface */
+	0x00,			/*  __u8  if_bInterfaceNumber; */
+	0x00,			/*  __u8  if_bAlternateSetting; */
+	0x01,			/*  __u8  if_bNumEndpoints; */
+	0x09,			/*  __u8  if_bInterfaceClass; HUB_CLASSCODE */
+	0x00,			/*  __u8  if_bInterfaceSubClass; */
+	0x00,			/*  __u8  if_bInterfaceProtocol; */
+	0x00,			/*  __u8  if_iInterface; */
+
+	/* endpoint */
+	0x07,			/*  __u8  ep_bLength; */
+	0x05,			/*  __u8  ep_bDescriptorType; Endpoint */
+	0x81,			/*  __u8  ep_bEndpointAddress; IN Endpoint 1 */
+	0x03,			/*  __u8  ep_bmAttributes; Interrupt */
+	0x00,			/*  __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
+	0x02,
+	0xff			/*  __u8  ep_bInterval; 255 ms */
+};
+
+static unsigned char root_hub_str_index0[] = {
+	0x04,			/*  __u8  bLength; */
+	0x03,			/*  __u8  bDescriptorType; String-descriptor */
+	0x09,			/*  __u8  lang ID */
+	0x04,			/*  __u8  lang ID */
+};
+
+static unsigned char root_hub_str_index1[] = {
+	0x22,			/*  __u8  bLength; */
+	0x03,			/*  __u8  bDescriptorType; String-descriptor */
+	'I',			/*  __u8  Unicode */
+	0,			/*  __u8  Unicode */
+	'S',			/*  __u8  Unicode */
+	0,			/*  __u8  Unicode */
+	'P',			/*  __u8  Unicode */
+	0,			/*  __u8  Unicode */
+	'1',			/*  __u8  Unicode */
+	0,			/*  __u8  Unicode */
+	'1',			/*  __u8  Unicode */
+	0,			/*  __u8  Unicode */
+	'6',			/*  __u8  Unicode */
+	0,			/*  __u8  Unicode */
+	'x',			/*  __u8  Unicode */
+	0,			/*  __u8  Unicode */
+	' ',			/*  __u8  Unicode */
+	0,			/*  __u8  Unicode */
+	'R',			/*  __u8  Unicode */
+	0,			/*  __u8  Unicode */
+	'o',			/*  __u8  Unicode */
+	0,			/*  __u8  Unicode */
+	'o',			/*  __u8  Unicode */
+	0,			/*  __u8  Unicode */
+	't',			/*  __u8  Unicode */
+	0,			/*  __u8  Unicode */
+	' ',			/*  __u8  Unicode */
+	0,			/*  __u8  Unicode */
+	'H',			/*  __u8  Unicode */
+	0,			/*  __u8  Unicode */
+	'u',			/*  __u8  Unicode */
+	0,			/*  __u8  Unicode */
+	'b',			/*  __u8  Unicode */
+	0,			/*  __u8  Unicode */
+};
+
+/*
+ * Hub class-specific descriptor is constructed dynamically
+ */
+
+/* --- Virtual root hub management functions ------------------------------- */
+
+static int rh_check_port_status(struct isp116x *isp116x)
+{
+	u32 temp, ndp, i;
+	int res;
+
+	res = -1;
+	temp = isp116x_read_reg32(isp116x, HCRHSTATUS);
+	ndp = (temp & RH_A_NDP);
+	for (i = 0; i < ndp; i++) {
+		temp = isp116x_read_reg32(isp116x, HCRHPORT1 + i);
+		/* check for a device disconnect */
+		if (((temp & (RH_PS_PESC | RH_PS_CSC)) ==
+		     (RH_PS_PESC | RH_PS_CSC)) && ((temp & RH_PS_CCS) == 0)) {
+			res = i;
+			break;
+		}
+	}
+	return res;
+}
+
+/* --- HC management functions --------------------------------------------- */
+
+/* Write len bytes to fifo, pad till 32-bit boundary
+ */
+static void write_ptddata_to_fifo(struct isp116x *isp116x, void *buf, int len)
+{
+	u8 *dp = (u8 *) buf;
+	u16 *dp2 = (u16 *) buf;
+	u16 w;
+	int quot = len % 4;
+	
+/* For EtherNat, take the raw_write out in write functions, here we don't
+ * like that EtherNat swap the bytes for us, so we swap them before we send
+ * them, then the bytes will arrive to the USB device with the correct positions
+ */
+ 	if ((unsigned long)dp2 & 1) {
+	DEBUG_HOST("---not aligned ---");
+		/* not aligned */
+		for (; len > 1; len -= 2) {
+			w = *dp++;
+			w |= *dp++ << 8;
+			isp116x_write_data16(isp116x, w);
+		}
+		if (len)
+			isp116x_write_data16(isp116x, (u16) * dp);
+	} else {
+	DEBUG_HOST("---aligned ---");
+		/* aligned */
+		for (; len > 1; len -= 2)
+			isp116x_write_data16(isp116x, *dp2++);
+		if (len){DEBUG_HOST("write_data16\r\n"); /* GALVEZ: DEBUG */
+			isp116x_raw_write_data16(isp116x, 0xff & *((u8 *) dp2));}
+	}
+	if (quot == 1 || quot == 2)
+		isp116x_write_data16(isp116x, 0);
+}
+
+/* Read len bytes from fifo and then read till 32-bit boundary
+ */
+static void read_ptddata_from_fifo(struct isp116x *isp116x, void *buf, int len)
+{
+	u8 *dp = (u8 *) buf;
+	u16 *dp2 = (u16 *) buf;
+	u16 w;
+	int quot = len % 4;
+
+/* For EtherNAT, take the raw_read out from read functions, we want to swap the bytes
+   to read correct values because EtherNat swapped the bytes by hardware before we read 
+   them */
+
+	if ((unsigned long)dp2 & 1) {
+		/* not aligned */
+		DEBUG_HOST("---not aligned ---");
+		for (; len > 1; len -= 2) {
+			w = isp116x_read_data16(isp116x);
+			*dp++ = w & 0xff;
+			*dp++ = (w >> 8) & 0xff;
+		}
+		if (len)
+			*dp = 0xff & isp116x_read_data16(isp116x);
+	} else {
+		/* aligned */
+		DEBUG_HOST("---aligned ---");
+		for (; len > 1; len -= 2)
+			*dp2++ = isp116x_read_data16(isp116x);
+		if (len)
+			*(u8 *) dp2 = 0xff & isp116x_raw_read_data16(isp116x);
+	}
+	if (quot == 1 || quot == 2)
+		isp116x_read_data16(isp116x);
+}
+
+/* Write PTD's and data for scheduled transfers into the fifo ram.
+ * Fifo must be empty and ready */
+static void pack_fifo(struct isp116x *isp116x, struct usb_device *dev,
+		      unsigned long pipe, struct ptd *ptd, int n, void *data,
+		      int len)
+{
+	int buflen = n * sizeof(struct ptd) + len;
+	int i, done;
+
+	DEBUG_HOST("--- pack buffer %p - %d bytes (fifo %d) ---", data, len, buflen);
+	
+	isp116x_write_reg16(isp116x, HCuPINT, HCuPINT_AIIEOT);
+	
+	isp116x_write_reg16(isp116x, HCXFERCTR, buflen);
+	isp116x_write_addr(isp116x, HCATLPORT | ISP116x_WRITE_OFFSET);
+
+	done = 0;
+	for (i = 0; i < n; i++) {
+		DEBUG_HOST("i=%d - done=%d - len=%d", i, done, PTD_GET_LEN(&ptd[i]));
+
+/* For EtherNAT, use raw_write to don't swap bytes */
+		dump_ptd(&ptd[i]);
+		isp116x_raw_write_data16(isp116x, ptd[i].count);
+		isp116x_raw_write_data16(isp116x, ptd[i].mps);
+		isp116x_raw_write_data16(isp116x, ptd[i].len);
+		isp116x_raw_write_data16(isp116x, ptd[i].faddr);
+
+		dump_ptd_data(&ptd[i], (__u8 *) data + done, 0);
+
+		write_ptddata_to_fifo(isp116x,
+				      (__u8 *) data + done,
+				      PTD_GET_LEN(&ptd[i]));
+
+		done += PTD_GET_LEN(&ptd[i]);
+	}
+}
+
+/* Read the processed PTD's and data from fifo ram back to URBs' buffers.
+ * Fifo must be full and done */
+static int unpack_fifo(struct isp116x *isp116x, struct usb_device *dev,
+		       unsigned long pipe, struct ptd *ptd, int n, void *data,
+		       int len)
+{
+	int buflen = n * sizeof(struct ptd) + len;
+	int i, done, cc, ret;
+
+	isp116x_write_reg16(isp116x, HCuPINT, HCuPINT_AIIEOT);
+	isp116x_write_reg16(isp116x, HCXFERCTR, buflen);
+	isp116x_write_addr(isp116x, HCATLPORT);
+
+	ret = TD_CC_NOERROR;
+	done = 0;
+	for (i = 0; i < n; i++) {
+		/* Galvez: DEBUG */
+//		DEBUG_HOST("i=%d - done=%d - len=%d", i, done, PTD_GET_LEN(&ptd[i]));
+		DEBUG_HOST("i=%d n=%d - done=%d - len= %d ptd_len=%d\n\r", i,n, done, len, PTD_GET_LEN(&ptd[i]));
+		/*****************/
+		
+	/* For EtherNAT, use raw_read to don't swap bytes */
+		ptd[i].count = isp116x_raw_read_data16(isp116x);
+		ptd[i].mps = isp116x_raw_read_data16(isp116x);
+		ptd[i].len = isp116x_raw_read_data16(isp116x);
+		ptd[i].faddr = isp116x_raw_read_data16(isp116x);
+		dump_ptd(&ptd[i]);
+		
+		/* when cc is 15 the data has not being touch by the HC
+		 * so we have to read all to empty completly the buffer
+		 */
+//		if ( PTD_GET_COUNT(ptd) != 0 || PTD_GET_CC(ptd) == 15 )
+			read_ptddata_from_fifo(isp116x,
+					       (__u8 *) data + done,
+					       PTD_GET_LEN(&ptd[i]));
+		dump_ptd_data(&ptd[i], (__u8 *) data + done, 1);
+
+		done += PTD_GET_LEN(&ptd[i]);
+	
+		cc = PTD_GET_CC(&ptd[i]);
+	
+		/* Data underrun means basically that we had more buffer space than
+		 * the function had data. It is perfectly normal but upper levels have
+		 * to know how much we actually transferred.
+		 */
+		if (cc == TD_NOTACCESSED ||
+				(cc != TD_CC_NOERROR && (ret == TD_CC_NOERROR || ret == TD_DATAUNDERRUN)))
+			ret = cc;
+	}
+
+	DEBUG_HOST("--- unpack buffer %p - %d bytes (fifo %d) count: %d---\n", data, len, buflen, PTD_GET_COUNT(ptd));
+
+	return ret;
+}
+
+/* Interrupt handling
+ */
+static int isp116x_interrupt(struct isp116x *isp116x)
+{
+	u16 irqstat;
+	u32 intstat;
+	int ret = 0;
+
+	isp116x_write_reg16(isp116x, HCuPINTENB, 0);
+	irqstat = isp116x_read_reg16(isp116x, HCuPINT);
+	isp116x_write_reg16(isp116x, HCuPINT, irqstat);
+	DEBUG_HOST(">>>>>> irqstat %x <<<<<<", irqstat);
+	
+	if (irqstat & HCuPINT_ATL) {
+		DEBUG_HOST(">>>>>> HCuPINT_ATL <<<<<<");
+		udelay(500);
+		ret = 1;
+	}
+
+	if (irqstat & HCuPINT_OPR) {
+		intstat = isp116x_read_reg32(isp116x, HCINTSTAT);
+		isp116x_write_reg32(isp116x, HCINTSTAT, intstat);
+		DEBUG_HOST(">>>>>> HCuPINT_OPR %x <<<<<<", intstat);
+
+		if (intstat & HCINT_UE) {
+			ERR("unrecoverable error, controller disabled");
+
+			/* FIXME: be optimistic, hope that bug won't repeat
+			 * often. Make some non-interrupt context restart the
+			 * controller. Count and limit the retries though;
+			 * either hardware or software errors can go forever...
+			 */
+			isp116x_reset(isp116x);
+			ret = -1;
+			return -1;
+		}
+
+		if (intstat & HCINT_RHSC) {
+			got_rhsc = 1;
+			ret = 1;
+			/* When root hub or any of its ports is going
+			   to come out of suspend, it may take more
+			   than 10ms for status bits to stabilize. */
+			wait_ms(20);
+		}
+
+		if (intstat & HCINT_SO) {
+			ERR("schedule overrun");
+			ret = -1;
+		}
+
+		irqstat &= ~HCuPINT_OPR;
+	}
+
+	return ret;
+}
+
+/* With one PTD we can transfer almost 1K in one go;
+ * HC does the splitting into endpoint digestible transactions
+ */
+struct ptd ptd[1];
+
+static inline int max_transfer_len(struct usb_device *dev, unsigned long pipe)
+{
+	unsigned mpck = usb_maxpacket(dev, pipe);
+
+	/* One PTD can transfer 1023 bytes but try to always
+	 * transfer multiples of endpoint buffer size
+	 */
+	return 1023 / mpck * mpck;
+}
+
+/* Do an USB transfer
+ */
+static int isp116x_submit_job(struct usb_device *dev, unsigned long pipe,
+			      int dir, void *buffer, int len)
+{
+	struct isp116x *isp116x = &isp116x_dev;
+	int type = usb_pipetype(pipe);
+	int epnum = usb_pipeendpoint(pipe);
+	int max = usb_maxpacket(dev, pipe);
+	int dir_out = usb_pipeout(pipe);
+	int speed_low = usb_pipeslow(pipe);
+	int i, done = 0, stat, timeout, cc;
+
+	/* 500 frames or 0.5s timeout when function is busy and NAKs transactions for a while */
+	int retries = 500;
+
+
+	DEBUG_HOST("------------------------------------------------");
+	dump_msg(dev, pipe, buffer, len, "SUBMIT");
+	DEBUG_HOST("------------------------------------------------");
+	
+	if (len >= 1024) {
+		ERR("Too big job");
+		dev->status = USB_ST_CRC_ERR;
+		return -1;
+	}
+
+	if (isp116x->disabled) {
+		ERR("EPIPE");
+		dev->status = USB_ST_CRC_ERR;
+		return -1;
+	}
+
+	/* device pulled? Shortcut the action. */
+	if (devgone == dev) {
+		ERR("ENODEV");
+		dev->status = USB_ST_CRC_ERR;
+		return USB_ST_CRC_ERR;
+	}
+
+	if (!max) {
+		ERR("pipesize for pipe %lx is zero", pipe);
+		dev->status = USB_ST_CRC_ERR;
+		return -1;
+	}
+
+	if (type == PIPE_ISOCHRONOUS) {
+		ERR("isochronous transfers not supported");
+		dev->status = USB_ST_CRC_ERR;
+		return -1;
+	}
+	
+	/* FIFO not empty? */
+	if (isp116x_read_reg16(isp116x, HCBUFSTAT) & HCBUFSTAT_ATL_FULL) {
+		DEBUG_HOST("****** FIFO not empty! ******");
+		printf("****** FIFO not empty! ******\n\r");
+		dev->status = USB_ST_BUF_ERR;
+		return -1;
+	}
+
+retry:
+	isp116x_write_reg32(isp116x, HCINTSTAT, 0xff);
+	/* Prepare the PTD data */
+	ptd->count = PTD_CC_MSK | PTD_ACTIVE_MSK |
+		PTD_TOGGLE(usb_gettoggle(dev, epnum, dir_out));
+	ptd->mps = PTD_MPS(max) | PTD_SPD(speed_low) | PTD_EP(epnum) | PTD_LAST_MSK;
+	ptd->len = PTD_LEN(len) | PTD_DIR(dir);
+	ptd->faddr = PTD_FA(usb_pipedevice(pipe));
+
+	
+retry_same:
+
+	/* FIFO not empty? */ /* GALVEZ: DEBUG */
+	if (isp116x_read_reg16(isp116x, HCBUFSTAT) & HCBUFSTAT_ATL_FULL) {
+		DEBUG_HOST("****** FIFO not empty! ******");
+		printf("****** FIFO not empty! ******\n\r");
+		dev->status = USB_ST_BUF_ERR;
+		return -1;
+	}
+
+	/* Pack data into FIFO ram */
+	pack_fifo(isp116x, dev, pipe, ptd, 1, buffer, len);
+
+#ifdef EXTRA_DELAY
+	wait_ms(EXTRA_DELAY);
+#endif
+
+	/* Start the data transfer */
+
+	/* Allow more time for a BULK device to react - some are slow */
+	if (usb_pipebulk(pipe))
+		timeout = 5000; /* Galvez: default = 5000 */
+	else
+		timeout = 100;
+
+	/* Wait for it to complete */
+	for (;;) {
+		/* Check whether the controller is done */
+		stat = isp116x_interrupt(isp116x);
+
+		if (stat < 0) {
+			dev->status = USB_ST_CRC_ERR;
+			break;
+		}
+		if (stat > 0)
+			break;
+
+		/* Check the timeout */
+		if (--timeout)
+			udelay(1);
+		else {
+			ERR("CTL:TIMEOUT ");
+			printf("CTL:TIMEOUT ");
+			stat = USB_ST_CRC_ERR;
+			break;
+		}
+	}
+
+	/* We got an Root Hub Status Change interrupt */
+	if (got_rhsc) {
+		isp116x_show_regs(isp116x);
+
+		got_rhsc = 0;
+
+		/* Abuse timeout */
+		timeout = rh_check_port_status(isp116x);
+		if (timeout >= 0) {
+			/*
+			 * FIXME! NOTE! AAAARGH!
+			 * This is potentially dangerous because it assumes
+			 * that only one device is ever plugged in!
+			 */
+			devgone = dev;
+		}
+	}
+
+
+	/* Ok, now we can read transfer status */
+
+	/* FIFO not ready? */
+	if (!(isp116x_read_reg16(isp116x, HCBUFSTAT) & HCBUFSTAT_ATL_DONE)) {
+		DEBUG_HOST("****** FIFO not ready! ******");
+		printf("****** FIFO not ready! ******\n\r");
+		dev->status = USB_ST_BUF_ERR;
+		return -1;
+	}
+	
+	
+	/* Unpack data from FIFO ram */
+	cc = unpack_fifo(isp116x, dev, pipe, ptd, 1, buffer, len);
+
+	i = PTD_GET_COUNT(ptd);
+	done += i;
+	buffer += i;
+	len -= i;
+	
+	
+	/* There was some kind of real problem; Prepare the PTD again
+	 * and retry from the failed transaction on
+	 */
+	if (cc && cc != TD_NOTACCESSED && cc != TD_DATAUNDERRUN) {
+	DEBUG_HOST("PROBLEM cc: %d", cc);
+		if (retries >= 100) {
+			retries -= 100;
+			/* The chip will have toggled the toggle bit for the failed
+			 * transaction too. We have to toggle it back.
+			 */
+			usb_settoggle(dev, epnum, dir_out, !PTD_GET_TOGGLE(ptd));
+			goto retry;
+		}
+	}
+	/* "Normal" errors; TD_NOTACCESSED would mean in effect that the function have NAKed
+	 * the transactions from the first on for the whole frame. It may be busy and we retry
+	 * with the same PTD. PTD_ACTIVE (and not TD_NOTACCESSED) would mean that some of the
+	 * PTD didn't make it because the function was busy or the frame ended before the PTD
+	 * finished. We prepare the rest of the data and try again.
+	 */
+	else if ( cc == TD_NOTACCESSED ||  PTD_GET_ACTIVE(ptd) ||  ( cc != TD_DATAUNDERRUN && PTD_GET_COUNT(ptd) < PTD_GET_LEN(ptd))) {
+		DEBUG_HOST("NORMAL ERROR");
+		if (retries) {
+			--retries;
+			if (cc == TD_NOTACCESSED && PTD_GET_ACTIVE(ptd) && !PTD_GET_COUNT(ptd)) {
+				goto retry_same;
+			}
+			usb_settoggle(dev, epnum, dir_out, PTD_GET_TOGGLE(ptd));
+			goto retry;
+		}
+	}
+
+
+	if (cc != TD_CC_NOERROR && cc != TD_DATAUNDERRUN) {
+		DEBUG_HOST("****** completition code error %x ******", cc);
+		switch (cc) {
+		case TD_CC_BITSTUFFING:
+			dev->status = USB_ST_BIT_ERR;
+			break;
+		case TD_CC_STALL:
+			dev->status = USB_ST_STALLED;
+			break;
+		case TD_BUFFEROVERRUN:
+		case TD_BUFFERUNDERRUN:
+			dev->status = USB_ST_BUF_ERR;
+			break;
+		default:
+			dev->status = USB_ST_CRC_ERR;
+		}
+		return -cc;
+	}
+	else usb_settoggle(dev, epnum, dir_out, PTD_GET_TOGGLE(ptd));
+
+	dump_msg(dev, pipe, buffer, len, "SUBMIT(ret)");
+
+	dev->status = 0;
+	return done;
+}
+
+/* Adapted from au1x00_usb_ohci.c
+ */
+static int isp116x_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
+				 void *buffer, int transfer_len,
+				 struct devrequest *cmd)
+{
+	struct isp116x *isp116x = &isp116x_dev;
+	u32 tmp = 0;
+
+	int leni = transfer_len;
+	int len = 0;
+	int stat = 0;
+	u32 datab[4];
+	u8 *data_buf = (u8 *) datab;
+	u16 bmRType_bReq;
+	u16 wValue;
+	u16 wIndex;
+	u16 wLength;
+
+	if (usb_pipeint(pipe)) {
+		INFO("Root-Hub submit IRQ: NOT implemented");
+		return 0;
+	}
+
+	bmRType_bReq = cmd->requesttype | (cmd->request << 8);
+	wValue = swap_16(cmd->value);
+	wIndex = swap_16(cmd->index);
+	wLength = swap_16(cmd->length);
+
+	DEBUG_HOST("--- HUB ----------------------------------------");
+	DEBUG_HOST("submit rh urb, req=%x val=%#x index=%#x len=%d",
+	    bmRType_bReq, wValue, wIndex, wLength);
+	dump_msg(dev, pipe, buffer, transfer_len, "RH");
+	DEBUG_HOST("------------------------------------------------");
+
+	switch (bmRType_bReq) {
+	case RH_GET_STATUS:
+		DEBUG_HOST("RH_GET_STATUS");
+
+		*(__u16 *) data_buf = swap_16(1);
+		len = 2;
+		break;
+
+	case RH_GET_STATUS | RH_INTERFACE:
+		DEBUG_HOST("RH_GET_STATUS | RH_INTERFACE");
+
+		*(__u16 *) data_buf = swap_16(0);
+		len = 2;
+		break;
+
+	case RH_GET_STATUS | RH_ENDPOINT:
+		DEBUG_HOST("RH_GET_STATUS | RH_ENDPOINT");
+
+		*(__u16 *) data_buf = swap_16(0);
+		len = 2;
+		break;
+
+	case RH_GET_STATUS | RH_CLASS:
+		DEBUG_HOST("RH_GET_STATUS | RH_CLASS");
+
+		tmp = isp116x_read_reg32(isp116x, HCRHSTATUS);
+
+		*(__u32 *) data_buf = swap_32(tmp & ~(RH_HS_CRWE | RH_HS_DRWE));
+		len = 4;
+		break;
+
+	case RH_GET_STATUS | RH_OTHER | RH_CLASS:
+		DEBUG_HOST("RH_GET_STATUS | RH_OTHER | RH_CLASS");
+
+		tmp = isp116x_read_reg32(isp116x, HCRHPORT1 + wIndex - 1);
+		*(__u32 *) data_buf = swap_32(tmp);
+		isp116x_show_regs(isp116x);
+		len = 4;
+		break;
+
+	case RH_CLEAR_FEATURE | RH_ENDPOINT:
+		DEBUG_HOST("RH_CLEAR_FEATURE | RH_ENDPOINT");
+
+		switch (wValue) {
+		case RH_ENDPOINT_STALL:
+			DEBUG_HOST("C_HUB_ENDPOINT_STALL");
+			len = 0;
+			break;
+		}
+		break;
+
+	case RH_CLEAR_FEATURE | RH_CLASS:
+		DEBUG_HOST("RH_CLEAR_FEATURE | RH_CLASS");
+
+		switch (wValue) {
+		case RH_C_HUB_LOCAL_POWER:
+			DEBUG_HOST("C_HUB_LOCAL_POWER");
+			len = 0;
+			break;
+
+		case RH_C_HUB_OVER_CURRENT:
+			DEBUG_HOST("C_HUB_OVER_CURRENT");
+			isp116x_write_reg32(isp116x, HCRHSTATUS, RH_HS_OCIC);
+			len = 0;
+			break;
+		}
+		break;
+
+	case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
+		DEBUG_HOST("RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS");
+
+		switch (wValue) {
+		case RH_PORT_ENABLE:
+			isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
+					    RH_PS_CCS);
+			len = 0;
+			break;
+
+		case RH_PORT_SUSPEND:
+			isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
+					    RH_PS_POCI);
+			len = 0;
+			break;
+
+		case RH_PORT_POWER:
+			isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
+					    RH_PS_LSDA);
+			len = 0;
+			break;
+
+		case RH_C_PORT_CONNECTION:
+			isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
+					    RH_PS_CSC);
+			len = 0;
+			break;
+
+		case RH_C_PORT_ENABLE:
+			isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
+					    RH_PS_PESC);
+			len = 0;
+			break;
+
+		case RH_C_PORT_SUSPEND:
+			isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
+					    RH_PS_PSSC);
+			len = 0;
+			break;
+
+		case RH_C_PORT_OVER_CURRENT:
+			isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
+					    RH_PS_POCI);
+			len = 0;
+			break;
+
+		case RH_C_PORT_RESET:
+			isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
+					    RH_PS_PRSC);
+			len = 0;
+			break;
+
+		default:
+			ERR("invalid wValue");
+			stat = USB_ST_STALLED;
+		}
+
+		isp116x_show_regs(isp116x);
+
+		break;
+
+	case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
+		DEBUG_HOST("RH_SET_FEATURE | RH_OTHER | RH_CLASS");
+
+		switch (wValue) {
+		case RH_PORT_SUSPEND:
+			isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
+					    RH_PS_PSS);
+			len = 0;
+			break;
+
+		case RH_PORT_RESET:
+			/* Spin until any current reset finishes */
+			while (1) {
+				tmp =
+				    isp116x_read_reg32(isp116x,
+						       HCRHPORT1 + wIndex - 1);
+				if (!(tmp & RH_PS_PRS))
+					break;
+				wait_ms(1);
+			}
+			isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
+					    RH_PS_PRS);
+			wait_ms(10);
+
+			len = 0;
+			break;
+
+		case RH_PORT_POWER:
+			isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
+					    RH_PS_PPS);
+			len = 0;
+			break;
+
+		case RH_PORT_ENABLE:
+			isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
+					    RH_PS_PES);
+			len = 0;
+			break;
+
+		default:
+			ERR("invalid wValue");
+			stat = USB_ST_STALLED;
+		}
+
+		isp116x_show_regs(isp116x);
+
+		break;
+
+	case RH_SET_ADDRESS:
+		DEBUG_HOST("RH_SET_ADDRESS");
+
+		rh_devnum = wValue;
+		len = 0;
+		break;
+
+	case RH_GET_DESCRIPTOR:
+		DEBUG_HOST("RH_GET_DESCRIPTOR: %x, %d", wValue, wLength);
+
+		switch (wValue) {
+		case (USB_DT_DEVICE << 8):	/* device descriptor */
+			len = min1_t(unsigned int,
+				    leni, min2_t(unsigned int,
+						sizeof(root_hub_dev_des),
+						wLength));
+			data_buf = root_hub_dev_des;
+			break;
+
+		case (USB_DT_CONFIG << 8):	/* configuration descriptor */
+			len = min1_t(unsigned int,
+				    leni, min2_t(unsigned int,
+						sizeof(root_hub_config_des),
+						wLength));
+			data_buf = root_hub_config_des;
+			break;
+
+		case ((USB_DT_STRING << 8) | 0x00):	/* string 0 descriptors */
+			len = min1_t(unsigned int,
+				    leni, min2_t(unsigned int,
+						sizeof(root_hub_str_index0),
+						wLength));
+			data_buf = root_hub_str_index0;
+			break;
+
+		case ((USB_DT_STRING << 8) | 0x01):	/* string 1 descriptors */
+			len = min1_t(unsigned int,
+				    leni, min2_t(unsigned int,
+						sizeof(root_hub_str_index1),
+						wLength));
+			data_buf = root_hub_str_index1;
+			break;
+
+		default:
+			ERR("invalid wValue");
+			stat = USB_ST_STALLED;
+		}
+
+		break;
+
+	case RH_GET_DESCRIPTOR | RH_CLASS:
+		DEBUG_HOST("RH_GET_DESCRIPTOR | RH_CLASS");
+
+		tmp = isp116x_read_reg32(isp116x, HCRHDESCA);
+
+		data_buf[0] = 0x09;	/* min length; */
+		data_buf[1] = 0x29;
+		data_buf[2] = tmp & RH_A_NDP;
+		data_buf[3] = 0;
+		if (tmp & RH_A_PSM)	/* per-port power switching? */
+			data_buf[3] |= 0x01;
+		if (tmp & RH_A_NOCP)	/* no overcurrent reporting? */
+			data_buf[3] |= 0x10;
+		else if (tmp & RH_A_OCPM)	/* per-port overcurrent rep? */
+			data_buf[3] |= 0x08;
+
+		/* Corresponds to data_buf[4-7] */
+		datab[1] = 0;
+		data_buf[5] = (tmp & RH_A_POTPGT) >> 24;
+
+		tmp = isp116x_read_reg32(isp116x, HCRHDESCB);
+
+		data_buf[7] = tmp & RH_B_DR;
+		if (data_buf[2] < 7)
+			data_buf[8] = 0xff;
+		else {
+			data_buf[0] += 2;
+			data_buf[8] = (tmp & RH_B_DR) >> 8;
+			data_buf[10] = data_buf[9] = 0xff;
+		}
+
+		len = min1_t(unsigned int, leni,
+			    min2_t(unsigned int, data_buf[0], wLength));
+		break;
+
+	case RH_GET_CONFIGURATION:
+		DEBUG_HOST("RH_GET_CONFIGURATION");
+
+		*(__u8 *) data_buf = 0x01;
+		len = 1;
+		break;
+
+	case RH_SET_CONFIGURATION:
+		DEBUG_HOST("RH_SET_CONFIGURATION");
+
+		isp116x_write_reg32(isp116x, HCRHSTATUS, RH_HS_LPSC);
+		len = 0;
+		break;
+
+	default:
+		ERR("*** *** *** unsupported root hub command *** *** ***");
+		stat = USB_ST_STALLED;
+	}
+
+	len = min1_t(int, len, leni);
+	if (buffer != data_buf)
+		memcpy(buffer, data_buf, len);
+
+	dev->act_len = len;
+	dev->status = stat;
+	DEBUG_HOST("dev act_len %d, status %ld", dev->act_len, dev->status);
+
+	dump_msg(dev, pipe, buffer, transfer_len, "RH(ret)");
+
+	return stat;
+}
+
+/* --- Transfer functions -------------------------------------------------- */
+
+int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+		   int len, int interval)
+{
+	DEBUG_HOST("dev=%p pipe=%#lx buf=%p size=%d int=%d",
+	    dev, pipe, buffer, len, interval);
+
+	return -1;
+}
+
+int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+		       int len, struct devrequest *setup)
+{
+	int devnum = usb_pipedevice(pipe);
+	int epnum = usb_pipeendpoint(pipe);
+	int max = max_transfer_len(dev, pipe);
+	int dir_in = usb_pipein(pipe);
+	int done, ret;
+	
+	
+	/* Control message is for the HUB? */
+	if (devnum == rh_devnum)
+		return isp116x_submit_rh_msg(dev, pipe, buffer, len, setup);
+
+	/* Ok, no HUB message so send the message to the device */
+
+	/* Setup phase */
+	DEBUG_HOST("--- SETUP PHASE --------------------------------");
+	usb_settoggle(dev, epnum, 1, 0);
+	
+	
+	ret = isp116x_submit_job(dev, pipe,
+				PTD_DIR_SETUP,
+				 setup, sizeof(struct devrequest));
+	if (ret < 0) {
+		DEBUG_HOST("control setup phase error (ret = %d", ret);
+		return -1;
+	}
+
+	/* Data phase */
+	DEBUG_HOST("--- DATA PHASE ---------------------------------");
+	done = 0;
+	usb_settoggle(dev, epnum, !dir_in, 1);
+	while (done < len) {
+		ret = isp116x_submit_job(dev, pipe,
+					 dir_in ? PTD_DIR_IN : PTD_DIR_OUT,
+					 (__u8 *) buffer + done,
+					 max > len - done ? len - done : max);
+		if (ret < 0) {
+			DEBUG_HOST("control data phase error (ret = %d)", ret);
+			return -1;
+		}
+		done += ret;
+
+		if (dir_in && ret < max)	/* short packet */
+			break;
+	}
+
+	/* Status phase */
+	DEBUG_HOST("--- STATUS PHASE -------------------------------");
+	usb_settoggle(dev, epnum, !dir_in, 1);
+	ret = isp116x_submit_job(dev, pipe,
+				 !dir_in ? PTD_DIR_IN : PTD_DIR_OUT, NULL, 0);
+	if (ret < 0) {
+		DEBUG_HOST("control status phase error (ret = %d", ret);
+		return -1;
+	}
+
+	dev->act_len = done;
+
+	dump_msg(dev, pipe, buffer, len, "DEV(ret)");
+
+	return done;
+}
+
+int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+		    int len)
+{
+	int dir_out = usb_pipeout(pipe);
+	int max = max_transfer_len(dev, pipe);
+	int done, ret;
+	
+	DEBUG_HOST("--- BULK ---------------------------------------");
+	DEBUG_HOST("dev=%ld pipe=%ld buf=%p size=%d dir_out=%d",
+	    usb_pipedevice(pipe), usb_pipeendpoint(pipe), buffer, len, dir_out);
+
+	done = 0;
+	while (done < len) {
+
+		ret = isp116x_submit_job(dev, pipe,
+					 !dir_out ? PTD_DIR_IN : PTD_DIR_OUT,
+					 (__u8 *) buffer + done,
+					 max > len - done ? len - done : max);
+
+		if (ret < 0) {
+			DEBUG_HOST("error on bulk message (ret = %d)", ret);
+			return -1;
+		}
+
+		done += ret;
+
+		if (!dir_out && ret < max)	/* short packet */
+			break;
+	}
+
+	dev->act_len = done;
+
+	return 0;
+}
+
+/* --- Basic functions ----------------------------------------------------- */
+
+
+#if 0
+/* GALVEZ: Test function */
+static int GALVEZ_test_function( struct isp116x *isp116x )
+{
+	short rwc;
+
+	rwc = isp116x_read_reg16(isp116x, HCCONTROL) & HCCONTROL_RWC;
+	if (rwc) {
+		INFO ("remote wake-up supported \n\r");
+	}
+	return 0;
+
+}
+#endif
+
+static int isp116x_sw_reset(struct isp116x *isp116x)
+{
+	int retries = 15;
+	int ret = 0;
+
+	DEBUG_HOST("");
+
+	isp116x->disabled = 1;
+
+	isp116x_write_reg16(isp116x, HCSWRES, HCSWRES_MAGIC);
+	isp116x_write_reg32(isp116x, HCCMDSTAT, HCCMDSTAT_HCR);
+	
+	while (--retries) {
+		/* It usually resets within 1 ms */
+		/* GALVEZ: not enough for TOS, try 7 ms */
+		wait_ms(7);
+		if (!(isp116x_read_reg32(isp116x, HCCMDSTAT) & HCCMDSTAT_HCR))
+			break;
+	}
+	
+	if (!retries) {
+		ERR("software reset timeout");
+		ret = -1;
+	}
+
+#if 0
+	/* GALVEZ: DEBUG SOFTWARE RESET */
+		
+	retries = 5000;
+	
+	while (--retries){
+		if ((isp116x_read_reg32(isp116x, HCCMDSTAT) & HCCMDSTAT_HCR)) {
+			INFO ("HCR: 1 retries: %d\n\r",retries);
+		}
+	}
+#endif /* END DEBUG */
+
+	return ret;
+}
+
+static int isp116x_reset(struct isp116x *isp116x)
+{
+	unsigned long t;
+	u16 clkrdy = 0;
+	int ret, timeout = 15;/* ms
+				* Galvez: 15 ms sometimes isn't enough,
+				* for EtherNat under TOS ??????? increased to 150 ms 
+				*/ 
+
+	DEBUG_HOST("");
+
+	ret = isp116x_sw_reset(isp116x);
+
+	if (ret)
+		return ret;
+
+	for (t = 0; t < timeout; t++) {
+		clkrdy = isp116x_read_reg16(isp116x, HCuPINT) & HCuPINT_CLKRDY;
+		if (clkrdy)
+			break;
+		wait_ms(1);
+	}
+	if (!clkrdy) {
+		ERR("clock not ready after %dms", timeout);
+		/* After sw_reset the clock won't report to be ready, if
+		   H_WAKEUP pin is high. */
+		ERR("please make sure that the H_WAKEUP pin is pulled low!");
+		ret = -1;
+	}
+	return ret;
+}
+
+static void isp116x_stop(struct isp116x *isp116x)
+{
+	u32 val;
+	
+	DEBUG_HOST("");
+	
+	isp116x_write_reg16(isp116x, HCuPINTENB, 0);
+
+	/* Switch off ports' power, some devices don't come up
+	   after next 'start' without this */
+	val = isp116x_read_reg32(isp116x, HCRHDESCA);
+	val &= ~(RH_A_NPS | RH_A_PSM);
+	isp116x_write_reg32(isp116x, HCRHDESCA, val);
+	isp116x_write_reg32(isp116x, HCRHSTATUS, RH_HS_LPS);
+	
+	isp116x_sw_reset(isp116x);
+	
+#if 0	
+	/* EtherNAT control register, disamble interrupt for USB */
+	u8 *cpld_cr, value;
+	p = SuperFromUser();
+	cpld_cr = ETHERNAT_CPLD_CR;
+	value = *cpld_cr;
+	INFO ("ETHERNAT_CPLD_CR %x", value);
+	value &= 0xFB;
+	INFO ("ETHERNAT_CPLD_CR %x", value);
+	*cpld_cr = value;
+	SuperToUser(p);
+#endif
+}
+
+/*
+ *  Configure the chip. The chip must be successfully reset by now.
+ */
+static int isp116x_start(struct isp116x *isp116x)
+{
+	struct isp116x_platform_data *board = isp116x->board;
+	u32 val;
+	
+	DEBUG_HOST("");
+
+	/* Clear interrupt status and disable all interrupt sources */
+	isp116x_write_reg16(isp116x, HCuPINT, 0xff);
+	isp116x_write_reg16(isp116x, HCuPINTENB, 0);
+
+	isp116x_write_reg16(isp116x, HCITLBUFLEN, ISP116x_ITL_BUFSIZE);
+	isp116x_write_reg16(isp116x, HCATLBUFLEN, ISP116x_ATL_BUFSIZE);
+
+	/* Hardware configuration */
+	val = HCHWCFG_DBWIDTH(1);
+
+	if (board->sel15Kres)
+		val |= HCHWCFG_15KRSEL;
+	/* Remote wakeup won't work without working clock */
+	if (board->remote_wakeup_enable)
+		val |= HCHWCFG_CLKNOTSTOP;
+	if (board->oc_enable)
+		val |= HCHWCFG_ANALOG_OC;
+	isp116x_write_reg16(isp116x, HCHWCFG, val);
+
+#if 0
+	/* EtherNAT control register, enable interrupt for USB */
+	u8 *cpld_cr, value;
+	p = SuperFromUser();
+	cpld_cr = ETHERNAT_CPLD_CR;
+	INFO ("%s: ETHERNAT_CPLD_CR reg: %x",__FUNCTION__, *cpld_cr);
+	value = *cpld_cr;
+	value |= 0x04;
+	Bconin(DEV_CONSOLE);
+	*cpld_cr = value;
+	Bconin(DEV_CONSOLE);
+	INFO ("%s: ETHERNAT_CPLD_CR reg:%x", __FUNCTION__, *cpld_cr);
+	SuperToUser(p);
+#endif	
+	/* --- Root hub configuration */
+	val = (25 << 24) & RH_A_POTPGT;
+	/* AN10003_1.pdf recommends RH_A_NPS (no power switching) to
+	   be always set. Yet, instead, we request individual port
+	   power switching. */
+	val |= RH_A_PSM;
+	/* Report overcurrent per port */
+	val |= RH_A_OCPM;
+	isp116x_write_reg32(isp116x, HCRHDESCA, val);
+	isp116x->rhdesca = isp116x_read_reg32(isp116x, HCRHDESCA);
+
+	val = RH_B_PPCM;
+	isp116x_write_reg32(isp116x, HCRHDESCB, val);
+	isp116x->rhdescb = isp116x_read_reg32(isp116x, HCRHDESCB);
+
+	val = 0;
+	if (board->remote_wakeup_enable)
+		val |= RH_HS_DRWE;
+	isp116x_write_reg32(isp116x, HCRHSTATUS, val);
+	isp116x->rhstatus = isp116x_read_reg32(isp116x, HCRHSTATUS);
+
+	isp116x_write_reg32(isp116x, HCFMINTVL, 0x27782edf);
+
+	/* Go operational */
+	val = HCCONTROL_USB_OPER;
+	if (board->remote_wakeup_enable)
+		val |= HCCONTROL_RWE;
+	isp116x_write_reg32(isp116x, HCCONTROL, val);
+
+	/* Disable ports to avoid race in device enumeration */
+	isp116x_write_reg32(isp116x, HCRHPORT1, RH_PS_CCS);
+	isp116x_write_reg32(isp116x, HCRHPORT2, RH_PS_CCS);
+
+	isp116x_show_regs(isp116x);
+
+	isp116x->disabled = 0;
+
+	return 0;
+}
+
+/* --- Init functions ------------------------------------------------------ */
+
+
+
+int isp116x_check_id(struct isp116x *isp116x)
+{
+	u16 val;
+
+	val = isp116x_read_reg16(isp116x, HCCHIPID);
+	DEBUG_HOST("chip ID: %04x", val);
+
+	if ((val & HCCHIPID_MASK) != HCCHIPID_MAGIC) {
+		printf("invalid chip ID %04x", val);
+		return -1;
+	}
+
+	return 0;
+}
+
+
+int usb_lowlevel_init(void)
+{
+//	u16 val;
+
+	struct isp116x *isp116x = &isp116x_dev;
+
+	DEBUG_HOST("");
+
+	got_rhsc = rh_devnum = 0;
+
+	/* Init device registers addr */
+	isp116x->addr_reg = (u16 *) ISP116X_HCD_ADDR;
+	isp116x->data_reg = (u16 *) ISP116X_HCD_DATA;
+
+	/* Setup specific board settings */
+#ifdef ISP116X_HCD_SEL15kRES
+	isp116x_board.sel15Kres = 1;
+#endif
+#ifdef ISP116X_HCD_OC_ENABLE
+	isp116x_board.oc_enable = 1;
+#endif
+#ifdef ISP116X_HCD_REMOTE_WAKEUP_ENABLE
+	isp116x_board.remote_wakeup_enable = 1;
+#endif
+	isp116x->board = &isp116x_board;
+
+	/* Try to get ISP116x silicon chip ID */
+	if (isp116x_check_id(isp116x) < 0)
+		return (-1);
+		
+	isp116x->disabled = 1;
+	isp116x->sleeping = 0;
+
+	isp116x_reset(isp116x);
+	isp116x_start(isp116x);
+
+	return 0;
+}
+
+int usb_lowlevel_stop(void)
+{
+	struct isp116x *isp116x = &isp116x_dev;
+
+	DEBUG_HOST("");
+
+	if (!isp116x->disabled)
+		isp116x_stop(isp116x);
+
+	return 0;
+}
diff --git a/FireBee/trunk/usb/store/host/ethernat/isp116x.h b/FireBee/trunk/usb/store/host/ethernat/isp116x.h
new file mode 100644
index 0000000..26678ba
--- /dev/null
+++ b/FireBee/trunk/usb/store/host/ethernat/isp116x.h
@@ -0,0 +1,542 @@
+/*
+ * Modified for Atari-EtherNat by David Gálvez 2010
+ *
+ * ISP116x register declarations and HCD data structures
+ *
+ * Copyright (C) 2007 Rodolfo Giometti <giometti@linux.it>
+ * Copyright (C) 2007 Eurotech S.p.A. <info@eurotech.it>
+ * Copyright (C) 2005 Olav Kongas <ok@artecdesign.ee>
+ * Portions:
+ * Copyright (C) 2004 Lothar Wassmann
+ * Copyright (C) 2004 Psion Teklogix
+ * Copyright (C) 2004 David Brownell
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ETHERNAT_ISP116X_H
+#define _ETHERNAT_ISP116X_H
+
+
+#define ERR(fmt, args...)	printf("isp116x: %s: " fmt "\n\r" , __FUNCTION__ , ## args)
+#define WARN(fmt, args...)	printf("isp116x: %s: " fmt "\n\r" , __FUNCTION__ , ## args)
+#define INFO(fmt, args...)	printf("isp116x: " fmt "\n\r" , ## args)
+
+/* ------------------------------------------------------------------------- */
+
+/* us of 1ms frame */
+#define  MAX_LOAD_LIMIT		850
+
+/* Full speed: max # of bytes to transfer for a single urb
+   at a time must be < 1024 && must be multiple of 64.
+   832 allows transfering 4kiB within 5 frames. */
+#define MAX_TRANSFER_SIZE_FULLSPEED	832
+
+/* Low speed: there is no reason to schedule in very big
+   chunks; often the requested long transfers are for
+   string descriptors containing short strings. */
+#define MAX_TRANSFER_SIZE_LOWSPEED	64
+
+/* Bytetime (us), a rough indication of how much time it
+   would take to transfer a byte of useful data over USB */
+#define BYTE_TIME_FULLSPEED	1
+#define BYTE_TIME_LOWSPEED	20
+
+/* Buffer sizes */
+#define ISP116x_BUF_SIZE	4096
+#define ISP116x_ITL_BUFSIZE	0
+#define ISP116x_ATL_BUFSIZE	((ISP116x_BUF_SIZE) - 2*(ISP116x_ITL_BUFSIZE))
+
+#define ISP116x_WRITE_OFFSET	0x80
+
+/* --- ISP116x address registers in EtherNAT --------------------------------*/
+
+#define ISP116X_HCD_ADDR	0x80000016
+#define ISP116X_HCD_DATA	0x80000012
+#define ETHERNAT_CPLD_CR	0x80000023   /* 0x80000023 - 1 */
+
+/* --- ISP116x registers/bits ---------------------------------------------- */
+
+#define	HCREVISION	0x00
+#define	HCCONTROL	0x01
+#define		HCCONTROL_HCFS	(3 << 6)	/* host controller
+						   functional state */
+#define		HCCONTROL_USB_RESET	(0 << 6)
+#define		HCCONTROL_USB_RESUME	(1 << 6)
+#define		HCCONTROL_USB_OPER	(2 << 6)
+#define		HCCONTROL_USB_SUSPEND	(3 << 6)
+#define		HCCONTROL_RWC	(1 << 9)	/* remote wakeup connected */
+#define		HCCONTROL_RWE	(1 << 10)	/* remote wakeup enable */
+#define	HCCMDSTAT	0x02
+#define		HCCMDSTAT_HCR	(1 << 0)	/* host controller reset */
+#define		HCCMDSTAT_SOC	(3 << 16)	/* scheduling overrun count */
+#define	HCINTSTAT	0x03
+#define		HCINT_SO	(1 << 0)	/* scheduling overrun */
+#define		HCINT_WDH	(1 << 1)	/* writeback of done_head */
+#define		HCINT_SF	(1 << 2)	/* start frame */
+#define		HCINT_RD	(1 << 3)	/* resume detect */
+#define		HCINT_UE	(1 << 4)	/* unrecoverable error */
+#define		HCINT_FNO	(1 << 5)	/* frame number overflow */
+#define		HCINT_RHSC	(1 << 6)	/* root hub status change */
+#define		HCINT_OC	(1 << 30)	/* ownership change */
+#define		HCINT_MIE	(1 << 31)	/* master interrupt enable */
+#define	HCINTENB	0x04
+#define	HCINTDIS	0x05
+#define	HCFMINTVL	0x0d
+#define	HCFMREM		0x0e
+#define	HCFMNUM		0x0f
+#define	HCLSTHRESH	0x11
+#define	HCRHDESCA	0x12
+#define		RH_A_NDP	(0x3 << 0)	/* # downstream ports */
+#define		RH_A_PSM	(1 << 8)	/* power switching mode */
+#define		RH_A_NPS	(1 << 9)	/* no power switching */
+#define		RH_A_DT		(1 << 10)	/* device type (mbz) */
+#define		RH_A_OCPM	(1 << 11)	/* overcurrent protection
+						   mode */
+#define		RH_A_NOCP	(1 << 12)	/* no overcurrent protection */
+#define		RH_A_POTPGT	(0xff << 24)	/* power on -> power good
+						   time */
+#define	HCRHDESCB	0x13
+#define		RH_B_DR		(0xffff << 0)	/* device removable flags */
+#define		RH_B_PPCM	(0xffff << 16)	/* port power control mask */
+#define	HCRHSTATUS	0x14
+#define		RH_HS_LPS	(1 << 0)	/* local power status */
+#define		RH_HS_OCI	(1 << 1)	/* over current indicator */
+#define		RH_HS_DRWE	(1 << 15)	/* device remote wakeup
+						   enable */
+#define		RH_HS_LPSC	(1 << 16)	/* local power status change */
+#define		RH_HS_OCIC	(1 << 17)	/* over current indicator
+						   change */
+#define		RH_HS_CRWE	(1 << 31)	/* clear remote wakeup
+						   enable */
+#define	HCRHPORT1	0x15
+#define		RH_PS_CCS	(1 << 0)	/* current connect status */
+#define		RH_PS_PES	(1 << 1)	/* port enable status */
+#define		RH_PS_PSS	(1 << 2)	/* port suspend status */
+#define		RH_PS_POCI	(1 << 3)	/* port over current
+						   indicator */
+#define		RH_PS_PRS	(1 << 4)	/* port reset status */
+#define		RH_PS_PPS	(1 << 8)	/* port power status */
+#define		RH_PS_LSDA	(1 << 9)	/* low speed device attached */
+#define		RH_PS_CSC	(1 << 16)	/* connect status change */
+#define		RH_PS_PESC	(1 << 17)	/* port enable status change */
+#define		RH_PS_PSSC	(1 << 18)	/* port suspend status
+						   change */
+#define		RH_PS_OCIC	(1 << 19)	/* over current indicator
+						   change */
+#define		RH_PS_PRSC	(1 << 20)	/* port reset status change */
+#define		HCRHPORT_CLRMASK	(0x1f << 16)
+#define	HCRHPORT2	0x16
+#define	HCHWCFG		0x20
+#define		HCHWCFG_15KRSEL		(1 << 12)
+#define		HCHWCFG_CLKNOTSTOP	(1 << 11)
+#define		HCHWCFG_ANALOG_OC	(1 << 10)
+#define		HCHWCFG_DACK_MODE	(1 << 8)
+#define		HCHWCFG_EOT_POL		(1 << 7)
+#define		HCHWCFG_DACK_POL	(1 << 6)
+#define		HCHWCFG_DREQ_POL	(1 << 5)
+#define		HCHWCFG_DBWIDTH_MASK	(0x03 << 3)
+#define		HCHWCFG_DBWIDTH(n)	(((n) << 3) & HCHWCFG_DBWIDTH_MASK)
+#define		HCHWCFG_INT_POL		(1 << 2)
+#define		HCHWCFG_INT_TRIGGER	(1 << 1)
+#define		HCHWCFG_INT_ENABLE	(1 << 0)
+#define	HCDMACFG	0x21
+#define		HCDMACFG_BURST_LEN_MASK	(0x03 << 5)
+#define		HCDMACFG_BURST_LEN(n)	(((n) << 5) & HCDMACFG_BURST_LEN_MASK)
+#define		HCDMACFG_BURST_LEN_1	HCDMACFG_BURST_LEN(0)
+#define		HCDMACFG_BURST_LEN_4	HCDMACFG_BURST_LEN(1)
+#define		HCDMACFG_BURST_LEN_8	HCDMACFG_BURST_LEN(2)
+#define		HCDMACFG_DMA_ENABLE	(1 << 4)
+#define		HCDMACFG_BUF_TYPE_MASK	(0x07 << 1)
+#define		HCDMACFG_CTR_SEL	(1 << 2)
+#define		HCDMACFG_ITLATL_SEL	(1 << 1)
+#define		HCDMACFG_DMA_RW_SELECT	(1 << 0)
+#define	HCXFERCTR	0x22
+#define	HCuPINT		0x24
+#define		HCuPINT_SOF		(1 << 0)
+#define		HCuPINT_ATL		(1 << 1)
+#define		HCuPINT_AIIEOT		(1 << 2)
+#define		HCuPINT_OPR		(1 << 4)
+#define		HCuPINT_SUSP		(1 << 5)
+#define		HCuPINT_CLKRDY		(1 << 6)
+#define	HCuPINTENB	0x25
+#define	HCCHIPID	0x27
+#define		HCCHIPID_MASK		0xff00
+#define		HCCHIPID_MAGIC		0x6100
+#define	HCSCRATCH	0x28
+#define	HCSWRES		0x29
+#define		HCSWRES_MAGIC		0x00f6
+#define	HCITLBUFLEN	0x2a
+#define	HCATLBUFLEN	0x2b
+#define	HCBUFSTAT	0x2c
+#define		HCBUFSTAT_ITL0_FULL	(1 << 0)
+#define		HCBUFSTAT_ITL1_FULL	(1 << 1)
+#define		HCBUFSTAT_ATL_FULL	(1 << 2)
+#define		HCBUFSTAT_ITL0_DONE	(1 << 3)
+#define		HCBUFSTAT_ITL1_DONE	(1 << 4)
+#define		HCBUFSTAT_ATL_DONE	(1 << 5)
+#define	HCRDITL0LEN	0x2d
+#define	HCRDITL1LEN	0x2e
+#define	HCITLPORT	0x40
+#define	HCATLPORT	0x41
+
+/* PTD accessor macros. */
+#define PTD_GET_COUNT(p)	(((p)->count & PTD_COUNT_MSK) >> 0)
+#define PTD_COUNT(v)		(((v) << 0) & PTD_COUNT_MSK)
+#define PTD_GET_TOGGLE(p)	(((p)->count & PTD_TOGGLE_MSK) >> 10)
+#define PTD_TOGGLE(v)		(((v) << 10) & PTD_TOGGLE_MSK)
+#define PTD_GET_ACTIVE(p)	(((p)->count & PTD_ACTIVE_MSK) >> 11)
+#define PTD_ACTIVE(v)		(((v) << 11) & PTD_ACTIVE_MSK)
+#define PTD_GET_CC(p)		(((p)->count & PTD_CC_MSK) >> 12)
+#define PTD_CC(v)		(((v) << 12) & PTD_CC_MSK)
+#define PTD_GET_MPS(p)		(((p)->mps & PTD_MPS_MSK) >> 0)
+#define PTD_MPS(v)		(((v) << 0) & PTD_MPS_MSK)
+#define PTD_GET_SPD(p)		(((p)->mps & PTD_SPD_MSK) >> 10)
+#define PTD_SPD(v)		(((v) << 10) & PTD_SPD_MSK)
+#define PTD_GET_LAST(p)		(((p)->mps & PTD_LAST_MSK) >> 11)
+#define PTD_LAST(v)		(((v) << 11) & PTD_LAST_MSK)
+#define PTD_GET_EP(p)		(((p)->mps & PTD_EP_MSK) >> 12)
+#define PTD_EP(v)		(((v) << 12) & PTD_EP_MSK)
+#define PTD_GET_LEN(p)		(((p)->len & PTD_LEN_MSK) >> 0)
+#define PTD_LEN(v)		(((v) << 0) & PTD_LEN_MSK)
+#define PTD_GET_DIR(p)		(((p)->len & PTD_DIR_MSK) >> 10)
+#define PTD_DIR(v)		(((v) << 10) & PTD_DIR_MSK)
+#define PTD_GET_B5_5(p)		(((p)->len & PTD_B5_5_MSK) >> 13)
+#define PTD_B5_5(v)		(((v) << 13) & PTD_B5_5_MSK)
+#define PTD_GET_FA(p)		(((p)->faddr & PTD_FA_MSK) >> 0)
+#define PTD_FA(v)		(((v) << 0) & PTD_FA_MSK)
+#define PTD_GET_FMT(p)		(((p)->faddr & PTD_FMT_MSK) >> 7)
+#define PTD_FMT(v)		(((v) << 7) & PTD_FMT_MSK)
+
+/*  Hardware transfer status codes -- CC from ptd->count */
+#define TD_CC_NOERROR      0x00
+#define TD_CC_CRC          0x01
+#define TD_CC_BITSTUFFING  0x02
+#define TD_CC_DATATOGGLEM  0x03
+#define TD_CC_STALL        0x04
+#define TD_DEVNOTRESP      0x05
+#define TD_PIDCHECKFAIL    0x06
+#define TD_UNEXPECTEDPID   0x07
+#define TD_DATAOVERRUN     0x08
+#define TD_DATAUNDERRUN    0x09
+    /* 0x0A, 0x0B reserved for hardware */
+#define TD_BUFFEROVERRUN   0x0C
+#define TD_BUFFERUNDERRUN  0x0D
+    /* 0x0E, 0x0F reserved for HCD */
+#define TD_NOTACCESSED     0x0F
+
+/* ------------------------------------------------------------------------- */
+
+#define	LOG2_PERIODIC_SIZE	5	/* arbitrary; this matches OHCI */
+#define	PERIODIC_SIZE		(1 << LOG2_PERIODIC_SIZE)
+
+/* Philips transfer descriptor */
+struct ptd {
+	u16 count;
+#define	PTD_COUNT_MSK	(0x3ff << 0)
+#define	PTD_TOGGLE_MSK	(1 << 10)
+#define	PTD_ACTIVE_MSK	(1 << 11)
+#define	PTD_CC_MSK	(0xf << 12)
+	u16 mps;
+#define	PTD_MPS_MSK	(0x3ff << 0)
+#define	PTD_SPD_MSK	(1 << 10)
+#define	PTD_LAST_MSK	(1 << 11)
+#define	PTD_EP_MSK	(0xf << 12)
+	u16 len;
+#define	PTD_LEN_MSK	(0x3ff << 0)
+#define	PTD_DIR_MSK	(3 << 10)
+#define	PTD_DIR_SETUP	(0)
+#define	PTD_DIR_OUT	(1)
+#define	PTD_DIR_IN	(2)
+#define	PTD_B5_5_MSK	(1 << 13)
+	u16 faddr;
+#define	PTD_FA_MSK	(0x7f << 0)
+#define	PTD_FMT_MSK	(1 << 7)
+} __attribute__ ((packed, aligned(2)));
+
+struct isp116x_ep {
+	struct usb_device *udev;
+	struct ptd ptd;
+
+	u8 maxpacket;
+	u8 epnum;
+	u8 nextpid;
+
+	u16 length;		/* of current packet */
+	unsigned char *data;	/* to databuf */
+
+	u16 error_count;
+};
+
+/* URB struct */
+#define N_URB_TD		48
+#define URB_DEL			1
+typedef struct {
+	struct isp116x_ep *ed;
+	void *transfer_buffer;	/* (in) associated data buffer */
+	int actual_length;	/* (return) actual transfer length */
+	unsigned long pipe;	/* (in) pipe information */
+#if 0
+	int state;
+#endif
+} urb_priv_t;
+
+struct isp116x_platform_data {
+	/* Enable internal resistors on downstream ports */
+	unsigned sel15Kres:1;
+	/* On-chip overcurrent detection */
+	unsigned oc_enable:1;
+	/* Enable wakeup by devices on usb bus (e.g. wakeup
+	   by attachment/detachment or by device activity
+	   such as moving a mouse). When chosen, this option
+	   prevents stopping internal clock, increasing
+	   thereby power consumption in suspended state. */
+	unsigned remote_wakeup_enable:1;
+};
+
+struct isp116x {
+	u16 *addr_reg;
+	u16 *data_reg;
+
+	struct isp116x_platform_data *board;
+
+	struct dentry *dentry;
+	unsigned long stat1, stat2, stat4, stat8, stat16;
+
+	/* Status flags */
+	unsigned disabled:1;
+	unsigned sleeping:1;
+
+	/* Root hub registers */
+	u32 rhdesca;
+	u32 rhdescb;
+	u32 rhstatus;
+	u32 rhport[2];
+
+	/* Schedule for the current frame */
+	struct isp116x_ep *atl_active;
+	int atl_buflen;
+	int atl_bufshrt;
+	int atl_last_dir;
+	int atl_finishing;
+};
+
+/* ------------------------------------------------- */
+
+/* Inter-io delay (ns). The chip is picky about access timings; it
+ * expects at least:
+ * 150ns delay between consecutive accesses to DATA_REG,
+ * 300ns delay between access to ADDR_REG and DATA_REG
+ * OE, WE MUST NOT be changed during these intervals
+ */
+#if defined(UDELAY)
+#define	isp116x_delay(h,d)	udelay(d)
+#else
+#define	isp116x_delay(h,d)	do {} while (0)
+#endif
+
+#include "../../super.h"	/*
+	 		 * Functions to call supervisor mode
+		 	 * Super() in TOS is buggy
+			 */
+
+u32 p;	
+			 
+static inline void isp116x_write_addr(struct isp116x *isp116x, unsigned reg)
+{
+//	p = SuperFromUser( );
+	__raw_writew(reg & 0xff, isp116x->addr_reg );
+	isp116x_delay(isp116x, UDELAY);
+//	SuperToUser( p );
+}
+
+static inline void isp116x_write_data16(struct isp116x *isp116x, u16 val)
+{
+//	p = SuperFromUser( );
+	writew(val, isp116x->data_reg);
+	isp116x_delay(isp116x, UDELAY);
+//	SuperToUser( p );
+}
+
+static inline void isp116x_raw_write_data16(struct isp116x *isp116x, u16 val)
+{
+//	p = SuperFromUser( );
+	__raw_writew(val, isp116x->data_reg);
+	isp116x_delay(isp116x, UDELAY);
+//	SuperToUser( p );
+}
+
+static inline u16 isp116x_read_data16(struct isp116x *isp116x)
+{
+	u16 val;
+//	p = SuperFromUser( );
+	val = readw(isp116x->data_reg);
+	isp116x_delay(isp116x, UDELAY);
+//	SuperToUser( p );
+	return val;
+}
+
+static inline u16 isp116x_raw_read_data16(struct isp116x *isp116x)
+{
+	u16 val;
+//	p = SuperFromUser( );
+	val = __raw_readw(isp116x->data_reg);
+	isp116x_delay(isp116x, UDELAY);
+//	SuperToUser( p );
+	return val;
+}
+
+
+static inline void isp116x_write_data32(struct isp116x *isp116x, u32 val)
+{
+//	p = SuperFromUser( );
+	writew(val & 0xffff, isp116x->data_reg);
+	isp116x_delay(isp116x, UDELAY);
+	writew(val >> 16, isp116x->data_reg);
+	isp116x_delay(isp116x, UDELAY);
+//	SuperToUser( p );
+}
+
+/*
+ * Added for EtherNat, to write HC registers without swaping them
+ * EtherNat already swap them by hardware (i suppose.....)
+ */
+static inline void isp116x_raw_write_data32(struct isp116x *isp116x, u32 val)
+{
+//	p = SuperFromUser( );
+	__raw_writew(val & 0xffff, isp116x->data_reg);
+	isp116x_delay(isp116x, UDELAY);
+	__raw_writew(val >> 16, isp116x->data_reg);
+	isp116x_delay(isp116x, UDELAY);
+//	SuperToUser( p );
+}
+/***********************************************/
+
+static inline u32 isp116x_read_data32(struct isp116x *isp116x)
+{
+	u32 val;
+//	p = SuperFromUser( );
+	val = (u32) readw(isp116x->data_reg);
+	isp116x_delay(isp116x, UDELAY);
+	val |= ((u32) readw(isp116x->data_reg)) << 16;
+	isp116x_delay(isp116x, UDELAY);
+//	SuperToUser( p );
+	return val;
+}
+
+/*
+ * Added for EtherNat, to read HC registers without swaping them
+ * EtherNat already swap them by hardware (i suppose.....)
+ */
+static inline u32 isp116x_raw_read_data32(struct isp116x *isp116x)
+{
+	u32 val;
+//	p = SuperFromUser( );
+	val = (u32) __raw_readw(isp116x->data_reg);
+	isp116x_delay(isp116x, UDELAY);
+	val |= ((u32) __raw_readw(isp116x->data_reg)) << 16;
+	isp116x_delay(isp116x, UDELAY);
+//	SuperToUser( p );
+	return val;
+}
+/*******************************************************************/
+
+/* Let's keep register access functions out of line. Hint:
+   we wait at least 150 ns at every access.
+*/
+
+/* with EtherNat use raw_read to avoid swaping bytes*/
+
+static u16 isp116x_read_reg16(struct isp116x *isp116x, unsigned reg)
+{
+	isp116x_write_addr(isp116x, reg);
+	return isp116x_raw_read_data16(isp116x);
+}
+
+static u32 isp116x_read_reg32(struct isp116x *isp116x, unsigned reg)
+{
+	isp116x_write_addr(isp116x, reg);
+	return isp116x_raw_read_data32(isp116x);
+}
+
+static void isp116x_write_reg16(struct isp116x *isp116x, unsigned reg,
+				unsigned val)
+{
+	isp116x_write_addr(isp116x, reg | ISP116x_WRITE_OFFSET);
+	isp116x_raw_write_data16(isp116x, (u16) (val & 0xffff));
+}
+
+/* with Etehrnat used raw_write to avoid swaping bytes by software */
+static void isp116x_write_reg32(struct isp116x *isp116x, unsigned reg,
+				unsigned val)
+{
+	isp116x_write_addr(isp116x, reg | ISP116x_WRITE_OFFSET);
+	isp116x_raw_write_data32(isp116x, (u32) val);
+}
+
+/* --- USB HUB constants (not OHCI-specific; see hub.h) -------------------- */
+
+/* destination of request */
+#define RH_INTERFACE               0x01
+#define RH_ENDPOINT                0x02
+#define RH_OTHER                   0x03
+
+#define RH_CLASS                   0x20
+#define RH_VENDOR                  0x40
+
+/* Requests: bRequest << 8 | bmRequestType */
+#define RH_GET_STATUS           0x0080
+#define RH_CLEAR_FEATURE        0x0100
+#define RH_SET_FEATURE          0x0300
+#define RH_SET_ADDRESS          0x0500
+#define RH_GET_DESCRIPTOR       0x0680
+#define RH_SET_DESCRIPTOR       0x0700
+#define RH_GET_CONFIGURATION    0x0880
+#define RH_SET_CONFIGURATION    0x0900
+#define RH_GET_STATE            0x0280
+#define RH_GET_INTERFACE        0x0A80
+#define RH_SET_INTERFACE        0x0B00
+#define RH_SYNC_FRAME           0x0C80
+/* Our Vendor Specific Request */
+#define RH_SET_EP               0x2000
+
+/* Hub port features */
+#define RH_PORT_CONNECTION         0x00
+#define RH_PORT_ENABLE             0x01
+#define RH_PORT_SUSPEND            0x02
+#define RH_PORT_OVER_CURRENT       0x03
+#define RH_PORT_RESET              0x04
+#define RH_PORT_POWER              0x08
+#define RH_PORT_LOW_SPEED          0x09
+
+#define RH_C_PORT_CONNECTION       0x10
+#define RH_C_PORT_ENABLE           0x11
+#define RH_C_PORT_SUSPEND          0x12
+#define RH_C_PORT_OVER_CURRENT     0x13
+#define RH_C_PORT_RESET            0x14
+
+/* Hub features */
+#define RH_C_HUB_LOCAL_POWER       0x00
+#define RH_C_HUB_OVER_CURRENT      0x01
+
+#define RH_DEVICE_REMOTE_WAKEUP    0x00
+#define RH_ENDPOINT_STALL          0x01
+
+#define RH_ACK                     0x01
+#define RH_REQ_ERR                 -1
+#define RH_NACK                    0x00
+
+#endif /* _ETHERNAT_ISP116X_H */
diff --git a/FireBee/trunk/usb/store/host/netusbee/isp116x-hcd.c b/FireBee/trunk/usb/store/host/netusbee/isp116x-hcd.c
new file mode 100644
index 0000000..c26e6e1
--- /dev/null
+++ b/FireBee/trunk/usb/store/host/netusbee/isp116x-hcd.c
@@ -0,0 +1,1561 @@
+/*
+ * Modified for Atari-NetUSBee by David Gálvez 2010
+ *
+ * ISP116x HCD (Host Controller Driver) for u-boot.
+ *
+ * Copyright (C) 2006-2007 Rodolfo Giometti <giometti@linux.it>
+ * Copyright (C) 2006-2007 Eurotech S.p.A. <info@eurotech.it>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ *
+ * Derived in part from the SL811 HCD driver "u-boot/drivers/usb/sl811_usb.c"
+ * (original copyright message follows):
+ *
+ *    (C) Copyright 2004
+ *    Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ *    This code is based on linux driver for sl811hs chip, source at
+ *    drivers/usb/host/sl811.c:
+ *
+ *    SL811 Host Controller Interface driver for USB.
+ *
+ *    Copyright (c) 2003/06, Courage Co., Ltd.
+ *
+ *    Based on:
+ *         1.uhci.c by Linus Torvalds, Johannes Erdfelt, Randy Dunlap,
+ *           Georg Acher, Deti Fliegl, Thomas Sailer, Roman Weissgaerber,
+ *           Adam Richter, Gregory P. Smith;
+ *         2.Original SL811 driver (hc_sl811.o) by Pei Liu <pbl@cypress.com>
+ *         3.Rewrited as sl811.o by Yin Aihua <yinah:couragetech.com.cn>
+ *
+ *    [[GNU/GPL disclaimer]]
+ *
+ * and in part from AU1x00 OHCI HCD driver "u-boot/cpu/mips/au1x00_usb_ohci.c"
+ * (original copyright message follows):
+ *
+ *    URB OHCI HCD (Host Controller Driver) for USB on the AU1x00.
+ *
+ *    (C) Copyright 2003
+ *    Gary Jennejohn, DENX Software Engineering <garyj@denx.de>
+ *
+ *    [[GNU/GPL disclaimer]]
+ *
+ *    Note: Part of this code has been derived from linux
+ */
+
+#include "../../config.h"
+#include "../../asm-m68k/io.h"
+#include "../../usb.h"
+#include "../../debug.h"
+
+void udelay (unsigned long usec);
+
+//extern void boot_printf (const char *fmt, ...);
+
+
+/*
+ * ISP116x chips require certain delays between accesses to its
+ * registers. The following timing options exist.
+ *
+ * 1. Configure your memory controller (the best)
+ * 2. Use ndelay (easiest, poorest). For that, enable the following macro.
+ *
+ * Value is in microseconds.
+ */
+#ifdef ISP116X_HCD_USE_UDELAY
+#define UDELAY		1
+#endif
+
+/*
+ * On some (slowly?) machines an extra delay after data packing into
+ * controller's FIFOs is required, * otherwise you may get the following
+ * error:
+ *
+ *   uboot> usb start
+ *   (Re)start USB...
+ *   USB:   scanning bus for devices... isp116x: isp116x_submit_job: CTL:TIMEOUT
+ *   isp116x: isp116x_submit_job: ****** FIFO not ready! ******
+ *
+ *         USB device not responding, giving up (status=4)
+ *         isp116x: isp116x_submit_job: ****** FIFO not empty! ******
+ *         isp116x: isp116x_submit_job: ****** FIFO not empty! ******
+ *         isp116x: isp116x_submit_job: ****** FIFO not empty! ******
+ *         3 USB Device(s) found
+ *                scanning bus for storage devices... 0 Storage Device(s) found
+ *
+ * Value is in milliseconds.
+ */
+#ifdef ISP116X_HCD_USE_EXTRA_DELAY
+#define EXTRA_DELAY	50
+#endif
+
+/*
+ * Enable the following defines if you wish enable extra debugging messages.
+ * Normal debug messages controlled from config.h.
+ */
+
+//#define TRACE		/* enable tracing code */
+//#define VERBOSE		/* verbose debugging messages */
+
+#include "isp116x.h"
+
+#define DRIVER_VERSION	"08 Jan 2007"
+static const char hcd_name[] = "isp116x-hcd";
+
+struct isp116x isp116x_dev;
+struct isp116x_platform_data isp116x_board;
+static int got_rhsc;		/* root hub status change */
+struct usb_device *devgone;	/* device which was disconnected */
+static int rh_devnum;		/* address of Root Hub endpoint */
+
+/* ------------------------------------------------------------------------- */
+
+#define ALIGN(x,a)	(((x)+(a)-1UL)&~((a)-1UL))
+#define min1_t(type,x,y)	\
+	({ type __x = (x); type __y = (y); __x < __y ? __x : __y; })
+
+/*Galvez: added to avoid shadow warnings */
+#define min2_t(type,x,y)	\
+	({ type __a = (x); type __b = (y); __a < __b ? __a : __b; })
+
+/* ------------------------------------------------------------------------- */
+
+
+static int isp116x_reset(struct isp116x *isp116x);
+
+/* --- Debugging functions ------------------------------------------------- */
+
+#define isp116x_show_reg(d, r) {				\
+	if ((r) < 0x20) {					\
+		DEBUG_HOST("%-12s[%02x]: %08x", #r,			\
+			r, isp116x_read_reg32(d, r));		\
+	} else {						\
+		DEBUG_HOST("%-12s[%02x]:     %04x", #r,		\
+			r, isp116x_read_reg16(d, r));		\
+	}							\
+}
+
+#define isp116x_show_regs(d) {					\
+	isp116x_show_reg(d, HCREVISION);			\
+	isp116x_show_reg(d, HCCONTROL);				\
+	isp116x_show_reg(d, HCCMDSTAT);				\
+	isp116x_show_reg(d, HCINTSTAT);				\
+	isp116x_show_reg(d, HCINTENB);				\
+	isp116x_show_reg(d, HCFMINTVL);				\
+	isp116x_show_reg(d, HCFMREM);				\
+	isp116x_show_reg(d, HCFMNUM);				\
+	isp116x_show_reg(d, HCLSTHRESH);			\
+	isp116x_show_reg(d, HCRHDESCA);				\
+	isp116x_show_reg(d, HCRHDESCB);				\
+	isp116x_show_reg(d, HCRHSTATUS);			\
+	isp116x_show_reg(d, HCRHPORT1);				\
+	isp116x_show_reg(d, HCRHPORT2);				\
+	isp116x_show_reg(d, HCHWCFG);				\
+	isp116x_show_reg(d, HCDMACFG);				\
+	isp116x_show_reg(d, HCXFERCTR);				\
+	isp116x_show_reg(d, HCuPINT);				\
+	isp116x_show_reg(d, HCuPINTENB);			\
+	isp116x_show_reg(d, HCCHIPID);				\
+	isp116x_show_reg(d, HCSCRATCH);				\
+	isp116x_show_reg(d, HCITLBUFLEN);			\
+	isp116x_show_reg(d, HCATLBUFLEN);			\
+	isp116x_show_reg(d, HCBUFSTAT);				\
+	isp116x_show_reg(d, HCRDITL0LEN);			\
+	isp116x_show_reg(d, HCRDITL1LEN);			\
+}
+
+#if defined(TRACE)
+
+static int isp116x_get_current_frame_number(struct usb_device *usb_dev)
+{
+	struct isp116x *isp116x = &isp116x_dev;
+
+	return isp116x_read_reg32(isp116x, HCFMNUM);
+}
+
+static void dump_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+		     int len, char *str)
+{
+#if defined(VERBOSE)
+	int i;
+#endif
+	DEBUG_HOST("%s URB:[%4x] dev:%2ld,ep:%2ld-%c,type:%s,len:%d stat:%#lx",
+	    str,
+	    isp116x_get_current_frame_number(dev),
+	    usb_pipedevice(pipe),
+	    usb_pipeendpoint(pipe),
+	    usb_pipeout(pipe) ? 'O' : 'I',
+	    usb_pipetype(pipe) < 2 ?
+	    (usb_pipeint(pipe) ?
+	     "INTR" : "ISOC") :
+	    (usb_pipecontrol(pipe) ? "CTRL" : "BULK"), len, dev->status);
+#if defined(VERBOSE)
+	debug_init ("usb.log");
+	if (len > 0 && buffer) {
+		debug(__FILE__ ": data(%d):", len);
+		for (i = 0; i < 16 && i < len; i++)
+			debug(" %02x", ((__u8 *) buffer)[i]);
+		debug("%s\r\n", i < len ? "..." : "");
+	}
+	debug_exit ( );
+#endif
+}
+
+#define PTD_DIR_STR(ptd)  ({char __c;		\
+	switch(PTD_GET_DIR(ptd)){		\
+	case 0:  __c = 's'; break;		\
+	case 1:  __c = 'o'; break;		\
+	default: __c = 'i'; break;		\
+	}; __c;})
+
+/*
+  Dump PTD info. The code documents the format
+  perfectly, right :)
+*/
+static inline void dump_ptd(struct ptd *ptd)
+{
+#if defined(VERBOSE)
+	int k;
+#endif
+
+	DEBUG_HOST("PTD(ext) : cc:%x %d%c%d %d,%d,%d t:%x %x%x%x",
+	    PTD_GET_CC(ptd),
+	    PTD_GET_FA(ptd), PTD_DIR_STR(ptd), PTD_GET_EP(ptd),
+	    PTD_GET_COUNT(ptd), PTD_GET_LEN(ptd), PTD_GET_MPS(ptd),
+	    PTD_GET_TOGGLE(ptd),
+	    PTD_GET_ACTIVE(ptd), PTD_GET_SPD(ptd), PTD_GET_LAST(ptd));
+#if defined(VERBOSE)
+	debug_init ("usb.log");
+	debug("isp116x: %s: PTD(byte): ", __FUNCTION__);
+	for (k = 0; k < sizeof(struct ptd); ++k) {
+		debug("%02x ", ((u8 *) ptd)[k]);
+	}
+	debug("\n\r");
+	debug_exit ( );
+#endif
+}
+
+static inline void dump_ptd_data(struct ptd *ptd, u8 * buf, int type)
+{
+#if defined(VERBOSE)
+	int k;
+	
+	debug_init ("usb.log");
+	if (type == 0 /* 0ut data */ ) {
+		debug("isp116x: %s: out data: ", __FUNCTION__);
+		for (k = 0; k < PTD_GET_LEN(ptd); ++k) {
+			debug("%02x ", ((u8 *) buf)[k]);
+		}
+		debug("\n\r");
+	}
+	if (type == 1 /* 1n data */ ) {
+		debug("isp116x: %s: in data: ", __FUNCTION__);
+		for (k = 0; k < PTD_GET_COUNT(ptd); ++k) {
+			debug("%02x ", ((u8 *) buf)[k]);
+		}
+		debug("\n\r");
+	}
+	
+	debug_exit ( );
+	
+	if (PTD_GET_LAST(ptd)) {
+		DEBUG_HOST("--- last PTD ---");
+	}
+#endif
+}
+
+#else
+
+#define dump_msg(dev, pipe, buffer, len, str)			do { } while (0)
+#define dump_pkt(dev, pipe, buffer, len, setup, str, small)	do {} while (0)
+
+#define dump_ptd(ptd)			do {} while (0)
+#define dump_ptd_data(ptd, buf, type)	do {} while (0)
+
+#endif
+
+/* --- Virtual Root Hub ---------------------------------------------------- */
+
+/* Device descriptor */
+static __u8 root_hub_dev_des[] = {
+	0x12,			/*  __u8  bLength; */
+	0x01,			/*  __u8  bDescriptorType; Device */
+	0x10,			/*  __u16 bcdUSB; v1.1 */
+	0x01,
+	0x09,			/*  __u8  bDeviceClass; HUB_CLASSCODE */
+	0x00,			/*  __u8  bDeviceSubClass; */
+	0x00,			/*  __u8  bDeviceProtocol; */
+	0x08,			/*  __u8  bMaxPacketSize0; 8 Bytes */
+	0x00,			/*  __u16 idVendor; */
+	0x00,
+	0x00,			/*  __u16 idProduct; */
+	0x00,
+	0x00,			/*  __u16 bcdDevice; */
+	0x00,
+	0x00,			/*  __u8  iManufacturer; */
+	0x01,			/*  __u8  iProduct; */
+	0x00,			/*  __u8  iSerialNumber; */
+	0x01			/*  __u8  bNumConfigurations; */
+};
+
+/* Configuration descriptor */
+static __u8 root_hub_config_des[] = {
+	0x09,			/*  __u8  bLength; */
+	0x02,			/*  __u8  bDescriptorType; Configuration */
+	0x19,			/*  __u16 wTotalLength; */
+	0x00,
+	0x01,			/*  __u8  bNumInterfaces; */
+	0x01,			/*  __u8  bConfigurationValue; */
+	0x00,			/*  __u8  iConfiguration; */
+	0x40,			/*  __u8  bmAttributes;
+				   Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
+	0x00,			/*  __u8  MaxPower; */
+
+	/* interface */
+	0x09,			/*  __u8  if_bLength; */
+	0x04,			/*  __u8  if_bDescriptorType; Interface */
+	0x00,			/*  __u8  if_bInterfaceNumber; */
+	0x00,			/*  __u8  if_bAlternateSetting; */
+	0x01,			/*  __u8  if_bNumEndpoints; */
+	0x09,			/*  __u8  if_bInterfaceClass; HUB_CLASSCODE */
+	0x00,			/*  __u8  if_bInterfaceSubClass; */
+	0x00,			/*  __u8  if_bInterfaceProtocol; */
+	0x00,			/*  __u8  if_iInterface; */
+
+	/* endpoint */
+	0x07,			/*  __u8  ep_bLength; */
+	0x05,			/*  __u8  ep_bDescriptorType; Endpoint */
+	0x81,			/*  __u8  ep_bEndpointAddress; IN Endpoint 1 */
+	0x03,			/*  __u8  ep_bmAttributes; Interrupt */
+	0x00,			/*  __u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
+	0x02,
+	0xff			/*  __u8  ep_bInterval; 255 ms */
+};
+
+static unsigned char root_hub_str_index0[] = {
+	0x04,			/*  __u8  bLength; */
+	0x03,			/*  __u8  bDescriptorType; String-descriptor */
+	0x09,			/*  __u8  lang ID */
+	0x04,			/*  __u8  lang ID */
+};
+
+static unsigned char root_hub_str_index1[] = {
+	0x22,			/*  __u8  bLength; */
+	0x03,			/*  __u8  bDescriptorType; String-descriptor */
+	'I',			/*  __u8  Unicode */
+	0,			/*  __u8  Unicode */
+	'S',			/*  __u8  Unicode */
+	0,			/*  __u8  Unicode */
+	'P',			/*  __u8  Unicode */
+	0,			/*  __u8  Unicode */
+	'1',			/*  __u8  Unicode */
+	0,			/*  __u8  Unicode */
+	'1',			/*  __u8  Unicode */
+	0,			/*  __u8  Unicode */
+	'6',			/*  __u8  Unicode */
+	0,			/*  __u8  Unicode */
+	'x',			/*  __u8  Unicode */
+	0,			/*  __u8  Unicode */
+	' ',			/*  __u8  Unicode */
+	0,			/*  __u8  Unicode */
+	'R',			/*  __u8  Unicode */
+	0,			/*  __u8  Unicode */
+	'o',			/*  __u8  Unicode */
+	0,			/*  __u8  Unicode */
+	'o',			/*  __u8  Unicode */
+	0,			/*  __u8  Unicode */
+	't',			/*  __u8  Unicode */
+	0,			/*  __u8  Unicode */
+	' ',			/*  __u8  Unicode */
+	0,			/*  __u8  Unicode */
+	'H',			/*  __u8  Unicode */
+	0,			/*  __u8  Unicode */
+	'u',			/*  __u8  Unicode */
+	0,			/*  __u8  Unicode */
+	'b',			/*  __u8  Unicode */
+	0,			/*  __u8  Unicode */
+};
+
+/*
+ * Hub class-specific descriptor is constructed dynamically
+ */
+
+/* --- Virtual root hub management functions ------------------------------- */
+
+static int rh_check_port_status(struct isp116x *isp116x)
+{
+	u32 temp, ndp, i;
+	int res;
+
+	res = -1;
+	temp = isp116x_read_reg32(isp116x, HCRHSTATUS);
+	ndp = (temp & RH_A_NDP);
+	for (i = 0; i < ndp; i++) {
+		temp = isp116x_read_reg32(isp116x, HCRHPORT1 + i);
+		/* check for a device disconnect */
+		if (((temp & (RH_PS_PESC | RH_PS_CSC)) ==
+		     (RH_PS_PESC | RH_PS_CSC)) && ((temp & RH_PS_CCS) == 0)) {
+			res = i;
+			break;
+		}
+	}
+	return res;
+}
+
+/* --- HC management functions --------------------------------------------- */
+
+/* Write len bytes to fifo, pad till 32-bit boundary
+ */
+static void write_ptddata_to_fifo(struct isp116x *isp116x, void *buf, int len)
+{
+	u8 *dp = (u8 *) buf;
+	u16 *dp2 = (u16 *) buf;
+	u16 w;
+	int quot = len % 4;
+	
+/* For NetUSBee, take the raw_write out in write functions, here we don't
+ * like that NetUSBee swap the bytes for us, so we swap them before we send
+ * them, then the bytes will arrive to the USB device with the correct positions
+ */
+ 	if ((unsigned long)dp2 & 1) {
+	DEBUG_HOST("---not aligned ---");
+		/* not aligned */
+		for (; len > 1; len -= 2) {
+			w = *dp++;
+			w |= *dp++ << 8;
+			isp116x_write_data16(isp116x, w);
+		}
+		if (len)
+			isp116x_write_data16(isp116x, (u16) * dp);
+	} else {
+	DEBUG_HOST("---aligned ---");
+		/* aligned */
+		for (; len > 1; len -= 2)
+			isp116x_write_data16(isp116x, *dp2++);
+		if (len){DEBUG_HOST("write_data16\r\n"); /*GALVEZ: DEBUG */
+			isp116x_raw_write_data16(isp116x, 0xff & *((u8 *) dp2));}
+	}
+	if (quot == 1 || quot == 2)
+		isp116x_write_data16(isp116x, 0);
+}
+
+/* Read len bytes from fifo and then read till 32-bit boundary
+ */
+static void read_ptddata_from_fifo(struct isp116x *isp116x, void *buf, int len)
+{
+	u8 *dp = (u8 *) buf;
+	u16 *dp2 = (u16 *) buf;
+	u16 w;
+	int quot = len % 4;
+
+/* For NetUSBee, take the raw_read out from read functions, we want to swap the bytes
+   to read correct values because NetUSBee swaped the bytes by hardware before we read 
+   them */
+
+	if ((unsigned long)dp2 & 1) {
+		/* not aligned */
+		DEBUG_HOST("---not aligned ---");
+		for (; len > 1; len -= 2) {
+			w = isp116x_read_data16(isp116x);
+			*dp++ = w & 0xff;
+			*dp++ = (w >> 8) & 0xff;
+		}
+		if (len)
+			*dp = 0xff & isp116x_read_data16(isp116x);
+	} else {
+		/* aligned */
+		DEBUG_HOST("---aligned ---");
+		for (; len > 1; len -= 2)
+			*dp2++ = isp116x_read_data16(isp116x);
+		if (len)
+			*(u8 *) dp2 = 0xff & isp116x_raw_read_data16(isp116x);
+	}
+	if (quot == 1 || quot == 2)
+		isp116x_read_data16(isp116x);
+}
+
+/* Write PTD's and data for scheduled transfers into the fifo ram.
+ * Fifo must be empty and ready */
+static void pack_fifo(struct isp116x *isp116x, struct usb_device *dev,
+		      unsigned long pipe, struct ptd *ptd, int n, void *data,
+		      int len)
+{
+	int buflen = n * sizeof(struct ptd) + len;
+	int i, done;
+
+	DEBUG_HOST("--- pack buffer %p - %d bytes (fifo %d) ---", data, len, buflen);
+	
+	isp116x_write_reg16(isp116x, HCuPINT, HCuPINT_AIIEOT);
+	
+	isp116x_write_reg16(isp116x, HCXFERCTR, buflen);
+	isp116x_write_addr(isp116x, HCATLPORT | ISP116x_WRITE_OFFSET);
+
+	done = 0;
+	for (i = 0; i < n; i++) {
+		DEBUG_HOST("i=%d - done=%d - len=%d", i, done, PTD_GET_LEN(&ptd[i]));
+
+/* For NetUSBee, use raw_write to don't swap bytes */
+		dump_ptd(&ptd[i]);
+		isp116x_raw_write_data16(isp116x, ptd[i].count);
+		isp116x_raw_write_data16(isp116x, ptd[i].mps);
+		isp116x_raw_write_data16(isp116x, ptd[i].len);
+		isp116x_raw_write_data16(isp116x, ptd[i].faddr);
+
+		dump_ptd_data(&ptd[i], (__u8 *) data + done, 0);
+
+		write_ptddata_to_fifo(isp116x,
+				      (__u8 *) data + done,
+				      PTD_GET_LEN(&ptd[i]));
+
+		done += PTD_GET_LEN(&ptd[i]);
+	}
+}
+
+/* Read the processed PTD's and data from fifo ram back to URBs' buffers.
+ * Fifo must be full and done */
+static int unpack_fifo(struct isp116x *isp116x, struct usb_device *dev,
+		       unsigned long pipe, struct ptd *ptd, int n, void *data,
+		       int len)
+{
+	int buflen = n * sizeof(struct ptd) + len;
+	int i, done, cc, ret;
+
+	isp116x_write_reg16(isp116x, HCuPINT, HCuPINT_AIIEOT);
+	isp116x_write_reg16(isp116x, HCXFERCTR, buflen);
+	isp116x_write_addr(isp116x, HCATLPORT);
+
+	ret = TD_CC_NOERROR;
+	done = 0;
+	for (i = 0; i < n; i++) {
+		/* Galvez: DEBUG */
+//		DEBUG_HOST("i=%d - done=%d - len=%d", i, done, PTD_GET_LEN(&ptd[i]));
+		DEBUG_HOST("i=%d n=%d - done=%d - len= %d ptd_len=%d\n\r", i,n, done, len, PTD_GET_LEN(&ptd[i]));
+		/*****************/
+		
+	/* For NetUSBee, use raw_read to don't swap bytes */
+		ptd[i].count = isp116x_raw_read_data16(isp116x);
+		ptd[i].mps = isp116x_raw_read_data16(isp116x);
+		ptd[i].len = isp116x_raw_read_data16(isp116x);
+		ptd[i].faddr = isp116x_raw_read_data16(isp116x);
+		dump_ptd(&ptd[i]);
+		
+		/* when cc is 15 the data has not being touch by the HC
+		 * so we have to read all to empty completly the buffer
+		 */
+//		if ( PTD_GET_COUNT(ptd) != 0 || PTD_GET_CC(ptd) == 15 )
+			read_ptddata_from_fifo(isp116x,
+					       (__u8 *) data + done,
+					       PTD_GET_LEN(&ptd[i]));
+		dump_ptd_data(&ptd[i], (__u8 *) data + done, 1);
+
+		done += PTD_GET_LEN(&ptd[i]);
+	
+		cc = PTD_GET_CC(&ptd[i]);
+	
+		/* Data underrun means basically that we had more buffer space than
+		 * the function had data. It is perfectly normal but upper levels have
+		 * to know how much we actually transferred.
+		 */
+		if (cc == TD_NOTACCESSED ||
+				(cc != TD_CC_NOERROR && (ret == TD_CC_NOERROR || ret == TD_DATAUNDERRUN)))
+			ret = cc;
+	}
+
+	DEBUG_HOST("--- unpack buffer %p - %d bytes (fifo %d) count: %d---\n", data, len, buflen, PTD_GET_COUNT(ptd));
+
+	return ret;
+}
+
+/* Interrupt handling
+ */
+static int isp116x_interrupt(struct isp116x *isp116x)
+{
+	u16 irqstat;
+	u32 intstat;
+	int ret = 0;
+
+	isp116x_write_reg16(isp116x, HCuPINTENB, 0);
+	irqstat = isp116x_read_reg16(isp116x, HCuPINT);
+	isp116x_write_reg16(isp116x, HCuPINT, irqstat);
+	DEBUG_HOST(">>>>>> irqstat %x <<<<<<", irqstat);
+	
+	if (irqstat & HCuPINT_ATL) {
+		DEBUG_HOST(">>>>>> HCuPINT_ATL <<<<<<");
+		udelay(500);
+		ret = 1;
+	}
+
+	if (irqstat & HCuPINT_OPR) {
+		intstat = isp116x_read_reg32(isp116x, HCINTSTAT);
+		isp116x_write_reg32(isp116x, HCINTSTAT, intstat);
+		DEBUG_HOST(">>>>>> HCuPINT_OPR %x <<<<<<", intstat);
+
+		if (intstat & HCINT_UE) {
+			ERR("unrecoverable error, controller disabled");
+
+			/* FIXME: be optimistic, hope that bug won't repeat
+			 * often. Make some non-interrupt context restart the
+			 * controller. Count and limit the retries though;
+			 * either hardware or software errors can go forever...
+			 */
+			isp116x_reset(isp116x);
+			ret = -1;
+			return -1;
+		}
+
+		if (intstat & HCINT_RHSC) {
+			got_rhsc = 1;
+			ret = 1;
+			/* When root hub or any of its ports is going
+			   to come out of suspend, it may take more
+			   than 10ms for status bits to stabilize. */
+			wait_ms(20);
+		}
+
+		if (intstat & HCINT_SO) {
+			ERR("schedule overrun");
+			ret = -1;
+		}
+
+		irqstat &= ~HCuPINT_OPR;
+	}
+
+	return ret;
+}
+
+/* With one PTD we can transfer almost 1K in one go;
+ * HC does the splitting into endpoint digestible transactions
+ */
+struct ptd ptd[1];
+
+static inline int max_transfer_len(struct usb_device *dev, unsigned long pipe)
+{
+	unsigned mpck = usb_maxpacket(dev, pipe);
+
+	/* One PTD can transfer 1023 bytes but try to always
+	 * transfer multiples of endpoint buffer size
+	 */
+	return 1023 / mpck * mpck;
+}
+
+/* Do an USB transfer
+ */
+static int isp116x_submit_job(struct usb_device *dev, unsigned long pipe,
+			      int dir, void *buffer, int len)
+{
+	struct isp116x *isp116x = &isp116x_dev;
+	int type = usb_pipetype(pipe);
+	int epnum = usb_pipeendpoint(pipe);
+	int max = usb_maxpacket(dev, pipe);
+	int dir_out = usb_pipeout(pipe);
+	int speed_low = usb_pipeslow(pipe);
+	int i, done = 0, stat, timeout, cc;
+
+	/* 500 frames or 0.5s timeout when function is busy and NAKs transactions for a while */
+	int retries = 500;
+
+
+	DEBUG_HOST("------------------------------------------------");
+	dump_msg(dev, pipe, buffer, len, "SUBMIT");
+	DEBUG_HOST("------------------------------------------------");
+	
+	if (len >= 1024) {
+		ERR("Too big job");
+		dev->status = USB_ST_CRC_ERR;
+		return -1;
+	}
+
+	if (isp116x->disabled) {
+		ERR("EPIPE");
+		dev->status = USB_ST_CRC_ERR;
+		return -1;
+	}
+
+	/* device pulled? Shortcut the action. */
+	if (devgone == dev) {
+		ERR("ENODEV");
+		dev->status = USB_ST_CRC_ERR;
+		return USB_ST_CRC_ERR;
+	}
+
+	if (!max) {
+		ERR("pipesize for pipe %lx is zero", pipe);
+		dev->status = USB_ST_CRC_ERR;
+		return -1;
+	}
+
+	if (type == PIPE_ISOCHRONOUS) {
+		ERR("isochronous transfers not supported");
+		dev->status = USB_ST_CRC_ERR;
+		return -1;
+	}
+	
+	/* FIFO not empty? */
+	if (isp116x_read_reg16(isp116x, HCBUFSTAT) & HCBUFSTAT_ATL_FULL) {
+		DEBUG_HOST("****** FIFO not empty! ******");
+		printf("****** FIFO not empty! ******\n\r");
+		dev->status = USB_ST_BUF_ERR;
+		return -1;
+	}
+
+retry:
+	isp116x_write_reg32(isp116x, HCINTSTAT, 0xff);
+	/* Prepare the PTD data */
+	ptd->count = PTD_CC_MSK | PTD_ACTIVE_MSK |
+		PTD_TOGGLE(usb_gettoggle(dev, epnum, dir_out));
+	ptd->mps = PTD_MPS(max) | PTD_SPD(speed_low) | PTD_EP(epnum) | PTD_LAST_MSK;
+	ptd->len = PTD_LEN(len) | PTD_DIR(dir);
+	ptd->faddr = PTD_FA(usb_pipedevice(pipe));
+
+	
+retry_same:
+
+	/* FIFO not empty? */ /* GALVEZ: DEBUG */
+	if (isp116x_read_reg16(isp116x, HCBUFSTAT) & HCBUFSTAT_ATL_FULL) {
+		DEBUG_HOST("****** FIFO not empty! ******");
+		printf("****** FIFO not empty! ******\n\r");
+//		dev->status = USB_ST_BUF_ERR;
+//		return -1;
+	}
+
+	/* Pack data into FIFO ram */
+	pack_fifo(isp116x, dev, pipe, ptd, 1, buffer, len);
+
+#ifdef EXTRA_DELAY
+	wait_ms(EXTRA_DELAY);
+#endif
+
+	/* Start the data transfer */
+
+	/* Allow more time for a BULK device to react - some are slow */
+	if (usb_pipebulk(pipe))
+		timeout = 5000; /* Galvez: default = 5000 */
+	else
+		timeout = 1000; /* Galvez : netusbee : default = 100 */
+
+	/* Wait for it to complete */
+	for (;;) {
+		/* Check whether the controller is done */
+		stat = isp116x_interrupt(isp116x);
+
+		if (stat < 0) {
+			dev->status = USB_ST_CRC_ERR;
+			break;
+		}
+		if (stat > 0)
+			break;
+
+		/* Check the timeout */
+		if (--timeout)
+			udelay(1);
+		else {
+			ERR("CTL:TIMEOUT ");
+			printf("CTL:TIMEOUT ");
+			stat = USB_ST_CRC_ERR;
+			break;
+		}
+	}
+
+	/* We got an Root Hub Status Change interrupt */
+	if (got_rhsc) {
+		isp116x_show_regs(isp116x);
+
+		got_rhsc = 0;
+
+		/* Abuse timeout */
+		timeout = rh_check_port_status(isp116x);
+		if (timeout >= 0) {
+			/*
+			 * FIXME! NOTE! AAAARGH!
+			 * This is potentially dangerous because it assumes
+			 * that only one device is ever plugged in!
+			 */
+			devgone = dev;
+		}
+	}
+
+
+	/* Ok, now we can read transfer status */
+
+	/* FIFO not ready? */
+	if (!(isp116x_read_reg16(isp116x, HCBUFSTAT) & HCBUFSTAT_ATL_DONE)) {
+		DEBUG_HOST("****** FIFO not ready! ******");
+		printf("****** FIFO not ready! ******\n\r");
+		dev->status = USB_ST_BUF_ERR;
+		return -1;
+	}
+	
+	
+	/* Unpack data from FIFO ram */
+	cc = unpack_fifo(isp116x, dev, pipe, ptd, 1, buffer, len);
+
+	i = PTD_GET_COUNT(ptd);
+	done += i;
+	buffer += i;
+	len -= i;
+	
+	
+	/* There was some kind of real problem; Prepare the PTD again
+	 * and retry from the failed transaction on
+	 */
+	if (cc && cc != TD_NOTACCESSED && cc != TD_DATAUNDERRUN) {
+	DEBUG_HOST("PROBLEM cc: %d", cc);
+		if (retries >= 100) {
+			retries -= 100;
+			/* The chip will have toggled the toggle bit for the failed
+			 * transaction too. We have to toggle it back.
+			 */
+			usb_settoggle(dev, epnum, dir_out, !PTD_GET_TOGGLE(ptd));
+			goto retry;
+		}
+	}
+	/* "Normal" errors; TD_NOTACCESSED would mean in effect that the function have NAKed
+	 * the transactions from the first on for the whole frame. It may be busy and we retry
+	 * with the same PTD. PTD_ACTIVE (and not TD_NOTACCESSED) would mean that some of the
+	 * PTD didn't make it because the function was busy or the frame ended before the PTD
+	 * finished. We prepare the rest of the data and try again.
+	 */
+	else if ( cc == TD_NOTACCESSED ||  PTD_GET_ACTIVE(ptd) ||  ( cc != TD_DATAUNDERRUN && PTD_GET_COUNT(ptd) < PTD_GET_LEN(ptd))) {
+		DEBUG_HOST("NORMAL ERROR");
+		if (retries) {
+			--retries;
+			if (cc == TD_NOTACCESSED && PTD_GET_ACTIVE(ptd) && !PTD_GET_COUNT(ptd)) {
+				goto retry_same;
+			}
+			usb_settoggle(dev, epnum, dir_out, PTD_GET_TOGGLE(ptd));
+			goto retry;
+		}
+	}
+
+
+	if (cc != TD_CC_NOERROR && cc != TD_DATAUNDERRUN) {
+		DEBUG_HOST("****** completition code error %x ******", cc);
+		switch (cc) {
+		case TD_CC_BITSTUFFING:
+			dev->status = USB_ST_BIT_ERR;
+			break;
+		case TD_CC_STALL:
+			dev->status = USB_ST_STALLED;
+			break;
+		case TD_BUFFEROVERRUN:
+		case TD_BUFFERUNDERRUN:
+			dev->status = USB_ST_BUF_ERR;
+			break;
+		default:
+			dev->status = USB_ST_CRC_ERR;
+		}
+		return -cc;
+	}
+	else usb_settoggle(dev, epnum, dir_out, PTD_GET_TOGGLE(ptd));
+
+	dump_msg(dev, pipe, buffer, len, "SUBMIT(ret)");
+
+	dev->status = 0;
+	return done;
+}
+
+/* Adapted from au1x00_usb_ohci.c
+ */
+static int isp116x_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
+				 void *buffer, int transfer_len,
+				 struct devrequest *cmd)
+{
+	struct isp116x *isp116x = &isp116x_dev;
+	u32 tmp = 0;
+
+	int leni = transfer_len;
+	int len = 0;
+	int stat = 0;
+	u32 datab[4];
+	u8 *data_buf = (u8 *) datab;
+	u16 bmRType_bReq;
+	u16 wValue;
+	u16 wIndex;
+	u16 wLength;
+
+	if (usb_pipeint(pipe)) {
+		INFO("Root-Hub submit IRQ: NOT implemented");
+		return 0;
+	}
+
+	bmRType_bReq = cmd->requesttype | (cmd->request << 8);
+	wValue = swap_16(cmd->value);
+	wIndex = swap_16(cmd->index);
+	wLength = swap_16(cmd->length);
+
+	DEBUG_HOST("--- HUB ----------------------------------------");
+	DEBUG_HOST("submit rh urb, req=%x val=%#x index=%#x len=%d",
+	    bmRType_bReq, wValue, wIndex, wLength);
+	dump_msg(dev, pipe, buffer, transfer_len, "RH");
+	DEBUG_HOST("------------------------------------------------");
+
+	switch (bmRType_bReq) {
+	case RH_GET_STATUS:
+		DEBUG_HOST("RH_GET_STATUS");
+
+		*(__u16 *) data_buf = swap_16(1);
+		len = 2;
+		break;
+
+	case RH_GET_STATUS | RH_INTERFACE:
+		DEBUG_HOST("RH_GET_STATUS | RH_INTERFACE");
+
+		*(__u16 *) data_buf = swap_16(0);
+		len = 2;
+		break;
+
+	case RH_GET_STATUS | RH_ENDPOINT:
+		DEBUG_HOST("RH_GET_STATUS | RH_ENDPOINT");
+
+		*(__u16 *) data_buf = swap_16(0);
+		len = 2;
+		break;
+
+	case RH_GET_STATUS | RH_CLASS:
+		DEBUG_HOST("RH_GET_STATUS | RH_CLASS");
+
+		tmp = isp116x_read_reg32(isp116x, HCRHSTATUS);
+
+		*(__u32 *) data_buf = swap_32(tmp & ~(RH_HS_CRWE | RH_HS_DRWE));
+		len = 4;
+		break;
+
+	case RH_GET_STATUS | RH_OTHER | RH_CLASS:
+		DEBUG_HOST("RH_GET_STATUS | RH_OTHER | RH_CLASS");
+
+		tmp = isp116x_read_reg32(isp116x, HCRHPORT1 + wIndex - 1);
+		*(__u32 *) data_buf = swap_32(tmp);
+		isp116x_show_regs(isp116x);
+		len = 4;
+		break;
+
+	case RH_CLEAR_FEATURE | RH_ENDPOINT:
+		DEBUG_HOST("RH_CLEAR_FEATURE | RH_ENDPOINT");
+
+		switch (wValue) {
+		case RH_ENDPOINT_STALL:
+			DEBUG_HOST("C_HUB_ENDPOINT_STALL");
+			len = 0;
+			break;
+		}
+		break;
+
+	case RH_CLEAR_FEATURE | RH_CLASS:
+		DEBUG_HOST("RH_CLEAR_FEATURE | RH_CLASS");
+
+		switch (wValue) {
+		case RH_C_HUB_LOCAL_POWER:
+			DEBUG_HOST("C_HUB_LOCAL_POWER");
+			len = 0;
+			break;
+
+		case RH_C_HUB_OVER_CURRENT:
+			DEBUG_HOST("C_HUB_OVER_CURRENT");
+			isp116x_write_reg32(isp116x, HCRHSTATUS, RH_HS_OCIC);
+			len = 0;
+			break;
+		}
+		break;
+
+	case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
+		DEBUG_HOST("RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS");
+
+		switch (wValue) {
+		case RH_PORT_ENABLE:
+			isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
+					    RH_PS_CCS);
+			len = 0;
+			break;
+
+		case RH_PORT_SUSPEND:
+			isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
+					    RH_PS_POCI);
+			len = 0;
+			break;
+
+		case RH_PORT_POWER:
+			isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
+					    RH_PS_LSDA);
+			len = 0;
+			break;
+
+		case RH_C_PORT_CONNECTION:
+			isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
+					    RH_PS_CSC);
+			len = 0;
+			break;
+
+		case RH_C_PORT_ENABLE:
+			isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
+					    RH_PS_PESC);
+			len = 0;
+			break;
+
+		case RH_C_PORT_SUSPEND:
+			isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
+					    RH_PS_PSSC);
+			len = 0;
+			break;
+
+		case RH_C_PORT_OVER_CURRENT:
+			isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
+					    RH_PS_POCI);
+			len = 0;
+			break;
+
+		case RH_C_PORT_RESET:
+			isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
+					    RH_PS_PRSC);
+			len = 0;
+			break;
+
+		default:
+			ERR("invalid wValue");
+			stat = USB_ST_STALLED;
+		}
+
+		isp116x_show_regs(isp116x);
+
+		break;
+
+	case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
+		DEBUG_HOST("RH_SET_FEATURE | RH_OTHER | RH_CLASS");
+
+		switch (wValue) {
+		case RH_PORT_SUSPEND:
+			isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
+					    RH_PS_PSS);
+			len = 0;
+			break;
+
+		case RH_PORT_RESET:
+			/* Spin until any current reset finishes */
+			while (1) {
+				tmp =
+				    isp116x_read_reg32(isp116x,
+						       HCRHPORT1 + wIndex - 1);
+				if (!(tmp & RH_PS_PRS))
+					break;
+				wait_ms(1);
+			}
+			isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
+					    RH_PS_PRS);
+			wait_ms(10);
+
+			len = 0;
+			break;
+
+		case RH_PORT_POWER:
+			isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
+					    RH_PS_PPS);
+			len = 0;
+			break;
+
+		case RH_PORT_ENABLE:
+			isp116x_write_reg32(isp116x, HCRHPORT1 + wIndex - 1,
+					    RH_PS_PES);
+			len = 0;
+			break;
+
+		default:
+			ERR("invalid wValue");
+			stat = USB_ST_STALLED;
+		}
+
+		isp116x_show_regs(isp116x);
+
+		break;
+
+	case RH_SET_ADDRESS:
+		DEBUG_HOST("RH_SET_ADDRESS");
+
+		rh_devnum = wValue;
+		len = 0;
+		break;
+
+	case RH_GET_DESCRIPTOR:
+		DEBUG_HOST("RH_GET_DESCRIPTOR: %x, %d", wValue, wLength);
+
+		switch (wValue) {
+		case (USB_DT_DEVICE << 8):	/* device descriptor */
+			len = min1_t(unsigned int,
+				    leni, min2_t(unsigned int,
+						sizeof(root_hub_dev_des),
+						wLength));
+			data_buf = root_hub_dev_des;
+			break;
+
+		case (USB_DT_CONFIG << 8):	/* configuration descriptor */
+			len = min1_t(unsigned int,
+				    leni, min2_t(unsigned int,
+						sizeof(root_hub_config_des),
+						wLength));
+			data_buf = root_hub_config_des;
+			break;
+
+		case ((USB_DT_STRING << 8) | 0x00):	/* string 0 descriptors */
+			len = min1_t(unsigned int,
+				    leni, min2_t(unsigned int,
+						sizeof(root_hub_str_index0),
+						wLength));
+			data_buf = root_hub_str_index0;
+			break;
+
+		case ((USB_DT_STRING << 8) | 0x01):	/* string 1 descriptors */
+			len = min1_t(unsigned int,
+				    leni, min2_t(unsigned int,
+						sizeof(root_hub_str_index1),
+						wLength));
+			data_buf = root_hub_str_index1;
+			break;
+
+		default:
+			ERR("invalid wValue");
+			stat = USB_ST_STALLED;
+		}
+
+		break;
+
+	case RH_GET_DESCRIPTOR | RH_CLASS:
+		DEBUG_HOST("RH_GET_DESCRIPTOR | RH_CLASS");
+
+		tmp = isp116x_read_reg32(isp116x, HCRHDESCA);
+
+		data_buf[0] = 0x09;	/* min length; */
+		data_buf[1] = 0x29;
+		data_buf[2] = tmp & RH_A_NDP;
+		data_buf[3] = 0;
+		if (tmp & RH_A_PSM)	/* per-port power switching? */
+			data_buf[3] |= 0x01;
+		if (tmp & RH_A_NOCP)	/* no overcurrent reporting? */
+			data_buf[3] |= 0x10;
+		else if (tmp & RH_A_OCPM)	/* per-port overcurrent rep? */
+			data_buf[3] |= 0x08;
+
+		/* Corresponds to data_buf[4-7] */
+		datab[1] = 0;
+		data_buf[5] = (tmp & RH_A_POTPGT) >> 24;
+
+		tmp = isp116x_read_reg32(isp116x, HCRHDESCB);
+
+		data_buf[7] = tmp & RH_B_DR;
+		if (data_buf[2] < 7)
+			data_buf[8] = 0xff;
+		else {
+			data_buf[0] += 2;
+			data_buf[8] = (tmp & RH_B_DR) >> 8;
+			data_buf[10] = data_buf[9] = 0xff;
+		}
+
+		len = min1_t(unsigned int, leni,
+			    min2_t(unsigned int, data_buf[0], wLength));
+		break;
+
+	case RH_GET_CONFIGURATION:
+		DEBUG_HOST("RH_GET_CONFIGURATION");
+
+		*(__u8 *) data_buf = 0x01;
+		len = 1;
+		break;
+
+	case RH_SET_CONFIGURATION:
+		DEBUG_HOST("RH_SET_CONFIGURATION");
+
+		isp116x_write_reg32(isp116x, HCRHSTATUS, RH_HS_LPSC);
+		len = 0;
+		break;
+
+	default:
+		ERR("*** *** *** unsupported root hub command *** *** ***");
+		stat = USB_ST_STALLED;
+	}
+
+	len = min1_t(int, len, leni);
+	if (buffer != data_buf)
+		memcpy(buffer, data_buf, len);
+
+	dev->act_len = len;
+	dev->status = stat;
+	DEBUG_HOST("dev act_len %d, status %ld", dev->act_len, dev->status);
+
+	dump_msg(dev, pipe, buffer, transfer_len, "RH(ret)");
+
+	return stat;
+}
+
+/* --- Transfer functions -------------------------------------------------- */
+
+int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+		   int len, int interval)
+{
+	DEBUG_HOST("dev=%p pipe=%#lx buf=%p size=%d int=%d",
+	    dev, pipe, buffer, len, interval);
+
+	return -1;
+}
+
+int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+		       int len, struct devrequest *setup)
+{
+	int devnum = usb_pipedevice(pipe);
+	int epnum = usb_pipeendpoint(pipe);
+	int max = max_transfer_len(dev, pipe);
+	int dir_in = usb_pipein(pipe);
+	int done, ret;
+	
+	
+	/* Control message is for the HUB? */
+	if (devnum == rh_devnum)
+		return isp116x_submit_rh_msg(dev, pipe, buffer, len, setup);
+
+	/* Ok, no HUB message so send the message to the device */
+
+	/* Setup phase */
+	DEBUG_HOST("--- SETUP PHASE --------------------------------");
+	usb_settoggle(dev, epnum, 1, 0);
+	
+	
+	ret = isp116x_submit_job(dev, pipe,
+				PTD_DIR_SETUP,
+				 setup, sizeof(struct devrequest));
+	if (ret < 0) {
+		DEBUG_HOST("control setup phase error (ret = %d", ret);
+		return -1;
+	}
+
+	/* Data phase */
+	DEBUG_HOST("--- DATA PHASE ---------------------------------");
+	done = 0;
+	usb_settoggle(dev, epnum, !dir_in, 1);
+	while (done < len) {
+		ret = isp116x_submit_job(dev, pipe,
+					 dir_in ? PTD_DIR_IN : PTD_DIR_OUT,
+					 (__u8 *) buffer + done,
+					 max > len - done ? len - done : max);
+		if (ret < 0) {
+			DEBUG_HOST("control data phase error (ret = %d)", ret);
+			return -1;
+		}
+		done += ret;
+
+		if (dir_in && ret < max)	/* short packet */
+			break;
+	}
+
+	/* Status phase */
+	DEBUG_HOST("--- STATUS PHASE -------------------------------");
+	usb_settoggle(dev, epnum, !dir_in, 1);
+	ret = isp116x_submit_job(dev, pipe,
+				 !dir_in ? PTD_DIR_IN : PTD_DIR_OUT, NULL, 0);
+	if (ret < 0) {
+		DEBUG_HOST("control status phase error (ret = %d", ret);
+		return -1;
+	}
+
+	dev->act_len = done;
+
+	dump_msg(dev, pipe, buffer, len, "DEV(ret)");
+
+	return done;
+}
+
+int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+		    int len)
+{
+	int dir_out = usb_pipeout(pipe);
+	int max = max_transfer_len(dev, pipe);
+	int done, ret;
+	
+	DEBUG_HOST("--- BULK ---------------------------------------");
+	DEBUG_HOST("dev=%ld pipe=%ld buf=%p size=%d dir_out=%d",
+	    usb_pipedevice(pipe), usb_pipeendpoint(pipe), buffer, len, dir_out);
+
+	done = 0;
+	while (done < len) {
+
+		ret = isp116x_submit_job(dev, pipe,
+					 !dir_out ? PTD_DIR_IN : PTD_DIR_OUT,
+					 (__u8 *) buffer + done,
+					 max > len - done ? len - done : max);
+
+		if (ret < 0) {
+			DEBUG_HOST("error on bulk message (ret = %d)", ret);
+			return -1;
+		}
+
+		done += ret;
+
+		if (!dir_out && ret < max)	/* short packet */
+			break;
+	}
+
+	dev->act_len = done;
+
+	return 0;
+}
+
+/* --- Basic functions ----------------------------------------------------- */
+
+
+#if 0
+/* GALVEZ: Test function */
+static int GALVEZ_test_function( struct isp116x *isp116x )
+{
+	short res;
+
+	isp116x_write_reg16(isp116x, HCSCRATCH, 0x1234);
+	res = isp116x_read_reg16(isp116x, HCSCRATCH);	
+	ERR ("Scratch register read: %x\r\n",res);
+	return 0;
+
+}
+#endif
+
+static int isp116x_sw_reset(struct isp116x *isp116x)
+{
+	int retries = 15;
+	int ret = 0;
+
+	DEBUG_HOST("");
+
+	isp116x->disabled = 1;
+
+	isp116x_write_reg16(isp116x, HCSWRES, HCSWRES_MAGIC);
+	isp116x_write_reg32(isp116x, HCCMDSTAT, HCCMDSTAT_HCR);
+	
+	while (--retries) {
+		/* It usually resets within 1 ms */
+		/* GALVEZ: not enough for TOS, try 7 ms */
+		wait_ms(7);
+		if (!(isp116x_read_reg32(isp116x, HCCMDSTAT) & HCCMDSTAT_HCR))
+			break;
+	}
+	
+	if (!retries) {
+		ERR("software reset timeout");
+		ret = -1;
+	}
+
+#if 0
+	/* GALVEZ: DEBUG SOFTWARE RESET */
+		
+	retries = 5000;
+	
+	while (--retries){
+		if ((isp116x_read_reg32(isp116x, HCCMDSTAT) & HCCMDSTAT_HCR)) {
+			INFO ("HCR: 1 retries: %d\n\r",retries);
+		}
+	}
+#endif /* END DEBUG */
+
+	return ret;
+}
+
+static int isp116x_reset(struct isp116x *isp116x)
+{
+	unsigned long t;
+	u16 clkrdy = 0;
+	int ret, timeout = 1000;/* ms
+				* Galvez: 15 ms sometimes isn't enough,
+				* for NetUSBee under TOS ??????? increased to 150 ms 
+				*/ 
+
+	DEBUG_HOST("");
+
+	ret = isp116x_sw_reset(isp116x);
+
+	if (ret)
+		return ret;
+
+	for (t = 0; t < timeout; t++) {
+		clkrdy = isp116x_read_reg16(isp116x, HCuPINT) & HCuPINT_CLKRDY;
+		if (clkrdy)
+			break;
+		wait_ms(1);
+	}
+	if (!clkrdy) {
+		ERR("clock not ready after %dms", timeout);
+		/* After sw_reset the clock won't report to be ready, if
+		   H_WAKEUP pin is high. */
+		ERR("please make sure that the H_WAKEUP pin is pulled low!");
+		ret = -1;
+	}
+	return ret;
+}
+
+static void isp116x_stop(struct isp116x *isp116x)
+{
+	u32 val;
+	
+	DEBUG_HOST("");
+	
+	isp116x_write_reg16(isp116x, HCuPINTENB, 0);
+
+	/* Switch off ports' power, some devices don't come up
+	   after next 'start' without this */
+	val = isp116x_read_reg32(isp116x, HCRHDESCA);
+	val &= ~(RH_A_NPS | RH_A_PSM);
+	isp116x_write_reg32(isp116x, HCRHDESCA, val);
+	isp116x_write_reg32(isp116x, HCRHSTATUS, RH_HS_LPS);
+	
+	isp116x_sw_reset(isp116x);
+}
+
+/*
+ *  Configure the chip. The chip must be successfully reset by now.
+ */
+static int isp116x_start(struct isp116x *isp116x)
+{
+	struct isp116x_platform_data *board = isp116x->board;
+	u32 val;
+	
+	DEBUG_HOST("");
+
+	/* Clear interrupt status and disable all interrupt sources */
+	isp116x_write_reg16(isp116x, HCuPINT, 0xff);
+	isp116x_write_reg16(isp116x, HCuPINTENB, 0);
+
+	isp116x_write_reg16(isp116x, HCITLBUFLEN, ISP116x_ITL_BUFSIZE);
+	isp116x_write_reg16(isp116x, HCATLBUFLEN, ISP116x_ATL_BUFSIZE);
+
+	/* Hardware configuration */
+	val = HCHWCFG_DBWIDTH(1);
+
+	if (board->sel15Kres)
+		val |= HCHWCFG_15KRSEL;
+	/* Remote wakeup won't work without working clock */
+	if (board->remote_wakeup_enable)
+		val |= HCHWCFG_CLKNOTSTOP;
+	if (board->oc_enable)
+		val |= HCHWCFG_ANALOG_OC;
+	isp116x_write_reg16(isp116x, HCHWCFG, val);
+
+
+	/* --- Root hub configuration */
+	val = (25 << 24) & RH_A_POTPGT;
+	/* AN10003_1.pdf recommends RH_A_NPS (no power switching) to
+	   be always set. Yet, instead, we request individual port
+	   power switching. */
+	val |= RH_A_PSM;
+	/* Report overcurrent per port */
+	val |= RH_A_OCPM;
+	isp116x_write_reg32(isp116x, HCRHDESCA, val);
+	isp116x->rhdesca = isp116x_read_reg32(isp116x, HCRHDESCA);
+
+	val = RH_B_PPCM;
+	isp116x_write_reg32(isp116x, HCRHDESCB, val);
+	isp116x->rhdescb = isp116x_read_reg32(isp116x, HCRHDESCB);
+
+	val = 0;
+	if (board->remote_wakeup_enable)
+		val |= RH_HS_DRWE;
+	isp116x_write_reg32(isp116x, HCRHSTATUS, val);
+	isp116x->rhstatus = isp116x_read_reg32(isp116x, HCRHSTATUS);
+
+	isp116x_write_reg32(isp116x, HCFMINTVL, 0x27782edf);
+
+	/* Go operational */
+	val = HCCONTROL_USB_OPER;
+	if (board->remote_wakeup_enable)
+		val |= HCCONTROL_RWE;
+	isp116x_write_reg32(isp116x, HCCONTROL, val);
+
+	/* Disable ports to avoid race in device enumeration */
+	isp116x_write_reg32(isp116x, HCRHPORT1, RH_PS_CCS);
+	isp116x_write_reg32(isp116x, HCRHPORT2, RH_PS_CCS);
+
+	isp116x_show_regs(isp116x);
+
+	isp116x->disabled = 0;
+
+	return 0;
+}
+
+/* --- Init functions ------------------------------------------------------ */
+
+
+
+int isp116x_check_id(struct isp116x *isp116x)
+{
+	u16 val;
+
+	val = isp116x_read_reg16(isp116x, HCCHIPID);
+	DEBUG_HOST("chip ID: %04x", val);
+	printf ("chip ID: %04x", val);
+	
+	if ((val & HCCHIPID_MASK) != HCCHIPID_MAGIC) {
+		printf("invalid chip ID %04x", val);
+		return -1;
+	}
+
+	return 0;
+}
+
+
+int usb_lowlevel_init(void)
+{
+//	u16 val;
+
+	struct isp116x *isp116x = &isp116x_dev;
+
+	DEBUG_HOST("");
+
+	got_rhsc = rh_devnum = 0;
+
+	/* Init device registers addr */
+	isp116x->addr_reg = (u16 *) ISP116X_HCD_ADDR_BEE;
+	isp116x->data_reg = (u16 *) ISP116X_HCD_DATA_BEE;
+
+	/* Setup specific board settings */
+#ifdef ISP116X_HCD_SEL15kRES
+	isp116x_board.sel15Kres = 1;
+#endif
+#ifdef ISP116X_HCD_OC_ENABLE
+	isp116x_board.oc_enable = 1;
+#endif
+#ifdef ISP116X_HCD_REMOTE_WAKEUP_ENABLE
+	isp116x_board.remote_wakeup_enable = 1;
+#endif
+	isp116x->board = &isp116x_board;
+
+	/* Try to get ISP116x silicon chip ID */
+	if (  isp116x_check_id(isp116x) < 0)
+		return -1;
+	
+
+//	GALVEZ_test_function ( isp116x );	/* Gálvez: Testing writing to registers */
+
+	isp116x->disabled = 1;
+	isp116x->sleeping = 0;
+
+	isp116x_reset(isp116x);
+	isp116x_start(isp116x);
+
+	return 0;
+}
+
+int usb_lowlevel_stop(void)
+{
+	struct isp116x *isp116x = &isp116x_dev;
+
+	DEBUG_HOST("");
+
+	if (!isp116x->disabled)
+		isp116x_stop(isp116x);
+
+	return 0;
+}
diff --git a/FireBee/trunk/usb/store/host/netusbee/isp116x.h b/FireBee/trunk/usb/store/host/netusbee/isp116x.h
new file mode 100644
index 0000000..7d62865
--- /dev/null
+++ b/FireBee/trunk/usb/store/host/netusbee/isp116x.h
@@ -0,0 +1,596 @@
+/*
+ * Modified for Atari-NetUSBee by David Gálvez 2010
+ *
+ * ISP116x register declarations and HCD data structures
+ *
+ * Copyright (C) 2007 Rodolfo Giometti <giometti@linux.it>
+ * Copyright (C) 2007 Eurotech S.p.A. <info@eurotech.it>
+ * Copyright (C) 2005 Olav Kongas <ok@artecdesign.ee>
+ * Portions:
+ * Copyright (C) 2004 Lothar Wassmann
+ * Copyright (C) 2004 Psion Teklogix
+ * Copyright (C) 2004 David Brownell
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _NETUSBEE_ISP116X_H
+#define _NETUSBEE_ISP116X_H
+
+
+#define ERR(fmt, args...)	printf("isp116x: %s: " fmt "\n\r" , __FUNCTION__ , ## args)
+#define WARN(fmt, args...)	printf("isp116x: %s: " fmt "\n\r" , __FUNCTION__ , ## args)
+#define INFO(fmt, args...)	printf("isp116x: " fmt "\n\r" , ## args)
+
+/* ------------------------------------------------------------------------- */
+
+/* us of 1ms frame */
+#define  MAX_LOAD_LIMIT		850
+
+/* Full speed: max # of bytes to transfer for a single urb
+   at a time must be < 1024 && must be multiple of 64.
+   832 allows transfering 4kiB within 5 frames. */
+#define MAX_TRANSFER_SIZE_FULLSPEED	832
+
+/* Low speed: there is no reason to schedule in very big
+   chunks; often the requested long transfers are for
+   string descriptors containing short strings. */
+#define MAX_TRANSFER_SIZE_LOWSPEED	64
+
+/* Bytetime (us), a rough indication of how much time it
+   would take to transfer a byte of useful data over USB */
+#define BYTE_TIME_FULLSPEED	1
+#define BYTE_TIME_LOWSPEED	20
+
+/* Buffer sizes */
+#define ISP116x_BUF_SIZE	4096
+#define ISP116x_ITL_BUFSIZE	0
+#define ISP116x_ATL_BUFSIZE	((ISP116x_BUF_SIZE) - 2*(ISP116x_ITL_BUFSIZE))
+
+#define ISP116x_WRITE_OFFSET	0x80
+
+
+/* --- ISP116x address registers in Netusbee --------------------------------*/
+
+#define ISP116X_HCD_ADDR_BEE	0x00FBC000
+#define ISP116X_HCD_DATA_BEE	0x00FA0000
+
+
+/* --- ISP116x registers/bits ---------------------------------------------- */
+
+#define	HCREVISION	0x00
+#define	HCCONTROL	0x01
+#define		HCCONTROL_HCFS	(3 << 6)	/* host controller
+						   functional state */
+#define		HCCONTROL_USB_RESET	(0 << 6)
+#define		HCCONTROL_USB_RESUME	(1 << 6)
+#define		HCCONTROL_USB_OPER	(2 << 6)
+#define		HCCONTROL_USB_SUSPEND	(3 << 6)
+#define		HCCONTROL_RWC	(1 << 9)	/* remote wakeup connected */
+#define		HCCONTROL_RWE	(1 << 10)	/* remote wakeup enable */
+#define	HCCMDSTAT	0x02
+#define		HCCMDSTAT_HCR	(1 << 0)	/* host controller reset */
+#define		HCCMDSTAT_SOC	(3 << 16)	/* scheduling overrun count */
+#define	HCINTSTAT	0x03
+#define		HCINT_SO	(1 << 0)	/* scheduling overrun */
+#define		HCINT_WDH	(1 << 1)	/* writeback of done_head */
+#define		HCINT_SF	(1 << 2)	/* start frame */
+#define		HCINT_RD	(1 << 3)	/* resume detect */
+#define		HCINT_UE	(1 << 4)	/* unrecoverable error */
+#define		HCINT_FNO	(1 << 5)	/* frame number overflow */
+#define		HCINT_RHSC	(1 << 6)	/* root hub status change */
+#define		HCINT_OC	(1 << 30)	/* ownership change */
+#define		HCINT_MIE	(1 << 31)	/* master interrupt enable */
+#define	HCINTENB	0x04
+#define	HCINTDIS	0x05
+#define	HCFMINTVL	0x0d
+#define	HCFMREM		0x0e
+#define	HCFMNUM		0x0f
+#define	HCLSTHRESH	0x11
+#define	HCRHDESCA	0x12
+#define		RH_A_NDP	(0x3 << 0)	/* # downstream ports */
+#define		RH_A_PSM	(1 << 8)	/* power switching mode */
+#define		RH_A_NPS	(1 << 9)	/* no power switching */
+#define		RH_A_DT		(1 << 10)	/* device type (mbz) */
+#define		RH_A_OCPM	(1 << 11)	/* overcurrent protection
+						   mode */
+#define		RH_A_NOCP	(1 << 12)	/* no overcurrent protection */
+#define		RH_A_POTPGT	(0xff << 24)	/* power on -> power good
+						   time */
+#define	HCRHDESCB	0x13
+#define		RH_B_DR		(0xffff << 0)	/* device removable flags */
+#define		RH_B_PPCM	(0xffff << 16)	/* port power control mask */
+#define	HCRHSTATUS	0x14
+#define		RH_HS_LPS	(1 << 0)	/* local power status */
+#define		RH_HS_OCI	(1 << 1)	/* over current indicator */
+#define		RH_HS_DRWE	(1 << 15)	/* device remote wakeup
+						   enable */
+#define		RH_HS_LPSC	(1 << 16)	/* local power status change */
+#define		RH_HS_OCIC	(1 << 17)	/* over current indicator
+						   change */
+#define		RH_HS_CRWE	(1 << 31)	/* clear remote wakeup
+						   enable */
+#define	HCRHPORT1	0x15
+#define		RH_PS_CCS	(1 << 0)	/* current connect status */
+#define		RH_PS_PES	(1 << 1)	/* port enable status */
+#define		RH_PS_PSS	(1 << 2)	/* port suspend status */
+#define		RH_PS_POCI	(1 << 3)	/* port over current
+						   indicator */
+#define		RH_PS_PRS	(1 << 4)	/* port reset status */
+#define		RH_PS_PPS	(1 << 8)	/* port power status */
+#define		RH_PS_LSDA	(1 << 9)	/* low speed device attached */
+#define		RH_PS_CSC	(1 << 16)	/* connect status change */
+#define		RH_PS_PESC	(1 << 17)	/* port enable status change */
+#define		RH_PS_PSSC	(1 << 18)	/* port suspend status
+						   change */
+#define		RH_PS_OCIC	(1 << 19)	/* over current indicator
+						   change */
+#define		RH_PS_PRSC	(1 << 20)	/* port reset status change */
+#define		HCRHPORT_CLRMASK	(0x1f << 16)
+#define	HCRHPORT2	0x16
+#define	HCHWCFG		0x20
+#define		HCHWCFG_15KRSEL		(1 << 12)
+#define		HCHWCFG_CLKNOTSTOP	(1 << 11)
+#define		HCHWCFG_ANALOG_OC	(1 << 10)
+#define		HCHWCFG_DACK_MODE	(1 << 8)
+#define		HCHWCFG_EOT_POL		(1 << 7)
+#define		HCHWCFG_DACK_POL	(1 << 6)
+#define		HCHWCFG_DREQ_POL	(1 << 5)
+#define		HCHWCFG_DBWIDTH_MASK	(0x03 << 3)
+#define		HCHWCFG_DBWIDTH(n)	(((n) << 3) & HCHWCFG_DBWIDTH_MASK)
+#define		HCHWCFG_INT_POL		(1 << 2)
+#define		HCHWCFG_INT_TRIGGER	(1 << 1)
+#define		HCHWCFG_INT_ENABLE	(1 << 0)
+#define	HCDMACFG	0x21
+#define		HCDMACFG_BURST_LEN_MASK	(0x03 << 5)
+#define		HCDMACFG_BURST_LEN(n)	(((n) << 5) & HCDMACFG_BURST_LEN_MASK)
+#define		HCDMACFG_BURST_LEN_1	HCDMACFG_BURST_LEN(0)
+#define		HCDMACFG_BURST_LEN_4	HCDMACFG_BURST_LEN(1)
+#define		HCDMACFG_BURST_LEN_8	HCDMACFG_BURST_LEN(2)
+#define		HCDMACFG_DMA_ENABLE	(1 << 4)
+#define		HCDMACFG_BUF_TYPE_MASK	(0x07 << 1)
+#define		HCDMACFG_CTR_SEL	(1 << 2)
+#define		HCDMACFG_ITLATL_SEL	(1 << 1)
+#define		HCDMACFG_DMA_RW_SELECT	(1 << 0)
+#define	HCXFERCTR	0x22
+#define	HCuPINT		0x24
+#define		HCuPINT_SOF		(1 << 0)
+#define		HCuPINT_ATL		(1 << 1)
+#define		HCuPINT_AIIEOT		(1 << 2)
+#define		HCuPINT_OPR		(1 << 4)
+#define		HCuPINT_SUSP		(1 << 5)
+#define		HCuPINT_CLKRDY		(1 << 6)
+#define	HCuPINTENB	0x25
+#define	HCCHIPID	0x27
+#define		HCCHIPID_MASK		0xff00
+#define		HCCHIPID_MAGIC		0x6100
+#define	HCSCRATCH	0x28
+#define	HCSWRES		0x29
+#define		HCSWRES_MAGIC		0x00f6
+#define	HCITLBUFLEN	0x2a
+#define	HCATLBUFLEN	0x2b
+#define	HCBUFSTAT	0x2c
+#define		HCBUFSTAT_ITL0_FULL	(1 << 0)
+#define		HCBUFSTAT_ITL1_FULL	(1 << 1)
+#define		HCBUFSTAT_ATL_FULL	(1 << 2)
+#define		HCBUFSTAT_ITL0_DONE	(1 << 3)
+#define		HCBUFSTAT_ITL1_DONE	(1 << 4)
+#define		HCBUFSTAT_ATL_DONE	(1 << 5)
+#define	HCRDITL0LEN	0x2d
+#define	HCRDITL1LEN	0x2e
+#define	HCITLPORT	0x40
+#define	HCATLPORT	0x41
+
+/* PTD accessor macros. */
+#define PTD_GET_COUNT(p)	(((p)->count & PTD_COUNT_MSK) >> 0)
+#define PTD_COUNT(v)		(((v) << 0) & PTD_COUNT_MSK)
+#define PTD_GET_TOGGLE(p)	(((p)->count & PTD_TOGGLE_MSK) >> 10)
+#define PTD_TOGGLE(v)		(((v) << 10) & PTD_TOGGLE_MSK)
+#define PTD_GET_ACTIVE(p)	(((p)->count & PTD_ACTIVE_MSK) >> 11)
+#define PTD_ACTIVE(v)		(((v) << 11) & PTD_ACTIVE_MSK)
+#define PTD_GET_CC(p)		(((p)->count & PTD_CC_MSK) >> 12)
+#define PTD_CC(v)		(((v) << 12) & PTD_CC_MSK)
+#define PTD_GET_MPS(p)		(((p)->mps & PTD_MPS_MSK) >> 0)
+#define PTD_MPS(v)		(((v) << 0) & PTD_MPS_MSK)
+#define PTD_GET_SPD(p)		(((p)->mps & PTD_SPD_MSK) >> 10)
+#define PTD_SPD(v)		(((v) << 10) & PTD_SPD_MSK)
+#define PTD_GET_LAST(p)		(((p)->mps & PTD_LAST_MSK) >> 11)
+#define PTD_LAST(v)		(((v) << 11) & PTD_LAST_MSK)
+#define PTD_GET_EP(p)		(((p)->mps & PTD_EP_MSK) >> 12)
+#define PTD_EP(v)		(((v) << 12) & PTD_EP_MSK)
+#define PTD_GET_LEN(p)		(((p)->len & PTD_LEN_MSK) >> 0)
+#define PTD_LEN(v)		(((v) << 0) & PTD_LEN_MSK)
+#define PTD_GET_DIR(p)		(((p)->len & PTD_DIR_MSK) >> 10)
+#define PTD_DIR(v)		(((v) << 10) & PTD_DIR_MSK)
+#define PTD_GET_B5_5(p)		(((p)->len & PTD_B5_5_MSK) >> 13)
+#define PTD_B5_5(v)		(((v) << 13) & PTD_B5_5_MSK)
+#define PTD_GET_FA(p)		(((p)->faddr & PTD_FA_MSK) >> 0)
+#define PTD_FA(v)		(((v) << 0) & PTD_FA_MSK)
+#define PTD_GET_FMT(p)		(((p)->faddr & PTD_FMT_MSK) >> 7)
+#define PTD_FMT(v)		(((v) << 7) & PTD_FMT_MSK)
+
+/*  Hardware transfer status codes -- CC from ptd->count */
+#define TD_CC_NOERROR      0x00
+#define TD_CC_CRC          0x01
+#define TD_CC_BITSTUFFING  0x02
+#define TD_CC_DATATOGGLEM  0x03
+#define TD_CC_STALL        0x04
+#define TD_DEVNOTRESP      0x05
+#define TD_PIDCHECKFAIL    0x06
+#define TD_UNEXPECTEDPID   0x07
+#define TD_DATAOVERRUN     0x08
+#define TD_DATAUNDERRUN    0x09
+    /* 0x0A, 0x0B reserved for hardware */
+#define TD_BUFFEROVERRUN   0x0C
+#define TD_BUFFERUNDERRUN  0x0D
+    /* 0x0E, 0x0F reserved for HCD */
+#define TD_NOTACCESSED     0x0F
+
+/* ------------------------------------------------------------------------- */
+
+#define	LOG2_PERIODIC_SIZE	5	/* arbitrary; this matches OHCI */
+#define	PERIODIC_SIZE		(1 << LOG2_PERIODIC_SIZE)
+
+/* Philips transfer descriptor */
+struct ptd {
+	u16 count;
+#define	PTD_COUNT_MSK	(0x3ff << 0)
+#define	PTD_TOGGLE_MSK	(1 << 10)
+#define	PTD_ACTIVE_MSK	(1 << 11)
+#define	PTD_CC_MSK	(0xf << 12)
+	u16 mps;
+#define	PTD_MPS_MSK	(0x3ff << 0)
+#define	PTD_SPD_MSK	(1 << 10)
+#define	PTD_LAST_MSK	(1 << 11)
+#define	PTD_EP_MSK	(0xf << 12)
+	u16 len;
+#define	PTD_LEN_MSK	(0x3ff << 0)
+#define	PTD_DIR_MSK	(3 << 10)
+#define	PTD_DIR_SETUP	(0)
+#define	PTD_DIR_OUT	(1)
+#define	PTD_DIR_IN	(2)
+#define	PTD_B5_5_MSK	(1 << 13)
+	u16 faddr;
+#define	PTD_FA_MSK	(0x7f << 0)
+#define	PTD_FMT_MSK	(1 << 7)
+} __attribute__ ((packed, aligned(2)));
+
+struct isp116x_ep {
+	struct usb_device *udev;
+	struct ptd ptd;
+
+	u8 maxpacket;
+	u8 epnum;
+	u8 nextpid;
+
+	u16 length;		/* of current packet */
+	unsigned char *data;	/* to databuf */
+
+	u16 error_count;
+};
+
+/* URB struct */
+#define N_URB_TD		48
+#define URB_DEL			1
+typedef struct {
+	struct isp116x_ep *ed;
+	void *transfer_buffer;	/* (in) associated data buffer */
+	int actual_length;	/* (return) actual transfer length */
+	unsigned long pipe;	/* (in) pipe information */
+#if 0
+	int state;
+#endif
+} urb_priv_t;
+
+struct isp116x_platform_data {
+	/* Enable internal resistors on downstream ports */
+	unsigned sel15Kres:1;
+	/* On-chip overcurrent detection */
+	unsigned oc_enable:1;
+	/* Enable wakeup by devices on usb bus (e.g. wakeup
+	   by attachment/detachment or by device activity
+	   such as moving a mouse). When chosen, this option
+	   prevents stopping internal clock, increasing
+	   thereby power consumption in suspended state. */
+	unsigned remote_wakeup_enable:1;
+};
+
+struct isp116x {
+	u16 *addr_reg;
+	u16 *data_reg;
+
+	struct isp116x_platform_data *board;
+
+	struct dentry *dentry;
+	unsigned long stat1, stat2, stat4, stat8, stat16;
+
+	/* Status flags */
+	unsigned disabled:1;
+	unsigned sleeping:1;
+
+	/* Root hub registers */
+	u32 rhdesca;
+	u32 rhdescb;
+	u32 rhstatus;
+	u32 rhport[2];
+
+	/* Schedule for the current frame */
+	struct isp116x_ep *atl_active;
+	int atl_buflen;
+	int atl_bufshrt;
+	int atl_last_dir;
+	int atl_finishing;
+};
+
+/* ------------------------------------------------- */
+
+/* Inter-io delay (ns). The chip is picky about access timings; it
+ * expects at least:
+ * 150ns delay between consecutive accesses to DATA_REG,
+ * 300ns delay between access to ADDR_REG and DATA_REG
+ * OE, WE MUST NOT be changed during these intervals
+ */
+#if defined(UDELAY)
+#define	isp116x_delay(h,d)	udelay(d)
+#else
+#define	isp116x_delay(h,d)	do {} while (0)
+#endif
+
+#include "../../super.h"	/*
+	 		 	* Functions to call supervisor mode
+		 	 	* Super() in in TOS is buggy
+			 	*/
+
+			 
+static inline void isp116x_write_addr(struct isp116x *isp116x, unsigned reg)
+{
+	u16 dumm;
+	u32 p = 0;
+	if ( !(Super (SUP_INQUIRE)))
+		p = SuperFromUser( );
+	isp116x->data_reg = (u16*)(ISP116X_HCD_DATA_BEE + ((reg & 0x00ff)<<1)); 
+	dumm = __raw_readw( isp116x->data_reg  );
+	isp116x->addr_reg = (u16*)ISP116X_HCD_ADDR_BEE;
+	dumm = __raw_readw( isp116x->addr_reg  );
+	isp116x_delay(isp116x, UDELAY);
+	if ((Super (SUP_INQUIRE)) && (p))
+		SuperToUser( p );
+//	ERR ( "data_reg: %x \n\r", isp116x->data_reg);
+//	ERR ( "addr_reg: %x \n\r", isp116x->addr_reg);
+}
+
+static inline void isp116x_write_data16(struct isp116x *isp116x, u16 val)
+{
+	u16 dumm;
+	u32 p = 0;
+	if ( !(Super (SUP_INQUIRE)))
+		p = SuperFromUser( );
+	isp116x->data_reg = (u16*)(ISP116X_HCD_DATA_BEE + ((val & 0xff00)>>7) ); 
+	dumm = __raw_readw(isp116x->data_reg);
+	isp116x->addr_reg = (u16*)((ISP116X_HCD_ADDR_BEE - 0x4000) + ((val & 0x00ff)<<1));
+	dumm = __raw_readw(isp116x->addr_reg);
+	isp116x_delay(isp116x, UDELAY);
+	if ((Super (SUP_INQUIRE)) && (p))
+		SuperToUser( p );
+//	ERR ( "data_reg: %x \n\r", isp116x->data_reg);
+//	ERR ( "addr_reg: %x \n\r", isp116x->addr_reg);
+}
+
+static inline void isp116x_raw_write_data16(struct isp116x *isp116x, u16 val)
+{
+	u16 dumm;
+	u32 p = 0;
+	if ( !(Super (SUP_INQUIRE)))
+		p = SuperFromUser( );
+	isp116x->data_reg = (u16*)(ISP116X_HCD_DATA_BEE + ((val & 0x00ff)<<1));
+	dumm = __raw_readw(isp116x->data_reg);
+	isp116x->addr_reg =  (u16*)((ISP116X_HCD_ADDR_BEE - 0x4000) + ((val & 0xff00)>>7)); 
+	dumm = __raw_readw(isp116x->addr_reg);
+	isp116x_delay(isp116x, UDELAY);
+	if ((Super (SUP_INQUIRE)) && (p))
+		SuperToUser( p );
+//	ERR ( "data_reg: %x \n\r", isp116x->data_reg);
+//	ERR ( "addr_reg: %x \n\r", isp116x->addr_reg);
+}
+
+
+static inline u16 isp116x_read_data16(struct isp116x *isp116x)
+{
+	u16 val;
+	u32 p = 0;
+	if ( !(Super (SUP_INQUIRE)))
+		p = SuperFromUser( );
+	isp116x->data_reg = (u16*)(ISP116X_HCD_DATA_BEE + 0x8000);
+	val = readw(isp116x->data_reg );
+	isp116x_delay(isp116x, UDELAY);
+	if ((Super (SUP_INQUIRE)) && (p))
+		SuperToUser( p );
+	return val;
+}
+
+
+static inline u16 isp116x_raw_read_data16(struct isp116x *isp116x)
+{
+	u16 val;
+	u32 p = 0;
+	if ( !(Super (SUP_INQUIRE)))
+		p = SuperFromUser( );
+	isp116x->data_reg = (u16*)(ISP116X_HCD_DATA_BEE + 0x8000);
+	val = __raw_readw(isp116x->data_reg );
+	isp116x_delay(isp116x, UDELAY);
+	if ((Super (SUP_INQUIRE)) && (p))
+		SuperToUser( p );
+//	ERR ( "data_reg: %x value: %x\n\r", isp116x->data_reg, val );
+	return val;
+}
+
+#if 0 /* We don't use it anymore */
+static inline void isp116x_write_data32(struct isp116x *isp116x, u32 val)
+{
+//	p = SuperFromUser( );
+	writew(val & 0xffff, isp116x->data_reg);
+	isp116x_delay(isp116x, UDELAY);
+	writew(val >> 16, isp116x->data_reg);
+	isp116x_delay(isp116x, UDELAY);
+//	SuperToUser( p );
+}
+#endif
+
+/*
+ * Added for NetUSBee, to write HC registers without swaping them
+ * NetUSBee already swap them by hardware (i suppose.....)
+ */
+static inline void isp116x_raw_write_data32(struct isp116x *isp116x, u32 val)
+{
+	u16 dumm;
+	u32 p = 0;
+	if ( !(Super (SUP_INQUIRE)))
+		p = SuperFromUser( );
+	isp116x->data_reg =  (u16*)(ISP116X_HCD_DATA_BEE + ((val & 0x000000ff)<<1) ); 
+	dumm = __raw_readw(isp116x->data_reg);
+	isp116x->addr_reg = (u16*)((ISP116X_HCD_ADDR_BEE - 0x4000) + ((val & 0x0000ff00)>>7)); 
+	dumm = __raw_readw(isp116x->addr_reg);
+	isp116x_delay(isp116x, UDELAY);
+	isp116x->data_reg = (u16*)(ISP116X_HCD_DATA_BEE + ((val & 0x00ff0000)>>15));
+	dumm = __raw_readw(isp116x->data_reg);
+	isp116x->addr_reg = (u16*)((ISP116X_HCD_ADDR_BEE - 0x4000) + ((val & 0xff000000)>>23) );
+	dumm = __raw_readw(isp116x->addr_reg);
+	isp116x_delay(isp116x, UDELAY);
+	if ((Super (SUP_INQUIRE)) && (p))
+		SuperToUser( p );
+}
+/***********************************************/
+
+#if 0 /* We don't use it */
+static inline u32 isp116x_read_data32(struct isp116x *isp116x)
+{
+	u32 val;
+	p = SuperFromUser( );
+	val = (u32) readw(isp116x->data_reg);
+	isp116x_delay(isp116x, UDELAY);
+	val |= ((u32) readw(isp116x->data_reg)) << 16;
+	isp116x_delay(isp116x, UDELAY);
+	SuperToUser( p );
+	return val;
+}
+#endif
+
+/*
+ * Added for NetUSBee, to read HC registers without swaping them
+ * NetUSBee already swap them by hardware (i suppose.....)
+ */
+static inline u32 isp116x_raw_read_data32(struct isp116x *isp116x)
+{
+	u32 val;
+	u32 p = 0;
+	if ( !(Super (SUP_INQUIRE)))
+		p = SuperFromUser( );
+	isp116x->data_reg = (u16*)(ISP116X_HCD_DATA_BEE + 0x8000);
+	val = (u32) __raw_readw(isp116x->data_reg );
+	isp116x_delay(isp116x, UDELAY);
+	val |= ((u32) __raw_readw(isp116x->data_reg )) << 16;
+	isp116x_delay(isp116x, UDELAY);
+	if ((Super (SUP_INQUIRE)) && (p))
+		SuperToUser( p );
+	return val;
+}
+/*******************************************************************/
+
+/* Let's keep register access functions out of line. Hint:
+   we wait at least 150 ns at every access.
+*/
+
+/* with NetUSBee use raw_read to avoid swaping bytes*/
+
+static u16 isp116x_read_reg16(struct isp116x *isp116x, unsigned reg)
+{
+	isp116x_write_addr(isp116x, reg);
+	return isp116x_raw_read_data16(isp116x);
+}
+
+static u32 isp116x_read_reg32(struct isp116x *isp116x, unsigned reg)
+{
+	isp116x_write_addr(isp116x, reg);
+	return isp116x_raw_read_data32(isp116x);
+}
+
+static void isp116x_write_reg16(struct isp116x *isp116x, unsigned reg,
+				unsigned val)
+{
+	isp116x_write_addr(isp116x, reg | ISP116x_WRITE_OFFSET);
+	isp116x_raw_write_data16(isp116x, (u16) (val & 0xffff));
+}
+
+/* with NetUSBee used raw_write to avoid swaping bytes by software */
+static void isp116x_write_reg32(struct isp116x *isp116x, unsigned reg,
+				unsigned val)
+{
+	isp116x_write_addr(isp116x, reg | ISP116x_WRITE_OFFSET);
+	isp116x_raw_write_data32(isp116x, (u32) val);
+}
+
+/* --- USB HUB constants (not OHCI-specific; see hub.h) -------------------- */
+
+/* destination of request */
+#define RH_INTERFACE               0x01
+#define RH_ENDPOINT                0x02
+#define RH_OTHER                   0x03
+
+#define RH_CLASS                   0x20
+#define RH_VENDOR                  0x40
+
+/* Requests: bRequest << 8 | bmRequestType */
+#define RH_GET_STATUS           0x0080
+#define RH_CLEAR_FEATURE        0x0100
+#define RH_SET_FEATURE          0x0300
+#define RH_SET_ADDRESS          0x0500
+#define RH_GET_DESCRIPTOR       0x0680
+#define RH_SET_DESCRIPTOR       0x0700
+#define RH_GET_CONFIGURATION    0x0880
+#define RH_SET_CONFIGURATION    0x0900
+#define RH_GET_STATE            0x0280
+#define RH_GET_INTERFACE        0x0A80
+#define RH_SET_INTERFACE        0x0B00
+#define RH_SYNC_FRAME           0x0C80
+/* Our Vendor Specific Request */
+#define RH_SET_EP               0x2000
+
+/* Hub port features */
+#define RH_PORT_CONNECTION         0x00
+#define RH_PORT_ENABLE             0x01
+#define RH_PORT_SUSPEND            0x02
+#define RH_PORT_OVER_CURRENT       0x03
+#define RH_PORT_RESET              0x04
+#define RH_PORT_POWER              0x08
+#define RH_PORT_LOW_SPEED          0x09
+
+#define RH_C_PORT_CONNECTION       0x10
+#define RH_C_PORT_ENABLE           0x11
+#define RH_C_PORT_SUSPEND          0x12
+#define RH_C_PORT_OVER_CURRENT     0x13
+#define RH_C_PORT_RESET            0x14
+
+/* Hub features */
+#define RH_C_HUB_LOCAL_POWER       0x00
+#define RH_C_HUB_OVER_CURRENT      0x01
+
+#define RH_DEVICE_REMOTE_WAKEUP    0x00
+#define RH_ENDPOINT_STALL          0x01
+
+#define RH_ACK                     0x01
+#define RH_REQ_ERR                 -1
+#define RH_NACK                    0x00
+
+#endif /* _NETUSBEE_ISP116X_H */
diff --git a/FireBee/trunk/usb/store/host/ohci-pci/ltoa.c b/FireBee/trunk/usb/store/host/ohci-pci/ltoa.c
new file mode 100644
index 0000000..747ec55
--- /dev/null
+++ b/FireBee/trunk/usb/store/host/ohci-pci/ltoa.c
@@ -0,0 +1,38 @@
+/*
+ * File:        ltoa.c
+ * Purpose:     Function normally found in a standard C lib.
+ *
+ * Notes:       This supports ASCII only!!!
+ */
+
+void ltoa(char *buf, long n, unsigned long base)
+{
+	unsigned long un;
+	char *tmp, ch;
+	un = n;
+	if((base == 10) && (n < 0))
+	{
+		*buf++ = '-';
+		un = -n;
+	}
+	tmp = buf;
+	do
+	{
+		ch = un % base;
+		un = un / base;
+		if(ch <= 9)
+			ch += '0';
+		else
+			ch += 'a' - 10;
+		*tmp++ = ch;
+	}
+	while(un);
+	*tmp = '\0';
+	while(tmp > buf)
+	{
+		ch = *buf;
+		*buf++ = *--tmp;
+		*tmp = ch;
+	}
+}
+
diff --git a/FireBee/trunk/usb/store/host/ohci-pci/mod_devicetable.h b/FireBee/trunk/usb/store/host/ohci-pci/mod_devicetable.h
new file mode 100644
index 0000000..8e480b5
--- /dev/null
+++ b/FireBee/trunk/usb/store/host/ohci-pci/mod_devicetable.h
@@ -0,0 +1,165 @@
+#ifndef MOD_DEVICETABLE_H
+#define MOD_DEVICETABLE_H
+
+#define PCI_ANY_ID (~0)
+
+struct pci_device_id {
+	unsigned long vendor, device;		/* Vendor and device ID or PCI_ANY_ID*/
+	unsigned long subvendor, subdevice;	/* Subsystem ID's or PCI_ANY_ID */
+	unsigned long class, class_mask;	/* (class,subclass,prog-if) triplet */
+	unsigned long driver_data;	/* Data private to the driver */
+};
+
+#define IEEE1394_MATCH_VENDOR_ID	0x0001
+#define IEEE1394_MATCH_MODEL_ID		0x0002
+#define IEEE1394_MATCH_SPECIFIER_ID	0x0004
+#define IEEE1394_MATCH_VERSION		0x0008
+
+struct ieee1394_device_id {
+	unsigned long match_flags;
+	unsigned long vendor_id;
+	unsigned long model_id;
+	unsigned long specifier_id;
+	unsigned long version;
+	unsigned long driver_data;
+};
+
+/*
+ * Device table entry for "new style" table-driven USB drivers.
+ * User mode code can read these tables to choose which modules to load.
+ * Declare the table as a MODULE_DEVICE_TABLE.
+ *
+ * A probe() parameter will point to a matching entry from this table.
+ * Use the driver_info field for each match to hold information tied
+ * to that match:  device quirks, etc.
+ *
+ * Terminate the driver's table with an all-zeroes entry.
+ * Use the flag values to control which fields are compared.
+ */
+
+/**
+ * struct usb_device_id - identifies USB devices for probing and hotplugging
+ * @match_flags: Bit mask controlling of the other fields are used to match
+ *	against new devices.  Any field except for driver_info may be used,
+ *	although some only make sense in conjunction with other fields.
+ *	This is usually set by a USB_DEVICE_*() macro, which sets all
+ *	other fields in this structure except for driver_info.
+ * @idVendor: USB vendor ID for a device; numbers are assigned
+ *	by the USB forum to its members.
+ * @idProduct: Vendor-assigned product ID.
+ * @bcdDevice_lo: Low end of range of vendor-assigned product version numbers.
+ *	This is also used to identify individual product versions, for
+ *	a range consisting of a single device.
+ * @bcdDevice_hi: High end of version number range.  The range of product
+ *	versions is inclusive.
+ * @bDeviceClass: Class of device; numbers are assigned
+ *	by the USB forum.  Products may choose to implement classes,
+ *	or be vendor-specific.  Device classes specify behavior of all
+ *	the interfaces on a devices.
+ * @bDeviceSubClass: Subclass of device; associated with bDeviceClass.
+ * @bDeviceProtocol: Protocol of device; associated with bDeviceClass.
+ * @bInterfaceClass: Class of interface; numbers are assigned
+ *	by the USB forum.  Products may choose to implement classes,
+ *	or be vendor-specific.  Interface classes specify behavior only
+ *	of a given interface; other interfaces may support other classes.
+ * @bInterfaceSubClass: Subclass of interface; associated with bInterfaceClass.
+ * @bInterfaceProtocol: Protocol of interface; associated with bInterfaceClass.
+ * @driver_info: Holds information used by the driver.  Usually it holds
+ *	a pointer to a descriptor understood by the driver, or perhaps
+ *	device flags.
+ *
+ * In most cases, drivers will create a table of device IDs by using
+ * USB_DEVICE(), or similar macros designed for that purpose.
+ * They will then export it to userspace using MODULE_DEVICE_TABLE(),
+ * and provide it to the USB core through their usb_driver structure.
+ *
+ * See the usb_match_id() function for information about how matches are
+ * performed.  Briefly, you will normally use one of several macros to help
+ * construct these entries.  Each entry you provide will either identify
+ * one or more specific products, or will identify a class of products
+ * which have agreed to behave the same.  You should put the more specific
+ * matches towards the beginning of your table, so that driver_info can
+ * record quirks of specific products.
+ */
+struct usb_device_id {
+	/* which fields to match against? */
+	unsigned short		match_flags;
+
+	/* Used for product specific matches; range is inclusive */
+	unsigned short		idVendor;
+	unsigned short		idProduct;
+	unsigned short		bcdDevice_lo;
+	unsigned short		bcdDevice_hi;
+
+	/* Used for device class matches */
+	unsigned char		bDeviceClass;
+	unsigned char		bDeviceSubClass;
+	unsigned char		bDeviceProtocol;
+
+	/* Used for interface class matches */
+	unsigned char		bInterfaceClass;
+	unsigned char		bInterfaceSubClass;
+	unsigned char		bInterfaceProtocol;
+
+	/* not matched against */
+	unsigned long	driver_info;
+};
+
+/* Some useful macros to use to create struct usb_device_id */
+#define USB_DEVICE_ID_MATCH_VENDOR		0x0001
+#define USB_DEVICE_ID_MATCH_PRODUCT		0x0002
+#define USB_DEVICE_ID_MATCH_DEV_LO		0x0004
+#define USB_DEVICE_ID_MATCH_DEV_HI		0x0008
+#define USB_DEVICE_ID_MATCH_DEV_CLASS		0x0010
+#define USB_DEVICE_ID_MATCH_DEV_SUBCLASS	0x0020
+#define USB_DEVICE_ID_MATCH_DEV_PROTOCOL	0x0040
+#define USB_DEVICE_ID_MATCH_INT_CLASS		0x0080
+#define USB_DEVICE_ID_MATCH_INT_SUBCLASS	0x0100
+#define USB_DEVICE_ID_MATCH_INT_PROTOCOL	0x0200
+
+/* s390 CCW devices */
+struct ccw_device_id {
+	unsigned short	match_flags;	/* which fields to match against */
+
+	unsigned short	cu_type;	/* control unit type     */
+	unsigned short	dev_type;	/* device type           */
+	unsigned char	cu_model;	/* control unit model    */
+	unsigned char	dev_model;	/* device model          */
+
+	unsigned long driver_info;
+};
+
+#define CCW_DEVICE_ID_MATCH_CU_TYPE		0x01
+#define CCW_DEVICE_ID_MATCH_CU_MODEL		0x02
+#define CCW_DEVICE_ID_MATCH_DEVICE_TYPE		0x04
+#define CCW_DEVICE_ID_MATCH_DEVICE_MODEL	0x08
+
+
+#define PNP_ID_LEN	8
+#define PNP_MAX_DEVICES	8
+
+struct pnp_device_id {
+	unsigned char id[PNP_ID_LEN];
+	unsigned long driver_data;
+};
+
+struct pnp_card_device_id {
+	unsigned char id[PNP_ID_LEN];
+	unsigned long driver_data;
+	struct {
+		unsigned char id[PNP_ID_LEN];
+	} devs[PNP_MAX_DEVICES];
+};
+
+
+#define SERIO_ANY	0xff
+
+struct serio_device_id {
+	unsigned char type;
+	unsigned char extra;
+	unsigned char id;
+	unsigned char proto;
+};
+
+
+#endif /* MOD_DEVICETABLE_H */
diff --git a/FireBee/trunk/usb/store/host/ohci-pci/ohci-hcd.c b/FireBee/trunk/usb/store/host/ohci-pci/ohci-hcd.c
new file mode 100644
index 0000000..8dcab45
--- /dev/null
+++ b/FireBee/trunk/usb/store/host/ohci-pci/ohci-hcd.c
@@ -0,0 +1,1953 @@
+/*
+ * URB OHCI HCD (Host Controller Driver) for USB and PCI bus.
+ *
+ * Interrupt support is added. Now, it has been tested
+ * on ULI1575 chip and works well with USB keyboard.
+ *
+ * (C) Copyright 2007
+ * Zhang Wei, Freescale Semiconductor, Inc. <wei.zhang@freescale.com>
+ *
+ * (C) Copyright 2003
+ * Gary Jennejohn, DENX Software Engineering <garyj@denx.de>
+ *
+ * Note: Much of this code has been derived from Linux 2.4
+ * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
+ * (C) Copyright 2000-2002 David Brownell
+ *
+ * Modified for the MP2USB by (C) Copyright 2005 Eric Benard
+ * ebenard@eukrea.com - based on s3c24x0's driver
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+/*
+ * IMPORTANT NOTE
+ * this driver is intended for use with USB Mass Storage Devices
+ * (BBB) and USB keyboard. There is NO support for Isochronous pipes!
+ */
+
+#include "../../config.h"
+#include "../../usb.h"
+#include "ohci.h"
+#include "pci_ids.h"
+#include "pcixbios.h"
+
+#include "../../debug.h"
+/* Extra debug information, aside from config.h */
+#undef OHCI_VERBOSE_DEBUG	/* not always helpful */
+#undef SHOW_INFO
+#undef OHCI_FILL_TRACE
+
+/* For initializing controller (mask in an HCFS mode too) */
+#define OHCI_CONTROL_INIT \
+	(OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
+
+/*
+ * e.g. PCI controllers need this
+ */
+#ifdef CONFIG_SYS_OHCI_SWAP_REG_ACCESS
+# define readl(a) __swap_32(*((volatile u32 *)(a)))
+# define writel(a, b) (*((volatile u32 *)(b)) = __swap_32((volatile u32)a))
+#else
+# define readl(a) (*((volatile u32 *)(a)))
+# define writel(a, b) (*((volatile u32 *)(b)) = ((volatile u32)a))
+#endif /* CONFIG_SYS_OHCI_SWAP_REG_ACCESS */
+
+#define min_t(type, x, y) \
+		    ({ type __x = (x); type __y = (y); __x < __y ? __x: __y; })
+
+/* Galvez: added to avoid shadow warnings */
+#define min2_t(type,x,y)	\
+	({ type __a = (x); type __b = (y); __a < __b ? __a : __b; })
+
+struct pci_device_id usb_pci_table[] = {
+	{ PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M5237, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* ULI1575 PCI OHCI module ids */
+	{ PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_USB, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* NEC PCI OHCI module ids */
+//	{ PCI_VENDOR_ID_PHILIPS, PCI_VENDOR_ID_PHILIPS_ISP1561, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 }, /* Philips 1561 PCI OHCI module ids */
+	/* Please add supported PCI OHCI controller ids here */
+	{ 0, 0, 0, 0, 0, 0, 0 }
+};
+
+
+#define err(format, arg...) printf("ERROR: " format "\r\n", ## arg)
+#ifdef SHOW_INFO
+#define info(format, arg...) printf("INFO: " format "\r\n", ## arg)
+#else
+#define info(format, arg...) do {} while (0)
+#endif
+
+#define m16_swap(x) cpu_to_le16(x)
+#define m32_swap(x) cpu_to_le32(x)
+
+typedef struct
+{
+	long ident;
+	union
+	{
+		long l;
+		short i[2];
+		char c[4];
+	} v;
+} COOKIE;
+
+extern COOKIE *get_cookie(long id);
+extern void udelay(long usec);
+extern void ltoa(char *buf, long n, unsigned long base);
+
+/* global ohci_t */
+static ohci_t gohci;
+/* device which was disconnected */
+struct usb_device *devgone;
+char ohci_inited;
+
+static inline u32 roothub_a(struct ohci *hc)
+	{ return readl(&hc->regs->roothub.a); }
+static inline u32 roothub_b(struct ohci *hc)
+	{ return readl(&hc->regs->roothub.b); }
+static inline u32 roothub_status(struct ohci *hc)
+	{ return readl(&hc->regs->roothub.status); }
+static inline u32 roothub_portstatus(struct ohci *hc, int i)
+	{ return readl(&hc->regs->roothub.portstatus[i]); }
+
+/* forward declaration */
+static int hc_interrupt(void);
+static void td_submit_job(struct usb_device *dev, unsigned long pipe,
+void *buffer, int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval);
+
+#if 0
+unsigned short cpu_to_le16(unsigned short val)
+{
+	extern unsigned short swap_short(unsigned short val);
+	if(gohci.big_endian)
+		return(swap_short(val));
+	return(val);
+}
+
+unsigned long cpu_to_le32(unsigned long val)
+{
+	extern unsigned long swap_long(unsigned long val);
+	if(gohci.big_endian)
+		return(swap_long(val));
+	return(val);
+}
+#endif
+
+/*-------------------------------------------------------------------------*
+ * URB support functions
+ *-------------------------------------------------------------------------*/
+
+/* free HCD-private data associated with this URB */
+
+static void urb_free_priv(urb_priv_t *urb)
+{
+	int i;
+	struct td	*td;
+	int last = urb->length - 1;
+	if(last >= 0)
+	{
+		for(i = 0; i <= last; i++)
+		{
+			td = urb->td[i];
+			if(td)
+			{
+				td->usb_dev = NULL;
+				urb->td[i] = NULL;
+			}
+		}
+	}
+	usb_free(urb);
+}
+
+/*-------------------------------------------------------------------------*/
+
+#if DEBUG_HOST_LAYER
+static int sohci_get_current_frame_number(struct usb_device *dev);
+
+/* debug| print the main components of an URB
+ * small: 0) header + data packets 1) just header */
+
+static void pkt_print(urb_priv_t *purb, struct usb_device *dev,
+		      unsigned long pipe, void *buffer, int transfer_len,
+		      struct devrequest *setup, char *str, int small)
+{
+	DEBUG_HOST("%s URB:[%4x] dev:%2lu,ep:%2lu-%c,type:%s,len:%d/%d stat:%#lx",
+			str,
+			sohci_get_current_frame_number(dev),
+			usb_pipedevice(pipe),
+			usb_pipeendpoint(pipe),
+			usb_pipeout(pipe)? 'O': 'I',
+			usb_pipetype(pipe) < 2 ? \
+				(usb_pipeint(pipe)? "INTR": "ISOC"): \
+				(usb_pipecontrol(pipe)? "CTRL": "BULK"),
+			(purb ? purb->actual_length : 0),
+			transfer_len, dev->status);
+#ifdef OHCI_VERBOSE_DEBUG
+	if(!small)
+	{
+		int i, len;
+		if(usb_pipecontrol(pipe))
+		{
+			DEBUG_HOST(__FILE__ ": cmd(8):");
+			for(i = 0; i < 8 ; i++)
+				DEBUG_HOST(" %02x", ((__u8 *)setup)[i]);
+			DEBUG_HOST("\r\n");
+		}
+		if(transfer_len > 0 && buffer)
+		{
+			DEBUG_HOST(__FILE__ ": data(%d/%d):", (purb ? purb->actual_length : 0), transfer_len);
+			len = usb_pipeout(pipe)? transfer_len : (purb ? purb->actual_length : 0);
+			for(i = 0; i < 16 && i < len; i++)
+				DEBUG_HOST(" %02x", ((__u8 *)buffer)[i]);
+			DEBUG_HOST("%s\r\n", i < len? "...": "");
+		}
+	}
+#endif
+}
+
+/* just for debugging; prints non-empty branches of the int ed tree
+ * inclusive iso eds */
+void ep_print_int_eds(ohci_t *ohci, char *str)
+{
+	int i, j;
+	__u32 *ed_p;
+	for(i = 0; i < 32; i++)
+	{
+		j = 5;
+		ed_p = &(ohci->hcca->int_table[i]);
+		if(*ed_p == 0)
+			continue;
+		DEBUG_HOST(__FILE__ ": %s branch int %2d(%2x):", str, i, i);
+		while(*ed_p != 0 && j--)
+		{
+			ed_t *ed = (ed_t *)m32_swap((unsigned long)ed_p);
+			DEBUG_HOST(" ed: %4x;", ed->hwINFO);
+			ed_p = &ed->hwNextED;
+		}
+		DEBUG_HOST("\r\n");
+	}
+}
+
+static void ohci_dump_intr_mask(char *label, __u32 mask)
+{
+	DEBUG_HOST("%s: 0x%08x%s%s%s%s%s%s%s%s%s",
+		label,
+		mask,
+		(mask & OHCI_INTR_MIE) ? " MIE" : "",
+		(mask & OHCI_INTR_OC) ? " OC" : "",
+		(mask & OHCI_INTR_RHSC) ? " RHSC" : "",
+		(mask & OHCI_INTR_FNO) ? " FNO" : "",
+		(mask & OHCI_INTR_UE) ? " UE" : "",
+		(mask & OHCI_INTR_RD) ? " RD" : "",
+		(mask & OHCI_INTR_SF) ? " SF" : "",
+		(mask & OHCI_INTR_WDH) ? " WDH" : "",
+		(mask & OHCI_INTR_SO) ? " SO" : ""
+		);
+}
+
+static void maybe_print_eds(char *label, __u32 value)
+{
+	ed_t *edp; 
+	value += gohci.dma_offset;
+	edp = (ed_t *)value;
+	if(value && (value < 0xDFFFF0))  /* STRAM */
+	{
+		DEBUG_HOST("%s %08x", label, value);
+		DEBUG_HOST("%08x", edp->hwINFO);
+		DEBUG_HOST("%08x", edp->hwTailP);
+		DEBUG_HOST("%08x", edp->hwHeadP);
+		DEBUG_HOST("%08x", edp->hwNextED);
+	}
+}
+
+static char *hcfs2string(int state)
+{
+	switch(state)
+	{
+		case OHCI_USB_RESET:	return "reset";
+		case OHCI_USB_RESUME:	return "resume";
+		case OHCI_USB_OPER:	return "operational";
+		case OHCI_USB_SUSPEND:	return "suspend";
+	}
+	return "?";
+}
+
+/* dump control and status registers */
+static void ohci_dump_status(ohci_t *controller)
+{
+	struct ohci_regs	*regs = controller->regs;
+	__u32	temp = readl(&regs->revision) & 0xff;
+	if(temp != 0x10)
+		DEBUG_HOST("spec %d.%d", (temp >> 4), (temp & 0x0f));
+	temp = readl(&regs->control);
+	DEBUG_HOST("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,
+		(temp & OHCI_CTRL_RWE) ? " RWE" : "",
+		(temp & OHCI_CTRL_RWC) ? " RWC" : "",
+		(temp & OHCI_CTRL_IR) ? " IR" : "",
+		hcfs2string(temp & OHCI_CTRL_HCFS),
+		(temp & OHCI_CTRL_BLE) ? " BLE" : "",
+		(temp & OHCI_CTRL_CLE) ? " CLE" : "",
+		(temp & OHCI_CTRL_IE) ? " IE" : "",
+		(temp & OHCI_CTRL_PLE) ? " PLE" : "",
+		temp & OHCI_CTRL_CBSR
+		);
+	temp = readl(&regs->cmdstatus);
+	DEBUG_HOST("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,
+		(temp & OHCI_SOC) >> 16,
+		(temp & OHCI_OCR) ? " OCR" : "",
+		(temp & OHCI_BLF) ? " BLF" : "",
+		(temp & OHCI_CLF) ? " CLF" : "",
+		(temp & OHCI_HCR) ? " HCR" : ""
+		);
+	ohci_dump_intr_mask("intrstatus", readl(&regs->intrstatus));
+	ohci_dump_intr_mask("intrenable", readl(&regs->intrenable));
+	maybe_print_eds("ed_periodcurrent", readl(&regs->ed_periodcurrent));
+	maybe_print_eds("ed_controlhead", readl(&regs->ed_controlhead));
+	maybe_print_eds("ed_controlcurrent", readl(&regs->ed_controlcurrent));
+	maybe_print_eds("ed_bulkhead", readl(&regs->ed_bulkhead));
+	maybe_print_eds("ed_bulkcurrent", readl(&regs->ed_bulkcurrent));
+	maybe_print_eds("donehead", readl(&regs->donehead));
+}
+
+static void ohci_dump_roothub(ohci_t *controller, int verbose)
+{
+	__u32	temp, ndp, i;
+	temp = roothub_a(controller);
+	ndp = (temp & RH_A_NDP);
+	if(verbose)
+	{
+		DEBUG_HOST("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,
+			((temp & RH_A_POTPGT) >> 24) & 0xff,
+			(temp & RH_A_NOCP) ? " NOCP" : "",
+			(temp & RH_A_OCPM) ? " OCPM" : "",
+			(temp & RH_A_DT) ? " DT" : "",
+			(temp & RH_A_NPS) ? " NPS" : "",
+			(temp & RH_A_PSM) ? " PSM" : "",
+			ndp
+			);
+		temp = roothub_b(controller);
+		DEBUG_HOST("roothub.b: %08x PPCM=%04x DR=%04x",
+			temp,
+			(temp & RH_B_PPCM) >> 16,
+			(temp & RH_B_DR)
+			);
+		temp = roothub_status(controller);
+		DEBUG_HOST("roothub.status: %08x%s%s%s%s%s%s",
+			temp,
+			(temp & RH_HS_CRWE) ? " CRWE" : "",
+			(temp & RH_HS_OCIC) ? " OCIC" : "",
+			(temp & RH_HS_LPSC) ? " LPSC" : "",
+			(temp & RH_HS_DRWE) ? " DRWE" : "",
+			(temp & RH_HS_OCI) ? " OCI" : "",
+			(temp & RH_HS_LPS) ? " LPS" : ""
+			);
+	}
+	for(i = 0; i < ndp; i++)
+	{
+		temp = roothub_portstatus(controller, i);
+		DEBUG_HOST("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",
+			i,
+			temp,
+			(temp & RH_PS_PRSC) ? " PRSC" : "",
+			(temp & RH_PS_OCIC) ? " OCIC" : "",
+			(temp & RH_PS_PSSC) ? " PSSC" : "",
+			(temp & RH_PS_PESC) ? " PESC" : "",
+			(temp & RH_PS_CSC) ? " CSC" : "",
+
+			(temp & RH_PS_LSDA) ? " LSDA" : "",
+			(temp & RH_PS_PPS) ? " PPS" : "",
+			(temp & RH_PS_PRS) ? " PRS" : "",
+			(temp & RH_PS_POCI) ? " POCI" : "",
+			(temp & RH_PS_PSS) ? " PSS" : "",
+
+			(temp & RH_PS_PES) ? " PES" : "",
+			(temp & RH_PS_CCS) ? " CCS" : ""
+			);
+	}
+}
+
+static void ohci_dump(ohci_t *controller, int verbose)
+{
+	DEBUG_HOST("OHCI controller usb-%s state", controller->slot_name);
+	/* dumps some of the state we know about */
+	ohci_dump_status(controller);
+	if(verbose)
+		ep_print_int_eds(controller, "hcca");
+	DEBUG_HOST("hcca frame #%04x", controller->hcca->frame_no);
+	ohci_dump_roothub(controller, 1);
+}
+#endif /* DEBUG */
+
+/*-------------------------------------------------------------------------*
+ * Interface functions (URB)
+ *-------------------------------------------------------------------------*/
+
+/* get a transfer request */
+
+int sohci_submit_job(urb_priv_t *urb, struct devrequest *setup)
+{
+	ohci_t *ohci;
+	ed_t *ed;
+	urb_priv_t *purb_priv = urb;
+	int i, size = 0;
+	struct usb_device *dev = urb->dev;
+	unsigned long pipe = urb->pipe;
+	void *buffer = urb->transfer_buffer;
+	int transfer_len = urb->transfer_buffer_length;
+	int interval = urb->interval;
+	ohci = &gohci;
+	/* when controller's hung, permit only roothub cleanup attempts
+	 * such as powering down ports */
+	if(ohci->disabled)
+	{
+		err("sohci_submit_job: EPIPE");
+		return -1;
+	}
+	/* we're about to begin a new transaction here so mark the
+	 * URB unfinished */
+	urb->finished = 0;
+	/* every endpoint has a ed, locate and fill it */
+	ed = ep_add_ed(dev, pipe, interval, 1);
+	if(!ed)
+	{
+		err("sohci_submit_job: ENOMEM");
+		return -1;
+	}
+	/* for the private part of the URB we need the number of TDs (size) */
+	switch(usb_pipetype(pipe))
+	{
+		case PIPE_BULK: /* one TD for every 4096 Byte */
+			size = (transfer_len - 1) / 4096 + 1;
+			break;
+		case PIPE_CONTROL:/* 1 TD for setup, 1 for ACK and 1 for every 4096 B */
+			size = (transfer_len == 0) ? 2: (transfer_len - 1) / 4096 + 3;
+			break;
+		case PIPE_INTERRUPT: /* 1 TD */
+			size = 1;
+			break;
+	}
+	ed->purb = urb;
+	if(size >= (N_URB_TD - 1))
+	{
+		err("need %d TDs, only have %d", size, N_URB_TD);
+		return -1;
+	}
+	purb_priv->pipe = pipe;
+	/* fill the private part of the URB */
+	purb_priv->length = size;
+	purb_priv->ed = ed;
+	purb_priv->actual_length = 0;
+	/* allocate the TDs */
+	/* note that td[0] was allocated in ep_add_ed */
+	for(i = 0; i < size; i++)
+	{
+		purb_priv->td[i] = td_alloc(dev);
+		if(!purb_priv->td[i])
+		{
+			purb_priv->length = i;
+			urb_free_priv(purb_priv);
+			err("sohci_submit_job: ENOMEM");
+			return -1;
+		}
+	}
+	if(ed->state == ED_NEW || (ed->state & ED_DEL))
+	{
+		urb_free_priv(purb_priv);
+		err("sohci_submit_job: EINVAL");
+		return -1;
+	}
+	/* link the ed into a chain if is not already */
+	if(ed->state != ED_OPER)
+		ep_link(ohci, ed);
+	/* fill the TDs and link it to the ed */
+	td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval);
+	return 0;
+}
+
+static inline int sohci_return_job(struct ohci *hc, urb_priv_t *urb)
+{
+	struct ohci_regs *regs = hc->regs;
+	switch(usb_pipetype(urb->pipe))
+	{
+		case PIPE_INTERRUPT:
+			/* implicitly requeued */
+			if(urb->dev->irq_handle && (urb->dev->irq_act_len = urb->actual_length))
+			{
+				writel(OHCI_INTR_WDH, &regs->intrenable);
+				readl(&regs->intrenable); /* PCI posting flush */
+ 				/* call interrupt device routine */
+ 				DEBUG_HOST("irq_handle device %d", urb->dev->devnum);
+				urb->dev->irq_handle(urb->dev);
+				writel(OHCI_INTR_WDH, &regs->intrdisable);
+				readl(&regs->intrdisable); /* PCI posting flush */
+			}
+			urb->actual_length = 0;
+			td_submit_job(urb->dev,	urb->pipe, urb->transfer_buffer, urb->transfer_buffer_length, NULL, urb, urb->interval);
+			break;
+		case PIPE_CONTROL:
+		case PIPE_BULK:
+			break;
+		default:
+			return 0;
+	}
+	return 1;
+}
+
+/*-------------------------------------------------------------------------*/
+
+#if DEBUG_HOST_LAYER
+/* tell us the current USB frame number */
+
+static int sohci_get_current_frame_number(struct usb_device *usb_dev)
+{
+	ohci_t *ohci = &gohci;
+	return m16_swap(ohci->hcca->frame_no);
+}
+#endif
+
+/*-------------------------------------------------------------------------*
+ * ED handling functions
+ *-------------------------------------------------------------------------*/
+
+/* search for the right branch to insert an interrupt ed into the int tree
+ * do some load ballancing;
+ * returns the branch and
+ * sets the interval to interval = 2^integer (ld (interval)) */
+
+static int ep_int_ballance(ohci_t *ohci, int interval, int load)
+{
+	int i, branch = 0;
+	/* search for the least loaded interrupt endpoint
+	 * branch of all 32 branches
+	 */
+	for (i = 0; i < 32; i++)
+		if (ohci->ohci_int_load [branch] > ohci->ohci_int_load [i])
+			branch = i;
+
+	branch = branch % interval;
+	for (i = branch; i < 32; i += interval)
+		ohci->ohci_int_load [i] += load;
+
+	return branch;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/*  2^int( ld (inter)) */
+
+static int ep_2_n_interval(int inter)
+{
+	int i;
+	for(i = 0; ((inter >> i) > 1) && (i < 5); i++);
+	return 1 << i;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* the int tree is a binary tree
+ * in order to process it sequentially the indexes of the branches have to
+ * be mapped the mapping reverses the bits of a word of num_bits length */
+static int ep_rev(int num_bits, int word)
+{
+	int i, wout = 0;
+	for(i = 0; i < num_bits; i++)
+		wout |= (((word >> i) & 1) << (num_bits - i - 1));
+	return wout;
+}
+
+/*-------------------------------------------------------------------------*
+ * ED handling functions
+ *-------------------------------------------------------------------------*/
+
+/* link an ed into one of the HC chains */
+
+static int ep_link(ohci_t *ohci, ed_t *edi)
+{
+	volatile ed_t *ed = edi;
+	int int_branch;
+	int i;
+	int inter;
+	int interval;
+	int load;
+	__u32 *ed_p;
+	ed->state = ED_OPER;
+	ed->int_interval = 0;
+	switch(ed->type)
+	{     
+		case PIPE_CONTROL:
+			ed->hwNextED = 0;
+			if(ohci->ed_controltail == NULL)
+				writel(ed - ohci->dma_offset, &ohci->regs->ed_controlhead);
+			else
+				ohci->ed_controltail->hwNextED = m32_swap((unsigned long)ed - ohci->dma_offset); 	
+			ed->ed_prev = ohci->ed_controltail;
+			if(!ohci->ed_controltail && !ohci->ed_rm_list[0] && !ohci->ed_rm_list[1] && !ohci->sleeping)
+			{
+				ohci->hc_control |= OHCI_CTRL_CLE;
+				writel(ohci->hc_control, &ohci->regs->control);
+			}
+			ohci->ed_controltail = edi;
+			break;
+		case PIPE_BULK:
+			ed->hwNextED = 0;
+			if(ohci->ed_bulktail == NULL)
+				writel(ed - ohci->dma_offset, &ohci->regs->ed_bulkhead);
+			else
+				ohci->ed_bulktail->hwNextED = m32_swap((unsigned long)ed - ohci->dma_offset);	
+			ed->ed_prev = ohci->ed_bulktail;
+			if(!ohci->ed_bulktail && !ohci->ed_rm_list[0] && !ohci->ed_rm_list[1] && !ohci->sleeping)
+			{
+				ohci->hc_control |= OHCI_CTRL_BLE;
+				writel(ohci->hc_control, &ohci->regs->control);
+			}
+			ohci->ed_bulktail = edi;
+			break; 	
+		case PIPE_INTERRUPT:
+			load = ed->int_load;
+			interval = ep_2_n_interval(ed->int_period);
+			ed->int_interval = interval;
+			int_branch = ep_int_ballance(ohci, interval, load);
+			ed->int_branch = int_branch;
+			for(i = 0; i < ep_rev(6, interval); i += inter)
+			{
+				inter = 1;
+				for(ed_p = &(ohci->hcca->int_table[ep_rev(5, i) + int_branch]);
+				 (*ed_p != 0) && (((ed_t *)ed_p)->int_interval >= interval);
+				 ed_p = &(((ed_t *)ed_p)->hwNextED))
+					inter = ep_rev(6, ((ed_t *)ed_p)->int_interval);
+				ed->hwNextED = *ed_p;
+				*ed_p = m32_swap((unsigned long)ed - ohci->dma_offset);
+			}
+			break;
+	}
+	return 0;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* scan the periodic table to find and unlink this ED */
+static void periodic_unlink(struct ohci *ohci, volatile struct ed *ed,
+			    unsigned idx, unsigned period)
+{
+	for( ;idx < NUM_INTS; idx += period)
+	{
+		__u32	*ed_p = &ohci->hcca->int_table[idx];
+		/* ED might have been unlinked through another path */
+		while(*ed_p != 0)
+		{
+			if(((struct ed *)m32_swap((unsigned long)ed_p)) == ed)
+			{
+				*ed_p = ed->hwNextED;
+				break;
+			}
+			ed_p = &(((struct ed *)m32_swap((unsigned long)ed_p))->hwNextED);
+		}
+	}
+}
+
+/* unlink an ed from one of the HC chains.
+ * just the link to the ed is unlinked.
+ * the link from the ed still points to another operational ed or 0
+ * so the HC can eventually finish the processing of the unlinked ed */
+
+static int ep_unlink(ohci_t *ohci, ed_t *edi)
+{
+	volatile ed_t *ed = edi;
+	int i;
+	ed->hwINFO |= m32_swap(OHCI_ED_SKIP);
+	switch(ed->type)
+	{
+		case PIPE_CONTROL:
+			if(ed->ed_prev == NULL)
+			{
+				if(!ed->hwNextED)
+				{
+					ohci->hc_control &= ~OHCI_CTRL_CLE;
+					writel(ohci->hc_control, &ohci->regs->control);
+				}
+				writel(m32_swap(*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead);
+			}
+			else
+				ed->ed_prev->hwNextED = ed->hwNextED;
+			if(ohci->ed_controltail == ed)
+				ohci->ed_controltail = ed->ed_prev;
+			else
+				((ed_t *)(m32_swap(*((__u32 *)&ed->hwNextED))) + ohci->dma_offset)->ed_prev = ed->ed_prev;
+			break;
+		case PIPE_BULK:
+			if(ed->ed_prev == NULL)
+			{
+				if(!ed->hwNextED)
+				{
+					ohci->hc_control &= ~OHCI_CTRL_BLE;
+					writel(ohci->hc_control, &ohci->regs->control);
+				}
+				writel(m32_swap(*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead);
+			}
+			else
+				ed->ed_prev->hwNextED = ed->hwNextED;
+			if(ohci->ed_bulktail == ed)
+				ohci->ed_bulktail = ed->ed_prev;
+			else
+				((ed_t *)(m32_swap(*((__u32 *)&ed->hwNextED))) + ohci->dma_offset)->ed_prev = ed->ed_prev;
+			break;
+		case PIPE_INTERRUPT:
+			periodic_unlink(ohci, ed, 0, 1);
+			for(i = ed->int_branch; i < 32; i += ed->int_interval)
+				ohci->ohci_int_load[i] -= ed->int_load;
+			break;
+	}
+	ed->state = ED_UNLINK;
+	return 0;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* add/reinit an endpoint; this should be done once at the
+ * usb_set_configuration command, but the USB stack is a little bit
+ * stateless so we do it at every transaction if the state of the ed
+ * is ED_NEW then a dummy td is added and the state is changed to
+ * ED_UNLINK in all other cases the state is left unchanged the ed
+ * info fields are setted anyway even though most of them should not
+ * change
+ */
+static ed_t *ep_add_ed(struct usb_device *usb_dev, unsigned long pipe, int interval, int load)
+{
+	td_t *td;
+	ed_t *ed_ret;
+	volatile ed_t *ed;
+	struct ohci_device *ohci_dev = gohci.ohci_dev;
+	ed = ed_ret = &ohci_dev->ed[(usb_pipeendpoint(pipe) << 1) | (usb_pipecontrol(pipe)? 0: usb_pipeout(pipe))];
+	if((ed->state & ED_DEL) || (ed->state & ED_URB_DEL))
+	{
+		err("ep_add_ed: pending delete");
+		/* pending delete request */
+		return NULL;
+	}
+	if(ed->state == ED_NEW)
+	{
+		/* dummy td; end of td list for ed */
+		td = td_alloc(usb_dev);
+		ed->hwTailP = m32_swap((unsigned long)td - gohci.dma_offset);
+		ed->hwHeadP = ed->hwTailP;
+		ed->state = ED_UNLINK;
+		ed->type = usb_pipetype(pipe);
+		ohci_dev->ed_cnt++;
+	}
+	ed->hwINFO = m32_swap(usb_pipedevice(pipe)
+			| usb_pipeendpoint(pipe) << 7
+			| (usb_pipeisoc(pipe)? 0x8000: 0)
+			| (usb_pipecontrol(pipe)? 0: \
+					   (usb_pipeout(pipe)? 0x800: 0x1000))
+			| usb_pipeslow(pipe) << 13
+			| usb_maxpacket(usb_dev, pipe) << 16);
+	if(ed->type == PIPE_INTERRUPT && ed->state == ED_UNLINK)
+	{
+		ed->int_period = interval;
+		ed->int_load = load;
+	}
+	return ed_ret;
+}
+
+/*-------------------------------------------------------------------------*
+ * TD handling functions
+ *-------------------------------------------------------------------------*/
+
+/* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
+
+static void td_fill(ohci_t *ohci, unsigned int info, void *data, int len,
+ struct usb_device *dev, int idx, urb_priv_t *urb_priv)
+{
+	volatile td_t *td, *td_pt;
+#ifdef OHCI_FILL_TRACE
+	int i;
+#endif
+	if(idx > urb_priv->length)
+	{
+		err("index > length");
+		return;
+	}
+	/* use this td as the next dummy */
+	td_pt = urb_priv->td[idx];
+	td_pt->hwNextTD = 0;
+	/* fill the old dummy TD */
+	td = urb_priv->td[idx] = (td_t *)((m32_swap(urb_priv->ed->hwTailP) & ~0xf) + ohci->dma_offset);
+	td->ed = urb_priv->ed;
+	td->next_dl_td = NULL;
+	td->index = idx;
+	td->data = (__u32)data;
+#ifdef OHCI_FILL_TRACE
+	if(usb_pipebulk(urb_priv->pipe) && usb_pipeout(urb_priv->pipe))
+	{
+		for(i = 0; i < len; i++)
+			printf("td->data[%d] %#2x ", i, ((unsigned char *)td->data)[i]);
+		printf("\r\n");
+	}
+#endif
+	if(!len)
+		data = NULL;
+	td->hwINFO = m32_swap(info);
+	if(data != NULL)
+	{
+		td->hwCBP = m32_swap((unsigned long)data - ohci->dma_offset);
+		td->hwBE = m32_swap((unsigned long)(data + len - 1 - ohci->dma_offset));
+	}
+	else
+	{
+		td->hwCBP = 0;
+		td->hwBE = 0;
+	}
+	td->hwNextTD = m32_swap((unsigned long)td_pt - ohci->dma_offset);
+	/* append to queue */
+	td->ed->hwTailP = td->hwNextTD;
+#if 0
+	if(data)
+	{
+		int i;
+		static char buf[4096];
+		char buf2[16];
+		*buf = '\0';
+		for(i = 0; i < len; i++)
+		{
+			ltoa(buf2, (long)*(unsigned char *)(data + i), 16);
+			strcat(buf, buf2);
+			strcat(buf, " ");
+		}	 
+		err(">>>>>>td_fill: %08x %08x %08X %08X at 0x%08x", 
+		 m32_swap(td->hwINFO), m32_swap(td->hwCBP), m32_swap(td->hwNextTD), m32_swap(td->hwBE), td);
+		err(" ... %s", buf);
+	}
+	else
+		err(">>>>>>td_fill: %08x %08x %08X %08X at 0x%08x", 
+		 m32_swap(td->hwINFO), m32_swap(td->hwCBP), m32_swap(td->hwNextTD), m32_swap(td->hwBE), td);
+#endif
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* prepare all TDs of a transfer */
+
+static void td_submit_job(struct usb_device *dev, unsigned long pipe,
+ void *buffer, int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval)
+{
+	ohci_t *ohci = &gohci;
+	int data_len = transfer_len;
+	void *data;
+	int cnt = 0;
+	__u32 info = 0;
+	unsigned int toggle = 0;
+	/* OHCI handles the DATA-toggles itself, we just use the USB-toggle
+	 * bits for reseting */
+	if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe)))
+		toggle = TD_T_TOGGLE;
+	else
+	{
+		toggle = TD_T_DATA0;
+		usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1);
+	}
+	urb->td_cnt = 0;
+	if(data_len)
+		data = buffer;
+	else
+		data = NULL;
+	switch(usb_pipetype(pipe))
+	{
+		case PIPE_BULK:
+			info = usb_pipeout(pipe) ? TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ;
+			while(data_len > 4096)
+			{
+				td_fill(ohci, info | (cnt? TD_T_TOGGLE : toggle), data, 4096, dev, cnt, urb);
+				data += 4096; data_len -= 4096; cnt++;
+			}
+			info = usb_pipeout(pipe) ? TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ;
+			td_fill(ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb);
+			cnt++;
+			if(!ohci->sleeping)	/* start bulk list */
+				writel(OHCI_BLF, &ohci->regs->cmdstatus);
+			break;
+		case PIPE_CONTROL:
+			/* Setup phase */
+			info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
+			td_fill(ohci, info, setup, 8, dev, cnt++, urb);
+			/* Optional Data phase */
+			if(data_len > 0)
+			{
+				info = usb_pipeout(pipe) ? TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R | TD_DP_IN | TD_T_DATA1;
+				/* NOTE:  mishandles transfers >8K, some >4K */
+				td_fill(ohci, info, data, data_len, dev, cnt++, urb);
+			}
+			/* Status phase */
+ 			info = usb_pipeout(pipe) ? TD_CC | TD_DP_IN | TD_T_DATA1 : TD_CC | TD_DP_OUT | TD_T_DATA1;
+			td_fill(ohci, info, data, 0, dev, cnt++, urb);
+			if(!ohci->sleeping) /* start Control list */
+				writel(OHCI_CLF, &ohci->regs->cmdstatus);
+			break;
+		case PIPE_INTERRUPT:
+			info = usb_pipeout(urb->pipe) ? TD_CC | TD_DP_OUT | toggle : TD_CC | TD_R | TD_DP_IN | toggle;
+			td_fill(ohci, info, data, data_len, dev, cnt++, urb);
+			break;
+	}
+	if(urb->length != cnt)
+		DEBUG_HOST("TD LENGTH %d != CNT %d", urb->length, cnt);
+}
+
+/*-------------------------------------------------------------------------*
+ * Done List handling functions
+ *-------------------------------------------------------------------------*/
+
+/* calculate the transfer length and update the urb */
+
+static void dl_transfer_length(td_t *td)
+{
+	__u32 tdINFO, tdBE, tdCBP;
+	urb_priv_t *lurb_priv = td->ed->purb;
+	tdINFO = m32_swap(td->hwINFO);
+	tdBE   = m32_swap(td->hwBE);
+	tdCBP  = m32_swap(td->hwCBP);
+	if(tdBE)
+		tdBE += gohci.dma_offset;
+	if(tdCBP)
+		tdCBP += gohci.dma_offset;
+	if(!(usb_pipecontrol(lurb_priv->pipe) && ((td->index == 0) || (td->index == lurb_priv->length - 1))))
+	{
+		if(tdBE != 0)
+		{
+			if(td->hwCBP == 0)
+				lurb_priv->actual_length += tdBE - td->data + 1;
+			else
+				lurb_priv->actual_length += tdCBP - td->data;
+		}
+	}
+}
+
+/*-------------------------------------------------------------------------*/
+void check_status(td_t *td_list)
+{
+	urb_priv_t *lurb_priv = td_list->ed->purb;
+	int urb_len = lurb_priv->length;
+	__u32 *phwHeadP = &td_list->ed->hwHeadP;
+	int cc = TD_CC_GET(m32_swap(td_list->hwINFO));
+	if(cc)
+	{
+		err(" USB-error: %s (%x)", cc_to_string[cc], cc);
+		if(*phwHeadP & m32_swap(0x1))
+		{
+			if(lurb_priv && ((td_list->index + 1) < urb_len))
+			{
+				*phwHeadP = (lurb_priv->td[urb_len - 1]->hwNextTD &	m32_swap(0xfffffff0)) | (*phwHeadP & m32_swap(0x2));
+				lurb_priv->td_cnt += urb_len - td_list->index - 1;
+			}
+			else
+				*phwHeadP &= m32_swap(0xfffffff2);
+		}
+#ifdef CONFIG_MPC5200
+		td_list->hwNextTD = 0;
+#endif
+	}
+}
+
+/* replies to the request have to be on a FIFO basis so
+ * we reverse the reversed done-list */
+td_t *dl_reverse_done_list(ohci_t *ohci)
+{
+	__u32 td_list_hc;
+	td_t *td_rev = NULL;
+	td_t *td_list = NULL;
+	td_list_hc = m32_swap(ohci->hcca->done_head) & ~0xf;
+	if(td_list_hc)
+		td_list_hc += ohci->dma_offset;
+	ohci->hcca->done_head = 0;
+	while(td_list_hc)
+	{
+		td_list = (td_t *)td_list_hc;
+		check_status(td_list);
+		td_list->next_dl_td = td_rev;
+		td_rev = td_list;
+		td_list_hc = m32_swap(td_list->hwNextTD) & ~0xf;
+		if(td_list_hc)
+			td_list_hc += ohci->dma_offset;
+	}
+	return td_list;
+}
+
+/*-------------------------------------------------------------------------*/
+/*-------------------------------------------------------------------------*/
+
+static void finish_urb(ohci_t *ohci, urb_priv_t *urb, int status)
+{
+	if((status & (ED_OPER | ED_UNLINK)) && (urb->state != URB_DEL))
+		urb->finished = sohci_return_job(ohci, urb);
+	else
+		DEBUG_HOST("finish_urb: strange.., ED state %x, \r\n", status);
+}
+
+/*
+ * Used to take back a TD from the host controller. This would normally be
+ * called from within dl_done_list, however it may be called directly if the
+ * HC no longer sees the TD and it has not appeared on the donelist (after
+ * two frames).  This bug has been observed on ZF Micro systems.
+ */
+int takeback_td(ohci_t *ohci, td_t *td_list)
+{
+	ed_t *ed;
+	int cc;
+	int stat = 0;
+	/* urb_t *urb; */
+	urb_priv_t *lurb_priv;
+	__u32 tdINFO, edHeadP, edTailP;
+	tdINFO = m32_swap(td_list->hwINFO);
+	ed = td_list->ed;
+	lurb_priv = ed->purb;
+	dl_transfer_length(td_list);
+	lurb_priv->td_cnt++;
+	/* error code of transfer */
+	cc = TD_CC_GET(tdINFO);
+	if(cc)
+	{
+		err("USB-error: %s (%x)", cc_to_string[cc], cc);
+		stat = cc_to_error[cc];
+	}
+	/* see if this done list makes for all TD's of current URB,
+	* and mark the URB finished if so */
+	if(lurb_priv->td_cnt == lurb_priv->length)
+		finish_urb(ohci, lurb_priv, ed->state);
+	DEBUG_HOST("dl_done_list: processing TD %x, len %x\r\n",
+		lurb_priv->td_cnt, lurb_priv->length);
+	if(ed->state != ED_NEW && (!usb_pipeint(lurb_priv->pipe)))
+	{
+		edHeadP = m32_swap(ed->hwHeadP) & ~0xf;
+		edTailP = m32_swap(ed->hwTailP);
+		/* unlink eds if they are not busy */
+		if((edHeadP == edTailP) && (ed->state == ED_OPER))
+			ep_unlink(ohci, ed);
+	}
+	return stat;
+}
+
+int dl_done_list(ohci_t *ohci)
+{
+	int stat = 0;
+	td_t *td_list = dl_reverse_done_list(ohci);
+	while(td_list)
+	{
+		td_t *td_next = td_list->next_dl_td;
+		stat = takeback_td(ohci, td_list);
+		td_list = td_next;
+	}
+	return stat;
+}
+
+/*-------------------------------------------------------------------------*
+ * Virtual Root Hub
+ *-------------------------------------------------------------------------*/
+
+/* Device descriptor */
+static __u8 root_hub_dev_des[] =
+{
+	0x12,	    /*	__u8  bLength; */
+	0x01,	    /*	__u8  bDescriptorType; Device */
+	0x10,	    /*	__u16 bcdUSB; v1.1 */
+	0x01,
+	0x09,	    /*	__u8  bDeviceClass; HUB_CLASSCODE */
+	0x00,	    /*	__u8  bDeviceSubClass; */
+	0x00,	    /*	__u8  bDeviceProtocol; */
+	0x08,	    /*	__u8  bMaxPacketSize0; 8 Bytes */
+	0x00,	    /*	__u16 idVendor; */
+	0x00,
+	0x00,	    /*	__u16 idProduct; */
+	0x00,
+	0x00,	    /*	__u16 bcdDevice; */
+	0x00,
+	0x00,	    /*	__u8  iManufacturer; */
+	0x01,	    /*	__u8  iProduct; */
+	0x00,	    /*	__u8  iSerialNumber; */
+	0x01	    /*	__u8  bNumConfigurations; */
+};
+
+/* Configuration descriptor */
+static __u8 root_hub_config_des[] =
+{
+	0x09,	    /*	__u8  bLength; */
+	0x02,	    /*	__u8  bDescriptorType; Configuration */
+	0x19,	    /*	__u16 wTotalLength; */
+	0x00,
+	0x01,	    /*	__u8  bNumInterfaces; */
+	0x01,	    /*	__u8  bConfigurationValue; */
+	0x00,	    /*	__u8  iConfiguration; */
+	0x40,	    /*	__u8  bmAttributes;
+	 Bit 7: Bus-powered, 6: Self-powered, 5 Remote-wakwup, 4..0: resvd */
+	0x00,	    /*	__u8  MaxPower; */
+
+	/* interface */
+	0x09,	    /*	__u8  if_bLength; */
+	0x04,	    /*	__u8  if_bDescriptorType; Interface */
+	0x00,	    /*	__u8  if_bInterfaceNumber; */
+	0x00,	    /*	__u8  if_bAlternateSetting; */
+	0x01,	    /*	__u8  if_bNumEndpoints; */
+	0x09,	    /*	__u8  if_bInterfaceClass; HUB_CLASSCODE */
+	0x00,	    /*	__u8  if_bInterfaceSubClass; */
+	0x00,	    /*	__u8  if_bInterfaceProtocol; */
+	0x00,	    /*	__u8  if_iInterface; */
+
+	/* endpoint */
+	0x07,	    /*	__u8  ep_bLength; */
+	0x05,	    /*	__u8  ep_bDescriptorType; Endpoint */
+	0x81,	    /*	__u8  ep_bEndpointAddress; IN Endpoint 1 */
+	0x03,	    /*	__u8  ep_bmAttributes; Interrupt */
+	0x02,	    /*	__u16 ep_wMaxPacketSize; ((MAX_ROOT_PORTS + 1) / 8 */
+	0x00,
+	0xff	    /*	__u8  ep_bInterval; 255 ms */
+};
+
+static unsigned char root_hub_str_index0[] =
+{
+	0x04,			/*  __u8  bLength; */
+	0x03,			/*  __u8  bDescriptorType; String-descriptor */
+	0x09,			/*  __u8  lang ID */
+	0x04,			/*  __u8  lang ID */
+};
+
+static unsigned char root_hub_str_index1[] =
+{
+	28,			/*  __u8  bLength; */
+	0x03,			/*  __u8  bDescriptorType; String-descriptor */
+	'O',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	'H',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	'C',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	'I',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	' ',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	'R',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	'o',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	'o',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	't',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	' ',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	'H',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	'u',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+	'b',			/*  __u8  Unicode */
+	0,				/*  __u8  Unicode */
+};
+
+/* Hub class-specific descriptor is constructed dynamically */
+
+/*-------------------------------------------------------------------------*/
+
+#define OK(x)			len = (x); break
+#if DEBUG_HOST_LAYER
+#define WR_RH_STAT(x)		{info("WR:status %#8x", (x)); writel((x), \
+						&gohci.regs->roothub.status); }
+#define WR_RH_PORTSTAT(x)	{info("WR:portstatus[%d] %#8x", wIndex-1, \
+		(x)); writel((x), &gohci.regs->roothub.portstatus[wIndex-1]); }
+#else
+#define WR_RH_STAT(x)		writel((x), &gohci.regs->roothub.status)
+#define WR_RH_PORTSTAT(x)	writel((x), \
+				    &gohci.regs->roothub.portstatus[wIndex-1])
+#endif
+#define RD_RH_STAT		roothub_status(&gohci)
+#define RD_RH_PORTSTAT		roothub_portstatus(&gohci, wIndex-1)
+
+/* request to virtual root hub */
+
+int rh_check_port_status(ohci_t *controller)
+{
+	__u32 temp, ndp, i;
+	int res = -1;
+	temp = roothub_a(controller);
+	ndp = (temp & RH_A_NDP);
+	for (i = 0; i < ndp; i++) {
+		temp = roothub_portstatus(controller, i);
+		/* check for a device disconnect */
+		if (((temp & (RH_PS_PESC | RH_PS_CSC)) ==
+			(RH_PS_PESC | RH_PS_CSC)) &&
+			((temp & RH_PS_CCS) == 0)) {
+			res = i;
+			break;
+		}
+	}
+	return res;
+}
+
+static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
+		void *buffer, int transfer_len, struct devrequest *cmd)
+{
+	void *data = buffer;
+	int leni = transfer_len;
+	int len = 0;
+	int stat = 0;
+	__u32 datab[4];
+	__u8 *data_buf = (__u8 *)datab;
+	__u16 bmRType_bReq;
+	__u16 wValue;
+	__u16 wIndex;
+	__u16 wLength;
+#if DEBUG_HOST_LAYER
+	pkt_print(NULL, dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));
+#else
+//	wait_ms(1);
+#endif
+	if(usb_pipeint(pipe))
+	{
+		info("Root-Hub submit IRQ: NOT implemented");
+		return 0;
+	}
+	bmRType_bReq  = cmd->requesttype | (cmd->request << 8);
+	wValue	      = le16_to_cpu(cmd->value);
+	wIndex	      = le16_to_cpu(cmd->index);
+	wLength	      = le16_to_cpu(cmd->length);
+	info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",
+		dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);
+	switch(bmRType_bReq)
+	{
+		/* Request Destination:
+		   without flags: Device,
+		   RH_INTERFACE: interface,
+		   RH_ENDPOINT: endpoint,
+		   RH_CLASS means HUB here,
+		   RH_OTHER | RH_CLASS	almost ever means HUB_PORT here
+		*/
+		case RH_GET_STATUS:
+			*(__u16 *)data_buf = cpu_to_le16(1);
+			OK(2);
+		case RH_GET_STATUS | RH_INTERFACE:
+			*(__u16 *)data_buf = cpu_to_le16(0);
+			OK(2);
+		case RH_GET_STATUS | RH_ENDPOINT:
+			*(__u16 *)data_buf = cpu_to_le16(0);
+			OK(2);
+		case RH_GET_STATUS | RH_CLASS:
+			*(__u32 *)data_buf = cpu_to_le32(RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE));
+			OK(4);
+		case RH_GET_STATUS | RH_OTHER | RH_CLASS:
+			*(__u32 *)data_buf = cpu_to_le32(RD_RH_PORTSTAT);
+			OK(4);
+		case RH_CLEAR_FEATURE | RH_ENDPOINT:
+			switch(wValue)
+			{
+				case (RH_ENDPOINT_STALL): OK(0);
+			}
+			break;
+		case RH_CLEAR_FEATURE | RH_CLASS:
+			switch(wValue)
+			{
+				case RH_C_HUB_LOCAL_POWER: OK(0);
+				case (RH_C_HUB_OVER_CURRENT): WR_RH_STAT(RH_HS_OCIC); OK(0);
+			}
+			break;
+		case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
+			switch(wValue)
+			{
+				case (RH_PORT_ENABLE):        WR_RH_PORTSTAT(RH_PS_CCS);  OK(0);
+				case (RH_PORT_SUSPEND):       WR_RH_PORTSTAT(RH_PS_POCI); OK(0);
+				case (RH_PORT_POWER):         WR_RH_PORTSTAT(RH_PS_LSDA); OK(0);
+				case (RH_C_PORT_CONNECTION):  WR_RH_PORTSTAT(RH_PS_CSC);  OK(0);
+				case (RH_C_PORT_ENABLE):      WR_RH_PORTSTAT(RH_PS_PESC); OK(0);
+				case (RH_C_PORT_SUSPEND):     WR_RH_PORTSTAT(RH_PS_PSSC); OK(0);
+				case (RH_C_PORT_OVER_CURRENT):WR_RH_PORTSTAT(RH_PS_OCIC); OK(0);
+				case (RH_C_PORT_RESET):       WR_RH_PORTSTAT(RH_PS_PRSC); OK(0);
+			}
+			break;
+		case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
+			switch(wValue)
+			{
+				case (RH_PORT_SUSPEND): WR_RH_PORTSTAT(RH_PS_PSS);  OK(0);
+				case (RH_PORT_RESET): /* BUG IN HUP CODE *********/
+					if(RD_RH_PORTSTAT & RH_PS_CCS)
+						WR_RH_PORTSTAT(RH_PS_PRS);
+					OK(0);
+				case (RH_PORT_POWER): WR_RH_PORTSTAT(RH_PS_PPS); wait_ms(100); OK(0);
+				case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/
+					if(RD_RH_PORTSTAT & RH_PS_CCS)
+						WR_RH_PORTSTAT(RH_PS_PES);
+					OK(0);
+			}
+			break;
+		case RH_SET_ADDRESS:
+			gohci.rh.devnum = wValue;
+			OK(0);
+		case RH_GET_DESCRIPTOR:
+			switch((wValue & 0xff00) >> 8)
+			{
+				case(0x01): /* device descriptor */
+					len = min_t(unsigned int, leni, min2_t(unsigned int, sizeof(root_hub_dev_des), wLength));
+					data_buf = root_hub_dev_des;
+					OK(len);
+				case(0x02): /* configuration descriptor */
+					len = min_t(unsigned int, leni, min2_t(unsigned int, sizeof(root_hub_config_des), wLength));
+					data_buf = root_hub_config_des;
+					OK(len);
+				case(0x03): /* string descriptors */
+					if(wValue == 0x0300)
+					{
+						len = min_t(unsigned int, leni, min2_t(unsigned int, sizeof(root_hub_str_index0), wLength));
+						data_buf = root_hub_str_index0;
+						OK(len);
+					}
+					if(wValue == 0x0301)
+					{
+						len = min_t(unsigned int, leni, min2_t(unsigned int, sizeof(root_hub_str_index1), wLength));
+						data_buf = root_hub_str_index1;
+						OK(len);
+					}
+				default:
+					stat = USB_ST_STALLED;
+			}
+			break;
+		case RH_GET_DESCRIPTOR | RH_CLASS:
+		{
+			__u32 temp = roothub_a(&gohci);
+			data_buf[0] = 9;		/* min length; */
+			data_buf[1] = 0x29;
+			data_buf[2] = temp & RH_A_NDP;
+			data_buf[3] = 0;
+			if(temp & RH_A_PSM)	/* per-port power switching? */
+				data_buf[3] |= 0x1;
+			if(temp & RH_A_NOCP)	/* no overcurrent reporting? */
+				data_buf[3] |= 0x10;
+			else if(temp & RH_A_OCPM) /* per-port overcurrent reporting? */
+				data_buf[3] |= 0x8;
+			/* corresponds to data_buf[4-7] */
+			datab[1] = 0;
+			data_buf[5] = (temp & RH_A_POTPGT) >> 24;
+			temp = roothub_b(&gohci);
+			data_buf[7] = temp & RH_B_DR;
+			if(data_buf[2] < 7)
+				data_buf[8] = 0xff;
+			else
+			{
+				data_buf[0] += 2;
+				data_buf[8] = (temp & RH_B_DR) >> 8;
+				data_buf[10] = data_buf[9] = 0xff;
+			}
+			len = min_t(unsigned int, leni, min2_t(unsigned int, data_buf [0], wLength));
+			OK(len);
+		}
+		case RH_GET_CONFIGURATION:	*(__u8 *) data_buf = 0x01; OK(1);
+		case RH_SET_CONFIGURATION:	WR_RH_STAT(0x10000); OK(0);
+		default:
+			DEBUG_HOST("unsupported root hub command");
+			stat = USB_ST_STALLED;
+	}
+#if DEBUG_HOST_LAYER
+	ohci_dump_roothub(&gohci, 1);
+#else
+//	wait_ms(1);
+#endif
+	len = min_t(int, len, leni);
+	if(data != data_buf)
+		memcpy(data, data_buf, len);
+	dev->act_len = len;
+	dev->status = stat;
+#if DEBUG_HOST_LAYER
+	pkt_print(NULL, dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/);
+#else
+//	wait_ms(1);
+#endif
+	return stat;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* common code for handling submit messages - used for all but root hub accesses. */
+
+int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+		int transfer_len, struct devrequest *setup, int interval)
+{
+	int stat = 0;
+	int maxsize = usb_maxpacket(dev, pipe);
+	int timeout;
+	urb_priv_t *urb;
+	urb = (urb_priv_t *)usb_malloc(sizeof(urb_priv_t));
+	if(urb == NULL)
+	{
+		err("submit_common_msg malloc failed");
+		return -1;
+	}
+	memset(urb, 0, sizeof(urb_priv_t));
+	urb->dev = dev;
+	urb->pipe = pipe;
+	urb->transfer_buffer = buffer;
+	urb->transfer_buffer_length = transfer_len;
+	urb->interval = interval;
+	/* device pulled? Shortcut the action. */
+	if(devgone == dev)
+	{
+		dev->status = USB_ST_CRC_ERR;
+		return 0;
+	}
+#if DEBUG_HOST_LAYER
+	urb->actual_length = 0;
+	pkt_print(urb, dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
+#else
+//	wait_ms(1);
+#endif
+	if(!maxsize)
+	{
+		err("submit_common_message: pipesize for pipe %lx is zero", pipe);
+		return -1;
+	}
+	if(sohci_submit_job(urb, setup) < 0)
+	{
+		err("sohci_submit_job failed");
+		return -1;
+	}
+#if 0
+	wait_ms(10);
+	/* ohci_dump_status(&gohci); */
+#endif
+	/* allow more time for a BULK device to react - some are slow */
+#define BULK_TO	 5000	/* timeout in milliseconds */
+	if(usb_pipebulk(pipe))
+		timeout = BULK_TO;
+	else
+		timeout = 100;
+	/* wait for it to complete */
+	while(1)
+	{
+		/* check whether the controller is done */
+#ifdef COLDFIRE /* no bus snooping on Coldfire */
+#ifdef NETWORK
+#ifdef LWIP
+		extern unsigned long pxCurrentTCB, tid_TOS;
+		extern void flush_caches(void);
+		if(pxCurrentTCB != tid_TOS)
+			flush_caches();
+		else
+#endif /* LWIP */
+#endif /* NETWORK */
+			asm(" .chip 68060\n cpusha DC\n .chip 5200\n");
+#endif /* COLDFIRE */
+		stat = hc_interrupt();
+		if(stat < 0)
+		{
+			stat = USB_ST_CRC_ERR;
+			break;
+		}
+		/* NOTE: since we are not interrupt driven in U-Boot and always
+		 * handle only one URB at a time, we cannot assume the
+		 * transaction finished on the first successful return from
+		 * hc_interrupt().. unless the flag for current URB is set,
+		 * meaning that all TD's to/from device got actually
+		 * transferred and processed. If the current URB is not
+		 * finished we need to re-iterate this loop so as
+		 * hc_interrupt() gets called again as there needs to be some
+		 * more TD's to process still */
+		if((stat >= 0) && (stat != 0xff) && (urb->finished))
+		{
+			/* 0xff is returned for an SF-interrupt */
+			break;
+		}
+		if(--timeout)
+		{
+			wait_ms(1);
+			if(!urb->finished)
+				DEBUG_HOST("*");
+		}
+		else
+		{
+			err("CTL:TIMEOUT ");
+			DEBUG_HOST("submit_common_msg: TO status %x\r\n", stat);
+			urb->finished = 1;
+			stat = USB_ST_CRC_ERR;
+			break;
+		}
+	}
+	dev->status = stat;
+	dev->act_len = transfer_len;
+#if DEBUG_HOST_LAYER
+	pkt_print(urb, dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe));
+#else
+//	wait_ms(1);
+#endif
+	/* free TDs in urb_priv */
+	if(!usb_pipeint(pipe))
+		urb_free_priv(urb);
+	return 0;
+}
+
+/* submit routines called from usb.c */
+int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer, int transfer_len)
+{
+	info("submit_bulk_msg");
+	return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0);
+}
+
+int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, int transfer_len, struct devrequest *setup)
+{
+	int maxsize = usb_maxpacket(dev, pipe);
+	info("submit_control_msg");
+#if DEBUG_HOST_LAYER
+	pkt_print(NULL, dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
+#else
+//	wait_ms(1);
+#endif
+	if(!maxsize)
+	{
+		err("submit_control_message: pipesize for pipe %lx is zero", pipe);
+		return -1;
+	}
+	if(((pipe >> 8) & 0x7f) == gohci.rh.devnum)
+	{
+		gohci.rh.dev = dev;
+		/* root hub - redirect */
+		return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len, setup);
+	}
+	return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0);
+}
+
+int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, int transfer_len, int interval)
+{
+	info("submit_int_msg");
+	return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, interval);
+}
+
+/*-------------------------------------------------------------------------*
+ * HC functions
+ *-------------------------------------------------------------------------*/
+
+/* reset the HC and BUS */
+
+static int hc_reset(ohci_t *ohci)
+{
+	int timeout = 30;
+	int smm_timeout = 50; /* 0,5 sec */
+	DEBUG_HOST("%s\r\n", __FUNCTION__);
+	if(readl(&ohci->regs->control) & OHCI_CTRL_IR)
+	{
+		/* SMM owns the HC */
+		writel(OHCI_OCR, &ohci->regs->cmdstatus);/* request ownership */
+		info("USB HC TakeOver from SMM");
+		while(readl(&ohci->regs->control) & OHCI_CTRL_IR)
+		{
+			wait_ms(10);
+			if(--smm_timeout == 0)
+			{
+				err("USB HC TakeOver failed!");
+				return -1;
+			}
+		}
+	}
+	/* Disable HC interrupts */
+	writel(OHCI_INTR_MIE, &ohci->regs->intrdisable);
+	DEBUG_HOST("USB HC reset_hc usb-%s: ctrl = 0x%X ;\r\n", ohci->slot_name, readl(&ohci->regs->control));
+	/* Reset USB (needed by some controllers) */
+	ohci->hc_control = 0;
+	writel(ohci->hc_control, &ohci->regs->control);
+	/* HC Reset requires max 10 us delay */
+	writel(OHCI_HCR,  &ohci->regs->cmdstatus);
+	while((readl(&ohci->regs->cmdstatus) & OHCI_HCR) != 0)
+	{
+		if(--timeout == 0)
+		{
+			err("USB HC reset timed out!");
+			return -1;
+		}
+		udelay(1);
+	}
+	return 0;
+}
+
+/*-------------------------------------------------------------------------*/
+
+/* Start an OHCI controller, set the BUS operational
+ * enable interrupts
+ * connect the virtual root hub */
+
+static int hc_start(ohci_t *ohci)
+{
+	__u32 mask;
+	unsigned int fminterval;
+	ohci->disabled = 1;
+	/* Tell the controller where the control and bulk lists are
+	 * The lists are empty now. */
+	writel(0, &ohci->regs->ed_controlhead);
+	writel(0, &ohci->regs->ed_bulkhead);
+	writel((__u32)ohci->hcca - ohci->dma_offset, &ohci->regs->hcca); /* a reset clears this */
+	fminterval = 0x2edf;
+	writel((fminterval * 9) / 10, &ohci->regs->periodicstart);
+	fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
+	writel(fminterval, &ohci->regs->fminterval);
+	writel(0x628, &ohci->regs->lsthresh);
+	/* start controller operations */
+	ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
+	ohci->disabled = 0;
+	writel(ohci->hc_control, &ohci->regs->control);
+	/* disable all interrupts */
+	mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD |
+			OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC | OHCI_INTR_OC | OHCI_INTR_MIE);
+	writel(mask, &ohci->regs->intrdisable);
+	/* clear all interrupts */
+	mask &= ~OHCI_INTR_MIE;
+	writel(mask, &ohci->regs->intrstatus);
+	/* Choose the interrupts we care about now  - but w/o MIE */
+	mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;
+	writel(mask, &ohci->regs->intrenable);
+#ifdef OHCI_USE_NPS
+	/* required for AMD-756 and some Mac platforms */
+	writel((roothub_a(ohci) | RH_A_NPS) & ~RH_A_PSM, &ohci->regs->roothub.a);
+	writel(RH_HS_LPSC, &ohci->regs->roothub.status);
+#endif /* OHCI_USE_NPS */
+#define mdelay(n) ({unsigned long msec = (n); while (msec--) udelay(1000); })
+	/* POTPGT delay is bits 24-31, in 2 ms units. */
+	mdelay((roothub_a(ohci) >> 23) & 0x1fe);
+	/* connect the virtual root hub */
+	ohci->rh.devnum = 0;
+	return 0;
+}
+
+/*-------------------------------------------------------------------------*/
+
+#ifdef CONFIG_USB_INTERRUPT_POLLING
+
+/* Poll USB interrupt. */
+void usb_event_poll(void)
+{
+	if(ohci_inited)
+	{
+#ifdef COLDFIRE /* no bus snooping on Coldfire */
+#ifdef NETWORK
+#ifdef LWIP
+		extern unsigned long pxCurrentTCB, tid_TOS;
+		extern void flush_caches(void);
+		if(pxCurrentTCB != tid_TOS)
+			flush_caches();
+		else
+#endif /* LWIP */
+#endif /* NETWORK */
+		asm(" .chip 68060\n cpusha DC\n .chip 5200\n");
+#endif /* COLDFIRE */
+		hc_interrupt();
+	}
+}
+
+#endif /* CONFIG_USB_INTERRUPT_POLLING */
+
+/* an interrupt happens */
+static int hc_interrupt(void)
+{
+	ohci_t *ohci = &gohci;
+	struct ohci_regs *regs = ohci->regs;
+	int ints, stat = -1;
+	if((ohci->hcca->done_head != 0) && !(m32_swap(ohci->hcca->done_head) & 0x01))
+		ints =  OHCI_INTR_WDH;
+	else
+	{
+		ints = readl(&regs->intrstatus);
+		if(ints == ~(u32)0)
+		{
+			ohci->disabled++;
+			err("%s device removed!", ohci->slot_name);
+			return -1;
+		}
+		else
+		{
+			ints &= readl(&regs->intrenable);
+			if(ints == 0)
+			{
+//				DEBUG_HOST("hc_interrupt: returning..\r\n");
+				return 0xff;
+			}
+		}
+	}
+  DEBUG_HOST("Interrupt: 0x%x frame: 0x%x", ints, le16_to_cpu(ohci->hcca->frame_no));
+	if(ints & OHCI_INTR_RHSC)
+	{
+		stat = 0xff;
+	}
+	if(ints & OHCI_INTR_UE)
+	{
+		ohci->disabled++;
+		err("OHCI Unrecoverable Error, controller usb-%s disabled", ohci->slot_name);
+		/* e.g. due to PCI Master/Target Abort */
+#if DEBUG_HOST_LAYER
+		ohci_dump(ohci, 1);
+#else
+//		wait_ms(1);
+#endif
+		/* FIXME: be optimistic, hope that bug won't repeat often. */
+		/* Make some non-interrupt context restart the controller. */
+		/* Count and limit the retries though; either hardware or */
+		/* software errors can go forever... */
+		hc_reset(ohci);
+		return -1;
+	}
+	if(ints & OHCI_INTR_WDH)
+	{
+//		wait_ms(1);
+		writel(OHCI_INTR_WDH, &regs->intrdisable);
+		(void)readl(&regs->intrdisable); /* flush */
+		stat = dl_done_list(&gohci);
+		writel(OHCI_INTR_WDH, &regs->intrenable);
+		(void)readl(&regs->intrdisable); /* flush */
+	}
+	if(ints & OHCI_INTR_SO)
+	{
+		DEBUG_HOST("USB Schedule overrun\r\n");
+		writel(OHCI_INTR_SO, &regs->intrenable);
+		stat = -1;
+	}
+	/* FIXME:  this assumes SOF (1/ms) interrupts don't get lost... */
+	if(ints & OHCI_INTR_SF)
+	{
+		unsigned int frame = m16_swap(ohci->hcca->frame_no) & 1;
+//		wait_ms(1);
+		writel(OHCI_INTR_SF, &regs->intrdisable);
+		if(ohci->ed_rm_list[frame] != NULL)
+			writel(OHCI_INTR_SF, &regs->intrenable);
+		stat = 0xff;
+	}
+	writel(ints, &regs->intrstatus);
+	return stat;
+}
+
+#ifndef CONFIG_USB_INTERRUPT_POLLING
+
+static int handle_usb_interrupt(void)
+{
+#ifdef COLDFIRE /* no bus snooping on Coldfire */
+	extern void flush_caches(void);
+	conout_debug('.');
+	flush_caches(); /* native interrupt */
+#endif /* COLDFIRE */
+	gohci.irq = 0;
+	hc_interrupt();
+	gohci.irq = -1;
+	return 1; /* clear interrupt, 0: disable interrupt */
+}
+
+void usb_enable_interrupt(int enable)
+{
+	ohci_t *ohci = &gohci;
+	if(enable)
+		writel(OHCI_INTR_MIE, &ohci->regs->intrenable);
+	else
+		writel(OHCI_INTR_MIE, &ohci->regs->intrdisable);
+}
+
+#endif /* !CONFIG_USB_INTERRUPT_POLLING */
+
+/*-------------------------------------------------------------------------*/
+
+/*-------------------------------------------------------------------------*/
+
+/* De-allocate all resources.. */
+
+static void hc_release_ohci(ohci_t *ohci)
+{
+	DEBUG_HOST("USB HC release ohci usb-%s", ohci->slot_name);
+	if(!ohci->disabled)
+		hc_reset(ohci);
+}
+
+static void hc_free_buffers(ohci_t *ohci)
+{
+	if(ohci->td_unaligned != NULL)
+	{
+		usb_free(ohci->td_unaligned);
+		ohci->td_unaligned = NULL;
+	}
+	if(ohci->ohci_dev_unaligned != NULL)
+	{
+		usb_free(ohci->ohci_dev_unaligned);
+		ohci->ohci_dev_unaligned = NULL;
+	}
+	if(ohci->hcca_unaligned  != NULL)
+	{
+		usb_free(ohci->hcca_unaligned);
+		ohci->hcca_unaligned = NULL;
+	}
+}
+
+/*-------------------------------------------------------------------------*/
+
+/*
+ * low level initalisation routine, called from usb.c
+ */
+int usb_lowlevel_init(long handle, const struct pci_device_id *ent)
+{
+	char buf[16];
+	unsigned long usb_base_addr = 0xFFFFFFFF;
+	PCI_RSC_DESC *pci_rsc_desc;
+#ifdef PCI_XBIOS
+	pci_rsc_desc = (PCI_RSC_DESC *)get_resource(handle); /* USB OHCI */
+#else
+	COOKIE *p = get_cookie('_PCI'); 
+  	PCI_COOKIE *bios_cookie = (PCI_COOKIE *)p->v.l;
+	if(bios_cookie == NULL)   /* faster than XBIOS calls */
+		return(-1);	
+	tab_funcs_pci = &bios_cookie->routine[0];
+	pci_rsc_desc = (PCI_RSC_DESC *)Get_resource(handle); /* USB OHCI */
+#endif
+	if(handle && (ent != NULL))
+	{
+		memset(&gohci, 0, sizeof(ohci_t));
+		gohci.handle = handle;
+	}
+	else if(!gohci.handle) /* for restart USB cmd */
+		return(-1);	
+	/* this must be aligned to a 256 byte boundary */
+	gohci.hcca_unaligned = (struct ohci_hcca *)usb_malloc(sizeof(struct ohci_hcca) + 256);
+	if(gohci.hcca_unaligned == NULL)
+	{
+		err("HCCA malloc failed");
+		return -1;
+	}
+	/* align the storage */
+	gohci.hcca = (struct ohci_hcca *)(((unsigned long)gohci.hcca_unaligned + 255) & ~255);
+	memset(gohci.hcca, 0, sizeof(struct ohci_hcca));
+	info("aligned ghcca 0x%p", gohci.hcca);
+	gohci.ohci_dev_unaligned = (struct ohci_device *)usb_malloc(sizeof(struct ohci_device) + 8);
+	if(gohci.ohci_dev_unaligned == NULL)
+	{
+		err("EDs malloc failed");
+		hc_free_buffers(&gohci);
+		return -1;
+	}
+	gohci.ohci_dev = (struct ohci_device *)(((unsigned long)gohci.ohci_dev_unaligned + 7) & ~7);
+	memset(gohci.ohci_dev, 0, sizeof(struct ohci_device));
+	info("aligned EDs 0x%p", gohci.ohci_dev);
+	gohci.td_unaligned = (td_t *)usb_malloc(sizeof(td_t) * (NUM_TD + 1));
+	if(gohci.td_unaligned == NULL)
+	{
+		err("TDs malloc failed");
+		hc_free_buffers(&gohci);
+		return -1;
+	}
+	ptd = (td_t *)(((unsigned long)gohci.td_unaligned + 7) & ~7);
+	memset(ptd, 0, sizeof(td_t) * NUM_TD);
+	info("aligned TDs 0x%p", ptd);
+	gohci.disabled = 1;
+	gohci.sleeping = 0;
+	gohci.irq = -1;
+	if((long)pci_rsc_desc >= 0)
+	{
+		unsigned short flags;
+		do
+		{
+			DEBUG_HOST("PCI USB descriptors: flags 0x%08x start 0x%08x \r\n offset 0x%08x dmaoffset 0x%08x length 0x%08x",
+				 pci_rsc_desc->flags, pci_rsc_desc->start, pci_rsc_desc->offset, pci_rsc_desc->dmaoffset, pci_rsc_desc->length);
+			if(!(pci_rsc_desc->flags & FLG_IO))
+			{
+				if(usb_base_addr == 0xFFFFFFFF)
+				{
+					usb_base_addr = pci_rsc_desc->start;
+					gohci.regs = (void *)(pci_rsc_desc->offset + pci_rsc_desc->start);
+					gohci.dma_offset = pci_rsc_desc->dmaoffset;
+					if((pci_rsc_desc->flags & FLG_ENDMASK) == ORD_MOTOROLA)
+						gohci.big_endian = 0; /* host bridge make swapping intel -> motorola */
+					else
+						gohci.big_endian = 1; /* driver must swapping intel -> motorola */
+				}
+			}
+			flags = pci_rsc_desc->flags;
+			pci_rsc_desc += (unsigned long)pci_rsc_desc->next;
+		}
+		while(!(flags & FLG_LAST));
+	}
+	else
+	{
+		hc_free_buffers(&gohci);
+		return(-1); /* get_resource error */
+	}
+	if(usb_base_addr == 0xFFFFFFFF)
+	{
+		hc_free_buffers(&gohci);
+		return(-1);
+	}
+	if(handle && (ent != NULL))
+	{
+		switch(ent->vendor)
+		{
+			case PCI_VENDOR_ID_AL: gohci.slot_name = "uli1575"; break;
+			case PCI_VENDOR_ID_NEC: gohci.slot_name = "uPD720101"; break;
+			case PCI_VENDOR_ID_PHILIPS: gohci.slot_name = "isp1561"; break;
+			default: gohci.slot_name = "generic"; break;
+		}
+	}
+	(void) Cconws("OHCI usb-");
+	(void) Cconws(gohci.slot_name);
+	(void) Cconws(", regs address 0x");
+	ltoa(buf, (long)gohci.regs, 16);
+	(void) Cconws(buf);
+	(void) Cconws(", PCI handle 0x");
+	ltoa(buf, handle, 16);
+	(void) Cconws(buf);
+	(void) Cconws("\r\n");
+	gohci.flags = 0;
+	if(hc_reset(&gohci) < 0)
+	{
+		err("Can't reset usb-%s", gohci.slot_name);
+		hc_release_ohci(&gohci);
+		hc_free_buffers(&gohci);
+		return -1;
+	}
+	if(hc_start(&gohci) < 0)
+	{
+		err("Can't start usb-%s", gohci.slot_name);
+		hc_release_ohci(&gohci);
+		hc_free_buffers(&gohci);
+		/* Initialization failed */
+		return -1;
+	}
+#if DEBUG_HOST_LAYER
+	ohci_dump(&gohci, 1);
+#else
+//	wait_ms(1);
+#endif
+#ifndef CONFIG_USB_INTERRUPT_POLLING
+#ifdef PCI_XBIOS
+	hook_interrupt(handle, handle_usb_interrupt, NULL);
+#else
+	Hook_interrupt(handle, (void *)handle_usb_interrupt, NULL);
+#endif /* PCI_BIOS */
+#endif /* CONFIG_USB_INTERRUPT_POLLING */
+	ohci_inited = 1;
+	return 0;
+}
+
+int usb_lowlevel_stop(void)
+{
+	/* this gets called really early - before the controller has */
+	/* even been initialized! */
+	if(!ohci_inited)
+		return 0;
+#ifndef CONFIG_USB_INTERRUPT_POLLING
+#ifdef PCI_XBIOS
+	unhook_interrupt(gohci.handle);
+#else
+	Unhook_interrupt(gohci.handle);
+#endif /* PCI_BIOS */
+#endif /* CONFIG_USB_INTERRUPT_POLLING */
+	/* call hc_release_ohci() here ? */
+	hc_reset(&gohci);
+	hc_free_buffers(&gohci);
+	/* This driver is no longer initialised. It needs a new low-level
+	 * init (board/cpu) before it can be used again. */
+	ohci_inited = 0;
+	return 0;
+}
diff --git a/FireBee/trunk/usb/store/host/ohci-pci/ohci.h b/FireBee/trunk/usb/store/host/ohci-pci/ohci.h
new file mode 100644
index 0000000..b07e3b2
--- /dev/null
+++ b/FireBee/trunk/usb/store/host/ohci-pci/ohci.h
@@ -0,0 +1,457 @@
+/*
+ * URB OHCI HCD (Host Controller Driver) for USB.
+ *
+ * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
+ * (C) Copyright 2000-2001 David Brownell <dbrownell@users.sourceforge.net>
+ *
+ * usb-ohci.h
+ */
+
+static int cc_to_error[16] = {
+
+/* mapping of the OHCI CC status to error codes */
+	/* No  Error  */	       0,
+	/* CRC Error  */	       USB_ST_CRC_ERR,
+	/* Bit Stuff  */	       USB_ST_BIT_ERR,
+	/* Data Togg  */	       USB_ST_CRC_ERR,
+	/* Stall      */	       USB_ST_STALLED,
+	/* DevNotResp */	       -1,
+	/* PIDCheck   */	       USB_ST_BIT_ERR,
+	/* UnExpPID   */	       USB_ST_BIT_ERR,
+	/* DataOver   */	       USB_ST_BUF_ERR,
+	/* DataUnder  */	       USB_ST_BUF_ERR,
+	/* reservd    */	       -1,
+	/* reservd    */	       -1,
+	/* BufferOver */	       USB_ST_BUF_ERR,
+	/* BuffUnder  */	       USB_ST_BUF_ERR,
+	/* Not Access */	       -1,
+	/* Not Access */	       -1
+};
+
+static const char *cc_to_string[16] = {
+	"No Error",
+	"CRC: Last data packet from endpoint contained a CRC error.",
+	"BITSTUFFING: Last data packet from endpoint contained a bit stuffing violation",
+	"DATATOGGLEMISMATCH: Last packet from endpoint had data toggle PID that did not match the expected value.",
+	"STALL: TD was moved to the Done Queue because the endpoint returned a STALL PID",
+	"DEVICENOTRESPONDING: Device did not respond to token (IN) or did not provide a handshake (OUT)",
+	"PIDCHECKFAILURE: Check bits on PID from endpoint failed on data PID (IN) or handshake (OUT)",
+	"UNEXPECTEDPID: Receive PID was not valid when encountered or PID value is not defined.",
+	"DATAOVERRUN: The amount of data returned by the endpoint exceeded either the size of the maximum data packet allowed from the endpoint (found in MaximumPacketSize field of ED) or the remaining buffer size.",
+	"DATAUNDERRUN: The endpoint returned less than MaximumPacketSize and that amount was not sufficient to fill the specified buffer",
+	"reserved1",
+	"reserved2",
+	"BUFFEROVERRUN: During an IN, HC received data from endpoint faster than it could be written to system memory",
+	"BUFFERUNDERRUN: During an OUT, HC could not retrieve data from system memory fast enough to keep up with data USB data rate.",
+	"NOT ACCESSED: This code is set by software before the TD is placed on a list to be processed by the HC.(1)",
+	"NOT ACCESSED: This code is set by software before the TD is placed on a list to be processed by the HC.(2)",
+};
+
+/* ED States */
+
+#define ED_NEW		0x00
+#define ED_UNLINK	0x01
+#define ED_OPER		0x02
+#define ED_DEL		0x04
+#define ED_URB_DEL	0x08
+
+/* usb_ohci_ed */
+struct ed {
+	__u32 hwINFO;
+	__u32 hwTailP;
+	__u32 hwHeadP;
+	__u32 hwNextED;
+
+	struct ed *ed_prev;
+	__u8 int_period;
+	__u8 int_branch;
+	__u8 int_load;
+	__u8 int_interval;
+	__u8 state;
+	__u8 type;
+	__u16 last_iso;
+	struct ed *ed_rm_list;
+
+	struct usb_device *usb_dev;
+	void *purb;
+	__u32 unused[2];
+} __attribute__((aligned(16)));
+typedef struct ed ed_t;
+
+
+/* TD info field */
+#define TD_CC	    0xf0000000
+#define TD_CC_GET(td_p) ((td_p >>28) & 0x0f)
+#define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28)
+#define TD_EC	    0x0C000000
+#define TD_T	    0x03000000
+#define TD_T_DATA0  0x02000000
+#define TD_T_DATA1  0x03000000
+#define TD_T_TOGGLE 0x00000000
+#define TD_R	    0x00040000
+#define TD_DI	    0x00E00000
+#define TD_DI_SET(X) (((X) & 0x07)<< 21)
+#define TD_DP	    0x00180000
+#define TD_DP_SETUP 0x00000000
+#define TD_DP_IN    0x00100000
+#define TD_DP_OUT   0x00080000
+
+#define TD_ISO	    0x00010000
+#define TD_DEL	    0x00020000
+
+/* CC Codes */
+#define TD_CC_NOERROR	   0x00
+#define TD_CC_CRC	   0x01
+#define TD_CC_BITSTUFFING  0x02
+#define TD_CC_DATATOGGLEM  0x03
+#define TD_CC_STALL	   0x04
+#define TD_DEVNOTRESP	   0x05
+#define TD_PIDCHECKFAIL	   0x06
+#define TD_UNEXPECTEDPID   0x07
+#define TD_DATAOVERRUN	   0x08
+#define TD_DATAUNDERRUN	   0x09
+#define TD_BUFFEROVERRUN   0x0C
+#define TD_BUFFERUNDERRUN  0x0D
+#define TD_NOTACCESSED	   0x0F
+
+
+#define MAXPSW 1
+
+struct td {
+	__u32 hwINFO;
+	__u32 hwCBP;		/* Current Buffer Pointer */
+	__u32 hwNextTD;		/* Next TD Pointer */
+	__u32 hwBE;		/* Memory Buffer End Pointer */
+
+	__u16 hwPSW[MAXPSW];
+	__u8 unused;
+	__u8 index;
+	struct ed *ed;
+	struct td *next_dl_td;
+	struct usb_device *usb_dev;
+	int transfer_len;
+	__u32 data;
+
+	__u32 unused2[2];
+} __attribute__((aligned(32)));
+typedef struct td td_t;
+
+#define OHCI_ED_SKIP	(1 << 14)
+
+/*
+ * The HCCA (Host Controller Communications Area) is a 256 byte
+ * structure defined in the OHCI spec. that the host controller is
+ * told the base address of.  It must be 256-byte aligned.
+ */
+
+#define NUM_INTS 32	/* part of the OHCI standard */
+struct ohci_hcca {
+	__u32	int_table[NUM_INTS];	/* Interrupt ED table */
+#if defined(CONFIG_MPC5200)
+	__u16	pad1;			/* set to 0 on each frame_no change */
+	__u16	frame_no;		/* current frame number */
+#else
+	__u16	frame_no;		/* current frame number */
+	__u16	pad1;			/* set to 0 on each frame_no change */
+#endif
+	__u32	done_head;		/* info returned for an interrupt */
+	u8		reserved_for_hc[116];
+} __attribute__((aligned(256)));
+
+
+/*
+ * Maximum number of root hub ports.
+ */
+#ifndef CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS
+# error "CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS undefined!"
+#endif
+
+/*
+ * This is the structure of the OHCI controller's memory mapped I/O
+ * region.  This is Memory Mapped I/O.	You must use the readl() and
+ * writel() macros defined in asm/io.h to access these!!
+ */
+struct ohci_regs {
+	/* control and status registers */
+	__u32	revision;
+	__u32	control;
+	__u32	cmdstatus;
+	__u32	intrstatus;
+	__u32	intrenable;
+	__u32	intrdisable;
+	/* memory pointers */
+	__u32	hcca;
+	__u32	ed_periodcurrent;
+	__u32	ed_controlhead;
+	__u32	ed_controlcurrent;
+	__u32	ed_bulkhead;
+	__u32	ed_bulkcurrent;
+	__u32	donehead;
+	/* frame counters */
+	__u32	fminterval;
+	__u32	fmremaining;
+	__u32	fmnumber;
+	__u32	periodicstart;
+	__u32	lsthresh;
+	/* Root hub ports */
+	struct	ohci_roothub_regs {
+		__u32	a;
+		__u32	b;
+		__u32	status;
+		__u32	portstatus[CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS];
+	} roothub;
+} __attribute__((aligned(32)));
+
+/* Some EHCI controls */
+#define EHCI_USBCMD_OFF		0x20
+#define EHCI_USBCMD_HCRESET	(1 << 1)
+
+/* OHCI CONTROL AND STATUS REGISTER MASKS */
+
+/*
+ * HcControl (control) register masks
+ */
+#define OHCI_CTRL_CBSR	(3 << 0)	/* control/bulk service ratio */
+#define OHCI_CTRL_PLE	(1 << 2)	/* periodic list enable */
+#define OHCI_CTRL_IE	(1 << 3)	/* isochronous enable */
+#define OHCI_CTRL_CLE	(1 << 4)	/* control list enable */
+#define OHCI_CTRL_BLE	(1 << 5)	/* bulk list enable */
+#define OHCI_CTRL_HCFS	(3 << 6)	/* host controller functional state */
+#define OHCI_CTRL_IR	(1 << 8)	/* interrupt routing */
+#define OHCI_CTRL_RWC	(1 << 9)	/* remote wakeup connected */
+#define OHCI_CTRL_RWE	(1 << 10)	/* remote wakeup enable */
+
+/* pre-shifted values for HCFS */
+#	define OHCI_USB_RESET	(0 << 6)
+#	define OHCI_USB_RESUME	(1 << 6)
+#	define OHCI_USB_OPER	(2 << 6)
+#	define OHCI_USB_SUSPEND (3 << 6)
+
+/*
+ * HcCommandStatus (cmdstatus) register masks
+ */
+#define OHCI_HCR	(1 << 0)	/* host controller reset */
+#define OHCI_CLF	(1 << 1)	/* control list filled */
+#define OHCI_BLF	(1 << 2)	/* bulk list filled */
+#define OHCI_OCR	(1 << 3)	/* ownership change request */
+#define OHCI_SOC	(3 << 16)	/* scheduling overrun count */
+
+/*
+ * masks used with interrupt registers:
+ * HcInterruptStatus (intrstatus)
+ * HcInterruptEnable (intrenable)
+ * HcInterruptDisable (intrdisable)
+ */
+#define OHCI_INTR_SO	(1 << 0)	/* scheduling overrun */
+#define OHCI_INTR_WDH	(1 << 1)	/* writeback of done_head */
+#define OHCI_INTR_SF	(1 << 2)	/* start frame */
+#define OHCI_INTR_RD	(1 << 3)	/* resume detect */
+#define OHCI_INTR_UE	(1 << 4)	/* unrecoverable error */
+#define OHCI_INTR_FNO	(1 << 5)	/* frame number overflow */
+#define OHCI_INTR_RHSC	(1 << 6)	/* root hub status change */
+#define OHCI_INTR_OC	(1 << 30)	/* ownership change */
+#define OHCI_INTR_MIE	(1 << 31)	/* master interrupt enable */
+
+
+/* Virtual Root HUB */
+struct virt_root_hub {
+	int devnum; /* Address of Root Hub endpoint */
+	void *dev;  /* was urb */
+	void *int_addr;
+	int send;
+	int interval;
+};
+
+/* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */
+
+/* destination of request */
+#define RH_INTERFACE		   0x01
+#define RH_ENDPOINT		   0x02
+#define RH_OTHER		   0x03
+
+#define RH_CLASS		   0x20
+#define RH_VENDOR		   0x40
+
+/* Requests: bRequest << 8 | bmRequestType */
+#define RH_GET_STATUS		0x0080
+#define RH_CLEAR_FEATURE	0x0100
+#define RH_SET_FEATURE		0x0300
+#define RH_SET_ADDRESS		0x0500
+#define RH_GET_DESCRIPTOR	0x0680
+#define RH_SET_DESCRIPTOR	0x0700
+#define RH_GET_CONFIGURATION	0x0880
+#define RH_SET_CONFIGURATION	0x0900
+#define RH_GET_STATE		0x0280
+#define RH_GET_INTERFACE	0x0A80
+#define RH_SET_INTERFACE	0x0B00
+#define RH_SYNC_FRAME		0x0C80
+/* Our Vendor Specific Request */
+#define RH_SET_EP		0x2000
+
+
+/* Hub port features */
+#define RH_PORT_CONNECTION	   0x00
+#define RH_PORT_ENABLE		   0x01
+#define RH_PORT_SUSPEND		   0x02
+#define RH_PORT_OVER_CURRENT	   0x03
+#define RH_PORT_RESET		   0x04
+#define RH_PORT_POWER		   0x08
+#define RH_PORT_LOW_SPEED	   0x09
+
+#define RH_C_PORT_CONNECTION	   0x10
+#define RH_C_PORT_ENABLE	   0x11
+#define RH_C_PORT_SUSPEND	   0x12
+#define RH_C_PORT_OVER_CURRENT	   0x13
+#define RH_C_PORT_RESET		   0x14
+
+/* Hub features */
+#define RH_C_HUB_LOCAL_POWER	   0x00
+#define RH_C_HUB_OVER_CURRENT	   0x01
+
+#define RH_DEVICE_REMOTE_WAKEUP	   0x00
+#define RH_ENDPOINT_STALL	   0x01
+
+#define RH_ACK			   0x01
+#define RH_REQ_ERR		   -1
+#define RH_NACK			   0x00
+
+
+/* OHCI ROOT HUB REGISTER MASKS */
+
+/* roothub.portstatus [i] bits */
+#define RH_PS_CCS	     0x00000001		/* current connect status */
+#define RH_PS_PES	     0x00000002		/* port enable status*/
+#define RH_PS_PSS	     0x00000004		/* port suspend status */
+#define RH_PS_POCI	     0x00000008		/* port over current indicator */
+#define RH_PS_PRS	     0x00000010		/* port reset status */
+#define RH_PS_PPS	     0x00000100		/* port power status */
+#define RH_PS_LSDA	     0x00000200		/* low speed device attached */
+#define RH_PS_CSC	     0x00010000		/* connect status change */
+#define RH_PS_PESC	     0x00020000		/* port enable status change */
+#define RH_PS_PSSC	     0x00040000		/* port suspend status change */
+#define RH_PS_OCIC	     0x00080000		/* over current indicator change */
+#define RH_PS_PRSC	     0x00100000		/* port reset status change */
+
+/* roothub.status bits */
+#define RH_HS_LPS	     0x00000001		/* local power status */
+#define RH_HS_OCI	     0x00000002		/* over current indicator */
+#define RH_HS_DRWE	     0x00008000		/* device remote wakeup enable */
+#define RH_HS_LPSC	     0x00010000		/* local power status change */
+#define RH_HS_OCIC	     0x00020000		/* over current indicator change */
+#define RH_HS_CRWE	     0x80000000		/* clear remote wakeup enable */
+
+/* roothub.b masks */
+#define RH_B_DR		0x0000ffff		/* device removable flags */
+#define RH_B_PPCM	0xffff0000		/* port power control mask */
+
+/* roothub.a masks */
+#define RH_A_NDP	(0xff << 0)		/* number of downstream ports */
+#define RH_A_PSM	(1 << 8)		/* power switching mode */
+#define RH_A_NPS	(1 << 9)		/* no power switching */
+#define RH_A_DT		(1 << 10)		/* device type (mbz) */
+#define RH_A_OCPM	(1 << 11)		/* over current protection mode */
+#define RH_A_NOCP	(1 << 12)		/* no over current protection */
+#define RH_A_POTPGT	(0xff << 24)		/* power on to power good time */
+
+/* urb */
+#define N_URB_TD 48
+typedef struct
+{
+	ed_t *ed;
+	__u16 length;	/* number of tds associated with this request */
+	__u16 td_cnt;	/* number of tds already serviced */
+	struct usb_device *dev;
+	int   state;
+	unsigned long pipe;
+	void *transfer_buffer;
+	int transfer_buffer_length;
+	int interval;
+	int actual_length;
+	int finished;
+	td_t *td[N_URB_TD];	/* list pointer to all corresponding TDs associated with this request */
+} urb_priv_t;
+#define URB_DEL 1
+
+#define NUM_EDS 8		/* num of preallocated endpoint descriptors */
+
+struct ohci_device {
+	ed_t	ed[NUM_EDS];
+	int ed_cnt;
+};
+
+/*
+ * This is the full ohci controller description
+ *
+ * Note how the "proper" USB information is just
+ * a subset of what the full implementation needs. (Linus)
+ */
+
+typedef struct ohci {
+	long handle;              /* PCI BIOS */
+	int big_endian;           /* PCI BIOS */
+	struct ohci_hcca *hcca_unaligned;
+	struct ohci_hcca *hcca;		/* hcca */
+	td_t *td_unaligned;
+	struct ohci_device *ohci_dev_unaligned;
+	/* this allocates EDs for all possible endpoints */
+	struct ohci_device *ohci_dev;
+	/*dma_addr_t hcca_dma;*/
+
+	int irq;
+	int disabled;			/* e.g. got a UE, we're hung */
+	int sleeping;
+	unsigned long flags;		/* for HC bugs */
+
+	unsigned long dma_offset;
+	struct ohci_regs *regs; /* OHCI controller's memory */
+
+	int ohci_int_load[32];	 /* load of the 32 Interrupt Chains (for load balancing)*/
+	ed_t *ed_rm_list[2];	 /* lists of all endpoints to be removed */
+	ed_t *ed_bulktail;	 /* last endpoint of bulk list */
+	ed_t *ed_controltail;	 /* last endpoint of control list */
+	int intrstatus;
+	__u32 hc_control;		/* copy of the hc control reg */
+	struct usb_device *dev[32];
+	struct virt_root_hub rh;
+
+	const char	*slot_name;
+} ohci_t;
+
+/* hcd */
+/* endpoint */
+static int ep_link(ohci_t * ohci, ed_t * ed);
+static int ep_unlink(ohci_t * ohci, ed_t * ed);
+static ed_t * ep_add_ed(struct usb_device * usb_dev, unsigned long pipe,
+		int interval, int load);
+
+/*-------------------------------------------------------------------------*/
+
+/* we need more TDs than EDs */
+#define NUM_TD 64
+
+/* pointers to aligned storage */
+td_t *ptd;
+
+/* TDs ... */
+static inline struct td *td_alloc(struct usb_device *usb_dev)
+{
+	int i;
+	struct td	*td;
+	td = NULL;
+	for(i = 0; i < NUM_TD; i++)
+	{
+		if(ptd[i].usb_dev == NULL)
+		{
+			td = &ptd[i];
+			td->usb_dev = usb_dev;
+			break;
+		}
+	}
+	return td;
+}
+
+static inline void ed_free(struct ed *ed)
+{
+	ed->usb_dev = NULL;
+}
+
diff --git a/FireBee/trunk/usb/store/host/ohci-pci/pci_ids.h b/FireBee/trunk/usb/store/host/ohci-pci/pci_ids.h
new file mode 100644
index 0000000..29ea2de
--- /dev/null
+++ b/FireBee/trunk/usb/store/host/ohci-pci/pci_ids.h
@@ -0,0 +1,2613 @@
+/*
+ *	PCI Class, Vendor and Device IDs
+ *
+ *	Please keep sorted.
+ */
+
+/* Device classes and subclasses */
+
+#define PCI_CLASS_NOT_DEFINED		0x0000
+#define PCI_CLASS_NOT_DEFINED_VGA	0x0001
+
+#define PCI_BASE_CLASS_STORAGE		0x01
+#define PCI_CLASS_STORAGE_SCSI		0x0100
+#define PCI_CLASS_STORAGE_IDE		0x0101
+#define PCI_CLASS_STORAGE_FLOPPY	0x0102
+#define PCI_CLASS_STORAGE_IPI		0x0103
+#define PCI_CLASS_STORAGE_RAID		0x0104
+#define PCI_CLASS_STORAGE_OTHER		0x0180
+
+#define PCI_BASE_CLASS_NETWORK		0x02
+#define PCI_CLASS_NETWORK_ETHERNET	0x0200
+#define PCI_CLASS_NETWORK_TOKEN_RING	0x0201
+#define PCI_CLASS_NETWORK_FDDI		0x0202
+#define PCI_CLASS_NETWORK_ATM		0x0203
+#define PCI_CLASS_NETWORK_OTHER		0x0280
+
+#define PCI_BASE_CLASS_DISPLAY		0x03
+#define PCI_CLASS_DISPLAY_VGA		0x0300
+#define PCI_CLASS_DISPLAY_XGA		0x0301
+#define PCI_CLASS_DISPLAY_3D		0x0302
+#define PCI_CLASS_DISPLAY_OTHER		0x0380
+
+#define PCI_BASE_CLASS_MULTIMEDIA	0x04
+#define PCI_CLASS_MULTIMEDIA_VIDEO	0x0400
+#define PCI_CLASS_MULTIMEDIA_AUDIO	0x0401
+#define PCI_CLASS_MULTIMEDIA_PHONE	0x0402
+#define PCI_CLASS_MULTIMEDIA_OTHER	0x0480
+
+#define PCI_BASE_CLASS_MEMORY		0x05
+#define PCI_CLASS_MEMORY_RAM		0x0500
+#define PCI_CLASS_MEMORY_FLASH		0x0501
+#define PCI_CLASS_MEMORY_OTHER		0x0580
+
+#define PCI_BASE_CLASS_BRIDGE		0x06
+#define PCI_CLASS_BRIDGE_HOST		0x0600
+#define PCI_CLASS_BRIDGE_ISA		0x0601
+#define PCI_CLASS_BRIDGE_EISA		0x0602
+#define PCI_CLASS_BRIDGE_MC		0x0603
+#define PCI_CLASS_BRIDGE_PCI		0x0604
+#define PCI_CLASS_BRIDGE_PCMCIA		0x0605
+#define PCI_CLASS_BRIDGE_NUBUS		0x0606
+#define PCI_CLASS_BRIDGE_CARDBUS	0x0607
+#define PCI_CLASS_BRIDGE_RACEWAY	0x0608
+#define PCI_CLASS_BRIDGE_OTHER		0x0680
+
+#define PCI_BASE_CLASS_COMMUNICATION	0x07
+#define PCI_CLASS_COMMUNICATION_SERIAL	0x0700
+#define PCI_CLASS_COMMUNICATION_PARALLEL 0x0701
+#define PCI_CLASS_COMMUNICATION_MULTISERIAL 0x0702
+#define PCI_CLASS_COMMUNICATION_MODEM	0x0703
+#define PCI_CLASS_COMMUNICATION_OTHER	0x0780
+
+#define PCI_BASE_CLASS_SYSTEM		0x08
+#define PCI_CLASS_SYSTEM_PIC		0x0800
+#define PCI_CLASS_SYSTEM_DMA		0x0801
+#define PCI_CLASS_SYSTEM_TIMER		0x0802
+#define PCI_CLASS_SYSTEM_RTC		0x0803
+#define PCI_CLASS_SYSTEM_PCI_HOTPLUG	0x0804
+#define PCI_CLASS_SYSTEM_OTHER		0x0880
+
+#define PCI_BASE_CLASS_INPUT		0x09
+#define PCI_CLASS_INPUT_KEYBOARD	0x0900
+#define PCI_CLASS_INPUT_PEN		0x0901
+#define PCI_CLASS_INPUT_MOUSE		0x0902
+#define PCI_CLASS_INPUT_SCANNER		0x0903
+#define PCI_CLASS_INPUT_GAMEPORT	0x0904
+#define PCI_CLASS_INPUT_OTHER		0x0980
+
+#define PCI_BASE_CLASS_DOCKING		0x0a
+#define PCI_CLASS_DOCKING_GENERIC	0x0a00
+#define PCI_CLASS_DOCKING_OTHER		0x0a80
+
+#define PCI_BASE_CLASS_PROCESSOR	0x0b
+#define PCI_CLASS_PROCESSOR_386		0x0b00
+#define PCI_CLASS_PROCESSOR_486		0x0b01
+#define PCI_CLASS_PROCESSOR_PENTIUM	0x0b02
+#define PCI_CLASS_PROCESSOR_ALPHA	0x0b10
+#define PCI_CLASS_PROCESSOR_POWERPC	0x0b20
+#define PCI_CLASS_PROCESSOR_MIPS	0x0b30
+#define PCI_CLASS_PROCESSOR_CO		0x0b40
+
+#define PCI_BASE_CLASS_SERIAL		0x0c
+#define PCI_CLASS_SERIAL_FIREWIRE	0x0c00
+#define PCI_CLASS_SERIAL_ACCESS		0x0c01
+#define PCI_CLASS_SERIAL_SSA		0x0c02
+#define PCI_CLASS_SERIAL_USB		0x0c03
+/* added code to find different types of USB controllers */
+#define PCI_CLASS_SERIAL_USB_UHCI   0x0c0300
+#define PCI_CLASS_SERIAL_USB_OHCI   0x0c0310
+#define PCI_CLASS_SERIAL_USB_EHCI   0x0c0320
+#define PCI_CLASS_SERIAL_FIBER		0x0c04
+#define PCI_CLASS_SERIAL_SMBUS		0x0c05
+
+#define PCI_BASE_CLASS_INTELLIGENT	0x0e
+#define PCI_CLASS_INTELLIGENT_I2O	0x0e00
+
+#define PCI_BASE_CLASS_SATELLITE	0x0f
+#define PCI_CLASS_SATELLITE_TV		0x0f00
+#define PCI_CLASS_SATELLITE_AUDIO	0x0f01
+#define PCI_CLASS_SATELLITE_VOICE	0x0f03
+#define PCI_CLASS_SATELLITE_DATA	0x0f04
+
+#define PCI_BASE_CLASS_CRYPT		0x10
+#define PCI_CLASS_CRYPT_NETWORK		0x1000
+#define PCI_CLASS_CRYPT_ENTERTAINMENT	0x1001
+#define PCI_CLASS_CRYPT_OTHER		0x1080
+
+#define PCI_BASE_CLASS_SIGNAL_PROCESSING 0x11
+#define PCI_CLASS_SP_DPIO		0x1100
+#define PCI_CLASS_SP_OTHER		0x1180
+
+#define PCI_CLASS_OTHERS		0xff
+
+/* Vendors and devices.  Sort key: vendor first, device next. */
+
+#define PCI_VENDOR_ID_DYNALINK		0x0675
+#define PCI_DEVICE_ID_DYNALINK_IS64PH	0x1702
+
+#define PCI_VENDOR_ID_BERKOM			0x0871
+#define PCI_DEVICE_ID_BERKOM_A1T		0xffa1
+#define PCI_DEVICE_ID_BERKOM_T_CONCEPT		0xffa2
+#define PCI_DEVICE_ID_BERKOM_A4T		0xffa4
+#define PCI_DEVICE_ID_BERKOM_SCITEL_QUADRO	0xffa8
+
+#define PCI_VENDOR_ID_COMPAQ		0x0e11
+#define PCI_DEVICE_ID_COMPAQ_TOKENRING	0x0508
+#define PCI_DEVICE_ID_COMPAQ_1280	0x3033
+#define PCI_DEVICE_ID_COMPAQ_TRIFLEX	0x4000
+#define PCI_DEVICE_ID_COMPAQ_6010	0x6010
+#define PCI_DEVICE_ID_COMPAQ_TACHYON	0xa0fc
+#define PCI_DEVICE_ID_COMPAQ_SMART2P	0xae10
+#define PCI_DEVICE_ID_COMPAQ_NETEL100	0xae32
+#define PCI_DEVICE_ID_COMPAQ_NETEL10	0xae34
+#define PCI_DEVICE_ID_COMPAQ_TRIFLEX_IDE 0xae33
+#define PCI_DEVICE_ID_COMPAQ_NETFLEX3I	0xae35
+#define PCI_DEVICE_ID_COMPAQ_NETEL100D	0xae40
+#define PCI_DEVICE_ID_COMPAQ_NETEL100PI	0xae43
+#define PCI_DEVICE_ID_COMPAQ_NETEL100I	0xb011
+#define PCI_DEVICE_ID_COMPAQ_CISS	0xb060
+#define PCI_DEVICE_ID_COMPAQ_CISSB	0xb178
+#define PCI_DEVICE_ID_COMPAQ_CISSC	0x46
+#define PCI_DEVICE_ID_COMPAQ_THUNDER	0xf130
+#define PCI_DEVICE_ID_COMPAQ_NETFLEX3B	0xf150
+
+#define PCI_VENDOR_ID_NCR		0x1000
+#define PCI_VENDOR_ID_LSI_LOGIC		0x1000
+#define PCI_DEVICE_ID_NCR_53C810	0x0001
+#define PCI_DEVICE_ID_NCR_53C820	0x0002
+#define PCI_DEVICE_ID_NCR_53C825	0x0003
+#define PCI_DEVICE_ID_NCR_53C815	0x0004
+#define PCI_DEVICE_ID_LSI_53C810AP	0x0005
+#define PCI_DEVICE_ID_NCR_53C860	0x0006
+#define PCI_DEVICE_ID_LSI_53C1510	0x000a
+#define PCI_DEVICE_ID_NCR_53C896	0x000b
+#define PCI_DEVICE_ID_NCR_53C895	0x000c
+#define PCI_DEVICE_ID_NCR_53C885	0x000d
+#define PCI_DEVICE_ID_NCR_53C875	0x000f
+#define PCI_DEVICE_ID_NCR_53C1510	0x0010
+#define PCI_DEVICE_ID_LSI_53C895A	0x0012
+#define PCI_DEVICE_ID_LSI_53C875A	0x0013
+#define PCI_DEVICE_ID_LSI_53C1010_33	0x0020
+#define PCI_DEVICE_ID_LSI_53C1010_66	0x0021
+#define PCI_DEVICE_ID_LSI_53C1030	0x0030
+#define PCI_DEVICE_ID_LSI_1030_53C1035	0x0032
+#define PCI_DEVICE_ID_LSI_53C1035	0x0040
+#define PCI_DEVICE_ID_NCR_53C875J	0x008f
+#define PCI_DEVICE_ID_LSI_FC909		0x0621
+#define PCI_DEVICE_ID_LSI_FC929		0x0622
+#define PCI_DEVICE_ID_LSI_FC929_LAN	0x0623
+#define PCI_DEVICE_ID_LSI_FC919		0x0624
+#define PCI_DEVICE_ID_LSI_FC919_LAN	0x0625
+#define PCI_DEVICE_ID_LSI_FC929X	0x0626
+#define PCI_DEVICE_ID_LSI_FC939X	0x0642
+#define PCI_DEVICE_ID_LSI_FC949X	0x0640
+#define PCI_DEVICE_ID_LSI_FC919X	0x0628
+#define PCI_DEVICE_ID_NCR_YELLOWFIN	0x0701
+#define PCI_DEVICE_ID_LSI_61C102	0x0901
+#define PCI_DEVICE_ID_LSI_63C815	0x1000
+#define PCI_DEVICE_ID_LSI_SAS1064	0x0050
+#define PCI_DEVICE_ID_LSI_SAS1066	0x005E
+#define PCI_DEVICE_ID_LSI_SAS1068	0x0054
+#define PCI_DEVICE_ID_LSI_SAS1064A	0x005C
+#define PCI_DEVICE_ID_LSI_SAS1064E	0x0056
+#define PCI_DEVICE_ID_LSI_SAS1066E	0x005A
+#define PCI_DEVICE_ID_LSI_SAS1068E	0x0058
+#define PCI_DEVICE_ID_LSI_SAS1078	0x0060
+
+#define PCI_VENDOR_ID_ATI		0x1002
+/* Mach64 */
+#define PCI_DEVICE_ID_ATI_68800		0x4158
+#define PCI_DEVICE_ID_ATI_215CT222	0x4354
+#define PCI_DEVICE_ID_ATI_210888CX	0x4358
+#define PCI_DEVICE_ID_ATI_215ET222	0x4554
+/* Mach64 / Rage */
+#define PCI_DEVICE_ID_ATI_215GB		0x4742
+#define PCI_DEVICE_ID_ATI_215GD		0x4744
+#define PCI_DEVICE_ID_ATI_215GI		0x4749
+#define PCI_DEVICE_ID_ATI_215GP		0x4750
+#define PCI_DEVICE_ID_ATI_215GQ		0x4751
+#define PCI_DEVICE_ID_ATI_215XL		0x4752
+#define PCI_DEVICE_ID_ATI_215GT		0x4754
+#define PCI_DEVICE_ID_ATI_215GTB	0x4755
+#define PCI_DEVICE_ID_ATI_215_IV	0x4756
+#define PCI_DEVICE_ID_ATI_215_IW	0x4757
+#define PCI_DEVICE_ID_ATI_215_IZ	0x475A
+#define PCI_DEVICE_ID_ATI_210888GX	0x4758
+#define PCI_DEVICE_ID_ATI_215_LB	0x4c42
+#define PCI_DEVICE_ID_ATI_215_LD	0x4c44
+#define PCI_DEVICE_ID_ATI_215_LG	0x4c47
+#define PCI_DEVICE_ID_ATI_215_LI	0x4c49
+#define PCI_DEVICE_ID_ATI_215_LM	0x4c4D
+#define PCI_DEVICE_ID_ATI_215_LN	0x4c4E
+#define PCI_DEVICE_ID_ATI_215_LR	0x4c52
+#define PCI_DEVICE_ID_ATI_215_LS	0x4c53
+#define PCI_DEVICE_ID_ATI_264_LT	0x4c54
+/* Mach64 VT */
+#define PCI_DEVICE_ID_ATI_264VT		0x5654
+#define PCI_DEVICE_ID_ATI_264VU		0x5655
+#define PCI_DEVICE_ID_ATI_264VV		0x5656
+/* Rage128 GL */
+#define PCI_DEVICE_ID_ATI_RAGE128_RE	0x5245
+#define PCI_DEVICE_ID_ATI_RAGE128_RF	0x5246
+#define PCI_DEVICE_ID_ATI_RAGE128_RG	0x5247
+/* Rage128 VR */
+#define PCI_DEVICE_ID_ATI_RAGE128_RK	0x524b
+#define PCI_DEVICE_ID_ATI_RAGE128_RL	0x524c
+#define PCI_DEVICE_ID_ATI_RAGE128_SE	0x5345
+#define PCI_DEVICE_ID_ATI_RAGE128_SF	0x5346
+#define PCI_DEVICE_ID_ATI_RAGE128_SG	0x5347
+#define PCI_DEVICE_ID_ATI_RAGE128_SH	0x5348
+#define PCI_DEVICE_ID_ATI_RAGE128_SK	0x534b
+#define PCI_DEVICE_ID_ATI_RAGE128_SL	0x534c
+#define PCI_DEVICE_ID_ATI_RAGE128_SM	0x534d
+#define PCI_DEVICE_ID_ATI_RAGE128_SN	0x534e
+/* Rage128 Ultra */
+#define PCI_DEVICE_ID_ATI_RAGE128_TF	0x5446
+#define PCI_DEVICE_ID_ATI_RAGE128_TL	0x544c
+#define PCI_DEVICE_ID_ATI_RAGE128_TR	0x5452
+#define PCI_DEVICE_ID_ATI_RAGE128_TS	0x5453
+#define PCI_DEVICE_ID_ATI_RAGE128_TT	0x5454
+#define PCI_DEVICE_ID_ATI_RAGE128_TU	0x5455
+/* Rage128 M3 */
+#define PCI_DEVICE_ID_ATI_RAGE128_LE	0x4c45
+#define PCI_DEVICE_ID_ATI_RAGE128_LF	0x4c46
+/* Rage128 M4 */
+#define PCI_DEVICE_ID_ATI_RAGE128_MF    0x4d46
+#define PCI_DEVICE_ID_ATI_RAGE128_ML    0x4d4c
+/* Rage128 Pro GL */
+#define PCI_DEVICE_ID_ATI_RAGE128_PA	0x5041
+#define PCI_DEVICE_ID_ATI_RAGE128_PB	0x5042
+#define PCI_DEVICE_ID_ATI_RAGE128_PC	0x5043
+#define PCI_DEVICE_ID_ATI_RAGE128_PD	0x5044
+#define PCI_DEVICE_ID_ATI_RAGE128_PE	0x5045
+#define PCI_DEVICE_ID_ATI_RAGE128_PF	0x5046
+/* Rage128 Pro VR */
+#define PCI_DEVICE_ID_ATI_RAGE128_PG	0x5047
+#define PCI_DEVICE_ID_ATI_RAGE128_PH	0x5048
+#define PCI_DEVICE_ID_ATI_RAGE128_PI	0x5049
+#define PCI_DEVICE_ID_ATI_RAGE128_PJ	0x504A
+#define PCI_DEVICE_ID_ATI_RAGE128_PK	0x504B
+#define PCI_DEVICE_ID_ATI_RAGE128_PL	0x504C
+#define PCI_DEVICE_ID_ATI_RAGE128_PM	0x504D
+#define PCI_DEVICE_ID_ATI_RAGE128_PN	0x504E
+#define PCI_DEVICE_ID_ATI_RAGE128_PO	0x504F
+#define PCI_DEVICE_ID_ATI_RAGE128_PP	0x5050
+#define PCI_DEVICE_ID_ATI_RAGE128_PQ	0x5051
+#define PCI_DEVICE_ID_ATI_RAGE128_PR	0x5052
+#define PCI_DEVICE_ID_ATI_RAGE128_TR	0x5452
+#define PCI_DEVICE_ID_ATI_RAGE128_PS	0x5053
+#define PCI_DEVICE_ID_ATI_RAGE128_PT	0x5054
+#define PCI_DEVICE_ID_ATI_RAGE128_PU	0x5055
+#define PCI_DEVICE_ID_ATI_RAGE128_PV	0x5056
+#define PCI_DEVICE_ID_ATI_RAGE128_PW	0x5057
+#define PCI_DEVICE_ID_ATI_RAGE128_PX	0x5058
+/* Rage128 M4 */
+#define PCI_DEVICE_ID_ATI_RADEON_LE	0x4d45
+#define PCI_DEVICE_ID_ATI_RADEON_LF	0x4d46
+/* Radeon R100 */
+#define PCI_DEVICE_ID_ATI_RADEON_QD	0x5144
+#define PCI_DEVICE_ID_ATI_RADEON_QE	0x5145
+#define PCI_DEVICE_ID_ATI_RADEON_QF	0x5146
+#define PCI_DEVICE_ID_ATI_RADEON_QG	0x5147
+/* Radeon RV100 (VE) */
+#define PCI_DEVICE_ID_ATI_RADEON_QY	0x5159
+#define PCI_DEVICE_ID_ATI_RADEON_QZ	0x515a
+/* Radeon R200 (8500) */
+#define PCI_DEVICE_ID_ATI_RADEON_QL	0x514c
+#define PCI_DEVICE_ID_ATI_RADEON_QN	0x514e
+#define PCI_DEVICE_ID_ATI_RADEON_QO	0x514f
+#define PCI_DEVICE_ID_ATI_RADEON_Ql	0x516c
+#define PCI_DEVICE_ID_ATI_RADEON_BB	0x4242
+/* Radeon R200 (9100) */
+#define PCI_DEVICE_ID_ATI_RADEON_QM	0x514d
+/* Radeon RV200 (7500) */
+#define PCI_DEVICE_ID_ATI_RADEON_QW	0x5157
+#define PCI_DEVICE_ID_ATI_RADEON_QX	0x5158
+/* Radeon NV-100 */
+#define PCI_DEVICE_ID_ATI_RADEON_N1	0x5159
+#define PCI_DEVICE_ID_ATI_RADEON_N2	0x515a
+/* Radeon RV250 (9000) */
+#define PCI_DEVICE_ID_ATI_RADEON_Id	0x4964
+#define PCI_DEVICE_ID_ATI_RADEON_Ie	0x4965
+#define PCI_DEVICE_ID_ATI_RADEON_If	0x4966
+#define PCI_DEVICE_ID_ATI_RADEON_Ig	0x4967
+/* Radeon RV280 (9200) */
+#define PCI_DEVICE_ID_ATI_RADEON_Y_	0x5960
+#define PCI_DEVICE_ID_ATI_RADEON_Ya	0x5961
+#define PCI_DEVICE_ID_ATI_RADEON_Yd	0x5964
+/* Radeon R300 (9500) */
+#define PCI_DEVICE_ID_ATI_RADEON_AD	0x4144
+/* Radeon R300 (9700) */
+#define PCI_DEVICE_ID_ATI_RADEON_ND	0x4e44
+#define PCI_DEVICE_ID_ATI_RADEON_NE	0x4e45
+#define PCI_DEVICE_ID_ATI_RADEON_NF	0x4e46
+#define PCI_DEVICE_ID_ATI_RADEON_NG	0x4e47
+#define PCI_DEVICE_ID_ATI_RADEON_AE	0x4145
+#define PCI_DEVICE_ID_ATI_RADEON_AF	0x4146
+/* Radeon R350 (9800) */
+#define PCI_DEVICE_ID_ATI_RADEON_NH	0x4e48
+#define PCI_DEVICE_ID_ATI_RADEON_NI	0x4e49
+/* Radeon RV350 (9600) */
+#define PCI_DEVICE_ID_ATI_RADEON_AP	0x4150
+#define PCI_DEVICE_ID_ATI_RADEON_AR	0x4152
+/* Radeon M6 */
+#define PCI_DEVICE_ID_ATI_RADEON_LY	0x4c59
+#define PCI_DEVICE_ID_ATI_RADEON_LZ	0x4c5a
+/* Radeon M7 */
+#define PCI_DEVICE_ID_ATI_RADEON_LW	0x4c57
+#define PCI_DEVICE_ID_ATI_RADEON_LX	0x4c58
+/* Radeon M9 */
+#define PCI_DEVICE_ID_ATI_RADEON_Ld	0x4c64
+#define PCI_DEVICE_ID_ATI_RADEON_Le	0x4c65
+#define PCI_DEVICE_ID_ATI_RADEON_Lf	0x4c66
+#define PCI_DEVICE_ID_ATI_RADEON_Lg	0x4c67
+/* Radeon */
+#define PCI_DEVICE_ID_ATI_RADEON_RA	0x5144
+#define PCI_DEVICE_ID_ATI_RADEON_RB	0x5145
+#define PCI_DEVICE_ID_ATI_RADEON_RC	0x5146
+#define PCI_DEVICE_ID_ATI_RADEON_RD	0x5147
+/* RadeonIGP */
+#define PCI_DEVICE_ID_ATI_RS100		0xcab0
+#define PCI_DEVICE_ID_ATI_RS200		0xcab2
+#define PCI_DEVICE_ID_ATI_RS200_B	0xcbb2
+#define PCI_DEVICE_ID_ATI_RS250		0xcab3
+#define PCI_DEVICE_ID_ATI_RS300_100	0x5830
+#define PCI_DEVICE_ID_ATI_RS300_133	0x5831
+#define PCI_DEVICE_ID_ATI_RS300_166	0x5832
+#define PCI_DEVICE_ID_ATI_RS300_200	0x5833
+#define PCI_DEVICE_ID_ATI_RS350_100     0x7830
+#define PCI_DEVICE_ID_ATI_RS350_133     0x7831
+#define PCI_DEVICE_ID_ATI_RS350_166     0x7832
+#define PCI_DEVICE_ID_ATI_RS350_200     0x7833
+#define PCI_DEVICE_ID_ATI_RS400_100     0x5a30
+#define PCI_DEVICE_ID_ATI_RS400_133     0x5a31
+#define PCI_DEVICE_ID_ATI_RS400_166     0x5a32
+#define PCI_DEVICE_ID_ATI_RS400_200     0x5a33
+#define PCI_DEVICE_ID_ATI_RS480         0x5950
+/* ATI IXP Chipset */
+#define PCI_DEVICE_ID_ATI_IXP200_IDE	0x4349
+#define PCI_DEVICE_ID_ATI_IXP300_IDE	0x4369
+#define PCI_DEVICE_ID_ATI_IXP300_SATA   0x436e
+#define PCI_DEVICE_ID_ATI_IXP400_IDE	0x4376
+#define PCI_DEVICE_ID_ATI_IXP400_SATA   0x4379
+
+#define PCI_VENDOR_ID_VLSI		0x1004
+#define PCI_DEVICE_ID_VLSI_82C592	0x0005
+#define PCI_DEVICE_ID_VLSI_82C593	0x0006
+#define PCI_DEVICE_ID_VLSI_82C594	0x0007
+#define PCI_DEVICE_ID_VLSI_82C597	0x0009
+#define PCI_DEVICE_ID_VLSI_82C541	0x000c
+#define PCI_DEVICE_ID_VLSI_82C543	0x000d
+#define PCI_DEVICE_ID_VLSI_82C532	0x0101
+#define PCI_DEVICE_ID_VLSI_82C534	0x0102
+#define PCI_DEVICE_ID_VLSI_82C535	0x0104
+#define PCI_DEVICE_ID_VLSI_82C147	0x0105
+#define PCI_DEVICE_ID_VLSI_VAS96011	0x0702
+
+#define PCI_VENDOR_ID_ADL		0x1005
+#define PCI_DEVICE_ID_ADL_2301		0x2301
+
+#define PCI_VENDOR_ID_NS		0x100b
+#define PCI_DEVICE_ID_NS_87415		0x0002
+#define PCI_DEVICE_ID_NS_87560_LIO	0x000e
+#define PCI_DEVICE_ID_NS_87560_USB	0x0012
+#define PCI_DEVICE_ID_NS_83815		0x0020
+#define PCI_DEVICE_ID_NS_83820		0x0022
+#define PCI_DEVICE_ID_NS_SCx200_BRIDGE	0x0500
+#define PCI_DEVICE_ID_NS_SCx200_SMI	0x0501
+#define PCI_DEVICE_ID_NS_SCx200_IDE	0x0502
+#define PCI_DEVICE_ID_NS_SCx200_AUDIO	0x0503
+#define PCI_DEVICE_ID_NS_SCx200_VIDEO	0x0504
+#define PCI_DEVICE_ID_NS_SCx200_XBUS	0x0505
+#define PCI_DEVICE_ID_NS_SC1100_BRIDGE	0x0510
+#define PCI_DEVICE_ID_NS_SC1100_SMI	0x0511
+#define PCI_DEVICE_ID_NS_SC1100_XBUS	0x0515
+#define PCI_DEVICE_ID_NS_87410		0xd001
+
+#define PCI_VENDOR_ID_TSENG		0x100c
+#define PCI_DEVICE_ID_TSENG_W32P_2	0x3202
+#define PCI_DEVICE_ID_TSENG_W32P_b	0x3205
+#define PCI_DEVICE_ID_TSENG_W32P_c	0x3206
+#define PCI_DEVICE_ID_TSENG_W32P_d	0x3207
+#define PCI_DEVICE_ID_TSENG_ET6000	0x3208
+
+#define PCI_VENDOR_ID_WEITEK		0x100e
+#define PCI_DEVICE_ID_WEITEK_P9000	0x9001
+#define PCI_DEVICE_ID_WEITEK_P9100	0x9100
+
+#define PCI_VENDOR_ID_DEC		0x1011
+#define PCI_DEVICE_ID_DEC_BRD		0x0001
+#define PCI_DEVICE_ID_DEC_TULIP		0x0002
+#define PCI_DEVICE_ID_DEC_TGA		0x0004
+#define PCI_DEVICE_ID_DEC_TULIP_FAST	0x0009
+#define PCI_DEVICE_ID_DEC_TGA2		0x000D
+#define PCI_DEVICE_ID_DEC_FDDI		0x000F
+#define PCI_DEVICE_ID_DEC_TULIP_PLUS	0x0014
+#define PCI_DEVICE_ID_DEC_21142		0x0019
+#define PCI_DEVICE_ID_DEC_21052		0x0021
+#define PCI_DEVICE_ID_DEC_21150		0x0022
+#define PCI_DEVICE_ID_DEC_21152		0x0024
+#define PCI_DEVICE_ID_DEC_21153		0x0025
+#define PCI_DEVICE_ID_DEC_21154		0x0026
+#define PCI_DEVICE_ID_DEC_21285		0x1065
+#define PCI_DEVICE_ID_COMPAQ_42XX	0x0046
+
+#define PCI_VENDOR_ID_CIRRUS		0x1013
+#define PCI_DEVICE_ID_CIRRUS_7548	0x0038
+#define PCI_DEVICE_ID_CIRRUS_5430	0x00a0
+#define PCI_DEVICE_ID_CIRRUS_5434_4	0x00a4
+#define PCI_DEVICE_ID_CIRRUS_5434_8	0x00a8
+#define PCI_DEVICE_ID_CIRRUS_5436	0x00ac
+#define PCI_DEVICE_ID_CIRRUS_5446	0x00b8
+#define PCI_DEVICE_ID_CIRRUS_5480	0x00bc
+#define PCI_DEVICE_ID_CIRRUS_5462	0x00d0
+#define PCI_DEVICE_ID_CIRRUS_5464	0x00d4
+#define PCI_DEVICE_ID_CIRRUS_5465	0x00d6
+#define PCI_DEVICE_ID_CIRRUS_6729	0x1100
+#define PCI_DEVICE_ID_CIRRUS_6832	0x1110
+#define PCI_DEVICE_ID_CIRRUS_7542	0x1200
+#define PCI_DEVICE_ID_CIRRUS_7543	0x1202
+#define PCI_DEVICE_ID_CIRRUS_7541	0x1204
+
+#define PCI_VENDOR_ID_IBM		0x1014
+#define PCI_DEVICE_ID_IBM_FIRE_CORAL	0x000a
+#define PCI_DEVICE_ID_IBM_TR		0x0018
+#define PCI_DEVICE_ID_IBM_82G2675	0x001d
+#define PCI_DEVICE_ID_IBM_MCA		0x0020
+#define PCI_DEVICE_ID_IBM_82351		0x0022
+#define PCI_DEVICE_ID_IBM_PYTHON	0x002d
+#define PCI_DEVICE_ID_IBM_SERVERAID	0x002e
+#define PCI_DEVICE_ID_IBM_TR_WAKE	0x003e
+#define PCI_DEVICE_ID_IBM_MPIC		0x0046
+#define PCI_DEVICE_ID_IBM_3780IDSP	0x007d
+#define PCI_DEVICE_ID_IBM_CHUKAR	0x0096
+#define PCI_DEVICE_ID_IBM_CPC710_PCI64	0x00fc
+#define PCI_DEVICE_ID_IBM_CPC710_PCI32	0x0105
+#define	PCI_DEVICE_ID_IBM_405GP		0x0156
+#define PCI_DEVICE_ID_IBM_SNIPE		0x0180
+#define PCI_DEVICE_ID_IBM_SERVERAIDI960	0x01bd
+#define PCI_DEVICE_ID_IBM_CITRINE		0x028C
+#define PCI_DEVICE_ID_IBM_GEMSTONE		0xB166
+#define PCI_DEVICE_ID_IBM_MPIC_2	0xffff
+#define PCI_DEVICE_ID_IBM_ICOM_DEV_ID_1	0x0031
+#define PCI_DEVICE_ID_IBM_ICOM_DEV_ID_2	0x0219
+#define PCI_DEVICE_ID_IBM_ICOM_V2_TWO_PORTS_RVX		0x021A
+#define PCI_DEVICE_ID_IBM_ICOM_V2_ONE_PORT_RVX_ONE_PORT_MDM	0x0251
+#define PCI_DEVICE_ID_IBM_ICOM_FOUR_PORT_MODEL	0x252
+
+#define PCI_VENDOR_ID_COMPEX2		0x101a // pci.ids says "AT&T GIS (NCR)"
+#define PCI_DEVICE_ID_COMPEX2_100VG	0x0005
+
+#define PCI_VENDOR_ID_WD		0x101c
+#define PCI_DEVICE_ID_WD_7197		0x3296
+#define PCI_DEVICE_ID_WD_90C		0xc24a
+
+#define PCI_VENDOR_ID_AMI		0x101e
+#define PCI_DEVICE_ID_AMI_MEGARAID3	0x1960
+#define PCI_DEVICE_ID_AMI_MEGARAID	0x9010
+#define PCI_DEVICE_ID_AMI_MEGARAID2	0x9060
+
+#define PCI_VENDOR_ID_AMD		0x1022
+#define PCI_DEVICE_ID_AMD_LANCE		0x2000
+#define PCI_DEVICE_ID_AMD_LANCE_HOME	0x2001
+#define PCI_DEVICE_ID_AMD_SCSI		0x2020
+#define PCI_DEVICE_ID_AMD_SERENADE	0x36c0
+#define PCI_DEVICE_ID_AMD_FE_GATE_7006	0x7006
+#define PCI_DEVICE_ID_AMD_FE_GATE_7007	0x7007
+#define PCI_DEVICE_ID_AMD_FE_GATE_700C	0x700C
+#define PCI_DEVICE_ID_AMD_FE_GATE_700D	0x700D
+#define PCI_DEVICE_ID_AMD_FE_GATE_700E	0x700E
+#define PCI_DEVICE_ID_AMD_FE_GATE_700F	0x700F
+#define PCI_DEVICE_ID_AMD_COBRA_7400	0x7400
+#define PCI_DEVICE_ID_AMD_COBRA_7401	0x7401
+#define PCI_DEVICE_ID_AMD_COBRA_7403	0x7403
+#define PCI_DEVICE_ID_AMD_COBRA_7404	0x7404
+#define PCI_DEVICE_ID_AMD_VIPER_7408	0x7408
+#define PCI_DEVICE_ID_AMD_VIPER_7409	0x7409
+#define PCI_DEVICE_ID_AMD_VIPER_740B	0x740B
+#define PCI_DEVICE_ID_AMD_VIPER_740C	0x740C
+#define PCI_DEVICE_ID_AMD_VIPER_7410	0x7410
+#define PCI_DEVICE_ID_AMD_VIPER_7411	0x7411
+#define PCI_DEVICE_ID_AMD_VIPER_7413	0x7413
+#define PCI_DEVICE_ID_AMD_VIPER_7414	0x7414
+#define PCI_DEVICE_ID_AMD_OPUS_7440	0x7440
+#	define PCI_DEVICE_ID_AMD_VIPER_7440	PCI_DEVICE_ID_AMD_OPUS_7440
+#define PCI_DEVICE_ID_AMD_OPUS_7441	0x7441
+#	define PCI_DEVICE_ID_AMD_VIPER_7441	PCI_DEVICE_ID_AMD_OPUS_7441
+#define PCI_DEVICE_ID_AMD_OPUS_7443	0x7443
+#	define PCI_DEVICE_ID_AMD_VIPER_7443	PCI_DEVICE_ID_AMD_OPUS_7443
+#define PCI_DEVICE_ID_AMD_OPUS_7445	0x7445
+#define PCI_DEVICE_ID_AMD_OPUS_7448	0x7448
+# define	PCI_DEVICE_ID_AMD_VIPER_7448	PCI_DEVICE_ID_AMD_OPUS_7448
+#define PCI_DEVICE_ID_AMD_OPUS_7449	0x7449
+#	define PCI_DEVICE_ID_AMD_VIPER_7449	PCI_DEVICE_ID_AMD_OPUS_7449
+#define PCI_DEVICE_ID_AMD_8111_LAN	0x7462
+#define PCI_DEVICE_ID_AMD_8111_LPC	0x7468
+#define PCI_DEVICE_ID_AMD_8111_IDE	0x7469
+#define PCI_DEVICE_ID_AMD_8111_SMBUS2	0x746a
+#define PCI_DEVICE_ID_AMD_8111_SMBUS	0x746b
+#define PCI_DEVICE_ID_AMD_8111_AUDIO	0x746d
+#define PCI_DEVICE_ID_AMD_8151_0	0x7454
+#define PCI_DEVICE_ID_AMD_8131_APIC     0x7450
+
+#define PCI_VENDOR_ID_TRIDENT		0x1023
+#define PCI_DEVICE_ID_TRIDENT_4DWAVE_DX	0x2000
+#define PCI_DEVICE_ID_TRIDENT_4DWAVE_NX	0x2001
+#define PCI_DEVICE_ID_TRIDENT_9320	0x9320
+#define PCI_DEVICE_ID_TRIDENT_9388	0x9388
+#define PCI_DEVICE_ID_TRIDENT_9397	0x9397
+#define PCI_DEVICE_ID_TRIDENT_939A	0x939A
+#define PCI_DEVICE_ID_TRIDENT_9520	0x9520
+#define PCI_DEVICE_ID_TRIDENT_9525	0x9525
+#define PCI_DEVICE_ID_TRIDENT_9420	0x9420
+#define PCI_DEVICE_ID_TRIDENT_9440	0x9440
+#define PCI_DEVICE_ID_TRIDENT_9660	0x9660
+#define PCI_DEVICE_ID_TRIDENT_9750	0x9750
+#define PCI_DEVICE_ID_TRIDENT_9850	0x9850
+#define PCI_DEVICE_ID_TRIDENT_9880	0x9880
+#define PCI_DEVICE_ID_TRIDENT_8400	0x8400
+#define PCI_DEVICE_ID_TRIDENT_8420	0x8420
+#define PCI_DEVICE_ID_TRIDENT_8500	0x8500
+
+#define PCI_VENDOR_ID_AI		0x1025
+#define PCI_DEVICE_ID_AI_M1435		0x1435
+
+#define PCI_VENDOR_ID_DELL		0x1028
+#define PCI_DEVICE_ID_DELL_RACIII	0x0008
+#define PCI_DEVICE_ID_DELL_RAC4		0x0012
+
+#define PCI_VENDOR_ID_MATROX		0x102B
+#define PCI_DEVICE_ID_MATROX_MGA_2	0x0518
+#define PCI_DEVICE_ID_MATROX_MIL	0x0519
+#define PCI_DEVICE_ID_MATROX_MYS	0x051A
+#define PCI_DEVICE_ID_MATROX_MIL_2	0x051b
+#define PCI_DEVICE_ID_MATROX_MIL_2_AGP	0x051f
+#define PCI_DEVICE_ID_MATROX_MGA_IMP	0x0d10
+#define PCI_DEVICE_ID_MATROX_G100_MM	0x1000
+#define PCI_DEVICE_ID_MATROX_G100_AGP	0x1001
+#define PCI_DEVICE_ID_MATROX_G200_PCI	0x0520
+#define PCI_DEVICE_ID_MATROX_G200_AGP	0x0521
+#define	PCI_DEVICE_ID_MATROX_G400	0x0525
+#define PCI_DEVICE_ID_MATROX_G550	0x2527
+#define PCI_DEVICE_ID_MATROX_VIA	0x4536
+
+#define PCI_VENDOR_ID_CT		0x102c
+#define PCI_DEVICE_ID_CT_69000		0x00c0
+#define PCI_DEVICE_ID_CT_65545		0x00d8
+#define PCI_DEVICE_ID_CT_65548		0x00dc
+#define PCI_DEVICE_ID_CT_65550		0x00e0
+#define PCI_DEVICE_ID_CT_65554		0x00e4
+#define PCI_DEVICE_ID_CT_65555		0x00e5
+
+#define PCI_VENDOR_ID_MIRO		0x1031
+#define PCI_DEVICE_ID_MIRO_36050	0x5601
+#define PCI_DEVICE_ID_MIRO_DC10PLUS	0x7efe
+#define PCI_DEVICE_ID_MIRO_DC30PLUS	0xd801
+
+#define PCI_VENDOR_ID_NEC		0x1033
+#define PCI_DEVICE_ID_NEC_CBUS_1	0x0001 /* PCI-Cbus Bridge */
+#define PCI_DEVICE_ID_NEC_LOCAL		0x0002 /* Local Bridge */
+#define PCI_DEVICE_ID_NEC_ATM		0x0003 /* ATM LAN Controller */
+#define PCI_DEVICE_ID_NEC_R4000		0x0004 /* R4000 Bridge */
+#define PCI_DEVICE_ID_NEC_486		0x0005 /* 486 Like Peripheral Bus Bridge */
+#define PCI_DEVICE_ID_NEC_ACCEL_1	0x0006 /* Graphic Accelerator */
+#define PCI_DEVICE_ID_NEC_UXBUS		0x0007 /* UX-Bus Bridge */
+#define PCI_DEVICE_ID_NEC_ACCEL_2	0x0008 /* Graphic Accelerator */
+#define PCI_DEVICE_ID_NEC_GRAPH		0x0009 /* PCI-CoreGraph Bridge */
+#define PCI_DEVICE_ID_NEC_VL		0x0016 /* PCI-VL Bridge */
+#define PCI_DEVICE_ID_NEC_STARALPHA2	0x002c /* STAR ALPHA2 */
+#define PCI_DEVICE_ID_NEC_CBUS_2	0x002d /* PCI-Cbus Bridge */
+#define PCI_DEVICE_ID_NEC_USB		0x0035 /* PCI-USB Host */
+#define PCI_DEVICE_ID_NEC_CBUS_3	0x003b
+#define PCI_DEVICE_ID_NEC_NAPCCARD	0x003e
+#define PCI_DEVICE_ID_NEC_PCX2		0x0046 /* PowerVR */
+#define PCI_DEVICE_ID_NEC_NILE4		0x005a
+#define PCI_DEVICE_ID_NEC_VRC5476       0x009b
+#define PCI_DEVICE_ID_NEC_VRC4173	0x00a5
+#define PCI_DEVICE_ID_NEC_VRC5477_AC97  0x00a6
+#define PCI_DEVICE_ID_NEC_PC9821CS01    0x800c /* PC-9821-CS01 */
+#define PCI_DEVICE_ID_NEC_PC9821NRB06   0x800d /* PC-9821NR-B06 */
+
+#define PCI_VENDOR_ID_FD		0x1036
+#define PCI_DEVICE_ID_FD_36C70		0x0000
+
+#define PCI_VENDOR_ID_SI		0x1039
+#define PCI_DEVICE_ID_SI_5591_AGP	0x0001
+#define PCI_DEVICE_ID_SI_6202		0x0002
+#define PCI_DEVICE_ID_SI_503		0x0008
+#define PCI_DEVICE_ID_SI_ACPI		0x0009
+#define PCI_DEVICE_ID_SI_SMBUS		0x0016
+#define PCI_DEVICE_ID_SI_LPC		0x0018
+#define PCI_DEVICE_ID_SI_5597_VGA	0x0200
+#define PCI_DEVICE_ID_SI_6205		0x0205
+#define PCI_DEVICE_ID_SI_501		0x0406
+#define PCI_DEVICE_ID_SI_496		0x0496
+#define PCI_DEVICE_ID_SI_300		0x0300
+#define PCI_DEVICE_ID_SI_315H		0x0310
+#define PCI_DEVICE_ID_SI_315		0x0315
+#define PCI_DEVICE_ID_SI_315PRO		0x0325
+#define PCI_DEVICE_ID_SI_530		0x0530
+#define PCI_DEVICE_ID_SI_540		0x0540
+#define PCI_DEVICE_ID_SI_550		0x0550
+#define PCI_DEVICE_ID_SI_540_VGA	0x5300
+#define PCI_DEVICE_ID_SI_550_VGA	0x5315
+#define PCI_DEVICE_ID_SI_601		0x0601
+#define PCI_DEVICE_ID_SI_620		0x0620
+#define PCI_DEVICE_ID_SI_630		0x0630
+#define PCI_DEVICE_ID_SI_633		0x0633
+#define PCI_DEVICE_ID_SI_635		0x0635
+#define PCI_DEVICE_ID_SI_640		0x0640
+#define PCI_DEVICE_ID_SI_645		0x0645
+#define PCI_DEVICE_ID_SI_646		0x0646
+#define PCI_DEVICE_ID_SI_648		0x0648
+#define PCI_DEVICE_ID_SI_650		0x0650
+#define PCI_DEVICE_ID_SI_651		0x0651
+#define PCI_DEVICE_ID_SI_652		0x0652
+#define PCI_DEVICE_ID_SI_655		0x0655
+#define PCI_DEVICE_ID_SI_661		0x0661
+#define PCI_DEVICE_ID_SI_730		0x0730
+#define PCI_DEVICE_ID_SI_733		0x0733
+#define PCI_DEVICE_ID_SI_630_VGA	0x6300
+#define PCI_DEVICE_ID_SI_730_VGA	0x7300
+#define PCI_DEVICE_ID_SI_735		0x0735
+#define PCI_DEVICE_ID_SI_740		0x0740
+#define PCI_DEVICE_ID_SI_741		0x0741
+#define PCI_DEVICE_ID_SI_745		0x0745
+#define PCI_DEVICE_ID_SI_746		0x0746
+#define PCI_DEVICE_ID_SI_748		0x0748
+#define PCI_DEVICE_ID_SI_750		0x0750
+#define PCI_DEVICE_ID_SI_751		0x0751
+#define PCI_DEVICE_ID_SI_752		0x0752
+#define PCI_DEVICE_ID_SI_755		0x0755
+#define PCI_DEVICE_ID_SI_760		0x0760
+#define PCI_DEVICE_ID_SI_900		0x0900
+#define PCI_DEVICE_ID_SI_961		0x0961
+#define PCI_DEVICE_ID_SI_962		0x0962
+#define PCI_DEVICE_ID_SI_963		0x0963
+#define PCI_DEVICE_ID_SI_5107		0x5107
+#define PCI_DEVICE_ID_SI_5300		0x5300
+#define PCI_DEVICE_ID_SI_5511		0x5511
+#define PCI_DEVICE_ID_SI_5513		0x5513
+#define PCI_DEVICE_ID_SI_5518		0x5518
+#define PCI_DEVICE_ID_SI_5571		0x5571
+#define PCI_DEVICE_ID_SI_5581		0x5581
+#define PCI_DEVICE_ID_SI_5582		0x5582
+#define PCI_DEVICE_ID_SI_5591		0x5591
+#define PCI_DEVICE_ID_SI_5596		0x5596
+#define PCI_DEVICE_ID_SI_5597		0x5597
+#define PCI_DEVICE_ID_SI_5598		0x5598
+#define PCI_DEVICE_ID_SI_5600		0x5600
+#define PCI_DEVICE_ID_SI_6300		0x6300
+#define PCI_DEVICE_ID_SI_6306		0x6306
+#define PCI_DEVICE_ID_SI_6326		0x6326
+#define PCI_DEVICE_ID_SI_7001		0x7001
+#define PCI_DEVICE_ID_SI_7012		0x7012
+#define PCI_DEVICE_ID_SI_7016		0x7016
+
+#define PCI_VENDOR_ID_HP		0x103c
+#define PCI_DEVICE_ID_HP_VISUALIZE_EG	0x1005
+#define PCI_DEVICE_ID_HP_VISUALIZE_FX6	0x1006
+#define PCI_DEVICE_ID_HP_VISUALIZE_FX4	0x1008
+#define PCI_DEVICE_ID_HP_VISUALIZE_FX2	0x100a
+#define PCI_DEVICE_ID_HP_TACHYON	0x1028
+#define PCI_DEVICE_ID_HP_TACHLITE	0x1029
+#define PCI_DEVICE_ID_HP_J2585A		0x1030
+#define PCI_DEVICE_ID_HP_J2585B		0x1031
+#define PCI_DEVICE_ID_HP_J2973A		0x1040
+#define PCI_DEVICE_ID_HP_J2970A		0x1042
+#define PCI_DEVICE_ID_HP_DIVA		0x1048
+#define PCI_DEVICE_ID_HP_DIVA_TOSCA1	0x1049
+#define PCI_DEVICE_ID_HP_DIVA_TOSCA2	0x104A
+#define PCI_DEVICE_ID_HP_DIVA_MAESTRO	0x104B
+#define PCI_DEVICE_ID_HP_PCI_LBA	0x1054
+#define PCI_DEVICE_ID_HP_REO_SBA	0x10f0
+#define PCI_DEVICE_ID_HP_REO_IOC	0x10f1
+#define PCI_DEVICE_ID_HP_VISUALIZE_FXE	0x108b
+#define PCI_DEVICE_ID_HP_DIVA_HALFDOME	0x1223
+#define PCI_DEVICE_ID_HP_DIVA_KEYSTONE	0x1226
+#define PCI_DEVICE_ID_HP_DIVA_POWERBAR	0x1227
+#define PCI_DEVICE_ID_HP_ZX1_SBA	0x1229
+#define PCI_DEVICE_ID_HP_ZX1_IOC	0x122a
+#define PCI_DEVICE_ID_HP_PCIX_LBA	0x122e
+#define PCI_DEVICE_ID_HP_SX1000_IOC	0x127c
+#define PCI_DEVICE_ID_HP_DIVA_EVEREST	0x1282
+#define PCI_DEVICE_ID_HP_DIVA_AUX	0x1290
+#define PCI_DEVICE_ID_HP_DIVA_RMP3	0x1301
+#define PCI_DEVICE_ID_HP_CISSA		0x3220
+#define PCI_DEVICE_ID_HP_CISSB		0x3230
+#define PCI_DEVICE_ID_HP_ZX2_IOC	0x4031
+
+#define PCI_VENDOR_ID_PCTECH		0x1042
+#define PCI_DEVICE_ID_PCTECH_RZ1000	0x1000
+#define PCI_DEVICE_ID_PCTECH_RZ1001	0x1001
+#define PCI_DEVICE_ID_PCTECH_SAMURAI_0	0x3000
+#define PCI_DEVICE_ID_PCTECH_SAMURAI_1	0x3010
+#define PCI_DEVICE_ID_PCTECH_SAMURAI_IDE 0x3020
+
+#define PCI_VENDOR_ID_ASUSTEK		0x1043
+#define PCI_DEVICE_ID_ASUSTEK_0675	0x0675
+
+#define PCI_VENDOR_ID_DPT		0x1044
+#define PCI_DEVICE_ID_DPT		0xa400
+
+#define PCI_VENDOR_ID_OPTI		0x1045
+#define PCI_DEVICE_ID_OPTI_92C178	0xc178
+#define PCI_DEVICE_ID_OPTI_82C557	0xc557
+#define PCI_DEVICE_ID_OPTI_82C558	0xc558
+#define PCI_DEVICE_ID_OPTI_82C621	0xc621
+#define PCI_DEVICE_ID_OPTI_82C700	0xc700
+#define PCI_DEVICE_ID_OPTI_82C701	0xc701
+#define PCI_DEVICE_ID_OPTI_82C814	0xc814
+#define PCI_DEVICE_ID_OPTI_82C822	0xc822
+#define PCI_DEVICE_ID_OPTI_82C861	0xc861
+#define PCI_DEVICE_ID_OPTI_82C825	0xd568
+
+#define PCI_VENDOR_ID_ELSA		0x1048
+#define PCI_DEVICE_ID_ELSA_MICROLINK	0x1000
+#define PCI_DEVICE_ID_ELSA_QS3000	0x3000
+
+#define PCI_VENDOR_ID_SGS		0x104a
+#define PCI_DEVICE_ID_SGS_2000		0x0008
+#define PCI_DEVICE_ID_SGS_1764		0x0009
+
+#define PCI_VENDOR_ID_BUSLOGIC		      0x104B
+#define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER_NC 0x0140
+#define PCI_DEVICE_ID_BUSLOGIC_MULTIMASTER    0x1040
+#define PCI_DEVICE_ID_BUSLOGIC_FLASHPOINT     0x8130
+
+#define PCI_VENDOR_ID_TI		0x104c
+#define PCI_DEVICE_ID_TI_TVP4010	0x3d04
+#define PCI_DEVICE_ID_TI_TVP4020	0x3d07
+#define PCI_DEVICE_ID_TI_4450		0x8011
+#define PCI_DEVICE_ID_TI_1130		0xac12
+#define PCI_DEVICE_ID_TI_1031		0xac13
+#define PCI_DEVICE_ID_TI_1131		0xac15
+#define PCI_DEVICE_ID_TI_1250		0xac16
+#define PCI_DEVICE_ID_TI_1220		0xac17
+#define PCI_DEVICE_ID_TI_1221		0xac19
+#define PCI_DEVICE_ID_TI_1210		0xac1a
+#define PCI_DEVICE_ID_TI_1450		0xac1b
+#define PCI_DEVICE_ID_TI_1225		0xac1c
+#define PCI_DEVICE_ID_TI_1251A		0xac1d
+#define PCI_DEVICE_ID_TI_1211		0xac1e
+#define PCI_DEVICE_ID_TI_1251B		0xac1f
+#define PCI_DEVICE_ID_TI_4410		0xac41
+#define PCI_DEVICE_ID_TI_4451		0xac42
+#define PCI_DEVICE_ID_TI_4510		0xac44
+#define PCI_DEVICE_ID_TI_4520		0xac46
+#define PCI_DEVICE_ID_TI_1410		0xac50
+#define PCI_DEVICE_ID_TI_1420		0xac51
+#define PCI_DEVICE_ID_TI_1451A		0xac52
+#define PCI_DEVICE_ID_TI_1620		0xac54
+#define PCI_DEVICE_ID_TI_1520		0xac55
+#define PCI_DEVICE_ID_TI_1510		0xac56
+
+#define PCI_VENDOR_ID_SONY		0x104d
+#define PCI_DEVICE_ID_SONY_CXD3222	0x8039
+
+#define PCI_VENDOR_ID_OAK		0x104e
+#define PCI_DEVICE_ID_OAK_OTI107	0x0107
+
+/* Winbond have two vendor IDs! See 0x10ad as well */
+#define PCI_VENDOR_ID_WINBOND2		0x1050
+#define PCI_DEVICE_ID_WINBOND2_89C940	0x0940
+#define PCI_DEVICE_ID_WINBOND2_89C940F	0x5a5a
+#define PCI_DEVICE_ID_WINBOND2_6692	0x6692
+
+#define PCI_VENDOR_ID_ANIGMA		0x1051
+#define PCI_DEVICE_ID_ANIGMA_MC145575	0x0100
+  
+#define PCI_VENDOR_ID_EFAR		0x1055
+#define PCI_DEVICE_ID_EFAR_SLC90E66_1	0x9130
+#define PCI_DEVICE_ID_EFAR_SLC90E66_0	0x9460
+#define PCI_DEVICE_ID_EFAR_SLC90E66_2	0x9462
+#define PCI_DEVICE_ID_EFAR_SLC90E66_3	0x9463
+
+#define PCI_VENDOR_ID_MOTOROLA		0x1057
+#define PCI_VENDOR_ID_MOTOROLA_OOPS	0x1507
+#define PCI_DEVICE_ID_MOTOROLA_MPC105	0x0001
+#define PCI_DEVICE_ID_MOTOROLA_MPC106	0x0002
+#define PCI_DEVICE_ID_MOTOROLA_MPC107	0x0004
+#define PCI_DEVICE_ID_MOTOROLA_RAVEN	0x4801
+#define PCI_DEVICE_ID_MOTOROLA_FALCON	0x4802
+#define PCI_DEVICE_ID_MOTOROLA_HAWK	0x4803
+#define PCI_DEVICE_ID_MOTOROLA_CPX8216	0x4806
+#define PCI_DEVICE_ID_MOTOROLA_HARRIER	0x480b
+#define PCI_DEVICE_ID_MOTOROLA_MPC5200	0x5803
+
+#define PCI_VENDOR_ID_PROMISE		0x105a
+#define PCI_DEVICE_ID_PROMISE_20265	0x0d30
+#define PCI_DEVICE_ID_PROMISE_20267	0x4d30
+#define PCI_DEVICE_ID_PROMISE_20246	0x4d33
+#define PCI_DEVICE_ID_PROMISE_20262	0x4d38
+#define PCI_DEVICE_ID_PROMISE_20263	0x0D38
+#define PCI_DEVICE_ID_PROMISE_20268	0x4d68
+#define PCI_DEVICE_ID_PROMISE_20268R	0x6268
+#define PCI_DEVICE_ID_PROMISE_20269	0x4d69
+#define PCI_DEVICE_ID_PROMISE_20270	0x6268
+#define PCI_DEVICE_ID_PROMISE_20271	0x6269
+#define PCI_DEVICE_ID_PROMISE_20275	0x1275
+#define PCI_DEVICE_ID_PROMISE_20276	0x5275
+#define PCI_DEVICE_ID_PROMISE_20277	0x7275
+#define PCI_DEVICE_ID_PROMISE_5300	0x5300
+
+#define PCI_VENDOR_ID_N9		0x105d
+#define PCI_DEVICE_ID_N9_I128		0x2309
+#define PCI_DEVICE_ID_N9_I128_2		0x2339
+#define PCI_DEVICE_ID_N9_I128_T2R	0x493d
+
+#define PCI_VENDOR_ID_UMC		0x1060
+#define PCI_DEVICE_ID_UMC_UM8673F	0x0101
+#define PCI_DEVICE_ID_UMC_UM8891A	0x0891
+#define PCI_DEVICE_ID_UMC_UM8886BF	0x673a
+#define PCI_DEVICE_ID_UMC_UM8886A	0x886a
+#define PCI_DEVICE_ID_UMC_UM8881F	0x8881
+#define PCI_DEVICE_ID_UMC_UM8886F	0x8886
+#define PCI_DEVICE_ID_UMC_UM9017F	0x9017
+#define PCI_DEVICE_ID_UMC_UM8886N	0xe886
+#define PCI_DEVICE_ID_UMC_UM8891N	0xe891
+
+#define PCI_VENDOR_ID_X			0x1061
+#define PCI_DEVICE_ID_X_AGX016		0x0001
+
+#define PCI_VENDOR_ID_MYLEX		0x1069
+#define PCI_DEVICE_ID_MYLEX_DAC960_P	0x0001
+#define PCI_DEVICE_ID_MYLEX_DAC960_PD	0x0002
+#define PCI_DEVICE_ID_MYLEX_DAC960_PG	0x0010
+#define PCI_DEVICE_ID_MYLEX_DAC960_LA	0x0020
+#define PCI_DEVICE_ID_MYLEX_DAC960_LP	0x0050
+#define PCI_DEVICE_ID_MYLEX_DAC960_BA	0xBA56
+#define PCI_DEVICE_ID_MYLEX_DAC960_GEM	0xB166
+
+#define PCI_VENDOR_ID_PICOP		0x1066
+#define PCI_DEVICE_ID_PICOP_PT86C52X	0x0001
+#define PCI_DEVICE_ID_PICOP_PT80C524	0x8002
+
+#define PCI_VENDOR_ID_APPLE		0x106b
+#define PCI_DEVICE_ID_APPLE_BANDIT	0x0001
+#define PCI_DEVICE_ID_APPLE_GC		0x0002
+#define PCI_DEVICE_ID_APPLE_HYDRA	0x000e
+#define PCI_DEVICE_ID_APPLE_UNI_N_FW	0x0018
+#define PCI_DEVICE_ID_APPLE_KL_USB	0x0019
+#define PCI_DEVICE_ID_APPLE_UNI_N_AGP	0x0020
+#define PCI_DEVICE_ID_APPLE_UNI_N_GMAC	0x0021
+#define PCI_DEVICE_ID_APPLE_KEYLARGO	0x0022
+#define PCI_DEVICE_ID_APPLE_UNI_N_GMACP	0x0024
+#define PCI_DEVICE_ID_APPLE_KEYLARGO_P	0x0025
+#define PCI_DEVICE_ID_APPLE_KL_USB_P	0x0026
+#define PCI_DEVICE_ID_APPLE_UNI_N_AGP_P	0x0027
+#define PCI_DEVICE_ID_APPLE_UNI_N_AGP15	0x002d
+#define PCI_DEVICE_ID_APPLE_UNI_N_PCI15	0x002e
+#define PCI_DEVICE_ID_APPLE_UNI_N_FW2	0x0030
+#define PCI_DEVICE_ID_APPLE_UNI_N_GMAC2	0x0032
+#define PCI_DEVIEC_ID_APPLE_UNI_N_ATA	0x0033
+#define PCI_DEVICE_ID_APPLE_UNI_N_AGP2	0x0034
+#define PCI_DEVICE_ID_APPLE_IPID_ATA100	0x003b
+#define PCI_DEVICE_ID_APPLE_KEYLARGO_I	0x003e
+#define PCI_DEVICE_ID_APPLE_K2_ATA100	0x0043
+#define PCI_DEVICE_ID_APPLE_U3_AGP	0x004b
+#define PCI_DEVICE_ID_APPLE_K2_GMAC	0x004c
+#define PCI_DEVICE_ID_APPLE_SH_ATA      0x0050
+#define PCI_DEVICE_ID_APPLE_SH_SUNGEM   0x0051
+#define PCI_DEVICE_ID_APPLE_SH_FW       0x0052
+#define PCI_DEVICE_ID_APPLE_U3L_AGP	0x0058
+#define PCI_DEVICE_ID_APPLE_U3H_AGP	0x0059
+#define PCI_DEVICE_ID_APPLE_TIGON3	0x1645
+
+#define PCI_VENDOR_ID_YAMAHA		0x1073
+#define PCI_DEVICE_ID_YAMAHA_724	0x0004
+#define PCI_DEVICE_ID_YAMAHA_724F	0x000d
+#define PCI_DEVICE_ID_YAMAHA_740	0x000a
+#define PCI_DEVICE_ID_YAMAHA_740C	0x000c
+#define PCI_DEVICE_ID_YAMAHA_744	0x0010
+#define PCI_DEVICE_ID_YAMAHA_754	0x0012
+
+#define PCI_VENDOR_ID_NEXGEN		0x1074
+#define PCI_DEVICE_ID_NEXGEN_82C501	0x4e78
+
+#define PCI_VENDOR_ID_QLOGIC		0x1077
+#define PCI_DEVICE_ID_QLOGIC_ISP1020	0x1020
+#define PCI_DEVICE_ID_QLOGIC_ISP1022	0x1022
+#define PCI_DEVICE_ID_QLOGIC_ISP2100	0x2100
+#define PCI_DEVICE_ID_QLOGIC_ISP2200	0x2200
+
+#define PCI_VENDOR_ID_CYRIX		0x1078
+#define PCI_DEVICE_ID_CYRIX_5510	0x0000
+#define PCI_DEVICE_ID_CYRIX_PCI_MASTER	0x0001
+#define PCI_DEVICE_ID_CYRIX_5520	0x0002
+#define PCI_DEVICE_ID_CYRIX_5530_LEGACY	0x0100
+#define PCI_DEVICE_ID_CYRIX_5530_SMI	0x0101
+#define PCI_DEVICE_ID_CYRIX_5530_IDE	0x0102
+#define PCI_DEVICE_ID_CYRIX_5530_AUDIO	0x0103
+#define PCI_DEVICE_ID_CYRIX_5530_VIDEO	0x0104
+
+#define PCI_VENDOR_ID_LEADTEK		0x107d
+#define PCI_DEVICE_ID_LEADTEK_805	0x0000
+
+#define PCI_VENDOR_ID_INTERPHASE	0x107e
+#define PCI_DEVICE_ID_INTERPHASE_5526	0x0004
+#define PCI_DEVICE_ID_INTERPHASE_55x6	0x0005
+#define PCI_DEVICE_ID_INTERPHASE_5575	0x0008
+
+#define PCI_VENDOR_ID_CONTAQ		0x1080
+#define PCI_DEVICE_ID_CONTAQ_82C599	0x0600
+#define PCI_DEVICE_ID_CONTAQ_82C693	0xc693
+
+#define PCI_VENDOR_ID_FOREX		0x1083
+
+#define PCI_VENDOR_ID_OLICOM		0x108d
+#define PCI_DEVICE_ID_OLICOM_OC3136	0x0001
+#define PCI_DEVICE_ID_OLICOM_OC2315	0x0011
+#define PCI_DEVICE_ID_OLICOM_OC2325	0x0012
+#define PCI_DEVICE_ID_OLICOM_OC2183	0x0013
+#define PCI_DEVICE_ID_OLICOM_OC2326	0x0014
+#define PCI_DEVICE_ID_OLICOM_OC6151	0x0021
+
+#define PCI_VENDOR_ID_SUN		0x108e
+#define PCI_DEVICE_ID_SUN_EBUS		0x1000
+#define PCI_DEVICE_ID_SUN_HAPPYMEAL	0x1001
+#define PCI_DEVICE_ID_SUN_RIO_EBUS	0x1100
+#define PCI_DEVICE_ID_SUN_RIO_GEM	0x1101
+#define PCI_DEVICE_ID_SUN_RIO_1394	0x1102
+#define PCI_DEVICE_ID_SUN_RIO_USB	0x1103
+#define PCI_DEVICE_ID_SUN_GEM		0x2bad
+#define PCI_DEVICE_ID_SUN_SIMBA		0x5000
+#define PCI_DEVICE_ID_SUN_PBM		0x8000
+#define PCI_DEVICE_ID_SUN_SCHIZO	0x8001
+#define PCI_DEVICE_ID_SUN_SABRE		0xa000
+#define PCI_DEVICE_ID_SUN_HUMMINGBIRD	0xa001
+#define PCI_DEVICE_ID_SUN_TOMATILLO	0xa801
+
+#define PCI_VENDOR_ID_CMD		0x1095
+#define PCI_DEVICE_ID_CMD_640		0x0640
+#define PCI_DEVICE_ID_CMD_643		0x0643
+#define PCI_DEVICE_ID_CMD_646		0x0646
+#define PCI_DEVICE_ID_CMD_647		0x0647
+#define PCI_DEVICE_ID_CMD_648		0x0648
+#define PCI_DEVICE_ID_CMD_649		0x0649
+#define PCI_DEVICE_ID_CMD_670		0x0670
+#define PCI_DEVICE_ID_CMD_680		0x0680
+
+#define PCI_DEVICE_ID_SII_680		0x0680
+#define PCI_DEVICE_ID_SII_3112		0x3112
+#define PCI_DEVICE_ID_SII_1210SA	0x0240
+
+#define PCI_VENDOR_ID_VISION		0x1098
+#define PCI_DEVICE_ID_VISION_QD8500	0x0001
+#define PCI_DEVICE_ID_VISION_QD8580	0x0002
+
+#define PCI_VENDOR_ID_BROOKTREE		0x109e
+#define PCI_DEVICE_ID_BROOKTREE_848	0x0350
+#define PCI_DEVICE_ID_BROOKTREE_849A	0x0351
+#define PCI_DEVICE_ID_BROOKTREE_878_1	0x036e
+#define PCI_DEVICE_ID_BROOKTREE_878	0x0878
+#define PCI_DEVICE_ID_BROOKTREE_8474	0x8474
+
+#define PCI_VENDOR_ID_SIERRA		0x10a8
+#define PCI_DEVICE_ID_SIERRA_STB	0x0000
+
+#define PCI_VENDOR_ID_SGI		0x10a9
+#define PCI_DEVICE_ID_SGI_IOC3		0x0003
+#define PCI_DEVICE_ID_SGI_IOC4		0x100a
+#define PCI_VENDOR_ID_SGI_LITHIUM	0x1002
+
+#define PCI_VENDOR_ID_ACC		0x10aa
+#define PCI_DEVICE_ID_ACC_2056		0x0000
+
+#define PCI_VENDOR_ID_WINBOND		0x10ad
+#define PCI_DEVICE_ID_WINBOND_83769	0x0001
+#define PCI_DEVICE_ID_WINBOND_82C105	0x0105
+#define PCI_DEVICE_ID_WINBOND_83C553	0x0565
+
+#define PCI_VENDOR_ID_DATABOOK		0x10b3
+#define PCI_DEVICE_ID_DATABOOK_87144	0xb106
+
+#define PCI_VENDOR_ID_PLX		0x10b5
+#define PCI_DEVICE_ID_PLX_R685		0x1030
+#define PCI_DEVICE_ID_PLX_ROMULUS	0x106a
+#define PCI_DEVICE_ID_PLX_SPCOM800	0x1076
+#define PCI_DEVICE_ID_PLX_1077		0x1077
+#define PCI_DEVICE_ID_PLX_SPCOM200	0x1103
+#define PCI_DEVICE_ID_PLX_DJINN_ITOO	0x1151
+#define PCI_DEVICE_ID_PLX_R753		0x1152
+#define PCI_DEVICE_ID_PLX_9030		0x9030
+#define PCI_DEVICE_ID_PLX_9050		0x9050
+#define PCI_DEVICE_ID_PLX_9060		0x9060
+#define PCI_DEVICE_ID_PLX_9060ES	0x906E
+#define PCI_DEVICE_ID_PLX_9060SD	0x906D
+#define PCI_DEVICE_ID_PLX_9080		0x9080
+#define PCI_DEVICE_ID_PLX_GTEK_SERIAL2	0xa001
+
+#define PCI_VENDOR_ID_MADGE		0x10b6
+#define PCI_DEVICE_ID_MADGE_MK2		0x0002
+#define PCI_DEVICE_ID_MADGE_C155S	0x1001
+
+#define PCI_VENDOR_ID_3COM		0x10b7
+#define PCI_DEVICE_ID_3COM_3C985	0x0001
+#define PCI_DEVICE_ID_3COM_3C940	0x1700
+#define PCI_DEVICE_ID_3COM_3C339	0x3390
+#define PCI_DEVICE_ID_3COM_3C359	0x3590
+#define PCI_DEVICE_ID_3COM_3C590	0x5900
+#define PCI_DEVICE_ID_3COM_3C595TX	0x5950
+#define PCI_DEVICE_ID_3COM_3C595T4	0x5951
+#define PCI_DEVICE_ID_3COM_3C595MII	0x5952
+#define PCI_DEVICE_ID_3COM_3C940B	0x80eb
+#define PCI_DEVICE_ID_3COM_3C900TPO	0x9000
+#define PCI_DEVICE_ID_3COM_3C900COMBO	0x9001
+#define PCI_DEVICE_ID_3COM_3C905TX	0x9050
+#define PCI_DEVICE_ID_3COM_3C905T4	0x9051
+#define PCI_DEVICE_ID_3COM_3C905B_TX	0x9055
+#define PCI_DEVICE_ID_3COM_3CR990	0x9900
+#define PCI_DEVICE_ID_3COM_3CR990_TX_95	0x9902
+#define PCI_DEVICE_ID_3COM_3CR990_TX_97	0x9903
+#define PCI_DEVICE_ID_3COM_3CR990B	0x9904
+#define PCI_DEVICE_ID_3COM_3CR990_FX	0x9905
+#define PCI_DEVICE_ID_3COM_3CR990SVR95	0x9908
+#define PCI_DEVICE_ID_3COM_3CR990SVR97	0x9909
+#define PCI_DEVICE_ID_3COM_3CR990SVR	0x990a
+
+#define PCI_VENDOR_ID_SMC		0x10b8
+#define PCI_DEVICE_ID_SMC_EPIC100	0x0005
+
+#define PCI_VENDOR_ID_AL		0x10b9
+#define PCI_DEVICE_ID_AL_M1445		0x1445
+#define PCI_DEVICE_ID_AL_M1449		0x1449
+#define PCI_DEVICE_ID_AL_M1451		0x1451
+#define PCI_DEVICE_ID_AL_M1461		0x1461
+#define PCI_DEVICE_ID_AL_M1489		0x1489
+#define PCI_DEVICE_ID_AL_M1511		0x1511
+#define PCI_DEVICE_ID_AL_M1513		0x1513
+#define PCI_DEVICE_ID_AL_M1521		0x1521
+#define PCI_DEVICE_ID_AL_M1523		0x1523
+#define PCI_DEVICE_ID_AL_M1531		0x1531
+#define PCI_DEVICE_ID_AL_M1533		0x1533
+#define PCI_DEVICE_ID_AL_M1535 		0x1535
+#define PCI_DEVICE_ID_AL_M1541		0x1541
+#define PCI_DEVICE_ID_AL_M1543		0x1543
+#define PCI_DEVICE_ID_AL_M1563		0x1563
+#define PCI_DEVICE_ID_AL_M1621		0x1621
+#define PCI_DEVICE_ID_AL_M1631		0x1631
+#define PCI_DEVICE_ID_AL_M1632		0x1632
+#define PCI_DEVICE_ID_AL_M1641		0x1641
+#define PCI_DEVICE_ID_AL_M1644		0x1644
+#define PCI_DEVICE_ID_AL_M1647		0x1647
+#define PCI_DEVICE_ID_AL_M1651		0x1651
+#define PCI_DEVICE_ID_AL_M1671		0x1671
+#define PCI_DEVICE_ID_AL_M1681		0x1681
+#define PCI_DEVICE_ID_AL_M1683		0x1683
+#define PCI_DEVICE_ID_AL_M1689		0x1689
+#define PCI_DEVICE_ID_AL_M3307		0x3307
+#define PCI_DEVICE_ID_AL_M4803		0x5215
+#define PCI_DEVICE_ID_AL_M5219		0x5219
+#define PCI_DEVICE_ID_AL_M5228		0x5228
+#define PCI_DEVICE_ID_AL_M5229		0x5229
+#define PCI_DEVICE_ID_AL_M5237		0x5237
+#define PCI_DEVICE_ID_AL_M5243		0x5243
+#define PCI_DEVICE_ID_AL_M5451		0x5451
+#define PCI_DEVICE_ID_AL_M7101		0x7101
+
+#define PCI_VENDOR_ID_MITSUBISHI	0x10ba
+
+#define PCI_VENDOR_ID_SURECOM		0x10bd
+#define PCI_DEVICE_ID_SURECOM_NE34	0x0e34
+
+#define PCI_VENDOR_ID_NEOMAGIC		0x10c8
+#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_NM2070 0x0001
+#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_128V 0x0002
+#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_128ZV 0x0003
+#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_NM2160 0x0004
+#define PCI_DEVICE_ID_NEOMAGIC_MAGICMEDIA_256AV       0x0005
+#define PCI_DEVICE_ID_NEOMAGIC_MAGICGRAPH_128ZVPLUS   0x0083
+
+#define PCI_VENDOR_ID_ASP		0x10cd
+#define PCI_DEVICE_ID_ASP_ABP940	0x1200
+#define PCI_DEVICE_ID_ASP_ABP940U	0x1300
+#define PCI_DEVICE_ID_ASP_ABP940UW	0x2300
+
+#define PCI_VENDOR_ID_MACRONIX		0x10d9
+#define PCI_DEVICE_ID_MACRONIX_MX98713	0x0512
+#define PCI_DEVICE_ID_MACRONIX_MX987x5	0x0531
+
+#define PCI_VENDOR_ID_TCONRAD		0x10da
+#define PCI_DEVICE_ID_TCONRAD_TOKENRING	0x0508
+
+#define PCI_VENDOR_ID_CERN		0x10dc
+#define PCI_DEVICE_ID_CERN_SPSB_PMC	0x0001
+#define PCI_DEVICE_ID_CERN_SPSB_PCI	0x0002
+#define PCI_DEVICE_ID_CERN_HIPPI_DST	0x0021
+#define PCI_DEVICE_ID_CERN_HIPPI_SRC	0x0022
+
+#define PCI_VENDOR_ID_NVIDIA			0x10de
+#define PCI_DEVICE_ID_NVIDIA_TNT		0x0020
+#define PCI_DEVICE_ID_NVIDIA_TNT2		0x0028
+#define PCI_DEVICE_ID_NVIDIA_UTNT2		0x0029
+#define PCI_DEVICE_ID_NVIDIA_TNT_UNKNOWN        0x002a
+#define PCI_DEVICE_ID_NVIDIA_VTNT2		0x002C
+#define PCI_DEVICE_ID_NVIDIA_UVTNT2		0x002D
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_IDE	0x0035
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA	0x0036
+#define PCI_DEVICE_ID_NVIDIA_NVENET_10		0x0037
+#define PCI_DEVICE_ID_NVIDIA_NVENET_11		0x0038
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA2	0x003e
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_ULTRA 0x0040
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800       0x0041
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_LE    0x0042
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800_GT    0x0045
+#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_4000     0x004E
+#define PCI_DEVICE_ID_NVIDIA_NFORCE4_SMBUS	0x0052
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_IDE	0x0053
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA	0x0054
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA2	0x0055
+#define PCI_DEVICE_ID_NVIDIA_NVENET_8		0x0056
+#define PCI_DEVICE_ID_NVIDIA_NVENET_9		0x0057
+#define PCI_DEVICE_ID_NVIDIA_CK804_AUDIO	0x0059
+#define PCI_DEVICE_ID_NVIDIA_NFORCE2_SMBUS	0x0064
+#define PCI_DEVICE_ID_NVIDIA_NFORCE2_IDE	0x0065
+#define PCI_DEVICE_ID_NVIDIA_NVENET_2		0x0066
+#define PCI_DEVICE_ID_NVIDIA_MCP2_AUDIO		0x006a
+#define PCI_DEVICE_ID_NVIDIA_NFORCE2S_SMBUS	0x0084
+#define PCI_DEVICE_ID_NVIDIA_NFORCE2S_IDE	0x0085
+#define PCI_DEVICE_ID_NVIDIA_NVENET_4		0x0086
+#define PCI_DEVICE_ID_NVIDIA_NVENET_5		0x008c
+#define PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA	0x008e
+#define PCI_DEVICE_ID_NVIDIA_ITNT2		0x00A0
+#define PCI_DEVICE_ID_GEFORCE_6800A             0x00c1
+#define PCI_DEVICE_ID_GEFORCE_6800A_LE          0x00c2
+#define PCI_DEVICE_ID_GEFORCE_GO_6800           0x00c8
+#define PCI_DEVICE_ID_GEFORCE_GO_6800_ULTRA     0x00c9
+#define PCI_DEVICE_ID_QUADRO_FX_GO1400          0x00cc
+#define PCI_DEVICE_ID_QUADRO_FX_1400            0x00ce
+#define PCI_DEVICE_ID_NVIDIA_NFORCE3		0x00d1
+#define PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO		0x00da
+#define PCI_DEVICE_ID_NVIDIA_NFORCE3_SMBUS	0x00d4
+#define PCI_DEVICE_ID_NVIDIA_NFORCE3_IDE	0x00d5
+#define PCI_DEVICE_ID_NVIDIA_NVENET_3		0x00d6
+#define PCI_DEVICE_ID_NVIDIA_MCP3_AUDIO		0x00da
+#define PCI_DEVICE_ID_NVIDIA_NVENET_7		0x00df
+#define PCI_DEVICE_ID_NVIDIA_NFORCE3S		0x00e1
+#define PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA	0x00e3
+#define PCI_DEVICE_ID_NVIDIA_NFORCE3S_SMBUS	0x00e4
+#define PCI_DEVICE_ID_NVIDIA_NFORCE3S_IDE	0x00e5
+#define PCI_DEVICE_ID_NVIDIA_NVENET_6		0x00e6
+#define PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2	0x00ee
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_SDR	0x0100
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_DDR	0x0101
+#define PCI_DEVICE_ID_NVIDIA_QUADRO		0x0103
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX	0x0110
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_MX2	0x0111
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_GO	0x0112
+#define PCI_DEVICE_ID_NVIDIA_QUADRO2_MXR	0x0113
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6600_GT	0x0140
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6600	0x0141
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6610_XL	0x0145
+#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_540	0x014E
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6200	0x014F
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS	0x0150
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_GTS2	0x0151
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE2_ULTRA	0x0152
+#define PCI_DEVICE_ID_NVIDIA_QUADRO2_PRO	0x0153
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6200_TURBOCACHE 0x0161
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6200    0x0164
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6250    0x0166
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6200_1  0x0167
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_GO_6250_1  0x0168
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_460	0x0170
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440	0x0171
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420	0x0172
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440_SE	0x0173
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO	0x0174
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO	0x0175
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_420_GO_M32 0x0176
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_460_GO    0x0177
+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_500XGL	0x0178
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_440_GO_M64 0x0179
+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_200	0x017A
+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_550XGL	0x017B
+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_500_GOGL	0x017C
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_410_GO_M16 0x017D
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440_8X 0x0181
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_440SE_8X 0x0182
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_420_8X 0x0183
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_448_GO    0x0186
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_488_GO    0x0187
+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_580_XGL    0x0188
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_MX_MAC    0x0189
+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_280_NVS    0x018A
+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_380_XGL    0x018B
+#define PCI_DEVICE_ID_NVIDIA_IGEFORCE2		0x01a0
+#define PCI_DEVICE_ID_NVIDIA_NFORCE		0x01a4
+#define PCI_DEVICE_ID_NVIDIA_MCP1_AUDIO		0x01b1
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_SMBUS	0x01b4
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_IDE		0x01bc
+#define PCI_DEVICE_ID_NVIDIA_NVENET_1		0x01c3
+#define PCI_DEVICE_ID_NVIDIA_NFORCE2		0x01e0
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE3		0x0200
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE3_1		0x0201
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE3_2		0x0202
+#define PCI_DEVICE_ID_NVIDIA_QUADRO_DDC		0x0203
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B      0x0211
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B_LE   0x0212
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_6800B_GT   0x0215
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4600	0x0250
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4400	0x0251
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4200	0x0253
+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_900XGL	0x0258
+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_750XGL	0x0259
+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_700XGL	0x025B
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_IDE	0x0265
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA	0x0266
+#define PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2	0x0267
+#define PCI_DEVICE_ID_NVIDIA_NVENET_12		0x0268
+#define PCI_DEVICE_ID_NVIDIA_NVENET_13		0x0269
+#define PCI_DEVICE_ID_NVIDIA_MCP51_AUDIO	0x026B
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800	0x0280
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800_8X    0x0281
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_TI_4800SE     0x0282
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE4_4200_GO       0x0286
+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_980_XGL        0x0288
+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_780_XGL        0x0289
+#define PCI_DEVICE_ID_NVIDIA_QUADRO4_700_GOGL       0x028C
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5800_ULTRA  0x0301
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5800        0x0302
+#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_2000         0x0308
+#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_1000         0x0309
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600_ULTRA  0x0311
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600        0x0312
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5600SE      0x0314
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5600      0x031A
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5650      0x031B
+#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_GO700        0x031C
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200        0x0320
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200_ULTRA  0x0321
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200_1      0x0322
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5200SE      0x0323
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5200      0x0324
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5250      0x0325
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5500        0x0326
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5100        0x0327
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5250_32   0x0328
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO_5200	    0x0329
+#define PCI_DEVICE_ID_NVIDIA_QUADRO_NVS_280_PCI     0x032A
+#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_500          0x032B
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5300      0x032C
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5100      0x032D
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900_ULTRA  0x0330
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900        0x0331
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900XT      0x0332
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5950_ULTRA  0x0333
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5900ZT      0x0334
+#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_3000         0x0338
+#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_700          0x033F
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700_ULTRA  0x0341
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700        0x0342
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700LE      0x0343
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_5700VE      0x0344
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5700_1    0x0347
+#define PCI_DEVICE_ID_NVIDIA_GEFORCE_FX_GO5700_2    0x0348
+#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_GO1000       0x034C
+#define PCI_DEVICE_ID_NVIDIA_QUADRO_FX_1100         0x034E
+
+#define PCI_VENDOR_ID_IMS		0x10e0
+#define PCI_DEVICE_ID_IMS_8849		0x8849
+#define PCI_DEVICE_ID_IMS_TT128		0x9128
+#define PCI_DEVICE_ID_IMS_TT3D		0x9135
+
+#define PCI_VENDOR_ID_TEKRAM2		0x10e1
+#define PCI_DEVICE_ID_TEKRAM2_690c	0x690c
+
+#define PCI_VENDOR_ID_TUNDRA		0x10e3
+#define PCI_DEVICE_ID_TUNDRA_CA91C042	0x0000
+
+#define PCI_VENDOR_ID_AMCC		0x10e8
+#define PCI_DEVICE_ID_AMCC_MYRINET	0x8043
+#define PCI_DEVICE_ID_AMCC_PARASTATION	0x8062
+#define PCI_DEVICE_ID_AMCC_S5933	0x807d
+#define PCI_DEVICE_ID_AMCC_S5933_HEPC3	0x809c
+
+#define PCI_VENDOR_ID_INTERG		0x10ea
+#define PCI_DEVICE_ID_INTERG_1680	0x1680
+#define PCI_DEVICE_ID_INTERG_1682	0x1682
+#define PCI_DEVICE_ID_INTERG_2000	0x2000
+#define PCI_DEVICE_ID_INTERG_2010	0x2010
+#define PCI_DEVICE_ID_INTERG_5000	0x5000
+#define PCI_DEVICE_ID_INTERG_5050	0x5050
+
+#define PCI_VENDOR_ID_REALTEK		0x10ec
+#define PCI_DEVICE_ID_REALTEK_8029	0x8029
+#define PCI_DEVICE_ID_REALTEK_8129	0x8129
+#define PCI_DEVICE_ID_REALTEK_8139	0x8139
+#define PCI_DEVICE_ID_REALTEK_8169	0x8169
+
+#define PCI_VENDOR_ID_XILINX		0x10ee
+#define PCI_DEVICE_ID_TURBOPAM		0x4020
+
+#define PCI_VENDOR_ID_TRUEVISION	0x10fa
+#define PCI_DEVICE_ID_TRUEVISION_T1000	0x000c
+
+#define PCI_VENDOR_ID_INIT		0x1101
+#define PCI_DEVICE_ID_INIT_320P		0x9100
+#define PCI_DEVICE_ID_INIT_360P		0x9500
+
+#define PCI_VENDOR_ID_CREATIVE		0x1102 // duplicate: ECTIVA
+#define PCI_DEVICE_ID_CREATIVE_EMU10K1	0x0002
+
+#define PCI_VENDOR_ID_ECTIVA		0x1102 // duplicate: CREATIVE
+#define PCI_DEVICE_ID_ECTIVA_EV1938	0x8938
+
+#define PCI_VENDOR_ID_TTI		0x1103
+#define PCI_DEVICE_ID_TTI_HPT343	0x0003
+#define PCI_DEVICE_ID_TTI_HPT366	0x0004
+#define PCI_DEVICE_ID_TTI_HPT372	0x0005
+#define PCI_DEVICE_ID_TTI_HPT302	0x0006
+#define PCI_DEVICE_ID_TTI_HPT371	0x0007
+#define PCI_DEVICE_ID_TTI_HPT374	0x0008
+#define PCI_DEVICE_ID_TTI_HPT372N	0x0009	// apparently a 372N variant?
+
+#define PCI_VENDOR_ID_VIA		0x1106
+#define PCI_DEVICE_ID_VIA_8763_0	0x0198
+#define PCI_DEVICE_ID_VIA_8380_0	0x0204
+#define PCI_DEVICE_ID_VIA_3238_0	0x0238
+#define PCI_DEVICE_ID_VIA_PT880		0x0258
+#define PCI_DEVICE_ID_VIA_PX8X0_0	0x0259
+#define PCI_DEVICE_ID_VIA_3269_0	0x0269
+#define PCI_DEVICE_ID_VIA_K8T800PRO_0	0x0282
+#define PCI_DEVICE_ID_VIA_8363_0	0x0305
+#define PCI_DEVICE_ID_VIA_8371_0	0x0391
+#define PCI_DEVICE_ID_VIA_8501_0	0x0501
+#define PCI_DEVICE_ID_VIA_82C505	0x0505
+#define PCI_DEVICE_ID_VIA_82C561	0x0561
+#define PCI_DEVICE_ID_VIA_82C586_1	0x0571
+#define PCI_DEVICE_ID_VIA_82C576	0x0576
+#define PCI_DEVICE_ID_VIA_82C585	0x0585
+#define PCI_DEVICE_ID_VIA_82C586_0	0x0586
+#define PCI_DEVICE_ID_VIA_82C595	0x0595
+#define PCI_DEVICE_ID_VIA_82C596	0x0596
+#define PCI_DEVICE_ID_VIA_82C597_0	0x0597
+#define PCI_DEVICE_ID_VIA_82C598_0	0x0598
+#define PCI_DEVICE_ID_VIA_8601_0	0x0601
+#define PCI_DEVICE_ID_VIA_8605_0	0x0605
+#define PCI_DEVICE_ID_VIA_82C680	0x0680
+#define PCI_DEVICE_ID_VIA_82C686	0x0686
+#define PCI_DEVICE_ID_VIA_82C691_0	0x0691
+#define PCI_DEVICE_ID_VIA_82C693	0x0693
+#define PCI_DEVICE_ID_VIA_82C693_1	0x0698
+#define PCI_DEVICE_ID_VIA_82C926	0x0926
+#define PCI_DEVICE_ID_VIA_82C576_1	0x1571
+#define PCI_DEVICE_ID_VIA_82C595_97	0x1595
+#define PCI_DEVICE_ID_VIA_82C586_2	0x3038
+#define PCI_DEVICE_ID_VIA_82C586_3	0x3040
+#define PCI_DEVICE_ID_VIA_6305		0x3044
+#define PCI_DEVICE_ID_VIA_82C596_3	0x3050
+#define PCI_DEVICE_ID_VIA_82C596B_3	0x3051
+#define PCI_DEVICE_ID_VIA_82C686_4	0x3057
+#define PCI_DEVICE_ID_VIA_82C686_5	0x3058
+#define PCI_DEVICE_ID_VIA_8233_5	0x3059
+#define PCI_DEVICE_ID_VIA_8233_7	0x3065
+#define PCI_DEVICE_ID_VIA_82C686_6	0x3068
+#define PCI_DEVICE_ID_VIA_8233_0	0x3074
+#define PCI_DEVICE_ID_VIA_8633_0	0x3091
+#define PCI_DEVICE_ID_VIA_8367_0	0x3099
+#define PCI_DEVICE_ID_VIA_8653_0	0x3101
+#define PCI_DEVICE_ID_VIA_8622		0x3102
+#define PCI_DEVICE_ID_VIA_8233C_0	0x3109
+#define PCI_DEVICE_ID_VIA_8361		0x3112
+#define PCI_DEVICE_ID_VIA_XM266		0x3116
+#define PCI_DEVICE_ID_VIA_612X		0x3119
+#define PCI_DEVICE_ID_VIA_862X_0	0x3123
+#define PCI_DEVICE_ID_VIA_8753_0	0x3128
+#define PCI_DEVICE_ID_VIA_8233A		0x3147
+#define PCI_DEVICE_ID_VIA_8703_51_0	0x3148
+#define PCI_DEVICE_ID_VIA_8237_SATA	0x3149
+#define PCI_DEVICE_ID_VIA_XN266		0x3156
+#define PCI_DEVICE_ID_VIA_8754C_0	0x3168
+#define PCI_DEVICE_ID_VIA_8235		0x3177
+#define PCI_DEVICE_ID_VIA_P4N333	0x3178
+#define PCI_DEVICE_ID_VIA_8385_0	0x3188
+#define PCI_DEVICE_ID_VIA_8377_0	0x3189
+#define PCI_DEVICE_ID_VIA_8378_0	0x3205
+#define PCI_DEVICE_ID_VIA_8783_0	0x3208
+#define PCI_DEVICE_ID_VIA_P4M400	0x3209
+#define PCI_DEVICE_ID_VIA_8237		0x3227
+#define PCI_DEVICE_ID_VIA_3296_0	0x0296
+#define PCI_DEVICE_ID_VIA_86C100A	0x6100
+#define PCI_DEVICE_ID_VIA_8231		0x8231
+#define PCI_DEVICE_ID_VIA_8231_4	0x8235
+#define PCI_DEVICE_ID_VIA_8365_1	0x8305
+#define PCI_DEVICE_ID_VIA_8371_1	0x8391
+#define PCI_DEVICE_ID_VIA_8501_1	0x8501
+#define PCI_DEVICE_ID_VIA_82C597_1	0x8597
+#define PCI_DEVICE_ID_VIA_82C598_1	0x8598
+#define PCI_DEVICE_ID_VIA_8601_1	0x8601
+#define PCI_DEVICE_ID_VIA_8505_1	0x8605
+#define PCI_DEVICE_ID_VIA_8633_1	0xB091
+#define PCI_DEVICE_ID_VIA_8367_1	0xB099
+#define PCI_DEVICE_ID_VIA_P4X266_1	0xB101
+#define PCI_DEVICE_ID_VIA_8615_1	0xB103
+#define PCI_DEVICE_ID_VIA_8361_1	0xB112
+#define PCI_DEVICE_ID_VIA_8235_1	0xB168
+#define PCI_DEVICE_ID_VIA_838X_1	0xB188
+#define PCI_DEVICE_ID_VIA_83_87XX_1	0xB198
+
+#define PCI_VENDOR_ID_SIEMENS           0x110A
+#define PCI_DEVICE_ID_SIEMENS_DSCC4     0x2102
+
+#define PCI_VENDOR_ID_SMC2		0x1113
+#define PCI_DEVICE_ID_SMC2_1211TX	0x1211
+
+#define PCI_VENDOR_ID_VORTEX		0x1119
+#define PCI_DEVICE_ID_VORTEX_GDT60x0	0x0000
+#define PCI_DEVICE_ID_VORTEX_GDT6000B	0x0001
+#define PCI_DEVICE_ID_VORTEX_GDT6x10	0x0002
+#define PCI_DEVICE_ID_VORTEX_GDT6x20	0x0003
+#define PCI_DEVICE_ID_VORTEX_GDT6530	0x0004
+#define PCI_DEVICE_ID_VORTEX_GDT6550	0x0005
+#define PCI_DEVICE_ID_VORTEX_GDT6x17	0x0006
+#define PCI_DEVICE_ID_VORTEX_GDT6x27	0x0007
+#define PCI_DEVICE_ID_VORTEX_GDT6537	0x0008
+#define PCI_DEVICE_ID_VORTEX_GDT6557	0x0009
+#define PCI_DEVICE_ID_VORTEX_GDT6x15	0x000a
+#define PCI_DEVICE_ID_VORTEX_GDT6x25	0x000b
+#define PCI_DEVICE_ID_VORTEX_GDT6535	0x000c
+#define PCI_DEVICE_ID_VORTEX_GDT6555	0x000d
+#define PCI_DEVICE_ID_VORTEX_GDT6x17RP	0x0100
+#define PCI_DEVICE_ID_VORTEX_GDT6x27RP	0x0101
+#define PCI_DEVICE_ID_VORTEX_GDT6537RP	0x0102
+#define PCI_DEVICE_ID_VORTEX_GDT6557RP	0x0103
+#define PCI_DEVICE_ID_VORTEX_GDT6x11RP	0x0104
+#define PCI_DEVICE_ID_VORTEX_GDT6x21RP	0x0105
+#define PCI_DEVICE_ID_VORTEX_GDT6x17RP1	0x0110
+#define PCI_DEVICE_ID_VORTEX_GDT6x27RP1	0x0111
+#define PCI_DEVICE_ID_VORTEX_GDT6537RP1	0x0112
+#define PCI_DEVICE_ID_VORTEX_GDT6557RP1	0x0113
+#define PCI_DEVICE_ID_VORTEX_GDT6x11RP1	0x0114
+#define PCI_DEVICE_ID_VORTEX_GDT6x21RP1	0x0115
+#define PCI_DEVICE_ID_VORTEX_GDT6x17RP2	0x0120
+#define PCI_DEVICE_ID_VORTEX_GDT6x27RP2	0x0121
+#define PCI_DEVICE_ID_VORTEX_GDT6537RP2	0x0122
+#define PCI_DEVICE_ID_VORTEX_GDT6557RP2	0x0123
+#define PCI_DEVICE_ID_VORTEX_GDT6x11RP2	0x0124
+#define PCI_DEVICE_ID_VORTEX_GDT6x21RP2	0x0125
+
+#define PCI_VENDOR_ID_EF		0x111a
+#define PCI_DEVICE_ID_EF_ATM_FPGA	0x0000
+#define PCI_DEVICE_ID_EF_ATM_ASIC	0x0002
+#define PCI_VENDOR_ID_EF_ATM_LANAI2	0x0003
+#define PCI_VENDOR_ID_EF_ATM_LANAIHB	0x0005
+
+#define PCI_VENDOR_ID_IDT		0x111d
+#define PCI_DEVICE_ID_IDT_IDT77201	0x0001
+
+#define PCI_VENDOR_ID_FORE		0x1127
+#define PCI_DEVICE_ID_FORE_PCA200PC	0x0210
+#define PCI_DEVICE_ID_FORE_PCA200E	0x0300
+
+#define PCI_VENDOR_ID_IMAGINGTECH	0x112f
+#define PCI_DEVICE_ID_IMAGINGTECH_ICPCI	0x0000
+
+#define PCI_VENDOR_ID_PHILIPS		0x1131
+#define PCI_DEVICE_ID_PHILIPS_SAA7145	0x7145
+#define PCI_DEVICE_ID_PHILIPS_SAA7146	0x7146
+#define PCI_DEVICE_ID_PHILIPS_SAA9730	0x9730
+
+#define PCI_VENDOR_ID_EICON		0x1133
+#define PCI_DEVICE_ID_EICON_DIVA20PRO	0xe001
+#define PCI_DEVICE_ID_EICON_DIVA20	0xe002
+#define PCI_DEVICE_ID_EICON_DIVA20PRO_U	0xe003
+#define PCI_DEVICE_ID_EICON_DIVA20_U	0xe004
+#define PCI_DEVICE_ID_EICON_DIVA201	0xe005
+#define PCI_DEVICE_ID_EICON_DIVA202	0xe00b
+#define PCI_DEVICE_ID_EICON_MAESTRA	0xe010
+#define PCI_DEVICE_ID_EICON_MAESTRAQ	0xe012
+#define PCI_DEVICE_ID_EICON_MAESTRAQ_U	0xe013
+#define PCI_DEVICE_ID_EICON_MAESTRAP	0xe014
+
+#define PCI_VENDOR_ID_ZIATECH		0x1138
+#define PCI_DEVICE_ID_ZIATECH_5550_HC	0x5550
+ 
+#define PCI_VENDOR_ID_CYCLONE		0x113c
+#define PCI_DEVICE_ID_CYCLONE_SDK	0x0001
+
+#define PCI_VENDOR_ID_ALLIANCE		0x1142
+#define PCI_DEVICE_ID_ALLIANCE_PROMOTIO	0x3210
+#define PCI_DEVICE_ID_ALLIANCE_PROVIDEO	0x6422
+#define PCI_DEVICE_ID_ALLIANCE_AT24	0x6424
+#define PCI_DEVICE_ID_ALLIANCE_AT3D	0x643d
+
+#define PCI_VENDOR_ID_SYSKONNECT	0x1148
+#define PCI_DEVICE_ID_SYSKONNECT_FP	0x4000
+#define PCI_DEVICE_ID_SYSKONNECT_TR	0x4200
+#define PCI_DEVICE_ID_SYSKONNECT_GE	0x4300
+#define PCI_DEVICE_ID_SYSKONNECT_YU	0x4320
+#define PCI_DEVICE_ID_SYSKONNECT_9DXX	0x4400
+#define PCI_DEVICE_ID_SYSKONNECT_9MXX	0x4500
+
+#define PCI_VENDOR_ID_VMIC		0x114a
+#define PCI_DEVICE_ID_VMIC_VME		0x7587
+
+#define PCI_VENDOR_ID_DIGI		0x114f
+#define PCI_DEVICE_ID_DIGI_EPC		0x0002
+#define PCI_DEVICE_ID_DIGI_RIGHTSWITCH	0x0003
+#define PCI_DEVICE_ID_DIGI_XEM		0x0004
+#define PCI_DEVICE_ID_DIGI_XR		0x0005
+#define PCI_DEVICE_ID_DIGI_CX		0x0006
+#define PCI_DEVICE_ID_DIGI_XRJ		0x0009
+#define PCI_DEVICE_ID_DIGI_EPCJ		0x000a
+#define PCI_DEVICE_ID_DIGI_XR_920	0x0027
+#define PCI_DEVICE_ID_DIGI_DF_M_IOM2_E	0x0070
+#define PCI_DEVICE_ID_DIGI_DF_M_E	0x0071
+#define PCI_DEVICE_ID_DIGI_DF_M_IOM2_A	0x0072
+#define PCI_DEVICE_ID_DIGI_DF_M_A	0x0073
+#define PCI_DEVICE_ID_NEO_2DB9          0x00C8
+#define PCI_DEVICE_ID_NEO_2DB9PRI       0x00C9
+#define PCI_DEVICE_ID_NEO_2RJ45         0x00CA
+#define PCI_DEVICE_ID_NEO_2RJ45PRI      0x00CB
+
+#define PCI_VENDOR_ID_MUTECH		0x1159
+#define PCI_DEVICE_ID_MUTECH_MV1000	0x0001
+
+#define PCI_VENDOR_ID_XIRCOM		0x115d
+#define PCI_DEVICE_ID_XIRCOM_X3201_ETH	0x0003
+#define PCI_DEVICE_ID_XIRCOM_RBM56G	0x0101
+#define PCI_DEVICE_ID_XIRCOM_X3201_MDM	0x0103
+
+#define PCI_VENDOR_ID_RENDITION		0x1163
+#define PCI_DEVICE_ID_RENDITION_VERITE	0x0001
+#define PCI_DEVICE_ID_RENDITION_VERITE2100 0x2000
+
+#define PCI_VENDOR_ID_SERVERWORKS	  0x1166
+#define PCI_DEVICE_ID_SERVERWORKS_HE	  0x0008
+#define PCI_DEVICE_ID_SERVERWORKS_LE	  0x0009
+#define PCI_DEVICE_ID_SERVERWORKS_CIOB30  0x0010
+#define PCI_DEVICE_ID_SERVERWORKS_CMIC_HE 0x0011
+#define PCI_DEVICE_ID_SERVERWORKS_GCNB_LE 0x0017
+#define PCI_DEVICE_ID_SERVERWORKS_OSB4	  0x0200
+#define PCI_DEVICE_ID_SERVERWORKS_CSB5	  0x0201
+#define PCI_DEVICE_ID_SERVERWORKS_CSB6    0x0203
+#define PCI_DEVICE_ID_SERVERWORKS_OSB4IDE 0x0211
+#define PCI_DEVICE_ID_SERVERWORKS_CSB5IDE 0x0212
+#define PCI_DEVICE_ID_SERVERWORKS_CSB6IDE 0x0213
+#define PCI_DEVICE_ID_SERVERWORKS_CSB6IDE2 0x0217
+#define PCI_DEVICE_ID_SERVERWORKS_OSB4USB 0x0220
+#define PCI_DEVICE_ID_SERVERWORKS_CSB5USB PCI_DEVICE_ID_SERVERWORKS_OSB4USB
+#define PCI_DEVICE_ID_SERVERWORKS_CSB6USB 0x0221
+#define PCI_DEVICE_ID_SERVERWORKS_GCLE    0x0225
+#define PCI_DEVICE_ID_SERVERWORKS_GCLE2   0x0227
+#define PCI_DEVICE_ID_SERVERWORKS_CSB5ISA 0x0230
+
+#define PCI_VENDOR_ID_SBE		0x1176
+#define PCI_DEVICE_ID_SBE_WANXL100	0x0301
+#define PCI_DEVICE_ID_SBE_WANXL200	0x0302
+#define PCI_DEVICE_ID_SBE_WANXL400	0x0104
+
+#define PCI_VENDOR_ID_TOSHIBA		0x1179
+#define PCI_DEVICE_ID_TOSHIBA_PICCOLO	0x0102
+#define PCI_DEVICE_ID_TOSHIBA_PICCOLO_1	0x0103
+#define PCI_DEVICE_ID_TOSHIBA_PICCOLO_2	0x0105
+#define PCI_DEVICE_ID_TOSHIBA_601	0x0601
+#define PCI_DEVICE_ID_TOSHIBA_TOPIC95	0x060a
+#define PCI_DEVICE_ID_TOSHIBA_TOPIC95_A 0x0603
+#define PCI_DEVICE_ID_TOSHIBA_TOPIC95_B 0x060a
+#define PCI_DEVICE_ID_TOSHIBA_TOPIC97	0x060f
+#define PCI_DEVICE_ID_TOSHIBA_TOPIC100	0x0617
+
+#define PCI_VENDOR_ID_TOSHIBA_2		0x102f
+#define PCI_DEVICE_ID_TOSHIBA_TX3927	0x000a
+#define PCI_DEVICE_ID_TOSHIBA_TC35815CF	0x0030
+#define PCI_DEVICE_ID_TOSHIBA_TX4927	0x0180
+#define PCI_DEVICE_ID_TOSHIBA_TC86C001_MISC	0x0108
+
+#define PCI_VENDOR_ID_RICOH		0x1180
+#define PCI_DEVICE_ID_RICOH_RL5C465	0x0465
+#define PCI_DEVICE_ID_RICOH_RL5C466	0x0466
+#define PCI_DEVICE_ID_RICOH_RL5C475	0x0475
+#define PCI_DEVICE_ID_RICOH_RL5C476	0x0476
+#define PCI_DEVICE_ID_RICOH_RL5C478	0x0478
+
+#define PCI_VENDOR_ID_DLINK		0x1186
+#define PCI_DEVICE_ID_DLINK_DGE510T	0x4c00
+
+#define PCI_VENDOR_ID_ARTOP		0x1191
+#define PCI_DEVICE_ID_ARTOP_ATP8400	0x0004
+#define PCI_DEVICE_ID_ARTOP_ATP850UF	0x0005
+#define PCI_DEVICE_ID_ARTOP_ATP860	0x0006
+#define PCI_DEVICE_ID_ARTOP_ATP860R	0x0007
+#define PCI_DEVICE_ID_ARTOP_ATP865	0x0008
+#define PCI_DEVICE_ID_ARTOP_ATP865R	0x0009
+#define PCI_DEVICE_ID_ARTOP_AEC7610	0x8002
+#define PCI_DEVICE_ID_ARTOP_AEC7612UW	0x8010
+#define PCI_DEVICE_ID_ARTOP_AEC7612U	0x8020
+#define PCI_DEVICE_ID_ARTOP_AEC7612S	0x8030
+#define PCI_DEVICE_ID_ARTOP_AEC7612D	0x8040
+#define PCI_DEVICE_ID_ARTOP_AEC7612SUW	0x8050
+#define PCI_DEVICE_ID_ARTOP_8060	0x8060
+#define PCI_DEVICE_ID_ARTOP_AEC67160	0x8080
+#define PCI_DEVICE_ID_ARTOP_AEC67160_2	0x8081
+#define PCI_DEVICE_ID_ARTOP_AEC67162	0x808a
+
+#define PCI_VENDOR_ID_ZEITNET		0x1193
+#define PCI_DEVICE_ID_ZEITNET_1221	0x0001
+#define PCI_DEVICE_ID_ZEITNET_1225	0x0002
+
+#define PCI_VENDOR_ID_OMEGA		0x119b
+#define PCI_DEVICE_ID_OMEGA_82C092G	0x1221
+
+#define PCI_VENDOR_ID_FUJITSU_ME	0x119e
+#define PCI_DEVICE_ID_FUJITSU_FS155	0x0001
+#define PCI_DEVICE_ID_FUJITSU_FS50	0x0003
+
+#define PCI_SUBVENDOR_ID_KEYSPAN	0x11a9
+#define PCI_SUBDEVICE_ID_KEYSPAN_SX2	0x5334
+
+#define PCI_VENDOR_ID_MARVELL		0x11ab
+#define PCI_DEVICE_ID_MARVELL_GT64011	0x4146
+#define PCI_DEVICE_ID_MARVELL_GT64111	0x4146
+#define PCI_DEVICE_ID_MARVELL_GT64260	0x6430
+#define PCI_DEVICE_ID_MARVELL_MV64360	0x6460
+#define PCI_DEVICE_ID_MARVELL_MV64460	0x6480
+#define PCI_DEVICE_ID_MARVELL_GT96100	0x9652
+#define PCI_DEVICE_ID_MARVELL_GT96100A	0x9653
+
+#define PCI_VENDOR_ID_LITEON		0x11ad
+#define PCI_DEVICE_ID_LITEON_LNE100TX	0x0002
+
+#define PCI_VENDOR_ID_V3		0x11b0
+#define PCI_DEVICE_ID_V3_V960		0x0001
+#define PCI_DEVICE_ID_V3_V350		0x0001
+#define PCI_DEVICE_ID_V3_V961		0x0002
+#define PCI_DEVICE_ID_V3_V351		0x0002
+
+#define PCI_VENDOR_ID_NP		0x11bc
+#define PCI_DEVICE_ID_NP_PCI_FDDI	0x0001
+
+#define PCI_VENDOR_ID_ATT		0x11c1
+#define PCI_DEVICE_ID_ATT_L56XMF	0x0440
+#define PCI_DEVICE_ID_ATT_VENUS_MODEM	0x480
+
+#define PCI_VENDOR_ID_NEC2		0x11c3 /* NEC (2nd) */
+
+#define PCI_VENDOR_ID_SPECIALIX		0x11cb
+#define PCI_DEVICE_ID_SPECIALIX_IO8	0x2000
+#define PCI_DEVICE_ID_SPECIALIX_XIO	0x4000
+#define PCI_DEVICE_ID_SPECIALIX_RIO	0x8000
+#define PCI_SUBDEVICE_ID_SPECIALIX_SPEED4 0xa004
+
+#define PCI_VENDOR_ID_AURAVISION	0x11d1
+#define PCI_DEVICE_ID_AURAVISION_VXP524	0x01f7
+
+#define PCI_VENDOR_ID_ANALOG_DEVICES	0x11d4
+#define PCI_DEVICE_ID_AD1889JS		0x1889
+
+#define PCI_VENDOR_ID_IKON		0x11d5
+#define PCI_DEVICE_ID_IKON_10115	0x0115
+#define PCI_DEVICE_ID_IKON_10117	0x0117
+
+#define PCI_VENDOR_ID_SEGA		0x11db
+#define PCI_DEVICE_ID_SEGA_BBA		0x1234
+
+#define PCI_VENDOR_ID_ZORAN		0x11de
+#define PCI_DEVICE_ID_ZORAN_36057	0x6057
+#define PCI_DEVICE_ID_ZORAN_36120	0x6120
+
+#define PCI_VENDOR_ID_KINETIC		0x11f4
+#define PCI_DEVICE_ID_KINETIC_2915	0x2915
+
+#define PCI_VENDOR_ID_COMPEX		0x11f6
+#define PCI_DEVICE_ID_COMPEX_ENET100VG4	0x0112
+#define PCI_DEVICE_ID_COMPEX_RL2000	0x1401
+
+#define PCI_VENDOR_ID_RP		0x11fe
+#define PCI_DEVICE_ID_RP32INTF		0x0001
+#define PCI_DEVICE_ID_RP8INTF		0x0002
+#define PCI_DEVICE_ID_RP16INTF		0x0003
+#define PCI_DEVICE_ID_RP4QUAD		0x0004
+#define PCI_DEVICE_ID_RP8OCTA		0x0005
+#define PCI_DEVICE_ID_RP8J		0x0006
+#define PCI_DEVICE_ID_RP4J		0x0007
+#define PCI_DEVICE_ID_RP8SNI		0x0008	
+#define PCI_DEVICE_ID_RP16SNI		0x0009	
+#define PCI_DEVICE_ID_RPP4		0x000A
+#define PCI_DEVICE_ID_RPP8		0x000B
+#define PCI_DEVICE_ID_RP8M		0x000C
+#define PCI_DEVICE_ID_RP4M		0x000D
+#define PCI_DEVICE_ID_RP2_232		0x000E
+#define PCI_DEVICE_ID_RP2_422		0x000F
+#define PCI_DEVICE_ID_URP32INTF		0x0801
+#define PCI_DEVICE_ID_URP8INTF		0x0802
+#define PCI_DEVICE_ID_URP16INTF		0x0803
+#define PCI_DEVICE_ID_URP8OCTA		0x0805
+#define PCI_DEVICE_ID_UPCI_RM3_8PORT	0x080C       
+#define PCI_DEVICE_ID_UPCI_RM3_4PORT	0x080D
+#define PCI_DEVICE_ID_CRP16INTF		0x0903       
+
+#define PCI_VENDOR_ID_CYCLADES		0x120e
+#define PCI_DEVICE_ID_CYCLOM_Y_Lo	0x0100
+#define PCI_DEVICE_ID_CYCLOM_Y_Hi	0x0101
+#define PCI_DEVICE_ID_CYCLOM_4Y_Lo	0x0102
+#define PCI_DEVICE_ID_CYCLOM_4Y_Hi	0x0103
+#define PCI_DEVICE_ID_CYCLOM_8Y_Lo	0x0104
+#define PCI_DEVICE_ID_CYCLOM_8Y_Hi	0x0105
+#define PCI_DEVICE_ID_CYCLOM_Z_Lo	0x0200
+#define PCI_DEVICE_ID_CYCLOM_Z_Hi	0x0201
+#define PCI_DEVICE_ID_PC300_RX_2	0x0300
+#define PCI_DEVICE_ID_PC300_RX_1	0x0301
+#define PCI_DEVICE_ID_PC300_TE_2	0x0310
+#define PCI_DEVICE_ID_PC300_TE_1	0x0311
+#define PCI_DEVICE_ID_PC300_TE_M_2	0x0320
+#define PCI_DEVICE_ID_PC300_TE_M_1	0x0321
+
+/* Allied Telesyn */
+#define PCI_VENDOR_ID_AT    		0x1259
+#define PCI_SUBDEVICE_ID_AT_2701FX	0x2703
+
+#define PCI_VENDOR_ID_ESSENTIAL		0x120f
+#define PCI_DEVICE_ID_ESSENTIAL_ROADRUNNER	0x0001
+
+#define PCI_VENDOR_ID_O2		0x1217
+#define PCI_DEVICE_ID_O2_6729		0x6729
+#define PCI_DEVICE_ID_O2_6730		0x673a
+#define PCI_DEVICE_ID_O2_6832		0x6832
+#define PCI_DEVICE_ID_O2_6836		0x6836
+
+#define PCI_VENDOR_ID_3DFX		0x121a
+#define PCI_DEVICE_ID_3DFX_VOODOO	0x0001
+#define PCI_DEVICE_ID_3DFX_VOODOO2	0x0002
+#define PCI_DEVICE_ID_3DFX_BANSHEE	0x0003
+#define PCI_DEVICE_ID_3DFX_VOODOO3	0x0005
+#define PCI_DEVICE_ID_3DFX_VOODOO5	0x0009
+
+#define PCI_VENDOR_ID_SIGMADES		0x1236
+#define PCI_DEVICE_ID_SIGMADES_6425	0x6401
+
+#define PCI_VENDOR_ID_CCUBE		0x123f
+
+#define PCI_VENDOR_ID_AVM		0x1244
+#define PCI_DEVICE_ID_AVM_B1		0x0700
+#define PCI_DEVICE_ID_AVM_C4		0x0800
+#define PCI_DEVICE_ID_AVM_A1		0x0a00
+#define PCI_DEVICE_ID_AVM_A1_V2		0x0e00
+#define PCI_DEVICE_ID_AVM_C2		0x1100
+#define PCI_DEVICE_ID_AVM_T1		0x1200
+
+#define PCI_VENDOR_ID_DIPIX		0x1246
+
+#define PCI_VENDOR_ID_STALLION		0x124d
+#define PCI_DEVICE_ID_STALLION_ECHPCI832 0x0000
+#define PCI_DEVICE_ID_STALLION_ECHPCI864 0x0002
+#define PCI_DEVICE_ID_STALLION_EIOPCI	0x0003
+
+#define PCI_VENDOR_ID_OPTIBASE		0x1255
+#define PCI_DEVICE_ID_OPTIBASE_FORGE	0x1110
+#define PCI_DEVICE_ID_OPTIBASE_FUSION	0x1210
+#define PCI_DEVICE_ID_OPTIBASE_VPLEX	0x2110
+#define PCI_DEVICE_ID_OPTIBASE_VPLEXCC	0x2120
+#define PCI_DEVICE_ID_OPTIBASE_VQUEST	0x2130
+
+/* Allied Telesyn */
+#define PCI_VENDOR_ID_AT    		0x1259
+#define PCI_SUBDEVICE_ID_AT_2700FX	0x2701
+#define PCI_SUBDEVICE_ID_AT_2701FX	0x2703
+
+#define PCI_VENDOR_ID_ESS		0x125d
+#define PCI_DEVICE_ID_ESS_ESS1968	0x1968
+#define PCI_DEVICE_ID_ESS_AUDIOPCI	0x1969
+#define PCI_DEVICE_ID_ESS_ESS1978	0x1978
+
+#define PCI_VENDOR_ID_SATSAGEM		0x1267
+#define PCI_DEVICE_ID_SATSAGEM_NICCY	0x1016
+#define PCI_DEVICE_ID_SATSAGEM_PCR2101	0x5352
+#define PCI_DEVICE_ID_SATSAGEM_TELSATTURBO 0x5a4b
+
+#define PCI_VENDOR_ID_HUGHES		0x1273
+#define PCI_DEVICE_ID_HUGHES_DIRECPC	0x0002
+
+#define PCI_VENDOR_ID_ENSONIQ		0x1274
+#define PCI_DEVICE_ID_ENSONIQ_CT5880	0x5880
+#define PCI_DEVICE_ID_ENSONIQ_ES1370	0x5000
+#define PCI_DEVICE_ID_ENSONIQ_ES1371	0x1371
+
+#define PCI_VENDOR_ID_TRANSMETA		0x1279
+#define PCI_DEVICE_ID_EFFICEON		0x0060
+
+#define PCI_VENDOR_ID_ROCKWELL		0x127A
+
+#define PCI_VENDOR_ID_ITE		0x1283
+#define PCI_DEVICE_ID_ITE_IT8172G	0x8172
+#define PCI_DEVICE_ID_ITE_IT8172G_AUDIO 0x0801
+#define PCI_DEVICE_ID_ITE_8872		0x8872
+#define PCI_DEVICE_ID_ITE_IT8330G_0	0xe886
+
+/* formerly Platform Tech */
+#define PCI_VENDOR_ID_ESS_OLD		0x1285
+#define PCI_DEVICE_ID_ESS_ESS0100	0x0100
+
+#define PCI_VENDOR_ID_ALTEON		0x12ae
+#define PCI_DEVICE_ID_ALTEON_ACENIC	0x0001
+
+#define PCI_VENDOR_ID_USR		0x12B9
+
+#define PCI_SUBVENDOR_ID_CONNECT_TECH			0x12c4
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232		0x0001
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232		0x0002
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232		0x0003
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485		0x0004
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4	0x0005
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485		0x0006
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2	0x0007
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485		0x0008
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6	0x0009
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1	0x000A
+#define PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1	0x000B
+
+#define PCI_VENDOR_ID_PICTUREL		0x12c5
+#define PCI_DEVICE_ID_PICTUREL_PCIVST	0x0081
+
+#define PCI_VENDOR_ID_NVIDIA_SGS	0x12d2
+#define PCI_DEVICE_ID_NVIDIA_SGS_RIVA128 0x0018
+
+#define PCI_SUBVENDOR_ID_CHASE_PCIFAST		0x12E0
+#define PCI_SUBDEVICE_ID_CHASE_PCIFAST4		0x0031
+#define PCI_SUBDEVICE_ID_CHASE_PCIFAST8		0x0021
+#define PCI_SUBDEVICE_ID_CHASE_PCIFAST16	0x0011
+#define PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC	0x0041
+#define PCI_SUBVENDOR_ID_CHASE_PCIRAS		0x124D
+#define PCI_SUBDEVICE_ID_CHASE_PCIRAS4		0xF001
+#define PCI_SUBDEVICE_ID_CHASE_PCIRAS8		0xF010
+
+#define PCI_VENDOR_ID_AUREAL		0x12eb
+#define PCI_DEVICE_ID_AUREAL_VORTEX_1	0x0001
+#define PCI_DEVICE_ID_AUREAL_VORTEX_2	0x0002
+#define PCI_DEVICE_ID_AUREAL_ADVANTAGE	0x0003
+
+#define PCI_VENDOR_ID_ELECTRONICDESIGNGMBH 0x12f8
+#define PCI_DEVICE_ID_LML_33R10		0x8a02
+
+#define PCI_VENDOR_ID_CBOARDS		0x1307
+#define PCI_DEVICE_ID_CBOARDS_DAS1602_16 0x0001
+
+#define PCI_VENDOR_ID_SIIG		0x131f
+#define PCI_DEVICE_ID_SIIG_1S_10x_550	0x1000
+#define PCI_DEVICE_ID_SIIG_1S_10x_650	0x1001
+#define PCI_DEVICE_ID_SIIG_1S_10x_850	0x1002
+#define PCI_DEVICE_ID_SIIG_1S1P_10x_550	0x1010
+#define PCI_DEVICE_ID_SIIG_1S1P_10x_650	0x1011
+#define PCI_DEVICE_ID_SIIG_1S1P_10x_850	0x1012
+#define PCI_DEVICE_ID_SIIG_1P_10x	0x1020
+#define PCI_DEVICE_ID_SIIG_2P_10x	0x1021
+#define PCI_DEVICE_ID_SIIG_2S_10x_550	0x1030
+#define PCI_DEVICE_ID_SIIG_2S_10x_650	0x1031
+#define PCI_DEVICE_ID_SIIG_2S_10x_850	0x1032
+#define PCI_DEVICE_ID_SIIG_2S1P_10x_550	0x1034
+#define PCI_DEVICE_ID_SIIG_2S1P_10x_650	0x1035
+#define PCI_DEVICE_ID_SIIG_2S1P_10x_850	0x1036
+#define PCI_DEVICE_ID_SIIG_4S_10x_550	0x1050
+#define PCI_DEVICE_ID_SIIG_4S_10x_650	0x1051
+#define PCI_DEVICE_ID_SIIG_4S_10x_850	0x1052
+#define PCI_DEVICE_ID_SIIG_1S_20x_550	0x2000
+#define PCI_DEVICE_ID_SIIG_1S_20x_650	0x2001
+#define PCI_DEVICE_ID_SIIG_1S_20x_850	0x2002
+#define PCI_DEVICE_ID_SIIG_1P_20x	0x2020
+#define PCI_DEVICE_ID_SIIG_2P_20x	0x2021
+#define PCI_DEVICE_ID_SIIG_2S_20x_550	0x2030
+#define PCI_DEVICE_ID_SIIG_2S_20x_650	0x2031
+#define PCI_DEVICE_ID_SIIG_2S_20x_850	0x2032
+#define PCI_DEVICE_ID_SIIG_2P1S_20x_550	0x2040
+#define PCI_DEVICE_ID_SIIG_2P1S_20x_650	0x2041
+#define PCI_DEVICE_ID_SIIG_2P1S_20x_850	0x2042
+#define PCI_DEVICE_ID_SIIG_1S1P_20x_550	0x2010
+#define PCI_DEVICE_ID_SIIG_1S1P_20x_650	0x2011
+#define PCI_DEVICE_ID_SIIG_1S1P_20x_850	0x2012
+#define PCI_DEVICE_ID_SIIG_4S_20x_550	0x2050
+#define PCI_DEVICE_ID_SIIG_4S_20x_650	0x2051
+#define PCI_DEVICE_ID_SIIG_4S_20x_850	0x2052
+#define PCI_DEVICE_ID_SIIG_2S1P_20x_550	0x2060
+#define PCI_DEVICE_ID_SIIG_2S1P_20x_650	0x2061
+#define PCI_DEVICE_ID_SIIG_2S1P_20x_850	0x2062
+
+#define PCI_VENDOR_ID_RADISYS		0x1331
+#define PCI_DEVICE_ID_RADISYS_ENP2611	0x0030
+
+#define PCI_VENDOR_ID_DOMEX		0x134a
+#define PCI_DEVICE_ID_DOMEX_DMX3191D	0x0001
+
+#define PCI_VENDOR_ID_QUATECH		0x135C
+#define PCI_DEVICE_ID_QUATECH_QSC100	0x0010
+#define PCI_DEVICE_ID_QUATECH_DSC100	0x0020
+#define PCI_DEVICE_ID_QUATECH_DSC200	0x0030
+#define PCI_DEVICE_ID_QUATECH_QSC200	0x0040
+#define PCI_DEVICE_ID_QUATECH_ESC100D	0x0050
+#define PCI_DEVICE_ID_QUATECH_ESC100M	0x0060
+
+#define PCI_VENDOR_ID_SEALEVEL		0x135e
+#define PCI_DEVICE_ID_SEALEVEL_U530	0x7101
+#define PCI_DEVICE_ID_SEALEVEL_UCOMM2	0x7201
+#define PCI_DEVICE_ID_SEALEVEL_UCOMM422	0x7402
+#define PCI_DEVICE_ID_SEALEVEL_UCOMM232	0x7202
+#define PCI_DEVICE_ID_SEALEVEL_COMM4	0x7401
+#define PCI_DEVICE_ID_SEALEVEL_COMM8	0x7801
+#define PCI_DEVICE_ID_SEALEVEL_UCOMM8	0x7804
+
+#define PCI_VENDOR_ID_HYPERCOPE		0x1365
+#define PCI_DEVICE_ID_HYPERCOPE_PLX	0x9050
+#define PCI_SUBDEVICE_ID_HYPERCOPE_OLD_ERGO	0x0104
+#define PCI_SUBDEVICE_ID_HYPERCOPE_ERGO		0x0106
+#define PCI_SUBDEVICE_ID_HYPERCOPE_METRO	0x0107
+#define PCI_SUBDEVICE_ID_HYPERCOPE_CHAMP2	0x0108
+#define PCI_SUBDEVICE_ID_HYPERCOPE_PLEXUS	0x0109
+
+#define PCI_VENDOR_ID_KAWASAKI		0x136b
+#define PCI_DEVICE_ID_MCHIP_KL5A72002	0xff01
+
+#define PCI_VENDOR_ID_CNET		0x1371
+#define PCI_DEVICE_ID_CNET_GIGACARD	0x434e
+
+#define PCI_VENDOR_ID_LMC		0x1376
+#define PCI_DEVICE_ID_LMC_HSSI		0x0003
+#define PCI_DEVICE_ID_LMC_DS3		0x0004
+#define PCI_DEVICE_ID_LMC_SSI		0x0005
+#define PCI_DEVICE_ID_LMC_T1		0x0006
+
+#define PCI_VENDOR_ID_NETGEAR		0x1385
+#define PCI_DEVICE_ID_NETGEAR_GA620	0x620a
+#define PCI_DEVICE_ID_NETGEAR_GA622	0x622a
+
+#define PCI_VENDOR_ID_APPLICOM		0x1389
+#define PCI_DEVICE_ID_APPLICOM_PCIGENERIC 0x0001
+#define PCI_DEVICE_ID_APPLICOM_PCI2000IBS_CAN 0x0002
+#define PCI_DEVICE_ID_APPLICOM_PCI2000PFB 0x0003
+
+#define PCI_VENDOR_ID_MOXA		0x1393
+#define PCI_DEVICE_ID_MOXA_RC7000	0x0001
+#define PCI_DEVICE_ID_MOXA_CP102	0x1020
+#define PCI_DEVICE_ID_MOXA_CP102UL	0x1021
+#define PCI_DEVICE_ID_MOXA_CP102U	0x1022
+#define PCI_DEVICE_ID_MOXA_C104		0x1040
+#define PCI_DEVICE_ID_MOXA_CP104U	0x1041
+#define PCI_DEVICE_ID_MOXA_CP104JU	0x1042
+#define PCI_DEVICE_ID_MOXA_CT114	0x1140
+#define PCI_DEVICE_ID_MOXA_CP114	0x1141
+#define PCI_DEVICE_ID_MOXA_CP118U	0x1180
+#define PCI_DEVICE_ID_MOXA_CP132	0x1320
+#define PCI_DEVICE_ID_MOXA_CP132U	0x1321
+#define PCI_DEVICE_ID_MOXA_CP134U	0x1340
+#define PCI_DEVICE_ID_MOXA_C168		0x1680
+#define PCI_DEVICE_ID_MOXA_CP168U	0x1681
+#define PCI_DEVICE_ID_MOXA_CP204J	0x2040
+#define PCI_DEVICE_ID_MOXA_C218		0x2180
+#define PCI_DEVICE_ID_MOXA_C320		0x3200
+
+#define PCI_VENDOR_ID_CCD		0x1397
+#define PCI_DEVICE_ID_CCD_2BD0		0x2bd0
+#define PCI_DEVICE_ID_CCD_B000		0xb000
+#define PCI_DEVICE_ID_CCD_B006		0xb006
+#define PCI_DEVICE_ID_CCD_B007		0xb007
+#define PCI_DEVICE_ID_CCD_B008		0xb008
+#define PCI_DEVICE_ID_CCD_B009		0xb009
+#define PCI_DEVICE_ID_CCD_B00A		0xb00a
+#define PCI_DEVICE_ID_CCD_B00B		0xb00b
+#define PCI_DEVICE_ID_CCD_B00C		0xb00c
+#define PCI_DEVICE_ID_CCD_B100		0xb100
+
+#define PCI_VENDOR_ID_EXAR		0x13a8
+#define PCI_DEVICE_ID_EXAR_XR17C152	0x0152
+#define PCI_DEVICE_ID_EXAR_XR17C154	0x0154
+#define PCI_DEVICE_ID_EXAR_XR17C158	0x0158
+
+#define PCI_VENDOR_ID_MICROGATE		0x13c0
+#define PCI_DEVICE_ID_MICROGATE_USC	0x0010
+#define PCI_DEVICE_ID_MICROGATE_SCC	0x0020
+#define PCI_DEVICE_ID_MICROGATE_SCA	0x0030
+#define PCI_DEVICE_ID_MICROGATE_USC2	0x0210
+
+#define PCI_VENDOR_ID_3WARE		0x13C1
+#define PCI_DEVICE_ID_3WARE_1000	0x1000
+#define PCI_DEVICE_ID_3WARE_7000	0x1001
+#define PCI_DEVICE_ID_3WARE_9000	0x1002
+
+#define PCI_VENDOR_ID_IOMEGA		0x13ca
+#define PCI_DEVICE_ID_IOMEGA_BUZ	0x4231
+
+#define PCI_VENDOR_ID_ABOCOM		0x13D1
+#define PCI_DEVICE_ID_ABOCOM_2BD1       0x2BD1
+
+#define PCI_VENDOR_ID_CMEDIA		0x13f6
+#define PCI_DEVICE_ID_CMEDIA_CM8338A	0x0100
+#define PCI_DEVICE_ID_CMEDIA_CM8338B	0x0101
+#define PCI_DEVICE_ID_CMEDIA_CM8738	0x0111
+#define PCI_DEVICE_ID_CMEDIA_CM8738B	0x0112
+
+#define PCI_VENDOR_ID_LAVA		0x1407
+#define PCI_DEVICE_ID_LAVA_DSERIAL	0x0100 /* 2x 16550 */
+#define PCI_DEVICE_ID_LAVA_QUATRO_A	0x0101 /* 2x 16550, half of 4 port */
+#define PCI_DEVICE_ID_LAVA_QUATRO_B	0x0102 /* 2x 16550, half of 4 port */
+#define PCI_DEVICE_ID_LAVA_OCTO_A	0x0180 /* 4x 16550A, half of 8 port */
+#define PCI_DEVICE_ID_LAVA_OCTO_B	0x0181 /* 4x 16550A, half of 8 port */
+#define PCI_DEVICE_ID_LAVA_PORT_PLUS	0x0200 /* 2x 16650 */
+#define PCI_DEVICE_ID_LAVA_QUAD_A	0x0201 /* 2x 16650, half of 4 port */
+#define PCI_DEVICE_ID_LAVA_QUAD_B	0x0202 /* 2x 16650, half of 4 port */
+#define PCI_DEVICE_ID_LAVA_SSERIAL	0x0500 /* 1x 16550 */
+#define PCI_DEVICE_ID_LAVA_PORT_650	0x0600 /* 1x 16650 */
+#define PCI_DEVICE_ID_LAVA_PARALLEL	0x8000
+#define PCI_DEVICE_ID_LAVA_DUAL_PAR_A	0x8002 /* The Lava Dual Parallel is */
+#define PCI_DEVICE_ID_LAVA_DUAL_PAR_B	0x8003 /* two PCI devices on a card */
+#define PCI_DEVICE_ID_LAVA_BOCA_IOPPAR	0x8800
+
+#define PCI_VENDOR_ID_TIMEDIA		0x1409
+#define PCI_DEVICE_ID_TIMEDIA_1889	0x7168
+
+#define PCI_VENDOR_ID_OXSEMI		0x1415
+#define PCI_DEVICE_ID_OXSEMI_12PCI840	0x8403
+#define PCI_DEVICE_ID_OXSEMI_16PCI954	0x9501
+#define PCI_DEVICE_ID_OXSEMI_16PCI95N	0x9511
+#define PCI_DEVICE_ID_OXSEMI_16PCI954PP	0x9513
+#define PCI_DEVICE_ID_OXSEMI_16PCI952	0x9521
+
+#define PCI_VENDOR_ID_SAMSUNG		0x144d
+
+#define PCI_VENDOR_ID_AIRONET		0x14b9
+#define PCI_DEVICE_ID_AIRONET_4800_1	0x0001
+#define PCI_DEVICE_ID_AIRONET_4800	0x4500 // values switched?  see
+#define PCI_DEVICE_ID_AIRONET_4500	0x4800 // drivers/net/aironet4500_card.c
+
+#define PCI_VENDOR_ID_TITAN		0x14D2
+#define PCI_DEVICE_ID_TITAN_010L	0x8001
+#define PCI_DEVICE_ID_TITAN_100L	0x8010
+#define PCI_DEVICE_ID_TITAN_110L	0x8011
+#define PCI_DEVICE_ID_TITAN_200L	0x8020
+#define PCI_DEVICE_ID_TITAN_210L	0x8021
+#define PCI_DEVICE_ID_TITAN_400L	0x8040
+#define PCI_DEVICE_ID_TITAN_800L	0x8080
+#define PCI_DEVICE_ID_TITAN_100		0xA001
+#define PCI_DEVICE_ID_TITAN_200		0xA005
+#define PCI_DEVICE_ID_TITAN_400		0xA003
+#define PCI_DEVICE_ID_TITAN_800B	0xA004
+
+#define PCI_VENDOR_ID_PANACOM		0x14d4
+#define PCI_DEVICE_ID_PANACOM_QUADMODEM	0x0400
+#define PCI_DEVICE_ID_PANACOM_DUALMODEM	0x0402
+
+#define PCI_VENDOR_ID_SIPACKETS		0x14d9
+#define PCI_DEVICE_ID_SP_HT		0x0010
+
+#define PCI_VENDOR_ID_AFAVLAB		0x14db
+#define PCI_DEVICE_ID_AFAVLAB_P028	0x2180
+#define PCI_DEVICE_ID_AFAVLAB_P030	0x2182
+
+#define PCI_VENDOR_ID_BROADCOM		0x14e4
+#define PCI_DEVICE_ID_TIGON3_5752	0x1600
+#define PCI_DEVICE_ID_TIGON3_5752M	0x1601
+#define PCI_DEVICE_ID_TIGON3_5700	0x1644
+#define PCI_DEVICE_ID_TIGON3_5701	0x1645
+#define PCI_DEVICE_ID_TIGON3_5702	0x1646
+#define PCI_DEVICE_ID_TIGON3_5703	0x1647
+#define PCI_DEVICE_ID_TIGON3_5704	0x1648
+#define PCI_DEVICE_ID_TIGON3_5704S_2	0x1649
+#define PCI_DEVICE_ID_NX2_5706		0x164a
+#define PCI_DEVICE_ID_TIGON3_5702FE	0x164d
+#define PCI_DEVICE_ID_TIGON3_5705	0x1653
+#define PCI_DEVICE_ID_TIGON3_5705_2	0x1654
+#define PCI_DEVICE_ID_TIGON3_5720	0x1658
+#define PCI_DEVICE_ID_TIGON3_5721	0x1659
+#define PCI_DEVICE_ID_TIGON3_5705M	0x165d
+#define PCI_DEVICE_ID_TIGON3_5705M_2	0x165e
+#define PCI_DEVICE_ID_TIGON3_5705F	0x166e
+#define PCI_DEVICE_ID_TIGON3_5750	0x1676
+#define PCI_DEVICE_ID_TIGON3_5751	0x1677
+#define PCI_DEVICE_ID_TIGON3_5750M	0x167c
+#define PCI_DEVICE_ID_TIGON3_5751M	0x167d
+#define PCI_DEVICE_ID_TIGON3_5751F	0x167e
+#define PCI_DEVICE_ID_TIGON3_5782	0x1696
+#define PCI_DEVICE_ID_TIGON3_5788	0x169c
+#define PCI_DEVICE_ID_TIGON3_5789	0x169d
+#define PCI_DEVICE_ID_TIGON3_5702X	0x16a6
+#define PCI_DEVICE_ID_TIGON3_5703X	0x16a7
+#define PCI_DEVICE_ID_TIGON3_5704S	0x16a8
+#define PCI_DEVICE_ID_NX2_5706S		0x16aa
+#define PCI_DEVICE_ID_TIGON3_5702A3	0x16c6
+#define PCI_DEVICE_ID_TIGON3_5703A3	0x16c7
+#define PCI_DEVICE_ID_TIGON3_5781	0x16dd
+#define PCI_DEVICE_ID_TIGON3_5753	0x16f7
+#define PCI_DEVICE_ID_TIGON3_5753M	0x16fd
+#define PCI_DEVICE_ID_TIGON3_5753F	0x16fe
+#define PCI_DEVICE_ID_TIGON3_5901	0x170d
+#define PCI_DEVICE_ID_BCM4401B1		0x170c
+#define PCI_DEVICE_ID_TIGON3_5901_2	0x170e
+#define PCI_DEVICE_ID_BCM4401		0x4401
+#define PCI_DEVICE_ID_BCM4401B0		0x4402
+
+#define PCI_VENDOR_ID_TOPIC		0x151f
+#define PCI_DEVICE_ID_TOPIC_TP560	0x0000
+
+#define PCI_VENDOR_ID_ENE		0x1524
+#define PCI_DEVICE_ID_ENE_1211		0x1211
+#define PCI_DEVICE_ID_ENE_1225		0x1225
+#define PCI_DEVICE_ID_ENE_1410		0x1410
+#define PCI_DEVICE_ID_ENE_1420		0x1420
+
+#define PCI_VENDOR_ID_SYBA		0x1592
+#define PCI_DEVICE_ID_SYBA_2P_EPP	0x0782
+#define PCI_DEVICE_ID_SYBA_1P_ECP	0x0783
+
+#define PCI_VENDOR_ID_MORETON		0x15aa
+#define PCI_DEVICE_ID_RASTEL_2PORT	0x2000
+
+#define PCI_VENDOR_ID_ZOLTRIX		0x15b0
+#define PCI_DEVICE_ID_ZOLTRIX_2BD0	0x2bd0 
+
+#define PCI_VENDOR_ID_MELLANOX		0x15b3
+#define PCI_DEVICE_ID_MELLANOX_TAVOR	0x5a44
+#define PCI_DEVICE_ID_MELLANOX_ARBEL_COMPAT 0x6278
+#define PCI_DEVICE_ID_MELLANOX_ARBEL	0x6282
+#define PCI_DEVICE_ID_MELLANOX_SINAI_OLD 0x5e8c
+#define PCI_DEVICE_ID_MELLANOX_SINAI	0x6274
+
+#define PCI_VENDOR_ID_PDC		0x15e9
+#define PCI_DEVICE_ID_PDC_1841		0x1841
+
+#define PCI_VENDOR_ID_MACROLINK		0x15ed
+#define PCI_DEVICE_ID_MACROLINK_MCCS8	0x1000
+#define PCI_DEVICE_ID_MACROLINK_MCCS	0x1001
+#define PCI_DEVICE_ID_MACROLINK_MCCS8H	0x1002
+#define PCI_DEVICE_ID_MACROLINK_MCCSH	0x1003
+#define PCI_DEVICE_ID_MACROLINK_MCCR8	0x2000
+#define PCI_DEVICE_ID_MACROLINK_MCCR	0x2001
+
+#define PCI_VENDOR_ID_FARSITE           0x1619
+#define PCI_DEVICE_ID_FARSITE_T2P       0x0400
+#define PCI_DEVICE_ID_FARSITE_T4P       0x0440
+#define PCI_DEVICE_ID_FARSITE_T1U       0x0610
+#define PCI_DEVICE_ID_FARSITE_T2U       0x0620
+#define PCI_DEVICE_ID_FARSITE_T4U       0x0640
+#define PCI_DEVICE_ID_FARSITE_TE1       0x1610
+#define PCI_DEVICE_ID_FARSITE_TE1C      0x1612
+
+#define PCI_VENDOR_ID_SIBYTE		0x166d
+#define PCI_DEVICE_ID_BCM1250_HT	0x0002
+
+#define PCI_VENDOR_ID_LINKSYS		0x1737
+#define PCI_DEVICE_ID_LINKSYS_EG1032	0x1032
+#define PCI_DEVICE_ID_LINKSYS_EG1064	0x1064
+
+#define PCI_VENDOR_ID_ALTIMA		0x173b
+#define PCI_DEVICE_ID_ALTIMA_AC1000	0x03e8
+#define PCI_DEVICE_ID_ALTIMA_AC1001	0x03e9
+#define PCI_DEVICE_ID_ALTIMA_AC9100	0x03ea
+#define PCI_DEVICE_ID_ALTIMA_AC1003	0x03eb
+
+#define PCI_VENDOR_ID_S2IO		0x17d5
+#define	PCI_DEVICE_ID_S2IO_WIN		0x5731
+#define	PCI_DEVICE_ID_S2IO_UNI		0x5831
+#define PCI_DEVICE_ID_HERC_WIN		0x5732
+#define PCI_DEVICE_ID_HERC_UNI		0x5832
+
+#define PCI_VENDOR_ID_INFINICON		0x1820
+
+#define PCI_VENDOR_ID_TOPSPIN		0x1867
+
+#define PCI_VENDOR_ID_TDI               0x192E
+#define PCI_DEVICE_ID_TDI_EHCI          0x0101
+
+#define PCI_VENDOR_ID_SYMPHONY		0x1c1c
+#define PCI_DEVICE_ID_SYMPHONY_101	0x0001
+
+#define PCI_VENDOR_ID_TEKRAM		0x1de1
+#define PCI_DEVICE_ID_TEKRAM_DC290	0xdc29
+
+#define PCI_VENDOR_ID_HINT             0x3388
+#define PCI_DEVICE_ID_HINT_VXPROII_IDE 0x8013
+
+#define PCI_VENDOR_ID_3DLABS		0x3d3d
+#define PCI_DEVICE_ID_3DLABS_300SX	0x0001
+#define PCI_DEVICE_ID_3DLABS_500TX	0x0002
+#define PCI_DEVICE_ID_3DLABS_DELTA	0x0003
+#define PCI_DEVICE_ID_3DLABS_PERMEDIA	0x0004
+#define PCI_DEVICE_ID_3DLABS_MX		0x0006
+#define PCI_DEVICE_ID_3DLABS_PERMEDIA2	0x0007
+#define PCI_DEVICE_ID_3DLABS_GAMMA	0x0008
+#define PCI_DEVICE_ID_3DLABS_PERMEDIA2V	0x0009
+
+#define PCI_VENDOR_ID_AVANCE		0x4005
+#define PCI_DEVICE_ID_AVANCE_ALG2064	0x2064
+#define PCI_DEVICE_ID_AVANCE_2302	0x2302
+
+#define PCI_VENDOR_ID_AKS		0x416c
+#define PCI_DEVICE_ID_AKS_ALADDINCARD	0x0100
+#define PCI_DEVICE_ID_AKS_CPC		0x0200
+
+#define PCI_VENDOR_ID_REDCREEK		0x4916
+#define PCI_DEVICE_ID_RC45		0x1960
+
+#define PCI_VENDOR_ID_NETVIN		0x4a14
+#define PCI_DEVICE_ID_NETVIN_NV5000SC	0x5000
+
+#define PCI_VENDOR_ID_S3		0x5333
+#define PCI_DEVICE_ID_S3_PLATO_PXS	0x0551
+#define PCI_DEVICE_ID_S3_ViRGE		0x5631
+#define PCI_DEVICE_ID_S3_TRIO		0x8811
+#define PCI_DEVICE_ID_S3_AURORA64VP	0x8812
+#define PCI_DEVICE_ID_S3_TRIO64UVP	0x8814
+#define PCI_DEVICE_ID_S3_ViRGE_VX	0x883d
+#define PCI_DEVICE_ID_S3_868		0x8880
+#define PCI_DEVICE_ID_S3_928		0x88b0
+#define PCI_DEVICE_ID_S3_864_1		0x88c0
+#define PCI_DEVICE_ID_S3_864_2		0x88c1
+#define PCI_DEVICE_ID_S3_964_1		0x88d0
+#define PCI_DEVICE_ID_S3_964_2		0x88d1
+#define PCI_DEVICE_ID_S3_968		0x88f0
+#define PCI_DEVICE_ID_S3_TRIO64V2	0x8901
+#define PCI_DEVICE_ID_S3_PLATO_PXG	0x8902
+#define PCI_DEVICE_ID_S3_ViRGE_DXGX	0x8a01
+#define PCI_DEVICE_ID_S3_ViRGE_GX2	0x8a10
+#define PCI_DEVICE_ID_S3_SAVAGE4	0x8a25
+#define PCI_DEVICE_ID_S3_ViRGE_MX	0x8c01
+#define PCI_DEVICE_ID_S3_ViRGE_MXP	0x8c02
+#define PCI_DEVICE_ID_S3_ViRGE_MXPMV	0x8c03
+#define PCI_DEVICE_ID_S3_PROSAVAGE8	0x8d04
+#define PCI_DEVICE_ID_S3_SONICVIBES	0xca00
+
+#define PCI_VENDOR_ID_DUNORD		0x5544
+#define PCI_DEVICE_ID_DUNORD_I3000	0x0001
+
+#define PCI_VENDOR_ID_DCI		0x6666
+#define PCI_DEVICE_ID_DCI_PCCOM4	0x0001
+#define PCI_DEVICE_ID_DCI_PCCOM8	0x0002
+
+#define PCI_VENDOR_ID_DUNORD		0x5544
+#define PCI_DEVICE_ID_DUNORD_I3000	0x0001
+
+#define PCI_VENDOR_ID_GENROCO		0x5555
+#define PCI_DEVICE_ID_GENROCO_HFP832	0x0003
+
+#define PCI_VENDOR_ID_INTEL		0x8086
+#define PCI_DEVICE_ID_INTEL_EESSC	0x0008
+#define PCI_DEVICE_ID_INTEL_21145	0x0039
+#define PCI_DEVICE_ID_INTEL_82375	0x0482
+#define PCI_DEVICE_ID_INTEL_82424	0x0483
+#define PCI_DEVICE_ID_INTEL_82378	0x0484
+#define PCI_DEVICE_ID_INTEL_82430	0x0486
+#define PCI_DEVICE_ID_INTEL_82434	0x04a3
+#define PCI_DEVICE_ID_INTEL_I960	0x0960
+#define PCI_DEVICE_ID_INTEL_I960RM	0x0962
+#define PCI_DEVICE_ID_INTEL_82562ET	0x1031
+#define PCI_DEVICE_ID_INTEL_82801CAM	0x1038
+#define PCI_DEVICE_ID_INTEL_82815_MC	0x1130
+#define PCI_DEVICE_ID_INTEL_82815_AB	0x1131
+#define PCI_DEVICE_ID_INTEL_82815_CGC	0x1132
+#define PCI_DEVICE_ID_INTEL_82559ER	0x1209
+#define PCI_DEVICE_ID_INTEL_82092AA_0	0x1221
+#define PCI_DEVICE_ID_INTEL_82092AA_1	0x1222
+#define PCI_DEVICE_ID_INTEL_7116	0x1223
+#define PCI_DEVICE_ID_INTEL_7505_0	0x2550  
+#define PCI_DEVICE_ID_INTEL_7505_1	0x2552  
+#define PCI_DEVICE_ID_INTEL_7205_0	0x255d
+#define PCI_DEVICE_ID_INTEL_82596	0x1226
+#define PCI_DEVICE_ID_INTEL_82865	0x1227
+#define PCI_DEVICE_ID_INTEL_82557	0x1229
+#define PCI_DEVICE_ID_INTEL_82437	0x122d
+#define PCI_DEVICE_ID_INTEL_82371FB_0	0x122e
+#define PCI_DEVICE_ID_INTEL_82371FB_1	0x1230
+#define PCI_DEVICE_ID_INTEL_82371MX	0x1234
+#define PCI_DEVICE_ID_INTEL_82437MX	0x1235
+#define PCI_DEVICE_ID_INTEL_82441	0x1237
+#define PCI_DEVICE_ID_INTEL_82380FB	0x124b
+#define PCI_DEVICE_ID_INTEL_82439	0x1250
+#define PCI_DEVICE_ID_INTEL_80960_RP	0x1960
+#define PCI_DEVICE_ID_INTEL_82840_HB	0x1a21
+#define PCI_DEVICE_ID_INTEL_82845_HB	0x1a30
+#define PCI_DEVICE_ID_INTEL_82801AA_0	0x2410
+#define PCI_DEVICE_ID_INTEL_82801AA_1	0x2411
+#define PCI_DEVICE_ID_INTEL_82801AA_2	0x2412
+#define PCI_DEVICE_ID_INTEL_82801AA_3	0x2413
+#define PCI_DEVICE_ID_INTEL_82801AA_5	0x2415
+#define PCI_DEVICE_ID_INTEL_82801AA_6	0x2416
+#define PCI_DEVICE_ID_INTEL_82801AA_8	0x2418
+#define PCI_DEVICE_ID_INTEL_82801AB_0	0x2420
+#define PCI_DEVICE_ID_INTEL_82801AB_1	0x2421
+#define PCI_DEVICE_ID_INTEL_82801AB_2	0x2422
+#define PCI_DEVICE_ID_INTEL_82801AB_3	0x2423
+#define PCI_DEVICE_ID_INTEL_82801AB_5	0x2425
+#define PCI_DEVICE_ID_INTEL_82801AB_6	0x2426
+#define PCI_DEVICE_ID_INTEL_82801AB_8	0x2428
+#define PCI_DEVICE_ID_INTEL_82801BA_0	0x2440
+#define PCI_DEVICE_ID_INTEL_82801BA_1	0x2442
+#define PCI_DEVICE_ID_INTEL_82801BA_2	0x2443
+#define PCI_DEVICE_ID_INTEL_82801BA_3	0x2444
+#define PCI_DEVICE_ID_INTEL_82801BA_4	0x2445
+#define PCI_DEVICE_ID_INTEL_82801BA_5	0x2446
+#define PCI_DEVICE_ID_INTEL_82801BA_6	0x2448
+#define PCI_DEVICE_ID_INTEL_82801BA_7	0x2449
+#define PCI_DEVICE_ID_INTEL_82801BA_8	0x244a
+#define PCI_DEVICE_ID_INTEL_82801BA_9	0x244b
+#define PCI_DEVICE_ID_INTEL_82801BA_10	0x244c
+#define PCI_DEVICE_ID_INTEL_82801BA_11	0x244e
+#define PCI_DEVICE_ID_INTEL_82801E_0	0x2450
+#define PCI_DEVICE_ID_INTEL_82801E_2	0x2452
+#define PCI_DEVICE_ID_INTEL_82801E_3	0x2453
+#define PCI_DEVICE_ID_INTEL_82801E_9	0x2459
+#define PCI_DEVICE_ID_INTEL_82801E_11	0x245b
+#define PCI_DEVICE_ID_INTEL_82801E_13	0x245d
+#define PCI_DEVICE_ID_INTEL_82801E_14	0x245e
+#define PCI_DEVICE_ID_INTEL_82801CA_0	0x2480
+#define PCI_DEVICE_ID_INTEL_82801CA_2	0x2482
+#define PCI_DEVICE_ID_INTEL_82801CA_3	0x2483
+#define PCI_DEVICE_ID_INTEL_82801CA_4	0x2484
+#define PCI_DEVICE_ID_INTEL_82801CA_5	0x2485
+#define PCI_DEVICE_ID_INTEL_82801CA_6	0x2486
+#define PCI_DEVICE_ID_INTEL_82801CA_7	0x2487
+#define PCI_DEVICE_ID_INTEL_82801CA_10	0x248a
+#define PCI_DEVICE_ID_INTEL_82801CA_11	0x248b
+#define PCI_DEVICE_ID_INTEL_82801CA_12	0x248c
+#define PCI_DEVICE_ID_INTEL_82801DB_0	0x24c0
+#define PCI_DEVICE_ID_INTEL_82801DB_1	0x24c1
+#define PCI_DEVICE_ID_INTEL_82801DB_2	0x24c2
+#define PCI_DEVICE_ID_INTEL_82801DB_3	0x24c3
+#define PCI_DEVICE_ID_INTEL_82801DB_4	0x24c4
+#define PCI_DEVICE_ID_INTEL_82801DB_5	0x24c5
+#define PCI_DEVICE_ID_INTEL_82801DB_6	0x24c6
+#define PCI_DEVICE_ID_INTEL_82801DB_7	0x24c7
+#define PCI_DEVICE_ID_INTEL_82801DB_9	0x24c9
+#define PCI_DEVICE_ID_INTEL_82801DB_10	0x24ca
+#define PCI_DEVICE_ID_INTEL_82801DB_11	0x24cb
+#define PCI_DEVICE_ID_INTEL_82801DB_12  0x24cc
+#define PCI_DEVICE_ID_INTEL_82801DB_13	0x24cd
+#define PCI_DEVICE_ID_INTEL_82801EB_0	0x24d0
+#define PCI_DEVICE_ID_INTEL_82801EB_1	0x24d1
+#define PCI_DEVICE_ID_INTEL_82801EB_2	0x24d2
+#define PCI_DEVICE_ID_INTEL_82801EB_3	0x24d3
+#define PCI_DEVICE_ID_INTEL_82801EB_4	0x24d4
+#define PCI_DEVICE_ID_INTEL_82801EB_5	0x24d5
+#define PCI_DEVICE_ID_INTEL_82801EB_6	0x24d6
+#define PCI_DEVICE_ID_INTEL_82801EB_7	0x24d7
+#define PCI_DEVICE_ID_INTEL_82801EB_11	0x24db
+#define PCI_DEVICE_ID_INTEL_82801EB_13	0x24dd
+#define PCI_DEVICE_ID_INTEL_ESB_1	0x25a1
+#define PCI_DEVICE_ID_INTEL_ESB_2	0x25a2
+#define PCI_DEVICE_ID_INTEL_ESB_3	0x25a3
+#define PCI_DEVICE_ID_INTEL_ESB_31	0x25b0
+#define PCI_DEVICE_ID_INTEL_ESB_4	0x25a4
+#define PCI_DEVICE_ID_INTEL_ESB_5	0x25a6
+#define PCI_DEVICE_ID_INTEL_ESB_6	0x25a7
+#define PCI_DEVICE_ID_INTEL_ESB_7	0x25a9
+#define PCI_DEVICE_ID_INTEL_ESB_8	0x25aa
+#define PCI_DEVICE_ID_INTEL_ESB_9	0x25ab
+#define PCI_DEVICE_ID_INTEL_ESB_11	0x25ac
+#define PCI_DEVICE_ID_INTEL_ESB_12	0x25ad
+#define PCI_DEVICE_ID_INTEL_ESB_13	0x25ae
+#define PCI_DEVICE_ID_INTEL_82820_HB	0x2500
+#define PCI_DEVICE_ID_INTEL_82820_UP_HB	0x2501
+#define PCI_DEVICE_ID_INTEL_82850_HB	0x2530
+#define PCI_DEVICE_ID_INTEL_82860_HB	0x2531
+#define PCI_DEVICE_ID_INTEL_82845G_HB	0x2560
+#define PCI_DEVICE_ID_INTEL_82845G_IG	0x2562
+#define PCI_DEVICE_ID_INTEL_82865_HB	0x2570
+#define PCI_DEVICE_ID_INTEL_82865_IG	0x2572
+#define PCI_DEVICE_ID_INTEL_82875_HB	0x2578
+#define PCI_DEVICE_ID_INTEL_82875_IG	0x257b
+#define PCI_DEVICE_ID_INTEL_82915G_HB	0x2580
+#define PCI_DEVICE_ID_INTEL_82915G_IG	0x2582
+#define PCI_DEVICE_ID_INTEL_82915GM_HB	0x2590
+#define PCI_DEVICE_ID_INTEL_82915GM_IG	0x2592
+#define PCI_DEVICE_ID_INTEL_82945G_HB	0x2770
+#define PCI_DEVICE_ID_INTEL_82945G_IG	0x2772
+#define PCI_DEVICE_ID_INTEL_ICH6_0	0x2640
+#define PCI_DEVICE_ID_INTEL_ICH6_1	0x2641
+#define PCI_DEVICE_ID_INTEL_ICH6_2	0x2642
+#define PCI_DEVICE_ID_INTEL_ICH6_3	0x2651
+#define PCI_DEVICE_ID_INTEL_ICH6_4	0x2652
+#define PCI_DEVICE_ID_INTEL_ICH6_5	0x2653
+#define PCI_DEVICE_ID_INTEL_ICH6_6	0x2658
+#define PCI_DEVICE_ID_INTEL_ICH6_7	0x2659
+#define PCI_DEVICE_ID_INTEL_ICH6_8	0x265a
+#define PCI_DEVICE_ID_INTEL_ICH6_9	0x265b
+#define PCI_DEVICE_ID_INTEL_ICH6_10	0x265c
+#define PCI_DEVICE_ID_INTEL_ICH6_11	0x2660
+#define PCI_DEVICE_ID_INTEL_ICH6_12	0x2662
+#define PCI_DEVICE_ID_INTEL_ICH6_13	0x2664
+#define PCI_DEVICE_ID_INTEL_ICH6_14	0x2666
+#define PCI_DEVICE_ID_INTEL_ICH6_15	0x2668
+#define PCI_DEVICE_ID_INTEL_ICH6_16	0x266a
+#define PCI_DEVICE_ID_INTEL_ICH6_17	0x266d
+#define PCI_DEVICE_ID_INTEL_ICH6_18	0x266e
+#define PCI_DEVICE_ID_INTEL_ICH6_19	0x266f
+#define PCI_DEVICE_ID_INTEL_ESB2_0	0x2670
+#define PCI_DEVICE_ID_INTEL_ESB2_1	0x2680
+#define PCI_DEVICE_ID_INTEL_ESB2_2	0x2681
+#define PCI_DEVICE_ID_INTEL_ESB2_3	0x2682
+#define PCI_DEVICE_ID_INTEL_ESB2_4	0x2683
+#define PCI_DEVICE_ID_INTEL_ESB2_5	0x2688
+#define PCI_DEVICE_ID_INTEL_ESB2_6	0x2689
+#define PCI_DEVICE_ID_INTEL_ESB2_7	0x268a
+#define PCI_DEVICE_ID_INTEL_ESB2_8	0x268b
+#define PCI_DEVICE_ID_INTEL_ESB2_9	0x268c
+#define PCI_DEVICE_ID_INTEL_ESB2_10	0x2690
+#define PCI_DEVICE_ID_INTEL_ESB2_11	0x2692
+#define PCI_DEVICE_ID_INTEL_ESB2_12	0x2694
+#define PCI_DEVICE_ID_INTEL_ESB2_13	0x2696
+#define PCI_DEVICE_ID_INTEL_ESB2_14	0x2698
+#define PCI_DEVICE_ID_INTEL_ESB2_15	0x2699
+#define PCI_DEVICE_ID_INTEL_ESB2_16	0x269a
+#define PCI_DEVICE_ID_INTEL_ESB2_17	0x269b
+#define PCI_DEVICE_ID_INTEL_ESB2_18	0x269e
+#define PCI_DEVICE_ID_INTEL_ICH7_0	0x27b8
+#define PCI_DEVICE_ID_INTEL_ICH7_1	0x27b9
+#define PCI_DEVICE_ID_INTEL_ICH7_2	0x27c0
+#define PCI_DEVICE_ID_INTEL_ICH7_3	0x27c1
+#define PCI_DEVICE_ID_INTEL_ICH7_30	0x27b0
+#define PCI_DEVICE_ID_INTEL_ICH7_31	0x27bd
+#define PCI_DEVICE_ID_INTEL_ICH7_5	0x27c4
+#define PCI_DEVICE_ID_INTEL_ICH7_6	0x27c5
+#define PCI_DEVICE_ID_INTEL_ICH7_7	0x27c8
+#define PCI_DEVICE_ID_INTEL_ICH7_8	0x27c9
+#define PCI_DEVICE_ID_INTEL_ICH7_9	0x27ca
+#define PCI_DEVICE_ID_INTEL_ICH7_10	0x27cb
+#define PCI_DEVICE_ID_INTEL_ICH7_11	0x27cc
+#define PCI_DEVICE_ID_INTEL_ICH7_12	0x27d0
+#define PCI_DEVICE_ID_INTEL_ICH7_13	0x27d2
+#define PCI_DEVICE_ID_INTEL_ICH7_14	0x27d4
+#define PCI_DEVICE_ID_INTEL_ICH7_15	0x27d6
+#define PCI_DEVICE_ID_INTEL_ICH7_16	0x27d8
+#define PCI_DEVICE_ID_INTEL_ICH7_17	0x27da
+#define PCI_DEVICE_ID_INTEL_ICH7_18	0x27dc
+#define PCI_DEVICE_ID_INTEL_ICH7_19	0x27dd
+#define PCI_DEVICE_ID_INTEL_ICH7_20	0x27de
+#define PCI_DEVICE_ID_INTEL_ICH7_21	0x27df
+#define PCI_DEVICE_ID_INTEL_ICH7_22	0x27e0
+#define PCI_DEVICE_ID_INTEL_ICH7_23	0x27e2
+#define PCI_DEVICE_ID_INTEL_82855PM_HB	0x3340
+#define PCI_DEVICE_ID_INTEL_ESB2_19	0x3500
+#define PCI_DEVICE_ID_INTEL_ESB2_20	0x3501
+#define PCI_DEVICE_ID_INTEL_ESB2_21	0x3504
+#define PCI_DEVICE_ID_INTEL_ESB2_22	0x3505
+#define PCI_DEVICE_ID_INTEL_ESB2_23	0x350c
+#define PCI_DEVICE_ID_INTEL_ESB2_24	0x350d
+#define PCI_DEVICE_ID_INTEL_ESB2_25	0x3510
+#define PCI_DEVICE_ID_INTEL_ESB2_26	0x3511
+#define PCI_DEVICE_ID_INTEL_ESB2_27	0x3514
+#define PCI_DEVICE_ID_INTEL_ESB2_28	0x3515
+#define PCI_DEVICE_ID_INTEL_ESB2_29	0x3518
+#define PCI_DEVICE_ID_INTEL_ESB2_30	0x3519
+#define PCI_DEVICE_ID_INTEL_82830_HB	0x3575
+#define PCI_DEVICE_ID_INTEL_82830_CGC	0x3577
+#define PCI_DEVICE_ID_INTEL_82855GM_HB	0x3580
+#define PCI_DEVICE_ID_INTEL_82855GM_IG	0x3582
+#define PCI_DEVICE_ID_INTEL_E7520_MCH	0x3590
+#define PCI_DEVICE_ID_INTEL_E7320_MCH	0x3592
+#define PCI_DEVICE_ID_INTEL_MCH_PA	0x3595
+#define PCI_DEVICE_ID_INTEL_MCH_PA1	0x3596
+#define PCI_DEVICE_ID_INTEL_MCH_PB	0x3597
+#define PCI_DEVICE_ID_INTEL_MCH_PB1	0x3598
+#define PCI_DEVICE_ID_INTEL_MCH_PC	0x3599
+#define PCI_DEVICE_ID_INTEL_MCH_PC1	0x359a
+#define PCI_DEVICE_ID_INTEL_E7525_MCH	0x359e
+#define PCI_DEVICE_ID_INTEL_80310	0x530d
+#define PCI_DEVICE_ID_INTEL_82371SB_0	0x7000
+#define PCI_DEVICE_ID_INTEL_82371SB_1	0x7010
+#define PCI_DEVICE_ID_INTEL_82371SB_2	0x7020
+#define PCI_DEVICE_ID_INTEL_82437VX	0x7030
+#define PCI_DEVICE_ID_INTEL_82439TX	0x7100
+#define PCI_DEVICE_ID_INTEL_82371AB_0	0x7110
+#define PCI_DEVICE_ID_INTEL_82371AB	0x7111
+#define PCI_DEVICE_ID_INTEL_82371AB_2	0x7112
+#define PCI_DEVICE_ID_INTEL_82371AB_3	0x7113
+#define PCI_DEVICE_ID_INTEL_82810_MC1	0x7120
+#define PCI_DEVICE_ID_INTEL_82810_IG1	0x7121
+#define PCI_DEVICE_ID_INTEL_82810_MC3	0x7122
+#define PCI_DEVICE_ID_INTEL_82810_IG3	0x7123
+#define PCI_DEVICE_ID_INTEL_82810E_MC	0x7124
+#define PCI_DEVICE_ID_INTEL_82810E_IG	0x7125
+#define PCI_DEVICE_ID_INTEL_82443LX_0	0x7180
+#define PCI_DEVICE_ID_INTEL_82443LX_1	0x7181
+#define PCI_DEVICE_ID_INTEL_82443BX_0	0x7190
+#define PCI_DEVICE_ID_INTEL_82443BX_1	0x7191
+#define PCI_DEVICE_ID_INTEL_82443BX_2	0x7192
+#define PCI_DEVICE_ID_INTEL_440MX	0x7195
+#define PCI_DEVICE_ID_INTEL_82443MX_0	0x7198
+#define PCI_DEVICE_ID_INTEL_82443MX_1	0x7199
+#define PCI_DEVICE_ID_INTEL_82443MX_2	0x719a
+#define PCI_DEVICE_ID_INTEL_82443MX_3	0x719b
+#define PCI_DEVICE_ID_INTEL_82443GX_0	0x71a0
+#define PCI_DEVICE_ID_INTEL_82443GX_1	0x71a1
+#define PCI_DEVICE_ID_INTEL_82443GX_2	0x71a2
+#define PCI_DEVICE_ID_INTEL_82372FB_0	0x7600
+#define PCI_DEVICE_ID_INTEL_82372FB_1	0x7601
+#define PCI_DEVICE_ID_INTEL_82372FB_2	0x7602
+#define PCI_DEVICE_ID_INTEL_82372FB_3	0x7603
+#define PCI_DEVICE_ID_INTEL_82454GX	0x84c4
+#define PCI_DEVICE_ID_INTEL_82450GX	0x84c5
+#define PCI_DEVICE_ID_INTEL_82451NX	0x84ca
+#define PCI_DEVICE_ID_INTEL_82454NX     0x84cb
+#define PCI_DEVICE_ID_INTEL_84460GX	0x84ea
+#define PCI_DEVICE_ID_INTEL_IXP4XX	0x8500
+#define PCI_DEVICE_ID_INTEL_IXP2400	0x9001
+#define PCI_DEVICE_ID_INTEL_IXP2800	0x9004
+#define PCI_DEVICE_ID_INTEL_S21152BB	0xb152
+
+#define PCI_VENDOR_ID_COMPUTONE		0x8e0e
+#define PCI_DEVICE_ID_COMPUTONE_IP2EX	0x0291
+#define PCI_DEVICE_ID_COMPUTONE_PG	0x0302
+#define PCI_SUBVENDOR_ID_COMPUTONE	0x8e0e
+#define PCI_SUBDEVICE_ID_COMPUTONE_PG4	0x0001
+#define PCI_SUBDEVICE_ID_COMPUTONE_PG8	0x0002
+#define PCI_SUBDEVICE_ID_COMPUTONE_PG6	0x0003
+
+#define PCI_VENDOR_ID_KTI		0x8e2e
+#define PCI_DEVICE_ID_KTI_ET32P2	0x3000
+
+#define PCI_VENDOR_ID_ADAPTEC		0x9004
+#define PCI_DEVICE_ID_ADAPTEC_7810	0x1078
+#define PCI_DEVICE_ID_ADAPTEC_7821	0x2178
+#define PCI_DEVICE_ID_ADAPTEC_38602	0x3860
+#define PCI_DEVICE_ID_ADAPTEC_7850	0x5078
+#define PCI_DEVICE_ID_ADAPTEC_7855	0x5578
+#define PCI_DEVICE_ID_ADAPTEC_5800	0x5800
+#define PCI_DEVICE_ID_ADAPTEC_3860	0x6038
+#define PCI_DEVICE_ID_ADAPTEC_1480A	0x6075
+#define PCI_DEVICE_ID_ADAPTEC_7860	0x6078
+#define PCI_DEVICE_ID_ADAPTEC_7861	0x6178
+#define PCI_DEVICE_ID_ADAPTEC_7870	0x7078
+#define PCI_DEVICE_ID_ADAPTEC_7871	0x7178
+#define PCI_DEVICE_ID_ADAPTEC_7872	0x7278
+#define PCI_DEVICE_ID_ADAPTEC_7873	0x7378
+#define PCI_DEVICE_ID_ADAPTEC_7874	0x7478
+#define PCI_DEVICE_ID_ADAPTEC_7895	0x7895
+#define PCI_DEVICE_ID_ADAPTEC_7880	0x8078
+#define PCI_DEVICE_ID_ADAPTEC_7881	0x8178
+#define PCI_DEVICE_ID_ADAPTEC_7882	0x8278
+#define PCI_DEVICE_ID_ADAPTEC_7883	0x8378
+#define PCI_DEVICE_ID_ADAPTEC_7884	0x8478
+#define PCI_DEVICE_ID_ADAPTEC_7885	0x8578
+#define PCI_DEVICE_ID_ADAPTEC_7886	0x8678
+#define PCI_DEVICE_ID_ADAPTEC_7887	0x8778
+#define PCI_DEVICE_ID_ADAPTEC_7888	0x8878
+#define PCI_DEVICE_ID_ADAPTEC_1030	0x8b78
+
+#define PCI_VENDOR_ID_ADAPTEC2		0x9005
+#define PCI_DEVICE_ID_ADAPTEC2_2940U2	0x0010
+#define PCI_DEVICE_ID_ADAPTEC2_2930U2	0x0011
+#define PCI_DEVICE_ID_ADAPTEC2_7890B	0x0013
+#define PCI_DEVICE_ID_ADAPTEC2_7890	0x001f
+#define PCI_DEVICE_ID_ADAPTEC2_3940U2	0x0050
+#define PCI_DEVICE_ID_ADAPTEC2_3950U2D	0x0051
+#define PCI_DEVICE_ID_ADAPTEC2_7896	0x005f
+#define PCI_DEVICE_ID_ADAPTEC2_7892A	0x0080
+#define PCI_DEVICE_ID_ADAPTEC2_7892B	0x0081
+#define PCI_DEVICE_ID_ADAPTEC2_7892D	0x0083
+#define PCI_DEVICE_ID_ADAPTEC2_7892P	0x008f
+#define PCI_DEVICE_ID_ADAPTEC2_7899A	0x00c0
+#define PCI_DEVICE_ID_ADAPTEC2_7899B	0x00c1
+#define PCI_DEVICE_ID_ADAPTEC2_7899D	0x00c3
+#define PCI_DEVICE_ID_ADAPTEC2_7899P	0x00cf
+#define PCI_DEVICE_ID_ADAPTEC2_SCAMP	0x0503
+
+#define PCI_VENDOR_ID_ATRONICS		0x907f
+#define PCI_DEVICE_ID_ATRONICS_2015	0x2015
+
+#define PCI_VENDOR_ID_HOLTEK		0x9412
+#define PCI_DEVICE_ID_HOLTEK_6565	0x6565
+
+#define PCI_VENDOR_ID_NETMOS		0x9710
+#define PCI_DEVICE_ID_NETMOS_9705	0x9705
+#define PCI_DEVICE_ID_NETMOS_9715	0x9715
+#define PCI_DEVICE_ID_NETMOS_9735	0x9735
+#define PCI_DEVICE_ID_NETMOS_9745	0x9745
+#define PCI_DEVICE_ID_NETMOS_9755	0x9755
+#define PCI_DEVICE_ID_NETMOS_9805	0x9805
+#define PCI_DEVICE_ID_NETMOS_9815	0x9815
+#define PCI_DEVICE_ID_NETMOS_9835	0x9835
+#define PCI_DEVICE_ID_NETMOS_9845	0x9845
+#define PCI_DEVICE_ID_NETMOS_9855	0x9855
+
+#define PCI_SUBVENDOR_ID_EXSYS		0xd84d
+#define PCI_SUBDEVICE_ID_EXSYS_4014	0x4014
+
+#define PCI_VENDOR_ID_TIGERJET		0xe159
+#define PCI_DEVICE_ID_TIGERJET_300	0x0001
+#define PCI_DEVICE_ID_TIGERJET_100	0x0002
+
+#define PCI_VENDOR_ID_TTTECH		0x0357
+#define PCI_DEVICE_ID_TTTECH_MC322	0x000A
+
+#define PCI_VENDOR_ID_ARK		0xedd8
+#define PCI_DEVICE_ID_ARK_STING		0xa091
+#define PCI_DEVICE_ID_ARK_STINGARK	0xa099
+#define PCI_DEVICE_ID_ARK_2000MT	0xa0a1
diff --git a/FireBee/trunk/usb/store/host/ohci-pci/pcixbios.h b/FireBee/trunk/usb/store/host/ohci-pci/pcixbios.h
new file mode 100644
index 0000000..5788130
--- /dev/null
+++ b/FireBee/trunk/usb/store/host/ohci-pci/pcixbios.h
@@ -0,0 +1,342 @@
+/* TOS 4.04 Xbios PCI for the CT60 board
+*  Didier Mequignon 2005, e-mail: aniplay@wanadoo.fr
+*
+*  This library is free software; you can redistribute it and/or
+*  modify it under the terms of the GNU Lesser General Public
+*  License as published by the Free Software Foundation; either
+*  version 2.1 of the License, or (at your option) any later version.
+*
+*  This library is distributed in the hope that it will be useful,
+*  but WITHOUT ANY WARRANTY; without even the implied warranty of
+*  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+*  Lesser General Public License for more details.
+*
+*  You should have received a copy of the GNU Lesser General Public
+*  License along with this library; if not, write to the Free Software
+*  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+*/
+
+#ifndef	_OHCI_PCI_PCIXBIOS_H
+#define	_OHCI_PCI_PCIXBIOS_H
+
+#define PCIIDR                0x00   /* PCI Configuration ID Register       */
+#define PCICSR                0x04   /* PCI Command/Status Register         */
+#define PCICR                 0x04   /* PCI Command Register                */
+#define PCISR                 0x06   /* PCI Status Register                 */
+#define PCIREV                0x08   /* PCI Revision ID Register            */
+#define PCICCR                0x09   /* PCI Class Code Register             */
+#define PCICLSR               0x0C   /* PCI Cache Line Size Register        */
+#define PCILTR                0x0D   /* PCI Latency Timer Register          */
+#define PCIHTR                0x0E   /* PCI Header Type Register            */
+#define PCIBISTR              0x0F   /* PCI Build-In Self Test Register     */
+#define PCIBAR0               0x10   /* PCI Base Address Register for Memory
+                                        Accesses to Local, Runtime, and DMA */
+#define PCIBAR1               0x14   /* PCI Base Address Register for I/O
+                                        Accesses to Local, Runtime, and DMA */
+#define PCIBAR2               0x18   /* PCI Base Address Register for Memory
+                                        Accesses to Local Address Space 0   */
+#define PCIBAR3               0x1C   /* PCI Base Address Register for Memory
+                                        Accesses to Local Address Space 1   */ 
+#define PCIBAR4               0x20   /* PCI Base Address Register, reserved */
+#define PCIBAR5               0x24   /* PCI Base Address Register, reserved */
+#define PCICIS                0x28   /* PCI Cardbus CIS Pointer, not support*/
+#define PCISVID               0x2C   /* PCI Subsystem Vendor ID             */
+#define PCISID                0x2E   /* PCI Subsystem ID                    */
+#define PCIERBAR              0x30   /* PCI Expansion ROM Base Register     */
+#define CAP_PTR               0x34   /* New Capability Pointer              */
+#define PCIILR                0x3C   /* PCI Interrupt Line Register         */
+#define PCIIPR                0x3D   /* PCI Interrupt Pin Register          */
+#define PCIMGR                0x3E   /* PCI Min_Gnt Register                */
+#define PCIMLR                0x3F   /* PCI Max_Lat Register                */
+#define PMCAPID               0x40   /* Power Management Capability ID      */
+#define PMNEXT                0x41   /* Power Management Next Capability
+                                        Pointer                             */
+#define PMC                   0x42   /* Power Management Capabilities       */
+#define PMCSR                 0x44   /* Power Management Control/Status     */
+#define PMCSR_BSE             0x46   /* PMCSR Bridge Support Extensions     */
+#define PMDATA                0x47   /* Power Management Data               */
+#define HS_CNTL               0x48   /* Hot Swap Control                    */
+#define HS_NEXT               0x49   /* Hot Swap Next Capability Pointer    */
+#define HS_CSR                0x4A   /* Hot Swap Control/Status             */
+#define PVPDCNTL              0x4C   /* PCI Vital Product Data Control      */
+#define PVPD_NEXT             0x4D   /* PCI Vital Product Data Next
+                                        Capability Pointer                  */
+#define PVPDAD                0x4E   /* PCI Vital Product Data Address      */
+#define PVPDATA               0x50   /* PCI VPD Data                        */
+
+typedef struct
+{
+  unsigned long *subcookie;
+  unsigned long version;
+  long routine[45];
+} PCI_COOKIE;
+
+typedef struct                       /* structure of resource descriptor    */
+{
+	unsigned short next;               /* length of the following structure   */
+	unsigned short flags;              /* type of resource and misc. flags    */
+	unsigned long start;               /* start-address of resource           */
+	unsigned long length;              /* length of resource                  */
+	unsigned long offset;              /* offset PCI to phys. CPU Address     */
+	unsigned long dmaoffset;           /* offset for DMA-transfers            */
+} PCI_RSC_DESC;
+
+typedef struct                       /* structure of address conversion     */
+{
+	unsigned long adr;                 /* calculated address (CPU<->PCI)      */
+	unsigned long len;                 /* length of memory range              */
+} PCI_CONV_ADR;
+
+/******************************************************************************/
+/*                          PCI-BIOS Error Codes                              */
+/******************************************************************************/
+#define PCI_SUCCESSFUL            0  /* everything's fine         */
+#define PCI_FUNC_NOT_SUPPORTED   -2  /* function not supported    */
+#define PCI_BAD_VENDOR_ID        -3  /* wrong Vendor ID           */
+#define PCI_DEVICE_NOT_FOUND     -4  /* PCI-Device not found      */
+#define PCI_BAD_REGISTER_NUMBER  -5  /* wrong register number     */
+#define PCI_SET_FAILED           -6  /* reserved for later use    */
+#define PCI_BUFFER_TOO_SMALL     -7  /* reserved for later use    */
+#define PCI_GENERAL_ERROR        -8  /* general BIOS error code   */
+#define PCI_BAD_HANDLE           -9  /* wrong/unknown PCI-handle  */
+
+/******************************************************************************/
+/*                      Flags used in Resource-Descriptor                     */
+/******************************************************************************/
+#define FLG_IO        0x4000         /* Ressource in IO range               */
+#define FLG_LAST      0x8000         /* last ressource                      */
+#define FLG_8BIT      0x0100         /* 8 bit accesses allowed              */
+#define FLG_16BIT     0x0200         /* 16 bit accesses allowed             */
+#define FLG_32BIT     0x0400         /* 32 bit accesses allowed             */
+#define FLG_ENDMASK   0x000F         /* mask for byte ordering              */
+
+/******************************************************************************/
+/*                 Values used in FLG_ENDMASK for Byte Ordering               */
+/******************************************************************************/
+#define ORD_MOTOROLA       0         /* Motorola (big endian)               */
+#define ORD_INTEL_AS       1         /* Intel (little endian), addr.swapped */
+#define ORD_INTEL_LS       2         /* Intel (little endian), lane swapped */
+#define ORD_UNKNOWN       15         /* unknown (BIOS-calls allowed only)   */
+
+/******************************************************************************/
+/*                   Status Info used in Device-Descriptor                    */
+/******************************************************************************/
+#define DEVICE_FREE        0         /* Device is not used                  */
+#define DEVICE_USED        1         /* Device is used by another driver    */
+#define DEVICE_CALLBACK    2         /* used, but driver can be cancelled   */
+#define DEVICE_AVAILABLE   3         /* used, not available                 */
+#define NO_DEVICE         -1         /* no device detected                  */
+
+/******************************************************************************/
+/*                            Callback-Routine                                */
+/******************************************************************************/
+ #define GET_DRIVER_ID      0        /* CB-Routine 0: Get Driver ID         */
+ #define REMOVE_DRIVER      1        /* CB-Routine 1: Remove Driver         */
+
+/******************************************************************************/
+/*                              Functions                                     */
+/******************************************************************************/
+//#ifndef OSBIND_CLOBBER_LIST
+//#define OSBIND_CLOBBER_LIST
+//#endif
+
+#ifndef trap_14_wlw
+#define trap_14_wlw(n, a, b)	\
+__extension__	\
+({	\
+	register long retvalue __asm__("d0");	\
+	long  _a = (long) (a);	\
+	short _b = (short) (b);	\
+	\
+	__asm__ volatile (	\
+		"movw	%3,sp@-\n\t"	\
+		"movl	%2,sp@-\n\t"	\
+		"movw	%1,sp@-\n\t"	\
+		"trap	#14\n\t"	\
+		"lea	sp@(8),sp"	\
+		: "=r"(retvalue)	\
+		: "g"(n), "r"(_a), "r"(_b)	\
+	);	\
+	retvalue;	\
+})
+#endif
+#ifndef trap_14_wll
+#define trap_14_wll(n, a, b)	\
+__extension__	\
+({	\
+	register long retvalue __asm__("d0");	\
+	long _a = (long) (a);	\
+	long _b = (long) (b);	\
+	\
+	__asm__ volatile (	\
+		"movl	%3,sp@-\n\t"	\
+		"movl	%2,sp@-\n\t"	\
+		"movw	%1,sp@-\n\t"	\
+		"trap	#14\n\t"	\
+		"lea	sp@(10),sp"	\
+		: "=r"(retvalue)	\
+		: "g"(n), "r"(_a), "r"(_b)	\
+	);	\
+	retvalue;	\
+})
+#endif
+#ifndef trap_14_wlww
+#define trap_14_wlww(n, a, b, c)	\
+__extension__	\
+({	\
+	register long retvalue __asm__("d0");	\
+	long  _a = (long) (a);	\
+	short _b = (short) (b);	\
+	short  _c = (short) (c);	\
+	\
+	__asm__ volatile (	\
+		"movl	%4,sp@-\n\t"	\
+		"movw	%3,sp@-\n\t"	\
+		"movw	%2,sp@-\n\t"	\
+		"movw	%1,sp@-\n\t"	\
+		"trap	#14\n\t"	\
+		"lea	sp@(10),sp"	\
+		: "=r"(retvalue)	\
+		: "g"(n), "r"(_a), "r"(_b), "r"(_c)	\
+	);	\
+	retvalue;	\
+})
+#endif
+#ifndef trap_14_wlwl
+#define trap_14_wlwl(n, a, b, c)	\
+__extension__	\
+({	\
+	register long retvalue __asm__("d0");	\
+	long  _a = (long) (a);	\
+	short _b = (short) (b);	\
+	long  _c = (long) (c);	\
+	\
+	__asm__ volatile (	\
+		"movl	%4,sp@-\n\t"	\
+		"movw	%3,sp@-\n\t"	\
+		"movl	%2,sp@-\n\t"	\
+		"movw	%1,sp@-\n\t"	\
+		"trap	#14\n\t"	\
+		"lea	sp@(12),sp"	\
+		: "=r"(retvalue)	\
+		: "g"(n), "r"(_a), "r"(_b), "r"(_c)	\
+	);	\
+	retvalue;	\
+})
+#endif
+#ifndef trap_14_wlll
+#define trap_14_wlll(n, a, b, c)	\
+__extension__	\
+({	\
+	register long retvalue __asm__("d0");	\
+	long  _a = (long) (a);	\
+	long  _b = (long) (b);	\
+	long  _c = (long) (c);	\
+	\
+	__asm__ volatile (	\
+		"movl	%4,sp@-\n\t"	\
+		"movl	%3,sp@-\n\t"	\
+		"movl	%2,sp@-\n\t"	\
+		"movw	%1,sp@-\n\t"	\
+		"trap	#14\n\t"	\
+		"lea	sp@(14),sp"	\
+		: "=r"(retvalue)	\
+		: "g"(n), "r"(_a), "r"(_b), "r"(_c)	\
+	);	\
+	retvalue;	\
+})
+#endif
+
+#define find_pci_device(id,index) (long)trap_14_wlw((short)(300),(unsigned long)(id),(unsigned short)(index))
+#define find_pci_classcode(classcode,index) (long)trap_14_wlw((short)(301),(unsigned long)(classcode),(unsigned short)(index))
+#define read_config_byte(handle,reg,address) (long)trap_14_wlwl((short)(302),(long)(handle),(unsigned short)(reg),(unsigned char *)(address))
+#define read_config_word(handle,reg,address) (long)trap_14_wlwl((short)(303),(long)(handle),(unsigned short)(reg),(unsigned short *)(address))
+#define read_config_longword(handle,reg,address) (long)trap_14_wlwl((short)(304),(long)(handle),(unsigned short)(reg),(unsigned long *)(address))
+#define fast_read_config_byte(handle,reg) (unsigned char)trap_14_wlw((short)(305),(long)(handle),(unsigned short)(reg))
+#define fast_read_config_word(handle,reg) (unsigned short)trap_14_wlw((short)(306),(long)(handle),(unsigned short)(reg))
+#define fast_read_config_longword(handle,reg) (unsigned long)trap_14_wlw((short)(307),(long)(handle),(unsigned short)(reg))
+#define write_config_byte(handle,reg,data) (long)trap_14_wlww((short)(308),(long)(handle),(unsigned short)(reg),(unsigned short)(data))
+#define write_config_word(handle,reg,data) (long)trap_14_wlww((short)(309),(long)(handle),(unsigned short)(reg),(unsigned short)(data))
+#define write_config_longword(handle,reg,data) (long)trap_14_wlwl((short)(310),(long)(handle),(unsigned short)(reg),(unsigned long)(data))
+#define hook_interrupt(handle,routine,parameter) (long)trap_14_wlll((short)(311),(long)(handle),(unsigned long *)(routine),(unsigned long *)(parameter))
+#define unhook_interrupt(handle) (long)trap_14_wl((short)(312),(long)(handle))
+#define special_cycle(bus_number,special_cycle) (long)trap_14_wwl((short)(313),(unsigned short)(bus_number),(unsigned long)(special_cycle))
+#define get_routing(handle) (long)trap_14_wl((short)(314),(long)(handle))
+#define set_interrupt(handle,mode) (long)trap_14_wlw((short)(315),(long)(handle),(short)(mode))
+#define get_resource(handle) (long)trap_14_wl((short)(316),(long)(handle))
+#define get_card_used(handle,callback) (long)trap_14_wll((short)(317),(long)(handle),(long *)(address))
+#define set_card_used(handle,callback) (long)trap_14_wll((short)(318),(long)(handle),(long *)(callback))
+#define read_mem_byte(handle,offset,address) (long)trap_14_wlll((short)(319),(long)(handle),(unsigned long)(offset),(unsigned char *)(address))
+#define read_mem_word(handle,offset,address) (long)trap_14_wlll((short)(320),(unsigned long)(offset),(unsigned short *)(address))
+#define read_mem_longword(handle,offset,address) (long)trap_14_wlll((short)(321),(unsigned long)(offset),(unsigned long *)(address))
+#define fast_read_mem_byte(handle,offset) (unsigned char)trap_14_wll((short)(322),(long)(handle),(unsigned long)(offset))
+#define fast_read_mem_word(handle,offset) (unsigned short)trap_14_wll((short)(323),(long)(handle),(unsigned long)(offset))
+#define fast_read_mem_longword(handle,offset) (unsigned long)trap_14_wll((short)(324),(long)(handle),(unsigned long)(offset))
+#define write_mem_byte(handle,offset,data) (long)trap_14_wllw((short)(325),(long)(handle),(unsigned long)(offset),(unsigned short)(data))
+#define write_mem_word(handle,offset,data) (long)trap_14_wllw((short)(326),(long)(handle),(unsigned long)(offset),(unsigned short)(data))
+#define write_mem_longword(handle,offset,data) (long)trap_14_wlll((short)(327),(long)(handle),(unsigned long)(offset),(unsigned long)(data))
+#define read_io_byte(handle,offset,address) (long)trap_14_wlll((short)(328),(long)(handle),(unsigned long)(offset),(unsigned char *)(address))
+#define read_io_word(handle,offset,address) (long)trap_14_wlll((short)(329),(long)(handle),(unsigned long)(offset),(unsigned short *)(address))
+#define read_io_longword(handle,offset,address) (long)trap_14_wlll((short)(330),(long)(handle),(unsigned long)(offset),(unsigned long *)(address))
+#define fast_read_io_byte(handle,offset) (unsigned char)trap_14_wll((short)(331),(long)(handle),(unsigned long)(offset))
+#define fast_read_io_word(handle,offset) (unsigned short)trap_14_wll((short)(332),(long)(handle),(unsigned long)(offset))
+#define fast_read_io_longword(handle,offset) (unsigned long)trap_14_wll((short)(333),(long)(handle),(unsigned long)(offset))
+#define write_io_byte(handle,offset,data) (long)trap_14_wllw((short)(334),(long)(handle),(unsigned long)(offset),(unsigned short)(data))
+#define write_io_word(handle,offset,data) (long)trap_14_wllw((short)(335),(long)(handle),(unsigned long)(offset),(unsigned short)(data))
+#define write_io_longword(handle,offset,data) (long)trap_14_wlll((short)(336),(long)(handle),(unsigned long)(offset),(unsigned long)(data))
+#define get_machine_id() (long)trap_14_w((short)(337))
+#define get_pagesize() (long)trap_14_w((short)(338))
+#define virt_to_bus(handle,address,pointer) (long)trap_14_wlll((short)(339),(long)(handle),(unsigned long)(address),(unsigned long *)(pointer))
+#define bus_to_virt(handle,address,pointer) (long)trap_14_wlll((short)(340),(long)(handle),(unsigned long)(address),(unsigned long *)(pointer))
+#define virt_to_phys(address,pointer) (long)trap_14_wll((short)(341),(unsigned long)(address),(unsigned long *)(pointer))
+#define phys_to_virt(address,pointer) (long)trap_14_wll((short)(342),(unsigned long)(address),(unsigned long *)(pointer))
+#define dma_setbuffer(pci_address,local_address,size) (long)trap_14_wlll((short)(350),(unsigned long)(pci_address),(unsigned long)(local_address),(unsigned long)(size))
+#define dma_buffoper(mode) (long)trap_14_ww((short)(351),(short)(mode))
+#define read_mailbox(mailbox,pointer)  (long)trap_14_wwl((short)(352),(short)(mailbox),(unsigned long *)(pointer))
+#define write_mailbox(mailbox,data) (long)trap_14_wwl((short)(353),(short)(mailbox),(unsigned long)(data))
+
+extern long Find_pci_device(unsigned long id, unsigned short index);
+extern long Find_pci_classcode(unsigned long class, unsigned short index);
+extern long Read_config_byte(long handle, unsigned short reg, unsigned char *address);
+extern long Read_config_word(long handle, unsigned short reg, unsigned short *address);
+extern long Read_config_longword(long handle, unsigned short reg, unsigned long *address);
+extern unsigned char Fast_read_config_byte(long handle, unsigned short reg);
+extern unsigned short Fast_read_config_word(long handle, unsigned short reg);
+extern unsigned long Fast_read_config_longword(long handle, unsigned short reg);
+extern long Write_config_byte(long handle, unsigned short reg, unsigned short val);
+extern long Write_config_word(long handle, unsigned short reg, unsigned short val);
+extern long Write_config_longword(long handle, unsigned short reg, unsigned long val);
+extern long Hook_interrupt(long handle, unsigned long *routine, unsigned long *parameter);
+extern long Unhook_interrupt(long handle);
+extern long Special_cycle(unsigned short bus, unsigned long data);
+extern long Get_routing(long handle);
+extern long Set_interrupt(long handle);
+extern long Get_resource(long handle);
+extern long Get_card_used(long handle, unsigned long *address);
+extern long Set_card_used(long handle, unsigned long *callback);
+extern long Read_mem_byte(long handle, unsigned long offset, unsigned char *address);
+extern long Read_mem_word(long handle, unsigned long offset, unsigned short *address);
+extern long Read_mem_longword(long handle, unsigned long offset, unsigned long *address);
+extern unsigned char Fast_read_mem_byte(long handle, unsigned long offset);
+extern unsigned short Fast_read_mem_word(long handle, unsigned long offset);
+extern unsigned long Fast_read_mem_longword(long handle, unsigned long offset);
+extern long Write_mem_byte(long handle, unsigned long offset, unsigned short val);
+extern long Write_mem_word(long handle, unsigned long offset, unsigned short val);
+extern long Write_mem_longword(long handle, unsigned long offset, unsigned long val);
+extern long Read_io_byte(long handle, unsigned long offset, unsigned char *address);
+extern long Read_io_word(long handle, unsigned long offset, unsigned short *address);
+extern long Read_io_longword(long handle, unsigned long offset, unsigned long *address);
+extern unsigned char Fast_read_io_byte(long handle, unsigned long offset);
+extern unsigned short Fast_read_io_word(long handle, unsigned long offset);
+extern unsigned long Fast_read_io_longword(long handle, unsigned long offset);
+extern long Write_io_byte(long handle, unsigned long offset, unsigned short val);
+extern long Write_io_word(long handle, unsigned long offset, unsigned short val);
+extern long Write_io_longword(long handle, unsigned long offset, unsigned long val);
+extern long Get_machine_id(void);
+extern long Get_pagesize(void);
+extern long Virt_to_bus(long handle, unsigned long address, PCI_CONV_ADR *pointer);
+extern long Bus_to_virt(long handle, unsigned long address, PCI_CONV_ADR *pointer);
+extern long Virt_to_phys(unsigned long address, PCI_CONV_ADR *pointer);
+extern long Phys_to_virt(unsigned long address, PCI_CONV_ADR *pointer);
+
+#endif
diff --git a/FireBee/trunk/usb/store/main.c b/FireBee/trunk/usb/store/main.c
new file mode 100644
index 0000000..32d7f4b
--- /dev/null
+++ b/FireBee/trunk/usb/store/main.c
@@ -0,0 +1,206 @@
+/* 
+ * David Galvez. 2010, e-mail: dgalvez75@gmail.com
+ * PCI code taken from FireTos by Didier Mequignon
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include "config.h"
+#include "usb.h"
+#include "super.h"
+#include "debug.h"
+#ifdef PCI_XBIOS
+#include "host/ohci-pci/pci_ids.h"
+#include "host/ohci-pci/pcixbios.h"
+#endif
+#include <mint/basepage.h>
+#include <mint/cookie.h>
+
+extern long install_usb_stor(int dev_num, unsigned long part_type, 
+			     unsigned long part_offset, unsigned long part_size, 
+			     char *vendor, char *revision, char *product);
+extern int do_usb(int argc, char **argv);
+extern unsigned long _PgmSize;
+extern long __mint;
+#ifdef PCI_XBIOS
+extern struct pci_device_id usb_pci_table[]; /* ohci-hcd.c */
+#endif
+
+int usb_stor_curr_dev;
+unsigned long usb_1st_disk_drive;
+short max_logical_drive;
+
+#ifdef PCI_XBIOS
+short pci_init(void)
+{
+/* PCI devices detection */ 
+	struct pci_device_id *board;
+	long handle;
+	short usb_found;
+
+	short idx;
+	long err;
+	unsigned long class;
+		
+	usb_found = 0;
+	idx = 0;
+	do {
+		handle = find_pci_device(0x0000FFFFL, idx++);
+printf("idx %d PCI handle: %lx\n", idx -1, handle); /* Galvez: Debug */
+		if(handle >= 0)	{
+			unsigned long id = 0;
+			err = read_config_longword(handle, PCIIDR, &id);
+
+			if((err >= 0) && !usb_found) {
+				if(read_config_longword(handle, PCIREV, &class) >= 0
+					&& ((class >> 16) == PCI_CLASS_SERIAL_USB)) {	
+					if((class >> 8) == PCI_CLASS_SERIAL_USB_UHCI)
+						(void) Cconws("UHCI USB controller found\r\n");
+					else if((class >> 8) == PCI_CLASS_SERIAL_USB_OHCI) {
+						(void) Cconws("OHCI USB controller found\r\n");
+#ifdef CONFIG_USB_OHCI
+						board = usb_pci_table; /* compare table */
+						while(board->vendor) {
+							if((board->vendor == (id & 0xFFFF))
+				 				&& (board->device == (id >> 16))) {
+								if(usb_init(handle, board) >= 0)
+									usb_found = 1;
+								break;
+							}
+							board++;
+						}
+#endif /* CONFIG_USB_OHCI */
+					}
+					else if((class >> 8) == PCI_CLASS_SERIAL_USB_EHCI)
+						(void) Cconws("EHCI USB controller found\r\n");
+				}
+			}
+		}    
+	}
+	while(handle >= 0);
+	return usb_found;
+}
+#endif /* PCI_XBIOS */
+
+int main(int argc, char **argv)
+{
+#ifdef CONFIG_USB_STORAGE			
+	long p = 0;
+	int r;
+
+	if (__mint)
+		max_logical_drive = 24;
+	else max_logical_drive = 16;
+
+	if (argc == 1) {
+		short usb_found = 0;
+	
+		usb_stor_curr_dev = -1;
+		usb_1st_disk_drive = 0;
+
+		usb_stop();
+#ifdef PCI_XBIOS
+		usb_found = pci_init();	
+#else
+		if (usb_init() >= 0)
+			usb_found = 1;
+#endif /* PCI_XBIOS */
+		if (usb_found) {
+			/* Scan and get info from all the storage devices found */
+			usb_stor_curr_dev = usb_stor_scan();
+			/* it doesn't really return current device *
+			 * only 0 if it has found any store device *
+			 * -1 otherwise				   */
+			if (usb_stor_curr_dev != -1) {
+				int dev_num = usb_stor_curr_dev;
+				block_dev_desc_t *stor_dev;
+	
+				while ((stor_dev = usb_stor_get_dev(dev_num)) != NULL) {
+					int part_num = 1;
+					unsigned long part_type, part_offset, part_size;
+					/* Now find partitions in this storage device */	
+					while (!fat_register_device(stor_dev, part_num, &part_type, 
+								    &part_offset, &part_size)) {
+		 				if (!(Super(SUP_INQUIRE))) {
+							p = SuperFromUser ();
+						}
+
+						/* install partition */
+						r = install_usb_stor(dev_num, part_type, part_offset, 
+								     part_size, stor_dev->vendor, 
+								     stor_dev->revision, stor_dev->product);
+						if (r == -1)
+							printf("unable to install storage device\n");		
+
+						if (p)
+							SuperToUser(p);
+						
+						part_num++;
+					}	
+					dev_num++;
+				}
+			
+			}
+#if 0			
+			long *drvbits;
+			long value;
+
+			p = SuperFromUser();
+					
+			drvbits =  0x000004c2;
+						
+			value = *drvbits;
+			printf("\ndrvbits: %x \n", (unsigned)value);
+			SuperToUser(p);	
+#endif		
+
+		}
+		
+		if (!__mint) {	
+			printf(" Press any key");
+			Bconin(DEV_CONSOLE);
+		}	
+		Ptermres( _PgmSize, 0);	
+	}
+#endif	/* CONFIG_USB_STORAGE */
+
+	if (strncmp(argv[1], "tree", 4) == 0) {
+		argc = 2;
+		argv[1] = "start";
+		do_usb(argc, argv);
+
+		argv[1] = "inf";
+		do_usb(argc, argv);
+
+		argv[1] = "tree";
+		do_usb(argc, argv);
+	
+		argv[1] = "storage";
+		do_usb(argc, argv);
+
+//		argc = 3;
+//		argv[1] = "dev";
+//		argv[2] = "0";
+//		do_usb(argc, argv);
+
+//		argc = 2;
+		argv[1] = "stop";
+		do_usb (argc, argv);
+
+		printf(" Press any key\r\n");
+		Bconin(DEV_CONSOLE);
+	}	
+	return 0;	
+}
diff --git a/FireBee/trunk/usb/store/makefile b/FireBee/trunk/usb/store/makefile
new file mode 100644
index 0000000..2164391
--- /dev/null
+++ b/FireBee/trunk/usb/store/makefile
@@ -0,0 +1,85 @@
+
+ifeq ($(CROSS),yes)
+CC			= m68k-atari-mint-gcc
+STRIP			= m68k-atari-mint-strip
+STACK			= m68k-atari-mint-stack
+INCLUDE_GEM_PATH	= /usr/local/cross-mint/m68k-atari-mint/include
+LIB_GEM_PATH		= /usr/local/cross-mint/m68k-atari-mint/lib
+else
+CC			= gcc
+STRIP			= /usr/bin/strip
+STACK			= stack
+COMPRESS		= upx
+INCLUDE_GEM_PATH	= /usr/GEM/include
+LIB_GEM_PATH		= /usr/GEM/lib
+endif
+
+
+ifeq ($(MAKECMDGOALS), aranym)
+HCD_S			= ./host/aranym/natfeat_asm.S
+HCD_C			= ./host/aranym/aranym-hcd.c ./host/aranym/natfeat.c
+HCD_H			= ./host/aranym/nf_ops.h ./host/aranym/usbhost_nfapi.h
+PROGRAM			= stor_ara.tos
+endif
+ifeq ($(MAKECMDGOALS), netusbee)
+HCD_C			= ./host/netusbee/isp116x-hcd.c
+HCD_H			= ./host/netusbee/isp116x.h
+PROGRAM			= stor_ntu.tos
+endif
+ifeq ($(MAKECMDGOALS), ethernat)
+HCD_C			= ./host/ethernat/isp116x-hcd.c
+HCD_H			= ./host/ethernat/isp116x.h
+PROGRAM 		= stor_etn.tos
+endif
+ifeq ($(MAKECMDGOALS), ohci-pci)
+HCD_C			= ./host/ohci-pci/ohci-hcd.c ./host/ohci-pci/ltoa.c
+HCD_H			= ./host/ohci-pci/ohci.h ./host/ohci-pci/pcixbios.h
+DEFS			= -DPCI_XBIOS
+PROGRAM 		= stor_pci.tos
+endif
+
+STACKSIZE		= 64k
+OPTIMISATION		= -O -fomit-frame-pointer
+CPU			= -m68020-60
+LIB			= 
+ASFLAGS			= $(CPU)
+CFLAGS			= $(CPU) $(OPTIMISATION) -Wall -Wshadow -I$(INCLUDE_GEM_PATH) $(DEFS) -g
+LFLAGS			= -L$(LIB_GEM_PATH)
+COBJS 			= main.c udelay.c cmd_usb.c usb.c usb_mem.c usb_storage.c debug.c $(HCD_C)
+SOBJS 			= debug2.S bios.S $(HCD_S)
+HSRC			= config.h debug.h part.h scsi.h super.h usb.h usb_defs.h vars.h $(HCD_H)
+COBJECTS 		= $(COBJS:.c=.o)
+SOBJECTS 		= $(SOBJS:.S=.o)
+
+all:
+	make ethernat
+	make netusbee
+	make aranym
+	rm -f *.o
+	make ohci-pci
+	
+ethernat: $(PROGRAM)
+	
+aranym: $(PROGRAM)
+	
+netusbee: $(PROGRAM)
+
+ohci-pci: $(PROGRAM)
+	
+$(PROGRAM): $(COBJECTS) $(SOBJECTS) $(HSRC)
+	$(CC) -o $@ $(COBJECTS) $(SOBJECTS)
+
+strip:
+	$(STRIP) $(PROGRAM)
+
+stack:
+	$(STACK) -S $(STACKSIZE) $(PROGRAM)
+
+compress:
+	$(COMPRESS) $(PROGRAM)
+	
+clean:
+	rm -f *.tos *.log
+	find ./ -type f -name "*.o" -exec rm -f {} \;
+
+
diff --git a/FireBee/trunk/usb/store/part.h b/FireBee/trunk/usb/store/part.h
new file mode 100644
index 0000000..96ae888
--- /dev/null
+++ b/FireBee/trunk/usb/store/part.h
@@ -0,0 +1,88 @@
+/*
+ * (C) Copyright 2000-2004
+ * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+#ifndef _PART_H
+#define _PART_H
+
+typedef unsigned long long uint64_t;
+typedef unsigned long lbaint_t;
+
+typedef struct block_dev_desc {
+	int		if_type;	/* type of the interface */
+	int		dev;		/* device number */
+	unsigned char	part_type;	/* partition type */
+	unsigned char	target;		/* target SCSI ID */
+	unsigned char	lun;		/* target LUN */
+	unsigned char	type;		/* device type */
+	unsigned char	removable;	/* removable device */
+#ifdef CONFIG_LBA48
+	unsigned char	lba48;		/* device can use 48bit addr (ATA/ATAPI v7) */
+#endif
+	lbaint_t		lba;		/* number of blocks */
+	unsigned long	blksz;		/* block size */
+	char		vendor [40+1];	/* IDE model, SCSI Vendor */
+	char		product[20+1];	/* IDE Serial no, SCSI product */
+	char		revision[8+1];	/* firmware revision */
+	unsigned long	(*block_read)(int dev, unsigned long start, lbaint_t blkcnt, void *buffer);
+	unsigned long	(*block_write)(int dev, unsigned long start, lbaint_t blkcnt, const void *buffer);
+	void		*priv;		/* driver private struct pointer */
+}block_dev_desc_t;
+
+/* Interface types: */
+#define IF_TYPE_UNKNOWN		0
+#define IF_TYPE_IDE		1
+#define IF_TYPE_SCSI		2
+#define IF_TYPE_ATAPI		3
+#define IF_TYPE_USB		4
+#define IF_TYPE_DOC		5
+#define IF_TYPE_MMC		6
+#define IF_TYPE_SD		7
+#define IF_TYPE_SATA		8
+
+/* Part types */
+#define PART_TYPE_UNKNOWN	0x00
+#define PART_TYPE_MAC		0x01
+#define PART_TYPE_DOS		0x02
+#define PART_TYPE_ISO		0x03
+#define PART_TYPE_AMIGA		0x04
+#define PART_TYPE_EFI		0x05
+
+/*
+ * Type string for U-Boot bootable partitions
+ */
+#define BOOT_PART_TYPE	"U-Boot"	/* primary boot partition type	*/
+#define BOOT_PART_COMP	"PPCBoot"	/* PPCBoot compatibility type	*/
+
+/* device types */
+#define DEV_TYPE_UNKNOWN	0xff	/* not connected */
+#define DEV_TYPE_HARDDISK	0x00	/* harddisk */
+#define DEV_TYPE_TAPE		0x01	/* Tape */
+#define DEV_TYPE_CDROM		0x05	/* CD-ROM */
+#define DEV_TYPE_OPDISK		0x07	/* optical disk */
+
+void print_part(block_dev_desc_t *dev_desc);
+void init_part(block_dev_desc_t *dev_desc);
+void dev_print(block_dev_desc_t *dev_desc);
+
+int fat_register_device(block_dev_desc_t *dev_desc, int part_no, unsigned long *part_type, unsigned long *part_offset, unsigned long *part_size);
+
+#endif /* _PART_H */
diff --git a/FireBee/trunk/usb/store/readme.txt b/FireBee/trunk/usb/store/readme.txt
new file mode 100644
index 0000000..a1de9ad
--- /dev/null
+++ b/FireBee/trunk/usb/store/readme.txt
@@ -0,0 +1,68 @@
+This application allows you to mount an USB mass storage device though 
+the Ethernat hardware or the Aranym USB Natfeat, read or copy files from/to this device.
+It's derived from the work done by Didier Mequignon for FireTOS.
+
+This is still quite experimental so i am not responsable for any data loss
+or corruption, play with it at your own risk. Please backup your data ;-)
+
+**** Binaries ****
+
+stor_etn.tos ---> EtherNat
+stor_ara.tos ---> Aranym
+stor_ntu.tos ---> NetUSBee
+stor_pci.tos ---> PCI-OHCI
+
+Note that NetUSBee and PCI-OHCI don't work yet
+
+**** How it works *****
+
+Depending on your hardware run stor_etn.tos or stor_ara.tos application from your desktop,
+if everything goes well you can use the "install partition" option in your desktop menu to 
+access the new partitions.
+
+It has been tested it under CT060 TOS and MiNT 1.16.3.
+Teted in Aranym with MiNT 1.17.0 beta and TOS 4.04.
+
+**** Limits/Problems *****
+
+- The supported partitions are the supported partitions by the OS.
+It has been tested with FAT16 in TOS4.04, with FAT16, FAT32 and ext2 with MiNT.
+
+- There is still no handle for mounting/unmounting partitions. Neither detection for
+devices already plugged, so when you mount one device you can't unmount it.
+If you run the application several times with the same USB stick plugged, it
+will mount the device again as a new different logical partition.
+
+- It's VERY VERY slow, for now the transfer rate it's quite ridiculous. I hope
+to solve this soon. Under Aranym it can be better.
+
+- I don't think that it works together with umouse from Jan Thomas.
+
+- This is only a start don't expect too much.
+
+- Thing desktop crashes when inquiring to show info about the device.
+
+For feedback, suggestions or tips mail me at dgalvez75@gmail.com
+
+**** Histoy ****
+* 5/10/2010 (alfa 05)
+ - XHDI working (assembler version).
+ - Under MiNT FAT32 and ext2 partitions can be accesed.
+ - Introduced NetUSBee sources (not working yet)
+ - Introduced OHCI-PCI sources (to be tested)
+* 27/8/2010 (alfa 04)
+ - Start XHDI translation to C.
+ - Support for Aranym HCD.
+* 19/5/2010 (alfa 03)
+ - Killed a bug that could produce some corruption in the pun_info struct.
+* 26/4/2010 (alfa 02) 
+ - Under MiNT if the number of partitions was greater than 16, the driver wasn't installed.
+ - Wait for a key pess before retuning the desktop under TOS when driver is loaded.
+ - Resolved big bug that produced that data written/read above the first 16 MB to be corrupted.
+* 1/3/2010 (alfa 01)
+ - Initial release 
+
+David Galvez 	05/10/2010
+Version: alfa 05
+ 
+
diff --git a/FireBee/trunk/usb/store/scsi.h b/FireBee/trunk/usb/store/scsi.h
new file mode 100644
index 0000000..a42c0a3
--- /dev/null
+++ b/FireBee/trunk/usb/store/scsi.h
@@ -0,0 +1,209 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+ #ifndef _SCSI_H
+ #define _SCSI_H
+
+typedef struct SCSI_cmd_block{
+	unsigned char		cmd[16];					/* command				   */
+	unsigned char		sense_buf[64];		/* for request sense */
+	unsigned char		status;						/* SCSI Status			 */
+	unsigned char		target;						/* Target ID				 */
+	unsigned char		lun;							/* Target LUN        */
+	unsigned char		cmdlen;						/* command len				*/
+	unsigned long		datalen;					/* Total data length	*/
+	unsigned char	*	pdata;						/* pointer to data		*/
+	unsigned char		msgout[12];				/* Messge out buffer (NOT USED) */
+	unsigned char		msgin[12];				/* Message in buffer	*/
+	unsigned char		sensecmdlen;			/* Sense command len	*/
+	unsigned long		sensedatalen;			/* Sense data len			*/
+	unsigned char		sensecmd[6];			/* Sense command			*/
+	unsigned long		contr_stat;				/* Controller Status	*/
+	unsigned long		trans_bytes;			/* tranfered bytes		*/
+
+	unsigned int		priv;
+}ccb;
+
+/*-----------------------------------------------------------
+**
+**	SCSI  constants.
+**
+**-----------------------------------------------------------
+*/
+
+/*
+**	Messages
+*/
+
+#define	M_COMPLETE	(0x00)
+#define	M_EXTENDED	(0x01)
+#define	M_SAVE_DP	(0x02)
+#define	M_RESTORE_DP	(0x03)
+#define	M_DISCONNECT	(0x04)
+#define	M_ID_ERROR	(0x05)
+#define	M_ABORT		(0x06)
+#define	M_REJECT	(0x07)
+#define	M_NOOP		(0x08)
+#define	M_PARITY	(0x09)
+#define	M_LCOMPLETE	(0x0a)
+#define	M_FCOMPLETE	(0x0b)
+#define	M_RESET		(0x0c)
+#define	M_ABORT_TAG	(0x0d)
+#define	M_CLEAR_QUEUE	(0x0e)
+#define	M_INIT_REC	(0x0f)
+#define	M_REL_REC	(0x10)
+#define	M_TERMINATE	(0x11)
+#define	M_SIMPLE_TAG	(0x20)
+#define	M_HEAD_TAG	(0x21)
+#define	M_ORDERED_TAG	(0x22)
+#define	M_IGN_RESIDUE	(0x23)
+#define	M_IDENTIFY	(0x80)
+
+#define	M_X_MODIFY_DP	(0x00)
+#define	M_X_SYNC_REQ	(0x01)
+#define	M_X_WIDE_REQ	(0x03)
+#define	M_X_PPR_REQ	(0x04)
+
+
+/*
+**	Status
+*/
+
+#define	S_GOOD		(0x00)
+#define	S_CHECK_COND	(0x02)
+#define	S_COND_MET	(0x04)
+#define	S_BUSY		(0x08)
+#define	S_INT		(0x10)
+#define	S_INT_COND_MET	(0x14)
+#define	S_CONFLICT	(0x18)
+#define	S_TERMINATED	(0x20)
+#define	S_QUEUE_FULL	(0x28)
+#define	S_ILLEGAL	(0xff)
+#define	S_SENSE		(0x80)
+
+/*
+ * Sense_keys
+ */
+
+#define SENSE_NO_SENSE				0x0
+#define SENSE_RECOVERED_ERROR	0x1
+#define SENSE_NOT_READY				0x2
+#define SENSE_MEDIUM_ERROR		0x3
+#define SENSE_HARDWARE_ERROR	0x4
+#define SENSE_ILLEGAL_REQUEST	0x5
+#define SENSE_UNIT_ATTENTION	0x6
+#define SENSE_DATA_PROTECT		0x7
+#define SENSE_BLANK_CHECK			0x8
+#define SENSE_VENDOR_SPECIFIC	0x9
+#define SENSE_COPY_ABORTED		0xA
+#define SENSE_ABORTED_COMMAND	0xB
+#define SENSE_VOLUME_OVERFLOW	0xD
+#define SENSE_MISCOMPARE			0xE
+
+
+#define SCSI_CHANGE_DEF	0x40		/* Change Definition (Optional) */
+#define SCSI_COMPARE		0x39		/* Compare (O) */
+#define SCSI_COPY			0x18		/* Copy (O) */
+#define SCSI_COP_VERIFY	0x3A		/* Copy and Verify (O) */
+#define SCSI_INQUIRY		0x12		/* Inquiry (MANDATORY) */
+#define SCSI_LOG_SELECT	0x4C		/* Log Select (O) */
+#define SCSI_LOG_SENSE	0x4D		/* Log Sense (O) */
+#define SCSI_MODE_SEL6	0x15		/* Mode Select 6-byte (Device Specific) */
+#define SCSI_MODE_SEL10	0x55		/* Mode Select 10-byte (Device Specific) */
+#define SCSI_MODE_SEN6	0x1A		/* Mode Sense 6-byte (Device Specific) */
+#define SCSI_MODE_SEN10	0x5A		/* Mode Sense 10-byte (Device Specific) */
+#define SCSI_READ_BUFF	0x3C		/* Read Buffer (O) */
+#define SCSI_REQ_SENSE	0x03		/* Request Sense (MANDATORY) */
+#define SCSI_SEND_DIAG	0x1D		/* Send Diagnostic (O) */
+#define SCSI_TST_U_RDY	0x00		/* Test Unit Ready (MANDATORY) */
+#define SCSI_WRITE_BUFF	0x3B		/* Write Buffer (O) */
+/***************************************************************************
+ *			  %%% Commands Unique to Direct Access Devices %%%
+ ***************************************************************************/
+#define SCSI_COMPARE		0x39		/* Compare (O) */
+#define SCSI_FORMAT		0x04		/* Format Unit (MANDATORY) */
+#define SCSI_LCK_UN_CAC	0x36		/* Lock Unlock Cache (O) */
+#define SCSI_PREFETCH	0x34		/* Prefetch (O) */
+#define SCSI_MED_REMOVL	0x1E		/* Prevent/Allow medium Removal (O) */
+#define SCSI_READ6		0x08		/* Read 6-byte (MANDATORY) */
+#define SCSI_READ10		0x28		/* Read 10-byte (MANDATORY) */
+#define SCSI_RD_CAPAC	0x25		/* Read Capacity (MANDATORY) */
+#define SCSI_RD_DEFECT	0x37		/* Read Defect Data (O) */
+#define SCSI_READ_LONG	0x3E		/* Read Long (O) */
+#define SCSI_REASS_BLK	0x07		/* Reassign Blocks (O) */
+#define SCSI_RCV_DIAG	0x1C		/* Receive Diagnostic Results (O) */
+#define SCSI_RELEASE	0x17		/* Release Unit (MANDATORY) */
+#define SCSI_REZERO		0x01		/* Rezero Unit (O) */
+#define SCSI_SRCH_DAT_E	0x31		/* Search Data Equal (O) */
+#define SCSI_SRCH_DAT_H	0x30		/* Search Data High (O) */
+#define SCSI_SRCH_DAT_L	0x32		/* Search Data Low (O) */
+#define SCSI_SEEK6		0x0B		/* Seek 6-Byte (O) */
+#define SCSI_SEEK10		0x2B		/* Seek 10-Byte (O) */
+#define SCSI_SEND_DIAG	0x1D		/* Send Diagnostics (MANDATORY) */
+#define SCSI_SET_LIMIT	0x33		/* Set Limits (O) */
+#define SCSI_START_STP	0x1B		/* Start/Stop Unit (O) */
+#define SCSI_SYNC_CACHE	0x35		/* Synchronize Cache (O) */
+#define SCSI_VERIFY		0x2F		/* Verify (O) */
+#define SCSI_WRITE6		0x0A		/* Write 6-Byte (MANDATORY) */
+#define SCSI_WRITE10	0x2A		/* Write 10-Byte (MANDATORY) */
+#define SCSI_WRT_VERIFY	0x2E		/* Write and Verify (O) */
+#define SCSI_WRITE_LONG	0x3F		/* Write Long (O) */
+#define SCSI_WRITE_SAME	0x41		/* Write Same (O) */
+
+#if 0
+/****************************************************************************
+ * decleration of functions which have to reside in the LowLevel Part Driver
+ */
+
+void scsi_print_error(ccb *pccb);
+int scsi_exec(ccb *pccb);
+void scsi_bus_reset(void);
+void scsi_low_level_init(int busdevfunc);
+
+
+/***************************************************************************
+ * functions residing inside cmd_scsi.c
+ */
+void scsi_init(void);
+
+#endif
+
+#define SCSI_IDENTIFY					0xC0  /* not used */
+
+/* Hardware errors  */
+#define SCSI_SEL_TIME_OUT			 0x00000101	 /* Selection time out */
+#define SCSI_HNS_TIME_OUT			 0x00000102  /* Handshake */
+#define SCSI_MA_TIME_OUT			 0x00000103  /* Phase error */
+#define SCSI_UNEXP_DIS				 0x00000104  /* unexpected disconnect */
+
+#define SCSI_INT_STATE				 0x00010000  /* unknown Interrupt number is stored in 16 LSB */
+
+
+#ifndef TRUE
+#define TRUE 1
+#endif
+#ifndef FALSE
+#define FALSE 0
+#endif
+
+#endif /* _SCSI_H */
diff --git a/FireBee/trunk/usb/store/super.h b/FireBee/trunk/usb/store/super.h
new file mode 100644
index 0000000..017beb9
--- /dev/null
+++ b/FireBee/trunk/usb/store/super.h
@@ -0,0 +1,58 @@
+/*
+ * super.h 
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef _SUPER_H
+#define _SUPER_H
+
+static inline
+long SuperFromUser()
+{
+	register long retvalue __asm__("d0");
+
+	__asm__ volatile
+	(
+		"clr.l -(%%sp)\n\t"
+		"move.w #0x20,-(%%sp)\n\t"
+		"trap #1\n\t"
+		"addq.l #6,%%sp"
+		: "=r"(retvalue)				/* outputs */
+	:							/* inputs  */
+	: "d1", "d2", "a0", "a1", "a2"	/* clobbered regs */
+	);
+
+	return retvalue;
+}
+
+static inline
+void SuperToUser(long ssp)
+{
+	register long spbackup;
+
+	__asm__ volatile
+	(
+		"move.l sp,%0\n\t"
+		"move.l %1,-(%%sp)\n\t"
+		"move.w #0x20,-(%%sp)\n\t"
+		"trap #1\n\t"
+		"move.l %0,sp"
+	: "=&r"(spbackup)						/* outputs */
+	: "g"(ssp)							/* inputs  */
+	: "d0", "d1", "d2", "a0", "a1", "a2"	/* clobbered regs */
+	);
+}
+#endif /* _SUPER_H */
diff --git a/FireBee/trunk/usb/store/udelay.c b/FireBee/trunk/usb/store/udelay.c
new file mode 100644
index 0000000..d685aad
--- /dev/null
+++ b/FireBee/trunk/usb/store/udelay.c
@@ -0,0 +1,39 @@
+/* 
+ * David Galvez. 2010, e-mail: dgalvez75@gmail.com
+ * Modified from MiNTlib
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <stdio.h>
+#include <errno.h>
+#include <time.h>
+#include <mint/mintbind.h>
+
+#define USEC_PER_TICK (1000000L / ((unsigned long)CLOCKS_PER_SEC))
+#define	USEC_TO_CLOCK_TICKS(us)	((us) / USEC_PER_TICK )
+
+/*
+ * Galvez: We should use usleep POSIX function in MiNTlib, but it gives problems related with
+ * Fselect system call, until we trace where the problems come from we are using this function 
+ */
+
+void udelay(unsigned long usec)
+{
+	long stop;
+	
+	stop = _clock() + USEC_TO_CLOCK_TICKS(usec);
+	while (_clock() < stop);
+}
diff --git a/FireBee/trunk/usb/store/usb.c b/FireBee/trunk/usb/store/usb.c
new file mode 100644
index 0000000..6b3335d
--- /dev/null
+++ b/FireBee/trunk/usb/store/usb.c
@@ -0,0 +1,1422 @@
+/*
+ * Modified for Atari by David Gálvez 2010
+ * Modified for Atari by Didier Mequignon 2009
+ *
+ * Most of this source has been derived from the Linux USB
+ * project:
+ * (C) Copyright Linus Torvalds 1999
+ * (C) Copyright Johannes Erdfelt 1999-2001
+ * (C) Copyright Andreas Gal 1999
+ * (C) Copyright Gregory P. Smith 1999
+ * (C) Copyright Deti Fliegl 1999 (new USB architecture)
+ * (C) Copyright Randy Dunlap 2000
+ * (C) Copyright David Brownell 2000 (kernel hotplug, usb_device_id)
+ * (C) Copyright Yggdrasil Computing, Inc. 2000
+ *     (usb_device_id matching changes by Adam J. Richter)
+ *
+ * Adapted for U-Boot:
+ * (C) Copyright 2001 Denis Peter, MPL AG Switzerland
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+/*
+ * How it works:
+ *
+ * Since this is a bootloader, the devices will not be automatic
+ * (re)configured on hotplug, but after a restart of the USB the
+ * device should work.
+ *
+ * For each transfer (except "Interrupt") we wait for completion.
+ */
+#include "config.h" 
+#include "debug.h"
+#include "usb.h"
+
+#ifdef CONFIG_4xx
+#include <asm/4xx_pci.h>
+#endif
+
+#include <sys/types.h>
+
+#define DEBUG_USB_LOCAL 1
+#ifndef	DEBUG_USB_LOCAL
+#define	DEBUG_USB(fmt, args...)
+#endif
+
+#define USB_BUFSIZ	512
+
+void udelay(unsigned long usec);
+
+static struct usb_device usb_dev[USB_MAX_DEVICE];
+static int dev_index;
+static int running;
+static int asynch_allowed;
+static struct devrequest setup_packet;
+
+char usb_started; /* flag for the started/stopped USB status */
+
+/**********************************************************************
+ * some forward declerations...
+ */
+void usb_scan_devices(void);
+
+int usb_hub_probe(struct usb_device *dev, int ifnum);
+void usb_hub_reset(void);
+static int hub_port_reset(struct usb_device *dev, int port,
+			  unsigned short *portstat);
+
+/***********************************************************************
+ * wait_ms
+ */
+
+inline void wait_ms(unsigned long ms)
+{
+	udelay( ms * 1000);
+}
+
+/***************************************************************************
+ * Init USB Device
+ */
+
+#ifndef PCI_XBIOS
+int usb_init(void)
+#else
+int usb_init(long handle, const struct pci_device_id *ent)
+#endif
+{
+	int result;
+	
+	running = 0;
+	dev_index = 0;
+	asynch_allowed = 1;
+	usb_hub_reset();
+	
+	/* Added by Didier */
+	if(usb_mem_init())
+	{
+		usb_started = 0;
+		return -1; /* out of memoy */
+	}
+	
+	/* init low_level USB */
+	printf("USB:   ");
+#ifndef PCI_XBIOS
+	result = usb_lowlevel_init( );
+#else
+	result = usb_lowlevel_init(0,NULL);
+#endif
+	/* if lowlevel init is OK, scan the bus for devices
+	 * i.e. search HUBs and configure them */
+	if (result == 0) {
+		printf("scanning bus for devices... ");
+		running = 1;
+		usb_scan_devices();
+		usb_started = 1;
+		return 0;
+	} else {
+		printf("Error, couldn't init Lowlevel part\n");
+		usb_started = 0;
+		return -1;
+	}
+}
+
+/******************************************************************************
+ * Stop USB this stops the LowLevel Part and deregisters USB devices.
+ */
+int usb_stop(void)
+{
+	int res = 0;
+
+	if (usb_started) {
+		asynch_allowed = 1;
+		usb_started = 0;
+		usb_hub_reset();
+		res = usb_lowlevel_stop();
+	}
+	return res;
+}
+
+/*
+ * disables the asynch behaviour of the control message. This is used for data
+ * transfers that uses the exclusiv access to the control and bulk messages.
+ */
+void usb_disable_asynch(int disable)
+{
+#if 0
+/* Added by Didier */
+#ifndef CONFIG_USB_INTERRUPT_POLLING
+	if(!asynch_allowed && !disable)
+	{
+		DEBUG_USB("Enable interrupts\r\n");
+		usb_enable_interrupt(1);
+	}
+	else if(asynch_allowed && disable)
+	{
+		DEBUG_USB("Disable interrupts\r\n");
+		usb_enable_interrupt(0);
+	}
+#endif
+#endif
+	asynch_allowed = !disable;
+}
+
+
+/*-------------------------------------------------------------------
+ * Message wrappers.
+ *
+ */
+
+/*
+ * submits an Interrupt Message
+ */
+int usb_submit_int_msg(struct usb_device *dev, unsigned long pipe,
+			void *buffer, int transfer_len, int interval)
+{
+	return submit_int_msg(dev, pipe, buffer, transfer_len, interval);
+}
+
+/*
+ * submits a control message and waits for comletion (at least timeout * 1ms)
+ * If timeout is 0, we don't wait for completion (used as example to set and
+ * clear keyboards LEDs). For data transfers, (storage transfers) we don't
+ * allow control messages with 0 timeout, by previousely resetting the flag
+ * asynch_allowed (usb_disable_asynch(1)).
+ * returns the transfered length if OK or -1 if error. The transfered length
+ * and the current status are stored in the dev->act_len and dev->status.
+ */
+int usb_control_msg(struct usb_device *dev, unsigned int pipe,
+			unsigned char request, unsigned char requesttype,
+			unsigned short value, unsigned short idx,
+			void *data, unsigned short size, int timeout)
+{
+	if ((timeout == 0) && (!asynch_allowed)) {
+		/* request for a asynch control pipe is not allowed */
+		return -1;
+	}
+
+	/* set setup command */
+	setup_packet.requesttype = requesttype;
+	setup_packet.request = request;
+	setup_packet.value = __cpu_to_le16(value);
+	setup_packet.index = __cpu_to_le16(idx);
+	setup_packet.length = __cpu_to_le16(size);
+	DEBUG_USB("usb_control_msg: request: 0x%X, requesttype: 0x%X, " \
+		   "value 0x%X idx 0x%X length 0x%X\n",
+		   request, requesttype, value, idx, size);
+	dev->status = USB_ST_NOT_PROC; /*not yet processed */
+
+	submit_control_msg(dev, pipe, data, size, &setup_packet);
+	if (timeout == 0){
+		DEBUG_USB("size %d \r\n", size);
+		return (int)size;
+	}
+
+	if (dev->status != 0) {
+		/*
+		 * Let's wait a while for the timeout to elapse.
+		 * It has no real use, but it keeps the interface happy.
+		 */
+		DEBUG_USB("status %ld \n\r", dev->status);
+		wait_ms(timeout);
+		return -1;
+	}
+	return dev->act_len;
+}
+
+/*-------------------------------------------------------------------
+ * submits bulk message, and waits for completion. returns 0 if Ok or
+ * -1 if Error.
+ * synchronous behavior
+ */
+int usb_bulk_msg(struct usb_device *dev, unsigned int pipe,
+			void *data, int len, int *actual_length, int timeout)
+{
+	if (len < 0)
+		return -1;
+	dev->status = USB_ST_NOT_PROC; /*not yet processed */
+	submit_bulk_msg(dev, pipe, data, len);
+	while (timeout--) {
+		if (!((volatile unsigned long)dev->status & USB_ST_NOT_PROC))
+			break;
+		wait_ms(1);
+	}
+
+	*actual_length = dev->act_len;
+	if (dev->status == 0)
+		return 0;
+	else
+		return -1;
+}
+
+
+/*-------------------------------------------------------------------
+ * Max Packet stuff
+ */
+
+/*
+ * returns the max packet size, depending on the pipe direction and
+ * the configurations values
+ */
+int usb_maxpacket(struct usb_device *dev, unsigned long pipe)
+{
+	/* direction is out -> use emaxpacket out */
+	if ((pipe & USB_DIR_IN) == 0)
+		return dev->epmaxpacketout[((pipe>>15) & 0xf)];
+	else
+		return dev->epmaxpacketin[((pipe>>15) & 0xf)];
+}
+
+/* The routine usb_set_maxpacket_ep() is extracted from the loop of routine
+ * usb_set_maxpacket(), because the optimizer of GCC 4.x chokes on this routine
+ * when it is inlined in 1 single routine. What happens is that the register r3
+ * is used as loop-count 'i', but gets overwritten later on.
+ * This is clearly a compiler bug, but it is easier to workaround it here than
+ * to update the compiler (Occurs with at least several GCC 4.{1,2},x
+ * CodeSourcery compilers like e.g. 2007q3, 2008q1, 2008q3 lite editions on ARM)
+ */
+static void  __attribute__((noinline))
+usb_set_maxpacket_ep(struct usb_device *dev, struct usb_endpoint_descriptor *ep)
+{
+	int b;
+
+	b = ep->bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
+
+	if ((ep->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) ==
+						USB_ENDPOINT_XFER_CONTROL) {
+		/* Control => bidirectional */
+		dev->epmaxpacketout[b] = ep->wMaxPacketSize;
+		dev->epmaxpacketin[b] = ep->wMaxPacketSize;
+		DEBUG_USB("##Control EP epmaxpacketout/in[%d] = %d\n",
+			   b, dev->epmaxpacketin[b]);
+	} else {
+		if ((ep->bEndpointAddress & 0x80) == 0) {
+			/* OUT Endpoint */
+			if (ep->wMaxPacketSize > dev->epmaxpacketout[b]) {
+				dev->epmaxpacketout[b] = ep->wMaxPacketSize;
+				DEBUG_USB("##EP epmaxpacketout[%d] = %d\n",
+					   b, dev->epmaxpacketout[b]);
+			}
+		} else {
+			/* IN Endpoint */
+			if (ep->wMaxPacketSize > dev->epmaxpacketin[b]) {
+				dev->epmaxpacketin[b] = ep->wMaxPacketSize;
+				DEBUG_USB("##EP epmaxpacketin[%d] = %d\n",
+					   b, dev->epmaxpacketin[b]);
+			}
+		} /* if out */
+	} /* if control */
+}
+
+/*
+ * set the max packed value of all endpoints in the given configuration
+ */
+int usb_set_maxpacket(struct usb_device *dev)
+{
+	int i, ii;
+
+	for (i = 0; i < dev->config.bNumInterfaces; i++)
+		for (ii = 0; ii < dev->config.if_desc[i].bNumEndpoints; ii++)
+			usb_set_maxpacket_ep(dev,
+					  &dev->config.if_desc[i].ep_desc[ii]);
+
+	return 0;
+}
+
+/*******************************************************************************
+ * Parse the config, located in buffer, and fills the dev->config structure.
+ * Note that all little/big endian swapping are done automatically.
+ */
+int usb_parse_config(struct usb_device *dev, unsigned char *buffer, int cfgno)
+{
+	struct usb_descriptor_header *head;
+	int idx, ifno, epno, curr_if_num;
+	int i;
+	unsigned char *ch;
+
+	ifno = -1;
+	epno = -1;
+	curr_if_num = -1;
+
+	dev->configno = cfgno;
+	head = (struct usb_descriptor_header *) &buffer[0];
+	if (head->bDescriptorType != USB_DT_CONFIG) {
+		printf(" ERROR: NOT USB_CONFIG_DESC %x\n",
+			head->bDescriptorType);
+		return -1;
+	}
+	memcpy(&dev->config, buffer, buffer[0]);
+	__le16_to_cpus(&(dev->config.wTotalLength));
+	dev->config.no_of_if = 0;
+
+	idx = dev->config.bLength;
+	/* Ok the first entry must be a configuration entry,
+	 * now process the others */
+	head = (struct usb_descriptor_header *) &buffer[idx];
+	while (idx + 1 < dev->config.wTotalLength) {
+		switch (head->bDescriptorType) {
+		case USB_DT_INTERFACE:
+			if (((struct usb_interface_descriptor *) \
+			     &buffer[idx])->bInterfaceNumber != curr_if_num) {
+				/* this is a new interface, copy new desc */
+				ifno = dev->config.no_of_if;
+				dev->config.no_of_if++;
+				memcpy(&dev->config.if_desc[ifno],
+					&buffer[idx], buffer[idx]);
+				dev->config.if_desc[ifno].no_of_ep = 0;
+				dev->config.if_desc[ifno].num_altsetting = 1;
+				curr_if_num =
+				     dev->config.if_desc[ifno].bInterfaceNumber;
+			} else {
+				/* found alternate setting for the interface */
+				dev->config.if_desc[ifno].num_altsetting++;
+			}
+			break;
+		case USB_DT_ENDPOINT:
+			epno = dev->config.if_desc[ifno].no_of_ep;
+			/* found an endpoint */
+			dev->config.if_desc[ifno].no_of_ep++;
+			memcpy(&dev->config.if_desc[ifno].ep_desc[epno],
+				&buffer[idx], buffer[idx]);
+			__le16_to_cpus(&(dev->config.if_desc[ifno].ep_desc[epno].\
+							       wMaxPacketSize));
+			DEBUG_USB("if %d, ep %d\n", ifno, epno);
+			break;
+		default:
+			if (head->bLength == 0)
+				return 1;
+
+			DEBUG_USB("unknown Description Type : %x\n",
+				   head->bDescriptorType);
+
+			{
+				ch = (unsigned char *)head;
+				for (i = 0; i < head->bLength; i++)
+					DEBUG_USB("%02X ", *ch++);
+				DEBUG_USB("\n\n\n");
+			}
+			break;
+		}
+		idx += head->bLength;
+		head = (struct usb_descriptor_header *)&buffer[idx];
+	}
+	return 1;
+}
+
+/***********************************************************************
+ * Clears an endpoint
+ * endp: endpoint number in bits 0-3;
+ * direction flag in bit 7 (1 = IN, 0 = OUT)
+ */
+int usb_clear_halt(struct usb_device *dev, int pipe)
+{
+	int result;
+	int endp = usb_pipeendpoint(pipe)|(usb_pipein(pipe)<<7);
+
+	result = usb_control_msg(dev, usb_sndctrlpipe(dev, 0),
+				 USB_REQ_CLEAR_FEATURE, USB_RECIP_ENDPOINT, 0,
+				 endp, NULL, 0, USB_CNTL_TIMEOUT * 3);
+
+	/* don't clear if failed */
+	if (result < 0)
+		return result;
+
+	/*
+	 * NOTE: we do not get status and verify reset was successful
+	 * as some devices are reported to lock up upon this check..
+	 */
+
+	usb_endpoint_running(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe));
+
+	/* toggle is reset on clear */
+	usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 0);
+	return 0;
+}
+
+
+/**********************************************************************
+ * get_descriptor type
+ */
+int usb_get_descriptor(struct usb_device *dev, unsigned char type,
+			unsigned char idx, void *buf, int size)
+{
+	int res;
+DEBUG_USB( "%s\n",__FUNCTION__);
+	res = usb_control_msg(dev, usb_rcvctrlpipe(dev, 0),
+			USB_REQ_GET_DESCRIPTOR, USB_DIR_IN,
+			(type << 8) + idx, 0,
+			buf, size, USB_CNTL_TIMEOUT);
+	return res;
+}
+
+/**********************************************************************
+ * gets configuration cfgno and store it in the buffer
+ */
+int usb_get_configuration_no(struct usb_device *dev,
+			     unsigned char *buffer, int cfgno)
+{
+	int result;
+	unsigned int tmp;
+	struct usb_config_descriptor *config;
+
+
+	config = (struct usb_config_descriptor *)&buffer[0];
+	result = usb_get_descriptor(dev, USB_DT_CONFIG, cfgno, buffer, 9);
+	if (result < 9) {
+		if (result < 0)
+			printf("unable to get descriptor, error %lX\n",
+				dev->status);
+		else
+			printf("config descriptor too short " \
+				"(expected %i, got %i)\n", 9, result);
+		return -1;
+	}
+	tmp = __le16_to_cpu(config->wTotalLength);
+
+	if (tmp > USB_BUFSIZ) {
+		DEBUG_USB("usb_get_configuration_no: failed to get " \
+			   "descriptor - too long: %d\n", tmp);
+		return -1;
+	}
+
+	result = usb_get_descriptor(dev, USB_DT_CONFIG, cfgno, buffer, tmp);
+	DEBUG_USB("get_conf_no %d Result %d, wLength %d\n",
+		   cfgno, result, tmp);
+	return result;
+}
+
+/********************************************************************
+ * set address of a device to the value in dev->devnum.
+ * This can only be done by addressing the device via the default address (0)
+ */
+int usb_set_address(struct usb_device *dev)
+{
+	int res;
+
+	DEBUG_USB("set address %d\n", dev->devnum);
+	res = usb_control_msg(dev, usb_snddefctrl(dev),
+				USB_REQ_SET_ADDRESS, 0,
+				(dev->devnum), 0,
+				NULL, 0, USB_CNTL_TIMEOUT);
+	return res;
+}
+
+/********************************************************************
+ * set interface number to interface
+ */
+int usb_set_interface(struct usb_device *dev, int interface, int alternate)
+{
+	struct usb_interface_descriptor *if_face = NULL;
+	int ret, i;
+
+	for (i = 0; i < dev->config.bNumInterfaces; i++) {
+		if (dev->config.if_desc[i].bInterfaceNumber == interface) {
+			if_face = &dev->config.if_desc[i];
+			break;
+		}
+	}
+	if (!if_face) {
+		printf("selecting invalid interface %d", interface);
+		return -1;
+	}
+	/*
+	 * We should return now for devices with only one alternate setting.
+	 * According to 9.4.10 of the Universal Serial Bus Specification
+	 * Revision 2.0 such devices can return with a STALL. This results in
+	 * some USB sticks timeouting during initialization and then being
+	 * unusable in U-Boot.
+	 */
+	if (if_face->num_altsetting == 1)
+		return 0;
+
+	ret = usb_control_msg(dev, usb_sndctrlpipe(dev, 0),
+				USB_REQ_SET_INTERFACE, USB_RECIP_INTERFACE,
+				alternate, interface, NULL, 0,
+				USB_CNTL_TIMEOUT * 5);
+	if (ret < 0)
+		return ret;
+
+	return 0;
+}
+
+/********************************************************************
+ * set configuration number to configuration
+ */
+int usb_set_configuration(struct usb_device *dev, int configuration)
+{
+	int res;
+	DEBUG_USB("set configuration %d\n", configuration);
+	/* set setup command */
+	res = usb_control_msg(dev, usb_sndctrlpipe(dev, 0),
+				USB_REQ_SET_CONFIGURATION, 0,
+				configuration, 0,
+				NULL, 0, USB_CNTL_TIMEOUT);
+	if (res == 0) {
+		dev->toggle[0] = 0;
+		dev->toggle[1] = 0;
+		return 0;
+	} else
+		return -1;
+}
+
+/********************************************************************
+ * set protocol to protocol
+ */
+int usb_set_protocol(struct usb_device *dev, int ifnum, int protocol)
+{
+	return usb_control_msg(dev, usb_sndctrlpipe(dev, 0),
+		USB_REQ_SET_PROTOCOL, USB_TYPE_CLASS | USB_RECIP_INTERFACE,
+		protocol, ifnum, NULL, 0, USB_CNTL_TIMEOUT);
+}
+
+/********************************************************************
+ * set idle
+ */
+int usb_set_idle(struct usb_device *dev, int ifnum, int duration, int report_id)
+{
+	return usb_control_msg(dev, usb_sndctrlpipe(dev, 0),
+		USB_REQ_SET_IDLE, USB_TYPE_CLASS | USB_RECIP_INTERFACE,
+		(duration << 8) | report_id, ifnum, NULL, 0, USB_CNTL_TIMEOUT);
+}
+
+/********************************************************************
+ * get report
+ */
+int usb_get_report(struct usb_device *dev, int ifnum, unsigned char type,
+		   unsigned char id, void *buf, int size)
+{
+	return usb_control_msg(dev, usb_rcvctrlpipe(dev, 0),
+			USB_REQ_GET_REPORT,
+			USB_DIR_IN | USB_TYPE_CLASS | USB_RECIP_INTERFACE,
+			(type << 8) + id, ifnum, buf, size, USB_CNTL_TIMEOUT);
+}
+
+/********************************************************************
+ * get class descriptor
+ */
+int usb_get_class_descriptor(struct usb_device *dev, int ifnum,
+		unsigned char type, unsigned char id, void *buf, int size)
+{
+	return usb_control_msg(dev, usb_rcvctrlpipe(dev, 0),
+		USB_REQ_GET_DESCRIPTOR, USB_RECIP_INTERFACE | USB_DIR_IN,
+		(type << 8) + id, ifnum, buf, size, USB_CNTL_TIMEOUT);
+}
+
+/********************************************************************
+ * get string index in buffer
+ */
+int usb_get_string(struct usb_device *dev, unsigned short langid,
+		   unsigned char idx, void *buf, int size)
+{
+	int i;
+	int result;
+
+	for (i = 0; i < 3; ++i) {
+		/* some devices are flaky */
+		result = usb_control_msg(dev, usb_rcvctrlpipe(dev, 0),
+			USB_REQ_GET_DESCRIPTOR, USB_DIR_IN,
+			(USB_DT_STRING << 8) + idx, langid, buf, size,
+			USB_CNTL_TIMEOUT);
+
+		if (result > 0)
+			break;
+	}
+
+	return result;
+}
+
+
+static void usb_try_string_workarounds(unsigned char *buf, int *length)
+{
+	int newlength, oldlength = *length;
+
+	for (newlength = 2; newlength + 1 < oldlength; newlength += 2)
+	{
+		char c = buf[newlength];
+		if ((c < ' ') || (c >= 127) || buf[newlength + 1])
+			break;
+	}
+	if (newlength > 2) {
+		buf[0] = newlength;
+		*length = newlength;
+	}
+}
+
+
+static int usb_string_sub(struct usb_device *dev, unsigned int langid,
+		unsigned int idx, unsigned char *buf)
+{
+	int rc;
+
+	/* Try to read the string descriptor by asking for the maximum
+	 * possible number of bytes */
+	rc = usb_get_string(dev, langid, idx, buf, 255);
+
+	/* If that failed try to read the descriptor length, then
+	 * ask for just that many bytes */
+	if (rc < 2) {
+		rc = usb_get_string(dev, langid, idx, buf, 2);
+		if (rc == 2)
+			rc = usb_get_string(dev, langid, idx, buf, buf[0]);
+	}
+
+	if (rc >= 2) {
+		if (!buf[0] && !buf[1])
+			usb_try_string_workarounds(buf, &rc);
+
+		/* There might be extra junk at the end of the descriptor */
+		if (buf[0] < rc)
+			rc = buf[0];
+
+		rc = rc - (rc & 1); /* force a multiple of two */
+	}
+
+	if (rc < 2)
+		rc = -1;
+
+	return rc;
+}
+
+
+/********************************************************************
+ * usb_string:
+ * Get string index and translate it to ascii.
+ * returns string length (> 0) or error (< 0)
+ */
+int usb_string(struct usb_device *dev, int idx, char *buf, size_t size)
+{
+	unsigned char mybuf[USB_BUFSIZ];
+	unsigned char *tbuf;
+	int err;
+	unsigned int u, idx2;
+
+	if (size <= 0 || !buf || !idx)
+		return -1;
+	buf[0] = 0;
+	tbuf = &mybuf[0];
+
+	/* get langid for strings if it's not yet known */
+	if (!dev->have_langid) {
+		err = usb_string_sub(dev, 0, 0, tbuf);
+		if (err < 0) {
+			DEBUG_USB("error getting string descriptor 0 " \
+				   "(error=%lx)\n", dev->status);
+			return -1;
+		} else if (tbuf[0] < 4) {
+			DEBUG_USB("string descriptor 0 too short\n");
+			return -1;
+		} else {
+			dev->have_langid = -1;
+			dev->string_langid = tbuf[2] | (tbuf[3] << 8);
+				/* always use the first langid listed */
+			DEBUG_USB("USB device number %d default " \
+				   "language ID 0x%x\n",
+				   dev->devnum, dev->string_langid);
+		}
+	}
+
+	err = usb_string_sub(dev, dev->string_langid, idx, tbuf);
+	if (err < 0)
+		return err;
+
+	size--;		/* leave room for trailing NULL char in output buffer */
+	for (idx2 = 0, u = 2; u < err; u += 2) {
+		if (idx2 >= size)
+			break;
+		if (tbuf[u+1])			/* high byte */
+			buf[idx2++] = '?';  /* non-ASCII character */
+		else
+			buf[idx2++] = tbuf[u];
+	}
+	buf[idx2] = 0;
+	err = idx2;
+	return err;
+}
+
+
+/********************************************************************
+ * USB device handling:
+ * the USB device are static allocated [USB_MAX_DEVICE].
+ */
+
+
+/* returns a pointer to the device with the index [idx].
+ * if the device is not assigned (dev->devnum==-1) returns NULL
+ */
+struct usb_device *usb_get_dev_index(int idx)
+{
+	if (usb_dev[idx].devnum == -1)
+		return NULL;
+	else
+		return &usb_dev[idx];
+}
+
+
+/* returns a pointer of a new device structure or NULL, if
+ * no device struct is available
+ */
+struct usb_device *usb_alloc_new_device(void)
+{
+	int i;
+	DEBUG_USB("New Device %d\n", dev_index);
+	if (dev_index == USB_MAX_DEVICE) {
+		printf("ERROR, too many USB Devices, max=%d\n", USB_MAX_DEVICE);
+		return NULL;
+	}
+	/* default Address is 0, real addresses start with 1 */
+	usb_dev[dev_index].devnum = dev_index + 1;
+	usb_dev[dev_index].maxchild = 0;
+	for (i = 0; i < USB_MAXCHILDREN; i++)
+		usb_dev[dev_index].children[i] = NULL;
+	usb_dev[dev_index].parent = NULL;
+	dev_index++;
+	return &usb_dev[dev_index - 1];
+}
+
+
+/*
+ * By the time we get here, the device has gotten a new device ID
+ * and is in the default state. We need to identify the thing and
+ * get the ball rolling..
+ *
+ * Returns 0 for success, != 0 for error.
+ */
+int usb_new_device(struct usb_device *dev)
+{
+	int addr, err;
+	int tmp;
+	unsigned char tmpbuf[USB_BUFSIZ];
+ 
+ 	/* We still haven't set the Address yet */
+ 	addr = dev->devnum;
+ 	dev->devnum = 0;
+	
+
+#ifdef CONFIG_LEGACY_USB_INIT_SEQ
+	/* this is the old and known way of initializing devices, it is
+	 * different than what Windows and Linux are doing. Windows and Linux
+	 * both retrieve 64 bytes while reading the device descriptor
+	 * Several USB stick devices report ERR: CTL_TIMEOUT, caused by an
+	 * invalid header while reading 8 bytes as device descriptor. */
+	dev->descriptor.bMaxPacketSize0 = 8;	    /* Start off at 8 bytes  */
+	dev->maxpacketsize = PACKET_SIZE_8;
+	dev->epmaxpacketin[0] = 8;
+	dev->epmaxpacketout[0] = 8;
+
+	err = usb_get_descriptor(dev, USB_DT_DEVICE, 0, &dev->descriptor, 8);
+	if (err < 8) {
+		printf("\n      USB device not responding, " \
+		       "giving up (status=%lX)\n", dev->status);
+		return 1;
+	}
+
+#else	
+	/* This is a Windows scheme of initialization sequence, with double
+	 * reset of the device (Linux uses the same sequence)
+	 * Some equipment is said to work only with such init sequence; this
+	 * patch is based on the work by Alan Stern:
+	 * http://sourceforge.net/mailarchive/forum.php?
+	 * thread_id=5729457&forum_id=5398
+	 */
+
+	struct usb_device_descriptor *desc;
+	int port = -1;
+	struct usb_device *parent = dev->parent;
+	unsigned short portstatus;
+
+	/* send 64-byte GET-DEVICE-DESCRIPTOR request.  Since the descriptor is
+	 * only 18 bytes long, this will terminate with a short packet.  But if
+	 * the maxpacket size is 8 or 16 the device may be waiting to transmit
+	 * some more, or keeps on retransmitting the 8 byte header. */
+
+	desc = (struct usb_device_descriptor *)tmpbuf;
+	dev->descriptor.bMaxPacketSize0 = 64;	    /* Start off at 64 bytes  */
+	/* Default to 64 byte max packet size */
+	dev->maxpacketsize = PACKET_SIZE_64;
+	dev->epmaxpacketin[0] = 64;
+	dev->epmaxpacketout[0] = 64;
+
+	err = usb_get_descriptor(dev, USB_DT_DEVICE, 0, desc, 64);
+	if (err < 0) {
+		DEBUG_USB("usb_new_device: usb_get_descriptor() failed\n");
+		return 1;
+	}
+
+	dev->descriptor.bMaxPacketSize0 = desc->bMaxPacketSize0;
+
+	/* find the port number we're at */
+	if (parent) {
+		int j;
+
+		for (j = 0; j < parent->maxchild; j++) {
+			if (parent->children[j] == dev) {
+				port = j;
+				break;
+			}
+		}
+		if (port < 0) {
+			printf("usb_new_device:cannot locate device's port.\n");
+			return 1;
+		}
+
+		/* reset the port for the second time */
+		err = hub_port_reset(dev->parent, port, &portstatus);
+		if (err < 0) {
+			printf("\n     Couldn't reset port %i\n", port);
+			return 1;
+		}
+	}
+#endif
+
+	dev->epmaxpacketin[0] = dev->descriptor.bMaxPacketSize0;
+	dev->epmaxpacketout[0] = dev->descriptor.bMaxPacketSize0;
+	switch (dev->descriptor.bMaxPacketSize0) {
+	case 8:
+		dev->maxpacketsize  = PACKET_SIZE_8;
+		break;
+	case 16:
+		dev->maxpacketsize = PACKET_SIZE_16;
+		break;
+	case 32:
+		dev->maxpacketsize = PACKET_SIZE_32;
+		break;
+	case 64:
+		dev->maxpacketsize = PACKET_SIZE_64;
+		break;
+	}
+	dev->devnum = addr;
+
+	err = usb_set_address(dev); /* set address */
+
+	if (err < 0) {
+		printf("\n      USB device not accepting new address " \
+			"(error=%lX)\n", dev->status);
+		return 1;
+	}
+
+	wait_ms(10);	/* Let the SET_ADDRESS settle */
+
+	tmp = sizeof(dev->descriptor);
+
+	err = usb_get_descriptor(dev, USB_DT_DEVICE, 0,
+				 &dev->descriptor, sizeof(dev->descriptor));
+	if (err < tmp) {
+		if (err < 0)
+			printf("unable to get device descriptor (error=%d)\n",
+			       err);
+		else
+			printf("USB device descriptor short read " \
+				"(expected %i, got %i)\n", tmp, err);
+		return 1;
+	}
+	/* correct le values */
+	__le16_to_cpus(&dev->descriptor.bcdUSB);
+	__le16_to_cpus(&dev->descriptor.idVendor);
+	__le16_to_cpus(&dev->descriptor.idProduct);
+	__le16_to_cpus(&dev->descriptor.bcdDevice);
+	/* only support for one config for now */
+	usb_get_configuration_no(dev, &tmpbuf[0], 0);
+	usb_parse_config(dev, &tmpbuf[0], 0);
+	usb_set_maxpacket(dev);
+	/* we set the default configuration here */
+	if (usb_set_configuration(dev, dev->config.bConfigurationValue)) {
+		printf("failed to set default configuration " \
+			"len %d, status %lX\n", dev->act_len, dev->status);
+		return -1;
+	}
+	DEBUG_USB("new device strings: Mfr=%d, Product=%d, SerialNumber=%d\n",
+		   dev->descriptor.iManufacturer, dev->descriptor.iProduct,
+		   dev->descriptor.iSerialNumber);
+	memset(dev->mf, 0, sizeof(dev->mf));
+	memset(dev->prod, 0, sizeof(dev->prod));
+	memset(dev->serial, 0, sizeof(dev->serial));
+	if (dev->descriptor.iManufacturer)
+		usb_string(dev, dev->descriptor.iManufacturer,
+			   dev->mf, sizeof(dev->mf));
+	if (dev->descriptor.iProduct)
+		usb_string(dev, dev->descriptor.iProduct,
+			   dev->prod, sizeof(dev->prod));
+	if (dev->descriptor.iSerialNumber)
+		usb_string(dev, dev->descriptor.iSerialNumber,
+			   dev->serial, sizeof(dev->serial));
+	DEBUG_USB("Manufacturer %s\n", dev->mf);
+	DEBUG_USB("Product      %s\n", dev->prod);
+	DEBUG_USB("SerialNumber %s\n", dev->serial);
+	/* now probe if the device is a hub */
+	usb_hub_probe(dev, 0);
+	return 0;
+}
+
+
+/* build device Tree  */
+void usb_scan_devices(void)
+{
+	int i;
+	struct usb_device *dev;
+
+	/* first make all devices unknown */
+	for (i = 0; i < USB_MAX_DEVICE; i++) {
+		memset(&usb_dev[i], 0, sizeof(struct usb_device));
+		usb_dev[i].devnum = -1;
+	}
+	dev_index = 0;
+	/* device 0 is always present (root hub, so let it analyze) */
+	dev = usb_alloc_new_device();
+	if (usb_new_device(dev))
+		printf("No USB Device found\n");
+	else
+		printf("%d USB Device(s) found\n", dev_index);
+	/* insert "driver" if possible */
+#ifdef CONFIG_USB_KEYBOARD
+	drv_usb_kbd_init();
+	DEBUG_USB("scan end\n");
+#endif
+
+#ifdef CONFIG_USB_MOUSE
+	drv_usb_mouse_init();
+	DEBUG_USB("scan end\n");
+#endif
+}
+
+
+/****************************************************************************
+ * HUB "Driver"
+ * Probes device for being a hub and configurate it
+ */
+
+static struct usb_hub_device hub_dev[USB_MAX_HUB];
+static int usb_hub_index;
+
+
+int usb_get_hub_descriptor(struct usb_device *dev, void *data, int size)
+{
+	return usb_control_msg(dev, usb_rcvctrlpipe(dev, 0),
+		USB_REQ_GET_DESCRIPTOR, USB_DIR_IN | USB_RT_HUB,
+		USB_DT_HUB << 8, 0, data, size, USB_CNTL_TIMEOUT);
+}
+
+int usb_clear_hub_feature(struct usb_device *dev, int feature)
+{
+	return usb_control_msg(dev, usb_sndctrlpipe(dev, 0),
+				USB_REQ_CLEAR_FEATURE, USB_RT_HUB, feature,
+				0, NULL, 0, USB_CNTL_TIMEOUT);
+}
+
+int usb_clear_port_feature(struct usb_device *dev, int port, int feature)
+{
+	return usb_control_msg(dev, usb_sndctrlpipe(dev, 0),
+				USB_REQ_CLEAR_FEATURE, USB_RT_PORT, feature,
+				port, NULL, 0, USB_CNTL_TIMEOUT);
+}
+
+int usb_set_port_feature(struct usb_device *dev, int port, int feature)
+{
+	return usb_control_msg(dev, usb_sndctrlpipe(dev, 0),
+				USB_REQ_SET_FEATURE, USB_RT_PORT, feature,
+				port, NULL, 0, USB_CNTL_TIMEOUT);
+}
+
+int usb_get_hub_status(struct usb_device *dev, void *data)
+{
+	return usb_control_msg(dev, usb_rcvctrlpipe(dev, 0),
+			USB_REQ_GET_STATUS, USB_DIR_IN | USB_RT_HUB, 0, 0,
+			data, sizeof(struct usb_hub_status), USB_CNTL_TIMEOUT);
+}
+
+int usb_get_port_status(struct usb_device *dev, int port, void *data)
+{
+	return usb_control_msg(dev, usb_rcvctrlpipe(dev, 0),
+			USB_REQ_GET_STATUS, USB_DIR_IN | USB_RT_PORT, 0, port,
+			data, sizeof(struct usb_hub_status), USB_CNTL_TIMEOUT);
+}
+
+
+static void usb_hub_power_on(struct usb_hub_device *hub)
+{
+	int i;
+	struct usb_device *dev;
+
+	dev = hub->pusb_dev;
+	/* Enable power to the ports */
+	DEBUG_HUB("enabling power on all ports\n");
+	for (i = 0; i < dev->maxchild; i++) {
+		usb_set_port_feature(dev, i + 1, USB_PORT_FEAT_POWER);
+		DEBUG_HUB("port %d returns %lX\n", i + 1, dev->status);
+		wait_ms(hub->desc.bPwrOn2PwrGood * 2);
+	}
+}
+
+void usb_hub_reset(void)
+{
+	usb_hub_index = 0;
+}
+
+struct usb_hub_device *usb_hub_allocate(void)
+{
+	if (usb_hub_index < USB_MAX_HUB)
+		return &hub_dev[usb_hub_index++];
+
+	printf("ERROR: USB_MAX_HUB (%d) reached\n", USB_MAX_HUB);
+	return NULL;
+}
+
+#define MAX_TRIES 5
+
+static inline char *portspeed(int portstatus)
+{
+	if (portstatus & (1 << USB_PORT_FEAT_HIGHSPEED))
+		return "480 Mb/s";
+	else if (portstatus & (1 << USB_PORT_FEAT_LOWSPEED))
+		return "1.5 Mb/s";
+	else
+		return "12 Mb/s";
+}
+
+static int hub_port_reset(struct usb_device *dev, int port,
+			unsigned short *portstat)
+{
+	int tries;
+	struct usb_port_status portsts;
+	unsigned short portstatus, portchange;
+
+	DEBUG_HUB("hub_port_reset: resetting port %d...\n", port);
+	for (tries = 0; tries < MAX_TRIES; tries++) {
+
+		usb_set_port_feature(dev, port + 1, USB_PORT_FEAT_RESET);
+		wait_ms(200);
+
+		if (usb_get_port_status(dev, port + 1, &portsts) < 0) {
+			DEBUG_HUB("get_port_status failed status %lX\n",
+					dev->status);
+			return -1;
+		}
+		portstatus = __le16_to_cpu(portsts.wPortStatus);
+		portchange = __le16_to_cpu(portsts.wPortChange);
+
+		DEBUG_HUB("portstatus %x, change %x, %s\n",
+				portstatus, portchange,
+				portspeed(portstatus));
+
+		DEBUG_HUB("STAT_C_CONNECTION = %d STAT_CONNECTION = %d" \
+			       "  USB_PORT_STAT_ENABLE %d\n",
+			(portchange & USB_PORT_STAT_C_CONNECTION) ? 1 : 0,
+			(portstatus & USB_PORT_STAT_CONNECTION) ? 1 : 0,
+			(portstatus & USB_PORT_STAT_ENABLE) ? 1 : 0);
+
+		if ((portchange & USB_PORT_STAT_C_CONNECTION) ||
+		    !(portstatus & USB_PORT_STAT_CONNECTION))
+			return -1;
+
+		if (portstatus & USB_PORT_STAT_ENABLE)
+			break;
+
+		wait_ms(200);
+	}
+
+	if (tries == MAX_TRIES) {
+		DEBUG_HUB("Cannot enable port %i after %i retries, " \
+				"disabling port.\n", port + 1, MAX_TRIES);
+		DEBUG_HUB("Maybe the USB cable is bad?\n");
+		return -1;
+	}
+
+	usb_clear_port_feature(dev, port + 1, USB_PORT_FEAT_C_RESET);
+	*portstat = portstatus;
+	return 0;
+}
+
+
+void usb_hub_port_connect_change(struct usb_device *dev, int port)
+{
+	struct usb_device *usb;
+	struct usb_port_status portsts;
+	unsigned short portstatus, portchange;
+
+	/* Check status */
+	if (usb_get_port_status(dev, port + 1, &portsts) < 0) {
+		DEBUG_HUB("get_port_status failed\n");
+		return;
+	}
+
+	portstatus = __le16_to_cpu(portsts.wPortStatus);
+	portchange = __le16_to_cpu(portsts.wPortChange);
+	DEBUG_HUB("portstatus %x, change %x, %s\n",
+			portstatus, portchange, portspeed(portstatus));
+
+	/* Clear the connection change status */
+	usb_clear_port_feature(dev, port + 1, USB_PORT_FEAT_C_CONNECTION);
+
+	/* Disconnect any existing devices under this port */
+	if (((!(portstatus & USB_PORT_STAT_CONNECTION)) &&
+	     (!(portstatus & USB_PORT_STAT_ENABLE))) || (dev->children[port])) {
+		DEBUG_HUB("usb_disconnect(&hub->children[port]);\n");
+		/* Return now if nothing is connected */
+		if (!(portstatus & USB_PORT_STAT_CONNECTION))
+			return;
+	}
+	wait_ms(200);
+
+	/* Reset the port */
+	if (hub_port_reset(dev, port, &portstatus) < 0) {
+		printf("cannot reset port %i!?\n", port + 1);
+		return;
+	}
+
+	wait_ms(200);
+
+	/* Allocate a new device struct for it */
+	usb = usb_alloc_new_device();
+	if (portstatus & USB_PORT_STAT_HIGH_SPEED)
+		usb->speed = USB_SPEED_HIGH;
+	else if (portstatus & USB_PORT_STAT_LOW_SPEED)
+		usb->speed = USB_SPEED_LOW;
+	else
+		usb->speed = USB_SPEED_FULL;
+
+	dev->children[port] = usb;
+	usb->parent = dev;
+	/* Run it through the hoops (find a driver, etc) */
+	if (usb_new_device(usb)) {
+		/* Woops, disable the port */
+		DEBUG_HUB("hub: disabling port %d\n", port + 1);
+		usb_clear_port_feature(dev, port + 1, USB_PORT_FEAT_ENABLE);
+	}
+}
+
+
+int usb_hub_configure(struct usb_device *dev)
+{
+	unsigned char buffer[USB_BUFSIZ], *bitmap;
+	struct usb_hub_descriptor *descriptor;
+	struct usb_hub_status *hubsts;
+	int i;
+	struct usb_hub_device *hub;
+
+	/* "allocate" Hub device */
+	hub = usb_hub_allocate();
+	if (hub == NULL)
+		return -1;
+	hub->pusb_dev = dev;
+	/* Get the the hub descriptor */
+	if (usb_get_hub_descriptor(dev, buffer, 4) < 0) {
+		DEBUG_HUB("usb_hub_configure: failed to get hub " \
+				   "descriptor, giving up %lX\n", dev->status);
+		return -1;
+	}
+	descriptor = (struct usb_hub_descriptor *)buffer;
+
+	/* silence compiler warning if USB_BUFSIZ is > 256 [= sizeof(char)] */
+	i = descriptor->bLength;
+	if (i > USB_BUFSIZ) {
+		DEBUG_HUB("usb_hub_configure: failed to get hub " \
+				"descriptor - too long: %d\n",
+				descriptor->bLength);
+		return -1;
+	}
+
+	if (usb_get_hub_descriptor(dev, buffer, descriptor->bLength) < 0) {
+		DEBUG_HUB("usb_hub_configure: failed to get hub " \
+				"descriptor 2nd giving up %lX\n", dev->status);
+		return -1;
+	}
+	memcpy((unsigned char *)&hub->desc, buffer, descriptor->bLength);
+	/* adjust 16bit values */
+	hub->desc.wHubCharacteristics =
+				__le16_to_cpu(descriptor->wHubCharacteristics);
+
+	/* set the bitmap */
+	bitmap = (unsigned char *)&hub->desc.DeviceRemovable[0];
+	/* devices not removable by default */
+	memset(bitmap, 0xff, (USB_MAXCHILDREN+1+7)/8);
+	bitmap = (unsigned char *)&hub->desc.PortPowerCtrlMask[0];
+	memset(bitmap, 0xff, (USB_MAXCHILDREN+1+7)/8); /* PowerMask = 1B */
+
+	for (i = 0; i < ((hub->desc.bNbrPorts + 1 + 7)/8); i++)
+		hub->desc.DeviceRemovable[i] = descriptor->DeviceRemovable[i];
+
+	for (i = 0; i < ((hub->desc.bNbrPorts + 1 + 7)/8); i++)
+		hub->desc.DeviceRemovable[i] = descriptor->PortPowerCtrlMask[i];
+
+	dev->maxchild = descriptor->bNbrPorts;
+	DEBUG_HUB("%d ports detected\n", dev->maxchild);
+
+	switch (hub->desc.wHubCharacteristics & HUB_CHAR_LPSM) {
+	case 0x00:
+		DEBUG_HUB("ganged power switching\n");
+		break;
+	case 0x01:
+		DEBUG_HUB("individual port power switching\n");
+		break;
+	case 0x02:
+	case 0x03:
+		DEBUG_HUB("unknown reserved power switching mode\n");
+		break;
+	}
+
+	if (hub->desc.wHubCharacteristics & HUB_CHAR_COMPOUND) {
+		DEBUG_HUB("part of a compound device\n");
+	}
+	else {
+		DEBUG_HUB("standalone hub\n");
+	}
+
+	switch (hub->desc.wHubCharacteristics & HUB_CHAR_OCPM) {
+	case 0x00:
+		DEBUG_HUB("global over-current protection\n");
+		break;
+	case 0x08:
+		DEBUG_HUB("individual port over-current protection\n");
+		break;
+	case 0x10:
+	case 0x18:
+		DEBUG_HUB("no over-current protection\n");
+		break;
+	}
+
+	DEBUG_HUB("power on to power good time: %dms\n",
+			descriptor->bPwrOn2PwrGood * 2);
+	DEBUG_HUB("hub controller current requirement: %dmA\n",
+			descriptor->bHubContrCurrent);
+
+	for (i = 0; i < dev->maxchild; i++)
+		DEBUG_HUB("port %d is%s removable\n", i + 1,
+			hub->desc.DeviceRemovable[(i + 1) / 8] & \
+					   (1 << ((i + 1) % 8)) ? " not" : "");
+
+	if (sizeof(struct usb_hub_status) > USB_BUFSIZ) {
+		DEBUG_HUB("usb_hub_configure: failed to get Status - " \
+				"too long: %d\n", descriptor->bLength);
+		return -1;
+	}
+
+	if (usb_get_hub_status(dev, buffer) < 0) {
+		DEBUG_HUB("usb_hub_configure: failed to get Status %lX\n",
+				dev->status);
+		return -1;
+	}
+
+	hubsts = (struct usb_hub_status *)buffer;
+	DEBUG_HUB("get_hub_status returned status %X, change %X\n",
+			__le16_to_cpu(hubsts->wHubStatus),
+			__le16_to_cpu(hubsts->wHubChange));
+	DEBUG_HUB("local power source is %s\n",
+		(__le16_to_cpu(hubsts->wHubStatus) & HUB_STATUS_LOCAL_POWER) ? \
+		"lost (inactive)" : "good");
+	DEBUG_HUB("%sover-current condition exists\n",
+		(__le16_to_cpu(hubsts->wHubStatus) & HUB_STATUS_OVERCURRENT) ? \
+		"" : "no ");
+	usb_hub_power_on(hub);
+
+
+
+	for (i = 0; i < dev->maxchild; i++) {
+		struct usb_port_status portsts;
+		unsigned short portstatus, portchange;
+		
+		wait_ms (100); /* GALVEZ: add delay for MiNT/TOS */
+		
+		if (usb_get_port_status(dev, i + 1, &portsts) < 0) {
+			DEBUG_HUB("get_port_status failed\n");
+			continue;
+		}
+
+		portstatus = __le16_to_cpu(portsts.wPortStatus);
+		portchange = __le16_to_cpu(portsts.wPortChange);
+		DEBUG_HUB("Port %d Status %X Change %X\n",
+				i + 1, portstatus, portchange);
+
+		if (portchange & USB_PORT_STAT_C_CONNECTION) {
+			DEBUG_HUB("port %d connection change\n", i + 1);
+			usb_hub_port_connect_change(dev, i);
+		}
+
+		if (portchange & USB_PORT_STAT_C_ENABLE) {
+			DEBUG_HUB("port %d enable change, status %x\n",
+					i + 1, portstatus);
+			usb_clear_port_feature(dev, i + 1,
+						USB_PORT_FEAT_C_ENABLE);
+
+			/* EM interference sometimes causes bad shielded USB
+			 * devices to be shutdown by the hub, this hack enables
+			 * them again. Works at least with mouse driver */
+			if (!(portstatus & USB_PORT_STAT_ENABLE) &&
+			     (portstatus & USB_PORT_STAT_CONNECTION) &&
+			     ((dev->children[i]))) {
+				DEBUG_HUB("already running port %i "  \
+						"disabled by hub (EMI?), " \
+						"re-enabling...\n", i + 1);
+					usb_hub_port_connect_change(dev, i);
+			}
+		}
+		if (portstatus & USB_PORT_STAT_SUSPEND) {
+			DEBUG_HUB("port %d suspend change\n", i + 1);
+			usb_clear_port_feature(dev, i + 1,
+						USB_PORT_FEAT_SUSPEND);
+		}
+
+		if (portchange & USB_PORT_STAT_C_OVERCURRENT) {
+			DEBUG_HUB("port %d over-current change\n", i + 1);
+			usb_clear_port_feature(dev, i + 1,
+						USB_PORT_FEAT_C_OVER_CURRENT);
+			usb_hub_power_on(hub);
+		}
+
+		if (portchange & USB_PORT_STAT_C_RESET) {
+			DEBUG_HUB("port %d reset change\n", i + 1);
+			usb_clear_port_feature(dev, i + 1,
+						USB_PORT_FEAT_C_RESET);
+		}
+	} /* end for i all ports */
+	return 0;
+}
+
+int usb_hub_probe(struct usb_device *dev, int ifnum)
+{
+	struct usb_interface_descriptor *iface;
+	struct usb_endpoint_descriptor *ep;
+	int ret;
+
+	iface = &dev->config.if_desc[ifnum];
+	/* Is it a hub? */
+	if (iface->bInterfaceClass != USB_CLASS_HUB)
+		return 0;
+	/* Some hubs have a subclass of 1, which AFAICT according to the */
+	/*  specs is not defined, but it works */
+	if ((iface->bInterfaceSubClass != 0) &&
+	    (iface->bInterfaceSubClass != 1))
+		return 0;
+	/* Multiple endpoints? What kind of mutant ninja-hub is this? */
+	if (iface->bNumEndpoints != 1)
+		return 0;
+	ep = &iface->ep_desc[0];
+	/* Output endpoint? Curiousier and curiousier.. */
+	if (!(ep->bEndpointAddress & USB_DIR_IN))
+		return 0;
+	/* If it's not an interrupt endpoint, we'd better punt! */
+	if ((ep->bmAttributes & 3) != 3)
+		return 0;
+	/* We found a hub */
+	DEBUG_HUB("USB hub found\n");
+	ret = usb_hub_configure(dev);
+
+	return ret;
+}
+
+/* EOF */
diff --git a/FireBee/trunk/usb/store/usb.h b/FireBee/trunk/usb/store/usb.h
new file mode 100644
index 0000000..ce2cd93
--- /dev/null
+++ b/FireBee/trunk/usb/store/usb.h
@@ -0,0 +1,470 @@
+/*
+ * Modified for Atari by David Gálvez 2010
+ * Modified for Atari by Didier Mequignon 2009
+ *	
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Note: Part of this code has been derived from linux
+ *
+ */
+#ifndef _USB_H_
+#define _USB_H_
+
+#include <mint/osbind.h>
+#include <mint/sysvars.h>
+#include <stdlib.h>
+#include <string.h>
+#include <stdio.h>
+
+#include "host/ohci-pci/mod_devicetable.h"
+#include "usb_defs.h"
+#include "asm-m68k/types.h"
+#include "asm-m68k/byteorder.h"
+#include "part.h"
+
+#ifdef PCI_XBIOS
+
+#define in8(addr)		fast_read_mem_byte(usb_handle,addr)
+#define in16r(addr)		fast_read_mem_word(usb_handle,addr)
+#define in32r(addr)		fast_read_mem_longword(usb_handle,addr)
+#define out8(addr,val)	write_mem_byte(usb_handle,addr,val)
+#define out16r(addr,val)	write_mem_word(usb_handle,addr,val)
+#define out32r(addr,val)	write_mem_longword(usb_handle,addr,val)
+
+#else /* !PCI_XBIOS */
+
+extern long *tab_funcs_pci;
+
+#define in8(addr)		Fast_read_mem_byte(usb_handle,addr)
+#define in16r(addr)		Fast_read_mem_word(usb_handle,addr)
+#define in32r(addr)		Fast_read_mem_longword(usb_handle,addr)
+#define out8(addr,val)	Write_mem_byte(usb_handle,addr,val)
+#define out16r(addr,val)	Write_mem_word(usb_handle,addr,val)
+#define out32r(addr,val)	Write_mem_longword(usb_handle,addr,val)
+
+#endif /* PCI_XBIOS */
+
+
+/* Everything is aribtrary */
+#define USB_ALTSETTINGALLOC		4
+#define USB_MAXALTSETTING		128	/* Hard limit */
+
+#define USB_MAX_DEVICE			32
+#define USB_MAXCONFIG			8
+#define USB_MAXINTERFACES		8
+#define USB_MAXENDPOINTS		16
+#define USB_MAXCHILDREN			8	/* This is arbitrary */
+#define USB_MAX_HUB			16
+
+#define USB_CNTL_TIMEOUT 100	/* 100ms timeout */
+
+/* String descriptor */
+struct usb_string_descriptor {
+	unsigned char	bLength;
+	unsigned char	bDescriptorType;
+	unsigned short	wData[1];
+} __attribute__ ((packed));
+
+/* device request (setup) */
+struct devrequest {
+	unsigned char	requesttype;
+	unsigned char	request;
+	unsigned short	value;
+	unsigned short	index;
+	unsigned short	length;
+} __attribute__ ((packed));
+
+/* All standard descriptors have these 2 fields in common */
+struct usb_descriptor_header {
+	unsigned char	bLength;
+	unsigned char	bDescriptorType;
+} __attribute__ ((packed));
+
+/* Device descriptor */
+struct usb_device_descriptor {
+	unsigned char	bLength;
+	unsigned char	bDescriptorType;
+	unsigned short	bcdUSB;
+	unsigned char	bDeviceClass;
+	unsigned char	bDeviceSubClass;
+	unsigned char	bDeviceProtocol;
+	unsigned char	bMaxPacketSize0;
+	unsigned short	idVendor;
+	unsigned short	idProduct;
+	unsigned short	bcdDevice;
+	unsigned char	iManufacturer;
+	unsigned char	iProduct;
+	unsigned char	iSerialNumber;
+	unsigned char	bNumConfigurations;
+} __attribute__ ((packed));
+
+/* Endpoint descriptor */
+struct usb_endpoint_descriptor {
+	unsigned char	bLength;
+	unsigned char	bDescriptorType;
+	unsigned char	bEndpointAddress;
+	unsigned char	bmAttributes;
+	unsigned short	wMaxPacketSize;
+	unsigned char	bInterval;
+	unsigned char	bRefresh;
+	unsigned char	bSynchAddress;
+} __attribute__ ((packed)) __attribute__ ((aligned(2)));
+
+/* Interface descriptor */
+struct usb_interface_descriptor {
+	unsigned char	bLength;
+	unsigned char	bDescriptorType;
+	unsigned char	bInterfaceNumber;
+	unsigned char	bAlternateSetting;
+	unsigned char	bNumEndpoints;
+	unsigned char	bInterfaceClass;
+	unsigned char	bInterfaceSubClass;
+	unsigned char	bInterfaceProtocol;
+	unsigned char	iInterface;
+
+	unsigned char	no_of_ep;
+	unsigned char	num_altsetting;
+	unsigned char	act_altsetting;
+
+	struct usb_endpoint_descriptor ep_desc[USB_MAXENDPOINTS];
+} __attribute__ ((packed));
+
+
+/* Configuration descriptor information.. */
+struct usb_config_descriptor {
+	unsigned char	bLength;
+	unsigned char	bDescriptorType;
+	unsigned short	wTotalLength;
+	unsigned char	bNumInterfaces;
+	unsigned char	bConfigurationValue;
+	unsigned char	iConfiguration;
+	unsigned char	bmAttributes;
+	unsigned char	MaxPower;
+
+	unsigned char	no_of_if;	/* number of interfaces */
+	struct usb_interface_descriptor if_desc[USB_MAXINTERFACES];
+} __attribute__ ((packed));
+
+enum {
+	/* Maximum packet size; encoded as 0,1,2,3 = 8,16,32,64 */
+	PACKET_SIZE_8   = 0,
+	PACKET_SIZE_16  = 1,
+	PACKET_SIZE_32  = 2,
+	PACKET_SIZE_64  = 3,
+};
+
+struct usb_device {
+	int	devnum;			/* Device number on USB bus */
+	int	speed;			/* full/low/high */
+	char	mf[32];			/* manufacturer */
+	char	prod[32];		/* product */
+	char	serial[32];		/* serial number */
+
+	/* Maximum packet size; one of: PACKET_SIZE_* */
+	int maxpacketsize;
+	/* one bit for each endpoint ([0] = IN, [1] = OUT) */
+	unsigned int toggle[2];
+	/* endpoint halts; one bit per endpoint # & direction;
+	 * [0] = IN, [1] = OUT
+	 */
+	unsigned int halted[2];
+	int epmaxpacketin[16];		/* INput endpoint specific maximums */
+	int epmaxpacketout[16];		/* OUTput endpoint specific maximums */
+
+	int configno;			/* selected config number */
+	struct usb_device_descriptor descriptor; /* Device Descriptor */
+	struct usb_config_descriptor config; /* config descriptor */
+
+	int have_langid;		/* whether string_langid is valid yet */
+	int string_langid;		/* language ID for strings */
+	int (*irq_handle)(struct usb_device *dev);
+	unsigned long irq_status;
+	int irq_act_len;		/* transfered bytes */
+	void *privptr;
+	/*
+	 * Child devices -  if this is a hub device
+	 * Each instance needs its own set of data structures.
+	 */
+	unsigned long status;
+	int act_len;			/* transfered bytes */
+	int maxchild;			/* Number of ports if hub */
+	int portnr;
+	struct usb_device *parent;
+	struct usb_device *children[USB_MAXCHILDREN];
+};
+
+/**********************************************************************
+ * this is how the lowlevel part communicate with the outer world
+ */
+
+#if defined(CONFIG_USB_UHCI) || defined(CONFIG_USB_OHCI) || \
+	defined(CONFIG_USB_EHCI) || defined(CONFIG_USB_OHCI_NEW) || \
+	defined(CONFIG_USB_SL811HS) || defined(CONFIG_USB_ISP116X_HCD) || \
+	defined(CONFIG_USB_R8A66597_HCD) || defined(CONFIG_USB_DAVINCI) || \
+	defined(CONFIG_USB_ARANYM_HCD)
+
+#ifdef PCI_XBIOS
+int usb_lowlevel_init(long handle, const struct pci_device_id *ent);
+#else
+int usb_lowlevel_init(void);
+#endif
+
+int usb_lowlevel_stop(void);
+int submit_bulk_msg(struct usb_device *dev, unsigned long pipe,
+			void *buffer, int transfer_len);
+int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+			int transfer_len, struct devrequest *setup);
+int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
+			int transfer_len, int interval);
+			
+#ifdef CONFIG_USB_INTERRUPT_POLLING
+void usb_event_poll(void);
+#else
+void usb_enable_interrupt(int enable);
+#endif
+
+/* Defines */
+#define USB_UHCI_VEND_ID	0x8086
+#define USB_UHCI_DEV_ID		0x7112
+
+#else
+#error USB Lowlevel not defined
+#endif
+
+#ifdef CONFIG_USB_STORAGE
+
+#define USB_MAX_STOR_DEV 2	/* GALVEZ: DEFAULT 5 */
+block_dev_desc_t *usb_stor_get_dev(int idx);
+int usb_stor_scan(void);
+int usb_stor_info(void);
+
+#endif
+
+#ifdef CONFIG_USB_MOUSE
+int drv_usb_mouse_init(void);
+int usb_mouse_deregister(void);
+#endif
+
+
+#ifdef CONFIG_USB_KEYBOARD
+int drv_usb_kbd_init(void);
+int usb_kbd_deregister(void);
+#endif
+
+/* memory */
+void *usb_malloc(long amount);
+int usb_free(void *addr);
+int usb_mem_init(void);
+void usb_mem_stop(void);
+
+
+/* routines */
+#ifdef PCI_XBIOS
+int usb_init(long handle, const struct pci_device_id *ent); /* initialize the USB Controller */
+#else
+int usb_init(void); /* initialize the USB Controller */
+#endif
+int usb_stop(void); /* stop the USB Controller */
+
+
+int usb_set_protocol(struct usb_device *dev, int ifnum, int protocol);
+int usb_set_idle(struct usb_device *dev, int ifnum, int duration,
+			int report_id);
+struct usb_device *usb_get_dev_index(int idx);
+int usb_control_msg(struct usb_device *dev, unsigned int pipe,
+			unsigned char request, unsigned char requesttype,
+			unsigned short value, unsigned short idx,
+			void *data, unsigned short size, int timeout);
+int usb_bulk_msg(struct usb_device *dev, unsigned int pipe,
+			void *data, int len, int *actual_length, int timeout);
+int usb_submit_int_msg(struct usb_device *dev, unsigned long pipe,
+			void *buffer, int transfer_len, int interval);
+void usb_disable_asynch(int disable);
+int usb_maxpacket(struct usb_device *dev, unsigned long pipe);
+inline void wait_ms(unsigned long ms);
+int usb_get_configuration_no(struct usb_device *dev, unsigned char *buffer,
+				int cfgno);
+int usb_get_report(struct usb_device *dev, int ifnum, unsigned char type,
+			unsigned char id, void *buf, int size);
+int usb_get_class_descriptor(struct usb_device *dev, int ifnum,
+			unsigned char type, unsigned char id, void *buf,
+			int size);
+int usb_clear_halt(struct usb_device *dev, int pipe);
+int usb_string(struct usb_device *dev, int idx, char *buf, size_t size);
+int usb_set_interface(struct usb_device *dev, int interface, int alternate);
+
+/* big endian -> little endian conversion */
+/* some CPUs are already little endian e.g. the ARM920T */
+#define __swap_16(x) \
+	({ unsigned short x_ = (unsigned short)x; \
+	 (unsigned short)( \
+		((x_ & 0x00FFU) << 8) | ((x_ & 0xFF00U) >> 8)); \
+	})
+#define __swap_32(x) \
+	({ unsigned long x_ = (unsigned long)x; \
+	 (unsigned long)( \
+		((x_ & 0x000000FFUL) << 24) | \
+		((x_ & 0x0000FF00UL) <<	 8) | \
+		((x_ & 0x00FF0000UL) >>	 8) | \
+		((x_ & 0xFF000000UL) >> 24)); \
+	})
+
+#ifdef __LITTLE_ENDIAN
+# define swap_16(x) (x)
+# define swap_32(x) (x)
+#else
+# define swap_16(x) __swap_16(x)
+# define swap_32(x) __swap_32(x)
+#endif
+
+/*
+ * Calling this entity a "pipe" is glorifying it. A USB pipe
+ * is something embarrassingly simple: it basically consists
+ * of the following information:
+ *  - device number (7 bits)
+ *  - endpoint number (4 bits)
+ *  - current Data0/1 state (1 bit)
+ *  - direction (1 bit)
+ *  - speed (2 bits)
+ *  - max packet size (2 bits: 8, 16, 32 or 64)
+ *  - pipe type (2 bits: control, interrupt, bulk, isochronous)
+ *
+ * That's 18 bits. Really. Nothing more. And the USB people have
+ * documented these eighteen bits as some kind of glorious
+ * virtual data structure.
+ *
+ * Let's not fall in that trap. We'll just encode it as a simple
+ * unsigned int. The encoding is:
+ *
+ *  - max size:		bits 0-1	(00 = 8, 01 = 16, 10 = 32, 11 = 64)
+ *  - direction:	bit 7		(0 = Host-to-Device [Out],
+ *					(1 = Device-to-Host [In])
+ *  - device:		bits 8-14
+ *  - endpoint:		bits 15-18
+ *  - Data0/1:		bit 19
+ *  - speed:		bit 26		(0 = Full, 1 = Low Speed, 2 = High)
+ *  - pipe type:	bits 30-31	(00 = isochronous, 01 = interrupt,
+ *					 10 = control, 11 = bulk)
+ *
+ * Why? Because it's arbitrary, and whatever encoding we select is really
+ * up to us. This one happens to share a lot of bit positions with the UHCI
+ * specification, so that much of the uhci driver can just mask the bits
+ * appropriately.
+ */
+/* Create various pipes... */
+#define create_pipe(dev,endpoint) \
+		(((dev)->devnum << 8) | (endpoint << 15) | \
+		((dev)->speed << 26) | (dev)->maxpacketsize)
+#define default_pipe(dev) ((dev)->speed << 26)
+
+#define usb_sndctrlpipe(dev, endpoint)	((PIPE_CONTROL << 30) | \
+					 create_pipe(dev, endpoint))
+#define usb_rcvctrlpipe(dev, endpoint)	((PIPE_CONTROL << 30) | \
+					 create_pipe(dev, endpoint) | \
+					 USB_DIR_IN)
+#define usb_sndisocpipe(dev, endpoint)	((PIPE_ISOCHRONOUS << 30) | \
+					 create_pipe(dev, endpoint))
+#define usb_rcvisocpipe(dev, endpoint)	((PIPE_ISOCHRONOUS << 30) | \
+					 create_pipe(dev, endpoint) | \
+					 USB_DIR_IN)
+#define usb_sndbulkpipe(dev, endpoint)	((PIPE_BULK << 30) | \
+					 create_pipe(dev, endpoint))
+#define usb_rcvbulkpipe(dev, endpoint)	((PIPE_BULK << 30) | \
+					 create_pipe(dev, endpoint) | \
+					 USB_DIR_IN)
+#define usb_sndintpipe(dev, endpoint)	((PIPE_INTERRUPT << 30) | \
+					 create_pipe(dev, endpoint))
+#define usb_rcvintpipe(dev, endpoint)	((PIPE_INTERRUPT << 30) | \
+					 create_pipe(dev, endpoint) | \
+					 USB_DIR_IN)
+#define usb_snddefctrl(dev)		((PIPE_CONTROL << 30) | \
+					 default_pipe(dev))
+#define usb_rcvdefctrl(dev)		((PIPE_CONTROL << 30) | \
+					 default_pipe(dev) | \
+					 USB_DIR_IN)
+
+/* The D0/D1 toggle bits */
+#define usb_gettoggle(dev, ep, out) (((dev)->toggle[out] >> ep) & 1)
+#define usb_dotoggle(dev, ep, out)  ((dev)->toggle[out] ^= (1 << ep))
+#define usb_settoggle(dev, ep, out, bit) ((dev)->toggle[out] = \
+						((dev)->toggle[out] & \
+						 ~(1 << ep)) | ((bit) << ep))
+
+/* Endpoint halt control/status */
+#define usb_endpoint_out(ep_dir)	(((ep_dir >> 7) & 1) ^ 1)
+#define usb_endpoint_halt(dev, ep, out) ((dev)->halted[out] |= (1 << (ep)))
+#define usb_endpoint_running(dev, ep, out) ((dev)->halted[out] &= ~(1 << (ep)))
+#define usb_endpoint_halted(dev, ep, out) ((dev)->halted[out] & (1 << (ep)))
+
+#define usb_packetid(pipe)	(((pipe) & USB_DIR_IN) ? USB_PID_IN : \
+				 USB_PID_OUT)
+
+#define usb_pipeout(pipe)	((((pipe) >> 7) & 1) ^ 1)
+#define usb_pipein(pipe)	(((pipe) >> 7) & 1)
+#define usb_pipedevice(pipe)	(((pipe) >> 8) & 0x7f)
+#define usb_pipe_endpdev(pipe)	(((pipe) >> 8) & 0x7ff)
+#define usb_pipeendpoint(pipe)	(((pipe) >> 15) & 0xf)
+#define usb_pipedata(pipe)	(((pipe) >> 19) & 1)
+#define usb_pipespeed(pipe)	(((pipe) >> 26) & 3)
+#define usb_pipeslow(pipe)	(usb_pipespeed(pipe) == USB_SPEED_LOW)
+#define usb_pipetype(pipe)	(((pipe) >> 30) & 3)
+#define usb_pipeisoc(pipe)	(usb_pipetype((pipe)) == PIPE_ISOCHRONOUS)
+#define usb_pipeint(pipe)	(usb_pipetype((pipe)) == PIPE_INTERRUPT)
+#define usb_pipecontrol(pipe)	(usb_pipetype((pipe)) == PIPE_CONTROL)
+#define usb_pipebulk(pipe)	(usb_pipetype((pipe)) == PIPE_BULK)
+
+
+/*************************************************************************
+ * Hub Stuff
+ */
+struct usb_port_status {
+	unsigned short wPortStatus;
+	unsigned short wPortChange;
+} __attribute__ ((packed));
+
+struct usb_hub_status {
+	unsigned short wHubStatus;
+	unsigned short wHubChange;
+} __attribute__ ((packed));
+
+
+/* Hub descriptor */
+struct usb_hub_descriptor {
+	unsigned char  bLength;
+	unsigned char  bDescriptorType;
+	unsigned char  bNbrPorts;
+	unsigned short wHubCharacteristics;
+	unsigned char  bPwrOn2PwrGood;
+	unsigned char  bHubContrCurrent;
+	unsigned char  DeviceRemovable[(USB_MAXCHILDREN+1+7)/8];
+	unsigned char  PortPowerCtrlMask[(USB_MAXCHILDREN+1+7)/8];
+	/* DeviceRemovable and PortPwrCtrlMask want to be variable-length
+	   bitmaps that hold max 255 entries. (bit0 is ignored) */
+} __attribute__ ((packed));
+
+
+struct usb_hub_device {
+	struct usb_device *pusb_dev;
+	struct usb_hub_descriptor desc;
+};
+
+#endif /*_USB_H_ */
diff --git a/FireBee/trunk/usb/store/usb_defs.h b/FireBee/trunk/usb/store/usb_defs.h
new file mode 100644
index 0000000..8032e57
--- /dev/null
+++ b/FireBee/trunk/usb/store/usb_defs.h
@@ -0,0 +1,251 @@
+/*
+ * (C) Copyright 2001
+ * Denis Peter, MPL AG Switzerland
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ * Note: Part of this code has been derived from linux
+ *
+ */
+#ifndef _USB_DEFS_H_
+#define _USB_DEFS_H_
+
+/* USB constants */
+
+/* Device and/or Interface Class codes */
+#define USB_CLASS_PER_INTERFACE  0	/* for DeviceClass */
+#define USB_CLASS_AUDIO          1
+#define USB_CLASS_COMM           2
+#define USB_CLASS_HID            3
+#define USB_CLASS_PRINTER	       7
+#define USB_CLASS_MASS_STORAGE   8
+#define USB_CLASS_HUB            9
+#define USB_CLASS_DATA           10
+#define USB_CLASS_VENDOR_SPEC    0xff
+
+/* some HID sub classes */
+#define USB_SUB_HID_NONE        0
+#define USB_SUB_HID_BOOT        1
+
+/* some UID Protocols */
+#define USB_PROT_HID_NONE       0
+#define USB_PROT_HID_KEYBOARD   1
+#define USB_PROT_HID_MOUSE      2
+
+
+/* Sub STORAGE Classes */
+#define US_SC_RBC              1		/* Typically, flash devices */
+#define US_SC_8020             2		/* CD-ROM */
+#define US_SC_QIC              3		/* QIC-157 Tapes */
+#define US_SC_UFI              4		/* Floppy */
+#define US_SC_8070             5		/* Removable media */
+#define US_SC_SCSI             6		/* Transparent */
+#define US_SC_MIN              US_SC_RBC
+#define US_SC_MAX              US_SC_SCSI
+
+/* STORAGE Protocols */
+#define US_PR_CB               1		/* Control/Bulk w/o interrupt */
+#define US_PR_CBI              0		/* Control/Bulk/Interrupt */
+#define US_PR_BULK             0x50		/* bulk only */
+
+/* USB types */
+#define USB_TYPE_STANDARD   (0x00 << 5)
+#define USB_TYPE_CLASS      (0x01 << 5)
+#define USB_TYPE_VENDOR     (0x02 << 5)
+#define USB_TYPE_RESERVED   (0x03 << 5)
+
+/* USB recipients */
+#define USB_RECIP_DEVICE      0x00
+#define USB_RECIP_INTERFACE   0x01
+#define USB_RECIP_ENDPOINT    0x02
+#define USB_RECIP_OTHER       0x03
+
+/* USB directions */
+#define USB_DIR_OUT           0
+#define USB_DIR_IN            0x80
+
+/* USB device speeds */
+#define USB_SPEED_FULL		0x0	/* 12Mbps */
+#define USB_SPEED_LOW		0x1	/* 1.5Mbps */
+#define USB_SPEED_HIGH		0x2	/* 480Mbps */
+#define USB_SPEED_RESERVED	0x3
+
+/* Descriptor types */
+#define USB_DT_DEVICE        0x01
+#define USB_DT_CONFIG        0x02
+#define USB_DT_STRING        0x03
+#define USB_DT_INTERFACE     0x04
+#define USB_DT_ENDPOINT      0x05
+
+#define USB_DT_HID          (USB_TYPE_CLASS | 0x01)
+#define USB_DT_REPORT       (USB_TYPE_CLASS | 0x02)
+#define USB_DT_PHYSICAL     (USB_TYPE_CLASS | 0x03)
+#define USB_DT_HUB          (USB_TYPE_CLASS | 0x09)
+
+/* Descriptor sizes per descriptor type */
+#define USB_DT_DEVICE_SIZE      18
+#define USB_DT_CONFIG_SIZE      9
+#define USB_DT_INTERFACE_SIZE   9
+#define USB_DT_ENDPOINT_SIZE    7
+#define USB_DT_ENDPOINT_AUDIO_SIZE  9	/* Audio extension */
+#define USB_DT_HUB_NONVAR_SIZE  7
+#define USB_DT_HID_SIZE         9
+
+/* Endpoints */
+#define USB_ENDPOINT_NUMBER_MASK  0x0f	/* in bEndpointAddress */
+#define USB_ENDPOINT_DIR_MASK     0x80
+
+#define USB_ENDPOINT_XFERTYPE_MASK 0x03	/* in bmAttributes */
+#define USB_ENDPOINT_XFER_CONTROL  0
+#define USB_ENDPOINT_XFER_ISOC     1
+#define USB_ENDPOINT_XFER_BULK     2
+#define USB_ENDPOINT_XFER_INT      3
+
+/* USB Packet IDs (PIDs) */
+#define USB_PID_UNDEF_0             0xf0
+#define USB_PID_OUT                 0xe1
+#define USB_PID_ACK                 0xd2
+#define USB_PID_DATA0               0xc3
+#define USB_PID_UNDEF_4             0xb4
+#define USB_PID_SOF                 0xa5
+#define USB_PID_UNDEF_6             0x96
+#define USB_PID_UNDEF_7             0x87
+#define USB_PID_UNDEF_8             0x78
+#define USB_PID_IN                  0x69
+#define USB_PID_NAK                 0x5a
+#define USB_PID_DATA1               0x4b
+#define USB_PID_PREAMBLE            0x3c
+#define USB_PID_SETUP               0x2d
+#define USB_PID_STALL               0x1e
+#define USB_PID_UNDEF_F             0x0f
+
+/* Standard requests */
+#define USB_REQ_GET_STATUS          0x00
+#define USB_REQ_CLEAR_FEATURE       0x01
+#define USB_REQ_SET_FEATURE         0x03
+#define USB_REQ_SET_ADDRESS         0x05
+#define USB_REQ_GET_DESCRIPTOR      0x06
+#define USB_REQ_SET_DESCRIPTOR      0x07
+#define USB_REQ_GET_CONFIGURATION   0x08
+#define USB_REQ_SET_CONFIGURATION   0x09
+#define USB_REQ_GET_INTERFACE       0x0A
+#define USB_REQ_SET_INTERFACE       0x0B
+#define USB_REQ_SYNCH_FRAME         0x0C
+
+/* HID requests */
+#define USB_REQ_GET_REPORT          0x01
+#define USB_REQ_GET_IDLE            0x02
+#define USB_REQ_GET_PROTOCOL        0x03
+#define USB_REQ_SET_REPORT          0x09
+#define USB_REQ_SET_IDLE            0x0A
+#define USB_REQ_SET_PROTOCOL        0x0B
+
+
+/* "pipe" definitions */
+
+#define PIPE_ISOCHRONOUS    0
+#define PIPE_INTERRUPT      1
+#define PIPE_CONTROL        2
+#define PIPE_BULK           3
+#define PIPE_DEVEP_MASK     0x0007ff00
+
+#define USB_ISOCHRONOUS    0
+#define USB_INTERRUPT      1
+#define USB_CONTROL        2
+#define USB_BULK           3
+
+/* USB-status codes: */
+#define USB_ST_ACTIVE           0x1		/* TD is active */
+#define USB_ST_STALLED          0x2		/* TD is stalled */
+#define USB_ST_BUF_ERR          0x4		/* buffer error */
+#define USB_ST_BABBLE_DET       0x8		/* Babble detected */
+#define USB_ST_NAK_REC          0x10	/* NAK Received*/
+#define USB_ST_CRC_ERR          0x20	/* CRC/timeout Error */
+#define USB_ST_BIT_ERR          0x40	/* Bitstuff error */
+#define USB_ST_NOT_PROC         0x80000000L	/* Not yet processed */
+
+
+/*************************************************************************
+ * Hub defines
+ */
+
+/*
+ * Hub request types
+ */
+
+#define USB_RT_HUB	(USB_TYPE_CLASS | USB_RECIP_DEVICE)
+#define USB_RT_PORT	(USB_TYPE_CLASS | USB_RECIP_OTHER)
+
+/*
+ * Hub Class feature numbers
+ */
+#define C_HUB_LOCAL_POWER   0
+#define C_HUB_OVER_CURRENT  1
+
+/*
+ * Port feature numbers
+ */
+#define USB_PORT_FEAT_CONNECTION     0
+#define USB_PORT_FEAT_ENABLE         1
+#define USB_PORT_FEAT_SUSPEND        2
+#define USB_PORT_FEAT_OVER_CURRENT   3
+#define USB_PORT_FEAT_RESET          4
+#define USB_PORT_FEAT_POWER          8
+#define USB_PORT_FEAT_LOWSPEED       9
+#define USB_PORT_FEAT_HIGHSPEED      10
+#define USB_PORT_FEAT_C_CONNECTION   16
+#define USB_PORT_FEAT_C_ENABLE       17
+#define USB_PORT_FEAT_C_SUSPEND      18
+#define USB_PORT_FEAT_C_OVER_CURRENT 19
+#define USB_PORT_FEAT_C_RESET        20
+
+/* wPortStatus bits */
+#define USB_PORT_STAT_CONNECTION    0x0001
+#define USB_PORT_STAT_ENABLE        0x0002
+#define USB_PORT_STAT_SUSPEND       0x0004
+#define USB_PORT_STAT_OVERCURRENT   0x0008
+#define USB_PORT_STAT_RESET         0x0010
+#define USB_PORT_STAT_POWER         0x0100
+#define USB_PORT_STAT_LOW_SPEED     0x0200
+#define USB_PORT_STAT_HIGH_SPEED    0x0400	/* support for EHCI */
+#define USB_PORT_STAT_SPEED	\
+	(USB_PORT_STAT_LOW_SPEED | USB_PORT_STAT_HIGH_SPEED)
+
+/* wPortChange bits */
+#define USB_PORT_STAT_C_CONNECTION  0x0001
+#define USB_PORT_STAT_C_ENABLE      0x0002
+#define USB_PORT_STAT_C_SUSPEND     0x0004
+#define USB_PORT_STAT_C_OVERCURRENT 0x0008
+#define USB_PORT_STAT_C_RESET       0x0010
+
+/* wHubCharacteristics (masks) */
+#define HUB_CHAR_LPSM               0x0003
+#define HUB_CHAR_COMPOUND           0x0004
+#define HUB_CHAR_OCPM               0x0018
+
+/*
+ *Hub Status & Hub Change bit masks
+ */
+#define HUB_STATUS_LOCAL_POWER	0x0001
+#define HUB_STATUS_OVERCURRENT	0x0002
+
+#define HUB_CHANGE_LOCAL_POWER	0x0001
+#define HUB_CHANGE_OVERCURRENT	0x0002
+
+#endif /*_USB_DEFS_H_ */
diff --git a/FireBee/trunk/usb/store/usb_mem.c b/FireBee/trunk/usb/store/usb_mem.c
new file mode 100644
index 0000000..7397d12
--- /dev/null
+++ b/FireBee/trunk/usb/store/usb_mem.c
@@ -0,0 +1,220 @@
+/*
+ * usb_mem.c
+ *
+ * based from Emutos / BDOS
+ * 
+ * Copyright (c) 2001 Lineo, Inc.
+ *
+ * Authors: Karl T. Braun, Martin Doering, Laurent Vogel
+ *
+ * This file is distributed under the GPL, version 2 or at your
+ * option any later version.
+ */
+
+#include <mint/errno.h>
+#include <mint/osbind.h> 
+#include <string.h>
+
+#ifndef FALSE
+#define FALSE 0
+#endif
+#ifndef TRUE
+#define TRUE 1
+#endif
+
+#define USB_BUFFER_SIZE 0x10000
+
+static void *usb_buffer;
+
+/* MD - Memory Descriptor */
+
+#define MD struct _md_
+
+MD
+{
+	MD *m_link;
+	long m_start;
+	long m_length;
+};
+
+/* MPB - Memory Partition Block */
+
+#define MPB struct _mpb
+
+MPB
+{
+	MD *mp_mfl;
+	MD *mp_mal;
+	MD *mp_rover;
+};
+
+#define MAXMD 100
+
+static int count_md;
+static MD tab_md[MAXMD];
+static MPB pmd;
+
+static MD *ffit(long amount, MPB *mp)
+{
+	MD *p,*q,*p1;                    /* free list is composed of MD's */
+	int maxflg;
+	long maxval;
+	if(amount != -1)
+	{
+		amount += 15;                  /* 16 bytes alignment */
+		amount &= 0xFFFFFFF0;
+	}
+	if((q = mp->mp_rover) == 0)      /* get rotating pointer */
+		return(0) ;
+	maxval = 0;
+	maxflg = (amount == -1 ? TRUE : FALSE) ;
+	p = q->m_link;                   /* start with next MD */
+	do /* search the list for an MD with enough space */
+	{
+		if(p == 0)
+		{
+			/*  at end of list, wrap back to start  */
+			q = (MD *) &mp->mp_mfl;      /*  q => mfl field  */
+			p = q->m_link;               /*  p => 1st MD     */
+		}
+		if((!maxflg) && (p->m_length >= amount))
+		{
+			/*  big enough */
+			if(p->m_length == amount)
+				q->m_link = p->m_link;     /* take the whole thing */
+			else
+			{
+				/* break it up - 1st allocate a new
+				   MD to describe the remainder */
+				if(count_md >= MAXMD)
+					return(0);
+				p1 = &tab_md[count_md++];
+				/* init new MD */
+				p1->m_length = p->m_length - amount;
+				p1->m_start = p->m_start + amount;
+				p1->m_link = p->m_link;
+				p->m_length = amount;      /* adjust allocated block */
+				q->m_link = p1;
+			}
+			/* link allocate block into allocated list,
+			    mark owner of block, & adjust rover  */
+			p->m_link = mp->mp_mal;
+			mp->mp_mal = p;
+			mp->mp_rover = (q == (MD *) &mp->mp_mfl ? q->m_link : q);
+			return(p);                   /* got some */
+		}
+		else if(p->m_length > maxval)
+			maxval = p->m_length;
+		p = ( q=p )->m_link;
+	}
+	while(q != mp->mp_rover);
+	/*  return either the max, or 0 (error)  */
+	if(maxflg)
+	{
+		maxval -= 15; /* 16 bytes alignment */
+		if(maxval < 0)
+			maxval = 0;
+		else
+			maxval &= 0xFFFFFFF0;
+	}
+	return(maxflg ? (MD *) maxval : 0);
+}
+
+static void freeit(MD *m, MPB *mp)
+{
+	MD *p, *q;
+	q = 0;
+	for(p = mp->mp_mfl; p ; p = (q=p) -> m_link)
+	{
+		if(m->m_start <= p->m_start)
+			break;
+	}
+	m->m_link = p;
+	if(q)
+		q->m_link = m;
+	else
+		mp->mp_mfl = m;
+	if(!mp->mp_rover)
+		mp->mp_rover = m;
+	if(p)
+	{
+		if(m->m_start + m->m_length == p->m_start)
+		{ /* join to higher neighbor */
+			m->m_length += p->m_length;
+			m->m_link = p->m_link;
+			if(p == mp->mp_rover)
+				mp->mp_rover = m;
+			if(count_md>=0)
+				count_md--;
+		}
+	}
+	if(q)
+	{
+		if(q->m_start + q->m_length == m->m_start)
+		{ /* join to lower neighbor */
+			q->m_length += m->m_length;
+			q->m_link = m->m_link;
+			if(m == mp->mp_rover)
+				mp->mp_rover = q;
+			if(count_md>=0)
+				count_md--;
+		}
+	}
+}
+
+int usb_free(void *addr)
+{
+	MD *p,**q;
+	MPB *mpb;
+	mpb = &pmd;
+	if(usb_buffer == NULL)
+		return(EFAULT);
+	for(p = *(q = &mpb->mp_mal); p; p = *(q = &p->m_link))
+	{
+		if((long)addr == p->m_start)
+			break;
+	}
+	if(!p)
+		return(EFAULT);
+	*q = p->m_link;
+	freeit(p,mpb);
+	return(0);
+}
+
+void *usb_malloc(long amount)
+{
+	MD *m;
+	if(usb_buffer == NULL)
+		return(NULL);
+	if(amount == -1L)
+		return((void *)ffit(-1L,&pmd));
+	if(amount <= 0 )
+		return(0);
+	if((amount & 1))
+		amount++;
+	m = ffit(amount,&pmd);
+	if(m == NULL)
+		return(NULL);
+	return((void *)m->m_start);
+}
+
+int usb_mem_init(void)
+{
+	usb_buffer = (void *)Mxalloc(USB_BUFFER_SIZE + 16, 0); /* STRAM - cache in writethough */
+	if(usb_buffer == NULL)
+		return(-1);
+	pmd.mp_mfl = pmd.mp_rover = &tab_md[0];
+	tab_md[0].m_link = (MD *)NULL;
+	tab_md[0].m_start = ((long)usb_buffer + 15) & ~15;
+	tab_md[0].m_length = USB_BUFFER_SIZE;	
+	pmd.mp_mal = (MD *)NULL;
+	count_md = 1;
+	return(0);
+}
+
+void usb_mem_stop(void)
+{
+	if(usb_buffer != NULL)
+		Mfree(usb_buffer);
+}
+
diff --git a/FireBee/trunk/usb/store/usb_storage.c b/FireBee/trunk/usb/store/usb_storage.c
new file mode 100644
index 0000000..e48724e
--- /dev/null
+++ b/FireBee/trunk/usb/store/usb_storage.c
@@ -0,0 +1,1632 @@
+/*
+ * Modified for Atari by David Gálvez 2010
+ * Modified for Atari by Didier Mequignon 2009
+ *
+ * Most of this source has been derived from the Linux USB
+ * project:
+ *   (c) 1999-2002 Matthew Dharm (mdharm-usb@one-eyed-alien.net)
+ *   (c) 2000 David L. Brown, Jr. (usb-storage@davidb.org)
+ *   (c) 1999 Michael Gee (michael@linuxspecific.com)
+ *   (c) 2000 Yggdrasil Computing, Inc.
+ *
+ *
+ * Adapted for U-Boot:
+ *   (C) Copyright 2001 Denis Peter, MPL AG Switzerland
+ *
+ * For BBB support (C) Copyright 2003
+ * Gary Jennejohn, DENX Software Engineering <garyj@denx.de>
+ *
+ * BBB support based on /sys/dev/usb/umass.c from
+ * FreeBSD.
+ *
+ * See file CREDITS for list of people who contributed to this
+ * project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ *
+ */
+
+/* Note:
+ * Currently only the CBI transport protocoll has been implemented, and it
+ * is only tested with a TEAC USB Floppy. Other Massstorages with CBI or CB
+ * transport protocoll may work as well.
+ */
+/*
+ * New Note:
+ * Support for USB Mass Storage Devices (BBB) has been added. It has
+ * only been tested with USB memory sticks.
+ */
+
+#include "config.h"
+#include "usb.h"
+#include "scsi.h"
+#include "super.h"
+#include "debug.h"
+
+#if defined(CONFIG_USB_UHCI) || defined(CONFIG_USB_OHCI) || defined(CONFIG_USB_EHCI) \
+			|| defined(CONFIG_USB_ISP116X_HCD) || defined(CONFIG_USB_ARANYM_HCD)
+#ifdef CONFIG_USB_STORAGE
+
+/*
+ * Extra debug to the one availble in config.h
+ * These three extra debug levels go always to the log file
+ * uncomment them if you want them on
+ */
+//#define USB_STOR_DEBUG
+//#define BBB_COMDAT_TRACE
+//#define BBB_XPORT_TRACE
+
+
+extern void udelay(long usec);
+extern void ltoa(char *buf, long n, unsigned long base);
+
+/* direction table -- this indicates the direction of the data
+ * transfer for each command code -- a 1 indicates input
+ */
+unsigned char us_direction[256/8] = {
+	0x28, 0x81, 0x14, 0x14, 0x20, 0x01, 0x90, 0x77,
+	0x0C, 0x20, 0x00, 0x04, 0x00, 0x00, 0x00, 0x00,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x01,
+	0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
+};
+#define US_DIRECTION(x) ((us_direction[x>>3] >> (x & 7)) & 1)
+
+static unsigned char *usb_stor_buf;
+static ccb usb_ccb;
+
+/*
+ * CBI style
+ */
+
+#define US_CBI_ADSC		0
+
+/*
+ * BULK only
+ */
+#define US_BBB_RESET		0xff
+#define US_BBB_GET_MAX_LUN	0xfe
+
+/* Command Block Wrapper */
+typedef struct {
+	__u32		dCBWSignature;
+#	define CBWSIGNATURE	0x43425355
+	__u32		dCBWTag;
+	__u32		dCBWDataTransferLength;
+	__u8		bCBWFlags;
+#	define CBWFLAGS_OUT	0x00
+#	define CBWFLAGS_IN	0x80
+	__u8		bCBWLUN;
+	__u8		bCDBLength;
+#	define CBWCDBLENGTH	16
+	__u8		CBWCDB[CBWCDBLENGTH];
+} umass_bbb_cbw_t;
+#define UMASS_BBB_CBW_SIZE	31
+static __u32 CBWTag;
+
+/* Command Status Wrapper */
+typedef struct {
+	__u32		dCSWSignature;
+#	define CSWSIGNATURE	0x53425355
+	__u32		dCSWTag;
+	__u32		dCSWDataResidue;
+	__u8		bCSWStatus;
+#	define CSWSTATUS_GOOD	0x0
+#	define CSWSTATUS_FAILED 0x1
+#	define CSWSTATUS_PHASE	0x2
+} umass_bbb_csw_t;
+#define UMASS_BBB_CSW_SIZE	13
+
+//#define USB_MAX_STOR_DEV 5 /* GALVEZ: Defined in usb.h */
+static int usb_max_devs; /* number of highest available usb device */
+
+static block_dev_desc_t usb_dev_desc[USB_MAX_STOR_DEV];
+
+struct us_data;
+typedef int (*trans_cmnd)(ccb *cb, struct us_data *data);
+typedef int (*trans_reset)(struct us_data *data);
+
+struct us_data {
+	struct usb_device *pusb_dev;	 /* this usb_device */
+
+	unsigned int	flags;			/* from filter initially */
+	unsigned char	ifnum;			/* interface number */
+	unsigned char	ep_in;			/* in endpoint */
+	unsigned char	ep_out;			/* out ....... */
+	unsigned char	ep_int;			/* interrupt . */
+	unsigned char	subclass;		/* as in overview */
+	unsigned char	protocol;		/* .............. */
+	unsigned char	attention_done;		/* force attn on first cmd */
+	unsigned short	ip_data;		/* interrupt data */
+	int		action;			/* what to do */
+	int		ip_wanted;		/* needed */
+	int		*irq_handle;		/* for USB int requests */
+	unsigned int	irqpipe;	 	/* pipe for release_irq */
+	unsigned char	irqmaxp;		/* max packed for irq Pipe */
+	unsigned char	irqinterval;		/* Intervall for IRQ Pipe */
+	ccb		*srb;			/* current srb */
+	trans_reset	transport_reset;	/* reset routine */
+	trans_cmnd	transport;		/* transport routine */
+};
+
+static struct us_data usb_stor[USB_MAX_STOR_DEV];
+
+#define USB_STOR_TRANSPORT_GOOD	   0
+#define USB_STOR_TRANSPORT_FAILED -1
+#define USB_STOR_TRANSPORT_ERROR  -2
+
+#define DEFAULT_SECTOR_SIZE 512
+
+#define DOS_PART_TBL_OFFSET	0x1be
+#define DOS_PART_MAGIC_OFFSET	0x1fe
+#define DOS_PBR_FSTYPE_OFFSET	0x36
+#define DOS_PBR_MEDIA_TYPE_OFFSET	0x15
+#define DOS_MBR	0
+#define DOS_PBR	1
+#define DOS_FS_TYPE_OFFSET 0x36
+
+typedef struct dos_partition {
+	unsigned char boot_ind;		/* 0x80 - active			*/
+	unsigned char head;		/* starting head			*/
+	unsigned char sector;		/* starting sector			*/
+	unsigned char cyl;		/* starting cylinder			*/
+	unsigned char sys_ind;		/* What partition type			*/
+	unsigned char end_head;		/* end head				*/
+	unsigned char end_sector;	/* end sector				*/
+	unsigned char end_cyl;		/* end cylinder				*/
+	unsigned char start4[4];	/* starting sector counting from 0	*/
+	unsigned char size4[4];		/* nr of sectors in partition		*/
+} dos_partition_t;
+
+typedef struct disk_partition {
+	unsigned long type;
+	unsigned long	start; /* # of first block in partition	*/
+	unsigned long	size;  /* number of blocks in partition	*/
+	unsigned long	blksz; /* block size in bytes			*/
+} disk_partition_t;
+
+//extern unsigned long swap_long(unsigned long val);
+#define le32_to_int(a) swap_32(*(unsigned long *)a)
+
+int usb_stor_get_info(struct usb_device *dev, struct us_data *us, block_dev_desc_t *dev_desc);
+int usb_storage_probe(struct usb_device *dev, unsigned int ifnum, struct us_data *ss);
+unsigned long usb_stor_read(int device, unsigned long blknr, unsigned long blkcnt, void *buffer);
+unsigned long usb_stor_write(int device, unsigned long blknr, unsigned long blkcnt, const void *buffer);
+struct usb_device * usb_get_dev_index(int index);
+void uhci_show_temp_int_td(void);
+
+block_dev_desc_t *usb_stor_get_dev(int idx)
+{
+	return(idx < USB_MAX_STOR_DEV) ? &usb_dev_desc[idx] : NULL;
+}
+
+void init_part(block_dev_desc_t *dev_desc)
+{
+	unsigned char *buffer = (unsigned char *)usb_malloc(DEFAULT_SECTOR_SIZE);
+	if(buffer == NULL)
+		return;
+	if((dev_desc->block_read(dev_desc->dev, 0, 1, (unsigned long *)buffer) != 1)
+	 || (buffer[DOS_PART_MAGIC_OFFSET + 0] != 0x55) || (buffer[DOS_PART_MAGIC_OFFSET + 1] != 0xaa))
+	{
+		usb_free(buffer);
+		return;
+	}
+	dev_desc->part_type = PART_TYPE_DOS;
+	DEBUG_STORAGE("DOS partition table found\r\n");
+#ifdef USB_STOR_DEBUG			
+	{
+		debug_init("usb.log");
+		int j;
+		for(j = 0; j < 512; j++)
+		{
+			if((j & 15) == 0)
+					debug("\r\n%04X ", j);
+			debug("%02X ", buffer[j]);
+			if((j & 15) == 15)
+			{
+				int k;
+					for(k = j-15; k <= j; k++)
+				{
+					if(buffer[k] < ' ' || buffer[k] >= 127)
+						debug(".");
+					else 
+						debug("%c", buffer[k]);
+				}
+			}
+		}
+		debug("\r\n");
+		debug_exit();
+	}			
+#endif	
+	usb_free(buffer);
+}
+
+static inline int is_extended(int part_type)
+{
+	return(part_type == 0x5 || part_type == 0xf || part_type == 0x85);
+}
+
+/*  Print a partition that is relative to its Extended partition table
+ */
+static int get_partition_info_extended(block_dev_desc_t *dev_desc, int ext_part_sector, int relative, int part_num, int which_part, disk_partition_t *info)
+{
+	dos_partition_t *pt;
+	int i;
+	unsigned char *buffer = (unsigned char *)usb_malloc(DEFAULT_SECTOR_SIZE);
+
+	if(buffer == NULL)
+		return -1;
+	if(dev_desc->block_read(dev_desc->dev, ext_part_sector, 1, (unsigned long *)buffer) != 1)
+	{
+		DEBUG_STORAGE("Can't read partition table on %d:%d\r\n", dev_desc->dev, ext_part_sector);
+		usb_free(buffer);
+		return -1;
+	}
+	if(buffer[DOS_PART_MAGIC_OFFSET] != 0x55 || buffer[DOS_PART_MAGIC_OFFSET + 1] != 0xaa)
+	{
+		DEBUG_STORAGE("bad MBR sector signature 0x%02x%02x\n", buffer[DOS_PART_MAGIC_OFFSET], buffer[DOS_PART_MAGIC_OFFSET + 1]);
+		usb_free(buffer);
+		return -1;
+	}
+	/* Print all primary/logical partitions */
+	pt = (dos_partition_t *)(buffer + DOS_PART_TBL_OFFSET);
+	for(i = 0; i < 4; i++, pt++)
+	{
+		/* fdisk does not show the extended partitions that are not in the MBR */
+		if((pt->sys_ind != 0) && (part_num == which_part) && (is_extended(pt->sys_ind) == 0))
+		{
+			info->type = (unsigned long)pt->sys_ind;
+			info->blksz = 512;
+			info->start = ext_part_sector + le32_to_int(pt->start4);
+			info->size = le32_to_int(pt->size4);
+			DEBUG_STORAGE("DOS partition at offset 0x%lx, size 0x%lx, type 0x%x %s\r\n", 
+					info->start, info->size, pt->sys_ind, 
+					(is_extended(pt->sys_ind) ? " Extd" : ""));
+			usb_free(buffer);
+			return 0;
+		}
+		/* Reverse engr the fdisk part# assignment rule! */
+		if((ext_part_sector == 0) || (pt->sys_ind != 0 && !is_extended (pt->sys_ind)))
+			part_num++;
+	}
+	/* Follows the extended partitions */
+	pt = (dos_partition_t *)(buffer + DOS_PART_TBL_OFFSET);
+	for(i = 0; i < 4; i++, pt++)
+	{
+		if(is_extended(pt->sys_ind))
+		{
+			int lba_start = le32_to_int(pt->start4) + relative;
+			usb_free(buffer);
+			return get_partition_info_extended(dev_desc, lba_start, ext_part_sector == 0 ? lba_start : relative, part_num, which_part, info);
+		}
+	}
+	usb_free(buffer);
+	return -1;
+}
+
+int fat_register_device(block_dev_desc_t *dev_desc, int part_no, unsigned long *part_type, unsigned long *part_offset, unsigned long *part_size)
+{
+	unsigned char *buffer;
+	disk_partition_t info;
+
+	if(!dev_desc->block_read)
+		return -1;
+		
+	buffer = (unsigned char *)usb_malloc(DEFAULT_SECTOR_SIZE);
+	if(buffer == NULL)
+		return -1;
+	/* check if we have a MBR (on floppies we have only a PBR) */
+		
+	if(dev_desc->block_read(dev_desc->dev, 0, 1, (unsigned long *)buffer) != 1)
+	{
+		DEBUG_STORAGE("Can't read from device %d\r\n", dev_desc->dev);
+		usb_free(buffer);
+		return -1;
+	}
+	
+	if(buffer[DOS_PART_MAGIC_OFFSET] != 0x55 || buffer[DOS_PART_MAGIC_OFFSET + 1] != 0xaa)
+	{
+		/* no signature found */
+		usb_free(buffer);
+		return -1;
+	}
+	
+	/* First we assume, there is a MBR */
+	if(!get_partition_info_extended(dev_desc, 0, 0, 1, part_no, &info))
+	{
+		*part_type = info.type;
+		*part_offset = info.start;
+		*part_size = info.size;
+	}
+	else if(!strncmp((char *)&buffer[DOS_FS_TYPE_OFFSET], "FAT", 3))
+	{
+		/* ok, we assume we are on a PBR only */
+		*part_type = 0;
+		*part_offset = 0;
+		*part_size = 0;
+	}
+	else
+	{
+		DEBUG_STORAGE("Partition %d not valid on device %d\r\n", part_no, dev_desc->dev);
+		usb_free(buffer);
+		return -1;
+	}
+	usb_free(buffer);
+	return 0;
+}
+
+#if defined(CONFIG_USB_OHCI) || defined(CONFIG_USB_ISP116X_HCD) || defined(CONFIG_USB_ARANYM_HCD)
+
+void dev_print(block_dev_desc_t *dev_desc)
+{
+#ifdef CONFIG_LBA48
+	uint64_t lba512; /* number of blocks if 512bytes block size */
+#else
+	lbaint_t lba512;
+#endif
+	if(dev_desc->type == DEV_TYPE_UNKNOWN)
+	{
+		printf("not available\r\n");
+		DEBUG_STORAGE("not available\r\n");
+		return;
+	}
+	DEBUG_STORAGE("Vendor: %s Rev: %s Prod: %s\r\n", dev_desc->vendor, dev_desc->revision, dev_desc->product);
+	DEBUG_STORAGE("\r\n");
+	printf("Vendor: %s Rev: %s Prod: %s\r\n", dev_desc->vendor, dev_desc->revision, dev_desc->product);
+	printf("\r\n");
+	if((dev_desc->lba * dev_desc->blksz) > 0L)
+	{
+		unsigned long mb, mb_quot, mb_rem, gb, gb_quot, gb_rem;
+		lbaint_t lba = dev_desc->lba;
+		lba512 = (lba * (dev_desc->blksz / 512));
+		mb = (10 * lba512) / 2048;	/* 2048 = (1024 * 1024) / 512 MB */
+		/* round to 1 digit */
+		mb_quot	= mb / 10;
+		mb_rem	= mb - (10 * mb_quot);
+		gb = mb / 1024;
+		gb_quot	= gb / 10;
+		gb_rem	= gb - (10 * gb_quot);
+#ifdef CONFIG_LBA48
+		if(dev_desc->lba48)
+			printf("Supports 48-bit addressing\r\n");
+#endif
+		DEBUG_STORAGE("Capacity: %ld.%ld MB = %ld.%ld GB (%ld x %ld)\r\n", mb_quot, mb_rem, gb_quot, gb_rem, (unsigned long)lba, dev_desc->blksz);
+		printf("Capacity: %ld.%ld MB = %ld.%ld GB (%ld x %ld)\r\n", mb_quot, mb_rem, gb_quot, gb_rem, (unsigned long)lba, dev_desc->blksz);
+	}
+	else {
+		DEBUG_STORAGE("Capacity: not available\r\n");
+		printf("Capacity: not available\r\n");
+	}
+}
+
+/*******************************************************************************
+ * show info on storage devices; 'usb start/init' must be invoked earlier
+ * as we only retrieve structures populated during devices initialization
+ */
+int usb_stor_info(void)
+{
+	int i;
+	if(usb_max_devs > 0)
+	{
+		for(i = 0; i < usb_max_devs; i++)
+		{
+			DEBUG_STORAGE("Device %d: ", i);
+			printf("Device %d: ", i);
+			dev_print(&usb_dev_desc[i]);
+		}
+		return 0;
+	}
+	DEBUG_STORAGE("No storage devices\r\n");
+	printf("No storage devices\r\n");
+	return 1;
+}
+
+#endif /* CONFIG_USB_OHCI */
+
+/*******************************************************************************
+ * scan the usb and reports device info to the user
+ * returns current device or -1 if no
+ */
+int usb_stor_scan(void)
+{
+	unsigned char i;
+	struct usb_device *dev;
+	DEBUG_STORAGE("usb_stor_scan()");		/* Galvez: Debug trace */
+	if(usb_stor_buf == NULL)
+		usb_stor_buf = (unsigned char *)usb_malloc(512);
+	if(usb_stor_buf == NULL)
+		return -1;
+	memset(usb_stor_buf, 0, sizeof(usb_stor_buf));
+	usb_disable_asynch(1); /* asynch transfer not allowed */
+	for(i = 0; i < USB_MAX_STOR_DEV; i++)
+	{
+		memset(&usb_dev_desc[i], 0, sizeof(block_dev_desc_t));
+		usb_dev_desc[i].target = 0xff;
+		usb_dev_desc[i].if_type = IF_TYPE_USB;
+		usb_dev_desc[i].dev = i;
+		usb_dev_desc[i].part_type = PART_TYPE_UNKNOWN;
+		usb_dev_desc[i].block_read = usb_stor_read;
+		usb_dev_desc[i].block_write = usb_stor_write;
+	}
+	usb_max_devs = 0;
+	for(i = 0; i < USB_MAX_DEVICE; i++)
+	{
+		dev = usb_get_dev_index(i); /* get device */
+		if(dev == NULL)
+			break; /* no more devices avaiable */
+		DEBUG_STORAGE("Device %d\r\n", i);
+		if(usb_storage_probe(dev, 0, &usb_stor[usb_max_devs]))
+		{
+			/* ok, it is a storage devices
+			 * get info and fill it in
+			 */
+			if(usb_stor_get_info(dev, &usb_stor[usb_max_devs], &usb_dev_desc[usb_max_devs]))
+				usb_max_devs++;
+		}
+		/* if storage device */
+		if(usb_max_devs == USB_MAX_STOR_DEV)
+		{
+			printf("Max USB Storage Device reached: %d stopping\r\n", usb_max_devs);
+			break;
+		}
+	} /* for */
+	usb_disable_asynch(0); /* asynch transfer allowed */
+	DEBUG_STORAGE("%d Storage Device(s) found\r\n", usb_max_devs);
+	printf("%d Storage Device(s) found\r\n", usb_max_devs);
+	if(usb_max_devs > 0)
+		return 0;
+	return -1;
+}
+
+static int usb_stor_irq(struct usb_device *dev)
+{
+	struct us_data *us;
+	us = (struct us_data *)dev->privptr;
+	if(us->ip_wanted)
+		us->ip_wanted = 0;
+	return 0;
+}
+
+#ifdef USB_STOR_DEBUG
+
+static void usb_show_srb(ccb *pccb)
+{
+	int i;
+	debug_init("usb.log");
+	debug("SRB: len %d datalen 0x%lX\r\n ", pccb->cmdlen, pccb->datalen);
+	for (i = 0; i < 12; i++)
+		debug("%02X ", pccb->cmd[i]);
+	debug("\r\n");
+	debug_exit();
+}
+
+static void display_int_status(unsigned long tmp)
+{
+	debug_init("usb.log");
+	debug("Status: %s %s %s %s %s %s %s\r\n",
+		(tmp & USB_ST_ACTIVE) ? "Active" : "",
+		(tmp & USB_ST_STALLED) ? "Stalled" : "",
+		(tmp & USB_ST_BUF_ERR) ? "Buffer Error" : "",
+		(tmp & USB_ST_BABBLE_DET) ? "Babble Det" : "",
+		(tmp & USB_ST_NAK_REC) ? "NAKed" : "",
+		(tmp & USB_ST_CRC_ERR) ? "CRC Error" : "",
+		(tmp & USB_ST_BIT_ERR) ? "Bitstuff Error" : "");
+	debug_exit();
+}
+
+#endif
+
+/***********************************************************************
+ * Data transfer routines
+ ***********************************************************************/
+
+static int us_one_transfer(struct us_data *us, int pipe, char *buf, int length)
+{
+	int max_size;
+	int this_xfer;
+	int result;
+	int partial;
+	int maxtry;
+	int stat;
+	/* determine the maximum packet size for these transfers */
+	max_size = usb_maxpacket(us->pusb_dev, pipe) * 16;
+	/* while we have data left to transfer */
+	while(length)
+	{
+		/* calculate how long this will be -- maximum or a remainder */
+		this_xfer = length > max_size ? max_size : length;
+		length -= this_xfer;
+		/* setup the retry counter */
+		maxtry = 10;
+		/* set up the transfer loop */
+		do
+		{
+			/* transfer the data */
+			DEBUG_STORAGE("Bulk xfer 0x%x(%d) try #%d\r\n", (unsigned int)buf, this_xfer, 11 - maxtry);
+			result = usb_bulk_msg(us->pusb_dev, pipe, buf, this_xfer, &partial, USB_CNTL_TIMEOUT * 5);
+			DEBUG_STORAGE("bulk_msg returned %d xferred %d/%d\r\n", result, partial, this_xfer);
+			if(us->pusb_dev->status != 0)
+			{
+				/* if we stall, we need to clear it before we go on */
+#ifdef USB_STOR_DEBUG
+				display_int_status(us->pusb_dev->status);
+#endif
+				if(us->pusb_dev->status & USB_ST_STALLED)
+				{
+					DEBUG_STORAGE("stalled ->clearing endpoint halt for pipe 0x%x\r\n", pipe);
+					stat = us->pusb_dev->status;
+					usb_clear_halt(us->pusb_dev, pipe);
+					us->pusb_dev->status = stat;
+					if(this_xfer == partial)
+					{
+						DEBUG_STORAGE("bulk transferred with error %lX, but data ok\r\n", us->pusb_dev->status);
+						return 0;
+					}
+					else
+						return result;
+				}
+				if(us->pusb_dev->status & USB_ST_NAK_REC)
+				{
+					DEBUG_STORAGE("Device NAKed bulk_msg\r\n");
+					return result;
+				}
+				DEBUG_STORAGE("bulk transferred with error");
+				if(this_xfer == partial)
+				{
+					DEBUG_STORAGE(" %ld, but data ok\r\n", us->pusb_dev->status);
+					return 0;
+				}
+				/* if our try counter reaches 0, bail out */
+				DEBUG_STORAGE(" %ld, data %d\r\n", us->pusb_dev->status, partial);
+				if(!maxtry--)
+					return result;
+			}
+			/* update to show what data was transferred */
+			this_xfer -= partial;
+			buf += partial;
+			/* continue until this transfer is done */
+		} while (this_xfer);
+	}
+	/* if we get here, we're done and successful */
+	return 0;
+}
+
+static int usb_stor_BBB_reset(struct us_data *us)
+{
+	int result;
+	unsigned int pipe;
+	/*
+	 * Reset recovery (5.3.4 in Universal Serial Bus Mass Storage Class)
+	 *
+	 * For Reset Recovery the host shall issue in the following order:
+	 * a) a Bulk-Only Mass Storage Reset
+	 * b) a Clear Feature HALT to the Bulk-In endpoint
+	 * c) a Clear Feature HALT to the Bulk-Out endpoint
+	 *
+	 * This is done in 3 steps.
+	 *
+	 * If the reset doesn't succeed, the device should be port reset.
+	 *
+	 * This comment stolen from FreeBSD's /sys/dev/usb/umass.c.
+	 */
+	DEBUG_STORAGE("BBB_reset\r\n");
+	result = usb_control_msg(us->pusb_dev, usb_sndctrlpipe(us->pusb_dev, 0),
+	 US_BBB_RESET, USB_TYPE_CLASS | USB_RECIP_INTERFACE, 0, us->ifnum, 0, 0, USB_CNTL_TIMEOUT * 5);
+	if((result < 0) && (us->pusb_dev->status & USB_ST_STALLED))
+	{
+		DEBUG_STORAGE("RESET:stall\r\n");
+		return -1;
+	}
+	/* long wait for reset */
+	wait_ms(150);
+	DEBUG_STORAGE("BBB_reset result %d: status %lX reset\r\n", result, us->pusb_dev->status);
+	pipe = usb_rcvbulkpipe(us->pusb_dev, us->ep_in);
+	result = usb_clear_halt(us->pusb_dev, pipe);
+	/* long wait for reset */
+	wait_ms(150);
+	DEBUG_STORAGE("BBB_reset result %d: status %lX clearing IN endpoint\r\n", result, us->pusb_dev->status);
+	/* long wait for reset */
+	pipe = usb_sndbulkpipe(us->pusb_dev, us->ep_out);
+	result = usb_clear_halt(us->pusb_dev, pipe);
+	wait_ms(150);
+	DEBUG_STORAGE("BBB_reset result %d: status %lX clearing OUT endpoint\r\n", result, us->pusb_dev->status);
+	DEBUG_STORAGE("BBB_reset done\r\n");
+	return 0;
+}
+
+/* FIXME: this reset function doesn't really reset the port, and it
+ * should. Actually it should probably do what it's doing here, and
+ * reset the port physically
+ */
+static int usb_stor_CB_reset(struct us_data *us)
+{
+	unsigned char cmd[12];
+	int result;
+	DEBUG_STORAGE("CB_reset\r\n");
+	memset(cmd, 0xff, sizeof(cmd));
+	cmd[0] = SCSI_SEND_DIAG;
+	cmd[1] = 4;
+	result = usb_control_msg(us->pusb_dev, usb_sndctrlpipe(us->pusb_dev, 0), 
+	 US_CBI_ADSC, USB_TYPE_CLASS | USB_RECIP_INTERFACE, 0, us->ifnum, cmd, sizeof(cmd), USB_CNTL_TIMEOUT * 5);
+	/* long wait for reset */
+	wait_ms(1500);
+	DEBUG_STORAGE("CB_reset result %d: status %lX clearing endpoint halt\r\n", result, us->pusb_dev->status);
+	usb_clear_halt(us->pusb_dev, usb_rcvbulkpipe(us->pusb_dev, us->ep_in));
+	usb_clear_halt(us->pusb_dev, usb_rcvbulkpipe(us->pusb_dev, us->ep_out));
+	DEBUG_STORAGE("CB_reset done\r\n");
+	return 0;
+}
+
+/*
+ * Set up the command for a BBB device. Note that the actual SCSI
+ * command is copied into cbw.CBWCDB.
+ */
+int usb_stor_BBB_comdat(ccb *srb, struct us_data *us)
+{
+	int result;
+	int actlen;
+	int dir_in;
+	unsigned int pipe;
+	umass_bbb_cbw_t *cbw = (umass_bbb_cbw_t *)usb_malloc(sizeof(umass_bbb_cbw_t));
+	if(cbw == NULL)
+	{
+		DEBUG_STORAGE("usb_stor_BBB_comdat: out of memory\r\n");
+		return -1;
+	}
+	dir_in = US_DIRECTION(srb->cmd[0]);
+	DEBUG_STORAGE("usb_stor_BBB_comdat: dir_in: %d\r\n",dir_in);
+#ifdef BBB_COMDAT_TRACE
+	debug_init ("usb.log");
+	debug("dir %d lun %d cmdlen %d cmd %p datalen %d pdata %p\r\n", dir_in, srb->lun, srb->cmdlen, srb->cmd, srb->datalen, srb->pdata);
+	if(srb->cmdlen)
+	{
+		for(result = 0; result < srb->cmdlen; result++)
+			debug("cmd[%d] %#x ", result, srb->cmd[result]);
+		debug("\r\n");
+	}
+	debug_exit( );
+#endif
+	/* sanity checks */
+	if(!(srb->cmdlen <= CBWCDBLENGTH))
+	{
+		DEBUG_STORAGE("usb_stor_BBB_comdat: cmdlen too large\r\n");
+		usb_free(cbw);
+		return -1;
+	}
+	/* always OUT to the ep */
+	pipe = usb_sndbulkpipe(us->pusb_dev, us->ep_out);
+	cbw->dCBWSignature = cpu_to_le32(CBWSIGNATURE);
+	cbw->dCBWTag = cpu_to_le32(CBWTag++);
+	cbw->dCBWDataTransferLength = cpu_to_le32(srb->datalen);
+	cbw->bCBWFlags = (dir_in ? CBWFLAGS_IN : CBWFLAGS_OUT);
+	cbw->bCBWLUN = srb->lun;
+	cbw->bCDBLength = srb->cmdlen;
+	/* copy the command data into the CBW command data buffer */
+	/* DST SRC LEN!!! */
+	memcpy(&cbw->CBWCDB, srb->cmd, srb->cmdlen);
+
+	result = usb_bulk_msg(us->pusb_dev, pipe, cbw, UMASS_BBB_CBW_SIZE, &actlen, USB_CNTL_TIMEOUT * 5);
+	if(result < 0)
+	{	DEBUG_STORAGE("usb_stor_BBB_comdat:usb_bulk_msg error\r\n");}
+	usb_free(cbw);
+	return result;
+}
+
+/* FIXME: we also need a CBI_command which sets up the completion
+ * interrupt, and waits for it
+ */
+int usb_stor_CB_comdat(ccb *srb, struct us_data *us)
+{
+	int result = 0;
+	int dir_in, retry;
+	unsigned int pipe;
+	unsigned long status;
+	retry = 5;
+	dir_in = US_DIRECTION(srb->cmd[0]);
+	if(dir_in)
+		pipe = usb_rcvbulkpipe(us->pusb_dev, us->ep_in);
+	else
+		pipe = usb_sndbulkpipe(us->pusb_dev, us->ep_out);
+	while(retry--)
+	{
+		DEBUG_STORAGE("CBI gets a command: Try %d\r\n", 5 - retry);
+#ifdef USB_STOR_DEBUG
+		usb_show_srb(srb);
+#endif
+		/* let's send the command via the control pipe */
+		result = usb_control_msg(us->pusb_dev, usb_sndctrlpipe(us->pusb_dev , 0),
+		 US_CBI_ADSC, USB_TYPE_CLASS | USB_RECIP_INTERFACE, 0, us->ifnum, srb->cmd, srb->cmdlen, USB_CNTL_TIMEOUT * 5);
+		DEBUG_STORAGE("CB_transport: control msg returned %d, status %lX\r\n", result, us->pusb_dev->status);
+		/* check the return code for the command */
+		if(result < 0)
+		{
+			if(us->pusb_dev->status & USB_ST_STALLED)
+			{
+				status = us->pusb_dev->status;
+				DEBUG_STORAGE(" stall during command found, clear pipe\r\n");
+				usb_clear_halt(us->pusb_dev, usb_sndctrlpipe(us->pusb_dev, 0));
+				us->pusb_dev->status = status;
+			}
+			DEBUG_STORAGE(" error during command %02X Stat = %lX\r\n", srb->cmd[0], us->pusb_dev->status);
+			return result;
+		}
+		/* transfer the data payload for this command, if one exists*/
+		DEBUG_STORAGE("CB_transport: control msg returned %d, direction is %s to go 0x%lx\r\n", result, dir_in ? "IN" : "OUT", srb->datalen);
+		if(srb->datalen)
+		{
+			result = us_one_transfer(us, pipe, (char *)srb->pdata, srb->datalen);
+			DEBUG_STORAGE("CBI attempted to transfer data, result is %d status %lX, len %d\r\n", result, us->pusb_dev->status, us->pusb_dev->act_len);
+			if(!(us->pusb_dev->status & USB_ST_NAK_REC))
+				break;
+		} /* if(srb->datalen) */
+		else
+			break;
+	}
+	/* return result */
+	return result;
+}
+
+int usb_stor_CBI_get_status(ccb *srb, struct us_data *us)
+{
+	int timeout;
+	us->ip_wanted = 1;
+	submit_int_msg(us->pusb_dev, us->irqpipe, (void *) &us->ip_data, us->irqmaxp, us->irqinterval);
+	timeout = 1000;
+	while(timeout--)
+	{
+		if((volatile int *) us->ip_wanted == 0)
+			break;
+		wait_ms(10);
+	}
+	if(us->ip_wanted)
+	{
+		DEBUG_STORAGE("Did not get interrupt on CBI\r\n");
+		printf("Did not get interrupt on CBI\r\n");
+		us->ip_wanted = 0;
+		return USB_STOR_TRANSPORT_ERROR;
+	}
+	DEBUG_STORAGE("Got interrupt data 0x%x, transfered %d status 0x%lX\r\n", us->ip_data, us->pusb_dev->irq_act_len, us->pusb_dev->irq_status);
+	/* UFI gives us ASC and ASCQ, like a request sense */
+	if(us->subclass == US_SC_UFI)
+	{
+		if(srb->cmd[0] == SCSI_REQ_SENSE || srb->cmd[0] == SCSI_INQUIRY)
+			return USB_STOR_TRANSPORT_GOOD; /* Good */
+		else if(us->ip_data)
+			return USB_STOR_TRANSPORT_FAILED;
+		else
+			return USB_STOR_TRANSPORT_GOOD;
+	}
+	/* otherwise, we interpret the data normally */
+	switch(us->ip_data)
+	{
+		case 0x0001: return USB_STOR_TRANSPORT_GOOD;
+		case 0x0002: return USB_STOR_TRANSPORT_FAILED;
+		default: return USB_STOR_TRANSPORT_ERROR;
+	}
+	return USB_STOR_TRANSPORT_ERROR;
+}
+
+#define USB_TRANSPORT_UNKNOWN_RETRY 5
+#define USB_TRANSPORT_NOT_READY_RETRY 10
+
+/* clear a stall on an endpoint - special for BBB devices */
+int usb_stor_BBB_clear_endpt_stall(struct us_data *us, __u8 endpt)
+{
+	int result;
+	/* ENDPOINT_HALT = 0, so set value to 0 */
+	result = usb_control_msg(us->pusb_dev, usb_sndctrlpipe(us->pusb_dev, 0),
+	 USB_REQ_CLEAR_FEATURE, USB_RECIP_ENDPOINT, 0, endpt, 0, 0, USB_CNTL_TIMEOUT * 5);
+	return result;
+}
+
+int usb_stor_BBB_transport(ccb *srb, struct us_data *us)
+{
+	int result, retry;
+	int dir_in;
+	int actlen, data_actlen;
+	unsigned int pipe, pipein, pipeout;
+//	DEBUG_STORAGE ( );  /* GALVEZ: DEBUG */
+#ifdef BBB_XPORT_TRACE
+	unsigned char *ptr;
+	int idx;
+#endif
+	umass_bbb_csw_t *csw = (umass_bbb_csw_t *)usb_malloc(sizeof(umass_bbb_csw_t));
+	if(csw == NULL)
+	{
+		DEBUG_STORAGE("out of memory\r\n");
+		return USB_STOR_TRANSPORT_FAILED;
+	}
+	dir_in = US_DIRECTION(srb->cmd[0]);
+	/* COMMAND phase */
+	DEBUG_STORAGE("COMMAND phase\n");
+	result = usb_stor_BBB_comdat(srb, us);
+	if(result < 0)
+	{
+		DEBUG_STORAGE("failed to send CBW status %ld\r\n", us->pusb_dev->status);
+		usb_stor_BBB_reset(us);
+		usb_free(csw);
+		return USB_STOR_TRANSPORT_FAILED;
+	}
+	wait_ms(5);
+	pipein = usb_rcvbulkpipe(us->pusb_dev, us->ep_in);
+	pipeout = usb_sndbulkpipe(us->pusb_dev, us->ep_out);
+	/* DATA phase + error handling */
+	data_actlen = 0;
+	/* no data, go immediately to the STATUS phase */
+	if(srb->datalen == 0)
+		goto st;
+	DEBUG_STORAGE("DATA phase\n");
+	if(dir_in)
+		pipe = pipein;
+	else
+		pipe = pipeout;
+	result = usb_bulk_msg(us->pusb_dev, pipe, srb->pdata, srb->datalen, &data_actlen, USB_CNTL_TIMEOUT * 5);
+	/* special handling of STALL in DATA phase */
+	if((result < 0) && (us->pusb_dev->status & USB_ST_STALLED))
+	{
+		DEBUG_STORAGE("DATA:stall\r\n");
+		/* clear the STALL on the endpoint */
+		result = usb_stor_BBB_clear_endpt_stall(us, dir_in ? us->ep_in : us->ep_out);
+		if(result >= 0)
+			/* continue on to STATUS phase */
+			goto st;
+	}
+	if(result < 0)
+	{
+		DEBUG_STORAGE("usb_bulk_msg error status %ld\r\n", us->pusb_dev->status);
+		usb_stor_BBB_reset(us);
+		usb_free(csw);
+		return USB_STOR_TRANSPORT_FAILED;
+	}
+#ifdef BBB_XPORT_TRACE
+	debug_init("usb.log");
+	for(idx = 0; idx < data_actlen; idx++)
+		debug("pdata[%d] %#x ", idx, srb->pdata[idx]);
+	debug("\r\n");
+	debug_exit( );
+#endif
+	/* STATUS phase + error handling */
+st:
+	retry = 0;
+again:
+	DEBUG_STORAGE("STATUS phase\n");
+	result = usb_bulk_msg(us->pusb_dev, pipein, csw, UMASS_BBB_CSW_SIZE, &actlen, USB_CNTL_TIMEOUT*5);
+	/* special handling of STALL in STATUS phase */
+
+	if((result < 0) && (retry < 1) && (us->pusb_dev->status & USB_ST_STALLED))
+	{
+		DEBUG_STORAGE("STATUS:stall\r\n");
+		/* clear the STALL on the endpoint */
+		result = usb_stor_BBB_clear_endpt_stall(us, us->ep_in);
+		if(result >= 0 && (retry++ < 1))
+			/* do a retry */
+			goto again;
+	}
+
+	if(result < 0)
+	{
+		DEBUG_STORAGE("usb_bulk_msg error status %ld\r\n", us->pusb_dev->status);
+		usb_stor_BBB_reset(us);
+		usb_free(csw);
+		return USB_STOR_TRANSPORT_FAILED;
+	}
+#ifdef BBB_XPORT_TRACE
+	debug_init("usb.log");
+	ptr = (unsigned char *)csw;
+	for(idx = 0; idx < UMASS_BBB_CSW_SIZE; idx++)
+		debug("ptr[%d] %#x ", idx, ptr[idx]);
+	debug("\r\n");
+	debug_exit( );
+#endif
+	/* misuse pipe to get the residue */
+	pipe = le32_to_cpu(csw->dCSWDataResidue);
+	if(pipe == 0 && srb->datalen != 0 && srb->datalen - data_actlen != 0)
+		pipe = srb->datalen - data_actlen;
+	if(CSWSIGNATURE != le32_to_cpu(csw->dCSWSignature))
+	{
+		DEBUG_STORAGE("!CSWSIGNATURE\r\n");
+		usb_stor_BBB_reset(us);
+		usb_free(csw);
+		return USB_STOR_TRANSPORT_FAILED;
+	}
+	else if((CBWTag - 1) != le32_to_cpu(csw->dCSWTag))
+	{
+		DEBUG_STORAGE("!Tag\r\n");
+		usb_stor_BBB_reset(us);
+		usb_free(csw);
+		return USB_STOR_TRANSPORT_FAILED;
+	}
+	else if(csw->bCSWStatus > CSWSTATUS_PHASE)
+	{
+		DEBUG_STORAGE(">PHASE\r\n");
+		usb_stor_BBB_reset(us);
+		usb_free(csw);
+		return USB_STOR_TRANSPORT_FAILED;
+	}
+	else if(csw->bCSWStatus == CSWSTATUS_PHASE)
+	{
+		DEBUG_STORAGE("=PHASE\r\n");
+		usb_stor_BBB_reset(us);
+		usb_free(csw);
+		return USB_STOR_TRANSPORT_FAILED;
+	}
+	else if(data_actlen > srb->datalen)
+	{
+		DEBUG_STORAGE("transferred %dB instead of %ldB\r\n", data_actlen, srb->datalen);
+		usb_free(csw);
+		return USB_STOR_TRANSPORT_FAILED;
+	}
+	else if(csw->bCSWStatus == CSWSTATUS_FAILED)
+	{
+//		printf("FAILED\r\n");      /* GALVEZ: DEBUG */
+		DEBUG_STORAGE("FAILED\r\n");
+		usb_free(csw);
+		return USB_STOR_TRANSPORT_FAILED;
+	}
+	usb_free(csw);;
+	return result;
+}
+
+int usb_stor_CB_transport(ccb *srb, struct us_data *us)
+{
+	int result, status;
+	ccb *psrb;
+	ccb reqsrb;
+	int retry, notready;
+	psrb = &reqsrb;
+	status = USB_STOR_TRANSPORT_GOOD;
+	retry = 0;
+	notready = 0;
+	/* issue the command */
+do_retry:
+	result = usb_stor_CB_comdat(srb, us);
+	DEBUG_STORAGE("command / Data returned %d, status %lX\r\n", result, us->pusb_dev->status);
+	/* if this is an CBI Protocol, get IRQ */
+	if(us->protocol == US_PR_CBI)
+	{
+		status = usb_stor_CBI_get_status(srb, us);
+		/* if the status is error, report it */
+		if(status == USB_STOR_TRANSPORT_ERROR)
+		{
+			DEBUG_STORAGE(" USB CBI Command Error\r\n");
+			return status;
+		}
+		srb->sense_buf[12] = (unsigned char)(us->ip_data >> 8);
+		srb->sense_buf[13] = (unsigned char)(us->ip_data & 0xff);
+		if(!us->ip_data)
+		{
+			/* if the status is good, report it */
+			if(status == USB_STOR_TRANSPORT_GOOD)
+			{
+				DEBUG_STORAGE(" USB CBI Command Good\r\n");
+				return status;
+			}
+		}
+	}
+	/* do we have to issue an auto request? */
+	/* HERE we have to check the result */
+	if((result < 0) && !(us->pusb_dev->status & USB_ST_STALLED))
+	{
+		DEBUG_STORAGE("ERROR %lX\r\n", us->pusb_dev->status);
+		us->transport_reset(us);
+		return USB_STOR_TRANSPORT_ERROR;
+	}
+	if((us->protocol == US_PR_CBI) && ((srb->cmd[0] == SCSI_REQ_SENSE) || (srb->cmd[0] == SCSI_INQUIRY)))
+	{
+		/* do not issue an autorequest after request sense */
+		DEBUG_STORAGE("No auto request and good\r\n");
+		return USB_STOR_TRANSPORT_GOOD;
+	}
+	/* issue an request_sense */
+	memset(&psrb->cmd[0], 0, 12);
+	psrb->cmd[0] = SCSI_REQ_SENSE;
+	psrb->cmd[1] = srb->lun << 5;
+	psrb->cmd[4] = 18;
+	psrb->datalen = 18;
+	psrb->pdata = &srb->sense_buf[0];
+	psrb->cmdlen = 12;
+	/* issue the command */
+	result = usb_stor_CB_comdat(psrb, us);
+	DEBUG_STORAGE("auto request returned %d\r\n", result);
+	/* if this is an CBI Protocol, get IRQ */
+	if(us->protocol == US_PR_CBI)
+		status = usb_stor_CBI_get_status(psrb, us);
+	if((result < 0) && !(us->pusb_dev->status & USB_ST_STALLED))
+	{
+		DEBUG_STORAGE(" AUTO REQUEST ERROR %ld\r\n", us->pusb_dev->status);
+		return USB_STOR_TRANSPORT_ERROR;
+	}
+	DEBUG_STORAGE("autorequest returned 0x%02X 0x%02X 0x%02X 0x%02X\r\n", srb->sense_buf[0], srb->sense_buf[2], srb->sense_buf[12], srb->sense_buf[13]);
+	/* Check the auto request result */
+	if((srb->sense_buf[2] == 0) && (srb->sense_buf[12] == 0) && (srb->sense_buf[13] == 0))
+	{
+		/* ok, no sense */
+		return USB_STOR_TRANSPORT_GOOD;
+	}
+	/* Check the auto request result */
+	switch(srb->sense_buf[2])
+	{
+		case 0x01:
+			/* Recovered Error */
+			return USB_STOR_TRANSPORT_GOOD;
+		case 0x02: /* Not Ready */
+			if(notready++ > USB_TRANSPORT_NOT_READY_RETRY)
+			{
+				DEBUG_STORAGE("cmd 0x%02X returned 0x%02X 0x%02X 0x%02X 0x%02X (NOT READY)\r\n", srb->cmd[0], srb->sense_buf[0], srb->sense_buf[2], srb->sense_buf[12], srb->sense_buf[13]);
+				return USB_STOR_TRANSPORT_FAILED;
+			}
+			else
+			{
+				wait_ms(100);
+				goto do_retry;
+			}
+			break;
+		default:
+			if(retry++ > USB_TRANSPORT_UNKNOWN_RETRY)
+			{
+				DEBUG_STORAGE("cmd 0x%02X returned 0x%02X 0x%02X 0x%02X 0x%02X\r\n", 
+					       srb->cmd[0], srb->sense_buf[0], srb->sense_buf[2],
+					       srb->sense_buf[12], srb->sense_buf[13]);
+				return USB_STOR_TRANSPORT_FAILED;
+			}
+			else
+				goto do_retry;
+			break;
+	}
+	return USB_STOR_TRANSPORT_FAILED;
+}
+
+static int usb_inquiry(ccb *srb, struct us_data *ss)
+{
+	DEBUG_STORAGE ("usb_inquiry()");  /* GALVEZ: DEBUG */
+
+	int retry, i;
+	retry = 5;
+	do
+	{
+		memset(&srb->cmd[0], 0, 12);
+		srb->cmd[0] = SCSI_INQUIRY;
+		srb->cmd[4] = 36;
+		srb->datalen = 36;
+		srb->cmdlen = 12;
+		i = ss->transport(srb, ss);
+		DEBUG_STORAGE("inquiry returns %d\r\n", i);
+		if(i == 0)
+			break;
+	}
+	while(retry--);
+	if(!retry)
+	{
+		DEBUG_STORAGE("error in inquiry\r\n");
+		printf("error in inquiry\r\n");
+		return -1;
+	}
+	return 0;
+}
+
+static int usb_request_sense(ccb *srb, struct us_data *ss)
+{
+	DEBUG_STORAGE("usb_request_sense()");  /* GALVEZ: DEBUG */
+	char *ptr;
+	ptr = (char *)srb->pdata;
+	memset(&srb->cmd[0], 0, /*12*/6);	/* GALVEZ: DEBUG: DEFAULT 12 */
+	srb->cmd[0] = SCSI_REQ_SENSE;
+	srb->cmd[4] = 18;
+	srb->datalen = 18;
+	srb->pdata = &srb->sense_buf[0];
+	srb->cmdlen = /*12*/6;		/* GALVEZ: DEBUG: DEFAULT 12 */
+	ss->transport(srb, ss);
+	DEBUG_STORAGE("Request Sense returned %02X %02X %02X\r\n", srb->sense_buf[2], srb->sense_buf[12], srb->sense_buf[13]);
+	srb->pdata = (unsigned char *)ptr;
+	return 0;
+}
+
+static int usb_test_unit_ready(ccb *srb, struct us_data *ss)
+{
+	int retries = 10;
+	DEBUG_STORAGE("usb_test_unit_ready()");  /* GALVEZ: DEBUG */
+	do
+	{
+		memset(&srb->cmd[0], 0, /*12*/ 6);	/* GALVEZ: DEBUG: DEFAULT 12 */ 
+		srb->cmd[0] = SCSI_TST_U_RDY;
+		srb->datalen = 0;
+		srb->cmdlen = /*12*/ 6;			/* GALVEZ: DEBUG: DEFAULT 12 */
+		if(ss->transport(srb, ss) == USB_STOR_TRANSPORT_GOOD)
+			return 0;
+		usb_request_sense(srb, ss);
+		wait_ms(100);
+	}
+	while(retries--);
+	return -1;
+}
+
+static int usb_read_capacity(ccb *srb, struct us_data *ss)
+{
+	int retry;
+	/* XXX retries */
+	retry = 3;
+	DEBUG_STORAGE("usb_read_capacity()");  /* GALVEZ: DEBUG */
+	do
+	{
+		memset(&srb->cmd[0], 0, 12);
+		srb->cmd[0] = SCSI_RD_CAPAC;
+		srb->datalen = 8;
+		srb->cmdlen = 12;
+		if(ss->transport(srb, ss) == USB_STOR_TRANSPORT_GOOD)
+			return 0;
+	}
+	while(retry--);
+	return -1;
+}
+
+static int usb_read_10(ccb *srb, struct us_data *ss, unsigned long start, unsigned short blocks)
+{
+	memset(&srb->cmd[0], 0, 12);
+	srb->cmd[0] = SCSI_READ10;
+	srb->cmd[2] = ((unsigned char) (start >> 24)) & 0xff;
+	srb->cmd[3] = ((unsigned char) (start >> 16)) & 0xff;
+	srb->cmd[4] = ((unsigned char) (start >> 8)) & 0xff;
+	srb->cmd[5] = ((unsigned char) (start)) & 0xff;
+	srb->cmd[7] = ((unsigned char) (blocks >> 8)) & 0xff;
+	srb->cmd[8] = (unsigned char) blocks & 0xff;
+	srb->cmdlen = 12;
+	DEBUG_STORAGE("read10: start %lx blocks %x\r\n", start, blocks);
+	return ss->transport(srb, ss);
+}
+
+static int usb_write_10(ccb *srb, struct us_data *ss, unsigned long start, unsigned short blocks)
+{
+	memset(&srb->cmd[0], 0, 12);
+	srb->cmd[0] = SCSI_WRITE10;
+	srb->cmd[2] = ((unsigned char) (start >> 24)) & 0xff;
+	srb->cmd[3] = ((unsigned char) (start >> 16)) & 0xff;
+	srb->cmd[4] = ((unsigned char) (start >> 8)) & 0xff;
+	srb->cmd[5] = ((unsigned char) (start)) & 0xff;
+	srb->cmd[7] = ((unsigned char) (blocks >> 8)) & 0xff;
+	srb->cmd[8] = (unsigned char) blocks & 0xff;
+	srb->cmdlen = 12;
+	DEBUG_STORAGE("write10: start %lx blocks %x\r\n", start, blocks);
+	return ss->transport(srb, ss);
+}
+
+#ifdef CONFIG_USB_BIN_FIXUP
+/*
+ * Some USB storage devices queried for SCSI identification data respond with
+ * binary strings, which if output to the console freeze the terminal. The
+ * workaround is to modify the vendor and product strings read from such
+ * device with proper values (as reported by 'usb info').
+ *
+ * Vendor and product length limits are taken from the definition of
+ * block_dev_desc_t in include/part.h.
+ */
+static void usb_bin_fixup(struct usb_device_descriptor descriptor, unsigned char vendor[], unsigned char product[])
+{
+	const unsigned char max_vendor_len = 40;
+	const unsigned char max_product_len = 20;
+	if(descriptor.idVendor == 0x0424 && descriptor.idProduct == 0x223a)
+	{
+		strncpy((char *)vendor, "SMSC", max_vendor_len);
+		strncpy((char *)product, "Flash Media Cntrller", max_product_len);
+	}
+}
+#endif /* CONFIG_USB_BIN_FIXUP */
+
+#define USB_MAX_READ_BLK 20
+
+unsigned long usb_stor_read(int device, unsigned long blknr, unsigned long blkcnt, void *buffer)
+{
+	unsigned long start, blks, buf_addr;
+	unsigned short smallblks;
+	struct usb_device *dev;
+	int retry, i;
+	ccb *srb = &usb_ccb;
+
+
+	if(blkcnt == 0)
+		return 0;
+	device &= 0xff;	
+	/* Setup  device */
+//	printf ("blknr: %x\n\r", blknr);	/* Galvez: Debug */
+	DEBUG_STORAGE("usb_read: dev %d \r\n", device);
+	dev = NULL;
+#ifdef SUPERVISOR
+	int p = 0;	
+	/* GALVEZ: Acces to register in Supervisor */
+	if (!(Super(SUP_INQUIRE))){
+		p = SuperFromUser();
+	}
+#endif
+		
+	for(i = 0; i < USB_MAX_DEVICE; i++)
+	{
+		dev = usb_get_dev_index(i);
+		if(dev == NULL){
+#ifdef SUPERVISOR
+			/* GALVEZ: come back to user mode */
+			if ((Super(SUP_INQUIRE)) && (p)){
+				SuperToUser(p);
+			}
+#endif
+			return 0;
+		}
+		if(dev->devnum == usb_dev_desc[device].target)
+			break;
+	}
+	usb_disable_asynch(1); /* asynch transfer not allowed */
+	srb->lun = usb_dev_desc[device].lun;
+	buf_addr = (unsigned long)buffer;
+	start = blknr;
+	blks = blkcnt;
+
+	if(usb_test_unit_ready(srb, (struct us_data *)dev->privptr))
+	{
+		DEBUG_STORAGE("Device NOT ready\r\n   Request Sense returned %02X %02X %02X\r\n", srb->sense_buf[2], srb->sense_buf[12], srb->sense_buf[13]);
+		printf("Device NOT ready\r\n   Request Sense returned %02X %02X %02X\r\n", srb->sense_buf[2], srb->sense_buf[12], srb->sense_buf[13]);
+#ifdef SUPERVISOR
+		/* GALVEZ: come back to user mode */
+		if ((Super(SUP_INQUIRE)) && (p)){
+			SuperToUser(p);
+		}
+#endif
+		return 0;
+	}
+
+	DEBUG_STORAGE("usb_read: dev %d startblk %lx, blccnt %lx buffer %lx\r\n", device, start, blks, buf_addr);
+	do
+	{
+		/* XXX need some comment here */
+		retry = 2;
+		srb->pdata = (unsigned char *)buf_addr;
+		if(blks > USB_MAX_READ_BLK)
+			smallblks = USB_MAX_READ_BLK;
+		else
+			smallblks = (unsigned short) blks;
+retry_it:
+		srb->datalen = usb_dev_desc[device].blksz * smallblks;
+		srb->pdata = (unsigned char *)buf_addr;
+		if(usb_read_10(srb, (struct us_data *)dev->privptr, start, smallblks))
+		{
+			DEBUG_STORAGE("Read ERROR\r\n");
+			usb_request_sense(srb, (struct us_data *)dev->privptr);
+			if(retry--)
+				goto retry_it;
+			blkcnt -= blks;
+			break;
+		}
+		start += smallblks;
+		blks -= smallblks;
+		buf_addr += srb->datalen;
+	}
+	while(blks != 0);
+	DEBUG_STORAGE("usb_read: end startblk %lx, blccnt %x buffer %lx\r\n", start, smallblks, buf_addr);
+	usb_disable_asynch(0); /* asynch transfer allowed */
+#ifdef SUPERVISOR
+	/* GALVEZ: come back to user mode */
+	if ((Super(SUP_INQUIRE)) && (p)){
+		SuperToUser(p);
+		}
+#endif
+	return blkcnt;
+}
+
+unsigned long usb_stor_write(int device, unsigned long blknr, unsigned long blkcnt, const void *buffer)
+{
+	unsigned long start, blks, buf_addr;
+	unsigned short smallblks;
+	struct usb_device *dev;
+	int retry, i;
+	ccb *srb = &usb_ccb;
+	
+	if(blkcnt == 0)
+		return 0;
+	device &= 0xff;
+	/* Setup  device */
+	DEBUG_STORAGE("usb_write: dev %d \r\n", device);
+#ifdef SUPERVISOR
+	int p = 0;	
+	/* GALVEZ: Acces to register in Supervisor */
+	if ( !(Super(SUP_INQUIRE))){
+		p = SuperFromUser();
+	}
+#endif
+	
+	dev = NULL;
+	for(i = 0; i < USB_MAX_DEVICE; i++)
+	{
+		dev = usb_get_dev_index(i);
+		if(dev == NULL){
+#ifdef SUPERVISOR
+			/* GALVEZ: come back to user mode */
+			if ((Super(SUP_INQUIRE)) && (p))
+				SuperToUser(p);
+#endif
+			return 0;
+		}
+		if(dev->devnum == usb_dev_desc[device].target)
+			break;
+	}
+	usb_disable_asynch(1); /* asynch transfer not allowed */
+	srb->lun = usb_dev_desc[device].lun;
+	buf_addr = (unsigned long)buffer;
+	start = blknr;
+	blks = blkcnt;
+//#if 1	/* GALVEZ: DEBUG */
+	if(usb_test_unit_ready(srb, (struct us_data *)dev->privptr))
+	{
+		DEBUG_STORAGE("Device NOT ready\r\n   Request Sense returned %02X %02X %02X\r\n", srb->sense_buf[2], srb->sense_buf[12], srb->sense_buf[13]);
+		printf("Device NOT ready\r\n   Request Sense returned %02X %02X %02X\r\n", srb->sense_buf[2], srb->sense_buf[12], srb->sense_buf[13]);
+#ifdef SUPERVISOR
+		/* GALVEZ: come back to user mode */
+		if ((Super(SUP_INQUIRE)) && (p))
+			SuperToUser(p);
+#endif					
+		return 0;
+	}
+//#endif
+	DEBUG_STORAGE("usb_write: dev %d startblk %lx, blccnt %lx buffer %lx\r\n", device, start, blks, buf_addr);
+	do
+	{
+		/* XXX need some comment here */
+		retry = 2;
+		srb->pdata = (unsigned char *)buf_addr;
+		if(blks > USB_MAX_READ_BLK)
+			smallblks = USB_MAX_READ_BLK;
+		else
+			smallblks = (unsigned short)blks;
+retry_it:
+		srb->datalen = usb_dev_desc[device].blksz * smallblks;
+		srb->pdata = (unsigned char *)buf_addr;
+		if(usb_write_10(srb, (struct us_data *)dev->privptr, start, smallblks))
+		{
+			DEBUG_STORAGE("Write ERROR\r\n");
+			usb_request_sense(srb, (struct us_data *)dev->privptr);
+			if(retry--)
+				goto retry_it;
+			blkcnt -= blks;
+			break;
+		}
+		start += smallblks;
+		blks -= smallblks;
+		buf_addr += srb->datalen;
+	}
+	while(blks != 0);
+	DEBUG_STORAGE("usb_write: end startblk %lx, blccnt %x buffer %lx\r\n", start, smallblks, buf_addr);
+	usb_disable_asynch(0); /* asynch transfer allowed */
+#ifdef SUPERVISOR
+	/* GALVEZ: come back to user mode */
+	if ((Super(SUP_INQUIRE)) && (p))
+		SuperToUser(p);
+#endif
+	return blkcnt;
+}
+
+/* Probe to see if a new device is actually a Storage device */
+int usb_storage_probe(struct usb_device *dev, unsigned int ifnum, struct us_data *ss)
+{
+	struct usb_interface_descriptor *iface;
+	int i;
+	unsigned int flags = 0;
+	int protocol = 0;
+	int subclass = 0;
+	
+	DEBUG_STORAGE("usb_storage_probe()");
+
+	/* let's examine the device now */
+	iface = &dev->config.if_desc[ifnum];
+#if 0
+	DEBUG_STORAGE("iVendor 0x%X iProduct 0x%X\r\n", dev->descriptor.idVendor, dev->descriptor.idProduct);
+	/* this is the place to patch some storage devices */
+	if((dev->descriptor.idVendor) == 0x066b && (dev->descriptor.idProduct) == 0x0103)
+	{
+		DEBUG_STORAGE("patched for E-USB\r\n");
+		protocol = US_PR_CB;
+		subclass = US_SC_UFI;	    /* an assumption */
+	}
+#endif
+	if(dev->descriptor.bDeviceClass != 0 || iface->bInterfaceClass != USB_CLASS_MASS_STORAGE
+	 || iface->bInterfaceSubClass < US_SC_MIN || iface->bInterfaceSubClass > US_SC_MAX)
+		/* if it's not a mass storage, we go no further */
+		return 0;
+	memset(ss, 0, sizeof(struct us_data));
+	/* At this point, we know we've got a live one */
+	DEBUG_STORAGE("\r\n\r\nUSB Mass Storage device detected\r\n");
+	DEBUG_STORAGE("Protocol: %x SubClass: %x", iface->bInterfaceProtocol,       /* GALVEZ: DEBUG */
+							 iface->bInterfaceSubClass );
+	/* Initialize the us_data structure with some useful info */
+	ss->flags = flags;
+	ss->ifnum = ifnum;
+	ss->pusb_dev = dev;
+	ss->attention_done = 0;
+	/* If the device has subclass and protocol, then use that.  Otherwise,
+	 * take data from the specific interface.
+	 */
+	if(subclass)
+	{
+		ss->subclass = subclass;
+		ss->protocol = protocol;
+	}
+	else
+	{
+		ss->subclass = iface->bInterfaceSubClass;
+		ss->protocol = iface->bInterfaceProtocol;
+	}
+	/* set the handler pointers based on the protocol */
+	DEBUG_STORAGE("Transport: ");
+	switch(ss->protocol)
+	{
+		case US_PR_CB:
+			DEBUG_STORAGE("Control/Bulk\r\n");
+			ss->transport = usb_stor_CB_transport;
+			ss->transport_reset = usb_stor_CB_reset;
+			break;
+		case US_PR_CBI:
+			DEBUG_STORAGE("Control/Bulk/Interrupt\r\n");
+			ss->transport = usb_stor_CB_transport;
+			ss->transport_reset = usb_stor_CB_reset;
+			break;
+		case US_PR_BULK:
+			DEBUG_STORAGE("Bulk/Bulk/Bulk\r\n");
+			ss->transport = usb_stor_BBB_transport;
+			ss->transport_reset = usb_stor_BBB_reset;
+			break;
+		default:
+			printf("USB Storage Transport unknown / not yet implemented\r\n");
+			return 0;
+			break;
+	}
+	/*
+	 * We are expecting a minimum of 2 endpoints - in and out (bulk).
+	 * An optional interrupt is OK (necessary for CBI protocol).
+	 * We will ignore any others.
+	 */
+	DEBUG_STORAGE("Number of endpoints: %d\r\n", iface->bNumEndpoints);
+	for(i = 0; i < iface->bNumEndpoints; i++)
+	{
+		/* is it an BULK endpoint? */
+		if((iface->ep_desc[i].bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK)
+		{
+			if(iface->ep_desc[i].bEndpointAddress & USB_DIR_IN)
+				ss->ep_in = iface->ep_desc[i].bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
+			else
+				ss->ep_out = iface->ep_desc[i].bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
+		}
+		/* is it an interrupt endpoint? */
+		if((iface->ep_desc[i].bmAttributes & USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT)
+		{
+			ss->ep_int = iface->ep_desc[i].bEndpointAddress & USB_ENDPOINT_NUMBER_MASK;
+			ss->irqinterval = iface->ep_desc[i].bInterval;
+		}
+	}
+	DEBUG_STORAGE("Endpoints In %d Out %d Int %d\r\n", ss->ep_in, ss->ep_out, ss->ep_int);
+	/* Do some basic sanity checks, and bail if we find a problem */
+	if(usb_set_interface(dev, iface->bInterfaceNumber, 0) || !ss->ep_in || !ss->ep_out
+	 || (ss->protocol == US_PR_CBI && ss->ep_int == 0))
+	{
+		DEBUG_STORAGE("Problems with device\r\n");
+		return 0;
+	}
+	/* set class specific stuff */
+	/* We only handle certain protocols.  Currently, these are
+	 * the only ones.
+	 * The SFF8070 accepts the requests used in u-boot
+	 */
+	if(ss->subclass != US_SC_UFI && ss->subclass != US_SC_SCSI && ss->subclass != US_SC_8070)
+	{
+		DEBUG_STORAGE("Sorry, protocol %d not yet supported.\r\n", ss->subclass);
+		printf("Sorry, protocol %d not yet supported.\r\n", ss->subclass);
+		return 0;
+	}
+	if(ss->ep_int)
+	{
+		/* we had found an interrupt endpoint, prepare irq pipe
+		 * set up the IRQ pipe and handler
+		 */
+		ss->irqinterval = (ss->irqinterval > 0) ? ss->irqinterval : 255;
+		ss->irqpipe = usb_rcvintpipe(ss->pusb_dev, ss->ep_int);
+		ss->irqmaxp = usb_maxpacket(dev, ss->irqpipe);
+		dev->irq_handle = usb_stor_irq;
+	}
+	dev->privptr = (void *)ss;
+	return 1;
+}
+
+int usb_stor_get_info(struct usb_device *dev, struct us_data *ss, block_dev_desc_t *dev_desc)
+{
+	unsigned char perq, modi;
+	unsigned long cap[2];
+	unsigned long *capacity, *blksz;
+	ccb *pccb = &usb_ccb;
+	DEBUG_STORAGE("usb_stor_ger_info()");
+	/* for some reasons a couple of devices would not survive this reset */
+	if(
+	 /* Sony USM256E */
+	 (dev->descriptor.idVendor == 0x054c && dev->descriptor.idProduct == 0x019e)
+	 /* USB007 Mini-USB2 Flash Drive */
+	 || (dev->descriptor.idVendor == 0x066f && dev->descriptor.idProduct == 0x2010)
+	 /* SanDisk Corporation Cruzer Micro 20044318410546613953 */
+	 || (dev->descriptor.idVendor == 0x0781 && dev->descriptor.idProduct == 0x5151)
+	 /* SanDisk Corporation U3 Cruzer Micro 1/4GB Flash Drive 000016244373FFB4 */
+	 || (dev->descriptor.idVendor == 0x0781 && dev->descriptor.idProduct == 0x5406)
+	)
+	{	DEBUG_STORAGE("usb_stor_get_info: skipping RESET..\r\n");}
+	else
+		ss->transport_reset(ss);
+	pccb->pdata = usb_stor_buf;
+	dev_desc->target = dev->devnum;
+	pccb->lun = dev_desc->lun;
+	DEBUG_STORAGE(" address %d\r\n", dev_desc->target);
+	if(usb_inquiry(pccb, ss))
+		return -1;
+	perq = usb_stor_buf[0];
+	modi = usb_stor_buf[1];
+	if((perq & 0x1f) == 0x1f)
+		/* skip unknown devices */
+		return 0;
+	if((modi&0x80) == 0x80)
+		/* drive is removable */
+		dev_desc->removable = 1;
+	memcpy(&dev_desc->vendor[0], &usb_stor_buf[8], 8);
+	memcpy(&dev_desc->product[0], &usb_stor_buf[16], 16);
+	memcpy(&dev_desc->revision[0], &usb_stor_buf[32], 4);
+	dev_desc->vendor[8] = 0;
+	dev_desc->product[16] = 0;
+	dev_desc->revision[4] = 0;
+#ifdef CONFIG_USB_BIN_FIXUP
+	usb_bin_fixup(dev->descriptor, (uchar *)dev_desc->vendor, (uchar *)dev_desc->product);
+#endif /* CONFIG_USB_BIN_FIXUP */
+	DEBUG_STORAGE("ISO Vers %X, Response Data %X\r\n", usb_stor_buf[2], usb_stor_buf[3]);
+	if(usb_test_unit_ready(pccb, ss))
+	{
+		DEBUG_STORAGE("Device NOT ready\r\n   Request Sense returned %02X %02X %02X\r\n", pccb->sense_buf[2], pccb->sense_buf[12], pccb->sense_buf[13]);
+		printf("Device NOT ready\r\n   Request Sense returned %02X %02X %02X\r\n", pccb->sense_buf[2], pccb->sense_buf[12], pccb->sense_buf[13]);
+		if(dev_desc->removable == 1)
+		{
+			dev_desc->type = perq;
+			return 1;
+		}
+		return 0;
+	}
+	pccb->pdata = (unsigned char *)&cap[0];
+	memset(pccb->pdata, 0, 8);
+	if(usb_read_capacity(pccb, ss) != 0)
+	{
+		printf("READ_CAP ERROR\r\n");
+		cap[0] = 2880;
+		cap[1] = 0x200;
+	}
+	DEBUG_STORAGE("Read Capacity returns: 0x%lx, 0x%lx\r\n", cap[0], cap[1]);
+#if 0
+	if(cap[0] > (0x200000 * 10)) /* greater than 10 GByte */
+		cap[0] >>= 16;
+#endif
+	cap[0] = cpu_to_be32(cap[0]);
+	cap[1] = cpu_to_be32(cap[1]);
+	/* this assumes bigendian! */
+	cap[0] += 1;
+	capacity = &cap[0];
+	blksz = &cap[1];
+	DEBUG_STORAGE("Capacity = 0x%lx, blocksz = 0x%lx\r\n", *capacity, *blksz);
+	dev_desc->lba = *capacity;
+	dev_desc->blksz = *blksz;
+	dev_desc->type = perq;
+	DEBUG_STORAGE(" address %d\r\n", dev_desc->target);
+	DEBUG_STORAGE("partype: %d\r\n", dev_desc->part_type);
+	init_part(dev_desc);
+	DEBUG_STORAGE("partype: %d\r\n", dev_desc->part_type);
+	return 1;
+}
+
+#endif /* CONFIG_USB_STORAGE */
+#endif /* CONFIG_USB_UHCI || CONFIG_USB_OHCI || CONFIG_USB_EHCI */
diff --git a/FireBee/trunk/usb/store/vars.h b/FireBee/trunk/usb/store/vars.h
new file mode 100644
index 0000000..b6e626b
--- /dev/null
+++ b/FireBee/trunk/usb/store/vars.h
@@ -0,0 +1,83 @@
+/*
+* Modified by David Gálvez 2010.
+*
+* TOS 4.04 Xbios vars for the CT60 board
+*  Didier Mequignon 2002-2005, e-mail: aniplay@wanadoo.fr
+*
+*  This library is free software; you can redistribute it and/or
+*  modify it under the terms of the GNU Lesser General Public
+*  License as published by the Free Software Foundation; either
+*  version 2.1 of the License, or (at your option) any later version.
+*
+*  This library is distributed in the hope that it will be useful,
+*  but WITHOUT ANY WARRANTY; without even the implied warranty of
+*  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+*  Lesser General Public License for more details.
+*
+*  You should have received a copy of the GNU Lesser General Public
+*  License along with this library; if not, write to the Free Software
+*  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+*/
+
+#ifndef	_VARS_H
+#define	_VARS_H
+
+
+#define etv_timer   0x400
+#define etv_critic  0x404
+#define memvalid    0x420
+#define memctrl     0x424
+#define resvalid    0x426
+#define resvector   0x42A
+#define phystop     0x42E
+#define _memtop     0x436
+#define memval2     0x43A
+#define flock       0x43E
+#define _timer_ms   0x442
+#define _bootdev    0x446
+#define sshiftmd    0x44C
+#define _v_bas_ad   0x44E
+#define vblsem      0x452
+#define nvbls       0x454
+#define _vblqueue   0x456
+#define colorptr    0x45A
+#define _vbclock    0x462
+#define _frclock    0x466
+#define hdv_init    0x46A
+#define HDV_BPB     0x472
+#define hdv_bpb    0x472
+#define HDV_RW      0x476
+#define hdv_rw     0x476
+#define hdv_boot    0x47A
+#define HDV_MEDIACH 0x47E
+#define hdv_mediach 0x47E
+#define _cmdload    0x482
+#define conterm     0x484
+#define trp14ret    0x486
+#define __md        0x49E
+#define savptr      0x4A2
+#define _nflops     0x4A6
+#define con_state   0x4A8
+#define save_row    0x4AC
+#define _hz_200     0x4BA
+#define _DRVBITS    0x4C2
+#define _drvbits    0x4C2
+#define DSKBUFP     0x4C6
+#define _dskbufp    0x4C6
+#define _dumpflg    0x4EE
+#define _sysbase    0x4F2
+#define exec_os     0x4FE
+#define dump_vec    0x502
+#define ptr_stat    0x506
+#define ptr_vec     0x50A
+#define aux_sta     0x50E
+#define aux_vec     0x512
+#define PUN_PTR     0x516
+#define memval3     0x51A
+#define proc_type   0x59E
+#define COOKIE      0x5A0
+#define cookie	    0x5A0
+                  
+
+
+#endif
diff --git a/FireBee/trunk/usb/store/xhdi.c b/FireBee/trunk/usb/store/xhdi.c
new file mode 100644
index 0000000..3be2bfa
--- /dev/null
+++ b/FireBee/trunk/usb/store/xhdi.c
@@ -0,0 +1,391 @@
+/***************** NOT READY YET ***********************/
+/**************** ONLY EXPERIMENTAL ********************/ 
+
+/* TOS 4.04 Xbios dispatcher for the CT60/CTPCI boards
+ * and USB-disk / Ram-Disk utility
+ * Didier Mequignon 2005-2009, e-mail: aniplay@wanadoo.fr
+ * 
+ * Translation to C by David Galvez. 2010, e-mail: dgalvez75@gmail.com
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#include <stdio.h>
+#include <mint/osbind.h>
+
+#include "config.h"
+#include "vars.h"
+#include "xhdi.h"
+#include "debug.h"
+
+long *drvbits = (long *)_DRVBITS;
+
+struct pun_info *old_pun_ptr = (struct pun_info *)0x512;
+struct usb_pun_info pun_ptr_usb;
+
+XBRA xbra_hdv_bpb;
+XBRA xbra_hdv_rw;
+XBRA xbra_hdv_mediach;
+
+extern long usb_1st_disk_drive;
+extern short max_logical_drive;
+
+extern unsigned long usb_stor_read(int device, unsigned long blknr, unsigned long blkcnt, void *buffer);
+
+void drive_full_usb(void)
+{
+	DEBUG_XHDI("\n");
+}
+
+long __CDECL hdv_bpb_usb(void)
+{
+	unsigned short dev;
+	long r;
+
+	__asm__ volatile	/* get arguments from the stack */
+	(
+		"move.w 12(%%sp),%0\n\t"
+
+		:/*outputs*/ "=m" (dev)
+		:/*inputs*/ 
+	);
+
+	__asm__ volatile	/* call old vector */
+	(
+		"movem.l %%d2-%%d7/%%a2-%%a6,-(%%sp)\n\t"	/* important to save register */
+		"move.l %1,%%a0\n\t"
+		"move.w #0,-(%%sp)\n\t"
+		"move.w %2,-(%%sp)\n\t"
+		"jsr (%%a0)\n\t"
+		"addq.l #4,%%sp\n\t"
+		"move.l %%d0,%0\n\t"
+		"movem.l (%%sp)+,%%d2-%%d7/%%a2-%%a6\n\t"
+		:/*outputs*/ "=r" (r)
+		:/*inputs*/ "m" (xbra_hdv_bpb.xb_oldvec), "m" (dev)
+		:"d0", "d1", "d2", "d3", "d4", "d5", "d6", "d7", "a2", "a3", "a4", "a5" /*clobbered regs*/
+	);
+	return r;
+}
+
+long __CDECL hdv_rw_usb(void)
+{	
+	void *buf;
+	short count, recno, dev, mode;
+	long lrecno;
+
+	long r = 0;
+	
+	__asm__ volatile	/* get arguments from the stack */
+	(
+		"move.l 18(%%sp),%0\n\t"
+		"move.w 14(%%sp),%1\n\t"
+		"move.w 12(%%sp),%2\n\t"
+		"move.w 10(%%sp),%3\n\t"
+		"move.l 8(%%sp),%4\n\t"
+		"move.w 4(%%sp),%5\n\t"
+		:/*outputs*/ "=r" (lrecno), "=r" (dev) ,"=r" (recno), "=r" (count), "=r" (buf), "=r" (mode)
+		:/*inputs*/ 
+	);
+	
+	DEBUG_XHDI("lrecno %lx dev %d recno %x count %d mode %x\n",
+			lrecno, dev, recno, count, mode);
+	
+	DEBUG_XHDI("\n");
+	DEBUG_XHDI("rw\n");
+
+	__asm__ volatile	/* call old vector */
+	(
+		"movem.l %%d2-%%d7/%%a2-%%a6,-(%%sp)\n\t"
+		"move.l %1,%%a0\n\t"
+		"move.l (%%a0),%%d0\n\t"
+		"move.w #0,-(%%sp)\n\t"
+		"move.l %2,-(%%sp)\n\t"
+		"move.w %3,-(%%sp)\n\t"
+		"move.w %4,-(%%sp)\n\t"
+		"move.w %5,-(%%sp)\n\t"
+		"move.l %6,-(%%sp)\n\t"
+		"move.w %7,-(%%sp)\n\t"
+		"move.l %%d0,%%a0\n\t"
+		"jsr (%%a0)\n\t"
+		"addq.l #4,%%sp\n\t"
+		"move.l %%d0,%0\n\t"
+		"movem.l (%%sp)+,%%d2-%%d7/%%a2-%%a6\n\t"
+		:/*outputs*/ "=r" (r)
+		:/*inputs*/ "r" (xbra_hdv_rw.xb_oldvec), "r" (lrecno), "r" (dev) ,"r" (recno), "r" (count), "r" (buf), "r" (mode)
+		:"d0"/*, "d1", "d2", "d3", "d4", "d5", "d6", "d7", "a2", "a3", "a4", "a5" clobbered regs*/
+	);
+
+//	r = (*xbra_hdv_rw.xb_oldvec)(mode, buf, num, recno, dev, l);
+	DEBUG_XHDI (" r %lx \n", r);
+
+	return r;
+}
+
+long __CDECL hdv_mediach_usb(void)
+{
+	DEBUG_XHDI("\n");
+	DEBUG_XHDI("mediach\n");
+
+	short dev, dev1, dev2;
+	long r;
+
+	__asm__ volatile	/* get arguments from the stack */
+	(
+		"move.w 2(%%sp),%0\n\t"
+		"move.w 4(%%sp),%1\n\t"
+		"move.w 6(%%sp),%2\n\t"
+		:/*outputs*/ "=r" (dev), "=r" (dev1), "=r" (dev2)
+		:/*inputs*/ 
+	);
+
+	DEBUG_XHDI (" dev(2) %x dev(4) %x dev(6) %x\n", dev, dev1, dev2);
+
+	__asm__ volatile	/* call old vector */
+	(
+		"movem.l %%d2-%%d7/%%a2-%%a6,-(%%sp)\n\t"
+		"move.l %1,%%a0\n\t"
+		"move.l (%%a0),%%d0\n\t"
+		"move.w #0,-(%%sp)\n\t"
+		"move.w %2,-(%%sp)\n\t"
+		"move.l %%d0,%%a0\n\t"
+		"jsr (%%a0)\n\t"
+		"addq.l #4,%%sp\n\t"
+		"move.l %%d0,%0\n\t"
+		"movem.l (%%sp)+,%%d2-%%d7/%%a2-%%a6\n\t"
+		:/*outputs*/ "=r" (r)
+		:/*inputs*/ "r" (xbra_hdv_mediach.xb_oldvec), "r" (dev)
+		:"d0"/*, "d1", "d2", "d3", "d4", "d5", "d6", "d7", "a2", "a3", "a4", "a5" clobbered regs*/
+	);
+//	printf (" r %lx \n", r);
+//	r = (*xbra_hdv_mediach.xb_oldvec)(d);
+//	DEBUG_XHDI("Calling vector: %x\n", xbra_hdv_mediach.xb_oldvec);
+//	r = (*xbra_hdv_mediach.xb_oldvec)(5);
+	DEBUG_XHDI(" r %lx \n", r);
+
+	return r;
+}
+
+void install_xbra(XBRA *xbra_hd, long id, long old_vec, long (*handle)())
+{
+	DEBUG_XHDI("\n");
+#define XBRA_MAGIC	0x58425241L /* "XBRA" */
+#define JMP_OPCODE	0x4EF9
+
+	xbra_hd->xb_magic = XBRA_MAGIC;
+	xbra_hd->xb_id = id;
+	xbra_hd->xb_oldvec = *((Func *)old_vec);
+	xbra_hd->jump = JMP_OPCODE;
+	xbra_hd->handle = (Func) handle;	
+
+	*((Func *)old_vec) = xbra_hd->handle;
+
+	DEBUG_XHDI("id: %x xbra_hd->xb_oldvec %x old_vec %x old_vec (*) %x old_vec (&)  %x\n", 
+			xbra_hd->xb_id, xbra_hd->xb_oldvec, old_vec, *((Func *)old_vec), &old_vec);
+
+	__asm__ volatile	/* clean cache ??? */
+	(
+		"cpusha BC\n\t"
+		:/*outputs*/
+		:/*inputs*/
+	);
+}
+
+void usb_drive_ok(void)
+{
+	DEBUG_XHDI("\n");
+
+}
+
+
+long install_usb_partition(unsigned char drive, int dev_num, unsigned long part_type, 
+			 unsigned long part_offset, unsigned long part_size)
+{
+	DEBUG_XHDI("\n");	
+
+	int *dskbufp = (int *)DSKBUFP; 
+	unsigned short status_register;
+
+	long old_hdv_bpb;
+	long old_hdv_rw;
+	long old_hdv_mediach;
+
+	if (drive < 16) {
+		(pun_ptr_usb.puns)++;
+		pun_ptr_usb.pun[drive] = dev_num | PUN_USB;
+		pun_ptr_usb.pstart[drive] = part_offset;
+		pun_ptr_usb.ptype[drive] = part_type;
+		pun_ptr_usb.psize[drive] = part_size;
+		/* flags B15:swap, B7:change, B0:bootable */
+#define BOOTABLE	0x0001
+#define CHANGE		0x0080
+#define SWAP		0x8000
+		pun_ptr_usb.flags[drive] = CHANGE;
+	}
+
+	if (drive < 16) {
+		old_pun_ptr->puns++;
+		old_pun_ptr->pun[drive] = dev_num | PUN_USB;
+	}
+
+	if (usb_stor_read (dev_num, part_offset, 1, (void *)(*dskbufp)) == 0)
+		return -1;
+
+	if (usb_1st_disk_drive)
+		usb_drive_ok();
+
+	usb_1st_disk_drive = drive;
+
+	long r;
+	r = (long)Getbpb (2);
+	DEBUG_XHDI("Before int. Getbpb return: %x \n", r);
+
+
+	__asm__ volatile	/* mask interrupts */
+	(
+		"move.w %%sr,%%d0\n\t"
+		"move.w %%d0,%0\n\t"
+		"or.l #0x700,%%d0\n\t"
+		"move.w %%d0,%%sr\n\t"
+		:/*outputs*/ "=r" (status_register)
+		:/*inputs*/
+		:"d0" /*clobbered regs*/
+	);
+
+#define _USB		0x5F555342  /* _USB   */
+	long id = _USB;
+	old_hdv_bpb = (long)HDV_BPB;
+
+	DEBUG_XHDI("id: %x old_hdv_bpb %x old_hdv_bpb (*) %x hdv_bpb_usb %x\n", 
+			id, old_hdv_bpb, *((Func *)old_hdv_bpb), hdv_bpb_usb);
+	install_xbra(&xbra_hdv_bpb, id, old_hdv_bpb, hdv_bpb_usb);
+	DEBUG_XHDI("id: %x old_hdv_bpb %x old_hdv_bpb (*) %x hdv_bpb_usb %x\n", 
+			xbra_hdv_bpb.xb_id, xbra_hdv_bpb.xb_oldvec, *((Func *)xbra_hdv_bpb.xb_oldvec), xbra_hdv_bpb.handle);
+#if 0	
+	old_hdv_rw = (long)HDV_RW;
+	DEBUG_XHDI("id: %x old_hdv_rw %x old_hdv_rw (*) %x hdv_rw_usb %x\n", 
+			id, old_hdv_rw, *((Func *)old_hdv_rw), hdv_rw_usb);
+	install_xbra(&xbra_hdv_rw, id, old_hdv_rw, hdv_rw_usb);
+	DEBUG_XHDI("id: %x old_hdv_rw %x old_hdv_rw (*) %x hdv_rw_usb %x\n", 
+			xbra_hdv_rw.xb_id, xbra_hdv_rw.xb_oldvec, *((Func *)xbra_hdv_rw.xb_oldvec), xbra_hdv_rw.handle);
+
+	old_hdv_mediach = (long)HDV_MEDIACH;
+	DEBUG_XHDI("id: %x old_hdv_mediach %x old_hdv_mediach (*) %x hdv_mediach_usb %x\n", 
+			id, old_hdv_mediach, *((Func *)old_hdv_mediach), hdv_mediach_usb);
+	install_xbra(&xbra_hdv_mediach, id, old_hdv_mediach, hdv_mediach_usb);
+	DEBUG_XHDI("id: %x old_hdv_mediach %x old_hdv_mediach (*) %x hdv_mediach_usb %x\n", 
+			xbra_hdv_mediach.xb_id, xbra_hdv_mediach.xb_oldvec, *((Func *)xbra_hdv_mediach.xb_oldvec), xbra_hdv_mediach.handle);
+#endif
+
+	r = (long)Getbpb (4);
+
+	DEBUG_XHDI("Before int. Getbpb return: %x \n", r);
+
+//	Bconin(DEV_CONSOLE);
+	__asm__ volatile	/* restore interrupts */
+	(
+		"move.w %%sr,%%d0\n\t"
+		"and.w %0,%%d0\n\t"
+		"move.w %%d0,%%sr\n\t"
+		:/*outputs*/
+		:/*inputs*/ "r" (status_register)
+		:"d0"
+	);
+	DEBUG_XHDI("after restore interrups\n");
+//	Bconin(DEV_CONSOLE);
+	return 0;
+} 	
+
+unsigned char search_empty_drive(int dev_num, unsigned long part_type, 
+	      unsigned long part_offset, unsigned long part_size)
+{
+	DEBUG_XHDI("\n");	
+	
+	unsigned char drive = 2;	
+
+	DEBUG_XHDI("drvbits: %x\n", *drvbits);
+	while (drive < MAX_LOGICAL_DRIVE) {
+		if (!(*drvbits & (0x00000001 << drive))) {
+			DEBUG_XHDI("drive: %d\n", drive);
+			if (install_usb_partition(drive, dev_num, part_type, part_offset, part_size) == -1) {
+				DEBUG_XHDI("Couldn't install USB partition\n");
+				return -1;
+			}
+			else return drive;
+		}
+		drive++;
+	}
+	printf("all drives already used!\n\r");
+
+	return -1;
+}	
+
+unsigned char add_partition(int dev_num, unsigned long part_type, 
+			    unsigned long part_offset, unsigned long part_size)
+{
+	DEBUG_XHDI("\n");
+
+	unsigned char i;
+	unsigned char drive;
+
+	pun_ptr_usb.puns = 0x0000;
+	pun_ptr_usb.version_num = 0x0300;
+	pun_ptr_usb.max_sect_siz = 0x4000;
+	
+	for (i=0; i<16; i++)
+		pun_ptr_usb.pun[i] = 0xff;
+
+	if ((drive = search_empty_drive(dev_num, part_type, part_offset, part_size)) == -1)
+		return -1;
+	return drive;
+}
+
+int install_usb_stor(int dev_num, unsigned long part_type, 
+		      unsigned long part_offset, unsigned long part_size, 
+		      char *vendor, char *revision, char *product )
+{
+	DEBUG_XHDI("\n");
+	unsigned char part_num;
+
+	if (dev_num <= PUN_DEV) {	/* Max. of 32 USB storage devices */
+		switch (part_type) {	/* Although real limit is 16 of pinfo struct */
+			case GEM:
+				break;
+			case BGM:
+				break;
+			case RAW:
+				break;
+			case FAT16_32MB:
+				break;
+			case FAT16:
+				break;
+			case FAT16_WIN95:
+				break;
+			case FAT32:
+				break;
+			case FAT32_II:
+				break;
+			default:
+				printf("Invalid partition type (0x%08lx)\r\n", part_type);
+				return -1;
+		}
+		if ((part_num = add_partition(dev_num, part_type, part_offset, part_size)) == -1)
+			return -1;
+		else return 0;
+	}
+	printf("Maxim number(%d) of USB storage device reached \n\r", dev_num);
+	return -1;
+}
+
+
diff --git a/FireBee/trunk/usb/store/xhdi.h b/FireBee/trunk/usb/store/xhdi.h
new file mode 100644
index 0000000..d8f20bb
--- /dev/null
+++ b/FireBee/trunk/usb/store/xhdi.h
@@ -0,0 +1,101 @@
+/* 
+ * David Galvez. 2010, e-mail: dgalvez75@gmail.com
+ *
+ * This file is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This file is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+ */
+
+#ifndef _XHDI_H
+#define _XHDI_H
+
+typedef long __CDECL (*Func)();
+
+//#define old_pun_ptr 	0x516
+
+#undef PUN_PTR
+//#define pun_ptr pun_ptr_usb
+
+#define MAX_LOGICAL_DRIVE	max_logical_drive
+
+/* AHDI */
+
+#define PUN_DEV           0x1F /* device number of HD */
+#define PUN_UNIT          0x07 /* Unit number */
+#define PUN_SCSI          0x08 /* 1=SCSI 0=ACSI */
+#define PUN_IDE           0x10 /* Falcon IDE */
+#define PUN_USB           0x20 /* USB */
+#define PUN_REMOVABLE     0x40 /* Removable media */
+#define PUN_VALID         0x80 /* zero if valid */
+
+#define PINFO_PUNS     0  // 2 bytes
+#define PINFO_PUN      2  // 16 bytes
+#define PINFO_PSTART  18  // 16 x 4 bytes
+#define PINFO_COOKIE  82  // 4 bytes
+#define PINFO_COOKPTR 86  // 4 bytes
+#define PINFO_VERNUM  90  // 2 bytes
+#define PINFO_MAXSIZE  92  // 2 bytes
+#define PINFO_PTYPE   94  // 16 x 4 bytes
+#define PINFO_PSIZE  158  // 16 x 4 bytes
+#define PINFO_FLAGS  222  // 16 x 2 bytes, internal use: B15:swap, B7:change, B0:bootable
+#define PINFO_BPB    256  // 16 x 32 bytes
+#define PINFO_SIZE   768
+
+struct pun_info
+{	
+	short		puns;			/* Number of HD's */
+	char		pun [16];		/* AND with masks below: */
+	long		pstart [16];
+	long		cookie;			/* 'AHDI' if following valid */
+	long		*cook_ptr;		/* Points to 'cookie' */
+	unsigned short	version_num;		/* AHDI version */
+	unsigned short	max_sect_siz;		/* Max logical sec size */
+	long		reserved[16];		/* Reserved */	
+};
+
+struct usb_pun_info
+{	
+	short		puns;			/* Number of HD's */
+	char		pun [16];		/* AND with masks below: */
+	long		pstart [16];
+	long		cookie;			/* 'AHDI' if following valid */
+	long		*cook_ptr;		/* Points to 'cookie' */
+	unsigned short	version_num;		/* AHDI version */
+	unsigned short	max_sect_siz;		/* Max logical sec size */
+	long		reserved[16];		/* Reserved */	
+	long		ptype[16];
+	long		psize[16];
+	unsigned short	flags[16];
+};
+	
+/* PARTITIONS TYPES */
+#define GEM		0x47454D   // GEM up to 16 MB
+#define BGM		0x42474D   // BGM over 16 MB
+#define RAW		0x524157   // RAW
+#define FAT16_32MB	0x4	   // DOS FAT16 up to 32 MB
+#define FAT16		0x6	   // DOS FAT16 over 32 MB
+#define FAT16_WIN95     0xE        // WIN95 FAT16
+#define FAT32           0xB        // FAT32
+#define FAT32_II	0xC	   // FAT32
+
+typedef struct xbra XBRA;
+struct xbra {
+	long  xb_magic;		/* "XBRA" = 0x58425241         */
+	long  xb_id;      	/* ID of four ASCII characters */
+	Func  xb_oldvec;	/* Old value of the vectors    */
+	short jump;
+  	Func  handle;
+};
+
+
+#endif /* _XHDI_H */
diff --git a/FireBee/trunk/vhdl/dsp56k/asm/asm.sh b/FireBee/trunk/vhdl/dsp56k/asm/asm.sh
new file mode 100644
index 0000000..58c4f53
--- /dev/null
+++ b/FireBee/trunk/vhdl/dsp56k/asm/asm.sh
@@ -0,0 +1,6 @@
+#!/bin/bash
+export DSP_PATH=~/.wine/drive_c/Programme/Motorola/DSP56300/clas
+
+wine $DSP_PATH/asm56300.exe -b -g -l $1.asm
+wine $DSP_PATH/dsplnk.exe $1.cln
+wine $DSP_PATH/cldlod.exe $1.cld > $1.lod
diff --git a/FireBee/trunk/vhdl/dsp56k/asm/test_agu/test.asm b/FireBee/trunk/vhdl/dsp56k/asm/test_agu/test.asm
new file mode 100644
index 0000000..ff0d2b6
--- /dev/null
+++ b/FireBee/trunk/vhdl/dsp56k/asm/test_agu/test.asm
@@ -0,0 +1,13 @@
+
+	move	#1,n1
+	move	#10,r1
+	nop
+	move	(r1)+n1
+	move	#15,m1
+	rep		#10
+	move	(r1)+n1
+	move	#10,n1
+	rep		#10
+	move	(r1)+n1
+
+
diff --git a/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_abs.asm b/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_abs.asm
new file mode 100644
index 0000000..9e400e8
--- /dev/null
+++ b/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_abs.asm
@@ -0,0 +1,12 @@
+
+; clear CCR
+	andi	#$00,CCR
+	move	#>0.25,a
+	abs		a
+	move	#>-0.25,a
+	abs		a
+	move	#>0,a
+	abs		a
+	move	#>$80,a2
+	abs		a
+
diff --git a/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_adc.asm b/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_adc.asm
new file mode 100644
index 0000000..0589a4e
--- /dev/null
+++ b/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_adc.asm
@@ -0,0 +1,11 @@
+	move	#>0,y0
+	move	#>1,y1
+	clr		b
+	move	#>1,b0
+; set only carry bit
+	andi	#$00,ccr
+	ori		#$01,ccr
+	adc		y,b
+	move	#>$800000,y1
+	move	#>$80,b2
+	adc		y,b
diff --git a/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_add.asm b/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_add.asm
new file mode 100644
index 0000000..ba12582
--- /dev/null
+++ b/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_add.asm
@@ -0,0 +1,11 @@
+	move	#>0,y0
+	move	#>1,y1
+	clr		b
+	move	#>1,b0
+; set only carry bit
+	andi	#$00,ccr
+	ori		#$01,ccr
+	add		y,b
+	move	#>$800000,y1
+	move	#>$80,b2
+	add		y,b
diff --git a/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_addl.asm b/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_addl.asm
new file mode 100644
index 0000000..dd80cb5
--- /dev/null
+++ b/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_addl.asm
@@ -0,0 +1,9 @@
+	move	#>$55,a
+	clr		b
+	move	#>$55,b0
+	andi	#$00,ccr
+	addl	a,b
+	move	#>$AA,a
+	addl	a,b
+	move	#>$80,b2
+	addl	a,b
diff --git a/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_addr.asm b/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_addr.asm
new file mode 100644
index 0000000..7be3b44
--- /dev/null
+++ b/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_addr.asm
@@ -0,0 +1,9 @@
+	move	#>$55,a
+	clr		b
+	move	#>$55,b0
+	andi	#$00,ccr
+	addr	a,b
+	move	#>$AA,a
+	addr	a,b
+	move	#>$80,b2
+	addr	a,b
diff --git a/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_and.asm b/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_and.asm
new file mode 100644
index 0000000..72aba75
--- /dev/null
+++ b/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_and.asm
@@ -0,0 +1,12 @@
+	move	#>$000FFF,y0
+	move	#>$FFFFFF,b
+	andi	#$00,ccr
+	and		y0,b
+	move	#>$FFF000,y0
+	move	#>$FFFFFF,b
+	andi	#$00,ccr
+	and		y0,b
+	move	#>$000000,y0
+	move	#>$FFFFFF,b
+	andi	#$00,ccr
+	and		y0,b
diff --git a/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_asl.asm b/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_asl.asm
new file mode 100644
index 0000000..9a7244b
--- /dev/null
+++ b/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_asl.asm
@@ -0,0 +1,8 @@
+;	move	#>0,y0
+;	move	#>1,y1
+	clr		b
+	move	#>$A5,b0
+	move	#>$A5,b1
+	move	#>$A5,b2
+	andi	#$00,ccr
+	asl		b
diff --git a/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_asr.asm b/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_asr.asm
new file mode 100644
index 0000000..c37a0cc
--- /dev/null
+++ b/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_asr.asm
@@ -0,0 +1,8 @@
+;	move	#>0,y0
+;	move	#>1,y1
+	clr		b
+	move	#>$A5,b0
+	move	#>$A5,b1
+	move	#>$A5,b2
+	andi	#$00,ccr
+	asr		b
diff --git a/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_carry.asm b/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_carry.asm
new file mode 100644
index 0000000..2fe6ff5
--- /dev/null
+++ b/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_carry.asm
@@ -0,0 +1,20 @@
+	clr		a
+	clr		b
+	andi	#$00,ccr
+	move 	#>$7F,a2
+	move 	#>$7F,b2
+	add		a,b
+
+	clr		a
+	clr		b
+	andi	#$00,ccr
+	move 	#>$80,a2
+	move 	#>$7F,b2
+	add		a,b
+
+	clr		a
+	clr		b
+	andi	#$00,ccr
+	move 	#>$80,a2
+	move 	#>$80,b2
+	add		a,b
diff --git a/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_clr.asm b/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_clr.asm
new file mode 100644
index 0000000..6b2083d
--- /dev/null
+++ b/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_clr.asm
@@ -0,0 +1,9 @@
+
+; clear CCR
+	andi	#$00,CCR
+	move	#>0.25,a
+	clr		a
+	move	#>-0.25,a
+	andi	#$00,CCR
+	ori		#$01,CCR
+	clr		a
diff --git a/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_cmp.asm b/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_cmp.asm
new file mode 100644
index 0000000..978933f
--- /dev/null
+++ b/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_cmp.asm
@@ -0,0 +1,20 @@
+	move	#$20,b
+	move	#$24,y0
+	andi	#$00,ccr
+	cmp		y0,b
+	move	#$20,b
+	move	#$20,y0
+	andi	#$00,ccr
+	cmp		y0,b
+	move	#$24,b
+	move	#$20,y0
+	andi	#$00,ccr
+	cmp		y0,b
+	move	#$800AAA,b
+	move	#$20,y0
+	andi	#$00,ccr
+	cmp		y0,b
+	move	#$800AAA,y0
+	move	#$20,b
+	andi	#$00,ccr
+	cmp		y0,b
diff --git a/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_cmpm.asm b/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_cmpm.asm
new file mode 100644
index 0000000..a63a0d4
--- /dev/null
+++ b/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_cmpm.asm
@@ -0,0 +1,20 @@
+	move	#$20,b
+	move	#$24,y0
+	andi	#$00,ccr
+	cmpm		y0,b
+	move	#$20,b
+	move	#$20,y0
+	andi	#$00,ccr
+	cmpm		y0,b
+	move	#$24,b
+	move	#$20,y0
+	andi	#$00,ccr
+	cmpm		y0,b
+	move	#$800AAA,b
+	move	#$20,y0
+	andi	#$00,ccr
+	cmpm		y0,b
+	move	#$800AAA,y0
+	move	#$20,b
+	andi	#$00,ccr
+	cmpm		y0,b
diff --git a/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_eor.asm b/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_eor.asm
new file mode 100644
index 0000000..381c5dc
--- /dev/null
+++ b/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_eor.asm
@@ -0,0 +1,8 @@
+	move	#>$000FFF,y0
+	move	#>$FF00FF,b
+	andi	#$00,ccr
+	eor		y0,b
+	move	#>$FFFFFF,y0
+	move	#>$FFFFFF,b
+	andi	#$00,ccr
+	eor		y0,b
diff --git a/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_lsl.asm b/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_lsl.asm
new file mode 100644
index 0000000..51e845f
--- /dev/null
+++ b/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_lsl.asm
@@ -0,0 +1,7 @@
+
+	andi	#$00,CCR
+	move	#>0.25,a
+	move	#>$AAAAAA,a
+	move	#>$BCDEFA,a0
+	rep		#24
+	lsl		a
diff --git a/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_lsr.asm b/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_lsr.asm
new file mode 100644
index 0000000..87177a9
--- /dev/null
+++ b/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_lsr.asm
@@ -0,0 +1,7 @@
+
+	andi	#$00,CCR
+	move	#>0.25,a
+	move	#>$AAAAAA,a
+	move	#>$BCDEFA,a0
+	rep		#24
+	lsr		a
diff --git a/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_mac.asm b/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_mac.asm
new file mode 100644
index 0000000..b97fb6a
--- /dev/null
+++ b/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_mac.asm
@@ -0,0 +1,17 @@
+
+	andi	#$00,CCR
+	clr		a
+	move	#$80,a2
+	move	#>0.25,x0
+	move	#>0.50,y0
+	mac		-x0,y0,a
+	move	#>-0.25,x0
+	move	#>-0.55,y0
+	mac		x0,y0,a
+	move	#>-0.20,x0
+	move	#>+0.55,y0
+	mac		x0,y0,a
+	move	#>-0.20,x0
+	move	#>+0.55,y0
+	mac		-x0,y0,a
+
diff --git a/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_macr.asm b/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_macr.asm
new file mode 100644
index 0000000..ebbfdf5
--- /dev/null
+++ b/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_macr.asm
@@ -0,0 +1,17 @@
+
+	andi	#$00,CCR
+	clr		a
+	move	#$100000,a
+	move	#>$123456,x0
+	move	#>$123456,y0
+	macr	x0,y0,a
+	move	#$100001,a
+	move	#>$123456,x0
+	move	#>$123456,y0
+	macr	x0,y0,a
+	move	#$100000,a
+	move	#$800000,a0
+	move	#>$123456,x0
+	move	#>$123456,y0
+	macr	x0,y0,a
+
diff --git a/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_mpy.asm b/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_mpy.asm
new file mode 100644
index 0000000..afde500
--- /dev/null
+++ b/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_mpy.asm
@@ -0,0 +1,15 @@
+
+	andi	#$00,CCR
+	move	#>0.25,x0
+	move	#>0.50,y0
+	mpy		x0,y0,a
+	move	#>-0.25,x0
+	move	#>-0.55,y0
+	mpy		x0,y0,a
+	move	#>-0.20,x0
+	move	#>+0.55,y0
+	mpy		x0,y0,a
+	move	#>-0.20,x0
+	move	#>+0.55,y0
+	mpy		-x0,y0,a
+
diff --git a/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_mpyr.asm b/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_mpyr.asm
new file mode 100644
index 0000000..847bccf
--- /dev/null
+++ b/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_mpyr.asm
@@ -0,0 +1,5 @@
+
+	andi	#$00,CCR
+	move	#>$654321,y0
+	mpyr	-y0,y0,a
+
diff --git a/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_neg.asm b/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_neg.asm
new file mode 100644
index 0000000..9fbc708
--- /dev/null
+++ b/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_neg.asm
@@ -0,0 +1,10 @@
+
+	andi	#$00,CCR
+	move	#>$654321,a
+	neg		a
+	clr		a
+	move 	#>$80,a2
+	neg		a
+	move	#>$800000,a
+	neg		a
+
diff --git a/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_norm.asm b/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_norm.asm
new file mode 100644
index 0000000..50749fe
--- /dev/null
+++ b/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_norm.asm
@@ -0,0 +1,14 @@
+	clr		a
+	move 	#$000001,a1
+	tst		a
+	rep		#$2F
+	norm	R3,a
+	clr		a
+	move 	#$FF0000,a
+	move	#$84,a2
+	tst		a
+	rep		#$2F
+	norm	R1,a
+	clr		a
+	rep		#$2F
+	norm	R2,a
diff --git a/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_not.asm b/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_not.asm
new file mode 100644
index 0000000..997fb45
--- /dev/null
+++ b/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_not.asm
@@ -0,0 +1,8 @@
+	move	#>$000FFF,y0
+	move	#>$7F00FF,b
+	andi	#$00,ccr
+	not 	b
+	move	#>$000000,y0
+	move	#>$FFFFFF,b
+	andi	#$00,ccr
+	not		b
diff --git a/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_or.asm b/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_or.asm
new file mode 100644
index 0000000..025991f
--- /dev/null
+++ b/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_or.asm
@@ -0,0 +1,8 @@
+	move	#>$000FFF,y0
+	move	#>$FF00FF,b
+	andi	#$00,ccr
+	or		y0,b
+	move	#>$000000,y0
+	move	#>$000000,b
+	andi	#$00,ccr
+	or		y0,b
diff --git a/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_rnd.asm b/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_rnd.asm
new file mode 100644
index 0000000..9c7f4bb
--- /dev/null
+++ b/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_rnd.asm
@@ -0,0 +1,11 @@
+
+	andi	#$00,CCR
+	move	#>$123456,a1
+	move	#>$789ABC,a0
+	rnd		a
+	move	#>$123456,a1
+	move	#>$800000,a0
+	rnd		a
+	move	#>$123455,a1
+	move	#>$800000,a0
+	rnd		a
diff --git a/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_rol.asm b/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_rol.asm
new file mode 100644
index 0000000..4f69ef6
--- /dev/null
+++ b/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_rol.asm
@@ -0,0 +1,6 @@
+
+	andi	#$00,CCR
+	move	#>$AAAAAA,a
+	move	#>$BCDEFA,a0
+	rep		#24
+	rol		a
diff --git a/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_ror.asm b/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_ror.asm
new file mode 100644
index 0000000..4fcca89
--- /dev/null
+++ b/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_ror.asm
@@ -0,0 +1,6 @@
+
+	andi	#$00,CCR
+	move	#>$AAAAAA,a
+	move	#>$BCDEFA,a0
+	rep		#24
+	ror		a
diff --git a/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_sbc.asm b/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_sbc.asm
new file mode 100644
index 0000000..7beb742
--- /dev/null
+++ b/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_sbc.asm
@@ -0,0 +1,15 @@
+	move	#>0,y0
+	move	#>1,y1
+	clr		b
+	move	#>1,b0
+; set only carry bit
+	andi	#$00,ccr
+	ori		#$01,ccr
+	sbc		y,b
+	move	#>$800000,y1
+	move	#>$80,b2
+	sbc		y,b
+	clr		b
+	move	#>$80,b2
+	move	#>$1,y1
+	sbc		y,b
diff --git a/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_sub.asm b/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_sub.asm
new file mode 100644
index 0000000..fa69320
--- /dev/null
+++ b/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_sub.asm
@@ -0,0 +1,15 @@
+	move	#>0,y0
+	move	#>1,y1
+	clr		b
+	move	#>1,b0
+; set only carry bit
+	andi	#$00,ccr
+	ori		#$01,ccr
+	sub		y,b
+	move	#>$800000,y1
+	move	#>$80,b2
+	sub		y,b
+	clr		b
+	move	#>$80,b2
+	move	#>$1,y1
+	sub		y1,b
diff --git a/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_subl.asm b/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_subl.asm
new file mode 100644
index 0000000..4d4a601
--- /dev/null
+++ b/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_subl.asm
@@ -0,0 +1,15 @@
+	move	#>0,a0
+	move	#>1,a1
+	clr		b
+	move	#>1,b0
+; set only carry bit
+	andi	#$00,ccr
+	ori		#$01,ccr
+	subl	a,b
+	move	#>$800000,a1
+	move	#>$80,b2
+	subl	a,b
+	clr		b
+	move	#>$80,b2
+	move	#>$1,a1
+	subl	a,b
diff --git a/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_subr.asm b/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_subr.asm
new file mode 100644
index 0000000..989ff9a
--- /dev/null
+++ b/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_subr.asm
@@ -0,0 +1,15 @@
+	move	#>0,a0
+	move	#>1,a1
+	clr		b
+	move	#>1,b0
+; set only carry bit
+	andi	#$00,ccr
+	ori		#$01,ccr
+	subr	a,b
+	move	#>$800000,a1
+	move	#>$80,b2
+	subr	a,b
+	clr		b
+	move	#>$80,b2
+	move	#>$1,a1
+	subr	a,b
diff --git a/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_tcc.asm b/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_tcc.asm
new file mode 100644
index 0000000..dd471b3
--- /dev/null
+++ b/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_tcc.asm
@@ -0,0 +1,10 @@
+	move	#20,r1
+	move	#$ABCDEF,x0
+	move	#$123456,b
+	andi	#$00,ccr
+	tcs		x0,a	r1,r3
+	tcc		x0,b	r1,r2	
+	; set Zero Flag
+	ori		#$04,ccr
+	teq		x0,a	r1,r3
+	tne		x0,b	r1,r2	
diff --git a/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_tfr.asm b/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_tfr.asm
new file mode 100644
index 0000000..26fa4c1
--- /dev/null
+++ b/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_tfr.asm
@@ -0,0 +1,7 @@
+	move	#$ABCDEF,a
+	move	#$123456,b
+	tfr		a,b	b,a
+	move	#$555555,x0
+	move	#$AAAAAA,y1
+	tfr		x0,a	a,x0
+	tfr		y1,b	b,y0
diff --git a/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_tst.asm b/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_tst.asm
new file mode 100644
index 0000000..b86e4a4
--- /dev/null
+++ b/FireBee/trunk/vhdl/dsp56k/asm/test_alu/test_tst.asm
@@ -0,0 +1,9 @@
+	clr		b
+	tst		b
+; set only carry bit
+	andi	#$00,ccr
+	ori		#$01,ccr
+	move	#>$80,b2
+	tst	b
+	move	#>$7F,b2
+	tst	b
diff --git a/FireBee/trunk/vhdl/dsp56k/asm/test_mem/test.asm b/FireBee/trunk/vhdl/dsp56k/asm/test_mem/test.asm
new file mode 100644
index 0000000..17599e4
--- /dev/null
+++ b/FireBee/trunk/vhdl/dsp56k/asm/test_mem/test.asm
@@ -0,0 +1,8 @@
+
+	move	#4,r0
+	move	#20,r1
+	move	r1,x:(r0)
+	move	x:(r0),a
+	move	r1,y:(r0)
+	move	l:(r0)+,ab
+
diff --git a/FireBee/trunk/vhdl/dsp56k/asm/test_pm_l/test.asm b/FireBee/trunk/vhdl/dsp56k/asm/test_pm_l/test.asm
new file mode 100644
index 0000000..821d39b
--- /dev/null
+++ b/FireBee/trunk/vhdl/dsp56k/asm/test_pm_l/test.asm
@@ -0,0 +1,21 @@
+
+	move	#>$10,x0
+	move	#>$11,x1
+	move	#11,a1
+	move	#-3,a2
+	jclr	#0,a,blubb
+	bset	#0,x:(r0)+
+	move	#>$26,y0
+	move	#>$27,y1
+	move	x,L:(r0)+
+	move	y,L:(r0)+
+	move	x,L:$0A
+	move	y,L:$1F
+	move	y,L:$00A0
+	move	x,L:$004F
+	move	L:-(r0),x
+	move	L:-(r0),y
+	move	L:$0A,x
+	move	L:$1F,y
+blubb
+
diff --git a/FireBee/trunk/vhdl/dsp56k/doc/Change.log b/FireBee/trunk/vhdl/dsp56k/doc/Change.log
new file mode 100644
index 0000000..1dc8d5b
--- /dev/null
+++ b/FireBee/trunk/vhdl/dsp56k/doc/Change.log
@@ -0,0 +1,185 @@
+Done:
+02.01.09
+ - Started work on pipeline (FE, FE2, DC, AG, EX)
+ - Program counter counts linearly
+ - Initial program memory holds program data
+ - Started work on instruction decoder
+03.01.09
+ - Jump instructions work (with flushing of the pipeline)
+ - First version of AGU implemented
+ - Detection of double word instructions
+ - Initial version of global register file
+04.01.09
+ - Included hardware stack
+ - Finished support for JSR and JSCC instructions
+ - RTI/RTS work
+ - ANDI/ORI work
+ - Initial work on REP instruction
+10.01.09
+ - Initial suppurt for X memory accesses. One stall cycle is introduced when
+   accessing the X memory.
+ - Finished implementation of REP instruction. Reading number of loops from
+   registers is still missing.
+ - Initial support for DO loops.
+ - Preventing to write the R registers when stalling occurs or a jump is
+   performed
+11.01.09
+ - Finished implementation of DO loops (stop looping at the end)
+ - Nested loops work
+ - Single instruction loops work
+ - ENDDO instruction implemented (very much the same as usual end of the loop)
+12.01.09
+ - Included Y memory and its addressing modes for REP and DO instruction.
+ - Setup of a sheet showing which types of which instructions have been 
+   implemented and how many clock cycles are needed.
+16.01.09
+ - Integration of LUA instruction.
+24.01.09
+ - Integrated different addressing schemes (immediate short, immediate long,
+   absolute address)
+ - Integration and test of MOVE(C) instruction. Some modes missing (writing to
+    memory)
+ - Testing of Y memory read accesses.
+26.01.09
+ - Continued testing of different addressing modes.
+ - Decoding for first parallel move operations.
+01.02.09
+ - Moved memory components to an extra entity (memory_management)
+ - Writing to internal X and Y memory supported. Problems are possible for 
+   reading the same address one instruction after writing at the same address!
+ - Included ALU registers (x,y,a,b) into register file
+ - Integration of x/y/l bus started
+03.02.09
+ - Continued testing of parallel moves (there are quite a few cases!)
+07.02.09
+ - Fixed REP instruction for instructions that are causing a stall due to
+   a memory read
+ - Fixed fetching from program data when stalling.
+ - Fixed detection of double word instruction, when previous instruction
+   used the AGU as well (forgot instruction word in sensitivity list).
+ - Continued testing of parallel moves.
+ - First synthesis run: Changed RAM description to map to BRAMs, removed 
+   latches, and many things are still missing, post-synthesis results:
+   - Xilinx Spartan3A, Speed-Grade -4
+   - 1488 FFs
+   - 4657 4-Input LUTs
+   - 3 BRAMs
+   - 71.08 MHz
+08.02.09
+  - Implemented second address generation unit in order to access X and Y
+    memory at the same time
+  - Implemented reverse carry addressing modes for FFT addressing
+  - Started implementation of modulo addressing.
+  - Set M0-M7 to -1 in reset.
+  - Downloaded the assembler for DSP56300. I hope to use it in order to
+    generate the content of the program memory automatically, which will
+    boost the testing speed...
+  - Encoding each instruction to test by hand just sucks. I think I will
+    integrate some bootloader in order to use the LOD files from the 
+    assembler to initiate the RAMs.
+  - Implementation of data shifter and limiter (when accessing a or b and
+    giving the result to XDB or YDB). Needs testing.
+  - Integration for L: addressing modes. Needs nesting.
+10.02.09
+  - Fixed decoding of X: and Y: adressing mode (collided with L: adressing)
+  - L: adressing modes are working
+14.02.09
+  - Implemented BCHG,BCLR,BSET,BTST,JCLR,JSCLR,JSET,JSSET. A lot of testing
+    is still needed. Peripheral register accesses are still missing.
+  - Second synthesis run: Removed new latches again.
+   , many things are still missing, post-synthesis results:
+   - Xilinx Spartan3A, Speed-Grade -4
+   - 1519 FFs
+   - 6210 4-Input LUTs
+   - 3 BRAMs
+   - 51.68 MHz
+   * Critical path for JSCLR/JSSET=> read limited a/b, go through bit modify
+     unit, test whether condition met, push data to stack. Reading of
+     limited A/B is probably a bug (DSP56001 UM says CCR is not changed,
+     in DSP56300 simulator the flag is set when reading a/b!!).
+15.02.09
+  - Started implementing the ALU.
+  - ABS works.
+  - MPY(R), MAC(R) implemented, rounding is missing.
+  - Clock frequency dropped to 41 MHz, but the critical path is not caused by
+    the MAC in the ALU! The multiplier is composed of four 18x18 multipliers
+    and still seems to be very fast!
+16.02.09
+  - Implemented decoding and controlling of ALU for
+    ADC, ADD, ADDL, ADDR, AND, ASL, ASR, CLR, CMP, CMPM, EOR, NEG, NOT, OR
+    Still missing ALU instructions:
+    DIV, NORM, RND, ROL, ROR, SBC, SUB, SUBL, SUBR, Tcc, TFR, TST
+    Except for DIV and NORM this will be straight forward.
+  - Other things that need to be done :
+    * Adress Generation Unit does not support modulo addressing.
+    * MOVEP/MOVEM/STOP/WAIT/ILLEGAL/RESET/SWI
+    * Interrupts
+    * External memory accesses
+    * Peripheral devices (SCI, SSI, Host port)
+17.02.09
+  - Implemented decoding and controlling of ALU instructions for
+    RND, ROL, ROR, SBC, SUB, SUBL, SUBR, TFR, TST
+    Still missing ALU instructions:
+    DIV, NORM, Tcc
+08.03.09
+  - Forgot integration of LSR and LSL instructions. TBD.
+  - Started integration of Condition flag generation in ALU.
+  - New synthesis run with ALU, register balancing: 
+   - Xilinx Spartan3A, Speed-Grade -4
+   - 3115 FFs
+   - 7417 4-Input LUTs
+   - 3 BRAMs
+   - 39.47 MHz
+13.03.09
+  - Integrated decoding of LSL/LSR instructions.
+  - Integrated rotating function into ALU.
+  - Included convergent rounding functionality into ALU.
+  - Implemented Tcc instruction.
+  - Implemented DIV instruction.
+15.03.09
+  - Tested ABS,ADC,ADD,ADDL,ADDR,AND,ASL,ASR,CLR,CMP,CMPM,DIV,EOR,
+    LSL,LSR,MPY,MPYR,MAC,MACR,NEG,NOT,OR
+  - Bugs fixed:
+    - Detection of overflow corrected when negating most negative
+      value $80 000000 000000.
+    - Decoding of ADC and TFR clarified.
+    - Overflow flag generation when left shifting of 56 bit values.
+    - For logical operations the flag generation relied on the adder
+      output which was wrong. Now relies on the Logical unit output.
+    - Decoding of CMPM clarified in order not to conflict with NOT.
+    - Shifter was used for CMP(M) instructions, which is wrong.
+    - Hopefully calculation of carry and overflow flag work correctly now...
+    - MPY/MAC write result back.
+    - Limit Flag is not cleared by the ALU anymore (has to be reset by the
+      user!).
+16.03.09
+  - Tested RND
+  - Bugs fixed:
+    - Simulator seems to misunderstand the X"1000000" where the first digit
+      represents a single bit. Comparing against this value fixed! RND works.
+
+17.03.09
+  - Tested ROR,ROL,SBC,SUB,SUBL,SUBR,TCC,TFR,TST,NORM
+  - Integrated logic for NORM instruction support.
+  - ALU is complete now!
+  - Bugs fixed:
+    - Fixed setting of CCR for ROL/ROR
+    - TCC didn't read register through ALU
+  - Known bugs:
+    - Carry calculation for SBC is still buggy
+  - New synthesis run with ALU, register balancing:
+   - Xilinx Spartan3A, Speed-Grade -4
+   - 1801 FFs
+   - 7407 4-Input LUTs
+   - 3 BRAMs
+   - 30.84 MHz
+   Critical path is in the ALU (multiplication, adding, rounding, zero-flag
+   calculation). I wonder why the values changed like that since the
+   last synthesis run.
+26.03.09
+  - Included support for modulo addressing in AGUs. This allows for the
+    integration of ring buffers. Now 7900 LUTs.
+18.05.10
+  - Commenting of code.
+  - Added second memory port for p-mem (needed for movem-instruction)
+
diff --git a/FireBee/trunk/vhdl/dsp56k/src/adgen_stage.vhd b/FireBee/trunk/vhdl/dsp56k/src/adgen_stage.vhd
new file mode 100644
index 0000000..df96c27
--- /dev/null
+++ b/FireBee/trunk/vhdl/dsp56k/src/adgen_stage.vhd
@@ -0,0 +1,291 @@
+------------------------------------------------------------------------------
+--! @file
+--! @author Matthias Alles
+--! @date 01/2009
+--! @brief Address generation logic
+--!
+------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.parameter_pkg.all;
+use work.types_pkg.all;
+use work.constants_pkg.all;
+
+entity adgen_stage is port(
+	activate_adgen    : in  std_logic;
+	activate_x_mem    : in  std_logic;
+	activate_y_mem    : in  std_logic;
+	activate_l_mem    : in  std_logic;
+	instr_word        : in  std_logic_vector(23 downto 0);
+	instr_array       : in  instructions_type;
+	optional_ea_word  : in  std_logic_vector(23 downto 0);
+	register_file     : in  register_file_type;
+	adgen_mode_a      : in  adgen_mode_type;
+	adgen_mode_b      : in  adgen_mode_type;
+	address_out_x     : out unsigned(BW_ADDRESS-1 downto 0);
+	address_out_y     : out unsigned(BW_ADDRESS-1 downto 0);
+	wr_R_port_A_valid : out std_logic;
+	wr_R_port_A       : out addr_wr_port_type;
+	wr_R_port_B_valid : out std_logic;
+	wr_R_port_B       : out addr_wr_port_type
+);
+end entity;
+
+
+architecture rtl of adgen_stage is
+
+	signal address_out_x_int : unsigned(BW_ADDRESS-1 downto 0);
+
+	signal r_reg_local_x : unsigned(BW_ADDRESS-1 downto 0);
+	signal n_reg_local_x : unsigned(BW_ADDRESS-1 downto 0);
+	signal m_reg_local_x : unsigned(BW_ADDRESS-1 downto 0);
+
+	signal r_reg_local_y : unsigned(BW_ADDRESS-1 downto 0);
+	signal n_reg_local_y : unsigned(BW_ADDRESS-1 downto 0);
+	signal m_reg_local_y : unsigned(BW_ADDRESS-1 downto 0);
+
+	function calculate_modulo_bitmask(m_reg_local : in unsigned ) return std_logic_vector is
+		variable modulo_bitmask_intern : std_logic_vector(BW_ADDRESS-1 downto 0);
+	begin
+		modulo_bitmask_intern(BW_ADDRESS-1) := m_reg_local(BW_ADDRESS-1);
+		for i in BW_ADDRESS-2 downto 0 loop
+			modulo_bitmask_intern(i) := modulo_bitmask_intern(i+1) or m_reg_local(i);
+		end loop;
+
+		return modulo_bitmask_intern;
+	end function calculate_modulo_bitmask;
+
+	function calculate_new_r_reg(new_r_reg_intermediate, r_reg_local, m_reg_local: in unsigned;
+	                             modulo_bitmask: in std_logic_vector ) return unsigned is
+		variable modulo_result : unsigned(BW_ADDRESS-1 downto 0);
+		variable new_r_reg_intern : unsigned(BW_ADDRESS-1 downto 0);
+	begin
+		-- cut out the bits we are interested in
+		-- for modulo addressing
+		for i in 0 to BW_ADDRESS-1 loop
+			if modulo_bitmask(i) = '1' then
+				modulo_result(i) := new_r_reg_intermediate(i);
+			else
+				modulo_result(i) := '0';
+			end if;
+		end loop;
+		-- compare whether an overflow occurred and we
+		-- have to renormalize the result
+		if modulo_result > m_reg_local then
+			modulo_result := modulo_result - m_reg_local;
+		end if;
+
+		-- linear addressing
+		if m_reg_local = 2**BW_ADDRESS-1 then 
+			new_r_reg_intern := new_r_reg_intermediate;
+		-- bit reverse operation
+		elsif m_reg_local = 0 then
+			for i in 0 to BW_ADDRESS-1 loop
+				new_r_reg_intern(BW_ADDRESS - 1 - i) := new_r_reg_intermediate(i);
+			end loop;
+		-- modulo arithmetic / linear addressing
+		else
+			-- only update the bits that are part of the bitmask!
+			for i in 0 to BW_ADDRESS-1 loop
+				if modulo_bitmask(i) = '1' then
+					new_r_reg_intern(i) := modulo_result(i);
+				else
+					new_r_reg_intern(i) := r_reg_local(i);
+				end if;
+			end loop;
+		end if;
+		return new_r_reg_intern;
+	end function calculate_new_r_reg;
+
+	procedure set_operands(r_reg_local, m_reg_local, addr_mod : in unsigned; op1, op2 : out unsigned) is
+	begin
+		-- bit reverse operation
+		if m_reg_local = 0 then
+			-- reverse the input to the adder bit wise
+			-- so we just need to use a single adder
+			for i in 0 to BW_ADDRESS-1 loop
+				op1(BW_ADDRESS - 1 - i) := r_reg_local(i);
+				op2(BW_ADDRESS - 1 - i) := addr_mod(i);
+			end loop;
+		-- modulo arithmetic / linear addressing
+		else
+			op1 := r_reg_local;
+			op2 := addr_mod;
+		end if;
+	end procedure set_operands;
+
+begin
+
+	address_out_x <= address_out_x_int;
+
+	r_reg_local_x <= register_file.addr_r(to_integer(unsigned(instr_word(10 downto 8))));
+	n_reg_local_x <= register_file.addr_n(to_integer(unsigned(instr_word(10 downto 8))));
+	m_reg_local_x <= register_file.addr_m(to_integer(unsigned(instr_word(10 downto 8))));
+
+	r_reg_local_y <= register_file.addr_r(to_integer(unsigned((not instr_word(10)) & instr_word(14 downto 13))));
+	n_reg_local_y <= register_file.addr_n(to_integer(unsigned((not instr_word(10)) & instr_word(14 downto 13))));
+	m_reg_local_y <= register_file.addr_m(to_integer(unsigned((not instr_word(10)) & instr_word(14 downto 13))));
+
+	address_generator_X: process(activate_adgen, instr_word, adgen_mode_a, r_reg_local_x, n_reg_local_x, m_reg_local_x) is
+		variable op1         : unsigned(BW_ADDRESS-1 downto 0);
+		variable op2         : unsigned(BW_ADDRESS-1 downto 0);
+		variable addr_mod    : unsigned(BW_ADDRESS-1 downto 0);
+		variable new_r_reg   : unsigned(BW_ADDRESS-1 downto 0);
+		variable new_r_reg_interm : unsigned(BW_ADDRESS-1 downto 0);
+		variable modulo_bitmask : std_logic_vector(BW_ADDRESS-1 downto 0);
+		variable modulo_result : unsigned(BW_ADDRESS-1 downto 0);
+	begin
+
+		-- select the operands for the calculation
+		case adgen_mode_a is
+			-- (Rn) - Nn
+			when POST_MIN_N =>  addr_mod := unsigned(- signed(n_reg_local_x));
+			-- (Rn) + Nn
+			when POST_PLUS_N => addr_mod :=   n_reg_local_x;
+			-- (Rn)-
+			when POST_MIN_1 =>  addr_mod := (others => '1'); -- -1
+			-- (Rn)+
+			when POST_PLUS_1 => addr_mod := to_unsigned(1, BW_ADDRESS);
+			-- (Rn)
+			when NOP =>         addr_mod := (others => '0');
+			-- (Rn + Nn)
+			when INDEXED_N =>   addr_mod := n_reg_local_x;
+			-- -(Rn)
+			when PRE_MIN_1 =>   addr_mod := (others => '1'); -- - 1
+			-- absolute address (appended to instruction word)
+			when ABSOLUTE =>    addr_mod := (others => '0');
+			when IMMEDIATE =>   addr_mod := (others => '0');
+		end case;
+
+		------------------------------------------------
+		-- set op1 and op2 according to modulo register
+		------------------------------------------------
+		set_operands(r_reg_local_x, m_reg_local_x, addr_mod, op1, op2);
+
+		-------------------------
+		-- Calculate new address
+		-------------------------
+		new_r_reg_interm := op1 + op2;
+
+		----------------------------------
+		-- Calculate new register content
+		-----------------------------------
+		modulo_bitmask := calculate_modulo_bitmask(m_reg_local_x);
+		new_r_reg := calculate_new_r_reg(new_r_reg_interm, r_reg_local_x, m_reg_local_x, modulo_bitmask);
+
+		-- store the updated register in the global register file
+		-- do not store when we do nothing or there is nothing to update
+		-- LUA instructions DO NOT UPDATE the source register!!
+		if (adgen_mode_a = NOP or adgen_mode_a = ABSOLUTE or adgen_mode_a = IMMEDIATE or instr_array = INSTR_LUA) then
+			wr_R_port_A_valid <= '0';
+		else
+			wr_R_port_A_valid <= '1';
+		end if;
+		wr_R_port_A.reg_number <= unsigned(instr_word(10 downto 8));
+		wr_R_port_A.reg_value  <= new_r_reg;
+
+		-- select the output of the AGU
+		case adgen_mode_a is
+			-- (Rn) - Nn
+			when POST_MIN_N =>  address_out_x_int <= r_reg_local_x;
+			-- (Rn) + Nn
+			when POST_PLUS_N => address_out_x_int <= r_reg_local_x;
+			-- (Rn)-
+			when POST_MIN_1 =>  address_out_x_int <= r_reg_local_x;
+			-- (Rn)+
+			when POST_PLUS_1 => address_out_x_int <= r_reg_local_x;
+			-- (Rn)
+			when NOP =>         address_out_x_int <= r_reg_local_x;
+			-- (Rn + Nn)
+			when INDEXED_N =>   address_out_x_int <= new_r_reg;
+			-- -(Rn)
+			when PRE_MIN_1 =>   address_out_x_int <= new_r_reg;
+			-- absolute address (appended to instruction word)
+			when ABSOLUTE =>    address_out_x_int <= unsigned(optional_ea_word(BW_ADDRESS-1 downto 0));
+			when IMMEDIATE =>   address_out_x_int <= r_reg_local_x; -- Done externally, value never used
+		end case;
+		-- LUA instructions only use the updated address!
+		if instr_array = INSTR_LUA then
+			address_out_x_int <= new_r_reg;
+		end if;
+
+	end process address_generator_X;
+
+
+	---------------------------------------------------------
+	-- Second address generator
+	-- Used when accessing X and Y memory at the same time
+	---------------------------------------------------------
+	address_generator_Y: process(activate_adgen, activate_x_mem, activate_y_mem, activate_l_mem, instr_word,
+	                             register_file, adgen_mode_b, address_out_x_int, r_reg_local_y, n_reg_local_y, m_reg_local_y) is
+		variable op1         : unsigned(BW_ADDRESS-1 downto 0);
+		variable op2         : unsigned(BW_ADDRESS-1 downto 0);
+		variable addr_mod    : unsigned(BW_ADDRESS-1 downto 0);
+		variable new_r_reg   : unsigned(BW_ADDRESS-1 downto 0);
+		variable new_r_reg_interm : unsigned(BW_ADDRESS-1 downto 0);
+		variable modulo_bitmask : std_logic_vector(BW_ADDRESS-1 downto 0);
+		variable modulo_result : unsigned(BW_ADDRESS-1 downto 0);
+	begin
+
+		-- select the operands for the calculation
+		case adgen_mode_b is
+			-- (Rn) + Nn
+			when POST_PLUS_N => addr_mod :=   n_reg_local_y;
+			-- (Rn)-
+			when POST_MIN_1  => addr_mod := (others => '1'); -- -1
+			-- (Rn)+
+			when POST_PLUS_1 => addr_mod := to_unsigned(1, BW_ADDRESS);
+			-- (Rn)
+			when others      => addr_mod := (others => '0');
+		end case;
+
+		------------------------------------------------
+		-- set op1 and op2 according to modulo register
+		------------------------------------------------
+		set_operands(r_reg_local_y, m_reg_local_y, addr_mod, op1, op2);
+
+		-------------------------
+		-- Calculate new address
+		-------------------------
+		new_r_reg_interm := op1 + op2;
+
+		----------------------------------
+		-- Calculate new register content
+		-----------------------------------
+		modulo_bitmask := calculate_modulo_bitmask(m_reg_local_y);
+		new_r_reg := calculate_new_r_reg(new_r_reg_interm, r_reg_local_y, m_reg_local_y, modulo_bitmask);
+
+		-- store the updated register in the global register file
+		-- do not store when we do nothing or there is nothing to update
+		if adgen_mode_b = NOP then
+			wr_R_port_B_valid <= '0';
+		else
+			wr_R_port_B_valid <= '1';
+		end if;
+		wr_R_port_B.reg_number <= unsigned((not instr_word(10)) & instr_word(14 downto 13));
+		wr_R_port_B.reg_value  <= new_r_reg;
+
+		-- the address for the y memory is calculated in the first AGU if the x memory is not accessed!
+		-- so use the other output as address output for the y memory!
+		-- Furthermore, use the same address for L memory accesses (X and Y memory access the same address!)
+		if (activate_y_mem = '1' and activate_x_mem = '0') or activate_l_mem = '1' then
+			address_out_y <= address_out_x_int;
+		-- in any other case use the locally computed value
+		else
+			-- select the output of the AGU
+			case adgen_mode_b is
+				-- (Rn) + Nn
+				when POST_PLUS_N => address_out_y <= r_reg_local_y;
+				-- (Rn)-
+				when POST_MIN_1  => address_out_y <= r_reg_local_y;
+				-- (Rn)+
+				when POST_PLUS_1 => address_out_y <= r_reg_local_y;
+				-- (Rn)
+				when others      => address_out_y <= r_reg_local_y;
+			end case;
+		end if;
+	end process address_generator_Y;
+
+end architecture;
diff --git a/FireBee/trunk/vhdl/dsp56k/src/constants_pkg.vhd b/FireBee/trunk/vhdl/dsp56k/src/constants_pkg.vhd
new file mode 100644
index 0000000..c84a406
--- /dev/null
+++ b/FireBee/trunk/vhdl/dsp56k/src/constants_pkg.vhd
@@ -0,0 +1,74 @@
+------------------------------------------------------------------------------
+--! @file
+--! @author Matthias Alles
+--! @date 01/2009
+--! @brief General constants for decoding pipeline.
+--!
+------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.parameter_pkg.all;
+use work.types_pkg.all;
+
+
+package constants_pkg is
+
+
+	-------------------------
+	-- Flags in CCR register
+	-------------------------
+
+	constant C_FLAG : natural := 0;
+	constant V_FLAG : natural := 1;
+	constant Z_FLAG : natural := 2;
+	constant N_FLAG : natural := 3;
+	constant U_FLAG : natural := 4;
+	constant E_FLAG : natural := 5;
+	constant L_FLAG : natural := 6;
+	constant S_FLAG : natural := 7;
+
+
+	-------------------
+	-- Pipeline stages
+	-------------------
+
+	constant ST_FE_FE2  : natural := 0;
+	constant ST_FE2_DEC : natural := 1;
+	constant ST_DEC_ADG : natural := 2;
+	constant ST_ADG_EX  : natural := 3;
+
+
+	----------------------
+	-- Activation signals
+	----------------------
+
+	constant ACT_ADGEN       : natural := 0; -- Run the address generator
+	constant ACT_ALU         : natural := 1; -- Activation of ALU results in modification of the status register
+	constant ACT_EXEC_BRA    : natural := 2; -- Branch (in execute stage)
+	constant ACT_EXEC_CR_MOD : natural := 3; -- Control Register Modification (in execute stage)
+	constant ACT_EXEC_LOOP   : natural := 4; -- Loop instruction (REP, DO)
+	constant ACT_X_MEM_RD    : natural := 5; -- Init read from X memory
+	constant ACT_Y_MEM_RD    : natural := 6; -- Init read from Y memory
+	constant ACT_P_MEM_RD    : natural := 7; -- Init read from P memory
+	constant ACT_X_MEM_WR    : natural := 8; -- Init write to  X memory
+	constant ACT_Y_MEM_WR    : natural := 9; -- Init write to  Y memory
+	constant ACT_P_MEM_WR    : natural := 10; -- Init write to P memory
+	constant ACT_REG_RD      : natural := 11; -- Read from register (6 bit addressing)
+	constant ACT_REG_WR      : natural := 12; -- Write to register (6 bit addressing)
+	constant ACT_IMM_8BIT    : natural := 13; -- 8 bit  immediate operand (in instruction word)
+	constant ACT_IMM_12BIT   : natural := 14; -- 12 bit immediate operand (in instruction word)
+	constant ACT_IMM_LONG    : natural := 15; -- 24 bit immediate operant (in optional instruction word)
+	constant ACT_X_BUS_RD    : natural := 16; -- Read  data via X-bus (from x0,x1,a,b)
+	constant ACT_X_BUS_WR    : natural := 17; -- Write data via X-bus (to   x0,x1,a,b)
+	constant ACT_Y_BUS_RD    : natural := 18; -- Read  data via Y-bus (from y0,y1,a,b)
+	constant ACT_Y_BUS_WR    : natural := 19; -- Write data via Y-bus (to   y0,y1,a,b)
+	constant ACT_L_BUS_RD    : natural := 20; -- Read  data via L-bus (from a10, b10,x,y,a,b,ab,ba)
+	constant ACT_L_BUS_WR    : natural := 21; -- Write data via L-bus (to   a10, b10,x,y,a,b,ab,ba)
+	constant ACT_BIT_MOD_WR  : natural := 22; -- Bit modify write (to set for BSET, BCLR, BCHG)
+	constant ACT_REG_WR_CC   : natural := 23; -- Write to register file conditionally (Tcc)
+	constant ACT_ALU_WR_CC   : natural := 24; -- Write ALU result conditionally (Tcc)
+	constant ACT_NORM        : natural := 25; -- NORM instruction needs special handling
+
+end package constants_pkg;
diff --git a/FireBee/trunk/vhdl/dsp56k/src/decode_stage.vhd b/FireBee/trunk/vhdl/dsp56k/src/decode_stage.vhd
new file mode 100644
index 0000000..0725c6b
--- /dev/null
+++ b/FireBee/trunk/vhdl/dsp56k/src/decode_stage.vhd
@@ -0,0 +1,1226 @@
+------------------------------------------------------------------------------
+--! @file
+--! @author Matthias Alles
+--! @date 01/2009
+--! @brief Instruction Decoder
+--!
+--! @details This entity generates multiple flags depending on the instruction
+--! word. The flags are used for activation of certain logic units within the
+--! subsequent pipeline stages (ALU, AGU, bit modifications, ...). Also the
+--! decoder checks whether currently we are processing a double word 
+--! instruction.
+--!
+------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.parameter_pkg.all;
+use work.types_pkg.all;
+use work.constants_pkg.all;
+
+entity decode_stage is port(
+	activate_dec    : in  std_logic;
+	instr_word      : in  std_logic_vector(23 downto 0);
+	dble_word_instr : out std_logic;
+	instr_array     : out instructions_type;
+	act_array       : out std_logic_vector(NUM_ACT_SIGNALS-1 downto 0);
+	reg_wr_addr     : out std_logic_vector(5 downto 0);
+	reg_rd_addr     : out std_logic_vector(5 downto 0);
+	x_bus_rd_addr   : out std_logic_vector(1 downto 0); 
+	x_bus_wr_addr   : out std_logic_vector(1 downto 0); 
+	y_bus_rd_addr   : out std_logic_vector(1 downto 0); 
+	y_bus_wr_addr   : out std_logic_vector(1 downto 0); 
+	l_bus_addr      : out std_logic_vector(2 downto 0); 
+	adgen_mode_a    : out adgen_mode_type;
+	adgen_mode_b    : out adgen_mode_type;
+	alu_ctrl        : out alu_ctrl_type
+);
+end entity;
+
+
+architecture rtl of decode_stage is
+
+	signal instr_array_int : instructions_type;
+--	signal activate_pm_int : std_logic;
+	type adgen_bittype_type is (NOP, SINGLE_X, SINGLE_X_SHORT, DOUBLE_X_Y);
+	-- SINGLE_X       : MMMRRR
+	-- SINGLE_X_SHORT :  MMRRR
+	-- DOUBLE_X_Y     : mmrrMMRRR
+	signal adgen_bittype : adgen_bittype_type;
+
+	signal ea_extension_available : std_logic;
+
+	signal alu_tcc_decoded : std_logic;
+	signal alu_div_decoded : std_logic;
+	signal alu_norm_decoded : std_logic;
+
+begin
+
+
+	-- output the decoded instruction
+	instr_array <= instr_array_int;
+
+	-- calculate whether this is a double word instruction
+	dble_word_instr <= '1' when ea_extension_available = '1'  or
+	                            instr_array_int = INSTR_DO    or
+	                            instr_array_int = INSTR_JCLR  or
+	                            instr_array_int = INSTR_JSCLR or
+	                            instr_array_int = INSTR_JSET  or
+	                            instr_array_int = INSTR_JSSET else
+	                   '0';
+
+	alu_instruction_decoder: process(instr_word, activate_dec, alu_tcc_decoded,
+	                                 alu_div_decoded, alu_norm_decoded) is
+		variable instr_word_var : std_logic_vector(23 downto 0);
+	begin
+		if activate_dec = '1' then
+			instr_word_var := instr_word;
+		else
+			instr_word_var := (others => '0');
+		end if;
+		
+		alu_ctrl.mul_op1 <= (others => '0');
+		alu_ctrl.mul_op2 <= (others => '0');
+		alu_ctrl.rotate <= '0';
+		alu_ctrl.div_instr <= '0';
+		alu_ctrl.norm_instr <= '0';
+		alu_ctrl.shift_src <= '0';
+		alu_ctrl.shift_src_sign <= (others => '0');
+		alu_ctrl.shift_mode <= ZEROS;
+		alu_ctrl.add_src_stage_1 <= (others => '0');
+		alu_ctrl.add_src_stage_2 <= (others => '0');
+		alu_ctrl.add_src_sign    <= (others => '0');
+		alu_ctrl.logic_function  <= (others => '0');
+		alu_ctrl.word_24_update  <= '0';
+		alu_ctrl.rounding_used   <= (others => '0');
+		alu_ctrl.store_result    <= '0';
+		for i in 0 to 7 loop -- by default do not touch any of the ccr flags (L;E;U;N;Z;V;C)
+			alu_ctrl.ccr_flags_ctrl(i) <= DONT_TOUCH;
+		end loop;
+		alu_ctrl.dst_accu <= instr_word_var(3); -- default value for all alu operations
+
+		-- check wether instruction that allows parallel moves 
+		-- has to be decoded, then it is an ALU operation in the 8 LSBs
+		-- Only exceptions are DIV, NORM, and Tcc
+		if instr_word_var(23 downto 20) /= "0000" then
+			-- ABS
+			if instr_word_var(7 downto 4) = "0010" and instr_word_var(2 downto 0) = "110" then
+				-- Read accu
+				alu_ctrl.shift_mode <= NO_SHIFT;
+				alu_ctrl.shift_src  <= instr_word_var(3); -- source/dst are the same register 
+				alu_ctrl.shift_src_sign <= "10";  -- the sign of the operand depends on the operand 
+				                                  -- negative operand will negate the content of the accu as
+				                                  -- needed by the ABS instruction
+				alu_ctrl.add_src_stage_2 <= "00"; -- select zero
+				alu_ctrl.store_result <= '1';     -- store the result
+				-- set all flags but carry
+				for i in 1 to 7 loop
+					alu_ctrl.ccr_flags_ctrl(i) <= MODIFY;
+				end loop;
+			end if;
+			-- ADC
+			if instr_word_var(7 downto 5) = "001" and instr_word_var(2 downto 0) = "001" then
+				-- Read accu
+				alu_ctrl.shift_mode <= NO_SHIFT;
+				alu_ctrl.shift_src  <= instr_word_var(3); -- accumulate to the same register we want to write to
+				alu_ctrl.shift_src_sign <= "00";          -- with the original sign
+				-- Read S
+				alu_ctrl.add_src_stage_1 <= "01" & instr_word_var(4); -- X or Y
+				alu_ctrl.add_src_stage_2 <= "01"; -- select the register source
+				alu_ctrl.add_src_sign    <= "00"; -- with original sign
+				alu_ctrl.store_result    <= '1';  -- store the result
+				alu_ctrl.rounding_used   <= "10"; -- add carry to result of addition
+				-- set all flags
+				for i in 0 to 7 loop
+					alu_ctrl.ccr_flags_ctrl(i) <= MODIFY;
+				end loop;
+			end if;
+			-- ADD
+			if instr_word_var(7) = '0' and instr_word_var(2 downto 0) = "000" and instr_word_var(6 downto 4) /= "000" then
+				-- Read accu
+				alu_ctrl.shift_mode <= NO_SHIFT;
+				alu_ctrl.shift_src  <= instr_word_var(3); -- accumulate to the same register we want to write to
+				alu_ctrl.shift_src_sign <= "00";          -- with the original sign
+				-- Read S
+				alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 4); -- source register (JJJ encoding)
+				alu_ctrl.add_src_stage_2 <= "01"; -- select the register source
+				alu_ctrl.add_src_sign    <= "00"; -- with original sign
+				alu_ctrl.store_result    <= '1';  -- store the result
+				alu_ctrl.rounding_used   <= "00"; -- no rounding needed
+				-- set all flags
+				for i in 0 to 7 loop
+					alu_ctrl.ccr_flags_ctrl(i) <= MODIFY;
+				end loop;
+			end if;
+			-- ADDL
+			if instr_word_var(7 downto 4) = "0001" and instr_word_var(2 downto 0) = "010" then
+				-- Read accu
+				alu_ctrl.shift_mode <= SHIFT_LEFT;
+				alu_ctrl.shift_src  <= instr_word_var(3); -- accumulate to the same register we want to write to
+				alu_ctrl.shift_src_sign <= "00";          -- with the original sign
+				-- Read S
+				alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 4); -- source register (JJJ encoding) (here: A,B)
+				alu_ctrl.add_src_stage_2 <= "01"; -- select the register source
+				alu_ctrl.add_src_sign    <= "00"; -- with original sign
+				alu_ctrl.store_result    <= '1';  -- store the result
+				alu_ctrl.rounding_used   <= "00"; -- no rounding needed
+				-- set all flags
+				for i in 0 to 7 loop
+					alu_ctrl.ccr_flags_ctrl(i) <= MODIFY;
+				end loop;
+			end if;
+			-- ADDR
+			if instr_word_var(7 downto 4) = "0000" and instr_word_var(2 downto 0) = "010" then
+				-- Read accu
+				alu_ctrl.shift_mode <= SHIFT_RIGHT;
+				alu_ctrl.shift_src  <= instr_word_var(3); -- accumulate to the same register we want to write to
+				alu_ctrl.shift_src_sign <= "00";          -- with the original sign
+				-- Read S
+				alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 5) & '1'; -- source register (JJJ encoding) (here: A,B)
+				alu_ctrl.add_src_stage_2 <= "01"; -- select the register source
+				alu_ctrl.add_src_sign    <= "00"; -- with original sign
+				alu_ctrl.store_result    <= '1';  -- store the result
+				alu_ctrl.rounding_used   <= "00"; -- no rounding needed
+				-- set all flags
+				for i in 0 to 7 loop
+					alu_ctrl.ccr_flags_ctrl(i) <= MODIFY;
+				end loop;
+			end if;
+			-- AND / OR / EOR
+			if instr_word_var(7 downto 6) = "01" and (instr_word_var(2 downto 0) = "110" or -- and
+			                                          instr_word_var(2 downto 0) = "010" or -- or
+				                                      instr_word_var(2 downto 0) = "011") then -- eor
+				alu_ctrl.logic_function <= instr_word_var(2 downto 0);  -- 000: none, 110: and, 010: or, 011: eor, 111: not
+				alu_ctrl.word_24_update <= '1';  -- only accumulator bits 47 downto 24 affected?
+				-- Read accu
+				alu_ctrl.shift_mode <= NO_SHIFT;
+				alu_ctrl.shift_src  <= instr_word_var(3); -- accumulate to the same register we want to write to
+				alu_ctrl.shift_src_sign <= "00";          -- with the original sign
+				-- Read S
+				alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 4); -- source register (JJJ encoding) (here: A,B)
+				alu_ctrl.add_src_stage_2 <= "01"; -- select the register source
+				alu_ctrl.add_src_sign    <= "00"; -- with original sign
+				alu_ctrl.store_result    <= '1';  -- store the result
+				alu_ctrl.rounding_used   <= "00"; -- no rounding needed
+				-- set following flags
+				alu_ctrl.ccr_flags_ctrl(N_FLAG) <= MODIFY;
+				alu_ctrl.ccr_flags_ctrl(Z_FLAG) <= MODIFY;
+				alu_ctrl.ccr_flags_ctrl(V_FLAG) <= CLEAR;
+			end if;
+			-- ASL
+			if instr_word_var(7 downto 4) = "0011" and instr_word_var(2 downto 0) = "010" then
+				-- Read accu
+				alu_ctrl.shift_mode <= SHIFT_LEFT;
+				alu_ctrl.shift_src  <= instr_word_var(3); -- accumulate to the same register we want to write to
+				alu_ctrl.shift_src_sign <= "00";          -- with the original sign
+				-- Read S
+				alu_ctrl.add_src_stage_2 <= "00"; -- select zero as operand
+				alu_ctrl.add_src_sign    <= "00"; -- with original sign
+				alu_ctrl.store_result    <= '1';  -- store the result
+				alu_ctrl.rounding_used   <= "00"; -- no rounding needed
+				-- set all flags
+				for i in 0 to 7 loop
+					alu_ctrl.ccr_flags_ctrl(i) <= MODIFY;
+				end loop;
+			end if;
+			-- ASR
+			if instr_word_var(7 downto 4) = "0010" and instr_word_var(2 downto 0) = "010" then
+				-- Read accu
+				alu_ctrl.shift_mode <= SHIFT_RIGHT;
+				alu_ctrl.shift_src  <= instr_word_var(3); -- accumulate to the same register we want to write to
+				alu_ctrl.shift_src_sign <= "00";          -- with the original sign
+				-- Read S
+				alu_ctrl.add_src_stage_2 <= "00"; -- select zero as operand
+				alu_ctrl.add_src_sign    <= "00"; -- with original sign
+				alu_ctrl.store_result    <= '1';  -- store the result
+				alu_ctrl.rounding_used   <= "00"; -- no rounding needed
+				-- set all flags, V-flag will be cleared due to shifting
+				for i in 0 to 7 loop
+					alu_ctrl.ccr_flags_ctrl(i) <= MODIFY;
+				end loop;
+			end if;
+			-- CLR
+			if instr_word_var(7 downto 4) = "0001" and instr_word_var(2 downto 0) = "011" then
+				-- Read accu
+				alu_ctrl.shift_mode <= ZEROS;
+				-- Read S
+				alu_ctrl.add_src_stage_2 <= "00"; -- select zero as operand
+				alu_ctrl.add_src_sign    <= "00"; -- with original sign
+				alu_ctrl.store_result    <= '1';  -- store the result
+				alu_ctrl.rounding_used   <= "00"; -- no rounding needed
+				-- set following flags
+				alu_ctrl.ccr_flags_ctrl(S_FLAG) <= MODIFY;
+				alu_ctrl.ccr_flags_ctrl(E_FLAG) <= MODIFY;
+				alu_ctrl.ccr_flags_ctrl(U_FLAG) <= MODIFY;
+				alu_ctrl.ccr_flags_ctrl(N_FLAG) <= MODIFY;
+				alu_ctrl.ccr_flags_ctrl(Z_FLAG) <= MODIFY;
+				alu_ctrl.ccr_flags_ctrl(V_FLAG) <= CLEAR;
+			end if;
+			-- CMP
+			if instr_word_var(7) = '0' and instr_word_var(6 downto 5) /= "01" and 
+			   instr_word_var(2 downto 0) = "101" then
+				-- Read accu
+				alu_ctrl.shift_mode <= NO_SHIFT;
+				alu_ctrl.shift_src  <= instr_word_var(3); -- accumulate to the same register we want to write to
+				alu_ctrl.shift_src_sign <= "00";          -- with the original sign
+				-- Read S
+				if instr_word_var(6) = '1' then
+					alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 4); -- source register (JJJ encoding) x0,x1,y0,y1
+				else
+					alu_ctrl.add_src_stage_1 <= "001"; -- select opposite accu (JJJ encoding)
+				end if;
+				alu_ctrl.add_src_stage_2 <= "01"; -- select the register source
+				alu_ctrl.add_src_sign    <= "01"; -- with negative sign
+				alu_ctrl.store_result    <= '0';  -- do not store the result
+				alu_ctrl.rounding_used   <= "00"; -- no rounding needed
+				-- set all flags
+				for i in 0 to 7 loop
+					alu_ctrl.ccr_flags_ctrl(i) <= MODIFY;
+				end loop;
+			end if;
+			-- CMPM
+			if instr_word_var(7) = '0' and instr_word_var(6 downto 5) /= "01" and 
+		       instr_word_var(2 downto 0) = "111" then
+				-- Read accu
+				alu_ctrl.shift_mode <= NO_SHIFT;
+				alu_ctrl.shift_src  <= instr_word_var(3); -- accumulate to the same register we want to write to
+				alu_ctrl.shift_src_sign <= "10";          -- with the sign dependant sign (magnitude!)
+				-- Read S
+				if instr_word_var(6) = '1' then
+					alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 4); -- source register (JJJ encoding) x0,x1,y0,y1
+				else
+					alu_ctrl.add_src_stage_1 <= "001"; -- select opposite accu (JJJ encoding)
+				end if;
+				alu_ctrl.add_src_stage_2 <= "01"; -- select the register source
+				alu_ctrl.add_src_sign    <= "10"; -- with sign dependant sign (magnitude!)
+				alu_ctrl.store_result    <= '0';  -- do not store the result
+				alu_ctrl.rounding_used   <= "00"; -- no rounding needed
+				-- set all flags
+				for i in 0 to 7 loop
+					alu_ctrl.ccr_flags_ctrl(i) <= MODIFY;
+				end loop;
+			end if;
+			-- LSL
+			if instr_word_var(7 downto 4) = "0011" and instr_word_var(2 downto 0) = "011" then
+				alu_ctrl.word_24_update <= '1';
+				-- Read accu
+				alu_ctrl.shift_mode <= SHIFT_LEFT;
+				alu_ctrl.shift_src  <= instr_word_var(3); -- accumulate to the same register we want to write to
+				alu_ctrl.shift_src_sign <= "00";          -- with normal sign
+				alu_ctrl.store_result    <= '1';  -- store the result
+				alu_ctrl.rounding_used   <= "00"; -- no rounding needed
+				alu_ctrl.add_src_stage_2 <= "00"; -- select zero as second operand
+				-- set N,Z,V,C flags
+				for i in 0 to 3 loop
+					alu_ctrl.ccr_flags_ctrl(i) <= MODIFY;
+				end loop;
+			end if;
+			-- LSR
+			if instr_word_var(7 downto 4) = "0010" and instr_word_var(2 downto 0) = "011" then
+				alu_ctrl.word_24_update <= '1';
+				-- Read accu
+				alu_ctrl.shift_mode <= SHIFT_RIGHT;
+				alu_ctrl.shift_src  <= instr_word_var(3); -- accumulate to the same register we want to write to
+				alu_ctrl.shift_src_sign <= "00";          -- with normal sign
+				alu_ctrl.store_result    <= '1';  -- store the result
+				alu_ctrl.rounding_used   <= "00"; -- no rounding needed
+				alu_ctrl.add_src_stage_2 <= "00"; -- select zero as second operand
+				-- set N,Z,V,C flags
+				for i in 0 to 3 loop
+					alu_ctrl.ccr_flags_ctrl(i) <= MODIFY;
+				end loop;
+			end if;
+			-- MPY, MPYR, MAC, MACR
+			if instr_word_var(7) = '1' then
+				case instr_word_var(6 downto 4) is
+					when "000"  => alu_ctrl.mul_op1 <= "00"; alu_ctrl.mul_op2 <= "00"; -- x0,x0
+					when "001"  => alu_ctrl.mul_op1 <= "10"; alu_ctrl.mul_op2 <= "10"; -- y0,y0
+					when "010"  => alu_ctrl.mul_op1 <= "01"; alu_ctrl.mul_op2 <= "00"; -- x1,x0
+					when "011"  => alu_ctrl.mul_op1 <= "11"; alu_ctrl.mul_op2 <= "10"; -- y1,y0
+					when "100"  => alu_ctrl.mul_op1 <= "00"; alu_ctrl.mul_op2 <= "11"; -- x0,y1
+					when "101"  => alu_ctrl.mul_op1 <= "10"; alu_ctrl.mul_op2 <= "00"; -- y0,x0
+					when "110"  => alu_ctrl.mul_op1 <= "01"; alu_ctrl.mul_op2 <= "10"; -- x1,y0
+					when others => alu_ctrl.mul_op1 <= "11"; alu_ctrl.mul_op2 <= "01"; -- y1,x1
+				end case;
+				alu_ctrl.store_result    <= '1';  -- store result in accu
+				alu_ctrl.add_src_stage_2 <= "10"; -- select mul out for adder!
+				alu_ctrl.add_src_sign    <= '0' & instr_word_var(2); -- select +/-
+				alu_ctrl.rounding_used   <= '0' & instr_word_var(0); -- rounding is determined by that bit!
+				if instr_word_var(1) = '0' then -- MPY(R)
+					alu_ctrl.shift_mode <= ZEROS;
+				else -- MAC(R)
+					alu_ctrl.shift_mode <= NO_SHIFT;
+					alu_ctrl.shift_src  <= instr_word_var(3); -- accumulate to the same register we want to write to
+					alu_ctrl.shift_src_sign <= "00";          -- with the original sign
+				end if;
+				-- set all flags but carry!
+				for i in 1 to 7 loop
+					alu_ctrl.ccr_flags_ctrl(i) <= MODIFY;
+				end loop;
+			end if;
+			-- NEG
+			if instr_word_var(7 downto 4) = "0011" and instr_word_var(2 downto 0) = "110" then
+				-- Read accu
+				alu_ctrl.shift_mode <= ZEROS;
+--				alu_ctrl.shift_src  <= instr_word_var(3); -- accumulate to the same register we want to write to
+--				alu_ctrl.shift_src_sign <= "01";          -- with negative sign
+				-- Read Accu
+				alu_ctrl.add_src_stage_1 <= "000"; -- source register equal to dst_register
+				alu_ctrl.add_src_stage_2 <= "01"; -- select register as operand
+				alu_ctrl.add_src_sign    <= "01"; -- with negative sign
+				alu_ctrl.store_result    <= '1';  -- store the result
+				alu_ctrl.rounding_used   <= "00"; -- no rounding needed
+				-- set all flags but carry!
+				for i in 1 to 7 loop
+					alu_ctrl.ccr_flags_ctrl(i) <= MODIFY;
+				end loop;
+			end if;
+			-- NOT
+			if instr_word_var(7 downto 4) = "0001" and instr_word_var(2 downto 0) = "111" then
+				alu_ctrl.word_24_update <= '1';
+				-- Read accu
+				alu_ctrl.shift_mode <= NO_SHIFT;
+				alu_ctrl.shift_src  <= instr_word_var(3); -- accumulate to the same register we want to write to
+				alu_ctrl.shift_src_sign <= "00";          -- with normal sign
+				alu_ctrl.logic_function  <= instr_word_var(2 downto 0); -- select not operation
+				alu_ctrl.store_result    <= '1';  -- store the result
+				alu_ctrl.rounding_used   <= "00"; -- no rounding needed
+				-- set following flags
+				alu_ctrl.ccr_flags_ctrl(N_FLAG) <= MODIFY;
+				alu_ctrl.ccr_flags_ctrl(Z_FLAG) <= MODIFY;
+				alu_ctrl.ccr_flags_ctrl(V_FLAG) <= CLEAR;
+			end if;
+			-- RND
+			if instr_word_var(7 downto 4) = "0001" and instr_word_var(2 downto 0) = "001" then
+				-- Read accu
+				alu_ctrl.shift_mode <= NO_SHIFT;
+				alu_ctrl.shift_src  <= instr_word_var(3); -- accumulate to the same register we want to write to
+				alu_ctrl.shift_src_sign <= "00";          -- with normal sign
+				alu_ctrl.store_result    <= '1';  -- store the result
+				alu_ctrl.rounding_used   <= "01"; -- normal rounding needed
+				alu_ctrl.add_src_stage_2 <= "00"; -- select zero as second operand
+				-- set all flags but carry!
+				for i in 1 to 7 loop
+					alu_ctrl.ccr_flags_ctrl(i) <= MODIFY;
+				end loop;
+			end if;
+			-- ROL
+			if instr_word_var(7 downto 4) = "0011" and instr_word_var(2 downto 0) = "111" then
+				alu_ctrl.word_24_update <= '1';
+				alu_ctrl.rotate <= '1';
+				-- Read accu
+				alu_ctrl.shift_mode <= SHIFT_LEFT;
+				alu_ctrl.shift_src  <= instr_word_var(3); -- accumulate to the same register we want to write to
+				alu_ctrl.shift_src_sign <= "00";          -- with normal sign
+				alu_ctrl.store_result    <= '1';  -- store the result
+				alu_ctrl.rounding_used   <= "00"; -- no rounding needed
+				alu_ctrl.add_src_stage_2 <= "00"; -- select zero as second operand
+				-- set the following flags
+				alu_ctrl.ccr_flags_ctrl(C_FLAG) <= MODIFY;
+				alu_ctrl.ccr_flags_ctrl(V_FLAG) <= CLEAR;
+				alu_ctrl.ccr_flags_ctrl(Z_FLAG) <= MODIFY;
+				alu_ctrl.ccr_flags_ctrl(N_FLAG) <= MODIFY;
+			end if;
+			-- ROR
+			if instr_word_var(7 downto 4) = "0010" and instr_word_var(2 downto 0) = "111" then
+				alu_ctrl.word_24_update <= '1';
+				alu_ctrl.rotate <= '1';
+				-- Read accu
+				alu_ctrl.shift_mode <= SHIFT_RIGHT;
+				alu_ctrl.shift_src  <= instr_word_var(3); -- accumulate to the same register we want to write to
+				alu_ctrl.shift_src_sign <= "00";          -- with normal sign
+				alu_ctrl.store_result    <= '1';  -- store the result
+				alu_ctrl.rounding_used   <= "00"; -- no rounding needed
+				alu_ctrl.add_src_stage_2 <= "00"; -- select zero as second operand
+				-- set the following flags
+				alu_ctrl.ccr_flags_ctrl(C_FLAG) <= MODIFY;
+				alu_ctrl.ccr_flags_ctrl(V_FLAG) <= CLEAR;
+				alu_ctrl.ccr_flags_ctrl(Z_FLAG) <= MODIFY;
+				alu_ctrl.ccr_flags_ctrl(N_FLAG) <= MODIFY;
+			end if;
+			-- SBC
+			if instr_word_var(7 downto 5) = "001" and instr_word_var(2 downto 0) = "101" then
+				-- Read accu
+				alu_ctrl.shift_mode <= NO_SHIFT;
+				alu_ctrl.shift_src  <= instr_word_var(3); -- accumulate to the same register we want to write to
+				alu_ctrl.shift_src_sign <= "00";          -- with normal sign
+				-- Read S
+				alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 4); -- source register (JJJ encoding) X,Y
+				alu_ctrl.add_src_stage_2 <= "01"; -- select the register source
+				alu_ctrl.add_src_sign    <= "01"; -- with negative sign
+				alu_ctrl.rounding_used   <= "11"; -- subtract carry
+				alu_ctrl.store_result    <= '1';  -- store the result
+				-- set all flags!
+				for i in 0 to 7 loop
+					alu_ctrl.ccr_flags_ctrl(i) <= MODIFY;
+				end loop;
+			end if;
+			-- SUB
+			if instr_word_var(7) = '0' and instr_word_var(2 downto 0) = "100" then
+				-- Read accu
+				alu_ctrl.shift_mode <= NO_SHIFT;
+				alu_ctrl.shift_src  <= instr_word_var(3); -- accumulate to the same register we want to write to
+				alu_ctrl.shift_src_sign <= "00";          -- with normal sign
+				-- Read S
+				alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 4); -- source register (JJJ encoding)
+				alu_ctrl.add_src_stage_2 <= "01"; -- select the register source
+				alu_ctrl.add_src_sign    <= "01"; -- with negative sign
+				alu_ctrl.rounding_used   <= "00"; -- no rounding needed
+				alu_ctrl.store_result    <= '1';  -- store the result
+				-- set all flags!
+				for i in 0 to 7 loop
+					alu_ctrl.ccr_flags_ctrl(i) <= MODIFY;
+				end loop;
+			end if;
+			-- SUBL
+			if instr_word_var(7 downto 4) = "0001" and instr_word_var(2 downto 0) = "110" then
+				-- Read accu
+				alu_ctrl.shift_mode <= SHIFT_LEFT;
+				alu_ctrl.shift_src  <= instr_word_var(3); -- accumulate to the same register we want to write to
+				alu_ctrl.shift_src_sign <= "00";          -- with normal sign
+				-- Read S
+				alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 4); -- source register (JJJ encoding)
+				alu_ctrl.add_src_stage_2 <= "01"; -- select the register source
+				alu_ctrl.add_src_sign    <= "01"; -- with negative sign
+				alu_ctrl.rounding_used   <= "00"; -- no rounding needed
+				alu_ctrl.store_result    <= '1';  -- store the result
+				-- set all flags!
+				for i in 0 to 7 loop
+					alu_ctrl.ccr_flags_ctrl(i) <= MODIFY;
+				end loop;
+			end if;
+			-- SUBR
+			if instr_word_var(7 downto 4) = "0000" and instr_word_var(2 downto 0) = "110" then
+				-- Read accu
+				alu_ctrl.shift_mode <= SHIFT_RIGHT;
+				alu_ctrl.shift_src  <= instr_word_var(3); -- accumulate to the same register we want to write to
+				alu_ctrl.shift_src_sign <= "00";          -- with normal sign
+				-- Read S
+				alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 5) & '1'; -- source register (JJJ encoding)
+				alu_ctrl.add_src_stage_2 <= "01"; -- select the register source
+				alu_ctrl.add_src_sign    <= "01"; -- with negative sign
+				alu_ctrl.rounding_used   <= "00"; -- no rounding needed
+				alu_ctrl.store_result    <= '1';  -- store the result
+				-- set all flags!
+				for i in 0 to 7 loop
+					alu_ctrl.ccr_flags_ctrl(i) <= MODIFY;
+				end loop;
+			end if;
+			-- TFR 
+			if instr_word_var(7) = '0' and instr_word_var(6 downto 5) /= "01" and 
+			   instr_word_var(6 downto 4) /= "001" and instr_word_var(2 downto 0) = "001" then
+				-- do not read accu
+				alu_ctrl.shift_mode <= ZEROS;
+				-- Read S
+				if instr_word_var(6) = '1' then
+					alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 4); -- source register (JJJ encoding)
+				else
+					alu_ctrl.add_src_stage_1 <= "001"; -- B,A or A,B (depending on dest. accu)
+				end if;
+				alu_ctrl.add_src_stage_2 <= "01"; -- select the register source
+				alu_ctrl.add_src_sign    <= "00"; -- with positive sign
+				alu_ctrl.rounding_used   <= "00"; -- no rounding needed
+				alu_ctrl.store_result    <= '1';  -- store the result
+				-- do not set any flag at all!
+			end if;
+			-- TST
+			if instr_word_var(7 downto 4) = "0000" and instr_word_var(2 downto 0) = "011" then
+				-- do not read accu
+				alu_ctrl.shift_mode <= NO_SHIFT;          -- no shift
+				alu_ctrl.shift_src  <= instr_word_var(3); -- read source accu
+				alu_ctrl.shift_src_sign  <= "00";         -- sign unchanged
+				-- Read S
+				alu_ctrl.add_src_stage_2 <= "00"; -- select zero
+				alu_ctrl.add_src_sign    <= "00"; -- with positive sign
+				alu_ctrl.rounding_used   <= "00"; -- no rounding needed
+				alu_ctrl.store_result    <= '0';  -- do not store the result
+				-- set all flags but carry!
+				for i in 1 to 7 loop
+					alu_ctrl.ccr_flags_ctrl(i) <= MODIFY;
+				end loop;
+			end if;
+		end if; -- Parallel move ALU instructions
+
+		-- Tcc
+		if alu_tcc_decoded = '1' then
+			-- Read source
+			if instr_word_var(6) = '1' then
+				alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 4); -- source register (JJJ encoding)
+			else
+				alu_ctrl.add_src_stage_1 <= "001"; -- B,A or A,B (depending on dest. accu)
+			end if;
+			alu_ctrl.add_src_stage_2 <= "01"; -- select the registers as source
+			-- The .store_result flag is generated in the execute stage
+			-- depending on the condition codes
+			-- do not set any flag at all!
+		end if;
+--mul_op1 : std_logic_vector(1 downto 0); -- x0,x1,y0,y1
+--mul_op2 : std_logic_vector(1 downto 0); -- x0,x1,y0,y1
+--shift_src  : std_logic; -- a,b
+--shift_src_sign : std_logic_vector(1 downto 0); -- 00: pos, 01: neg, 10: sign dependant, 11: reserved
+--shift_mode : alu_shift_mode;
+--add_src_stage_1  : std_logic_vector(2 downto 0); -- x0,x1,y0,y1,x,y,a,b
+--add_src_stage_2  : std_logic_vector(1 downto 0); -- 00: 0 , 01: add_src_1, 10: mul_result, 11: reserved
+--add_src_sign   : std_logic_vector(1 downto 0); -- 00: pos, 01: neg, 10: sign dependant, 11: div instruction!
+--logic_function : std_logic_vector(2 downto 0);  -- 000: none, 110: and, 010: or, 011: eor, 111: not
+--word_24_update : std_logic;  -- only accumulator bits 47 downto 24 affected?
+--rounding_used  : std_logic_vector(1 downto 0); -- 00: no rounding, 01: rounding, 10: add carry, 11: subtract carry
+--store_result   : std_logic; -- 0: do not update accumulator, 1: update accumulator
+--dst_accu       : std_logic; -- 0: a, 1: b
+		-- DIV
+		if alu_div_decoded = '1' then
+			alu_ctrl.store_result    <= '1';          -- do store the result
+			-- shifter operation
+			alu_ctrl.shift_mode <= SHIFT_LEFT;        -- shift left
+			alu_ctrl.shift_src  <= instr_word_var(3); -- read source accu
+			alu_ctrl.div_instr  <= '1';               -- this is THE div instruction, special handling needed
+			-- source operand loading
+			alu_ctrl.add_src_stage_1 <= instr_word_var(6 downto 4); -- source register (JJJ encoding)
+			alu_ctrl.add_src_stage_2 <= "01"; -- select the registers as source
+			alu_ctrl.add_src_sign    <= "11"; -- div instruction, sign dependant on D[55] XOR S[23] 
+			                                  -- if 1: positive, if 0: negative
+			alu_ctrl.ccr_flags_ctrl(C_FLAG) <= MODIFY;
+			alu_ctrl.ccr_flags_ctrl(V_FLAG) <= MODIFY;
+			alu_ctrl.ccr_flags_ctrl(L_FLAG) <= MODIFY;
+		end if;
+		-- NORM
+		if alu_norm_decoded = '1' then
+			-- set all alu-ctrl signals to ASL/ASR already here
+			-- depending on the condition code registers the flags
+			-- will be completed in the execute stage
+			alu_ctrl.norm_instr <= '1';
+			-- Read accu
+			--alu_ctrl.shift_mode <= SHIFT_RIGHT/SHIFT_LEFT/NO_SHIFT;
+			alu_ctrl.shift_src  <= instr_word_var(3); -- accumulate to the same register we want to write to
+			alu_ctrl.shift_src_sign <= "00";          -- with the original sign
+			-- Read S
+			alu_ctrl.add_src_stage_2 <= "00"; -- select zero as operand
+			alu_ctrl.add_src_sign    <= "00"; -- with original sign
+			alu_ctrl.store_result    <= '1';  -- store the result
+			alu_ctrl.rounding_used   <= "00"; -- no rounding needed
+			-- set all flags, V-flag will be cleared due to shifting
+			for i in 0 to 7 loop
+				alu_ctrl.ccr_flags_ctrl(i) <= MODIFY;
+			end loop;
+
+		end if;
+	end process;
+
+
+	instruction_decoder: process(instr_word, activate_dec) is
+		variable instr_word_var : std_logic_vector(23 downto 0);
+		procedure activate_AGU is
+		begin
+			-- check for immediate long addressing
+			if instr_word_var(13 downto 8) = "110100" then
+				act_array(ACT_IMM_LONG) <= '1';
+				act_array(ACT_X_MEM_RD) <= '0'; -- No memory accesses for Immediate addressing!
+				act_array(ACT_Y_MEM_RD) <= '0';
+				act_array(ACT_X_MEM_WR) <= '0';
+				act_array(ACT_Y_MEM_WR) <= '0';
+			else
+				act_array(ACT_ADGEN) <= '1';
+			end if;
+		end procedure activate_AGU;
+	begin
+		instr_array_int <= INSTR_NOP;
+		act_array   <= (others => '0');
+		adgen_bittype <= NOP;
+		reg_rd_addr <= (others => '0');
+		reg_wr_addr <= (others => '0');
+		x_bus_rd_addr <= (others => '0');
+		x_bus_wr_addr <= (others => '0');
+		y_bus_rd_addr <= (others => '0');
+		y_bus_wr_addr <= (others => '0');
+		l_bus_addr <= instr_word_var(19) & instr_word_var(17 downto 16);
+
+		alu_tcc_decoded <= '0';
+		alu_div_decoded <= '0';
+		alu_norm_decoded <= '0';
+
+		-- in case the decoding is not activated we insert a nop
+		if activate_dec = '1' then
+			instr_word_var := instr_word;
+		else
+			instr_word_var := (others => '0');
+		end if;
+
+		if instr_word_var(23 downto 16) = X"00" then
+			case instr_word_var(15 downto 0) is
+				when X"0000" => instr_array_int <= INSTR_NOP;
+				when X"0004" => instr_array_int <= INSTR_RTI; act_array(ACT_EXEC_BRA) <= '1';
+				when X"0005" => instr_array_int <= INSTR_ILLEGAL;
+				when X"0006" => instr_array_int <= INSTR_SWI;
+				when X"000C" => instr_array_int <= INSTR_RTS; act_array(ACT_EXEC_BRA) <= '1';
+				when X"0084" => instr_array_int <= INSTR_RESET;
+				when X"0086" => instr_array_int <= INSTR_WAIT;
+				when X"0087" => instr_array_int <= INSTR_STOP;
+				when X"008C" => instr_array_int <= INSTR_ENDDO;
+				                act_array(ACT_EXEC_LOOP) <= '1';
+				when others =>
+					act_array(ACT_EXEC_CR_MOD) <= '1'; -- modify control register
+					if instr_word_var(7 downto 2) = "101110" then
+						instr_array_int <= INSTR_ANDI;
+					elsif instr_word_var(7 downto 2) = "111110" then
+						instr_array_int <= INSTR_ORI;
+					end if;
+			end case;
+		end if;
+		---------------------------------------------------------
+		-- DIV and NORM
+		---------------------------------------------------------
+		if instr_word_var(23 downto 16) = X"01" then
+			-- DIV
+			if instr_word_var(15 downto 6) = "1000000001" and instr_word_var(2 downto 0) = "000" then
+				alu_div_decoded <= '1';
+				act_array(ACT_ALU) <= '1'; -- force ALU to update status register
+			end if;
+			-- NORM
+			if instr_word_var(15 downto 11) = "11011" and instr_word_var(7 downto 4) = "0001" and
+		   	   instr_word_var(2 downto 0) = "101" then
+				alu_norm_decoded <= '1';
+				act_array(ACT_NORM) <= '1'; -- NORM instruction decoded,
+				                            -- special handling in exec-stage is caused
+				act_array(ACT_REG_RD) <= '1';
+				reg_rd_addr <= instr_word_var(13 downto 12) & '0' & instr_word_var(10 downto 8); -- Write same Rn
+				act_array(ACT_REG_WR) <= '1';
+				reg_wr_addr <= instr_word_var(13 downto 12) & '0' & instr_word_var(10 downto 8); -- Write same Rn
+			end if;
+		end if;
+		---------------------------------------------------------
+		-- Tcc
+		---------------------------------------------------------
+		if instr_word_var(23 downto 16) = X"02" or instr_word_var(23 downto 16) = X"03" then
+			-- Tcc S1, D1  S2, D2 (ALU/Reg file)
+			if instr_word_var(16) = '0' and instr_word_var(11 downto 7) = "00000" and
+		       instr_word_var(2 downto 0) = "000" then
+				act_array(ACT_ALU_WR_CC) <= '1';
+				alu_tcc_decoded <= '1';
+			-- Tcc S1, D1  S2, D2 (ALU/Reg file)
+			elsif instr_word_var(16) = '1' and instr_word_var(11) = '0' and 
+		   	      instr_word_var(7) = '0' then
+				act_array(ACT_ALU_WR_CC) <= '1';
+				alu_tcc_decoded <= '1';
+				act_array(ACT_REG_WR_CC) <= '1';
+				reg_rd_addr <= "010" & instr_word_var(10 downto 8); -- Read Rn
+				reg_wr_addr <= "010" & instr_word_var( 2 downto 0); -- Write to other Rn
+			end if;
+		end if;
+		---------------------------------------------------------
+		-- MOVEC and LUA instruction with registers
+		---------------------------------------------------------
+		if instr_word_var(23 downto 16) = X"04" then
+			act_array(ACT_REG_WR) <= '1';
+			-- LUA instruction
+			if instr_word_var(15 downto 13) = "010" and instr_word_var(7 downto 4) = "0001" then
+				instr_array_int <= INSTR_LUA;
+				act_array(ACT_ADGEN) <= '1';
+				adgen_bittype <= SINGLE_X_SHORT;
+				reg_wr_addr <= instr_word_var(5 downto 0);
+			end if;
+			-- MOVEC instruction (S1, D2) or (S2, D1)
+			if instr_word_var(14) = '1' and instr_word_var(7 downto 5) = "101" then
+				instr_array_int <= INSTR_MOVEC;
+				act_array(ACT_REG_RD) <= '1';
+				-- Write D1
+				if instr_word_var(15) = '1' then
+					reg_wr_addr <= instr_word_var(5 downto 0);
+					reg_rd_addr <= instr_word_var(13 downto 8);
+				-- Read S1
+				else
+					reg_wr_addr <= instr_word_var(13 downto 8);
+					reg_rd_addr <= instr_word_var(5 downto 0);
+				end if;
+			end if;
+		end if;
+		-------------------------------------------------------------------------
+		-- MOVEC instruction with memory access/absolute address
+		-------------------------------------------------------------------------
+		if instr_word_var(23 downto 16) = X"05" and 
+		   instr_word_var(7) = '0' and instr_word_var(5) = '1' then
+			
+			instr_array_int <= INSTR_MOVEC;
+			-- read from memory, write to register
+			if instr_word_var(15) = '1' then
+				act_array(ACT_REG_WR) <= '1';
+				reg_wr_addr <= instr_word_var(5 downto 0);
+				-- X Memory read?
+				if instr_word_var(6) = '0' then
+					act_array(ACT_X_MEM_RD) <= '1';
+				-- Y Memory read?
+				else
+					act_array(ACT_Y_MEM_RD) <= '1';
+				end if;
+			-- write to memory, read register
+			else
+				act_array(ACT_REG_RD) <= '1';
+				reg_rd_addr <= instr_word_var(5 downto 0);
+				-- X Memory write?
+				if instr_word_var(6) = '0' then
+					act_array(ACT_X_MEM_WR) <= '1';
+				-- Y Memory write?
+				else
+					act_array(ACT_Y_MEM_WR) <= '1';
+				end if;
+			end if;
+			-- AGU needed?
+			if instr_word_var(14) = '1' then
+				-- detect whether two word instruction!
+				adgen_bittype <= SINGLE_X;
+				-- check for immediate long addressing
+				if instr_word_var(13 downto 8) = "110100" then
+					act_array(ACT_IMM_LONG) <= '1';
+					act_array(ACT_X_MEM_RD) <= '0'; -- No memory accesses for Immediate addressing!
+					act_array(ACT_Y_MEM_RD) <= '0';
+					act_array(ACT_X_MEM_WR) <= '0';
+					act_array(ACT_Y_MEM_WR) <= '0';
+				else
+					act_array(ACT_ADGEN) <= '1';
+				end if;
+			else
+				-- X:/Y:aa short is done in the adgen-stage automatically
+			end if;
+		end if;
+		-------------------------------------------------------------------------
+		-- MOVEC instruction with immediate
+		-------------------------------------------------------------------------
+		if instr_word_var(23 downto 16) = X"05" and instr_word_var(7 downto 5) = "101" then
+			instr_array_int <= INSTR_MOVEC;
+			act_array(ACT_IMM_8BIT) <= '1';
+			act_array(ACT_REG_WR) <= '1';
+			reg_wr_addr <= instr_word_var(5 downto 0);
+		end if;
+		---------------------------------
+		-- REP or DO loop?
+		---------------------------------
+		if instr_word_var(23 downto 16) = X"06" then
+			-- Instruction encoding is the same for both except of this bit
+			if instr_word_var(5) = '1' then
+				instr_array_int <= INSTR_REP;
+			else
+				instr_array_int <= INSTR_DO;
+			end if;
+			act_array(ACT_EXEC_LOOP) <= '1';
+			-- Init reading of loop counter from memory
+			if instr_word_var(15) = '0' and instr_word_var(7) = '0' then
+				-- X/Y: ea?
+				if instr_word_var(14) = '1' then
+					act_array(ACT_ADGEN) <= '1';
+				end if;
+				-- X/Y: aa?
+				-- Done automatically in the ADGEN stage by testing whether the ADGEN unit activated or not!
+				-- If not the absolute address stored in the instruction word is used.
+				-------
+				-- only a single memory access is required
+				adgen_bittype <= SINGLE_X;
+				-- X/Y as source?
+				if instr_word_var(6) = '0' then
+					act_array(ACT_X_MEM_RD) <= '1';
+				else 
+					act_array(ACT_Y_MEM_RD) <= '1';
+				end if;
+			elsif instr_word_var(15) = '1' and instr_word_var(7) = '0' then
+				-- S (register as source)
+				reg_rd_addr <= instr_word_var(13 downto 8);
+				act_array(ACT_REG_RD) <= '1';
+				-- #xxx ,12 bit immediate
+			elsif instr_word_var(7 downto 6) = "10" and instr_word_var(4) = '0' then
+				act_array(ACT_IMM_12BIT) <= '1';
+			end if;
+		end if;
+		--------------------------------
+		-- MOVEM (Program memory move)
+		--------------------------------
+		if instr_word_var(23 downto 16) = X"07" then
+			-- read memory, write reg
+			if instr_word_var(15) = '1' then
+				act_array(ACT_REG_WR) <= '1';
+				reg_wr_addr <= instr_word_var(5 downto 0);
+				act_array(ACT_P_MEM_RD) <= '1';
+			-- read reg, write memory
+			elsif instr_word_var(15) = '0' then
+				act_array(ACT_REG_RD) <= '1';
+				reg_rd_addr <= instr_word_var(5 downto 0);
+				act_array(ACT_P_MEM_WR) <= '1';
+			end if;
+			-- AGU needed?
+			if instr_word_var(14) = '1' and instr_word_var(7 downto 6) = "10" then
+				adgen_bittype <= SINGLE_X;
+				-- activate AGU and test whether immediate data is used
+				activate_AGU;
+			elsif instr_word_var(14) = '0' and instr_word_var(7 downto 6) = "00" then
+				-- X:/Y:aa short is done in the adgen-stage automatically
+			end if;
+		end if;
+		--------------------------------
+		-- MOVEP (Peripheral memory move)
+		--------------------------------
+		if instr_word_var(23 downto 16) = "0000100-" then
+			-- TODO?? Why parallel moves in software model??
+			case instr_word_var(15 downto 0) is
+--				when "-1------1-------" => instr_array_int(INSTR_MOVEP) <= '1';
+--				when "-1------01------" => instr_array_int(INSTR_MOVEP) <= '1';
+--				when "-1------00------" => instr_array_int(INSTR_MOVEP) <= '1';
+				when others =>
+			end case;
+		end if;
+		-- BSET, BCLR, BCHG, BTST, JCLR, JSET, JSCLR, JSSET, JMP, JCC, JSCC, JSR
+		if instr_word_var(23 downto 16) = X"0A" or instr_word_var(23 downto 16) = X"0B" then
+
+			reg_rd_addr <= instr_word_var(13 downto 8);
+			reg_wr_addr <= instr_word_var(13 downto 8);
+
+			if instr_word_var(16) = '0' then
+				if instr_word_var(7) = '0' and instr_word_var(5) = '0' then
+					instr_array_int <= INSTR_BCLR;
+				elsif instr_word_var(7) = '0' and instr_word_var(5) = '1' then
+					instr_array_int <= INSTR_BSET;
+				elsif instr_word_var(7) = '1' and instr_word_var(5) = '0' then
+					instr_array_int <= INSTR_JCLR;
+				elsif instr_word_var(7) = '1' and instr_word_var(5) = '1' then
+					instr_array_int <= INSTR_JSET;
+				end if;
+			elsif instr_word_var(16) = '1' then
+				if instr_word_var(7) = '0' and instr_word_var(5) = '0' then
+					instr_array_int <= INSTR_BCHG;
+				elsif instr_word_var(7) = '0' and instr_word_var(5) = '1' then
+					instr_array_int <= INSTR_BTST;
+				elsif instr_word_var(7) = '1' and instr_word_var(5) = '0' then
+					instr_array_int <= INSTR_JSCLR;
+				elsif instr_word_var(7) = '1' and instr_word_var(5) = '1' then
+					instr_array_int <= INSTR_JSSET;
+				end if;
+			end if;
+			if instr_word_var(7) = '1' then
+				act_array(ACT_EXEC_BRA) <= '1';
+			end if;
+
+			-- memory access?
+			if instr_word_var(15) = '0' then
+				-- X:
+				if instr_word_var(6) = '0' then
+					act_array(ACT_X_MEM_RD) <= '1';
+					-- if not a jump instruction and not BTST write back the result
+					if instr_word_var(7) = '0' and not(instr_word_var(16) = '1' and instr_word_var(5) = '1') then
+						act_array(ACT_X_MEM_WR) <= '1';
+					end if;
+				-- Y:
+				else
+					act_array(ACT_Y_MEM_RD) <= '1';
+					-- if not a jump instruction and not BTST write back the result
+					if instr_word_var(7) = '0' and not(instr_word_var(16) = '1' and instr_word_var(5) = '1') then
+						act_array(ACT_Y_MEM_WR) <= '1';
+					end if;
+				end if;
+			end if;
+
+			case instr_word_var(15 downto 14) is
+				-- X:/Y: aa
+				when "00" =>
+
+				-- X:/Y: ea
+				when "01" =>
+					act_array(ACT_ADGEN) <= '1';
+					adgen_bittype <= SINGLE_X;
+
+				-- X:/Y: pp 
+				-- TODO!
+				when "10" =>
+
+				when others => -- "11"
+					if instr_word_var(7 downto 0) = "10000000" then
+						-- JMP/JSR ea
+						act_array(ACT_EXEC_BRA) <= '1';
+						act_array(ACT_ADGEN) <= '1';
+						adgen_bittype <= SINGLE_X;
+						if instr_word_var(16) = '0' then
+							instr_array_int <= INSTR_JMP;
+						elsif instr_word_var(16) = '1' then
+							instr_array_int <= INSTR_JSR;
+						end if;
+					elsif instr_word_var(7 downto 4) = "1010" then
+						-- JCC/JSCC ea
+						act_array(ACT_EXEC_BRA) <= '1';
+						act_array(ACT_ADGEN) <= '1';
+						adgen_bittype <= SINGLE_X;
+						if instr_word_var(16) = '0' then
+							instr_array_int <= INSTR_JCC;
+						elsif instr_word_var(16) = '1' then
+							instr_array_int <= INSTR_JSCC;
+						end if;
+					-- JSCLR,JSET,JCLR,JSSET,BTST,BCLR,BSET,BCHG S/D
+					else
+						act_array(ACT_REG_RD) <= '1';
+						-- if not a jump instruction and not BTST write back the result
+						if instr_word_var(7) = '0' and not(instr_word_var(16) = '1' and instr_word_var(5) = '1') then
+							act_array(ACT_REG_WR) <= '1';
+						end if;
+					end if;
+			end case;
+		end if;
+		-- JMP xxx (absoulute short)
+		if instr_word_var(23 downto 16) = X"0C" then
+			if instr_word_var(15 downto 12) = "0000" then
+				instr_array_int <= INSTR_JMP;
+				act_array(ACT_EXEC_BRA) <= '1';
+			end if;
+		end if;
+		-- JSR xxx (absolute short)
+		if instr_word_var(23 downto 16) = X"0D" then
+			if instr_word_var(15 downto 12) = "0000" then
+				instr_array_int <= INSTR_JSR;
+				act_array(ACT_EXEC_BRA) <= '1';
+			end if;
+		end if;
+		-- JCC xxx (absolute short)
+		if instr_word_var(23 downto 16) = X"0E" then
+			instr_array_int <= INSTR_JCC;
+			act_array(ACT_EXEC_BRA) <= '1';
+		end if;
+		-- JSCC xxx (absolute short)
+		if instr_word_var(23 downto 16) = X"0F" then
+			instr_array_int <= INSTR_JSCC;
+			act_array(ACT_EXEC_BRA) <= '1';
+		end if;
+
+		------------------------------------------------
+		-- PARALLEL MOVE SECTION!!
+		------------------------------------------------
+		-- Here are the ALU operations that allow for parallel moves
+		if instr_word_var(23 downto 20) /= "0000" then
+			act_array(ACT_ALU) <= '1'; -- force ALU to update status register
+		end if;
+		-- PM: I
+		if instr_word_var(23 downto 21) = "001" and instr_word_var(20 downto 18) /= "000" then
+			act_array(ACT_IMM_8BIT) <= '1';
+			act_array(ACT_REG_WR) <= '1';
+			reg_wr_addr <= '0' & instr_word_var(20 downto 16);
+		end if;
+		-- PM: R
+		if instr_word_var(23 downto 18) = "001000" then
+			act_array(ACT_REG_WR) <= '1';
+			reg_wr_addr <= '0' & instr_word_var(12 downto  8);
+			act_array(ACT_REG_RD) <= '1';
+			reg_rd_addr <= '0' & instr_word_var(17 downto 13);
+		end if;
+		-- PM: U
+		if instr_word_var(23 downto 13) = "00100000010" then
+			act_array(ACT_ADGEN) <= '1';
+			adgen_bittype <= SINGLE_X_SHORT;
+		end if;
+		-- PM: X or PM:Y
+		if instr_word_var(23 downto 22) = "01" and 
+		   -- Check whether L: type parallel move. If so do not enter this branch!
+		   not (instr_word_var(21 downto 20) = "00" and instr_word_var(18) = '0') then
+			-- read memory, write reg
+			if instr_word_var(15) = '1' then
+				act_array(ACT_REG_WR) <= '1';
+				reg_wr_addr <= '0' & instr_word_var(21 downto 20) & instr_word_var(18 downto 16); -- TODO: CHECK!!
+				-- X Memory read?
+				if instr_word_var(19) = '0' then
+					act_array(ACT_X_MEM_RD) <= '1';
+				-- Y Memory read?
+				else
+					act_array(ACT_Y_MEM_RD) <= '1';
+				end if;
+			-- read reg, write memory
+			elsif instr_word_var(15) = '0' then
+				act_array(ACT_REG_RD) <= '1';
+				reg_rd_addr <= '0' & instr_word_var(21 downto 20) & instr_word_var(18 downto 16); -- TODO: CHECK!!
+				-- X Memory write?
+				if instr_word_var(19) = '0' then
+					act_array(ACT_X_MEM_WR) <= '1';
+				-- Y Memory write?
+				else
+					act_array(ACT_Y_MEM_WR) <= '1';
+				end if;
+			end if;
+			-- AGU needed?
+			if instr_word_var(14) = '1' then
+				-- detect whether two word instruction!
+				adgen_bittype <= SINGLE_X;
+				-- activate AGU and test whether immediate data is used
+				activate_AGU;
+			else
+				-- X:/Y:aa short is done in the adgen-stage automatically
+			end if;
+		end if;
+		-- PM: X:R or R:Y (Class I)
+		if instr_word_var(23 downto 20) = "0001" then
+			adgen_bittype <= SINGLE_X;
+			-- X:R
+			if instr_word_var(14) = '0' then
+				x_bus_rd_addr <= instr_word_var(19 downto 18);
+				x_bus_wr_addr <= instr_word_var(19 downto 18);
+				y_bus_rd_addr <= '1' & instr_word_var(17);
+				y_bus_wr_addr <= '0' & instr_word_var(16); -- TODO: Check encoding, manual uses three fs!
+				-- S2,D2 in any case!
+				act_array(ACT_Y_BUS_RD) <= '1';
+				act_array(ACT_Y_BUS_WR) <= '1';
+				-- Write D1?
+				if instr_word_var(15) = '1' then
+					act_array(ACT_X_MEM_RD) <= '1';
+					act_array(ACT_X_BUS_WR) <= '1';
+				else
+				-- Read S1?
+					act_array(ACT_X_MEM_WR) <= '1';
+					act_array(ACT_X_BUS_RD) <= '1';
+				end if;
+			-- R:Y
+			elsif instr_word_var(14) = '1' then
+				x_bus_rd_addr <= '1' & instr_word_var(19);
+				x_bus_wr_addr <= '0' & instr_word_var(18);
+				y_bus_rd_addr <= instr_word_var(17 downto 16);
+				y_bus_wr_addr <= instr_word_var(17 downto 16);
+				-- S1,D1 in any case!
+				act_array(ACT_X_BUS_RD) <= '1';
+				act_array(ACT_X_BUS_WR) <= '1';
+				-- Write D1?
+				if instr_word_var(15) = '1' then
+					act_array(ACT_Y_MEM_RD) <= '1';
+					act_array(ACT_Y_BUS_WR) <= '1';
+				else
+				-- Read S1?
+					act_array(ACT_Y_MEM_WR) <= '1';
+					act_array(ACT_Y_BUS_RD) <= '1';
+				end if;
+
+			end if;
+			-- detect whether two word instruction!
+			adgen_bittype <= SINGLE_X;
+			-- activate AGU and test whether immediate data is used
+			activate_AGU;
+		end if;
+		-- PM: X:R or R:Y (Class II)
+		if instr_word_var(23 downto 17) = "0000100" and instr_word_var(14) = '0' then
+			act_array(ACT_REG_RD) <= '1';
+			-- X:R
+			if instr_word_var(15) = '0' then
+				reg_rd_addr <= "00111" & instr_word_var(16); -- read A or B
+				act_array(ACT_X_MEM_WR) <= '1'; -- and store it in X memory
+				x_bus_rd_addr <= "00"; -- read x0
+				x_bus_wr_addr <= '1' & instr_word_var(16); -- and write to A or B
+				act_array(ACT_X_BUS_RD) <= '1';
+				act_array(ACT_X_BUS_WR) <= '1';
+			-- R:Y
+			elsif instr_word_var(15) = '1' then
+				reg_rd_addr <= "00111" & instr_word_var(16); -- read A or B
+				act_array(ACT_Y_MEM_WR) <= '1'; -- and store it in Y memory
+				y_bus_rd_addr <= "00"; -- read y0
+				y_bus_wr_addr <= '1' & instr_word_var(16); -- and write to A or B
+				act_array(ACT_Y_BUS_RD) <= '1';
+				act_array(ACT_Y_BUS_WR) <= '1';
+			end if;
+			-- detect whether two word instruction!
+			adgen_bittype <= SINGLE_X;
+			-- activate AGU and test whether immediate data is used
+			activate_AGU;
+		end if;
+		-- PM: L:
+		l_bus_addr <= instr_word_var(19) & instr_word_var(17 downto 16);
+		if instr_word_var(23 downto 20) = "0100" and instr_word_var(18) = '0' then
+			-- Read S?
+			if instr_word_var(15) = '0' then
+				act_array(ACT_L_BUS_RD) <= '1';
+				act_array(ACT_X_MEM_WR) <= '1';
+				act_array(ACT_Y_MEM_WR) <= '1';
+			else -- Write D
+				act_array(ACT_L_BUS_WR) <= '1';
+				act_array(ACT_X_MEM_RD) <= '1';
+				act_array(ACT_Y_MEM_RD) <= '1';
+			end if;
+			if instr_word_var(14) = '1' then
+				adgen_bittype <= SINGLE_X;
+				activate_AGU;
+			else
+				-- L:aa automatically performed in ADGEN stage
+			end if;
+		end if;
+		-- PM: X: Y:
+		if instr_word_var(23) = '1' then
+			adgen_bittype <= DOUBLE_X_Y;
+			-- No immediate value allowed, so activate in any case!
+			act_array(ACT_ADGEN) <= '1';
+			-- S1, X:
+			if instr_word_var(15) = '0' then
+				act_array(ACT_X_BUS_RD) <= '1';
+				x_bus_rd_addr <= instr_word_var(19 downto 18);
+				act_array(ACT_X_MEM_WR) <= '1'; 
+			-- X:, D1
+			else
+				act_array(ACT_X_BUS_WR) <= '1';
+				x_bus_wr_addr <= instr_word_var(19 downto 18);
+				act_array(ACT_X_MEM_RD) <= '1'; 
+			end if;
+			-- S2, Y:
+			if instr_word_var(22) = '0' then
+				act_array(ACT_Y_BUS_RD) <= '1';
+				y_bus_rd_addr <= instr_word_var(17 downto 16);
+				act_array(ACT_Y_MEM_WR) <= '1'; 
+			-- Y:, D2
+			else
+				act_array(ACT_Y_BUS_WR) <= '1';
+				y_bus_wr_addr <= instr_word_var(17 downto 16);
+				act_array(ACT_Y_MEM_RD) <= '1'; 
+			end if;
+		end if;
+	end process;
+
+	adgen_decoder: process(adgen_bittype, instr_word) is
+	begin
+		adgen_mode_a <= NOP;
+		adgen_mode_b <= NOP;
+		ea_extension_available <= '0';
+
+		case adgen_bittype is
+			when SINGLE_X =>
+				case instr_word(13 downto 11) is
+					when "000" => adgen_mode_a <= POST_MIN_N;
+					when "001" => adgen_mode_a <= POST_PLUS_N;
+					when "010" => adgen_mode_a <= POST_MIN_1;
+					when "011" => adgen_mode_a <= POST_PLUS_1;
+					when "100" => adgen_mode_a <= NOP;
+					when "101" => adgen_mode_a <= INDEXED_N;
+					when "111" => adgen_mode_a <= PRE_MIN_1;
+					when "110" =>
+						if instr_word(10 downto 8) = "000" then
+							adgen_mode_a <= ABSOLUTE;
+							ea_extension_available <= '1';
+						elsif instr_word(10 downto 8) = "100" then
+							adgen_mode_a <= IMMEDIATE;
+							ea_extension_available <= '1';
+						else 
+							adgen_mode_a <= NOP; -- INVALID OPCODE!
+						end if;
+					when others =>
+				end case;
+			when SINGLE_X_SHORT =>
+				case instr_word(12 downto 11) is
+					when "00" => adgen_mode_a <= POST_MIN_N;
+					when "01" => adgen_mode_a <= POST_PLUS_N;
+					when "10" => adgen_mode_a <= POST_MIN_1;
+					when "11" => adgen_mode_a <= POST_PLUS_1;
+					when others => 
+				end case;
+			when DOUBLE_X_Y =>
+				case instr_word(12 downto 11) is
+					when "00" => adgen_mode_a <= NOP;
+					when "01" => adgen_mode_a <= POST_PLUS_N;
+					when "10" => adgen_mode_a <= POST_MIN_1;
+					when "11" => adgen_mode_a <= POST_PLUS_1;
+					when others =>
+				end case;
+				case instr_word(21 downto 20) is
+					when "00" => adgen_mode_b <= NOP;
+					when "01" => adgen_mode_b <= POST_PLUS_N;
+					when "10" => adgen_mode_b <= POST_MIN_1;
+					when "11" => adgen_mode_b <= POST_PLUS_1;
+					when others =>
+				end case;
+			when others =>
+		end case;
+	end process adgen_decoder;
+
+end architecture rtl;
+
diff --git a/FireBee/trunk/vhdl/dsp56k/src/dsp56k.vhd b/FireBee/trunk/vhdl/dsp56k/src/dsp56k.vhd
new file mode 100644
index 0000000..c8be35c
--- /dev/null
+++ b/FireBee/trunk/vhdl/dsp56k/src/dsp56k.vhd
@@ -0,0 +1,117 @@
+------------------------------------------------------------------------------
+--! @file
+--! @author Matthias Alles
+--! @date 01/2009
+--! @brief Top entity of DSP
+--!
+------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.parameter_pkg.all;
+use work.types_pkg.all;
+use work.constants_pkg.all;
+
+entity dsp56k is port (
+	clk, rst : in std_logic;
+	-- put register file here for synthesis!
+	register_file : out register_file_type
+--	port_a_in     : in  port_a_in_type;
+--	port_a_out    : out port_a_out_type;
+--	port_b_in     : in  port_b_in_type;
+--	port_b_out    : out port_b_out_type;
+--	port_c_in     : in  port_c_in_type;
+--	port_c_out    : out port_c_out_type;
+
+);
+end dsp56k;
+
+
+architecture rtl of dsp56k is
+
+	component pipeline is port (
+		clk, rst : in std_logic;
+		register_file_out : out register_file_type;
+		stall_flags_out   : out std_logic_vector(PIPELINE_DEPTH-1 downto 0);
+		memory_stall   : in  std_logic;
+		data_rom_enable: out std_logic;
+		pmem_ctrl_in   : out mem_ctrl_type_in;
+		pmem_ctrl_out  : in  mem_ctrl_type_out;
+		pmem2_ctrl_in  : out mem_ctrl_type_in;
+		pmem2_ctrl_out : in  mem_ctrl_type_out;
+		xmem_ctrl_in   : out mem_ctrl_type_in;
+		xmem_ctrl_out  : in  mem_ctrl_type_out;
+		ymem_ctrl_in   : out mem_ctrl_type_in;
+		ymem_ctrl_out  : in  mem_ctrl_type_out
+	
+	);
+	end component pipeline;
+
+	component memory_management is port (
+		clk, rst : in std_logic;
+		stall_flags    : in  std_logic_vector(PIPELINE_DEPTH-1 downto 0);
+		memory_stall   : out std_logic;
+		data_rom_enable: in  std_logic;
+		pmem_ctrl_in   : in  mem_ctrl_type_in;
+		pmem_ctrl_out  : out mem_ctrl_type_out;
+		pmem2_ctrl_in  : in  mem_ctrl_type_in;
+		pmem2_ctrl_out : out mem_ctrl_type_out;
+		xmem_ctrl_in   : in  mem_ctrl_type_in;
+		xmem_ctrl_out  : out mem_ctrl_type_out;
+		ymem_ctrl_in   : in  mem_ctrl_type_in;
+		ymem_ctrl_out  : out mem_ctrl_type_out
+	);
+	end component memory_management;
+
+	signal stall_flags     : std_logic_vector(PIPELINE_DEPTH-1 downto 0);
+	signal memory_stall    : std_logic;
+	signal data_rom_enable : std_logic;
+	signal pmem_ctrl_in   : mem_ctrl_type_in;
+	signal pmem_ctrl_out  : mem_ctrl_type_out;
+	signal pmem2_ctrl_in  : mem_ctrl_type_in;
+	signal pmem2_ctrl_out : mem_ctrl_type_out;
+	signal xmem_ctrl_in   : mem_ctrl_type_in;
+	signal xmem_ctrl_out  : mem_ctrl_type_out;
+	signal ymem_ctrl_in   : mem_ctrl_type_in;
+	signal ymem_ctrl_out  : mem_ctrl_type_out;
+
+begin
+
+	pipeline_inst : pipeline port map(
+		clk => clk,
+		rst => rst,
+		register_file_out => register_file,
+		stall_flags_out   => stall_flags,
+		memory_stall  => memory_stall,
+		data_rom_enable => data_rom_enable,
+		pmem_ctrl_in   => pmem_ctrl_in,
+		pmem_ctrl_out  => pmem_ctrl_out,
+		pmem2_ctrl_in  => pmem2_ctrl_in,
+		pmem2_ctrl_out => pmem2_ctrl_out,
+		xmem_ctrl_in   => xmem_ctrl_in,
+		xmem_ctrl_out  => xmem_ctrl_out,
+		ymem_ctrl_in   => ymem_ctrl_in,
+		ymem_ctrl_out  => ymem_ctrl_out
+	);
+
+	---------------------
+	-- MEMORY MANAGEMENT
+	---------------------
+	MMU_inst: memory_management port map (
+		clk => clk,
+		rst => rst,
+		stall_flags   => stall_flags,
+		memory_stall  => memory_stall,
+		data_rom_enable => data_rom_enable,
+		pmem_ctrl_in   => pmem_ctrl_in,
+		pmem_ctrl_out  => pmem_ctrl_out,
+		pmem2_ctrl_in  => pmem2_ctrl_in,
+		pmem2_ctrl_out => pmem2_ctrl_out,
+		xmem_ctrl_in   => xmem_ctrl_in,
+		xmem_ctrl_out  => xmem_ctrl_out,
+		ymem_ctrl_in   => ymem_ctrl_in,
+		ymem_ctrl_out  => ymem_ctrl_out
+	);
+
+end architecture rtl;
diff --git a/FireBee/trunk/vhdl/dsp56k/src/exec_stage_alu.vhd b/FireBee/trunk/vhdl/dsp56k/src/exec_stage_alu.vhd
new file mode 100644
index 0000000..249be3c
--- /dev/null
+++ b/FireBee/trunk/vhdl/dsp56k/src/exec_stage_alu.vhd
@@ -0,0 +1,611 @@
+------------------------------------------------------------------------------
+--! @file
+--! @author Matthias Alles
+--! @date 01/2009
+--! @brief ALU, including shifter, MAC unit, etc.
+--!
+------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.parameter_pkg.all;
+use work.types_pkg.all;
+use work.constants_pkg.all;
+
+entity exec_stage_alu is port(
+	alu_activate      : in  std_logic;
+	instr_word        : in  std_logic_vector(23 downto 0);
+	alu_ctrl          : in  alu_ctrl_type;
+	register_file     : in  register_file_type;
+	addr_r_in         : in  unsigned(BW_ADDRESS-1 downto 0);
+	addr_r_out        : out unsigned(BW_ADDRESS-1 downto 0);
+	modify_accu       : out std_logic;
+	dst_accu          : out std_logic;
+	modified_accu     : out signed(55 downto 0);
+	modify_sr         : out std_logic;
+	modified_sr       : out std_logic_vector(15 downto 0)
+);
+end entity;
+
+architecture rtl of exec_stage_alu is 
+
+	signal alu_shifter_out          : signed(55 downto 0);
+	signal alu_shifter_carry_out    : std_logic;
+	signal alu_shifter_overflow_out : std_logic;
+
+	signal alu_logic_conj        : signed(55 downto 0);
+	signal alu_multiplier_out    : signed(55 downto 0);
+	signal alu_src_op            : signed(55 downto 0);
+	signal alu_add_result        : signed(56 downto 0);
+	signal alu_add_carry_out     : std_logic;
+	signal alu_post_adder_result : signed(56 downto 0);
+
+	signal scaling_mode          : std_logic_vector(1 downto 0);
+
+	signal modified_accu_int     : signed(55 downto 0);
+
+	signal norm_instr_asl  : std_logic;
+	signal norm_instr_asr  : std_logic;
+	signal norm_instr_nop  : std_logic;
+	signal norm_update_ccr : std_logic; 
+
+begin
+
+
+	-- store calculated value?
+	modify_accu <= alu_ctrl.store_result;
+	modified_accu <= modified_accu_int;
+	-- for the norm instruction we first need to determine whether we have to
+	-- update the CCR register or not
+	modify_sr <= alu_activate when alu_ctrl.norm_instr = '0' else
+	             norm_update_ccr;
+	dst_accu <= alu_ctrl.dst_accu;
+
+	scaling_mode <= register_file.sr(11 downto 10);
+
+
+	calcule_ccr_flags: process(register_file, alu_ctrl, alu_shifter_carry_out,
+	                           alu_post_adder_result, modified_accu_int, alu_add_carry_out) is
+	begin
+		-- by default do not modify the flags in the status register
+		modified_sr <= register_file.sr;
+		
+		-- Carry flag generation
+		-------------------------
+		case alu_ctrl.ccr_flags_ctrl(C_FLAG) is
+			when CLEAR  => modified_sr(C_FLAG) <= '0';
+			when SET    => modified_sr(C_FLAG) <= '1';
+			when MODIFY =>
+				-- the carry flag can stem from the shifter or from the post adder
+				-- in case we shift and add only a zero to the shift result (ASL, ASR, LSL, LSR, ROL, ROR)
+				-- take the carry flag from the shifter, else from the post adder
+				if (alu_ctrl.shift_mode = SHIFT_LEFT or alu_ctrl.shift_mode = SHIFT_RIGHT) and
+				    alu_ctrl.add_src_stage_2 = "00" then -- add zero after shifting?
+					modified_sr(C_FLAG) <= alu_shifter_carry_out;
+				elsif alu_ctrl.div_instr = '1' then
+					modified_sr(C_FLAG) <= not std_logic(alu_post_adder_result(55));
+				else
+--					modified_sr(C_FLAG) <= std_logic(alu_post_adder_result(57));
+					modified_sr(C_FLAG) <= alu_add_carry_out;
+				end if;
+			when others => -- Don't touch
+		end case;
+
+		-- Overflow flag generation
+		----------------------------
+		case alu_ctrl.ccr_flags_ctrl(V_FLAG) is
+			when CLEAR  => modified_sr(V_FLAG) <= '0';
+			when SET    => modified_sr(V_FLAG) <= '1';
+			when MODIFY =>
+				-- There are two sources for the overflow flag:
+				-- 1)
+				-- in case the result cannot be represented using 56 bits set
+				-- the overflow flag. this is the case when the two MSBs of 
+				-- the 57 bit result are different
+				-- 2)
+				-- The shifter circuit performs a 56 bit left shift. In case the 
+				-- two MSBs of the operand are different set the overflow flag as well
+				if (alu_ctrl.div_instr = '0' and alu_post_adder_result(56) /= alu_post_adder_result(55)) or
+				   (alu_ctrl.shift_mode = SHIFT_LEFT and alu_ctrl.word_24_update = '0' and 
+				    alu_shifter_overflow_out = '1' ) then
+					modified_sr(V_FLAG) <= '1';
+				else
+					modified_sr(V_FLAG) <= '0';
+				end if;
+			when others => -- Don't touch
+		end case;
+		
+		-- Zero flag generation
+		----------------------------
+		case alu_ctrl.ccr_flags_ctrl(Z_FLAG) is
+			when CLEAR  => modified_sr(Z_FLAG) <= '0';
+			when SET    => modified_sr(Z_FLAG) <= '1';
+			when MODIFY =>
+				-- in case the result is zero set this flag
+				-- distinguish between 24 bit and 56 bit ALU operations
+				-- 24 bit instructions are LSL, LSR, ROR, ROL, OR, EOR, NOT, AND
+				if (alu_ctrl.word_24_update = '1' and modified_accu_int(47 downto 24) = 0) or
+				   (alu_ctrl.word_24_update = '0' and modified_accu_int(55 downto  0) = 0) then
+					modified_sr(Z_FLAG) <= '1';
+				else
+					modified_sr(Z_FLAG) <= '0';
+				end if;
+			when others => -- Don't touch
+		end case;
+
+		-- Negative flag generation
+		----------------------------
+		case alu_ctrl.ccr_flags_ctrl(N_FLAG) is
+			when CLEAR  => modified_sr(N_FLAG) <= '0';
+			when SET    => modified_sr(N_FLAG) <= '1';
+			when MODIFY =>
+				-- in case the result is negative set this flag
+				-- distinguish between 24 bit and 56 bit ALU operations
+				-- 24 bit instructions are LSL, LSR, ROR, ROL, OR, EOR, NOT, AND
+				if alu_ctrl.word_24_update = '1' then
+					modified_sr(N_FLAG) <= std_logic(modified_accu_int(47));
+				else
+					modified_sr(N_FLAG) <= std_logic(modified_accu_int(55));
+				end if;
+			when others => -- Don't touch
+		end case;
+
+		-- Unnormalized flag generation
+		----------------------------
+		case alu_ctrl.ccr_flags_ctrl(U_FLAG) is
+			when CLEAR  => modified_sr(U_FLAG) <= '0';
+			when SET    => modified_sr(U_FLAG) <= '1';
+			when MODIFY =>
+				-- Set unnormalized bit according to the scaling mode
+				if (scaling_mode = "00" and alu_post_adder_result(47) = alu_post_adder_result(46)) or
+				   (scaling_mode = "01" and alu_post_adder_result(48) = alu_post_adder_result(47)) or
+				   (scaling_mode = "10" and alu_post_adder_result(46) = alu_post_adder_result(45)) then
+					modified_sr(U_FLAG) <= '1';
+				else
+					modified_sr(U_FLAG) <= '0';
+				end if;
+			when others => -- Don't touch
+		end case;
+
+		-- Extension flag generation
+		----------------------------
+		case alu_ctrl.ccr_flags_ctrl(E_FLAG) is
+			when CLEAR  => modified_sr(E_FLAG) <= '0';
+			when SET    => modified_sr(E_FLAG) <= '1';
+			when MODIFY =>
+				-- Set extension flag by default
+				modified_sr(E_FLAG) <= '1';
+				-- Clear extension flag according to the scaling mode
+				case scaling_mode is
+					when "00" =>
+						if alu_post_adder_result(55 downto 47) = "111111111" or alu_post_adder_result(55 downto 47) = "000000000" then
+							modified_sr(E_FLAG) <= '0';
+						end if;
+					when "01" =>
+						if alu_post_adder_result(55 downto 48) = "11111111" or alu_post_adder_result(55 downto 48) = "00000000" then
+							modified_sr(E_FLAG) <= '0';
+						end if;
+					when "10" =>
+						if alu_post_adder_result(55 downto 46) = "1111111111" or alu_post_adder_result(55 downto 46) = "0000000000" then
+							modified_sr(E_FLAG) <= '0';
+						end if;
+					when others =>
+						modified_sr(E_FLAG) <= '0';
+				end case;
+			when others => -- Don't touch
+		end case;
+
+		-- Limit flag generation (equals overflow flag generaton!)
+		-- Clearing of the Limit flag has to be done by the user!
+		-----------------------------------------------------------
+		case alu_ctrl.ccr_flags_ctrl(L_FLAG) is
+			when CLEAR  => modified_sr(L_FLAG) <= '0';
+			when SET    => modified_sr(L_FLAG) <= '1';
+			when MODIFY =>
+				-- There are two sources for the overflow flag:
+				-- 1)
+				-- in case the result cannot be represented using 56 bits set
+				-- the overflow flag. this is the case when the two MSBs of 
+				-- the 57 bit result are different
+				-- 2)
+				-- The shifter circuit performs a 56 bit left shift. In case the 
+				-- two MSBs of the operand are different set the overflow flag as well
+				if (alu_ctrl.div_instr = '0' and alu_post_adder_result(56) /= alu_post_adder_result(55)) or
+			   	   (alu_ctrl.shift_mode = SHIFT_LEFT and alu_ctrl.word_24_update = '0' and 
+				    alu_shifter_overflow_out = '1' ) then
+					modified_sr(L_FLAG) <= '1';
+				end if;
+			when others => -- Don't touch
+		end case;
+
+		-- Scaling flag generation (DSP56002 and up)
+		--------------------------------------------
+		-- Scaling flag is not generated in the ALU, but when A or B are read to the XDB or YDB
+
+	end process;
+
+
+	src_operand_select: process(register_file, alu_ctrl) is
+	begin
+		-- decoding according similar to JJJ representation
+		case alu_ctrl.add_src_stage_1 is 
+			when "000" =>
+				-- select depending on destination accu
+				if alu_ctrl.dst_accu = '0' then
+					alu_src_op <= register_file.a;
+				else
+					alu_src_op <= register_file.b;
+				end if;
+			when "001" => -- A,B or B,A
+				-- select depending on destination accu
+				if alu_ctrl.dst_accu = '0' then
+					alu_src_op <= register_file.b;
+				else
+					alu_src_op <= register_file.a;
+				end if;
+			when "010" =>  -- X
+				alu_src_op(55 downto 48) <= (others => register_file.x1(23));
+				alu_src_op(47 downto  0) <= register_file.x1 & register_file.x0;
+			when "011" =>  -- Y
+				alu_src_op(55 downto 48) <= (others => register_file.y1(23));
+				alu_src_op(47 downto  0) <= register_file.y1 & register_file.y0;
+			when "100" =>  -- x0
+				alu_src_op(55 downto 48) <= (others => register_file.x0(23));
+				alu_src_op(47 downto 24) <= register_file.x0;
+				alu_src_op(23 downto  0) <= (others => '0');
+			when "101" =>  -- y0
+				alu_src_op(55 downto 48) <= (others => register_file.y0(23));
+				alu_src_op(47 downto 24) <= register_file.y0;
+				alu_src_op(23 downto  0) <= (others => '0');
+			when "110" =>  -- x1
+				alu_src_op(55 downto 48) <= (others => register_file.x1(23));
+				alu_src_op(47 downto 24) <= register_file.x1;
+				alu_src_op(23 downto  0) <= (others => '0');
+			when "111" =>  -- y1
+				alu_src_op(55 downto 48) <= (others => register_file.y1(23));
+				alu_src_op(47 downto 24) <= register_file.y1;
+				alu_src_op(23 downto  0) <= (others => '0');
+			when others =>
+		end case;
+	end process;
+
+	alu_logical_functions: process(alu_ctrl, alu_src_op, alu_shifter_out) is
+	begin
+		alu_logic_conj <= alu_shifter_out;
+		case alu_ctrl.logic_function is
+			when "110" =>
+				alu_logic_conj(47 downto 24) <= alu_shifter_out(47 downto 24) and alu_src_op(47 downto 24);
+			when "010" =>
+				alu_logic_conj(47 downto 24) <= alu_shifter_out(47 downto 24) or  alu_src_op(47 downto 24);
+			when "011" =>
+				alu_logic_conj(47 downto 24) <= alu_shifter_out(47 downto 24) xor alu_src_op(47 downto 24);
+			when "111" =>
+				alu_logic_conj(47 downto 24) <= not alu_shifter_out(47 downto 24);
+			when others =>
+		end case;
+	end process;
+
+	alu_adder : process(alu_ctrl, alu_src_op, alu_multiplier_out, alu_shifter_out) is
+		variable add_src_op_1 : signed(56 downto 0);
+		variable add_src_op_2 : signed(56 downto 0);
+		variable carry_const  : signed(56 downto 0);
+		variable alu_shifter_out_57 : signed(56 downto 0);
+		variable alu_add_result_58  : signed(57 downto 0);
+		variable alu_add_result_interm : signed(56 downto 0);
+		variable invert_carry_flag : std_logic;
+	begin
+
+		-- by default do not invert the carry
+		invert_carry_flag := '0';
+
+		-- determine whether to use multiplier output, the operand defined above, or zeros!
+		-- resizing is done here already. Like that we can see whether an overflow
+		-- occurs due to negating the source operand
+		case alu_ctrl.add_src_stage_2 is
+			when "00" => add_src_op_1 := (others => '0');
+			when "10" => add_src_op_1 := resize(alu_multiplier_out, 57);
+			when others => add_src_op_1 := resize(alu_src_op, 57);
+		end case;
+
+		-- determine the sign for the 1st operand!
+		case alu_ctrl.add_src_sign is
+			-- normal operation
+			when "00" => add_src_op_1 := add_src_op_1;
+			-- negative sign
+			when "01" => add_src_op_1 := - add_src_op_1;
+			             invert_carry_flag := not invert_carry_flag;
+			-- change according to sign
+			-- performs - | accu | for the CMPM instruction
+			when "10" =>
+				-- we subtract in any case, so invert the carry!
+				invert_carry_flag := not invert_carry_flag;
+				if add_src_op_1(55) = '0' then 
+					add_src_op_1 := - add_src_op_1;
+				else
+					add_src_op_1 :=   add_src_op_1;
+				end if;
+			-- div instruction!
+			-- sign dependant of D[55] XOR S[23], if 1 => positive , if 0 => negative
+			-- add_src_op_1 holds S[23] (sign extension!)
+			when others => 
+				if (alu_ctrl.shift_src = '0' and add_src_op_1(55) /= register_file.a(55)) or
+			   	   (alu_ctrl.shift_src = '1' and add_src_op_1(55) /= register_file.b(55)) then 
+					add_src_op_1 :=   add_src_op_1;
+				else
+					add_src_op_1 := - add_src_op_1;
+--					invert_carry_flag := not invert_carry_flag;
+				end if;
+		end case;
+
+		alu_shifter_out_57 := resize(alu_shifter_out, 57);
+
+		-- determine the sign for the 2nd operand (coming from the shifter)!
+		case alu_ctrl.shift_src_sign is
+			-- negative sign
+			when "01" =>
+			   	add_src_op_2 := - alu_shifter_out_57;
+			-- change according to sign
+			-- this allows to build the magnitude (ABS, CMPM)
+			when "10" =>
+				if alu_shifter_out(55) = '1' then 
+					add_src_op_2 := - alu_shifter_out_57;
+				else
+					add_src_op_2 :=   alu_shifter_out_57;
+				end if;
+			when others =>
+			   	add_src_op_2 := alu_shifter_out_57;
+		end case;
+
+		-- determine whether carry flag has to be added or subtracted
+		if alu_ctrl.rounding_used = "10" then
+			carry_const := (others => '0');
+			-- add carry flag
+			carry_const(0) := register_file.sr(C_FLAG);
+		elsif alu_ctrl.rounding_used = "11" then
+			-- subtract carry flag
+			carry_const := (others => register_file.sr(0)); -- carry flag
+		else
+			carry_const := (others => '0');
+		end if;
+
+		-- add the values and calculate the carry bit
+		alu_add_result_interm := ('0' & add_src_op_1(55 downto 0)) + 
+		                         ('0' & add_src_op_2(55 downto 0)) +
+		                         ('0' & carry_const(55 downto 0));
+
+		-- here pops the new carry out of the adder
+		if invert_carry_flag = '0' then
+			alu_add_carry_out <= alu_add_result_interm(56);
+		else 
+			alu_add_carry_out <= not alu_add_result_interm(56);
+		end if;
+
+		-- calculate the last bit (56), in order to test for overflow later on
+		alu_add_result(55 downto 0) <= alu_add_result_interm(55 downto 0);
+--		alu_add_result(56) <= add_src_op_1(56) xor add_src_op_2(56) xor alu_add_result_interm(56);
+		alu_add_result(56) <= add_src_op_1(56) xor add_src_op_2(56) 
+		                      xor carry_const(56) xor alu_add_result_interm(56);
+
+	end process alu_adder;
+
+
+	-- Adder after the normal arithmetic adder
+	-- This adder is responsible for
+--	-- 1) carry addition
+--	-- 2) carry subtration
+	-- 3) convergent rounding
+	alu_post_adder: process(alu_add_result, scaling_mode, alu_ctrl) is
+		variable post_adder_constant : signed(56 downto 0);
+		variable testing_constant    : signed(24 downto 0);
+	begin
+		-- by default add nothing
+		post_adder_constant := (others => '0');
+
+		case alu_ctrl.rounding_used is
+			-- rounding dependant on scaling bits
+			when "01" =>
+				case scaling_mode is 
+					-- no scaling
+					when "00" => testing_constant := alu_add_result(23 downto 0) & '0';
+					-- scale down
+					when "01" => testing_constant := alu_add_result(24 downto 0);
+					-- scale up
+					when "10" => testing_constant := alu_add_result(22 downto 0) & "00";
+					when others =>
+					             testing_constant := alu_add_result(23 downto 0) & '0';
+				end case;
+
+				-- Special case!
+				if testing_constant(24) = '1' and testing_constant(23 downto 0) = X"000000" then
+					-- add depending on bit left to the rounding position
+					case scaling_mode is
+						-- no scaling
+						when "00" => post_adder_constant(23) := alu_add_result(24);
+						-- scale down
+						when "01" => post_adder_constant(24) := alu_add_result(25);
+						-- scale up
+						when "10" => post_adder_constant(22) := alu_add_result(23);
+						when others =>
+					end case;
+				else -- testing_constant /= X"1000000" 
+					-- add rounding constant depending on scaling mode
+					-- results in round up if MSB of testing constant is set, else nothing happens
+					case scaling_mode is
+						-- no scaling
+						when "00" => post_adder_constant(23) := '1';
+						-- scale down
+						when "01" => post_adder_constant(24) := '1';
+						-- scale up
+						when "10" => post_adder_constant(22) := '1';
+						when others =>
+					end case;
+				end if;
+			-- no rounding
+			when others =>
+				post_adder_constant := (others => '0');
+
+		end case;
+
+		-- Add the result of the first adder to the constant (e.g., carry flag)
+		alu_post_adder_result <= alu_add_result + post_adder_constant;
+
+		-- When rounding is used set 24 LSBs to zero!
+		if alu_ctrl.rounding_used = "01" then
+			alu_post_adder_result(23 downto 0) <= (others => '0');
+		end if;
+	end process;
+
+
+
+	alu_select_new_accu: process(alu_post_adder_result, alu_logic_conj, alu_ctrl) is
+	begin
+		if alu_ctrl.logic_function /= "000" then
+			modified_accu_int <= alu_logic_conj;
+		else
+			modified_accu_int <= alu_post_adder_result(55 downto 0);
+		end if;
+	end process;
+
+
+	-- contains the 24*24 bit fractional multiplier
+	alu_multiplier : process(register_file, alu_ctrl) is
+		variable src_op1: signed(23 downto 0);
+		variable src_op2: signed(23 downto 0);
+		variable mul_result_interm : signed(47 downto 0);
+	begin
+		-- select source operands for multiplication
+		case alu_ctrl.mul_op1 is
+			when "00"   => src_op1 := register_file.x0;
+			when "01"   => src_op1 := register_file.x1;
+			when "10"   => src_op1 := register_file.y0;
+			when others => src_op1 := register_file.y1;
+		end case;
+		case alu_ctrl.mul_op2 is
+			when "00"   => src_op2 := register_file.x0;
+			when "01"   => src_op2 := register_file.x1;
+			when "10"   => src_op2 := register_file.y0;
+			when others => src_op2 := register_file.y1;
+		end case;
+
+		-- perform integer multiplication
+		mul_result_interm := src_op1 * src_op2;
+
+		-- sign extension of result
+		alu_multiplier_out(55 downto 48) <= (others => mul_result_interm(47));
+		-- convert from two's complement representation to fractional format
+		-- signed integer multiplication delivers twice the sign bit, but only one is needed for the
+		-- fractional multiplication, so remove one and append a zero to the result
+		alu_multiplier_out(47 downto 0) <= mul_result_interm(46 downto 0) & '0';
+
+	end process alu_multiplier;
+
+
+	-- contains the data shifter
+	alu_shifter: process(register_file, alu_ctrl, norm_instr_asl, norm_instr_asr) is
+		variable src_accu : signed(55 downto 0);
+		variable shift_to_perform : alu_shift_mode;
+	begin
+		-- read source accumulator
+		if alu_ctrl.shift_src = '0' then
+			src_accu := register_file.a;
+		else
+			src_accu := register_file.b;
+		end if;
+
+		alu_shifter_carry_out <= '0';
+		alu_shifter_overflow_out <= '0';
+
+		-- NORM instruction determines the shift value just
+		-- in time, so overwrite the flag from the alu_ctrl
+ 		-- for this instruction by the calculated value
+		if alu_ctrl.norm_instr = '0' then
+			shift_to_perform := alu_ctrl.shift_mode;
+		else
+			if norm_instr_asl = '1' then
+				shift_to_perform := SHIFT_LEFT;
+			elsif norm_instr_asr = '1' then
+				shift_to_perform := SHIFT_RIGHT;
+			else
+				shift_to_perform := NO_SHIFT;
+			end if;
+		end if;
+
+		case shift_to_perform is
+			when NO_SHIFT => 
+				alu_shifter_out <= src_accu;
+			when SHIFT_LEFT => 
+				-- ASL, ADDL, DIV?
+				if alu_ctrl.word_24_update = '0' then
+					-- special handling for div instruction required
+					if alu_ctrl.div_instr = '1' then
+						alu_shifter_out <= src_accu(54 downto 0) & register_file.sr(C_FLAG);
+					else
+						alu_shifter_out <= src_accu(54 downto 0) & '0';
+					end if;
+					alu_shifter_carry_out <= src_accu(55);
+					-- detect overflow that results from left shifting 
+					-- Needed for ASL, ADDL, DIV instructions
+					if src_accu(55) /= src_accu(54) then
+						alu_shifter_overflow_out <= '1';
+					end if;
+				-- LSL/ROL?
+				elsif alu_ctrl.word_24_update = '1' then
+					alu_shifter_out(55 downto 48) <= src_accu(55 downto 48);
+					alu_shifter_out(23 downto  0) <= src_accu(23 downto  0);
+					alu_shifter_carry_out <= src_accu(47);
+					if alu_ctrl.rotate = '0' then -- LSL ?
+						alu_shifter_out(47 downto 24) <= src_accu(46 downto 24) & '0';
+					else -- ROL ?
+						alu_shifter_out(47 downto 24) <= src_accu(46 downto 24) & register_file.sr(C_FLAG);
+					end if;
+				end if;
+			when SHIFT_RIGHT => 
+				-- ASR?
+				if alu_ctrl.word_24_update = '0' then
+					alu_shifter_out <= src_accu(55) & src_accu(55 downto 1);
+					alu_shifter_carry_out <= src_accu(0);
+				-- LSR/ROR?
+				elsif alu_ctrl.word_24_update = '1' then
+					alu_shifter_out(55 downto 48) <= src_accu(55 downto 48);
+					alu_shifter_out(23 downto  0) <= src_accu(23 downto  0);
+					alu_shifter_carry_out <= src_accu(24);
+					if alu_ctrl.rotate = '0' then -- LSR
+						alu_shifter_out(47 downto 24) <= '0' & src_accu(47 downto 25);
+					else -- ROR
+						alu_shifter_out(47 downto 24) <= register_file.sr(C_FLAG) & src_accu(47 downto 25);
+					end if;
+				end if;
+			when ZEROS =>
+				alu_shifter_out <= (others => '0');
+		end case;
+	end process alu_shifter;
+
+
+	-- Special handling for NORM instruction
+ 	-- Determine which case occurs (see User's Manual for more information)
+	norm_instr_logic: process(register_file, addr_r_in) is
+	begin
+		norm_instr_asl <= '0';
+		norm_instr_asr <= '0';
+
+		-- Either left shift
+		if register_file.sr(E_FLAG) = '0' and
+		   register_file.sr(U_FLAG) = '1' and
+		   register_file.sr(Z_FLAG) = '0' then
+			norm_instr_asl <= '1';
+			norm_update_ccr <= '1';
+			addr_r_out <= addr_r_in - 1;
+		-- Or right shift
+		elsif register_file.sr(E_FLAG) = '1' then
+			norm_instr_asr <= '1';
+			norm_update_ccr <= '1';
+			addr_r_out <= addr_r_in + 1;
+		-- Or do nothing!
+		else 
+			norm_update_ccr <= '0';
+			addr_r_out <= addr_r_in;
+		end if;
+	end process;
+
+end architecture;
diff --git a/FireBee/trunk/vhdl/dsp56k/src/exec_stage_bit_modify.vhd b/FireBee/trunk/vhdl/dsp56k/src/exec_stage_bit_modify.vhd
new file mode 100644
index 0000000..0bd69cd
--- /dev/null
+++ b/FireBee/trunk/vhdl/dsp56k/src/exec_stage_bit_modify.vhd
@@ -0,0 +1,86 @@
+-----------------------------------------------------------------------------
+--! @file
+--! @author Matthias Alles
+--! @date 01/2009
+--! @brief Bit modify (BCLR, BSET, J(S)CLR, J(S)SET)
+--!
+------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.parameter_pkg.all;
+use work.types_pkg.all;
+use work.constants_pkg.all;
+
+entity exec_stage_bit_modify is port(
+	instr_word        : in  std_logic_vector(23 downto 0);
+	instr_array       : in  instructions_type;
+	src_operand       : in  std_logic_vector(23 downto 0);
+	register_file     : in  register_file_type;
+	dst_operand       : out std_logic_vector(23 downto 0);
+	bit_cond_met      : out std_logic;
+	modify_sr         : out std_logic;
+	modified_sr       : out std_logic_vector(15 downto 0)
+);
+end entity;
+
+
+architecture rtl of exec_stage_bit_modify is 
+
+	signal operand_bit : std_logic;
+	signal src_operand_32 : std_logic_vector(31 downto 0);
+
+begin
+
+	-- this is just a helper signal to prevent the simulator
+	-- to stop when accessing a bit > 23.
+	src_operand_32 <= "00000000" & src_operand;
+	-- read the bit we want to test (and modify)
+	operand_bit <= src_operand_32(to_integer(unsigned(instr_word(4 downto 0))));
+
+	-- modify the Carry flag only for the bit modify instructions!
+	modify_sr <= '1' when instr_array = INSTR_BCLR or instr_array = INSTR_BSET or instr_array = INSTR_BCHG or instr_array = INSTR_BTST else '0';
+	modified_sr <= register_file.sr(15 downto 1) & operand_bit;
+
+	bit_operation: process(instr_word, instr_array, src_operand, operand_bit) is
+		variable new_bit : std_logic;
+	begin
+		-- do nothing by default!
+		dst_operand <= src_operand;
+		bit_cond_met <= '0';
+
+		-- determine which bit to write
+		if instr_array = INSTR_BCLR then
+			new_bit := '0';
+		elsif instr_array = INSTR_BSET then
+			new_bit := '1';
+		else -- BCHG
+			new_bit := not operand_bit;
+		end if;
+
+		if instr_array = INSTR_BCLR or instr_array = INSTR_BSET or instr_array = INSTR_BCHG then
+			dst_operand(to_integer(unsigned(instr_word(4 downto 0)))) <= new_bit;
+		end if;
+
+
+		-- check for the jump instructions whether condition is met or not!
+		if instr_array = INSTR_JCLR or instr_array = INSTR_JSCLR then
+			if operand_bit = '0' then
+				bit_cond_met <= '1';
+			else
+				bit_cond_met <= '0';
+			end if;
+		end if;
+		if instr_array = INSTR_JSET or instr_array = INSTR_JSSET then
+			if operand_bit = '0' then
+				bit_cond_met <= '0';
+			else
+				bit_cond_met <= '1';
+			end if;
+		end if;
+
+	end process;
+
+
+end architecture;
diff --git a/FireBee/trunk/vhdl/dsp56k/src/exec_stage_branch.vhd b/FireBee/trunk/vhdl/dsp56k/src/exec_stage_branch.vhd
new file mode 100644
index 0000000..f59cc09
--- /dev/null
+++ b/FireBee/trunk/vhdl/dsp56k/src/exec_stage_branch.vhd
@@ -0,0 +1,124 @@
+-----------------------------------------------------------------------------
+--! @file
+--! @author Matthias Alles
+--! @date 01/2009
+--! @brief Branch control
+--!
+------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.parameter_pkg.all;
+use work.types_pkg.all;
+use work.constants_pkg.all;
+
+entity exec_stage_branch is port(
+	activate_exec_bra : in  std_logic;
+	instr_word        : in  std_logic_vector(23 downto 0);
+	instr_array       : in  instructions_type;
+	register_file     : in  register_file_type;
+	jump_address      : in  unsigned(BW_ADDRESS-1 downto 0);
+	bit_cond_met      : in  std_logic;
+	cc_flag_set       : in  std_logic;
+	push_stack        : out push_stack_type;
+	pop_stack         : out pop_stack_type;
+	modify_pc         : out std_logic;
+	modified_pc       : out unsigned(BW_ADDRESS-1 downto 0);
+	modify_sr         : out std_logic;
+	modified_sr       : out std_logic_vector(15 downto 0)
+);
+end entity;
+
+
+architecture rtl of exec_stage_branch is 
+
+	signal branch_condition_met : std_logic;
+	signal modify_pc_int        : std_logic;
+
+begin
+
+	modify_pc_int <= '1' when activate_exec_bra = '1' and branch_condition_met = '1' else '0';
+	modify_pc     <= modify_pc_int;
+
+	calculate_branch_condition : process(instr_word, instr_array, register_file, bit_cond_met)
+	begin
+		branch_condition_met <= '0';
+
+		-- unconditional jumps
+		if instr_array = INSTR_JMP or 
+		   instr_array = INSTR_JSR or
+		   instr_array = INSTR_RTI or
+		   instr_array = INSTR_RTS then
+			-- jump always
+			branch_condition_met <= '1';
+		end if;
+		--  then see whether the branch condition is satisfied
+		if instr_array = INSTR_JCC or instr_array = INSTR_JSCC then
+			branch_condition_met <= cc_flag_set;
+		end if;
+		-- jmp that is executed according to a certain bit condition
+		if instr_array = INSTR_JCLR or instr_array = INSTR_JSCLR or
+		   instr_array = INSTR_JSET or instr_array = INSTR_JSSET then
+			branch_condition_met <= bit_cond_met;
+		end if;
+	end process calculate_branch_condition;
+
+
+	calculate_branch_target : process(instr_array, instr_word, jump_address)
+	begin
+		modified_pc <= jump_address;
+
+		-- address calculation is the same for the following instructions
+		if instr_array = INSTR_JMP  or 
+		   instr_array = INSTR_JCC  or 
+		   instr_array = INSTR_JSCC or
+		   instr_array = INSTR_JSR then
+			if instr_word(18) = '1' then
+				-- short jump address included in opcode (bits 11 downto 0)
+				modified_pc(11 downto 0) <= unsigned(instr_word(11 downto 0));
+			elsif instr_word(18) = '0' then
+				-- effective address defined by opcode and coming from address generator unit
+				modified_pc <= jump_address;
+			end if;
+		end if;
+
+		-- jump address contains the obligatory address of the second
+		-- instruction word
+		if instr_array = INSTR_JCLR or
+		   instr_array = INSTR_JSET or
+		   instr_array = INSTR_JSCLR or
+		   instr_array = INSTR_JSSET then
+			   modified_pc <= jump_address;
+		end if;
+
+		-- target address is stored on the stack
+		if instr_array = INSTR_RTS or
+		   instr_array = INSTR_RTI then
+			   modified_pc <= unsigned(register_file.current_ssh);
+		end if;
+	end process calculate_branch_target;
+
+	-- Subroutine functions need to store PC and SR on the stack
+	push_stack.valid <= '1' when modify_pc_int = '1' and (instr_array = INSTR_JSCC  or instr_array = INSTR_JSR or 
+	                                                      instr_array = INSTR_JSCLR or instr_array = INSTR_JSSET) else '0';
+	push_stack.content <= PC_AND_SR;
+	-- pc is set externally!
+	push_stack.pc <= (others => '0');
+
+	-- RTI/RTS instructions need to read from the stack
+	pop_stack.valid <= '1' when modify_pc_int = '1' and (instr_array = INSTR_RTI or instr_array = INSTR_RTS) else '0';
+
+	-- some instructions require to set the SR
+	calculate_status_register : process(instr_array)
+	begin
+		modify_sr <= '0';
+		modified_sr <= (others => '0');
+		if instr_array = INSTR_RTI then
+			modify_sr <= '1';
+			modified_sr <= register_file.current_ssl;
+		end if;
+	end process calculate_status_register;
+
+
+end architecture rtl;
diff --git a/FireBee/trunk/vhdl/dsp56k/src/exec_stage_cc_flag_calc.vhd b/FireBee/trunk/vhdl/dsp56k/src/exec_stage_cc_flag_calc.vhd
new file mode 100644
index 0000000..2f69230
--- /dev/null
+++ b/FireBee/trunk/vhdl/dsp56k/src/exec_stage_cc_flag_calc.vhd
@@ -0,0 +1,82 @@
+-----------------------------------------------------------------------------
+--! @file
+--! @author Matthias Alles
+--! @date 01/2009
+--! @brief Calculate whether cc flag condition is true
+--!
+------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.parameter_pkg.all;
+use work.types_pkg.all;
+use work.constants_pkg.all;
+
+entity exec_stage_cc_flag_calc is port(
+	instr_word        : in  std_logic_vector(23 downto 0);
+	instr_array       : in  instructions_type;
+	register_file     : in  register_file_type;
+	cc_flag_set       : out std_logic
+);
+end entity;
+
+
+architecture rtl of exec_stage_cc_flag_calc is
+
+
+begin
+
+	calculate_cc_flag : process(instr_word, instr_array, register_file)
+
+		variable cc_select : std_logic_vector(3 downto 0);
+
+		procedure calculate_cc_flag(cc: std_logic_vector(3 downto 0)) is
+			variable c_flag : std_logic := register_file.ccr(0);
+			variable v_flag : std_logic := register_file.ccr(1);
+			variable z_flag : std_logic := register_file.ccr(2);
+			variable n_flag : std_logic := register_file.ccr(3);
+			variable u_flag : std_logic := register_file.ccr(4);
+			variable e_flag : std_logic := register_file.ccr(5);
+			variable l_flag : std_logic := register_file.ccr(6);
+
+		begin
+			if (cc = "0000" and c_flag = '0')  or -- CC: carry clear 
+			   (cc = "1000" and c_flag = '1')  or -- CS: carry set
+			   (cc = "0101" and e_flag = '0')  or -- EC: extension clear
+			   (cc = "1010" and z_flag = '1')  or -- EQ: equal
+			   (cc = "1101" and e_flag = '1')  or -- ES: extension set
+			   (cc = "0001" and (n_flag = v_flag))  or -- GE: greater than or equal
+			   (cc = "0001" and ((n_flag xor v_flag) or z_flag) = '0')  or -- GT: greater than
+			   (cc = "0110" and l_flag = '0')  or -- LC: limit clear 
+			   (cc = "1111" and ((n_flag xor v_flag) or z_flag ) = '1')  or -- LE: less or equal
+			   (cc = "1110" and l_flag = '1')  or -- LS: limit set
+			   (cc = "1001" and (n_flag /= v_flag))  or -- LT: less than
+			   (cc = "1011" and n_flag = '1')  or -- MI: minus
+			   (cc = "0010" and z_flag = '0')  or -- NE: not equal
+			   (cc = "1100" and (( not u_flag and not  e_flag) or z_flag) = '1') or -- NR: normalized
+			   (cc = "0011" and n_flag = '0')  or -- PL: plus
+			   (cc = "0100" and (( not u_flag and not e_flag ) or z_flag) = '0')   -- NN: not normalized
+			then
+				cc_flag_set <= '1';
+			end if;
+		end procedure;
+	
+	begin
+
+		cc_flag_set <= '0';
+
+		-- Rip the flags we have to test for from the instruction word
+		if (instr_array = INSTR_JCC and instr_word(18) = '0') or
+		   (instr_array = INSTR_JSCC) then
+			   cc_select := instr_word(3 downto 0);
+		else
+			   cc_select := instr_word(15 downto 12);
+		end if;
+	
+		calculate_cc_flag(cc_select);
+
+	end process;
+
+
+end architecture;
diff --git a/FireBee/trunk/vhdl/dsp56k/src/exec_stage_cr_mod.vhd b/FireBee/trunk/vhdl/dsp56k/src/exec_stage_cr_mod.vhd
new file mode 100644
index 0000000..2465125
--- /dev/null
+++ b/FireBee/trunk/vhdl/dsp56k/src/exec_stage_cr_mod.vhd
@@ -0,0 +1,79 @@
+-----------------------------------------------------------------------------
+--! @file
+--! @author Matthias Alles
+--! @date 01/2009
+--! @brief
+--!
+------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.parameter_pkg.all;
+use work.types_pkg.all;
+use work.constants_pkg.all;
+
+entity exec_stage_cr_mod is port (
+	activate_exec_cr_mod : in  std_logic;
+	instr_word           : in  std_logic_vector(23 downto 0);
+	instr_array          : in  instructions_type;
+	register_file        : in  register_file_type;
+	modify_sr            : out std_logic;
+	modified_sr          : out std_logic_vector(15 downto 0);
+	modify_omr           : out std_logic;
+	modified_omr         : out std_logic_vector(7 downto 0)
+);
+end exec_stage_cr_mod;
+
+
+architecture rtl of exec_stage_cr_mod is
+
+begin
+
+	process(activate_exec_cr_mod, instr_word, instr_array, register_file) is
+		variable imm8 : std_logic_vector(7 downto 0);
+		variable op8  : std_logic_vector(7 downto 0);
+		variable res8 : std_logic_vector(7 downto 0);
+	begin
+		modify_sr    <= '0';
+		modify_omr   <= '0';
+		modified_sr  <= (others => '0');
+		modified_omr <= (others => '0');
+
+		imm8 := instr_word(15 downto 8);
+		if instr_word(1 downto 0) = "00" then
+			-- read MR
+			op8 := register_file.mr;
+		elsif instr_word(1 downto 0) = "01" then
+			-- read CCR
+			op8 := register_file.ccr;
+		else  -- instr_word(1 downto 0) = "10"
+			-- read OMR
+			op8 := register_file.omr;
+		end if;
+
+		if instr_array = INSTR_ANDI then
+			res8 := imm8 and op8;
+		else -- instr_array = INSTR_ORI
+			res8 := imm8 or op8;
+		end if;
+
+		-- only write the result when activated
+		if activate_exec_cr_mod = '1' then
+			if instr_word(1 downto 0) = "00" then
+				-- update MR
+				modify_sr    <= '1';
+				modified_sr  <= res8 & register_file.ccr;
+			elsif instr_word(1 downto 0) = "01" then
+				-- update CCR
+				modify_sr    <= '1';
+				modified_sr  <= register_file.mr & res8;
+			elsif instr_word(1 downto 0) = "10" then
+				-- update OMR
+				modify_omr   <= '1';
+				modified_omr <= res8;
+			end if;
+		end if;
+	end process;
+
+end architecture;
diff --git a/FireBee/trunk/vhdl/dsp56k/src/exec_stage_loops.vhd b/FireBee/trunk/vhdl/dsp56k/src/exec_stage_loops.vhd
new file mode 100644
index 0000000..3472636
--- /dev/null
+++ b/FireBee/trunk/vhdl/dsp56k/src/exec_stage_loops.vhd
@@ -0,0 +1,207 @@
+------------------------------------------------------------------------------
+--! @file
+--! @author Matthias Alles
+--! @date 01/2009
+--! @brief Loop control (REP, DO, ENDDO)
+--!
+------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.parameter_pkg.all;
+use work.types_pkg.all;
+use work.constants_pkg.all;
+
+entity exec_stage_loop is port(
+	clk, rst           : in  std_logic;
+	activate_exec_loop : in  std_logic;
+	instr_word        : in  std_logic_vector(23 downto 0);
+	instr_array       : in  instructions_type;
+	loop_iterations   : in  unsigned(15 downto 0);
+	loop_address      : in  unsigned(BW_ADDRESS-1 downto 0);
+	loop_start_address: in  unsigned(BW_ADDRESS-1 downto 0);
+	register_file     : in  register_file_type;
+	fetch_perform_enddo: in std_logic;
+	memory_stall      : in  std_logic;
+	push_stack        : out push_stack_type;
+	pop_stack         : out pop_stack_type;
+	stall_rep         : out std_logic;
+	stall_do          : out std_logic;
+	decrement_lc      : out std_logic;
+	modify_lc         : out std_logic;
+	modified_lc       : out unsigned(15 downto 0);
+	modify_la         : out std_logic;
+	modified_la       : out unsigned(15 downto 0);
+	modify_pc         : out std_logic;
+	modified_pc       : out unsigned(BW_ADDRESS-1 downto 0);
+	modify_sr         : out std_logic;
+	modified_sr       : out std_logic_vector(15 downto 0)
+);
+end entity;
+
+
+architecture rtl of exec_stage_loop is
+
+	signal rep_loop_polling : std_logic;
+	signal do_loop_polling  : std_logic;
+	signal enddo_polling    : std_logic;
+	signal lc_temp          : unsigned(15 downto 0);
+	signal rf_lc_eq_1       : std_logic;
+	signal memory_stall_t   : std_logic;
+
+begin
+
+	modified_pc <= loop_start_address;
+
+
+	-- loop counter in register file equal to 1?
+	rf_lc_eq_1 <= '1' when register_file.lc = 1 else '0';
+
+	process(activate_exec_loop, instr_array, register_file, fetch_perform_enddo,
+	        rep_loop_polling, loop_iterations, rf_lc_eq_1, loop_start_address) is
+	begin
+		stall_rep <= '0';
+		stall_do  <= '0';
+
+		modify_la <= '0';
+		modify_lc <= '0';
+		modify_pc <= '0';
+		modify_sr <= '0';
+		modified_la <= loop_address;
+		modified_lc <= loop_iterations; -- default
+		-- set the loop flag LF (bit 15) of Status register
+		modified_sr(15) <= '1';
+		modified_sr(14 downto 0) <= register_file.sr(14 downto 0);
+
+		push_stack.valid <= '0'; -- push PC and SR on the stack
+		push_stack.pc    <= loop_start_address;
+		push_stack.content <= LA_AND_LC;
+
+		pop_stack.valid <= '0';
+		decrement_lc <= '0';
+		------------------
+		-- DO instruction
+		------------------
+		if activate_exec_loop = '1' and instr_array = INSTR_DO then
+			-- first instruction of the do loop instruction?
+			if do_loop_polling = '0' then
+				stall_do <= '1';
+				modify_lc <= '1'; -- store the new loop counter
+				modify_la <= '1'; -- store the new loop address 
+				push_stack.valid <= '1'; -- push LA and LC on the stack
+				push_stack.content <= LA_AND_LC;
+			else  -- second clock cycle of the do loop instruction ?
+				push_stack.valid <= '1'; -- push PC and SR on the stack
+				push_stack.pc    <= loop_start_address;
+				push_stack.content <= PC_AND_SR;
+				-- set the PC to the first instruction of the loop
+				-- the already fetched instruction are flushed from the pipeline
+				-- this prevents problems, when the loop consists of only one or two instructions
+				modify_pc   <= '1';
+				-- set the loop flag
+				modify_sr   <= '1';
+			end if;
+		end if;
+		-----------------------------------------------
+		-- ENDDO instruction / loop end in fetch stage
+		-----------------------------------------------
+		if (activate_exec_loop = '1' and instr_array = INSTR_ENDDO) or fetch_perform_enddo = '1' or enddo_polling = '1' then
+			pop_stack.valid <= '1';
+			if enddo_polling = '0' then
+				-- only restore the LF from the stack
+				modified_sr(15) <= register_file.current_ssl(15);
+				modify_sr <= '1';
+				stall_do <= '1'; -- stall one clock cycle 
+			else
+				-- restore loop counter and loop address in second clock cycle
+				modified_lc <= unsigned(register_file.current_ssl);
+				modify_lc <= '1';
+				modified_la <= unsigned(register_file.current_ssh);
+				modify_la <= '1';
+			end if;
+		end if;
+		-------------------
+		-- REP instruction
+		-------------------
+		if activate_exec_loop = '1' and instr_array = INSTR_REP then
+			-- only do something when there are more than 1 iterations
+			-- the first execution is already on the way
+			if loop_iterations /= 1 then
+				stall_rep <= '1'; -- stall the fetch and decode stages
+				modify_lc <= '1'; -- store the loop counter
+				modified_lc <= loop_iterations - 1;
+			end if;
+		end if;
+
+		-- keep processing the single instruction
+		if rep_loop_polling = '1' then
+			stall_rep <= '1';
+			-- if the REP instruction caused a stall do not modify the lc!
+			if memory_stall_t = '0' then
+				if rf_lc_eq_1 = '0' then
+					decrement_lc <= '1';
+				-- when the instruction to repeat caused a memory stall
+				-- do not continue!
+				else
+					-- finish the REP instruction by restoring the LC
+					stall_rep <= '0';
+					modify_lc <= '1';
+					modified_lc <= lc_temp;
+				end if;
+			end if;
+		end if;
+	end process;
+
+
+	-- process that allows to remember that we are processing a REP/DO instruction
+	-- even though the REP instruction is not available in the pipeline anymore
+	-- also store the old loop counter
+	process(clk) is
+	begin
+		if rising_edge(clk) then
+			if rst = '1' then
+				rep_loop_polling <= '0';
+				do_loop_polling  <= '0';
+				enddo_polling    <= '0';
+				lc_temp <= (others => '0');
+				memory_stall_t <= '0';
+			else
+				memory_stall_t <= memory_stall;
+
+				if activate_exec_loop = '1' and instr_array = INSTR_REP then
+					-- only do something when there are more than 1 iterations
+					-- the first execution is already on the way
+					if loop_iterations /= 1 then
+						rep_loop_polling <= '1';
+						lc_temp <= register_file.lc;
+					end if;
+				end if;
+				-- test whether the REP instruction has been executed
+				if rep_loop_polling = '1' and rf_lc_eq_1 = '1' and memory_stall_t = '0'  then
+					rep_loop_polling <= '0';
+				end if;
+
+				-- do loop execution takes two clock cycles
+				-- in the first  clock cycle we store loop address and loop counter on the stack
+				-- in the second clock cycle we store programm counter and status register on the stack
+				if activate_exec_loop = '1' and instr_array = INSTR_DO then
+					do_loop_polling <= '1';
+				end if;
+				-- clear the flag immediately again (only two cycles execution time!)
+				if do_loop_polling = '1' then
+					do_loop_polling <= '0';
+				end if;
+
+				-- ENDDO instructions take two clock cycles as well!
+				if (activate_exec_loop = '1' and instr_array = INSTR_ENDDO) or fetch_perform_enddo = '1' then
+					enddo_polling <= '1';
+				end if;
+				if enddo_polling = '1' then
+					enddo_polling <= '0';
+				end if;
+			end if;
+		end if;
+	end process;
+
+end architecture;
diff --git a/FireBee/trunk/vhdl/dsp56k/src/fetch_stage.vhd b/FireBee/trunk/vhdl/dsp56k/src/fetch_stage.vhd
new file mode 100644
index 0000000..0848bf8
--- /dev/null
+++ b/FireBee/trunk/vhdl/dsp56k/src/fetch_stage.vhd
@@ -0,0 +1,67 @@
+------------------------------------------------------------------------------
+--! @file
+--! @author Matthias Alles
+--! @date 01/2009
+--! @brief Fetching from program memory
+--!
+------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.parameter_pkg.all;
+use work.types_pkg.all;
+
+
+entity fetch_stage is port(
+
+	pc_old        : in  unsigned(BW_ADDRESS-1 downto 0);
+	pc_new        : out unsigned(BW_ADDRESS-1 downto 0);
+	modify_pc     : in  std_logic;
+	modified_pc   : in  unsigned(BW_ADDRESS-1 downto 0);
+	register_file : in  register_file_type;
+	decrement_lc  : out std_logic;
+	perform_enddo : out std_logic
+
+);
+end fetch_stage;
+
+
+architecture rtl of fetch_stage is
+
+
+begin
+
+	pc_calculation: process(pc_old, modify_pc, modified_pc, register_file)  is
+	begin
+		decrement_lc  <= '0';
+		perform_enddo <= '0';
+
+		-- by default increment pc by one
+		pc_new <= pc_old + 1;
+		if modify_pc = '1' then
+			pc_new <= modified_pc;
+		end if;
+		-- Loop Flag set?
+		if register_file.sr(15) = '1' then
+			if register_file.la = pc_old then
+				-- Loop not finished?
+				-- => start from the beginning if necessary
+				if register_file.lc /= 1 then
+					-- if the last address was LA and the loop is not finished yet, we have to 
+					-- read now from the beginning of the loop again
+					pc_new <= unsigned(register_file.current_ssh(BW_ADDRESS-1 downto 0));
+					-- decrement loop counter
+					decrement_lc <= '1';
+				else
+					-- loop done!
+					-- => tell the loop controller in the exec stage to perform the enddo operation
+					-- (without flushing of the pipeline!)
+					perform_enddo <= '1';
+				end if;
+		   	end if;
+		end if;
+	end process pc_calculation;
+
+end architecture rtl;
+
diff --git a/FireBee/trunk/vhdl/dsp56k/src/mem_control.vhd b/FireBee/trunk/vhdl/dsp56k/src/mem_control.vhd
new file mode 100644
index 0000000..02c70eb
--- /dev/null
+++ b/FireBee/trunk/vhdl/dsp56k/src/mem_control.vhd
@@ -0,0 +1,1543 @@
+------------------------------------------------------------------------------
+--! @file
+--! @author Matthias Alles
+--! @date 01/2009
+--! @brief Internal DSP RAM
+--!
+------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.parameter_pkg.all;
+use work.types_pkg.all;
+
+entity mem_control is
+	generic(
+		mem_type : memory_type := P_MEM
+	);
+	port(
+		clk, rst        : in std_logic;
+		rd_addr         : in unsigned(BW_ADDRESS-1 downto 0);
+		rd_en           : in std_logic;
+		data_out        : out std_logic_vector(23 downto 0);
+		data_out_valid  : out std_logic;
+		wr_addr         : in  unsigned(BW_ADDRESS-1 downto 0);
+		wr_en           : in  std_logic;
+		wr_accomplished : out std_logic;
+		data_in         : in  std_logic_vector(23 downto 0)
+	);
+end entity mem_control;
+
+
+architecture rtl of mem_control is
+
+	signal int_mem_rd_addr : std_logic_vector(7 downto 0);
+	type int_mem_type is array(0 to 255) of std_logic_vector(23 downto 0);
+	signal int_mem : int_mem_type;
+	signal int_pmem : int_mem_type := (
+-- AGU testing
+X"390100",
+X"310A00",
+X"000000",
+X"204900",
+X"050FA1",
+X"060AA0",
+X"204900",
+X"390A00",
+X"060AA0",
+X"204900",
+X"000000",
+X"000000",
+X"000000",
+X"000000",
+-- AGU testing
+
+-- ABS begin
+--X"0000B9",
+--X"56F400",
+--X"200000",
+--X"200026",
+--X"56F400",
+--X"E00000",
+--X"200026",
+--X"56F400",
+--X"000000",
+--X"200026",
+--X"52F400",
+--X"000080",
+--X"200026",
+-- ABS end
+
+-- ADC begin
+--X"46F400",
+--X"000000",
+--X"47F400",
+--X"000001",
+--X"20001B",
+--X"51F400",
+--X"000001",
+--X"0000B9",
+--X"0001F9",
+--X"200039",
+--X"47F400",
+--X"800000",
+--X"53F400",
+--X"000080",
+--X"200039",
+-- ADC end
+
+-- ADD begin
+--X"46F400",
+--X"000000",
+--X"47F400",
+--X"000001",
+--X"20001B",
+--X"51F400",
+--X"000001",
+--X"0000B9",
+--X"0001F9",
+--X"200038",
+--X"47F400",
+--X"800000",
+--X"53F400",
+--X"000080",
+--X"200038",
+-- ADD end
+
+-- ADDL begin
+--X"56F400",
+--X"000055",
+--X"20001B",
+--X"51F400",
+--X"000055",
+--X"0000B9",
+--X"20001A",
+--X"56F400",
+--X"0000AA",
+--X"20001A",
+--X"53F400",
+--X"000080",
+--X"20001A",
+-- ADDL end
+
+-- ADDR begin
+--X"56F400",
+--X"000055",
+--X"20001B",
+--X"51F400",
+--X"000055",
+--X"0000B9",
+--X"20000A",
+--X"56F400",
+--X"0000AA",
+--X"20000A",
+--X"53F400",
+--X"000080",
+--X"20000A",
+-- ADDR end
+
+-- AND begin
+--X"46F400",
+--X"000FFF",
+--X"57F400",
+--X"FFFFFF",
+--X"0000B9",
+--X"20005E",
+--X"46F400",
+--X"FFF000",
+--X"57F400",
+--X"FFFFFF",
+--X"0000B9",
+--X"20005E",
+--X"46F400",
+--X"000000",
+--X"57F400",
+--X"FFFFFF",
+--X"0000B9",
+--X"20005E",
+-- AND end
+
+-- EOR begin
+--X"46F400",
+--X"000FFF",
+--X"57F400",
+--X"FF00FF",
+--X"0000B9",
+--X"20005B",
+--X"46F400",
+--X"FFFFFF",
+--X"57F400",
+--X"FFFFFF",
+--X"0000B9",
+--X"20005B",
+-- EOR end
+
+-- OR begin
+--X"46F400",
+--X"000FFF",
+--X"57F400",
+--X"FF00FF",
+--X"0000B9",
+--X"20005A",
+--X"46F400",
+--X"000000",
+--X"57F400",
+--X"000000",
+--X"0000B9",
+--X"20005A",
+-- OR end
+
+-- NOT begin
+--X"46F400",
+--X"000FFF",
+--X"57F400",
+--X"7F00FF",
+--X"0000B9",
+--X"20001F",
+--X"46F400",
+--X"000000",
+--X"57F400",
+--X"FFFFFF",
+--X"0000B9",
+--X"20001F",
+-- NOT end
+
+-- ASL begin
+--X"20001B",
+--X"51F400",
+--X"0000A5",
+--X"55F400",
+--X"0000A5",
+--X"53F400",
+--X"0000A5",
+--X"0000B9",
+--X"20003A",
+-- ASL end
+
+-- ASR begin
+--X"20001B",
+--X"51F400",
+--X"0000A5",
+--X"55F400",
+--X"0000A5",
+--X"53F400",
+--X"0000A5",
+--X"0000B9",
+--X"20002A",
+-- ASR end
+
+-- CLR begin
+--X"0000B9",
+--X"56F400",
+--X"200000",
+--X"200013",
+--X"56F400",
+--X"E00000",
+--X"0000B9",
+--X"0001F9",
+--X"200013",
+-- CLR end
+
+-- CMP begin
+--X"2F2000",
+--X"262400",
+--X"0000B9",
+--X"20005D",
+--X"2F2000",
+--X"262000",
+--X"0000B9",
+--X"20005D",
+--X"2F2400",
+--X"262000",
+--X"0000B9",
+--X"20005D",
+--X"57F400",
+--X"800AAA",
+--X"262000",
+--X"0000B9",
+--X"20005D",
+--X"46F400",
+--X"800AAA",
+--X"2F2000",
+--X"0000B9",
+--X"20005D",
+-- CMP end
+
+-- CMPM begin
+--X"2F2000",
+--X"262400",
+--X"0000B9",
+--X"20005F",
+--X"2F2000",
+--X"262000",
+--X"0000B9",
+--X"20005F",
+--X"2F2400",
+--X"262000",
+--X"0000B9",
+--X"20005F",
+--X"57F400",
+--X"800AAA",
+--X"262000",
+--X"0000B9",
+--X"20005F",
+--X"46F400",
+--X"800AAA",
+--X"2F2000",
+--X"0000B9",
+--X"20005F",
+-- CMPM end
+
+-- DIV begin
+--X"00FEB9",
+--X"44F400",
+--X"600000",
+--X"56F400",
+--X"200000",
+--X"0618A0",
+--X"018040",
+--X"210E00",
+-- DIV end
+
+-- LSL begin
+--X"0000B9",
+--X"56F400",
+--X"200000",
+--X"56F400",
+--X"AAAAAA",
+--X"50F400",
+--X"BCDEFA",
+--X"0618A0",
+--X"200033",
+-- LSL end
+
+-- LSR begin
+--X"0000B9",
+--X"56F400",
+--X"200000",
+--X"56F400",
+--X"AAAAAA",
+--X"50F400",
+--X"BCDEFA",
+--X"0618A0",
+--X"200023",
+-- LSR end
+
+-- MPY begin
+--X"0000B9",
+--X"44F400",
+--X"200000",
+--X"46F400",
+--X"400000",
+--X"2000D0",
+--X"44F400",
+--X"E00000",
+--X"46F400",
+--X"B9999A",
+--X"2000D0",
+--X"44F400",
+--X"E66666",
+--X"46F400",
+--X"466666",
+--X"2000D0",
+--X"44F400",
+--X"E66666",
+--X"46F400",
+--X"466666",
+--X"2000D4",
+-- MPY end
+
+-- MAC begin
+--X"0000B9",
+--X"200013",
+--X"2A8000",
+--X"44F400",
+--X"200000",
+--X"46F400",
+--X"400000",
+--X"2000D6",
+--X"44F400",
+--X"E00000",
+--X"46F400",
+--X"B9999A",
+--X"2000D2",
+--X"44F400",
+--X"E66666",
+--X"46F400",
+--X"466666",
+--X"2000D2",
+--X"44F400",
+--X"E66666",
+--X"46F400",
+--X"466666",
+--X"2000D6",
+-- MAC end
+
+-- MACR begin
+--X"0000B9",
+--X"200013",
+--X"2E1000",
+--X"44F400",
+--X"123456",
+--X"46F400",
+--X"123456",
+--X"2000D3",
+--X"56F400",
+--X"100001",
+--X"44F400",
+--X"123456",
+--X"46F400",
+--X"123456",
+--X"2000D3",
+--X"2E1000",
+--X"50F400",
+--X"800000",
+--X"44F400",
+--X"123456",
+--X"46F400",
+--X"123456",
+--X"2000D3",
+-- MACR end
+
+-- MPYR begin
+--X"0000B9",
+--X"46F400",
+--X"654321",
+--X"200095",
+-- MPYR end
+
+-- NEG begin
+--X"0000B9",
+--X"56F400",
+--X"654321",
+--X"200036",
+--X"200013",
+--X"52F400",
+--X"000080",
+--X"200036",
+--X"56F400",
+--X"800000",
+--X"200036",
+-- NEG end
+
+-- NORM begin
+--X"200013",
+--X"2C0100",
+--X"200003",
+--X"062FA0",
+--X"01DB15",
+--X"200013",
+--X"2EFF00",
+--X"2A8400",
+--X"200003",
+--X"062FA0",
+--X"01D915",
+--X"200013",
+--X"062FA0",
+--X"01DA15",
+-- NORM end
+
+-- RND begin
+--X"0000B9",
+--X"54F400",
+--X"123456",
+--X"50F400",
+--X"789ABC",
+--X"200011",
+--X"54F400",
+--X"123456",
+--X"50F400",
+--X"800000",
+--X"200011",
+--X"54F400",
+--X"123455",
+--X"50F400",
+--X"800000",
+--X"200011",
+-- RND end
+
+-- ROR begin
+--X"0000B9",
+--X"56F400",
+--X"AAAAAA",
+--X"50F400",
+--X"BCDEFA",
+--X"0618A0",
+--X"200027",
+-- ROR end
+
+-- ROL begin
+--X"0000B9",
+--X"56F400",
+--X"AAAAAA",
+--X"50F400",
+--X"BCDEFA",
+--X"0618A0",
+--X"200037",
+-- ROL end
+
+
+-- SUB begin
+--X"46F400",
+--X"000000",
+--X"47F400",
+--X"000001",
+--X"20001B",
+--X"51F400",
+--X"000001",
+--X"0000B9",
+--X"0001F9",
+--X"20003C",
+--X"47F400",
+--X"800000",
+--X"53F400",
+--X"000080",
+--X"20003C",
+--X"20001B",
+--X"53F400",
+--X"000080",
+--X"47F400",
+--X"000001",
+--X"20007C",
+-- SUB end
+
+-- SUBL begin
+--X"50F400",
+--X"000000",
+--X"54F400",
+--X"000001",
+--X"20001B",
+--X"51F400",
+--X"000001",
+--X"0000B9",
+--X"0001F9",
+--X"20001E",
+--X"54F400",
+--X"800000",
+--X"53F400",
+--X"000080",
+--X"20001E",
+--X"20001B",
+--X"53F400",
+--X"000080",
+--X"54F400",
+--X"000001",
+--X"20001E",
+-- SUBL end
+
+-- SUBR begin
+--X"50F400",
+--X"000000",
+--X"54F400",
+--X"000001",
+--X"20001B",
+--X"51F400",
+--X"000001",
+--X"0000B9",
+--X"0001F9",
+--X"20000E",
+--X"54F400",
+--X"800000",
+--X"53F400",
+--X"000080",
+--X"20000E",
+--X"20001B",
+--X"53F400",
+--X"000080",
+--X"54F400",
+--X"000001",
+--X"20000E",
+-- SUBR end
+
+-- SBC begin
+--X"46F400",
+--X"000000",
+--X"47F400",
+--X"000001",
+--X"20001B",
+--X"51F400",
+--X"000001",
+--X"0000B9",
+--X"0001F9",
+--X"20003D",
+--X"47F400",
+--X"800000",
+--X"53F400",
+--X"000080",
+--X"20003D",
+--X"20001B",
+--X"53F400",
+--X"000080",
+--X"47F400",
+--X"000001",
+--X"20003D",
+-- SBC end
+
+-- TCC begin
+--X"311400",
+--X"44F400",
+--X"ABCDEF",
+--X"57F400",
+--X"123456",
+--X"0000B9",
+--X"038143",
+--X"03014A",
+--X"0004F9",
+--X"03A143",
+--X"03214A",
+-- TCC end
+
+-- TFR begin
+--X"56F400",
+--X"ABCDEF",
+--X"57F400",
+--X"123456",
+--X"21EE09",
+--X"44F400",
+--X"555555",
+--X"47F400",
+--X"AAAAAA",
+--X"21C441",
+--X"21E679",
+-- TFR end
+
+-- TST begin
+--X"20001B",
+--X"20000B",
+--X"0000B9",
+--X"0001F9",
+--X"53F400",
+--X"000080",
+--X"20000B",
+--X"53F400",
+--X"00007F",
+--X"20000B",
+-- TST end
+
+
+--X"2AFF00",
+--X"54F400",
+--X"FFFFFF",
+--X"50F400",
+--X"FFFFF2",
+--X"200026",
+--X"000000",
+--X"000000",
+--X"000000",
+--X"000000",
+--X"000000",
+--X"000000",
+--X"000000",
+--X"000000",
+--X"000000",
+--X"000000",
+X"000000",
+X"000000",
+X"000000",
+X"000000",
+X"000000",
+X"000000",
+X"000000",
+X"000000",
+X"000000",
+--X"44F400",
+--X"100010",
+--X"45F400",
+--X"100011",
+--X"0B5880",
+--X"000017",
+--X"46F400",
+--X"100026",
+--X"47F400",
+--X"100027",
+--X"425800",
+--X"435800",
+--X"420A00",
+--X"431F00",
+--X"437000",
+--X"0000A0",
+--X"427000",
+--X"00004F",
+--  X"42F800",
+--  X"43F800",
+--  X"428A00",
+--  X"439F00",
+--	"001100000100100000000000",  -- 0 move #72,r0
+--	"001110000000100000000000",  -- 1 move #8,n0
+--	"000001010000000010100000",  -- 2 move #0,m0
+--	"000001010001000010100001",  -- 3 move #16,m1
+--	"000001101110000100100000",  -- 4 rep m1
+--	"010001001100100000000000",  -- 5 move x:(r0)+n0,x0
+--	"000000000000000000000000",  -- 6
+--	"000000000000000000000000",  -- 7
+--	"000000000000000000000000",  -- 8
+--	"000000000000000000000000",  -- 9 
+--	"000000000000000000000000",  -- 10
+--	"000000000000000000000000",  -- 11
+--	"000000000000000000000000",  -- 12
+--	"000000000000000000000000",  -- 13
+--	"000000000000000000000000",  -- 14
+--	"000000000000000000000000",  -- 15
+--	"000000000000000000000000",  -- 16
+--	"000000000000000000000000",  -- 17
+--	"000000000000000000000000",  -- 18
+--	"000000000000000000000000",  -- 19
+--	"000010101101101010000000",  -- 20 -- JMP (r2)+
+--	"000000000000000000000000",  -- 20
+--	"000000000000000000000000",  -- 21
+--	"000000000000000000000000",  -- 22
+	"000000000000000000000000",  -- 23
+	"000000000000000000000000",  -- 24
+	"000000000000000000000000",  -- 25
+	"000000000000000000000000",  -- 26
+	"000000000000000000000000",  -- 27
+	"000000000000000000000000",  -- 28
+	"000000000000000000000000",  -- 29
+	"000000000000000000000000",  -- 30
+	"000000000000000000000000",  -- 31
+--	"000000000000000000000000",  -- 32
+--	"000011010000000000000000",  -- 32 -- JSR #0
+	"000010111111000010000000",  -- 32 -- JSR absolute
+	"000000000000000001000000",  -- 33 -- #64
+	"000000000000000000000000",  -- 34
+	"000000000000000000000000",  -- 35
+	"000000000000000000000000",  -- 36
+	"000000000000000000000000",  -- 37
+	"000000000000000000000000",  -- 38
+	"000000000000000000000000",  -- 39
+	"000000000000000000000000",  -- 40
+	"000000000000000000000000",  -- 41
+	"000000000000000000000000",  -- 42
+	"000000000000000000000000",  -- 43
+	"000000000000000000000000",  -- 44
+	"000000000000000000000000",  -- 45
+	"000000000000000000000000",  -- 46
+	"000000000000000000000000",  -- 47
+	"000000000000000000000000",  -- 48
+	"000000000000000000000000",  -- 49
+	"000000000000000000000000",  -- 50
+	"000000000000000000000000",  -- 51
+	"000000000000000000000000",  -- 52
+	"000000000000000000000000",  -- 53
+	"000000000000000000000000",  -- 54
+	"000000000000000000000000",  -- 55
+	"000000000000000000000000",  -- 56
+	"000000000000000000000000",  -- 57
+	"000000000000000000000000",  -- 58
+	"000000000000000000000000",  -- 59
+	"000000000000000000000000",  -- 60
+	"000000000000000000000000",  -- 61
+	"000000000000000000000000",  -- 62
+	"000000000000000000000000",  -- 63
+	"000000000000000000000000",  -- 64
+	"000000000000000000000000",  -- 65
+	"000000000000000000000000",  -- 66
+	"000000000000000000000000",  -- 67
+	"000000000000000000000000",  -- 68
+	"000000000000000000000000",  -- 69
+	"000000000000000000000100",  -- 70 -- RTI
+	"000000000000000000000000",  -- 71
+	"000000000000000000000000",  -- 72
+	"000000000000000000000000",  -- 73
+	"000000000000000000000000",  -- 74
+	"000000000000000000000000",  -- 75
+	"000000000000000000000000",  -- 76
+	"000000000000000000000000",  -- 77
+	"000000000000000000000000",  -- 78
+	"000000000000000000000000",  -- 79
+	"000000000000000000000000",  -- 80
+	"000000000000000000000000",  -- 81
+	"000000000000000000000000",  -- 82
+	"000000000000000000000000",  -- 83
+	"000000000000000000000000",  -- 84
+	"000000000000000000000000",  -- 85
+	"000000000000000000000000",  -- 86
+	"000000000000000000000000",  -- 87
+	"000000000000000000000000",  -- 88
+	"000000000000000000000000",  -- 89
+	"000000000000000000000000",  -- 90
+	"000000000000000000000000",  -- 91
+	"000000000000000000000000",  -- 92
+	"000000000000000000000000",  -- 93
+	"000000000000000000000000",  -- 94
+	"000000000000000000000000",  -- 95
+	"000000000000000000000000",  -- 96
+	"000000000000000000000000",  -- 97
+	"000000000000000000000000",  -- 98
+	"000000000000000000000000",  -- 99
+	"000000000000000000000000",  -- 100
+	"000000000000000000000000",  -- 101
+	"000000000000000000000000",  -- 102
+	"000000000000000000000000",  -- 103
+	"000000000000000000000000",  -- 104
+	"000000000000000000000000",  -- 105
+	"000000000000000000000000",  -- 106
+	"000000000000000000000000",  -- 107
+	"000000000000000000000000",  -- 108
+	"000000000000000000000000",  -- 109
+	"000000000000000000000000",  -- 110
+	"000000000000000000000000",  -- 111
+	"000000000000000000000000",  -- 112
+	"000000000000000000000000",  -- 113
+	"000000000000000000000000",  -- 114
+	"000000000000000000000000",  -- 115
+	"000000000000000000000000",  -- 116
+	"000000000000000000000000",  -- 117
+	"000000000000000000000000",  -- 118
+	"000000000000000000000000",  -- 119
+	"000000000000000000000000",  -- 120
+	"000000000000000000000000",  -- 121
+	"000000000000000000000000",  -- 122
+	"000000000000000000000000",  -- 123
+	"000000000000000000000000",  -- 124
+	"000000000000000000000000",  -- 125
+	"000000000000000000000000",  -- 126
+	"000000000000000000000000",  -- 127
+	"000000000000000000000000",  -- 128
+	"000000000000000000000000",  -- 129
+	"000000000000000000000000",  -- 130
+	"000000000000000000000000",  -- 131
+	"000000000000000000000000",  -- 132
+	"000000000000000000000000",  -- 133
+	"000000000000000000000000",  -- 134
+	"000000000000000000000000",  -- 135
+	"000000000000000000000000",  -- 136
+	"000000000000000000000000",  -- 137
+	"000000000000000000000000",  -- 138
+	"000000000000000000000000",  -- 139
+	"000000000000000000000000",  -- 140
+	"000000000000000000000000",  -- 141
+	"000000000000000000000000",  -- 142
+	"000000000000000000000000",  -- 143
+	"000000000000000000000000",  -- 144
+	"000000000000000000000000",  -- 145
+	"000000000000000000000000",  -- 146
+	"000000000000000000000000",  -- 147
+	"000000000000000000000000",  -- 148
+	"000000000000000000000000",  -- 149
+	"000000000000000000000000",  -- 150
+	"000000000000000000000000",  -- 151
+	"000000000000000000000000",  -- 152
+	"000000000000000000000000",  -- 153
+	"000000000000000000000000",  -- 154
+	"000000000000000000000000",  -- 155
+	"000000000000000000000000",  -- 156
+	"000000000000000000000000",  -- 157
+	"000000000000000000000000",  -- 158
+	"000000000000000000000000",  -- 159
+	"000000000000000000000000",  -- 160
+	"000000000000000000000000",  -- 161
+	"000000000000000000000000",  -- 162
+	"000000000000000000000000",  -- 163
+	"000000000000000000000000",  -- 164
+	"000000000000000000000000",  -- 165
+	"000000000000000000000000",  -- 166
+	"000000000000000000000000",  -- 167
+	"000000000000000000000000",  -- 168
+	"000000000000000000000000",  -- 169
+	"000000000000000000000000",  -- 170
+	"000000000000000000000000",  -- 171
+	"000000000000000000000000",  -- 172
+	"000000000000000000000000",  -- 173
+	"000000000000000000000000",  -- 174
+	"000000000000000000000000",  -- 175
+	"000000000000000000000000",  -- 176
+	"000000000000000000000000",  -- 177
+	"000000000000000000000000",  -- 178
+	"000000000000000000000000",  -- 179
+	"000000000000000000000000",  -- 180
+	"000000000000000000000000",  -- 181
+	"000000000000000000000000",  -- 182
+	"000000000000000000000000",  -- 183
+	"000000000000000000000000",  -- 184
+	"000000000000000000000000",  -- 185
+	"000000000000000000000000",  -- 186
+	"000000000000000000000000",  -- 187
+	"000000000000000000000000",  -- 188
+	"000000000000000000000000",  -- 189
+	"000000000000000000000000",  -- 190
+	"000000000000000000000000",  -- 191
+	"000000000000000000000000",  -- 192
+	"000000000000000000000000",  -- 193
+	"000000000000000000000000",  -- 194
+	"000000000000000000000000",  -- 195
+	"000000000000000000000000",  -- 196
+	"000000000000000000000000",  -- 197
+	"000000000000000000000000",  -- 198
+	"000000000000000000000000",  -- 199
+	"000000000000000000000000",  -- 200
+	"000000000000000000000000",  -- 201
+	"000000000000000000000000",  -- 202
+	"000000000000000000000000",  -- 203
+	"000000000000000000000000",  -- 204
+	"000000000000000000000000",  -- 205
+	"000000000000000000000000",  -- 206
+	"000000000000000000000000",  -- 207
+	"000000000000000000000000",  -- 208
+	"000000000000000000000000",  -- 209
+	"000000000000000000000000",  -- 210
+	"000000000000000000000000",  -- 211
+	"000000000000000000000000",  -- 212
+	"000000000000000000000000",  -- 213
+	"000000000000000000000000",  -- 214
+	"000000000000000000000000",  -- 215
+	"000000000000000000000000",  -- 216
+	"000000000000000000000000",  -- 217
+	"000000000000000000000000",  -- 218
+	"000000000000000000000000",  -- 219
+	"000000000000000000000000",  -- 220
+	"000000000000000000000000",  -- 221
+	"000000000000000000000000",  -- 222
+	"000000000000000000000000",  -- 223
+	"000000000000000000000000",  -- 224
+	"000000000000000000000000",  -- 225
+	"000000000000000000000000",  -- 226
+	"000000000000000000000000",  -- 227
+	"000000000000000000000000",  -- 228
+	"000000000000000000000000",  -- 229
+	"000000000000000000000000",  -- 230
+	"000000000000000000000000",  -- 231
+	"000000000000000000000000",  -- 232
+	"000000000000000000000000",  -- 233
+	"000000000000000000000000",  -- 234
+	"000000000000000000000000",  -- 235
+	"000000000000000000000000",  -- 236
+	"000000000000000000000000",  -- 237
+	"000000000000000000000000",  -- 238
+	"000000000000000000000000",  -- 239
+	"000000000000000000000000",  -- 240
+	"000000000000000000000000",  -- 241
+	"000000000000000000000000",  -- 242
+	"000000000000000000000000",  -- 243
+	"000000000000000000000000",  -- 244
+	"000000000000000000000000",  -- 245
+	"000000000000000000000000",  -- 246
+	"000000000000000000000000",  -- 247
+	"000000000000000000000000",  -- 248
+	"000000000000000000000000",  -- 249
+	"000000000000000000000000",  -- 250
+	"000000000000000000000000",  -- 251
+	"000000000000000000000000",  -- 252
+	"000000000000000000000000",  -- 253
+	"000000000000000000000000",  -- 254
+	"000000000000000000000000");  -- 255
+	signal int_xmem : int_mem_type := (
+--						when "11------10000000" => instr_array(JMP_INSTR)  <= '1';
+--	"000000000000111011111001",  -- 0 -- ORI #$0E, CCR
+	"000000000000000000001100",  -- 0 -- REP
+	"000000000000000000000101",  -- 1 -- ORI #$0E, MR
+	"000000000000111011111010",  -- 2 -- ORI #$0E, OMR
+	"000000000000100010111010",  -- 3 -- ANDI #$08, OMR
+--	"000010101111000010000000",  -- 1 -- JMP absolute
+--	"000000000000000000011111",  -- 2 -- #31
+--	"000011000000000000010000",  -- 3 -- JMP #16
+	"000000000000000000000000",  -- 4
+	"000000000000000000000000",  -- 5
+	"000000000000000000000000",  -- 6
+	"000000000000000000000000",  -- 7
+	"000000000000000000000000",  -- 8
+	"000000000000000000000000",  -- 9
+	"000000000000000000000000",  -- 10
+	"000000000000000000000000",  -- 11
+	"000000000000000000000000",  -- 12
+	"000000000000000000000000",  -- 13
+	"000000000000000000000000",  -- 14
+	"000000000000000000000000",  -- 15
+	"000000000000000000000000",  -- 16
+--	"000000000000000000000000",  -- 17
+	"000010101101010110100000",  -- 17 -- JCC (r5)-
+	"000000000000000000000000",  -- 18
+	"000000000000000000000000",  -- 19
+	"000010101101101010000000",  -- 20 -- JMP (r2)+
+	"000000000000000000000000",  -- 21
+	"000000000000000000000000",  -- 22
+	"000000000000000000000000",  -- 23
+	"000000000000000000000000",  -- 24
+	"000000000000000000000000",  -- 25
+	"000000000000000000000000",  -- 26
+	"000000000000000000000000",  -- 27
+	"000000000000000000000000",  -- 28
+	"000000000000000000000000",  -- 29
+	"000000000000000000000000",  -- 30
+	"000000000000000000000000",  -- 31
+--	"000000000000000000000000",  -- 32
+--	"000011010000000000000000",  -- 32 -- JSR #0
+	"000010111111000010000000",  -- 32 -- JSR absolute
+	"000000000000000001000000",  -- 33 -- #64
+	"000000000000000000000000",  -- 34
+	"000000000000000000000000",  -- 35
+	"000000000000000000000000",  -- 36
+	"000000000000000000000000",  -- 37
+	"000000000000000000000000",  -- 38
+	"000000000000000000000000",  -- 39
+	"000000000000000000000000",  -- 40
+	"000000000000000000000000",  -- 41
+	"000000000000000000000000",  -- 42
+	"000000000000000000000000",  -- 43
+	"000000000000000000000000",  -- 44
+	"000000000000000000000000",  -- 45
+	"000000000000000000000000",  -- 46
+	"000000000000000000000000",  -- 47
+	"000000000000000000000000",  -- 48
+	"000000000000000000000000",  -- 49
+	"000000000000000000000000",  -- 50
+	"000000000000000000000000",  -- 51
+	"000000000000000000000000",  -- 52
+	"000000000000000000000000",  -- 53
+	"000000000000000000000000",  -- 54
+	"000000000000000000000000",  -- 55
+	"000000000000000000000000",  -- 56
+	"000000000000000000000000",  -- 57
+	"000000000000000000000000",  -- 58
+	"000000000000000000000000",  -- 59
+	"000000000000000000000000",  -- 60
+	"000000000000000000000000",  -- 61
+	"000000000000000000000000",  -- 62
+	"000000000000000000000000",  -- 63
+	"000000000000000000000000",  -- 64
+	"000000000000000000000000",  -- 65
+	"000000000000000000000000",  -- 66
+	"000000000000000000000000",  -- 67
+	"000000000000000000000000",  -- 68
+	"000000000000000000000000",  -- 69
+	"000000000000000000000100",  -- 70 -- RTI
+	"000000000000000000000000",  -- 71
+	"000000000000000000000000",  -- 72
+	"000000000000000000000000",  -- 73
+	"000000000000000000000000",  -- 74
+	"000000000000000000000000",  -- 75
+	"000000000000000000000000",  -- 76
+	"000000000000000000000000",  -- 77
+	"000000000000000000000000",  -- 78
+	"000000000000000000000000",  -- 79
+	"000000000000000000000000",  -- 80
+	"000000000000000000000000",  -- 81
+	"000000000000000000000000",  -- 82
+	"000000000000000000000000",  -- 83
+	"000000000000000000000000",  -- 84
+	"000000000000000000000000",  -- 85
+	"000000000000000000000000",  -- 86
+	"000000000000000000000000",  -- 87
+	"000000000000000000000000",  -- 88
+	"000000000000000000000000",  -- 89
+	"000000000000000000000000",  -- 90
+	"000000000000000000000000",  -- 91
+	"000000000000000000000000",  -- 92
+	"000000000000000000000000",  -- 93
+	"000000000000000000000000",  -- 94
+	"000000000000000000000000",  -- 95
+	"000000000000000000000000",  -- 96
+	"000000000000000000000000",  -- 97
+	"000000000000000000000000",  -- 98
+	"000000000000000000000000",  -- 99
+	"000000000000000000000000",  -- 100
+	"000000000000000000000000",  -- 101
+	"000000000000000000000000",  -- 102
+	"000000000000000000000000",  -- 103
+	"000000000000000000000000",  -- 104
+	"000000000000000000000000",  -- 105
+	"000000000000000000000000",  -- 106
+	"000000000000000000000000",  -- 107
+	"000000000000000000000000",  -- 108
+	"000000000000000000000000",  -- 109
+	"000000000000000000000000",  -- 110
+	"000000000000000000000000",  -- 111
+	"000000000000000000000000",  -- 112
+	"000000000000000000000000",  -- 113
+	"000000000000000000000000",  -- 114
+	"000000000000000000000000",  -- 115
+	"000000000000000000000000",  -- 116
+	"000000000000000000000000",  -- 117
+	"000000000000000000000000",  -- 118
+	"000000000000000000000000",  -- 119
+	"000000000000000000000000",  -- 120
+	"000000000000000000000000",  -- 121
+	"000000000000000000000000",  -- 122
+	"000000000000000000000000",  -- 123
+	"000000000000000000000000",  -- 124
+	"000000000000000000000000",  -- 125
+	"000000000000000000000000",  -- 126
+	"000000000000000000000000",  -- 127
+	"000000000000000000000000",  -- 128
+	"000000000000000000000000",  -- 129
+	"000000000000000000000000",  -- 130
+	"000000000000000000000000",  -- 131
+	"000000000000000000000000",  -- 132
+	"000000000000000000000000",  -- 133
+	"000000000000000000000000",  -- 134
+	"000000000000000000000000",  -- 135
+	"000000000000000000000000",  -- 136
+	"000000000000000000000000",  -- 137
+	"000000000000000000000000",  -- 138
+	"000000000000000000000000",  -- 139
+	"000000000000000000000000",  -- 140
+	"000000000000000000000000",  -- 141
+	"000000000000000000000000",  -- 142
+	"000000000000000000000000",  -- 143
+	"000000000000000000000000",  -- 144
+	"000000000000000000000000",  -- 145
+	"000000000000000000000000",  -- 146
+	"000000000000000000000000",  -- 147
+	"000000000000000000000000",  -- 148
+	"000000000000000000000000",  -- 149
+	"000000000000000000000000",  -- 150
+	"000000000000000000000000",  -- 151
+	"000000000000000000000000",  -- 152
+	"000000000000000000000000",  -- 153
+	"000000000000000000000000",  -- 154
+	"000000000000000000000000",  -- 155
+	"000000000000000000000000",  -- 156
+	"000000000000000000000000",  -- 157
+	"000000000000000000000000",  -- 158
+	"000000000000000000000000",  -- 159
+	"000000000000000000000000",  -- 160
+	"000000000000000000000000",  -- 161
+	"000000000000000000000000",  -- 162
+	"000000000000000000000000",  -- 163
+	"000000000000000000000000",  -- 164
+	"000000000000000000000000",  -- 165
+	"000000000000000000000000",  -- 166
+	"000000000000000000000000",  -- 167
+	"000000000000000000000000",  -- 168
+	"000000000000000000000000",  -- 169
+	"000000000000000000000000",  -- 170
+	"000000000000000000000000",  -- 171
+	"000000000000000000000000",  -- 172
+	"000000000000000000000000",  -- 173
+	"000000000000000000000000",  -- 174
+	"000000000000000000000000",  -- 175
+	"000000000000000000000000",  -- 176
+	"000000000000000000000000",  -- 177
+	"000000000000000000000000",  -- 178
+	"000000000000000000000000",  -- 179
+	"000000000000000000000000",  -- 180
+	"000000000000000000000000",  -- 181
+	"000000000000000000000000",  -- 182
+	"000000000000000000000000",  -- 183
+	"000000000000000000000000",  -- 184
+	"000000000000000000000000",  -- 185
+	"000000000000000000000000",  -- 186
+	"000000000000000000000000",  -- 187
+	"000000000000000000000000",  -- 188
+	"000000000000000000000000",  -- 189
+	"000000000000000000000000",  -- 190
+	"000000000000000000000000",  -- 191
+	"000000000000000000000000",  -- 192
+	"000000000000000000000000",  -- 193
+	"000000000000000000000000",  -- 194
+	"000000000000000000000000",  -- 195
+	"000000000000000000000000",  -- 196
+	"000000000000000000000000",  -- 197
+	"000000000000000000000000",  -- 198
+	"000000000000000000000000",  -- 199
+	"000000000000000000000000",  -- 200
+	"000000000000000000000000",  -- 201
+	"000000000000000000000000",  -- 202
+	"000000000000000000000000",  -- 203
+	"000000000000000000000000",  -- 204
+	"000000000000000000000000",  -- 205
+	"000000000000000000000000",  -- 206
+	"000000000000000000000000",  -- 207
+	"000000000000000000000000",  -- 208
+	"000000000000000000000000",  -- 209
+	"000000000000000000000000",  -- 210
+	"000000000000000000000000",  -- 211
+	"000000000000000000000000",  -- 212
+	"000000000000000000000000",  -- 213
+	"000000000000000000000000",  -- 214
+	"000000000000000000000000",  -- 215
+	"000000000000000000000000",  -- 216
+	"000000000000000000000000",  -- 217
+	"000000000000000000000000",  -- 218
+	"000000000000000000000000",  -- 219
+	"000000000000000000000000",  -- 220
+	"000000000000000000000000",  -- 221
+	"000000000000000000000000",  -- 222
+	"000000000000000000000000",  -- 223
+	"000000000000000000000000",  -- 224
+	"000000000000000000000000",  -- 225
+	"000000000000000000000000",  -- 226
+	"000000000000000000000000",  -- 227
+	"000000000000000000000000",  -- 228
+	"000000000000000000000000",  -- 229
+	"000000000000000000000000",  -- 230
+	"000000000000000000000000",  -- 231
+	"000000000000000000000000",  -- 232
+	"000000000000000000000000",  -- 233
+	"000000000000000000000000",  -- 234
+	"000000000000000000000000",  -- 235
+	"000000000000000000000000",  -- 236
+	"000000000000000000000000",  -- 237
+	"000000000000000000000000",  -- 238
+	"000000000000000000000000",  -- 239
+	"000000000000000000000000",  -- 240
+	"000000000000000000000000",  -- 241
+	"000000000000000000000000",  -- 242
+	"000000000000000000000000",  -- 243
+	"000000000000000000000000",  -- 244
+	"000000000000000000000000",  -- 245
+	"000000000000000000000000",  -- 246
+	"000000000000000000000000",  -- 247
+	"000000000000000000000000",  -- 248
+	"000000000000000000000000",  -- 249
+	"000000000000000000000000",  -- 250
+	"000000000000000000000000",  -- 251
+	"000000000000000000000000",  -- 252
+	"000000000000000000000000",  -- 253
+	"000000000000000000000000",  -- 254
+	"000000000000000000000000");  -- 255
+	signal int_ymem : int_mem_type := (
+--						when "11------10000000" => instr_array(JMP_INSTR)  <= '1';
+--	"000000000000111011111001",  -- 0 -- ORI #$0E, CCR
+	"000000000000000000000001",  -- 0 -- REP
+	"000000000000000000000010",  -- 1 -- ORI #$0E, MR
+	"000000000000000000000011",  -- 2 -- ORI #$0E, OMR
+	"000000000000000000000100",  -- 3 -- ANDI #$08, OMR
+--	"000010101111000010000000",  -- 1 -- JMP absolute
+--	"000000000000000000011111",  -- 2 -- #31
+--	"000011000000000000010000",  -- 3 -- JMP #16
+	"000000000000000000000101",  -- 4
+	"000000000000000000000110",  -- 5
+	"000000000000000000000111",  -- 6
+	"000000000000000000001000",  -- 7
+	"000000000000000000001001",  -- 8
+	"000000000000000000001010",  -- 9
+	"000000000000000000001011",  -- 10
+	"000000000000000000001100",  -- 11
+	"000000000000000000001101",  -- 12
+	"000000000000000000001110",  -- 13
+	"000000000000000000001111",  -- 14
+	"000000000000000000010000",  -- 15
+	"000000000000000000010001",  -- 16
+--	"000000000000000000000000",  -- 17
+	"000010101101010110100000",  -- 17 -- JCC (r5)-
+	"000000000000000000000000",  -- 18
+	"000000000000000000000000",  -- 19
+	"000010101101101010000000",  -- 20 -- JMP (r2)+
+	"000000000000000000000000",  -- 21
+	"000000000000000000000000",  -- 22
+	"000000000000000000000000",  -- 23
+	"000000000000000000000000",  -- 24
+	"000000000000000000000000",  -- 25
+	"000000000000000000000000",  -- 26
+	"000000000000000000000000",  -- 27
+	"000000000000000000000000",  -- 28
+	"000000000000000000000000",  -- 29
+	"000000000000000000000000",  -- 30
+	"000000000000000000000000",  -- 31
+--	"000000000000000000000000",  -- 32
+--	"000011010000000000000000",  -- 32 -- JSR #0
+	"000010111111000010000000",  -- 32 -- JSR absolute
+	"000000000000000001000000",  -- 33 -- #64
+	"000000000000000000000000",  -- 34
+	"000000000000000000000000",  -- 35
+	"000000000000000000000000",  -- 36
+	"000000000000000000000000",  -- 37
+	"000000000000000000000000",  -- 38
+	"000000000000000000000000",  -- 39
+	"000000000000000000000000",  -- 40
+	"000000000000000000000000",  -- 41
+	"000000000000000000000000",  -- 42
+	"000000000000000000000000",  -- 43
+	"000000000000000000000000",  -- 44
+	"000000000000000000000000",  -- 45
+	"000000000000000000000000",  -- 46
+	"000000000000000000000000",  -- 47
+	"000000000000000000000000",  -- 48
+	"000000000000000000000000",  -- 49
+	"000000000000000000000000",  -- 50
+	"000000000000000000000000",  -- 51
+	"000000000000000000000000",  -- 52
+	"000000000000000000000000",  -- 53
+	"000000000000000000000000",  -- 54
+	"000000000000000000000000",  -- 55
+	"000000000000000000000000",  -- 56
+	"000000000000000000000000",  -- 57
+	"000000000000000000000000",  -- 58
+	"000000000000000000000000",  -- 59
+	"000000000000000000000000",  -- 60
+	"000000000000000000000000",  -- 61
+	"000000000000000000000000",  -- 62
+	"000000000000000000000000",  -- 63
+	"000000000000000000000000",  -- 64
+	"000000000000000000000000",  -- 65
+	"000000000000000000000000",  -- 66
+	"000000000000000000000000",  -- 67
+	"000000000000000000000000",  -- 68
+	"000000000000000000000000",  -- 69
+	"000000000000000000000100",  -- 70 -- RTI
+	"000000000000000000000000",  -- 71
+	"000000000000000000000000",  -- 72
+	"000000000000000000000000",  -- 73
+	"000000000000000000000000",  -- 74
+	"000000000000000000000000",  -- 75
+	"000000000000000000000000",  -- 76
+	"000000000000000000000000",  -- 77
+	"000000000000000000000000",  -- 78
+	"000000000000000000000000",  -- 79
+	"000000000000000000000000",  -- 80
+	"000000000000000000000000",  -- 81
+	"000000000000000000000000",  -- 82
+	"000000000000000000000000",  -- 83
+	"000000000000000000000000",  -- 84
+	"000000000000000000000000",  -- 85
+	"000000000000000000000000",  -- 86
+	"000000000000000000000000",  -- 87
+	"000000000000000000000000",  -- 88
+	"000000000000000000000000",  -- 89
+	"000000000000000000000000",  -- 90
+	"000000000000000000000000",  -- 91
+	"000000000000000000000000",  -- 92
+	"000000000000000000000000",  -- 93
+	"000000000000000000000000",  -- 94
+	"000000000000000000000000",  -- 95
+	"000000000000000000000000",  -- 96
+	"000000000000000000000000",  -- 97
+	"000000000000000000000000",  -- 98
+	"000000000000000000000000",  -- 99
+	"000000000000000000000000",  -- 100
+	"000000000000000000000000",  -- 101
+	"000000000000000000000000",  -- 102
+	"000000000000000000000000",  -- 103
+	"000000000000000000000000",  -- 104
+	"000000000000000000000000",  -- 105
+	"000000000000000000000000",  -- 106
+	"000000000000000000000000",  -- 107
+	"000000000000000000000000",  -- 108
+	"000000000000000000000000",  -- 109
+	"000000000000000000000000",  -- 110
+	"000000000000000000000000",  -- 111
+	"000000000000000000000000",  -- 112
+	"000000000000000000000000",  -- 113
+	"000000000000000000000000",  -- 114
+	"000000000000000000000000",  -- 115
+	"000000000000000000000000",  -- 116
+	"000000000000000000000000",  -- 117
+	"000000000000000000000000",  -- 118
+	"000000000000000000000000",  -- 119
+	"000000000000000000000000",  -- 120
+	"000000000000000000000000",  -- 121
+	"000000000000000000000000",  -- 122
+	"000000000000000000000000",  -- 123
+	"000000000000000000000000",  -- 124
+	"000000000000000000000000",  -- 125
+	"000000000000000000000000",  -- 126
+	"000000000000000000000000",  -- 127
+	"000000000000000000000000",  -- 128
+	"000000000000000000000000",  -- 129
+	"000000000000000000000000",  -- 130
+	"000000000000000000000000",  -- 131
+	"000000000000000000000000",  -- 132
+	"000000000000000000000000",  -- 133
+	"000000000000000000000000",  -- 134
+	"000000000000000000000000",  -- 135
+	"000000000000000000000000",  -- 136
+	"000000000000000000000000",  -- 137
+	"000000000000000000000000",  -- 138
+	"000000000000000000000000",  -- 139
+	"000000000000000000000000",  -- 140
+	"000000000000000000000000",  -- 141
+	"000000000000000000000000",  -- 142
+	"000000000000000000000000",  -- 143
+	"000000000000000000000000",  -- 144
+	"000000000000000000000000",  -- 145
+	"000000000000000000000000",  -- 146
+	"000000000000000000000000",  -- 147
+	"000000000000000000000000",  -- 148
+	"000000000000000000000000",  -- 149
+	"000000000000000000000000",  -- 150
+	"000000000000000000000000",  -- 151
+	"000000000000000000000000",  -- 152
+	"000000000000000000000000",  -- 153
+	"000000000000000000000000",  -- 154
+	"000000000000000000000000",  -- 155
+	"000000000000000000000000",  -- 156
+	"000000000000000000000000",  -- 157
+	"000000000000000000000000",  -- 158
+	"000000000000000000000000",  -- 159
+	"000000000000000000000000",  -- 160
+	"000000000000000000000000",  -- 161
+	"000000000000000000000000",  -- 162
+	"000000000000000000000000",  -- 163
+	"000000000000000000000000",  -- 164
+	"000000000000000000000000",  -- 165
+	"000000000000000000000000",  -- 166
+	"000000000000000000000000",  -- 167
+	"000000000000000000000000",  -- 168
+	"000000000000000000000000",  -- 169
+	"000000000000000000000000",  -- 170
+	"000000000000000000000000",  -- 171
+	"000000000000000000000000",  -- 172
+	"000000000000000000000000",  -- 173
+	"000000000000000000000000",  -- 174
+	"000000000000000000000000",  -- 175
+	"000000000000000000000000",  -- 176
+	"000000000000000000000000",  -- 177
+	"000000000000000000000000",  -- 178
+	"000000000000000000000000",  -- 179
+	"000000000000000000000000",  -- 180
+	"000000000000000000000000",  -- 181
+	"000000000000000000000000",  -- 182
+	"000000000000000000000000",  -- 183
+	"000000000000000000000000",  -- 184
+	"000000000000000000000000",  -- 185
+	"000000000000000000000000",  -- 186
+	"000000000000000000000000",  -- 187
+	"000000000000000000000000",  -- 188
+	"000000000000000000000000",  -- 189
+	"000000000000000000000000",  -- 190
+	"000000000000000000000000",  -- 191
+	"000000000000000000000000",  -- 192
+	"000000000000000000000000",  -- 193
+	"000000000000000000000000",  -- 194
+	"000000000000000000000000",  -- 195
+	"000000000000000000000000",  -- 196
+	"000000000000000000000000",  -- 197
+	"000000000000000000000000",  -- 198
+	"000000000000000000000000",  -- 199
+	"000000000000000000000000",  -- 200
+	"000000000000000000000000",  -- 201
+	"000000000000000000000000",  -- 202
+	"000000000000000000000000",  -- 203
+	"000000000000000000000000",  -- 204
+	"000000000000000000000000",  -- 205
+	"000000000000000000000000",  -- 206
+	"000000000000000000000000",  -- 207
+	"000000000000000000000000",  -- 208
+	"000000000000000000000000",  -- 209
+	"000000000000000000000000",  -- 210
+	"000000000000000000000000",  -- 211
+	"000000000000000000000000",  -- 212
+	"000000000000000000000000",  -- 213
+	"000000000000000000000000",  -- 214
+	"000000000000000000000000",  -- 215
+	"000000000000000000000000",  -- 216
+	"000000000000000000000000",  -- 217
+	"000000000000000000000000",  -- 218
+	"000000000000000000000000",  -- 219
+	"000000000000000000000000",  -- 220
+	"000000000000000000000000",  -- 221
+	"000000000000000000000000",  -- 222
+	"000000000000000000000000",  -- 223
+	"000000000000000000000000",  -- 224
+	"000000000000000000000000",  -- 225
+	"000000000000000000000000",  -- 226
+	"000000000000000000000000",  -- 227
+	"000000000000000000000000",  -- 228
+	"000000000000000000000000",  -- 229
+	"000000000000000000000000",  -- 230
+	"000000000000000000000000",  -- 231
+	"000000000000000000000000",  -- 232
+	"000000000000000000000000",  -- 233
+	"000000000000000000000000",  -- 234
+	"000000000000000000000000",  -- 235
+	"000000000000000000000000",  -- 236
+	"000000000000000000000000",  -- 237
+	"000000000000000000000000",  -- 238
+	"000000000000000000000000",  -- 239
+	"000000000000000000000000",  -- 240
+	"000000000000000000000000",  -- 241
+	"000000000000000000000000",  -- 242
+	"000000000000000000000000",  -- 243
+	"000000000000000000000000",  -- 244
+	"000000000000000000000000",  -- 245
+	"000000000000000000000000",  -- 246
+	"000000000000000000000000",  -- 247
+	"000000000000000000000000",  -- 248
+	"000000000000000000000000",  -- 249
+	"000000000000000000000000",  -- 250
+	"000000000000000000000000",  -- 251
+	"000000000000000000000000",  -- 252
+	"000000000000000000000000",  -- 253
+	"000000000000000000000000",  -- 254
+	"000000000000000000000000");  -- 255
+
+begin
+
+--	int_mem <= int_pmem when mem_type = P_MEM else
+--	           int_xmem when mem_type = X_MEM else
+--	           int_ymem when mem_type = Y_MEM;
+
+	wr_accomplished <= wr_en;
+
+	PMEM_GEN: if mem_type = P_MEM generate
+		data_out <= int_pmem(to_integer(unsigned(int_mem_rd_addr)));
+		process(clk) is
+		begin
+			if rising_edge(clk) then
+--				if rst = '1' then
+--					data_out_valid <= '0';
+--					int_mem_rd_addr <= (others => '0');
+--				else
+					int_mem_rd_addr <= std_logic_vector(rd_addr(7 downto 0));
+					data_out_valid <= rd_en;
+					if wr_en = '1' then
+							int_pmem(to_integer(wr_addr)) <= data_in;
+					end if;
+--				end if;
+			end if;
+		end process;
+	end generate;
+
+	XMEM_GEN: if mem_type = X_MEM generate
+		data_out <= int_xmem(to_integer(unsigned(int_mem_rd_addr)));
+		process(clk) is
+		begin
+			if rising_edge(clk) then
+--				if rst = '1' then
+--					data_out_valid <= '0';
+--					int_mem_rd_addr <= (others => '0');
+--				else
+					int_mem_rd_addr <= std_logic_vector(rd_addr(7 downto 0));
+					data_out_valid <= rd_en;
+					if wr_en = '1' then
+							int_xmem(to_integer(wr_addr)) <= data_in;
+					end if;
+--				end if;
+			end if;
+		end process;
+	end generate;
+
+	YMEM_GEN: if mem_type = Y_MEM generate
+		data_out <= int_ymem(to_integer(unsigned(int_mem_rd_addr)));
+		process(clk) is
+		begin
+			if rising_edge(clk) then
+--				if rst = '1' then
+--					data_out_valid <= '0';
+--					int_mem_rd_addr <= (others => '0');
+--				else
+					int_mem_rd_addr <= std_logic_vector(rd_addr(7 downto 0));
+					data_out_valid <= rd_en;
+					if wr_en = '1' then
+							int_ymem(to_integer(wr_addr)) <= data_in;
+					end if;
+--				end if;
+			end if;
+		end process;
+	end generate;
+--	process(clk, rst) is
+--	begin
+--		if rising_edge(clk) then
+--			if rst = '1' then
+--				data_out_valid <= '0';
+--				int_mem_rd_addr <= (others => '0');
+--			else
+--				int_mem_rd_addr <= std_logic_vector(rd_addr(7 downto 0));
+--				data_out_valid <= rd_en;
+--				if wr_en = '1' then
+--					if mem_type = P_MEM then
+--						int_pmem(to_integer(wr_addr)) <= data_in;
+--					elsif mem_type = X_MEM then
+--						int_xmem(to_integer(wr_addr)) <= data_in;
+--					elsif mem_type = Y_MEM then
+--						int_ymem(to_integer(wr_addr)) <= data_in;
+--					end if;
+--				end if;
+--			end if;
+--		end if;
+--	end process;
+
+end architecture rtl;
+
diff --git a/FireBee/trunk/vhdl/dsp56k/src/memory_management.vhd b/FireBee/trunk/vhdl/dsp56k/src/memory_management.vhd
new file mode 100644
index 0000000..215fe66
--- /dev/null
+++ b/FireBee/trunk/vhdl/dsp56k/src/memory_management.vhd
@@ -0,0 +1,223 @@
+------------------------------------------------------------------------------
+--! @file
+--! @author Matthias Alles
+--! @date 01/2009
+--! @brief Memory controller
+--!
+--! @details This entity contains the internal memories. These are:
+--!  - pmem
+--!  - xmem
+--!  - ymem
+--!  - ROM tables
+--!  - Bootup code
+--! All memory requests are collected here. Only when they are all finished
+--! the memory_stall-flag is released. External memory accesses are given to
+--! the external interface.
+--!
+------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.parameter_pkg.all;
+use work.types_pkg.all;
+use work.constants_pkg.all;
+
+entity memory_management is port (
+	clk, rst : in std_logic;
+	stall_flags    : in  std_logic_vector(PIPELINE_DEPTH-1 downto 0);
+	memory_stall   : out std_logic;
+	data_rom_enable: in  std_logic;
+	pmem_ctrl_in   : in  mem_ctrl_type_in;
+	pmem_ctrl_out  : out mem_ctrl_type_out;
+	pmem2_ctrl_in  : in  mem_ctrl_type_in;
+	pmem2_ctrl_out : out mem_ctrl_type_out;
+	xmem_ctrl_in   : in  mem_ctrl_type_in;
+	xmem_ctrl_out  : out mem_ctrl_type_out;
+	ymem_ctrl_in   : in  mem_ctrl_type_in;
+	ymem_ctrl_out  : out mem_ctrl_type_out
+);
+end memory_management;
+
+
+architecture rtl of memory_management is
+
+	component mem_control is
+	generic(
+		mem_type : memory_type
+	);
+	port(
+		clk, rst        : in std_logic;
+		rd_addr         : in unsigned(BW_ADDRESS-1 downto 0);
+		rd_en           : in std_logic;
+		data_out        : out std_logic_vector(23 downto 0);
+		data_out_valid  : out std_logic;
+		wr_addr         : in  unsigned(BW_ADDRESS-1 downto 0);
+		wr_en           : in  std_logic;
+		wr_accomplished : out std_logic;
+		data_in         : in  std_logic_vector(23 downto 0)
+	);
+	end component mem_control;
+
+	signal pmem_data_out        : std_logic_vector(23 downto 0);
+	signal pmem_data_out_valid  : std_logic;
+
+	signal pmem_rd_addr   : unsigned(BW_ADDRESS-1 downto 0);
+	signal pmem_rd_en     : std_logic;
+
+	signal xmem_rd_en          : std_logic;
+	signal xmem_data_out       : std_logic_vector(23 downto 0);
+	signal xmem_data_out_valid : std_logic;
+	signal xmem_rd_polling : std_logic;
+
+	signal ymem_rd_en          : std_logic;
+	signal ymem_data_out       : std_logic_vector(23 downto 0);
+	signal ymem_data_out_valid : std_logic;
+	signal ymem_rd_polling : std_logic;
+
+	signal pmem_stall_buffer : std_logic_vector(23 downto 0);
+	signal pmem_stall_buffer_valid : std_logic;
+	signal xmem_stall_buffer : std_logic_vector(23 downto 0);
+	signal ymem_stall_buffer : std_logic_vector(23 downto 0);
+
+	signal stall_flags_d    : std_logic_vector(PIPELINE_DEPTH-1 downto 0);
+
+begin
+
+	-- here it is necessary to store the output of the pmem/xmem/ymem when the pipeline enters a stall
+	-- when the pipeline wakes up, this temporal result is inserted into the pipeline
+	stall_buffer: process(clk) is
+	begin
+		if rising_edge(clk) then
+			if rst = '1' then
+				pmem_stall_buffer <= (others => '0');
+				pmem_stall_buffer_valid <= '0';
+				xmem_stall_buffer <= (others => '0');
+				ymem_stall_buffer <= (others => '0');
+				stall_flags_d <= (others => '0');
+			else
+				stall_flags_d <= stall_flags;
+				if stall_flags(ST_FE2_DEC) = '1' and stall_flags_d(ST_FE2_DEC) = '0' then
+					if pmem_data_out_valid = '1' then
+						pmem_stall_buffer <= pmem_data_out;
+						pmem_stall_buffer_valid <= '1';
+					end if;
+				end if;
+				if stall_flags(ST_FE2_DEC) = '0' and stall_flags_d(ST_FE2_DEC) = '1' then
+					pmem_stall_buffer_valid <= '0';
+				end if;
+
+			end if;
+		end if;
+	end process stall_buffer;
+	
+	memory_stall <= '1' when ( xmem_rd_en = '1' or (xmem_rd_polling = '1' and xmem_data_out_valid = '0') ) or
+	                         ( ymem_rd_en = '1' or (ymem_rd_polling = '1' and ymem_data_out_valid = '0') ) else
+	                '0';
+
+	-------------------------------
+	-- PMEM CONTROLLER
+	-------------------------------
+	inst_pmem_ctrl : mem_control
+	generic map(
+		mem_type => P_MEM
+	)
+	port map(
+		clk => clk,
+		rst => rst,
+		rd_addr => pmem_ctrl_in.rd_addr,
+		rd_en   => pmem_ctrl_in.rd_en,
+		data_out => pmem_data_out,
+		data_out_valid => pmem_data_out_valid,
+		wr_addr => pmem_ctrl_in.wr_addr,
+		wr_en   => pmem_ctrl_in.wr_en,
+		data_in => pmem_ctrl_in.data_in
+	);
+
+	-- In case we wake up from a stall use the buffered value
+	pmem_ctrl_out.data_out <= pmem_stall_buffer when stall_flags(ST_FE2_DEC) = '0' and 
+	                                                 stall_flags_d(ST_FE2_DEC) = '1' and 
+	                                                 pmem_stall_buffer_valid = '1'  else
+	                          pmem_data_out;
+
+	pmem_ctrl_out.data_out_valid <= pmem_stall_buffer_valid when stall_flags(ST_FE2_DEC) = '0' and 
+	                                                             stall_flags_d(ST_FE2_DEC) = '1' else
+	                                '0'                     when stall_flags(ST_FE2_DEC) = '1' else
+	                                pmem_data_out_valid;
+
+	-------------------------------
+	-- XMEM CONTROLLER
+	-------------------------------
+	inst_xmem_ctrl : mem_control
+	generic map(
+		mem_type => X_MEM
+	)
+	port map(
+		clk => clk,
+		rst => rst,
+		rd_addr => xmem_ctrl_in.rd_addr,
+		rd_en   => xmem_rd_en,
+		data_out => xmem_data_out,
+		data_out_valid => xmem_data_out_valid,
+		wr_addr => xmem_ctrl_in.wr_addr,
+		wr_en   => xmem_ctrl_in.wr_en,
+		data_in => xmem_ctrl_in.data_in
+	);
+
+	xmem_rd_en <= '1' when xmem_rd_polling = '0' and xmem_ctrl_in.rd_en = '1' else '0';
+
+	xmem_ctrl_out.data_out <= xmem_data_out;
+	xmem_ctrl_out.data_out_valid <= xmem_data_out_valid;
+
+	-------------------------------
+	-- YMEM CONTROLLER
+	-------------------------------
+	inst_ymem_ctrl : mem_control
+	generic map(
+		mem_type => Y_MEM
+	)
+	port map(
+		clk => clk,
+		rst => rst,
+		rd_addr => ymem_ctrl_in.rd_addr,
+		rd_en   => ymem_rd_en,
+		data_out => ymem_data_out,
+		data_out_valid => ymem_data_out_valid,
+		wr_addr => ymem_ctrl_in.wr_addr,
+		wr_en   => ymem_ctrl_in.wr_en,
+		data_in => ymem_ctrl_in.data_in
+	);
+
+	ymem_rd_en <= '1' when ymem_rd_polling = '0' and ymem_ctrl_in.rd_en = '1' else '0';
+
+	ymem_ctrl_out.data_out <= ymem_data_out;
+	ymem_ctrl_out.data_out_valid <= ymem_data_out_valid;
+
+	mem_stall_control: process(clk) is
+	begin
+		if rising_edge(clk) then
+			if rst = '1' then
+				xmem_rd_polling <= '0';
+				ymem_rd_polling <= '0';
+			else
+				if xmem_rd_en = '1' then
+					xmem_rd_polling <= '1';
+				end if;
+
+				if xmem_data_out_valid = '1' then
+					xmem_rd_polling <= '0';
+				end if;
+
+				if ymem_rd_en = '1' then
+					ymem_rd_polling <= '1';
+				end if;
+
+				if ymem_data_out_valid = '1' then
+					ymem_rd_polling <= '0';
+				end if;
+
+			end if;
+		end if;
+	end process;
+end architecture;
+
diff --git a/FireBee/trunk/vhdl/dsp56k/src/parameter_pkg.vhd b/FireBee/trunk/vhdl/dsp56k/src/parameter_pkg.vhd
new file mode 100644
index 0000000..f06c000
--- /dev/null
+++ b/FireBee/trunk/vhdl/dsp56k/src/parameter_pkg.vhd
@@ -0,0 +1,18 @@
+------------------------------------------------------------------------------
+--! @file
+--! @author Matthias Alles
+--! @date 01/2009
+--! @brief Global parameters
+--!
+------------------------------------------------------------------------------
+
+package parameter_pkg is
+
+	constant BW_ADDRESS : natural := 16;
+
+	-- number of pipeline register stages
+	constant PIPELINE_DEPTH : natural := 4;
+
+	constant NUM_ACT_SIGNALS : natural := 26;
+
+end package;
diff --git a/FireBee/trunk/vhdl/dsp56k/src/pipeline.vhd b/FireBee/trunk/vhdl/dsp56k/src/pipeline.vhd
new file mode 100644
index 0000000..f00db65
--- /dev/null
+++ b/FireBee/trunk/vhdl/dsp56k/src/pipeline.vhd
@@ -0,0 +1,1007 @@
+------------------------------------------------------------------------------
+--! @file
+--! @author Matthias Alles
+--! @date 01/2009
+--! @brief DSP 56k pipeline
+--!
+--! @details This is the computational part of the DSP core. The pipeline
+--! consists of five stages:
+--!  - FE : Initiate read access to program memory
+--!  - FE2: Retrieve data from program memory
+--!  - DEC: Instruction decode
+--!  - ADG: Address generation units - also inits of xmem, ymem, and pmem reads
+--!  - EX : Execute stage, contains ALU, loop controls, writes to xmem, ymem,
+--!         pmem
+--!
+------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.parameter_pkg.all;
+use work.types_pkg.all;
+use work.constants_pkg.all;
+
+entity pipeline is port (
+	clk, rst : in std_logic;
+	register_file_out : out register_file_type;
+	stall_flags_out   : out std_logic_vector(PIPELINE_DEPTH-1 downto 0);
+	memory_stall   : in  std_logic;
+	data_rom_enable: out std_logic;
+	pmem_ctrl_in   : out mem_ctrl_type_in;
+	pmem_ctrl_out  : in  mem_ctrl_type_out;
+	pmem2_ctrl_in  : out mem_ctrl_type_in;
+	pmem2_ctrl_out : in  mem_ctrl_type_out;
+	xmem_ctrl_in   : out mem_ctrl_type_in;
+	xmem_ctrl_out  : in  mem_ctrl_type_out;
+	ymem_ctrl_in   : out mem_ctrl_type_in;
+	ymem_ctrl_out  : in  mem_ctrl_type_out
+
+);
+end pipeline;
+
+-- TODOs:
+-- External memory accesses
+-- ROM tables
+-- Reading from SSH flag has to modify stack pointer
+-- Memory access (x,y,p) and stalling accordingly
+
+-- List of known BUGS:
+-- - Reading from address one clock cycle after writing to the same address might result in corrupted data!!
+-- - SBC instruction has errorneous carry flag calculation
+
+-- List of probable issues:
+-- - Reading from XMEM/YMEM with stalls probably results in corrupted data
+-- - ENDDO instruction probably has to flush the pipeline afterwards
+-- - Writing to memory occurs twice, when stalls occur
+
+-- Things to optimize:
+--  - RTS/RTI could be executed in the ADGEN Stage already
+--  - DO loops always flush the pipeline. This is necessary in case we have a very short loop.
+--     The single instruction of the loop then has passed the fetch stage already without the branch
+
+
+architecture rtl of pipeline is
+
+	signal pipeline_regs : pipeline_type;
+	signal stall_flags   : std_logic_vector(PIPELINE_DEPTH-1 downto 0);
+
+	component fetch_stage is port(
+		pc_old        : in  unsigned(BW_ADDRESS-1 downto 0);
+		pc_new        : out unsigned(BW_ADDRESS-1 downto 0);
+		modify_pc     : in  std_logic;
+		modified_pc   : in  unsigned(BW_ADDRESS-1 downto 0);
+		register_file : in  register_file_type;
+		decrement_lc  : out std_logic;
+		perform_enddo : out std_logic
+	);
+	end component fetch_stage;
+
+	signal pc_old, pc_new    : unsigned(BW_ADDRESS-1 downto 0);
+	signal fetch_modify_pc   : std_logic;
+	signal fetch_modified_pc : unsigned(BW_ADDRESS-1 downto 0);
+	signal fetch_perform_enddo: std_logic;
+	signal fetch_decrement_lc: std_logic;
+
+
+	component decode_stage is port(
+		activate_dec    : in  std_logic;
+		instr_word      : in  std_logic_vector(23 downto 0);
+		dble_word_instr : out std_logic;
+		instr_array     : out instructions_type;
+		act_array       : out std_logic_vector(NUM_ACT_SIGNALS-1 downto 0);
+		reg_wr_addr     : out std_logic_vector(5 downto 0);
+		reg_rd_addr     : out std_logic_vector(5 downto 0);
+		x_bus_rd_addr   : out std_logic_vector(1 downto 0); 
+		x_bus_wr_addr   : out std_logic_vector(1 downto 0); 
+		y_bus_rd_addr   : out std_logic_vector(1 downto 0); 
+		y_bus_wr_addr   : out std_logic_vector(1 downto 0); 
+		l_bus_addr      : out std_logic_vector(2 downto 0); 
+		adgen_mode_a    : out adgen_mode_type;
+		adgen_mode_b    : out adgen_mode_type;
+		alu_ctrl        : out alu_ctrl_type
+	);
+	end component decode_stage;
+
+	signal dec_activate : std_logic;
+	signal dec_instr_word      : std_logic_vector(23 downto 0);
+	signal dec_dble_word_instr : std_logic;
+	signal dec_instr_array     : instructions_type;
+	signal dec_act_array       : std_logic_vector(NUM_ACT_SIGNALS-1 downto 0);
+	signal dec_reg_wr_addr     : std_logic_vector(5 downto 0);
+	signal dec_reg_rd_addr     : std_logic_vector(5 downto 0);
+	signal dec_x_bus_wr_addr   : std_logic_vector(1 downto 0);
+	signal dec_x_bus_rd_addr   : std_logic_vector(1 downto 0);
+	signal dec_y_bus_wr_addr   : std_logic_vector(1 downto 0);
+	signal dec_y_bus_rd_addr   : std_logic_vector(1 downto 0);
+	signal dec_l_bus_addr      : std_logic_vector(2 downto 0);
+	signal dec_adgen_mode_a    : adgen_mode_type;
+	signal dec_adgen_mode_b    : adgen_mode_type;
+	signal dec_alu_ctrl        : alu_ctrl_type;
+
+	component adgen_stage is port(
+		activate_adgen    : in  std_logic;
+		activate_x_mem    : in  std_logic;
+		activate_y_mem    : in  std_logic;
+		activate_l_mem    : in  std_logic;
+		instr_word        : in  std_logic_vector(23 downto 0);
+		instr_array       : in  instructions_type;
+		optional_ea_word  : in  std_logic_vector(23 downto 0);
+		register_file     : in  register_file_type;
+		adgen_mode_a      : in  adgen_mode_type;
+		adgen_mode_b      : in  adgen_mode_type;
+		address_out_x     : out unsigned(BW_ADDRESS-1 downto 0);
+		address_out_y     : out unsigned(BW_ADDRESS-1 downto 0);
+		wr_R_port_A_valid : out std_logic;
+		wr_R_port_A       : out addr_wr_port_type;
+		wr_R_port_B_valid : out std_logic;
+		wr_R_port_B       : out addr_wr_port_type
+	);
+	end component adgen_stage;
+
+	signal adgen_activate          : std_logic;
+	signal adgen_activate_x_mem    : std_logic;
+	signal adgen_activate_y_mem    : std_logic;
+	signal adgen_activate_l_mem    : std_logic;
+	signal adgen_instr_word        : std_logic_vector(23 downto 0);
+	signal adgen_instr_array       : instructions_type;
+	signal adgen_optional_ea_word  : std_logic_vector(23 downto 0);
+	signal adgen_register_file     : register_file_type;
+	signal adgen_mode_a            : adgen_mode_type;
+	signal adgen_mode_b            : adgen_mode_type;
+	signal adgen_address_out_x     : unsigned(BW_ADDRESS-1 downto 0);
+	signal adgen_address_out_y     : unsigned(BW_ADDRESS-1 downto 0);
+	signal adgen_wr_R_port_A_valid : std_logic;
+	signal adgen_wr_R_port_A       : addr_wr_port_type;
+	signal adgen_wr_R_port_B_valid : std_logic;
+	signal adgen_wr_R_port_B       : addr_wr_port_type;
+
+	component exec_stage_bit_modify is port(
+		instr_word        : in  std_logic_vector(23 downto 0);
+		instr_array       : in  instructions_type;
+		src_operand       : in  std_logic_vector(23 downto 0);
+		register_file     : in  register_file_type;
+		dst_operand       : out std_logic_vector(23 downto 0);
+		bit_cond_met      : out std_logic;
+		modify_sr         : out std_logic;
+		modified_sr       : out std_logic_vector(15 downto 0)
+	);
+	end component exec_stage_bit_modify;
+
+	signal exec_bit_modify_instr_word    : std_logic_vector(23 downto 0);
+	signal exec_bit_modify_instr_array   : instructions_type;
+	signal exec_bit_modify_src_operand   : std_logic_vector(23 downto 0);
+	signal exec_bit_modify_dst_operand   : std_logic_vector(23 downto 0);
+	signal exec_bit_modify_bit_cond_met  : std_logic;
+	signal exec_bit_modify_modify_sr     : std_logic;
+	signal exec_bit_modify_modified_sr   : std_logic_vector(15 downto 0);
+
+	component exec_stage_branch is port(
+		activate_exec_bra : in  std_logic;
+		instr_word        : in  std_logic_vector(23 downto 0);
+		instr_array       : in  instructions_type;
+		register_file     : in  register_file_type;
+		jump_address      : in  unsigned(BW_ADDRESS-1 downto 0);
+		bit_cond_met      : in  std_logic;
+		cc_flag_set       : in  std_logic;
+		push_stack        : out push_stack_type;
+		pop_stack         : out pop_stack_type;
+		modify_pc         : out std_logic;
+		modified_pc       : out unsigned(BW_ADDRESS-1 downto 0);
+		modify_sr         : out std_logic;
+		modified_sr       : out std_logic_vector(15 downto 0)
+	);
+	end component exec_stage_branch;
+
+	signal exec_bra_activate     : std_logic;
+	signal exec_bra_instr_word   : std_logic_vector(23 downto 0);
+	signal exec_bra_instr_array  : instructions_type;
+	signal exec_bra_jump_address : unsigned(BW_ADDRESS-1 downto 0);
+	signal exec_bra_bit_cond_met : std_logic;
+	signal exec_bra_push_stack   : push_stack_type;
+	signal exec_bra_pop_stack    : pop_stack_type;
+	signal exec_bra_modify_pc    : std_logic;
+	signal exec_bra_modified_pc  : unsigned(BW_ADDRESS-1 downto 0);
+	signal exec_bra_modify_sr    : std_logic;
+	signal exec_bra_modified_sr  : std_logic_vector(15 downto 0);
+
+	component exec_stage_cr_mod is port(
+		activate_exec_cr_mod : in  std_logic;
+		instr_word           : in  std_logic_vector(23 downto 0);
+		instr_array          : in  instructions_type;
+		register_file        : in  register_file_type;
+		modify_sr            : out std_logic;
+		modified_sr          : out std_logic_vector(15 downto 0);
+		modify_omr           : out std_logic;
+		modified_omr         : out std_logic_vector(7 downto 0)
+	);
+	end component exec_stage_cr_mod;
+
+	signal exec_cr_mod_activate     : std_logic;
+	signal exec_cr_mod_instr_word   : std_logic_vector(23 downto 0);
+	signal exec_cr_mod_instr_array  : instructions_type;
+	signal exec_cr_mod_modify_sr    : std_logic;
+	signal exec_cr_mod_modified_sr  : std_logic_vector(15 downto 0);
+	signal exec_cr_mod_modify_omr   : std_logic;
+	signal exec_cr_mod_modified_omr : std_logic_vector(7 downto 0);
+
+	component exec_stage_loop is port(
+		clk, rst           : in  std_logic;
+		activate_exec_loop : in  std_logic;
+		instr_word        : in  std_logic_vector(23 downto 0);
+		instr_array       : in  instructions_type;
+		loop_iterations   : in  unsigned(15 downto 0);
+		loop_address      : in  unsigned(BW_ADDRESS-1 downto 0);
+		loop_start_address: in  unsigned(BW_ADDRESS-1 downto 0);
+		register_file     : in  register_file_type;
+		fetch_perform_enddo: in std_logic;
+		memory_stall      : in  std_logic;
+		push_stack        : out push_stack_type;
+		pop_stack         : out pop_stack_type;
+		stall_rep         : out std_logic;
+		stall_do          : out std_logic;
+		decrement_lc      : out std_logic;
+		modify_lc         : out std_logic;
+		modified_lc       : out unsigned(15 downto 0);
+		modify_la         : out std_logic;
+		modified_la       : out unsigned(15 downto 0);
+		modify_pc         : out std_logic;
+		modified_pc       : out unsigned(BW_ADDRESS-1 downto 0);
+		modify_sr         : out std_logic;
+		modified_sr       : out std_logic_vector(15 downto 0)
+	);
+	end component exec_stage_loop;
+
+	signal exec_loop_activate : std_logic;
+	signal exec_loop_instr_word    : std_logic_vector(23 downto 0);
+	signal exec_loop_instr_array   : instructions_type;
+	signal exec_loop_iterations    : unsigned(15 downto 0);
+	signal exec_loop_address       : unsigned(BW_ADDRESS-1 downto 0);
+	signal exec_loop_start_address : unsigned(BW_ADDRESS-1 downto 0);
+	signal exec_loop_register_file : register_file_type;
+	signal exec_loop_push_stack    : push_stack_type;
+	signal exec_loop_pop_stack     : pop_stack_type;
+	signal exec_loop_stall_rep     : std_logic;
+	signal exec_loop_stall_do      : std_logic;
+	signal exec_loop_decrement_lc  : std_logic;
+	signal exec_loop_modify_lc     : std_logic;
+	signal exec_loop_modified_lc   : unsigned(15 downto 0);
+	signal exec_loop_modify_la     : std_logic;
+	signal exec_loop_modified_la   : unsigned(BW_ADDRESS-1 downto 0);
+	signal exec_loop_modify_pc     : std_logic;
+	signal exec_loop_modified_pc   : unsigned(BW_ADDRESS-1 downto 0);
+	signal exec_loop_modify_sr     : std_logic;
+	signal exec_loop_modified_sr   : std_logic_vector(BW_ADDRESS-1 downto 0);
+
+	component exec_stage_alu is port(
+		alu_activate      : in  std_logic;
+		instr_word        : in  std_logic_vector(23 downto 0);
+		alu_ctrl          : in  alu_ctrl_type;
+		register_file     : in  register_file_type;
+		addr_r_in         : in  unsigned(BW_ADDRESS-1 downto 0);
+		addr_r_out        : out unsigned(BW_ADDRESS-1 downto 0);
+		modify_accu       : out std_logic;
+		dst_accu          : out std_logic;
+		modified_accu     : out signed(55 downto 0);
+		modify_sr         : out std_logic;
+		modified_sr       : out std_logic_vector(15 downto 0)
+	);
+	end component exec_stage_alu;
+
+	signal exec_alu_activate      : std_logic;
+	signal exec_alu_instr_word    : std_logic_vector(23 downto 0);
+	signal exec_alu_ctrl          : alu_ctrl_type;
+	signal exec_alu_addr_r_in     : unsigned(BW_ADDRESS-1 downto 0);
+	signal exec_alu_addr_r_out    : unsigned(BW_ADDRESS-1 downto 0);
+	signal exec_alu_modify_accu   : std_logic;
+	signal exec_alu_dst_accu      : std_logic;
+	signal exec_alu_modified_accu : signed(55 downto 0);
+	signal exec_alu_modify_sr     : std_logic;
+	signal exec_alu_modified_sr   : std_logic_vector(15 downto 0);
+
+	signal exec_imm_8bit    : std_logic_vector(23 downto 0);
+	signal exec_imm_12bit   : std_logic_vector(23 downto 0);
+	signal exec_src_operand : std_logic_vector(23 downto 0);
+	signal exec_dst_operand : std_logic_vector(23 downto 0);
+
+	component exec_stage_cc_flag_calc is port(
+		instr_word        : in  std_logic_vector(23 downto 0);
+		instr_array       : in  instructions_type;
+		register_file     : in  register_file_type;
+		cc_flag_set       : out std_logic
+	);
+	end component exec_stage_cc_flag_calc;
+
+	signal exec_cc_flag_calc_instr_word   : std_logic_vector(23 downto 0);
+	signal exec_cc_flag_calc_instr_array  : instructions_type;
+	signal exec_cc_flag_set : std_logic;
+
+	component reg_file is port(
+		clk, rst          : in  std_logic;
+		register_file     : out register_file_type;
+		wr_R_port_A_valid : in  std_logic;
+		wr_R_port_A       : in  addr_wr_port_type;
+		wr_R_port_B_valid : in  std_logic;
+		wr_R_port_B       : in  addr_wr_port_type;
+		alu_wr_valid      : in  std_logic;
+		alu_wr_addr       : in  std_logic;
+		alu_wr_data       : in  signed(55 downto 0);
+		reg_wr_addr       : in  std_logic_vector(5 downto 0);
+		reg_wr_addr_valid : in  std_logic;
+		reg_wr_data       : in  std_Logic_vector(23 downto 0);
+		reg_rd_addr       : in  std_logic_vector(5 downto 0);
+		reg_rd_data       : out std_Logic_vector(23 downto 0);
+		X_bus_rd_addr     : in  std_logic_vector(1 downto 0);
+		X_bus_data_out    : out std_logic_vector(23 downto 0);
+		X_bus_wr_addr     : in  std_logic_vector(1 downto 0);
+		X_bus_wr_valid    : in  std_logic;
+		X_bus_data_in     : in  std_logic_vector(23 downto 0);
+		Y_bus_rd_addr     : in  std_logic_vector(1 downto 0);
+		Y_bus_data_out    : out std_logic_vector(23 downto 0);
+		Y_bus_wr_addr     : in  std_logic_vector(1 downto 0);
+		Y_bus_wr_valid    : in  std_logic;
+		Y_bus_data_in     : in  std_logic_vector(23 downto 0);
+		L_bus_rd_addr     : in  std_logic_vector(2 downto 0);
+		L_bus_rd_valid    : in  std_logic;
+		L_bus_wr_addr     : in  std_logic_vector(2 downto 0);
+		L_bus_wr_valid    : in  std_logic;
+		push_stack        : in  push_stack_type;
+		pop_stack         : in  pop_stack_type;
+		set_sr            : in  std_logic;
+		new_sr            : in  std_logic_vector(15 downto 0);
+		set_omr           : in  std_logic;
+		new_omr           : in  std_logic_vector(7 downto 0);
+		set_lc            : in  std_logic;
+		new_lc            : in  unsigned(15 downto 0);
+		dec_lc            : in  std_logic;
+		set_la            : in  std_logic;
+		new_la            : in  unsigned(BW_ADDRESS-1 downto 0)
+	);
+	end component reg_file;
+
+	signal register_file        : register_file_type;
+	signal rf_wr_R_port_A_valid : std_logic;
+	signal rf_wr_R_port_B_valid : std_logic;
+	signal rf_reg_wr_addr       : std_logic_vector(5 downto 0);
+	signal rf_reg_wr_addr_valid : std_logic;
+	signal rf_reg_wr_data       : std_logic_vector(23 downto 0);
+	signal rf_reg_rd_addr       : std_logic_vector(5 downto 0);
+	signal rf_reg_rd_data       : std_logic_vector(23 downto 0);
+	signal rf_X_bus_rd_addr     : std_logic_vector(1 downto 0);
+	signal rf_X_bus_data_out    : std_logic_vector(23 downto 0);
+	signal rf_X_bus_wr_addr     : std_logic_vector(1 downto 0);
+	signal rf_X_bus_wr_valid    : std_logic;
+	signal rf_X_bus_data_in     : std_logic_vector(23 downto 0);
+	signal rf_Y_bus_rd_addr     : std_logic_vector(1 downto 0);
+	signal rf_Y_bus_data_out    : std_logic_vector(23 downto 0);
+	signal rf_Y_bus_wr_addr     : std_logic_vector(1 downto 0);
+	signal rf_Y_bus_wr_valid    : std_logic;
+	signal rf_Y_bus_data_in     : std_logic_vector(23 downto 0);
+	signal rf_L_bus_rd_addr     : std_logic_vector(2 downto 0);
+	signal rf_L_bus_rd_valid    : std_logic;
+	signal rf_L_bus_wr_addr     : std_logic_vector(2 downto 0);
+	signal rf_L_bus_wr_valid    : std_logic;
+	signal push_stack           : push_stack_type;
+	signal pop_stack            : pop_stack_type;
+	signal rf_set_sr            : std_logic;
+	signal rf_new_sr            : std_logic_vector(15 downto 0);
+	signal rf_set_omr           : std_logic;
+	signal rf_new_omr           : std_logic_vector(7 downto 0);
+	signal rf_dec_lc            : std_logic;
+	signal rf_set_lc            : std_logic;
+	signal rf_new_lc            : unsigned(15 downto 0);
+	signal rf_set_la            : std_logic;
+	signal rf_new_la            : unsigned(BW_ADDRESS-1 downto 0);
+	signal rf_alu_wr_valid      : std_logic;
+
+	signal pmem_data_out       : std_logic_vector(23 downto 0);
+	signal pmem_data_out_valid : std_logic;
+	signal pmem2_data_out       : std_logic_vector(23 downto 0);
+	signal pmem2_data_out_valid : std_logic;
+
+begin
+
+	register_file_out <= register_file;
+	stall_flags_out   <= stall_flags;
+
+	-- merge all stall sources
+	stall_flags(ST_FE_FE2)  <= '1' when exec_loop_stall_rep   = '1' or
+	                                   memory_stall = '1' or
+	                                   exec_loop_stall_do    = '1' else '0';
+	stall_flags(ST_FE2_DEC) <= '1' when exec_loop_stall_rep = '1' or
+	                                   memory_stall = '1' or
+	                                   exec_loop_stall_do = '1' else '0';
+	stall_flags(ST_DEC_ADG) <= '1' when exec_loop_stall_rep = '1' or
+	                                   memory_stall = '1' or
+	                                   exec_loop_stall_do = '1' else '0';
+	stall_flags(ST_ADG_EX)  <= exec_loop_stall_do;
+
+
+	shift_pipeline: process(clk, rst) is
+		procedure flush_pipeline_stage(stage: natural) is
+		begin
+			pipeline_regs(stage).pc <= (others => '1');
+			pipeline_regs(stage).instr_word <= (others => '0');
+			pipeline_regs(stage).act_array   <= (others => '0');
+			pipeline_regs(stage).instr_array <= INSTR_NOP;
+			pipeline_regs(stage).dble_word_instr <= '0';
+			pipeline_regs(stage).dec_activate <= '0';
+			pipeline_regs(stage).adgen_mode_a <= NOP;
+			pipeline_regs(stage).adgen_mode_b <= NOP;
+			pipeline_regs(stage).reg_wr_addr  <= (others => '0');
+			pipeline_regs(stage).reg_rd_addr  <= (others => '0');
+			pipeline_regs(stage).x_bus_rd_addr  <= (others => '0');
+			pipeline_regs(stage).x_bus_wr_addr  <= (others => '0');
+			pipeline_regs(stage).y_bus_rd_addr  <= (others => '0');
+			pipeline_regs(stage).y_bus_wr_addr  <= (others => '0');
+			pipeline_regs(stage).l_bus_addr     <= (others => '0');
+			pipeline_regs(stage).adgen_address_x <= (others => '0');
+			pipeline_regs(stage).adgen_address_y <= (others => '0');
+			pipeline_regs(stage).RAM_out_x <= (others => '0');
+			pipeline_regs(stage).RAM_out_y <= (others => '0');
+			pipeline_regs(stage).alu_ctrl.store_result <= '0';
+		end procedure flush_pipeline_stage;
+	begin
+		if rising_edge(clk) then
+			if rst = '1' then
+				for i in 0 to PIPELINE_DEPTH-1 loop
+					flush_pipeline_stage(i);
+				end loop;
+			else
+				-- shift the pipeline registers when no stall applies
+				for i in 1 to PIPELINE_DEPTH-1 loop
+					if stall_flags(i) = '0' then
+						-- The following situations have to be considered:
+						-- 1) Do not copy the pipeline registers from a stalled pipeline stage.
+						--    Instead insert NOPs into the pipeline, except for the REP instruction.
+						-- 2) Flushing of the ST_ADG_EX-stage is required when a memory access causes
+						--    a stall. In this case the EX-stage will perform its task and the pipeline
+						--    stage has to be flushed. Otherwise the instruction would be executed twice.
+-- TODO:
+-- What happens when memory writes cause a stall? => Flushing of ST_ADG_EX not allowed!?
+						if (stall_flags(i-1) = '1' and exec_loop_stall_rep = '0') or
+						   (i = ST_ADG_EX and memory_stall = '1' and exec_loop_stall_rep = '1') then
+							flush_pipeline_stage(i);
+						else
+							pipeline_regs(i) <= pipeline_regs(i-1);
+						end if;
+					end if;
+				end loop;
+				-- FE_FE2 Pipeline Registers 
+				if stall_flags(ST_FE_FE2) = '0' then
+					pipeline_regs(ST_FE_FE2).pc <= pc_new;
+					pipeline_regs(ST_FE_FE2).dec_activate <= '1';
+				end if;
+
+				-- FE2_DEC Pipeline Registers
+				if stall_flags(ST_FE2_DEC) = '0' then
+					-- Normal pipeline operation?
+					-- Buffering of RAM output when stalling is performed in the memory management
+					if pmem_data_out_valid = '1' then
+						pipeline_regs(ST_FE2_DEC).instr_word <= pmem_data_out;
+					end if;
+				end if;
+
+				-- DEC_ADG Pipeline registers
+				if stall_flags(ST_DEC_ADG) = '0' then
+					pipeline_regs(ST_DEC_ADG).act_array       <= dec_act_array;
+					pipeline_regs(ST_DEC_ADG).instr_array     <= dec_instr_array;
+					pipeline_regs(ST_DEC_ADG).dble_word_instr <= dec_dble_word_instr;
+					pipeline_regs(ST_DEC_ADG).reg_wr_addr     <= dec_reg_wr_addr;
+					pipeline_regs(ST_DEC_ADG).reg_rd_addr     <= dec_reg_rd_addr;
+					pipeline_regs(ST_DEC_ADG).x_bus_wr_addr   <= dec_x_bus_wr_addr;
+					pipeline_regs(ST_DEC_ADG).x_bus_rd_addr   <= dec_x_bus_rd_addr;
+					pipeline_regs(ST_DEC_ADG).y_bus_wr_addr   <= dec_y_bus_wr_addr;
+					pipeline_regs(ST_DEC_ADG).y_bus_rd_addr   <= dec_y_bus_rd_addr;
+					pipeline_regs(ST_DEC_ADG).l_bus_addr      <= dec_l_bus_addr;
+					pipeline_regs(ST_DEC_ADG).adgen_mode_a    <= dec_adgen_mode_a;
+					pipeline_regs(ST_DEC_ADG).adgen_mode_b    <= dec_adgen_mode_b;
+					pipeline_regs(ST_DEC_ADG).alu_ctrl        <= dec_alu_ctrl;
+				end if;
+
+				-- ADG_EX Pipeline registers
+				if stall_flags(ST_ADG_EX) = '0' then
+					pipeline_regs(ST_ADG_EX).adgen_address_x <= adgen_address_out_x;
+					pipeline_regs(ST_ADG_EX).adgen_address_y <= adgen_address_out_y;
+				end if;
+
+-- TODO: memory_stall neu eingebaut, noch nicht getestet. Hier evtl. wie oben direkt auf
+-- stall_flags zugreifen (ST_ADG_EX)?
+				-- Copying to the pipeline register should only happen, when the stall is released.
+				-- Otherwise the content could be deleted before it is actually used (when x and y
+				-- content are not valid at the same time).
+				if xmem_ctrl_out.data_out_valid = '1' and memory_stall = '0' then
+					pipeline_regs(ST_ADG_EX).RAM_out_x <= xmem_ctrl_out.data_out;
+				end if;
+				if ymem_ctrl_out.data_out_valid = '1'and memory_stall = '0'  then
+					pipeline_regs(ST_ADG_EX).RAM_out_y <= ymem_ctrl_out.data_out;
+				end if;
+
+				-- EXECUTE Pipeline stuff
+				if exec_bra_modify_pc = '1' or exec_loop_modify_pc = '1' then
+					-- clear the following pipeline stages,
+					-- since we modified the pc.
+					-- Do not flush ST_FE_FE2 - it will hold the correct pc.
+					flush_pipeline_stage(ST_FE2_DEC);
+					flush_pipeline_stage(ST_DEC_ADG);
+					flush_pipeline_stage(ST_ADG_EX);
+				end if;
+			end if;
+		end if;
+	end process shift_pipeline;
+
+
+	-------------------------------
+	-- FETCH STAGE INSTANTIATION
+	-------------------------------
+
+	inst_fetch_stage: fetch_stage port map(
+		pc_old => pc_old,
+		pc_new => pc_new,
+		modify_pc => fetch_modify_pc,
+		modified_pc => fetch_modified_pc,
+		register_file => register_file,
+		decrement_lc  => fetch_decrement_lc,
+		perform_enddo => fetch_perform_enddo
+	);
+
+	pc_old <= pipeline_regs(ST_FE_FE2).pc;
+
+	fetch_modify_pc <= '1' when exec_bra_modify_pc = '1' or exec_loop_modify_pc = '1' else '0';
+	fetch_modified_pc <= exec_bra_modified_pc when exec_bra_modify_pc = '1' else
+	                     exec_loop_modified_pc;
+
+
+	-------------------------------
+	-- DECODE STAGE INSTANTIATION
+	-------------------------------
+
+	inst_decode_stage : decode_stage port map(
+		activate_dec    => dec_activate,
+		instr_word      => dec_instr_word,
+		dble_word_instr => dec_dble_word_instr,
+		instr_array     => dec_instr_array,
+		act_array       => dec_act_array,
+		reg_wr_addr     => dec_reg_wr_addr,
+		reg_rd_addr     => dec_reg_rd_addr,
+		x_bus_wr_addr   => dec_x_bus_wr_addr,
+		x_bus_rd_addr   => dec_x_bus_rd_addr,
+		y_bus_wr_addr   => dec_y_bus_wr_addr,
+		y_bus_rd_addr   => dec_y_bus_rd_addr,
+		l_bus_addr      => dec_l_bus_addr,
+		adgen_mode_a    => dec_adgen_mode_a,
+		adgen_mode_b    => dec_adgen_mode_b,
+		alu_ctrl        => dec_alu_ctrl
+	);
+
+	dec_instr_word <= pipeline_regs(ST_FE2_DEC).instr_word;
+	-- do not decode, when we have no valid instruction. This can happen when
+	--  1) the pipeline just started its operation
+	--  2) the pipeline was flushed due to a jump
+	--  3) we are processing an instruction that consists of two words
+	dec_activate   <= '1' when pipeline_regs(ST_FE2_DEC).dec_activate = '1' and pipeline_regs(ST_DEC_ADG).dble_word_instr = '0' else '0';
+
+
+	-------------------------------
+	-- AGU STAGE INSTANTIATION
+	-------------------------------
+
+	inst_adgen_stage: adgen_stage port map(
+		activate_adgen    => adgen_activate,
+		activate_x_mem    => adgen_activate_x_mem,
+		activate_y_mem    => adgen_activate_y_mem,
+		activate_l_mem    => adgen_activate_l_mem,
+		instr_word        => adgen_instr_word,
+		instr_array       => adgen_instr_array,
+		optional_ea_word  => adgen_optional_ea_word,
+		register_file     => register_file,
+		adgen_mode_a      => adgen_mode_a,
+		adgen_mode_b      => adgen_mode_b,
+		address_out_x     => adgen_address_out_x,
+		address_out_y     => adgen_address_out_y,
+		wr_R_port_A_valid => adgen_wr_R_port_A_valid,
+		wr_R_port_A       => adgen_wr_R_port_A,
+		wr_R_port_B_valid => adgen_wr_R_port_B_valid,
+		wr_R_port_B       => adgen_wr_R_port_B
+	);
+
+	adgen_activate          <= pipeline_regs(ST_DEC_ADG).act_array(ACT_ADGEN);
+	adgen_activate_x_mem    <= '1' when pipeline_regs(ST_DEC_ADG).act_array(ACT_X_MEM_RD) = '1' or
+	                                    pipeline_regs(ST_DEC_ADG).act_array(ACT_X_MEM_WR) = '1' else '0';
+	adgen_activate_y_mem    <= '1' when pipeline_regs(ST_DEC_ADG).act_array(ACT_Y_MEM_RD) = '1' or
+	                                    pipeline_regs(ST_DEC_ADG).act_array(ACT_Y_MEM_WR) = '1' else '0';
+	adgen_activate_l_mem    <= '1' when pipeline_regs(ST_DEC_ADG).act_array(ACT_L_BUS_RD) = '1' or
+	                                    pipeline_regs(ST_DEC_ADG).act_array(ACT_L_BUS_WR) = '1' else '0';
+	adgen_instr_word        <= pipeline_regs(ST_DEC_ADG).instr_word;
+	adgen_instr_array       <= pipeline_regs(ST_DEC_ADG).instr_array;
+	adgen_optional_ea_word  <= pipeline_regs(ST_DEC_ADG-1).instr_word;
+	adgen_mode_a            <= pipeline_regs(ST_DEC_ADG).adgen_mode_a;
+	adgen_mode_b            <= pipeline_regs(ST_DEC_ADG).adgen_mode_b;
+
+
+	-------------------------------
+	-- EXECUTE STAGE INSTANTIATIONS
+	-------------------------------
+
+	-- Data ALU (MPY, MAC, ADD, shift, ...)
+	inst_exec_stage_alu: exec_stage_alu port map(
+		alu_activate  => exec_alu_activate,
+		instr_word    => exec_alu_instr_word,
+		alu_ctrl      => exec_alu_ctrl,
+		register_file => register_file,
+		addr_r_in     => exec_alu_addr_r_in,
+		addr_r_out    => exec_alu_addr_r_out,
+		modify_accu   => exec_alu_modify_accu,
+		dst_accu      => exec_alu_dst_accu,
+		modified_accu => exec_alu_modified_accu,
+		modify_sr     => exec_alu_modify_sr,
+		modified_sr   => exec_alu_modified_sr
+	);
+
+	exec_alu_activate   <= pipeline_regs(ST_ADG_EX).act_array(ACT_ALU);
+	exec_alu_instr_word <= pipeline_regs(ST_ADG_EX).instr_word;
+	exec_alu_ctrl       <= pipeline_regs(ST_ADG_EX).alu_ctrl;
+
+	exec_alu_addr_r_in <= unsigned(rf_reg_rd_data(BW_ADDRESS-1 downto 0));
+
+	-- Bit modification unit (BCLR, BSET, BCHG, ...)
+	inst_exec_stage_bit_modify: exec_stage_bit_modify port map(
+		instr_word     => exec_bit_modify_instr_word,
+		instr_array    => exec_bit_modify_instr_array,
+		src_operand    => exec_bit_modify_src_operand,
+		register_file  => register_file,
+		dst_operand    => exec_bit_modify_dst_operand,
+		bit_cond_met   => exec_bit_modify_bit_cond_met,
+		modify_sr      => exec_bit_modify_modify_sr,
+		modified_sr    => exec_bit_modify_modified_sr
+	);
+
+	exec_bit_modify_instr_word   <= pipeline_regs(ST_ADG_EX).instr_word;
+	exec_bit_modify_instr_array  <= pipeline_regs(ST_ADG_EX).instr_array;
+	exec_bit_modify_src_operand  <= exec_src_operand;
+
+	-- Writing to the register file using the 6 bit addressing scheme
+	-- sources are:
+	-- 1) X-RAM output
+	-- 2) Y-RAM output
+	-- 3) register file itself
+	-- 4) short immediate value (8 bit stored in instruction word)
+	-- 5) long immediate value (from optional effective address extension)
+	-- 6) address generated by the address generation unit (LUA instr)
+	exec_src_operand <= pipeline_regs(ST_ADG_EX).RAM_out_x  when pipeline_regs(ST_ADG_EX).act_array(ACT_X_MEM_RD)  = '1' else
+	                    pipeline_regs(ST_ADG_EX).RAM_out_y  when pipeline_regs(ST_ADG_EX).act_array(ACT_Y_MEM_RD)  = '1' else
+	                    rf_reg_rd_data                      when pipeline_regs(ST_ADG_EX).act_array(ACT_REG_RD)    = '1' else
+	                    exec_imm_8bit                       when pipeline_regs(ST_ADG_EX).act_array(ACT_IMM_8BIT)  = '1' else
+	                    exec_imm_12bit                      when pipeline_regs(ST_ADG_EX).act_array(ACT_IMM_12BIT) = '1' else
+	                    pipeline_regs(ST_ADG_EX-1).instr_word when pipeline_regs(ST_ADG_EX).act_array(ACT_IMM_LONG)  = '1' else
+	                    std_logic_vector(resize(pipeline_regs(ST_ADG_EX).adgen_address_x, 24)); -- for LUA instr.
+
+	-- Destination for the register file using the 6 bit addressing scheme.
+	-- Either read the bit modified version of the read value
+	-- or the output of a p-memory read
+	-- or use the modified Rn in case of a NORM instruction
+	exec_dst_operand <= exec_bit_modify_dst_operand when pipeline_regs(ST_ADG_EX).act_array(ACT_NORM) = '0' else
+	                    pmem2_data_out              when pipeline_regs(ST_ADG_EX).act_array(ACT_P_MEM_RD) = '1' else
+	                    std_logic_vector(resize(exec_alu_addr_r_out,24));
+
+	-- Unit to check whether cc (in Jcc, JScc, Tcc, ...) is true
+	inst_exec_stage_cc_flag_calc: exec_stage_cc_flag_calc port map(
+		instr_word        => exec_cc_flag_calc_instr_word,
+		instr_array       => exec_cc_flag_calc_instr_array,
+		register_file     => register_file,
+		cc_flag_set       => exec_cc_flag_set
+	);
+
+	exec_cc_flag_calc_instr_word   <= pipeline_regs(ST_ADG_EX).instr_word;
+	exec_cc_flag_calc_instr_array  <= pipeline_regs(ST_ADG_EX).instr_array;
+
+	-- Branch calculation unit
+	inst_exec_stage_branch : exec_stage_branch port map(
+		activate_exec_bra => exec_bra_activate,
+		instr_word        => exec_bra_instr_word,
+		instr_array       => exec_bra_instr_array,
+		register_file     => register_file,
+		jump_address      => exec_bra_jump_address,
+		bit_cond_met      => exec_bra_bit_cond_met,
+		cc_flag_set       => exec_cc_flag_set,
+		push_stack        => exec_bra_push_stack,
+		pop_stack         => exec_bra_pop_stack,
+		modify_pc         => exec_bra_modify_pc,
+		modified_pc       => exec_bra_modified_pc,
+		modify_sr         => exec_bra_modify_sr,
+		modified_sr       => exec_bra_modified_sr
+	);
+
+	exec_bra_activate     <= pipeline_regs(ST_ADG_EX).act_array(ACT_EXEC_BRA);
+	exec_bra_instr_word   <= pipeline_regs(ST_ADG_EX).instr_word;
+	exec_bra_instr_array  <= pipeline_regs(ST_ADG_EX).instr_array;
+	exec_bra_jump_address <= pipeline_regs(ST_ADG_EX).adgen_address_x when pipeline_regs(ST_ADG_EX).dble_word_instr = '0' else
+	                         unsigned(pipeline_regs(ST_ADG_EX-1).instr_word(BW_ADDRESS-1 downto 0));
+	exec_bra_bit_cond_met <= exec_bit_modify_bit_cond_met;
+
+	-- Control register modifications
+	inst_exec_stage_cr_mod : exec_stage_cr_mod port map(
+		activate_exec_cr_mod => exec_cr_mod_activate,
+		instr_word           => exec_cr_mod_instr_word,
+		instr_array          => exec_cr_mod_instr_array,
+		register_file        => register_file,
+		modify_sr            => exec_cr_mod_modify_sr,
+		modified_sr          => exec_cr_mod_modified_sr,
+		modify_omr           => exec_cr_mod_modify_omr,
+		modified_omr         => exec_cr_mod_modified_omr
+	);
+
+	exec_cr_mod_activate    <= pipeline_regs(ST_ADG_EX).act_array(ACT_EXEC_CR_MOD);
+	exec_cr_mod_instr_word  <= pipeline_regs(ST_ADG_EX).instr_word;
+	exec_cr_mod_instr_array <= pipeline_regs(ST_ADG_EX).instr_array;
+
+	-- Loop control
+	inst_exec_stage_loop: exec_stage_loop port map(
+		clk                => clk,
+		rst                => rst,
+		activate_exec_loop => exec_loop_activate,
+		instr_word         => exec_loop_instr_word,
+		instr_array        => exec_loop_instr_array,
+		loop_iterations    => exec_loop_iterations,
+		loop_address       => exec_loop_address,
+		loop_start_address => exec_loop_start_address,
+		register_file      => register_file,
+		fetch_perform_enddo=> fetch_perform_enddo,
+		memory_stall       => memory_stall,
+		push_stack         => exec_loop_push_stack,
+		pop_stack          => exec_loop_pop_stack,
+		stall_rep          => exec_loop_stall_rep,
+		stall_do           => exec_loop_stall_do,
+		modify_lc          => exec_loop_modify_lc,
+		decrement_lc       => exec_loop_decrement_lc,
+		modified_lc        => exec_loop_modified_lc,
+		modify_la          => exec_loop_modify_la,
+		modified_la        => exec_loop_modified_la,
+		modify_pc          => exec_loop_modify_pc,
+		modified_pc        => exec_loop_modified_pc,
+		modify_sr          => exec_loop_modify_sr,
+		modified_sr        => exec_loop_modified_sr
+	);
+
+	exec_loop_activate    <= pipeline_regs(ST_ADG_EX).act_array(ACT_EXEC_LOOP);
+	exec_loop_instr_word  <= pipeline_regs(ST_ADG_EX).instr_word;
+	exec_loop_instr_array <= pipeline_regs(ST_ADG_EX).instr_array;
+	exec_loop_iterations  <= unsigned(exec_src_operand(15 downto 0));
+
+	-- Loop address is given by the second instruction word of the DO instruction.
+	-- This address is available one previous stage within the pipeline
+	exec_loop_address     <= unsigned(pipeline_regs(ST_ADG_EX-1).instr_word(BW_ADDRESS-1 downto 0)) - 1; 
+	-- one more stage before we find the programm counter of the first instruction to be executed in a DO loop
+	exec_loop_start_address <= unsigned(pipeline_regs(ST_ADG_EX-2).pc);
+
+	-- For the 8 bit immediate is can be either a fractional (registers x0,x1,y0,y1,a,b) or an unsigned (the rest)
+	exec_imm_8bit(23 downto 16) <= (others => '0') when rf_reg_wr_addr(5 downto 2) /= "0001" and rf_reg_wr_addr(5 downto 1) /= "00111" else
+	                               pipeline_regs(ST_ADG_EX).instr_word(15 downto 8);
+	exec_imm_8bit(15 downto  8) <= (others => '0');
+	exec_imm_8bit( 7 downto  0) <= (others => '0') when rf_reg_wr_addr(5 downto 2) = "0001" or rf_reg_wr_addr(5 downto 1) = "00111" else
+	                               pipeline_regs(ST_ADG_EX).instr_word(15 downto 8);
+	-- The 12 bit immediate stems from the instruction word
+	exec_imm_12bit(23 downto 12) <= (others => '0');
+	exec_imm_12bit(11 downto  0) <= pipeline_regs(ST_ADG_EX).instr_word(3 downto 0) & pipeline_regs(ST_ADG_EX).instr_word(15 downto 8);
+
+
+	-----------------
+	-- REGISTER FILE
+	-----------------
+
+	inst_reg_file: reg_file port map(
+		clk                => clk,
+		rst                => rst,
+
+		-- Output for reading when needed
+		register_file      => register_file,
+
+		-- AGU write ports
+		wr_R_port_A_valid  => rf_wr_R_port_A_valid,
+		wr_R_port_A        => adgen_wr_R_port_A,
+		wr_R_port_B_valid  => rf_wr_R_port_B_valid,
+		wr_R_port_B        => adgen_wr_R_port_B,
+
+		-- register read/write port
+		reg_wr_addr        => rf_reg_wr_addr,
+		reg_wr_addr_valid  => rf_reg_wr_addr_valid,
+		reg_wr_data        => rf_reg_wr_data,
+		reg_rd_addr        => rf_reg_rd_addr,
+		reg_rd_data        => rf_reg_rd_data,
+
+		-- ALU result write port
+		alu_wr_valid       => rf_alu_wr_valid,
+		alu_wr_addr        => exec_alu_dst_accu,
+		alu_wr_data        => exec_alu_modified_accu,
+
+		-- Bus read and write ports (X/Y/L)
+		X_bus_rd_addr      => rf_X_bus_rd_addr,
+		X_bus_data_out     => rf_X_bus_data_out,
+		X_bus_wr_addr      => rf_X_bus_wr_addr ,
+		X_bus_wr_valid     => rf_X_bus_wr_valid,
+		X_bus_data_in      => rf_X_bus_data_in ,
+		Y_bus_rd_addr      => rf_Y_bus_rd_addr ,
+		Y_bus_data_out     => rf_Y_bus_data_out,
+		Y_bus_wr_addr      => rf_Y_bus_wr_addr ,
+		Y_bus_wr_valid     => rf_Y_bus_wr_valid,
+		Y_bus_data_in      => rf_Y_bus_data_in ,
+		L_bus_rd_addr      => rf_L_bus_rd_addr ,
+		L_bus_rd_valid     => rf_L_bus_rd_valid,
+		L_bus_wr_addr      => rf_L_bus_wr_addr ,
+		L_bus_wr_valid     => rf_L_bus_wr_valid,
+
+		-- Stack modifications
+		push_stack         => push_stack,
+		pop_stack          => pop_stack,
+
+		-- Control register modifications
+		set_sr             => rf_set_sr,
+		new_sr             => rf_new_sr,
+		set_omr            => rf_set_omr,
+		new_omr            => rf_new_omr,
+		set_la             => rf_set_la,
+		new_la             => rf_new_la,
+		dec_lc             => rf_dec_lc,
+		set_lc             => rf_set_lc,
+		new_lc             => rf_new_lc
+	);
+
+	-- writing to the R registers within the ADGEN stage has to be prevented when
+	-- 1) a jump is currently being executed (which is detected in the exec stage)
+	-- 2) stall cycles occur. In this case the write will happen in the last cycle, when we stop stalling.
+	-- 3) a memory access results in a stall (e.g. caused by the instruction to REP)
+	rf_wr_R_port_A_valid <= '0' when stall_flags(ST_ADG_EX) = '1' or
+	                                 exec_bra_modify_pc = '1' or
+	                                 memory_stall = '1' else
+	                        adgen_wr_R_port_A_valid;
+	rf_wr_R_port_B_valid <= '0' when stall_flags(ST_ADG_EX) = '1' or
+	                                 exec_bra_modify_pc = '1' or
+	                                 memory_stall = '1' else
+	                        adgen_wr_R_port_B_valid;
+
+
+	rf_reg_wr_addr <= pipeline_regs(ST_ADG_EX).reg_wr_addr;
+	-- can be set due to
+	-- 1) normal write operation (e.g., move)
+	-- 2) conditional move (Tcc)
+	rf_reg_wr_addr_valid <= '1'              when pipeline_regs(ST_ADG_EX).act_array(ACT_REG_WR) = '1' else
+	                        exec_cc_flag_set when pipeline_regs(ST_ADG_EX).act_array(ACT_REG_WR_CC) = '1' else '0';
+	rf_reg_wr_data <= exec_dst_operand;
+
+	rf_reg_rd_addr <= pipeline_regs(ST_ADG_EX).reg_rd_addr;
+
+	-- Writing from the ALU can depend on the condition code (Tcc) instruction
+	rf_alu_wr_valid <= exec_cc_flag_set when pipeline_regs(ST_ADG_EX).act_array(ACT_ALU_WR_CC) = '1' else
+	                   exec_alu_modify_accu;
+
+	push_stack.valid   <= '1' when exec_bra_push_stack.valid = '1' or exec_loop_push_stack.valid = '1' else '0';
+	push_stack.content <= exec_bra_push_stack.content when exec_bra_push_stack.valid = '1' else
+	                      exec_loop_push_stack.content;
+	-- for jump to subroutine store the pc of the subsequent instruction
+	push_stack.pc <= pipeline_regs(ST_ADG_EX-1).pc when exec_bra_push_stack.valid = '1' and pipeline_regs(ST_ADG_EX).dble_word_instr = '0' else
+	                 pipeline_regs(ST_ADG_EX-2).pc when exec_bra_push_stack.valid = '1' and pipeline_regs(ST_ADG_EX).dble_word_instr = '1' else
+	                 exec_loop_push_stack.pc     when exec_loop_push_stack.valid = '1' else
+	                 (others => '0');
+
+	pop_stack.valid <= '1' when exec_bra_pop_stack.valid = '1' or exec_loop_pop_stack.valid = '1' else '0';
+
+	rf_set_sr <= '1' when exec_bra_modify_sr    = '1' or
+	                      exec_cr_mod_modify_sr = '1' or
+	                      exec_loop_modify_sr   = '1' or
+	                      exec_alu_modify_sr    = '1' or
+	                      exec_bit_modify_modify_sr = '1' else '0';
+	rf_new_sr <= exec_bra_modified_sr    when exec_bra_modify_sr = '1'    else
+	             exec_cr_mod_modified_sr when exec_cr_mod_modify_sr = '1' else
+	             exec_loop_modified_sr   when exec_loop_modify_sr = '1' else
+	             exec_alu_modified_sr    when exec_alu_modify_sr = '1' else
+	             exec_bit_modify_modified_sr; -- when exec_bit_modify_modify_sr = '1' else
+
+	rf_set_omr <= exec_cr_mod_modify_omr;
+	rf_new_omr <= exec_cr_mod_modified_omr;
+	rf_set_lc <= exec_loop_modify_lc;
+	rf_new_lc <= exec_loop_modified_lc;
+	rf_set_la <= exec_loop_modify_la;
+	rf_new_la <= exec_loop_modified_la;
+
+	rf_dec_lc <= '1' when exec_loop_decrement_lc = '1' or fetch_decrement_lc = '1' else '0';
+
+	-----------------
+	-- BUSES (X,Y,L)
+	-----------------
+
+	rf_X_bus_wr_valid <= pipeline_regs(ST_ADG_EX).act_array(ACT_X_BUS_WR);
+	rf_X_bus_wr_addr  <= pipeline_regs(ST_ADG_EX).x_bus_wr_addr;
+	rf_X_bus_rd_addr  <= pipeline_regs(ST_ADG_EX).x_bus_rd_addr;
+	rf_X_bus_data_in  <= rf_X_bus_data_out when pipeline_regs(ST_ADG_EX).act_array(ACT_X_BUS_RD) = '1' else
+	                     pipeline_regs(ST_ADG_EX).RAM_out_x; -- when pipeline_regs(ST_ADG_EX).act_array(ACT_X_MEM_RD) = '1' else
+
+	rf_Y_bus_wr_valid <= pipeline_regs(ST_ADG_EX).act_array(ACT_Y_BUS_WR);
+	rf_Y_bus_wr_addr  <= pipeline_regs(ST_ADG_EX).y_bus_wr_addr;
+	rf_Y_bus_rd_addr  <= pipeline_regs(ST_ADG_EX).y_bus_rd_addr;
+	rf_Y_bus_data_in  <= rf_Y_bus_data_out when pipeline_regs(ST_ADG_EX).act_array(ACT_Y_BUS_RD) = '1' else
+	                     pipeline_regs(ST_ADG_EX).RAM_out_y; -- when pipeline_regs(ST_ADG_EX).act_array(ACT_Y_MEM_RD) = '1' else
+
+	rf_L_bus_wr_valid <= pipeline_regs(ST_ADG_EX).act_array(ACT_L_BUS_WR);
+	rf_L_bus_rd_valid <= pipeline_regs(ST_ADG_EX).act_array(ACT_L_BUS_RD);
+	rf_L_bus_wr_addr  <= pipeline_regs(ST_ADG_EX).l_bus_addr; -- equal to bits in instruction word
+	rf_L_bus_rd_addr  <= pipeline_regs(ST_ADG_EX).l_bus_addr; -- could be simplified by taking these bits..
+
+
+	data_rom_enable <= register_file.omr(2);
+
+
+	-------------------------
+	-- Program Memory Port 1
+	--------------------------
+
+	-- pmem port 1 is only for instruction fetch
+	pmem_ctrl_in.rd_addr <= pc_new;
+	pmem_ctrl_in.rd_en   <= '1' when stall_flags(ST_FE_FE2) = '0' else '0';
+
+	-- never write to this port
+	pmem_ctrl_in.wr_addr <= (others => '0');
+	pmem_ctrl_in.wr_en   <= '0';
+	pmem_ctrl_in.data_in <= (others => '0');
+
+	pmem_data_out       <= pmem_ctrl_out.data_out;
+	pmem_data_out_valid <= pmem_ctrl_out.data_out_valid;
+
+
+	-------------------------
+	-- Program Memory Port 2
+	--------------------------
+-- TODO: This is untested!
+
+	-- pmem port 2 is for movem instructions
+
+	-- take x memory address as address
+	pmem2_ctrl_in.rd_addr <= adgen_address_out_x when pipeline_regs(ST_DEC_ADG).act_array(ACT_ADGEN) = '1' else
+	                         "0000000000" &  unsigned(pipeline_regs(ST_DEC_ADG).instr_word(13 downto 8));
+	pmem2_ctrl_in.rd_en   <= pipeline_regs(ST_DEC_ADG).act_array(ACT_P_MEM_RD);
+
+
+	-- Either take the result of the AGU or use the absolute value stored in the instruction word
+	pmem2_ctrl_in.wr_addr <= pipeline_regs(ST_ADG_EX).adgen_address_x when pipeline_regs(ST_ADG_EX).act_array(ACT_ADGEN) = '1' else
+	                        "0000000000" & unsigned(pipeline_regs(ST_ADG_EX).instr_word(13 downto 8));
+	pmem2_ctrl_in.wr_en   <= pipeline_regs(ST_ADG_EX).act_array(ACT_P_MEM_WR);
+
+	-- only the register file read value is allowed here
+	pmem2_ctrl_in.data_in <= rf_reg_rd_data;
+
+	pmem2_data_out       <= pmem2_ctrl_out.data_out;
+	pmem2_data_out_valid <= pmem2_ctrl_out.data_out_valid;
+
+	------------------
+	-- X Memory
+	------------------
+
+	-- Either take the result of the AGU or use the short absolute value stored in the instruction word
+	xmem_ctrl_in.rd_addr <= adgen_address_out_x when pipeline_regs(ST_DEC_ADG).act_array(ACT_ADGEN) = '1' else
+	                        "0000000000" &  unsigned(pipeline_regs(ST_DEC_ADG).instr_word(13 downto 8));
+	xmem_ctrl_in.rd_en   <=  '1' when pipeline_regs(ST_DEC_ADG).act_array(ACT_X_MEM_RD) = '1' else '0';
+	-- Either take the result of the AGU or use the absolute value stored in the instruction word
+	xmem_ctrl_in.wr_addr <= pipeline_regs(ST_ADG_EX).adgen_address_x when pipeline_regs(ST_ADG_EX).act_array(ACT_ADGEN) = '1' else
+	                        "0000000000" & unsigned(pipeline_regs(ST_ADG_EX).instr_word(13 downto 8));
+	xmem_ctrl_in.wr_en   <= '1' when pipeline_regs(ST_ADG_EX).act_array(ACT_X_MEM_WR) = '1' else '0';
+	xmem_ctrl_in.data_in <= rf_X_bus_data_out when pipeline_regs(ST_ADG_EX).act_array(ACT_X_BUS_RD) = '1' or
+	                                               pipeline_regs(ST_ADG_EX).act_array(ACT_L_BUS_RD) = '1'  else
+	                        exec_dst_operand;
+
+
+	------------------
+	-- Y Memory
+	------------------
+
+	-- Either take the result of the AGU or use the absolute value stored in the instruction word
+	ymem_ctrl_in.rd_addr <= adgen_address_out_y when pipeline_regs(ST_DEC_ADG).act_array(ACT_ADGEN) = '1' else
+	                        "0000000000" &  unsigned(pipeline_regs(ST_DEC_ADG).instr_word(13 downto 8));
+	ymem_ctrl_in.rd_en   <=  '1' when pipeline_regs(ST_DEC_ADG).act_array(ACT_Y_MEM_RD) = '1' else '0';
+	-- Either take the result of the AGU or use the absolute value stored in the instruction word
+	ymem_ctrl_in.wr_addr <= pipeline_regs(ST_ADG_EX).adgen_address_y when pipeline_regs(ST_ADG_EX).act_array(ACT_ADGEN) = '1' else
+	                        "0000000000" & unsigned(pipeline_regs(ST_ADG_EX).instr_word(13 downto 8));
+	ymem_ctrl_in.wr_en   <= '1' when pipeline_regs(ST_ADG_EX).act_array(ACT_Y_MEM_WR) = '1' else '0';
+	ymem_ctrl_in.data_in <= rf_Y_bus_data_out when pipeline_regs(ST_ADG_EX).act_array(ACT_Y_BUS_RD) = '1' or
+	                                               pipeline_regs(ST_ADG_EX).act_array(ACT_L_BUS_RD) = '1'  else
+	                        exec_dst_operand;
+
+end architecture rtl;
diff --git a/FireBee/trunk/vhdl/dsp56k/src/reg_file.vhd b/FireBee/trunk/vhdl/dsp56k/src/reg_file.vhd
new file mode 100644
index 0000000..afeeda0
--- /dev/null
+++ b/FireBee/trunk/vhdl/dsp56k/src/reg_file.vhd
@@ -0,0 +1,686 @@
+------------------------------------------------------------------------------
+--! @file
+--! @author Matthias Alles
+--! @date 01/2009
+--! @brief Global register file, including scaler and limiter
+--!
+------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.parameter_pkg.all;
+use work.types_pkg.all;
+use work.constants_pkg.all;
+
+entity reg_file is port(
+	clk, rst          : in  std_logic;
+	register_file     : out register_file_type;
+	wr_R_port_A_valid : in  std_logic;
+	wr_R_port_A       : in  addr_wr_port_type;
+	wr_R_port_B_valid : in  std_logic;
+	wr_R_port_B       : in  addr_wr_port_type;
+	alu_wr_valid      : in  std_logic;
+	alu_wr_addr       : in  std_logic;
+	alu_wr_data       : in  signed(55 downto 0);
+	reg_wr_addr       : in  std_logic_vector(5 downto 0);
+	reg_wr_addr_valid : in  std_logic;
+	reg_wr_data       : in  std_Logic_vector(23 downto 0);
+	reg_rd_addr       : in  std_logic_vector(5 downto 0);
+	reg_rd_data       : out std_Logic_vector(23 downto 0);
+	X_bus_rd_addr     : in  std_logic_vector(1 downto 0);
+	X_bus_data_out    : out std_logic_vector(23 downto 0);
+	X_bus_wr_addr     : in  std_logic_vector(1 downto 0);
+	X_bus_wr_valid    : in  std_logic;
+	X_bus_data_in     : in  std_logic_vector(23 downto 0);
+	Y_bus_rd_addr     : in  std_logic_vector(1 downto 0);
+	Y_bus_data_out    : out std_logic_vector(23 downto 0);
+	Y_bus_wr_addr     : in  std_logic_vector(1 downto 0);
+	Y_bus_wr_valid    : in  std_logic;
+	Y_bus_data_in     : in  std_logic_vector(23 downto 0);
+	L_bus_rd_addr     : in  std_logic_vector(2 downto 0);
+	L_bus_rd_valid    : in  std_logic;
+	L_bus_wr_addr     : in  std_logic_vector(2 downto 0);
+	L_bus_wr_valid    : in  std_logic;
+	push_stack        : in  push_stack_type;
+	pop_stack         : in  pop_stack_type;
+	set_sr            : in  std_logic;
+	new_sr            : in  std_logic_vector(15 downto 0);
+	set_omr           : in  std_logic;
+	new_omr           : in  std_logic_vector(7 downto 0);
+	dec_lc            : in  std_logic;
+	set_lc            : in  std_logic;
+	new_lc            : in  unsigned(15 downto 0);
+	set_la            : in  std_logic;
+	new_la            : in  unsigned(BW_ADDRESS-1 downto 0)
+);
+end entity;
+
+
+architecture rtl of reg_file is
+
+	signal addr_r : addr_array;
+	signal addr_m : addr_array;
+	signal addr_n : addr_array;
+
+	signal loop_address : unsigned(BW_ADDRESS-1 downto 0);
+	signal loop_counter : unsigned(15 downto 0);
+
+	-- condition code register
+	signal ccr : std_logic_vector(7 downto 0);
+	-- mode register
+	signal mr  : std_logic_vector(7 downto 0);
+	-- status register = mode register + condition code register
+	signal sr  : std_logic_vector(15 downto 0);
+	-- operation mode register
+	signal omr : std_logic_vector(7 downto 0);
+
+	signal stack_pointer    : unsigned(5 downto 0);
+	signal system_stack_ssh : stack_array_type;
+	signal system_stack_ssl : stack_array_type;
+
+	signal x0 : signed(23 downto 0);
+	signal x1 : signed(23 downto 0);
+	signal y0 : signed(23 downto 0);
+	signal y1 : signed(23 downto 0);
+
+	signal a0 : signed(23 downto 0);
+	signal a1 : signed(23 downto 0);
+	signal a2 : signed(7 downto 0);
+
+	signal b0 : signed(23 downto 0);
+	signal b1 : signed(23 downto 0);
+	signal b2 : signed(7 downto 0);
+	
+	signal limited_a1 : signed(23 downto 0);
+	signal limited_b1 : signed(23 downto 0);
+	signal limited_a0 : signed(23 downto 0);
+	signal limited_b0 : signed(23 downto 0);
+	signal set_limiting_flag  : std_logic;
+	signal X_bus_rd_limited_a : std_logic;
+	signal X_bus_rd_limited_b : std_logic;
+	signal Y_bus_rd_limited_a : std_logic;
+	signal Y_bus_rd_limited_b : std_logic;
+	signal reg_rd_limited_a   : std_logic;
+	signal reg_rd_limited_b   : std_logic;
+	signal rd_limited_a       : std_logic;
+	signal rd_limited_b       : std_logic;
+
+begin
+
+
+
+	sr <= mr & ccr;
+
+	register_file.addr_r <= addr_r;
+	register_file.addr_n <= addr_n;
+	register_file.addr_m <= addr_m;
+	register_file.lc <= loop_counter;
+	register_file.la <= loop_address;
+	register_file.ccr <= ccr;
+	register_file.mr <= mr;
+	register_file.sr <= sr;
+	register_file.omr <= omr;
+	register_file.stack_pointer <= stack_pointer;
+	register_file.current_ssh <= system_stack_ssh(to_integer(stack_pointer(3 downto 0)));
+	register_file.current_ssl <= system_stack_ssl(to_integer(stack_pointer(3 downto 0)));
+	register_file.a  <= a2 & a1 & a0;
+	register_file.b  <= b2 & b1 & b0;
+	register_file.x0 <= x0;
+	register_file.x1 <= x1;
+	register_file.y0 <= y0;
+	register_file.y1 <= y1;
+
+
+	global_register_file: process(clk) is
+		variable stack_pointer_plus_1 : unsigned(3 downto 0);
+		variable reg_addr : integer range 0 to 7;
+	begin
+		if rising_edge(clk) then
+			if rst = '1' then
+				addr_r <= (others => (others => '0'));
+				addr_n <= (others => (others => '0'));
+				addr_m <= (others => (others => '1'));
+				ccr    <= (others => '0');
+				mr     <= (others => '0');
+				omr    <= (others => '0');
+				system_stack_ssl <= (others => (others => '0'));
+				system_stack_ssh <= (others => (others => '0'));
+				stack_pointer    <= (others => '0');
+				loop_counter <= (others => '0');
+				loop_address <= (others => '0');
+				x0 <= (others => '0');
+				x1 <= (others => '0');
+				y0 <= (others => '0');
+				y1 <= (others => '0');
+				a0 <= (others => '0');
+				a1 <= (others => '0');
+				a2 <= (others => '0');
+				b0 <= (others => '0');
+				b1 <= (others => '0');
+				b2 <= (others => '0');
+			else
+				reg_addr := to_integer(unsigned(reg_wr_addr(2 downto 0)));
+				-----------------------------------------------------------------------
+				-- General write port to register file using 6 bit addressing scheme
+				-----------------------------------------------------------------------
+				if reg_wr_addr_valid = '1' then
+					case reg_wr_addr(5 downto 3) is
+						-- X0, X1, Y0, Y1
+						when "000" =>
+							case reg_wr_addr(2 downto 0) is
+								when "100" =>
+									x0 <= signed(reg_wr_data);
+								when "101" =>
+									x1 <= signed(reg_wr_data);
+								when "110" =>
+									y0 <= signed(reg_wr_data);
+								when "111" =>
+									y1 <= signed(reg_wr_data);
+								when others =>
+							end case;
+
+						-- A0, B0, A2, B2, A1, B1, A, B
+						when "001" =>
+							case reg_wr_addr(2 downto 0) is
+								when "000" =>
+									a0 <= signed(reg_wr_data);
+								when "001" =>
+									b0 <= signed(reg_wr_data);
+								when "010" =>
+									a2 <= signed(reg_wr_data(7 downto 0));
+								when "011" =>
+									b2 <= signed(reg_wr_data(7 downto 0));
+								when "100" =>
+									a1 <= signed(reg_wr_data);
+								when "101" =>
+									b1 <= signed(reg_wr_data);
+								when "110" =>
+									a2 <= (others => reg_wr_data(23));
+									a1 <= signed(reg_wr_data);
+									a0 <= (others => '0');
+								when "111" =>
+									b2 <= (others => reg_wr_data(23));
+									b1 <= signed(reg_wr_data);
+									b0 <= (others => '0');
+								when others =>
+							end case;
+
+						-- R0-R7
+						when "010" =>
+							addr_r(reg_addr) <= unsigned(reg_wr_data(BW_ADDRESS-1 downto 0));
+
+						-- N0-N7
+						when "011" =>
+							addr_n(reg_addr) <= unsigned(reg_wr_data(BW_ADDRESS-1 downto 0));
+
+						-- M0-M7
+						when "100" =>
+							addr_m(reg_addr) <= unsigned(reg_wr_data(BW_ADDRESS-1 downto 0));
+
+						-- SR, OMR, SP, SSH, SSL, LA, LC
+						when "111" =>
+							case reg_wr_addr(2 downto 0) is
+								-- SR
+								when "001" =>
+									mr  <= reg_wr_data(15 downto 8);
+									ccr <= reg_wr_data( 7 downto 0);
+
+								-- OMR
+								when "010" =>
+									omr  <= reg_wr_data(7 downto 0);
+
+								-- SP
+								when "011" =>
+									stack_pointer <= unsigned(reg_wr_data(5 downto 0));
+
+								-- SSH
+								when "100" =>
+									system_stack_ssh(to_integer(stack_pointer_plus_1)) <= reg_wr_data(BW_ADDRESS-1 downto 0);
+									-- increase stack after writing
+									stack_pointer(3 downto 0) <= stack_pointer_plus_1;
+									-- test whether stack is full, if so set the stack error flag (SE)
+									if stack_pointer(3 downto 0) = "1111" then
+										stack_pointer(4) <= '1';
+									end if;
+
+								-- SSL
+								when "101" =>
+									system_stack_ssl(to_integer(stack_pointer)) <= reg_wr_data(BW_ADDRESS-1 downto 0);
+
+								-- LA
+								when "110" =>
+									loop_address <= unsigned(reg_wr_data(BW_ADDRESS-1 downto 0));
+
+								-- LC
+								when "111" =>
+									loop_counter <= unsigned(reg_wr_data(15 downto 0));
+
+								when others =>
+							end case;
+						when others =>
+					end case;
+				end if;
+
+				----------------
+				-- X BUS Write
+				----------------
+				if X_bus_wr_valid = '1' then
+					case X_bus_wr_addr is
+						when "00" =>
+							x0 <= signed(X_bus_data_in);
+						when "01" =>
+							x1 <= signed(X_bus_data_in);
+						when "10" =>
+							a2 <= (others => X_bus_data_in(23));
+							a1 <= signed(X_bus_data_in);
+							a0 <= (others => '0');
+						when others =>
+							b2 <= (others => X_bus_data_in(23));
+							b1 <= signed(X_bus_data_in);
+							b0 <= (others => '0');
+					end case;
+				end if;
+				----------------
+				-- Y BUS Write
+				----------------
+				if Y_bus_wr_valid = '1' then
+					case Y_bus_wr_addr is
+						when "00" =>
+							y0 <= signed(Y_bus_data_in);
+						when "01" =>
+							y1 <= signed(Y_bus_data_in);
+						when "10" =>
+							a2 <= (others => Y_bus_data_in(23));
+							a1 <= signed(Y_bus_data_in);
+							a0 <= (others => '0');
+						when others =>
+							b2 <= (others => Y_bus_data_in(23));
+							b1 <= signed(Y_bus_data_in);
+							b0 <= (others => '0');
+					end case;
+				end if;
+				------------------
+				-- L BUS Write
+				------------------
+				if L_bus_wr_valid = '1' then
+					case L_bus_wr_addr is
+						-- A10
+						when "000" =>
+							a1 <= signed(X_bus_data_in);
+							a0 <= signed(Y_bus_data_in);
+						-- B10
+						when "001" =>
+							b1 <= signed(X_bus_data_in);
+							b0 <= signed(Y_bus_data_in);
+						-- X
+						when "010" =>
+							x1 <= signed(X_bus_data_in);
+							x0 <= signed(Y_bus_data_in);
+						-- Y
+						when "011" =>
+							y1 <= signed(X_bus_data_in);
+							y0 <= signed(Y_bus_data_in);
+						-- A
+						when "100" =>
+							a2 <= (others => X_bus_data_in(23));
+							a1 <= signed(X_bus_data_in);
+							a0 <= signed(Y_bus_data_in);
+						-- B
+						when "101" =>
+							b2 <= (others => X_bus_data_in(23));
+							b1 <= signed(X_bus_data_in);
+							b0 <= signed(Y_bus_data_in);
+						-- AB
+						when "110" =>
+							a2 <= (others => X_bus_data_in(23));
+							a1 <= signed(X_bus_data_in);
+							a0 <= (others => '0');
+							b2 <= (others => Y_bus_data_in(23));
+							b1 <= signed(Y_bus_data_in);
+							b0 <= (others => '0');
+						-- BA
+						when others =>
+							a2 <= (others => Y_bus_data_in(23));
+							a1 <= signed(Y_bus_data_in);
+							a0 <= (others => '0');
+							b2 <= (others => X_bus_data_in(23));
+							b1 <= signed(X_bus_data_in);
+							b0 <= (others => '0');
+					end case;
+				end if;
+
+				---------------------
+				-- STATUS REGISTERS
+				---------------------
+				if set_sr = '1' then
+					ccr <= new_sr( 7 downto 0);
+					mr  <= new_sr(15 downto 8);
+				end if;
+				if set_omr = '1' then
+					omr <= new_omr;
+				end if;
+				-- data limiter active?
+				-- listing this statement after the set_sr test results
+				-- in the correct behaviour for ALU operations with parallel move
+				if set_limiting_flag = '1' then
+					ccr(6) <= '1';
+				end if;
+
+				--------------------
+				-- LOOP REGISTERS 
+				--------------------
+				if set_la = '1' then
+					loop_address <= new_la;
+				end if;
+				if set_lc = '1' then
+					loop_counter <= new_lc;
+				end if;
+				if dec_lc = '1' then
+					loop_counter <= loop_counter - 1;
+				end if;
+
+				---------------------
+				-- ADDRESS REGISTER
+				---------------------
+				if wr_R_port_A_valid = '1' then
+					addr_r(to_integer(wr_R_port_A.reg_number)) <= wr_R_port_A.reg_value;
+				end if;
+				if wr_R_port_B_valid = '1' then
+					addr_r(to_integer(wr_R_port_B.reg_number)) <= wr_R_port_B.reg_value;
+				end if;
+
+				-------------------------
+				-- ALU ACCUMULATOR WRITE
+				-------------------------
+				if alu_wr_valid = '1' then
+					if alu_wr_addr = '0' then
+						a2 <= alu_wr_data(55 downto 48);
+						a1 <= alu_wr_data(47 downto 24);
+						a0 <= alu_wr_data(23 downto  0);
+					else
+						b2 <= alu_wr_data(55 downto 48);
+						b1 <= alu_wr_data(47 downto 24);
+						b0 <= alu_wr_data(23 downto  0);
+					end if;
+				end if;
+
+				---------------------
+				-- STACK CONTROLLER 
+				---------------------
+				stack_pointer_plus_1 := stack_pointer(3 downto 0) + 1;
+				if push_stack.valid = '1' then
+					-- increase stack after writing
+					stack_pointer(3 downto 0) <= stack_pointer_plus_1;
+					-- test whether stack is full, if so set the stack error flag (SE)
+					if stack_pointer(3 downto 0) = "1111" then
+						stack_pointer(4) <= '1';
+					end if;
+					case push_stack.content is
+						when PC =>
+							system_stack_ssh(to_integer(stack_pointer_plus_1)) <= std_logic_vector(push_stack.pc);
+
+						when PC_AND_SR =>
+							system_stack_ssh(to_integer(stack_pointer_plus_1)) <= std_logic_vector(push_stack.pc);
+							system_stack_ssl(to_integer(stack_pointer_plus_1)) <= SR;
+
+						when LA_AND_LC =>
+							system_stack_ssh(to_integer(stack_pointer_plus_1)) <= std_logic_vector(loop_address);
+							system_stack_ssl(to_integer(stack_pointer_plus_1)) <= std_logic_vector(loop_counter);
+
+					end case;
+				end if;
+
+				-- decrease stack pointer
+				if pop_stack.valid = '1' then
+					stack_pointer(3 downto 0) <= stack_pointer(3 downto 0) - 1;
+					-- if stack is empty set the underflow flag (bit 5, UF) and the stack error flag (bit 4, SE)
+					if stack_pointer(3 downto 0) = "0000" then
+						stack_pointer(5) <= '1';
+						stack_pointer(4) <= '1';
+					end if;
+				end if;
+			end if;
+		end if;
+	end process;
+
+
+	x_bus_rd_port: process(X_bus_rd_addr,x0,x1,a1,b1,limited_a1,limited_b1,
+	                       L_bus_rd_addr,L_bus_rd_valid,y1) is
+	begin
+		X_bus_rd_limited_a <= '0';
+		X_bus_rd_limited_b <= '0';
+		case X_bus_rd_addr is
+			when "00" =>   X_bus_data_out <= std_logic_vector(x0);
+			when "01" =>   X_bus_data_out <= std_logic_vector(x1);
+			when "10" =>   X_bus_data_out <= std_logic_vector(limited_a1); X_bus_rd_limited_a <= '1';
+			when others => X_bus_data_out <= std_logic_vector(limited_b1); X_bus_rd_limited_b <= '1';
+		end case;
+		if L_bus_rd_valid = '1' then
+			case L_bus_rd_addr is
+				when "000" =>  X_bus_data_out <= std_logic_vector(a1);
+				when "001" =>  X_bus_data_out <= std_logic_vector(b1);
+				when "010" =>  X_bus_data_out <= std_logic_vector(x1);
+				when "011" =>  X_bus_data_out <= std_logic_vector(y1);
+				when "100" =>  X_bus_data_out <= std_logic_vector(limited_a1); X_bus_rd_limited_a <= '1';
+				when "101" =>  X_bus_data_out <= std_logic_vector(limited_b1); X_bus_rd_limited_b <= '1';
+				when "110" =>  X_bus_data_out <= std_logic_vector(limited_a1); X_bus_rd_limited_a <= '1';
+				when others => X_bus_data_out <= std_logic_vector(limited_b1); X_bus_rd_limited_b <= '1';
+			end case;
+		end if;
+	end process x_bus_rd_port;
+
+	y_bus_rd_port: process(Y_bus_rd_addr,y0,y1,a1,b1,limited_a1,limited_b1,
+	                       L_bus_rd_addr,L_bus_rd_valid,a0,b0,x0,limited_a0,limited_b0) is
+	begin
+		Y_bus_rd_limited_a <= '0';
+		Y_bus_rd_limited_b <= '0';
+		case Y_bus_rd_addr is
+			when "00" =>   Y_bus_data_out <= std_logic_vector(y0);
+			when "01" =>   Y_bus_data_out <= std_logic_vector(y1);
+			when "10" =>   Y_bus_data_out <= std_logic_vector(limited_a1); Y_bus_rd_limited_a <= '1';
+			when others => Y_bus_data_out <= std_logic_vector(limited_b1); Y_bus_rd_limited_b <= '1';
+		end case;
+		if L_bus_rd_valid = '1' then
+			case L_bus_rd_addr is
+				when "000" =>  Y_bus_data_out <= std_logic_vector(a0);
+				when "001" =>  Y_bus_data_out <= std_logic_vector(b0);
+				when "010" =>  Y_bus_data_out <= std_logic_vector(x0);
+				when "011" =>  Y_bus_data_out <= std_logic_vector(y0);
+				when "100" =>  Y_bus_data_out <= std_logic_vector(limited_a0); Y_bus_rd_limited_a <= '1';
+				when "101" =>  Y_bus_data_out <= std_logic_vector(limited_b0); Y_bus_rd_limited_b <= '1';
+				when "110" =>  Y_bus_data_out <= std_logic_vector(limited_b1); Y_bus_rd_limited_b <= '1';
+				when others => Y_bus_data_out <= std_logic_vector(limited_a1); Y_bus_rd_limited_a <= '1';
+			end case;
+		end if;
+	end process y_bus_rd_port;
+
+
+	reg_rd_port: process(reg_rd_addr, x0,x1,y0,y1,a0,a1,a2,b0,b1,b2,
+	                     omr,ccr,mr,addr_r,addr_n,addr_m,stack_pointer,
+	                     loop_address,loop_counter,system_stack_ssl,system_stack_ssh) is
+		variable reg_addr : integer range 0 to 7;
+	begin
+		reg_addr := to_integer(unsigned(reg_rd_addr(2 downto 0)));
+		reg_rd_data <= (others => '0');
+		reg_rd_limited_a <= '0';
+		reg_rd_limited_b <= '0';
+
+		case reg_rd_addr(5 downto 3) is
+			-- X0, X1, Y0, Y1
+			when "000" =>
+				case reg_rd_addr(2 downto 0) is
+					when "100" =>
+						reg_rd_data <= std_logic_vector(x0);
+					when "101" =>
+						reg_rd_data <= std_logic_vector(x1);
+					when "110" =>
+						reg_rd_data <= std_logic_vector(y0);
+					when "111" =>
+						reg_rd_data <= std_logic_vector(y1);
+					when others =>
+				end case;
+
+			-- A0, B0, A2, B2, A1, B1, A, B
+			when "001" =>
+				case reg_rd_addr(2 downto 0) is
+					when "000" =>
+						reg_rd_data <= std_logic_vector(a0);
+					when "001" =>
+						reg_rd_data <= std_logic_vector(b0);
+					when "010" =>
+						-- MSBs are read as zero!
+						reg_rd_data(23 downto 8) <= (others => '0');
+						reg_rd_data(7 downto 0) <= std_logic_vector(a2);
+					when "011" =>
+						-- MSBs are read as zero!
+						reg_rd_data(23 downto 8) <= (others => '0');
+						reg_rd_data(7 downto 0) <= std_logic_vector(b2);
+					when "100" =>
+						reg_rd_data <= std_logic_vector(a1);
+					when "101" =>
+						reg_rd_data <= std_logic_vector(b1);
+					when "110" =>
+						reg_rd_data <= std_logic_vector(limited_a1);
+						reg_rd_limited_a <= '1';
+					when "111" =>
+						reg_rd_data <= std_logic_vector(limited_b1);
+						reg_rd_limited_b <= '1';
+					when others =>
+				end case;
+
+			-- R0-R7
+			when "010" =>
+				reg_rd_data <= std_logic_vector(resize(addr_r(reg_addr), 24));
+
+			-- N0-N7
+			when "011" =>
+				reg_rd_data <= std_logic_vector(resize(addr_n(reg_addr), 24));
+
+			-- M0-M7
+			when "100" =>
+				reg_rd_data <= std_logic_vector(resize(addr_m(reg_addr), 24));
+
+			-- SR, OMR, SP, SSH, SSL, LA, LC
+			when "111" =>
+				case reg_wr_addr(2 downto 0) is
+					-- SR
+					when "001" =>
+						reg_rd_data(23 downto 16) <= (others => '0');
+						reg_rd_data(15 downto  0) <= mr & ccr;
+
+					-- OMR
+					when "010" =>
+						reg_rd_data(23 downto 8) <= (others => '0');
+						reg_rd_data( 7 downto 0) <= omr;
+
+					-- SP
+					when "011" =>
+						reg_rd_data(23 downto 6) <= (others => '0');
+						reg_rd_data(5 downto 0) <= std_logic_vector(stack_pointer);
+
+					-- SSH
+					when "100" =>
+-- TODO!
+--						system_stack_ssh(to_integer(stack_pointer_plus_1)) <= reg_wr_data(BW_ADDRESS-1 downto 0);
+--						-- increase stack after writing
+--						stack_pointer(3 downto 0) <= stack_pointer_plus_1;
+--						-- test whether stack is full, if so set the stack error flag (SE)
+--						if stack_pointer(3 downto 0) = "1111" then
+--							stack_pointer(4) <= '1';
+--						end if;
+
+					-- SSL
+					when "101" =>
+						reg_rd_data <= (others => '0');
+						reg_rd_data(BW_ADDRESS-1 downto 0) <= std_logic_vector(system_stack_ssl(to_integer(stack_pointer)));
+
+					-- LA
+					when "110" =>
+						reg_rd_data <= (others => '0');
+						reg_rd_data(BW_ADDRESS-1 downto 0) <= std_logic_vector(loop_address);
+
+					-- LC
+					when "111" =>
+						reg_rd_data <= (others => '0');
+						reg_rd_data(15 downto 0) <= std_logic_vector(loop_counter);
+
+					when others =>
+				end case;
+			when others =>
+		end case;
+	end process;
+
+	rd_limited_a <= '1' when reg_rd_limited_a = '1' or X_bus_rd_limited_a = '1' or Y_bus_rd_limited_a = '1' else '0';
+	rd_limited_b <= '1' when reg_rd_limited_b = '1' or X_bus_rd_limited_b = '1' or Y_bus_rd_limited_b = '1' else '0';
+
+	data_shifter_limiter: process(a2,a1,a0,b2,b1,b0,sr,rd_limited_a,rd_limited_b) is
+		variable scaled_a : signed(55 downto 0);
+		variable scaled_b : signed(55 downto 0);
+	begin
+
+		set_limiting_flag <= '0';
+		-----------------
+		-- DATA SCALING
+		-----------------
+		-- test against scaling bits S1, S0
+		case sr(11 downto 10) is
+			-- scale down (right shift)
+			when "01" =>
+				scaled_a := a2(7) & a2 & a1 & a0(23 downto 1);
+				scaled_b := b2(7) & b2 & b1 & b0(23 downto 1);
+			-- scale up (arithmetic left shift)
+			when "10" =>
+				scaled_a := a2(6 downto 0) & a1 & a0 & '0';
+				scaled_b := b2(6 downto 0) & b1 & b0 & '0';
+			-- "00" do not scale!
+			when others =>
+				scaled_a := a2 & a1 & a0;
+				scaled_b := b2 & b1 & b0;
+		end case;
+
+		-- only sign extension stored in a2?
+		-- Yes: No limiting needed!
+		if scaled_a(55 downto 47) = "111111111" or scaled_a(55 downto 47) = "000000000" then
+			limited_a1 <= scaled_a(47 downto 24);
+			limited_a0 <= scaled_a(23 downto  0);
+		else
+			-- positive value in a?
+			if scaled_a(55) = '0' then
+				limited_a1 <= X"7FFFFF";
+				limited_a0 <= X"FFFFFF";
+			-- negative value in a?
+			else
+				limited_a1 <= X"800000";
+				limited_a0 <= X"000000";
+			end if;
+			-- set the limit flag in the status register
+			if rd_limited_a = '1' then
+				set_limiting_flag <= '1';
+			end if;
+		end if;
+		-- only sign extension stored in b2?
+		-- Yes: No limiting needed!
+		if scaled_b(55 downto 47) = "111111111" or scaled_b(55 downto 47) = "000000000" then
+			limited_b1 <= scaled_b(47 downto 24);
+			limited_b0 <= scaled_b(23 downto  0);
+		else
+			-- positive value in b?
+			if scaled_b(55) = '0' then
+				limited_b1 <= X"7FFFFF";
+				limited_b0 <= X"FFFFFF";
+			-- negative value in b?
+			else
+				limited_b1 <= X"800000";
+				limited_b0 <= X"000000";
+			end if;
+			-- set the limit flag in the status register
+			if rd_limited_b = '1' then
+				set_limiting_flag <= '1';
+			end if;
+		end if;
+
+	end process;
+
+
+end architecture rtl;
diff --git a/FireBee/trunk/vhdl/dsp56k/src/types_pkg.vhd b/FireBee/trunk/vhdl/dsp56k/src/types_pkg.vhd
new file mode 100644
index 0000000..f0f1175
--- /dev/null
+++ b/FireBee/trunk/vhdl/dsp56k/src/types_pkg.vhd
@@ -0,0 +1,182 @@
+------------------------------------------------------------------------------
+--! @file
+--! @author Matthias Alles
+--! @date 01/2009
+--! @brief Global types
+--!
+------------------------------------------------------------------------------
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.parameter_pkg.all;
+
+
+
+package types_pkg is
+
+	-- the different addressing modes
+	type ADGen_mode_type is (NOP,
+	                         POST_MIN_N,
+	                         POST_PLUS_N,
+	                         POST_MIN_1,
+	                         POST_PLUS_1,
+	                         INDEXED_N,
+	                         PRE_MIN_1,
+	                         ABSOLUTE,
+	                         IMMEDIATE);
+
+	------------------------
+	-- Decoded instructions
+	------------------------
+	type instructions_type is (
+	INSTR_NOP     ,
+	INSTR_RTI     ,
+	INSTR_ILLEGAL ,
+	INSTR_SWI     ,
+	INSTR_RTS     ,
+	INSTR_RESET   ,
+	INSTR_WAIT    ,
+	INSTR_STOP    ,
+	INSTR_ENDDO   ,
+	INSTR_ANDI    ,
+	INSTR_ORI     ,
+	INSTR_DIV     ,
+	INSTR_NORM    ,
+	INSTR_LUA     ,
+	INSTR_MOVEC   ,
+	INSTR_REP     ,
+	INSTR_DO      ,
+	INSTR_MOVEM   ,
+	INSTR_MOVEP   ,
+	INSTR_PM_MOVEM,
+	INSTR_BCLR    ,
+	INSTR_BSET    ,
+	INSTR_JCLR    ,
+	INSTR_JSET    ,
+	INSTR_JMP     ,
+	INSTR_JCC     ,
+	INSTR_BCHG    ,
+	INSTR_BTST    ,
+	INSTR_JSCLR   ,
+	INSTR_JSSET   ,
+	INSTR_JSR     ,
+	INSTR_JSCC    );
+
+	type addr_array is array(0 to 7) of unsigned(BW_ADDRESS-1 downto 0);
+
+	type alu_shift_mode is (NO_SHIFT, SHIFT_LEFT, SHIFT_RIGHT, ZEROS);
+	type alu_ccr_flag is (DONT_TOUCH, CLEAR, MODIFY, SET);
+	type alu_ccr_flag_array is array(7 downto 0) of alu_ccr_flag;
+
+	type alu_ctrl_type is record
+		mul_op1 : std_logic_vector(1 downto 0); -- x0,x1,y0,y1
+		mul_op2 : std_logic_vector(1 downto 0); -- x0,x1,y0,y1
+		shift_src  : std_logic; -- a,b
+		shift_src_sign : std_logic_vector(1 downto 0); -- 00: pos, 01: neg, 10: sign dependant, 11: reserved
+		shift_mode : alu_shift_mode;
+		rotate     : std_logic;  -- 0: logical shift, 1: rotate shift
+		add_src_stage_1  : std_logic_vector(2 downto 0); -- x0,x1,y0,y1,x,y,a,b
+		add_src_stage_2  : std_logic_vector(1 downto 0); -- 00: 0 , 01: add_src_1, 10: mul_result, 11: reserved
+		add_src_sign   : std_logic_vector(1 downto 0); -- 00: pos, 01: neg, 10: sign dependant, 11: reserved
+		logic_function : std_logic_vector(2 downto 0);  -- 000: none, 001: and, 010: or, 011: eor, 100: not
+		word_24_update : std_logic;  -- only accumulator bits 47 downto 24 affected?
+		rounding_used  : std_logic_vector(1 downto 0); -- 00: no rounding, 01: rounding, 10: add carry, 11: subtract carry
+		store_result   : std_logic; -- 0: do not update accumulator, 1: update accumulator
+		dst_accu       : std_logic; -- 0: a, 1: b
+		div_instr      : std_logic; -- DIV instruction? Special ALU operations needed!
+		norm_instr     : std_logic; -- NORM instruction? Special ALU operations needed!
+		ccr_flags_ctrl : alu_ccr_flag_array;
+	end record;
+
+	type pipeline_signals is record
+		instr_word: std_logic_vector(23 downto 0);
+		pc        : unsigned(BW_ADDRESS-1 downto 0);
+		dble_word_instr : std_logic;
+		instr_array     : instructions_type;
+		act_array       : std_logic_vector(NUM_ACT_SIGNALS-1 downto 0);
+		dec_activate    : std_logic;
+		adgen_mode_a    : adgen_mode_type;
+		adgen_mode_b    : adgen_mode_type;
+		reg_wr_addr     : std_logic_vector(5 downto 0);
+		reg_rd_addr     : std_logic_vector(5 downto 0);
+		x_bus_rd_addr   : std_logic_vector(1 downto 0);
+		x_bus_wr_addr   : std_logic_vector(1 downto 0);
+		y_bus_rd_addr   : std_logic_vector(1 downto 0);
+		y_bus_wr_addr   : std_logic_vector(1 downto 0);
+		l_bus_addr      : std_logic_vector(2 downto 0);
+		adgen_address_x : unsigned(BW_ADDRESS-1 downto 0);
+		adgen_address_y : unsigned(BW_ADDRESS-1 downto 0);
+		RAM_out_x       : std_logic_vector(23 downto 0);
+		RAM_out_y       : std_logic_vector(23 downto 0);
+		alu_ctrl        : alu_ctrl_type;
+	end record;
+
+	type pipeline_type is array(0 to PIPELINE_DEPTH-1) of pipeline_signals;
+
+
+	type register_file_type is record 
+		a            : signed(55 downto 0);
+		b            : signed(55 downto 0);
+		x0           : signed(23 downto 0);
+		x1           : signed(23 downto 0);
+		y0           : signed(23 downto 0);
+		y1           : signed(23 downto 0);
+		la           : unsigned(BW_ADDRESS-1 downto 0);
+		lc           : unsigned(15 downto 0);
+		addr_r       : addr_array;
+		addr_n       : addr_array;
+		addr_m       : addr_array;
+		ccr          : std_logic_vector(7 downto 0);
+		mr           : std_logic_vector(7 downto 0);
+		sr           : std_logic_vector(15 downto 0);
+		omr          : std_logic_vector(7 downto 0);
+		stack_pointer    : unsigned(5 downto 0);
+--		system_stack_ssh : stack_array_type;
+--		system_stack_ssl : stack_array_type;
+		current_ssh      : std_logic_vector(BW_ADDRESS-1 downto 0);
+		current_ssl      : std_logic_vector(BW_ADDRESS-1 downto 0);
+
+	end record;
+
+	type addr_wr_port_type is record
+--		write_valid : std_logic;
+		reg_number  : unsigned(2 downto 0);
+		reg_value   : unsigned(15 downto 0);
+	end record;
+
+	type mem_ctrl_type_in is record
+		rd_addr   : unsigned(BW_ADDRESS-1 downto 0);
+		rd_en     : std_logic;
+		wr_addr   : unsigned(BW_ADDRESS-1 downto 0);
+		wr_en     : std_logic;
+		data_in   : std_logic_vector(23 downto 0);
+	end record;
+
+	type mem_ctrl_type_out is record
+		data_out       : std_logic_vector(23 downto 0);
+		data_out_valid : std_logic;
+	end record;
+
+	type memory_type is (X_MEM, Y_MEM, P_MEM);
+	---------------
+	-- STACK TYPES
+	---------------
+	type stack_array_type is array(0 to 15) of std_logic_vector(BW_ADDRESS-1 downto 0);
+
+	type push_stack_content_type is (PC, PC_AND_SR, LA_AND_LC);
+
+	type push_stack_type is record
+		valid   : std_logic;
+		pc      : unsigned(BW_ADDRESS-1 downto 0);
+		content : push_stack_content_type;
+	end record;
+
+
+--	type pop_stack_type is std_logic;
+	type pop_stack_type is record
+		valid : std_logic;
+--		content : pop_stack_content_type;
+	end record;
+
+end package types_pkg;
diff --git a/FireBee/trunk/vhdl/dsp56k/testbench/tb_pipeline.vhd b/FireBee/trunk/vhdl/dsp56k/testbench/tb_pipeline.vhd
new file mode 100644
index 0000000..e4ed829
--- /dev/null
+++ b/FireBee/trunk/vhdl/dsp56k/testbench/tb_pipeline.vhd
@@ -0,0 +1,49 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+library work;
+use work.parameter_pkg.all;
+use work.types_pkg.all;
+
+entity tb_pipeline is generic (
+	clk_period : time := 10 ns
+	);
+
+	
+end entity tb_pipeline;
+
+
+architecture uut of tb_pipeline is
+
+	signal clk : std_logic := '0';
+	signal rst : std_logic;
+
+	component pipeline is port(
+		clk, rst : std_logic
+	);
+	end component pipeline;
+
+begin
+
+
+
+	uut: pipeline port map(
+	clk => clk,
+	rst => rst
+	);
+
+	clk_gen: process
+	begin
+		wait for clk_period/2;
+		clk <= not clk;
+	end process clk_gen;
+
+	rst_gen : process 
+	begin
+		rst <= '1';
+		wait for 10 * clk_period;
+		rst <= '0';
+		wait;
+	end process rst_gen;
+
+end architecture uut;
diff --git a/firebeeV1/bin/DDRAM.elf b/firebeeV1/bin/DDRAM.elf
new file mode 100644
index 0000000..7350e7a
Binary files /dev/null and b/firebeeV1/bin/DDRAM.elf differ
diff --git a/firebeeV1/bin/DDRAM.elf.S19 b/firebeeV1/bin/DDRAM.elf.S19
new file mode 100644
index 0000000..a716ff9
--- /dev/null
+++ b/firebeeV1/bin/DDRAM.elf.S19
@@ -0,0 +1,289 @@
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diff --git a/firebeeV1/bin/DDRAM.elf.xMAP b/firebeeV1/bin/DDRAM.elf.xMAP
new file mode 100644
index 0000000..a677e37
--- /dev/null
+++ b/firebeeV1/bin/DDRAM.elf.xMAP
@@ -0,0 +1,80 @@
+
+
+#>1FE00000          ___Bas_base (linker command file)
+#>E0000000          ___BOOT_FLASH (linker command file)
+#>00800000          ___BOOT_FLASH_SIZE (linker command file)
+#>00000000          ___SDRAM (linker command file)
+#>20000000          ___SDRAM_SIZE (linker command file)
+#>FF000000          ___MBAR (linker command file)
+#>FF040000          ___MMUBAR (linker command file)
+#>FF100000          ___RAMBAR0 (linker command file)
+#>00001000          ___RAMBAR0_SIZE (linker command file)
+#>FF100FFC          ___SUP_SP (linker command file)
+#>FF101000          ___RAMBAR1 (linker command file)
+#>00001000          ___RAMBAR1_SIZE (linker command file)
+#>FF100800          _rt_mod (linker command file)
+#>FF100804          _rt_ssp (linker command file)
+#>FF100808          _rt_usp (linker command file)
+#>FF10080C          _rt_vbr (linker command file)
+#>FF100810          _rt_cacr (linker command file)
+#>FF100814          _rt_asid (linker command file)
+#>FF100818          _rt_acr0 (linker command file)
+#>FF10081C          _rt_acr1 (linker command file)
+#>FF100820          _rt_acr2 (linker command file)
+#>FF100824          _rt_acr3 (linker command file)
+#>FF100828          _rt_mmubar (linker command file)
+#>FF100844          _rt_mbar (linker command file)
+#>FF100848          _d0_save (linker command file)
+#>FF10084C          _a7_save (linker command file)
+#>FF010000          ___SYS_SRAM (linker command file)
+#>00008000          ___SYS_SRAM_SIZE (linker command file)
+
+# .userram
+
+# .code
+
+# .text
+  1FE00000 0000005C .text   _startup	(startcf.c)
+  1FE0005C 00000208 .text   BaS	(BaS.c)
+  1FE00264 000001CC .text   .text	(mmu.s)
+  1FE00264 00000000 .text   mmu_init	(mmu.s)
+  1FE00264 000001CC .text   @DummyFn3	(mmu.s)
+  1FE003F8 00000000 .text   mmutr_miss	(mmu.s)
+  1FE00430 0000072E .text   @DummyFn1	(exceptions.s)
+  1FE00430 00000000 .text   vec_init	(exceptions.s)
+  1FE00430 0000072E .text   .text	(exceptions.s)
+  1FE00B60 00000000 .text   privileg_violation	(supervisor.s)
+  1FE00B60 000005BC .text   .text	(supervisor.s)
+  1FE0111C 00000188 .text   .text	(illegal_instruction.s)
+  1FE0111C 00000188 .text   @DummyFn2	(illegal_instruction.s)
+  1FE012A2 00000000 .text   illegal_instruction	(illegal_instruction.s)
+  1FE012A2 00000000 .text   illegal_table_make	(illegal_instruction.s)
+  1FE012A4 0000003C .text   init_slt	(sysinit.c)
+  1FE012E0 00000068 .text   init_gpio	(sysinit.c)
+  1FE01348 000001C4 .text   init_seriel	(sysinit.c)
+  1FE0150C 000000F4 .text   init_ddram	(sysinit.c)
+  1FE01600 000000DC .text   init_fbcs	(sysinit.c)
+  1FE016DC 000000E0 .text   init_fpga	(sysinit.c)
+  1FE017BC 00000028 .text   warte_200us	(sysinit.c)
+  1FE017E4 00000058 .text   init_video_ddr	(sysinit.c)
+  1FE0183C 0000009C .text   init_PCI	(sysinit.c)
+  1FE018D8 0000007C .text   test_upd720101	(sysinit.c)
+  1FE01954 00000324 .text   vdi_on	(sysinit.c)
+  1FE01C78 0000023C .text   init_ac97	(sysinit.c)
+  1FE01EB4 00000094 .text   __initialize_hardware	(sysinit.c)
+#>1FE01F48          ___ROM_AT (linker command file)
+#>1FE01F48          ___DATA_ROM (linker command file)
+
+# .data
+  00000000 00000004 .data   .data	(exceptions.s)
+
+
+# Memory map:
+  v_addr   p_addr   size     name
+  00000000 00000000 00000000 .userram   userram
+  00000000 00000000 00000004 .data      userram
+  1FE00000 1FE00000 00000000 .code      code
+  1FE00000 1FE00000 00001F48 .text      code
+
+# Link start time: Fri Aug 13 14:25:01 2010
+# Link end time: Fri Aug 13 14:25:01 2010
diff --git a/firebeeV1/bin/FLASH.elf b/firebeeV1/bin/FLASH.elf
new file mode 100644
index 0000000..6dece81
Binary files /dev/null and b/firebeeV1/bin/FLASH.elf differ
diff --git a/firebeeV1/bin/FLASH.elf.S19 b/firebeeV1/bin/FLASH.elf.S19
new file mode 100644
index 0000000..27a561c
--- /dev/null
+++ b/firebeeV1/bin/FLASH.elf.S19
@@ -0,0 +1,362 @@
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diff --git a/firebeeV1/bin/FLASH.elf.xMAP b/firebeeV1/bin/FLASH.elf.xMAP
new file mode 100644
index 0000000..a049441
--- /dev/null
+++ b/firebeeV1/bin/FLASH.elf.xMAP
@@ -0,0 +1,87 @@
+
+
+#>1FE00000          ___Bas_base (linker command file)
+#>E0000000          ___BOOT_FLASH (linker command file)
+#>00800000          ___BOOT_FLASH_SIZE (linker command file)
+#>00000000          ___SDRAM (linker command file)
+#>20000000          ___SDRAM_SIZE (linker command file)
+#>60000000          ___VRAM (linker command file)
+#>FF000000          ___MBAR (linker command file)
+#>FF040000          ___MMUBAR (linker command file)
+#>FF100000          ___RAMBAR0 (linker command file)
+#>00001000          ___RAMBAR0_SIZE (linker command file)
+#>FF100FFC          ___SUP_SP (linker command file)
+#>FF101000          ___RAMBAR1 (linker command file)
+#>00001000          ___RAMBAR1_SIZE (linker command file)
+#>FF100800          _rt_mod (linker command file)
+#>FF100804          _rt_ssp (linker command file)
+#>FF100808          _rt_usp (linker command file)
+#>FF10080C          _rt_vbr (linker command file)
+#>FF100810          _rt_cacr (linker command file)
+#>FF100814          _rt_asid (linker command file)
+#>FF100818          _rt_acr0 (linker command file)
+#>FF10081C          _rt_acr1 (linker command file)
+#>FF100820          _rt_acr2 (linker command file)
+#>FF100824          _rt_acr3 (linker command file)
+#>FF100828          _rt_mmubar (linker command file)
+#>FF10082C          _rt_sr  (linker command file)
+#>FF100830          _d0_save (linker command file)
+#>FF100834          _a7_save (linker command file)
+#>FF100838          _video_tlb (linker command file)
+#>FF10083C          _video_sbt (linker command file)
+#>FF100844          _rt_mbar (linker command file)
+#>FF010000          ___SYS_SRAM (linker command file)
+#>00008000          ___SYS_SRAM_SIZE (linker command file)
+
+# .code
+
+# .text
+  E0000000 0000005C .text   _startup	(startcf.c)
+  E000005C 0000003C .text   init_slt	(sysinit.c)
+  E0000098 00000068 .text   init_gpio	(sysinit.c)
+  E0000100 000001C4 .text   init_seriel	(sysinit.c)
+  E00002C4 000000F4 .text   init_ddram	(sysinit.c)
+  E00003B8 000000DC .text   init_fbcs	(sysinit.c)
+  E0000494 00000178 .text   init_fpga	(sysinit.c)
+  E000060C 00000058 .text   init_video_ddr	(sysinit.c)
+  E0000664 0000009C .text   init_PCI	(sysinit.c)
+  E0000700 00000070 .text   test_upd720101	(sysinit.c)
+  E0000770 000003AC .text   vdi_on	(sysinit.c)
+  E0000B1C 00000248 .text   init_ac97	(sysinit.c)
+  E0000D64 00000098 .text   __initialize_hardware	(sysinit.c)
+  E0000DFC 0000001C .text   warte_10ms	(BaS.c)
+  E0000E18 0000001C .text   warte_1ms	(BaS.c)
+  E0000E34 0000001C .text   warte_100us	(BaS.c)
+  E0000E50 0000001C .text   warte_50us	(BaS.c)
+  E0000E6C 0000001C .text   warte_10us	(BaS.c)
+  E0000E88 000001FC .text   BaS	(BaS.c)
+  E0001084 0000001C .text   wait_10ms	(sd_card.c)
+  E00010A0 00000018 .text   sd_com	(sd_card.c)
+  E00010B8 00000014 .text   sd_get_status	(sd_card.c)
+  E00010CC 00000020 .text   sd_rcv_info	(sd_card.c)
+  E00010EC 00000060 .text   sd_card_idle	(sd_card.c)
+  E000114C 000004A0 .text   sd_card_init	(sd_card.c)
+  E00015EC 000001B0 .text   .text	(mmu.s)
+  E00015EC 00000000 .text   mmu_init	(mmu.s)
+  E00015EC 000001B0 .text   @DummyFn1	(mmu.s)
+  E0001760 00000000 .text   mmutr_miss	(mmu.s)
+  E000179C 000009D4 .text   @DummyFn1	(exceptions.s)
+  E000179C 00000000 .text   vec_init	(exceptions.s)
+  E000179C 000009D4 .text   .text	(exceptions.s)
+  E0002170 00000000 .text   privileg_violation	(supervisor.s)
+  E0002170 000005CA .text   .text	(supervisor.s)
+  E00026F2 00000000 .text   cpusha	(supervisor.s)
+  E000273C 0000000A .text   .text	(illegal_instruction.s)
+  E000273C 0000000A .text   @DummyFn3	(illegal_instruction.s)
+  E0002744 00000000 .text   illegal_instruction	(illegal_instruction.s)
+  E0002744 00000000 .text   illegal_table_make	(illegal_instruction.s)
+  E0002748 00000004 .text   copy_end	(last.c)
+
+
+# Memory map:
+  v_addr   p_addr   size     name
+  E0000000 E0000000 00000000 .code      code
+  E0000000 E0000000 0000274C .text      code
+
+# Link start time: Sat Aug 14 02:56:27 2010
+# Link end time: Sat Aug 14 02:56:27 2010
diff --git a/firebeeV1/cfg/DDRAM.cfg b/firebeeV1/cfg/DDRAM.cfg
new file mode 100644
index 0000000..7545850
--- /dev/null
+++ b/firebeeV1/cfg/DDRAM.cfg
@@ -0,0 +1,57 @@
+; This is the board specific initialization file used in CodeWarrior Embedded product for ColdFire architecture
+;        $RCSfile: M5475EVB.cfg,v $
+;        $Revision: 1.4 $   $Date: 2008/01/09 11:46:41 $
+; Please do NOT modifiy this file. If you wish to modify this file, please keep a backup copy of this file.
+
+ResetHalt
+
+;Set VBR - debugger must know this in order
+;   to do exception capture
+writecontrolreg 0x0801 0x00000000
+
+; If MBAR changes all following writes must change
+;   and if a memory configuration file is used,
+;   the reserved areas in the register block must
+;   change also.
+;Turn on MBAR at 0xFF00_0000
+writecontrolreg 0x0C0F 0xFF000000
+
+;Turn on RAMBAR0 at address FF10_0000 
+writecontrolreg 0x0C04 0xFF100035
+
+;Turn on RAMBAR1 at address FF10_1000 
+writecontrolreg 0x0C05 0xFF101035
+
+;Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes)
+writemem.l 0xFF000500 0xE0000000;
+writemem.l 0xFF000508 0x00101980;  16-bit port
+writemem.l 0xFF000504 0x007F0001;
+
+;SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes
+writemem.l 0xFF000004 0x000002AA;   SDRAMDS configuration
+writemem.l 0xFF000020 0x0000001A;   SDRAM CS0 configuration (128Mbytes 0000_0000 - 07FF_FFFF)
+writemem.l 0xFF000024 0x0800001A;   SDRAM CS1 configuration (128Mbytes 0800_0000 - 0FFF_FFFF)
+writemem.l 0xFF000028 0x1000001A;   SDRAM CS2 configuration (128Mbytes 1000_0000 - 07FF_FFFF)
+writemem.l 0xFF00002C 0x1800001A;   SDRAM CS3 configuration (128Mbytes 1800_0000 - 1FFF_FFFF)
+;writemem.l 0xFF000108 0x73611730;   SDCFG1
+writemem.l 0xFF000108 0x53611730;   SDCFG1
+;writemem.l 0xFF00010C 0x46770000;   SDCFG2
+writemem.l 0xFF00010C 0x24730000;   SDCFG2
+
+;writemem.l 0xFF000104 0xE10D0002;   SDCR + IPALL
+writemem.l 0xFF000104 0xE10F0002;   SDCR + IPALL
+writemem.l 0xFF000100 0x40010000;   SDMR (write to LEMR)
+;writemem.l 0xFF000100 0x048D0000;   SDMR (write to LMR)
+writemem.l 0xFF000100 0x04890000;   SDMR (write to LMR)
+;writemem.l 0xFF000104 0xE10D0002;   SDCR + IPALL
+writemem.l 0xFF000104 0xE10F0002;   SDCR + IPALL
+;writemem.l 0xFF000104 0xE10D0004;   SDCR + IREF (first refresh)
+writemem.l 0xFF000104 0xE10F0004;   SDCR + IREF (first refresh)
+;writemem.l 0xFF000104 0xE10D0004;   SDCR + IREF (second refresh)
+writemem.l 0xFF000104 0xE10F0004;   SDCR + IREF (first refresh)
+;writemem.l 0xFF000100 0x008D0000;   SDMR (write to LMR)
+writemem.l 0xFF000100 0x00890000;   SDMR (write to LMR)
+;writemem.l 0xFF000104 0x71100F00;   SDCR (lock SDMR and enable refresh)
+writemem.l 0xFF000104 0x71100F00;   SDCR (lock SDMR and enable refresh)
+
+delay 1000
diff --git a/firebeeV1/cfg/DDRAM.mem b/firebeeV1/cfg/DDRAM.mem
new file mode 100644
index 0000000..1bc400b
--- /dev/null
+++ b/firebeeV1/cfg/DDRAM.mem
@@ -0,0 +1,47 @@
+// Memory Configuration File
+//
+// Description:
+//  A memory configuration file contains commands that define the legally accessible
+//  areas of memory for your specific board. Useful for example when the debugger
+//  tries to display the content of a "char *" variable, that has not yet been initialized.
+//  In this case the debugger may try to read from a bogus address, which could cause a
+//  bus error.
+//
+// Board:
+//  LogicPD COLDARI1
+//
+// Reference:
+//  MCF5475RM.pdf
+
+
+// All reserved ranges read back 0xBABA...
+reservedchar 0xBA
+
+address 	MBAR_BASE 		0xFF000000 
+address 	MMUBAR_BASE 	0xFF040000
+
+usederivative "MCF5475"
+
+//         Memory Map:
+//         ----------------------------------------------------------------------
+range		0x00000000 			0x1FFFFFFF 				4 ReadWrite		// 512MB DDR SDRAM
+reserved	0x20000000 			0x5FFFFFFF
+
+range		0x60000000			0x7FFFFFFF				4 ReadWrite
+
+range		0x80000000			0xCFFFFFFF				4 ReadWrite			
+
+range		0xD0000000			0xFBFFFFFF				4 ReadWrite
+			
+reserved	0xFC000000			$MBAR_BASE-1			
+
+ 			$MBAR_BASE 			$MBAR_BASE+0x3FFFF						// Memory Mapped Registers
+range		$MBAR_BASE+0x10000	$MBAR_BASE+0x17FFC		4 ReadWrite		// 32K Internal SRAM
+
+range		$MMUBAR_BASE		$MMUBAR_BASE+0xFFFF
+reserved	$MMUBAR_BASE+1x0000	0xFF0FFFFF	     						// Added to fill gap in MMR
+
+range      	0xFF100000 			0xFF100FFF 				4 ReadWrite		// 4K SRAM0 (RAMBAR0)
+range      	0xFF101000 			0xFFFFFFFF 				4 ReadWrite		// 4K SRAM1 (RAMBAR1)
+
+
diff --git a/firebeeV1/cfg/flash.cfg b/firebeeV1/cfg/flash.cfg
new file mode 100644
index 0000000..cfa2772
--- /dev/null
+++ b/firebeeV1/cfg/flash.cfg
@@ -0,0 +1,11 @@
+; This is the board specific initialization file used in CodeWarrior Embedded product for ColdFire architecture
+;        $RCSfile: M5475EVB.cfg,v $
+;        $Revision: 1.4 $   $Date: 2008/01/09 11:46:41 $
+; Please do NOT modifiy this file. If you wish to modify this file, please keep a backup copy of this file.
+
+
+;Init CS0 (BootFLASH @ FE00_0000 - FE7F_FFFF 8Mbytes)
+writemem.l 0xFF000500 0xFE000000;
+writemem.l 0xFF000508 0x00101980;  16-bit port
+writemem.l 0xFF000504 0x007F0001;
+
diff --git a/firebeeV1/cfg/mem.cfg b/firebeeV1/cfg/mem.cfg
new file mode 100644
index 0000000..20830c0
--- /dev/null
+++ b/firebeeV1/cfg/mem.cfg
@@ -0,0 +1,48 @@
+; This is the board specific initialization file used in CodeWarrior Embedded product for ColdFire architecture
+;        $RCSfile: M5475EVB.cfg,v $
+;        $Revision: 1.4 $   $Date: 2008/01/09 11:46:41 $
+; Please do NOT modifiy this file. If you wish to modify this file, please keep a backup copy of this file.
+
+ResetHalt
+
+;Set VBR - debugger must know this in order
+;   to do exception capture
+writecontrolreg 0x0801 0x00000000
+
+; If MBAR changes all following writes must change
+;   and if a memory configuration file is used,
+;   the reserved areas in the register block must
+;   change also.
+;Turn on MBAR at 0xFF00_0000
+writecontrolreg 0x0C0F 0xFF000000
+
+;Turn on RAMBAR0 at address FF10_0000 
+writecontrolreg 0x0C04 0xFF100035
+
+;Turn on RAMBAR1 at address FF10_1000 
+writecontrolreg 0x0C05 0xFF101035
+
+;Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes)
+writemem.l 0xFF000500 0xE0000000;
+writemem.l 0xFF000508 0x00001180;  16-bit port
+writemem.l 0xFF000504 0x007F0001;
+
+;SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes
+writemem.l 0xFF000004 0x000002AA;   SDRAMDS configuration
+writemem.l 0xFF000020 0x0000001A;   SDRAM CS0 configuration (128Mbytes 0000_0000 - 07FF_FFFF)
+writemem.l 0xFF000024 0x0800001A;   SDRAM CS1 configuration (128Mbytes 0800_0000 - 0FFF_FFFF)
+writemem.l 0xFF000028 0x1000001A;   SDRAM CS2 configuration (128Mbytes 1000_0000 - 17FF_FFFF)
+writemem.l 0xFF00002C 0x1800001A;   SDRAM CS3 configuration (128Mbytes 1800_0000 - 1FFF_FFFF)
+writemem.l 0xFF000108 0x53722938;   SDCFG1
+writemem.l 0xFF00010C 0x24330000;   SDCFG2
+
+writemem.l 0xFF000104 0xE10F0002;   SDCR + IPALL
+writemem.l 0xFF000100 0x40010000;   SDMR (write to LEMR)
+writemem.l 0xFF000100 0x05890000;   SDRM (write to LMR)
+writemem.l 0xFF000104 0xE10F0002;   SDCR + IPALL
+writemem.l 0xFF000104 0xE10F0004;   SDCR + IREF (first refresh)
+writemem.l 0xFF000104 0xE10F0004;   SDCR + IREF (second refresh)
+writemem.l 0xFF000100 0x01890000;   SDMR (write to LMR)
+writemem.l 0xFF000104 0x710F0F00;   SDCR (lock SDMR and enable refresh)
+
+delay 1000
diff --git a/firebeeV1/cfg/mem.mem b/firebeeV1/cfg/mem.mem
new file mode 100644
index 0000000..46bda65
--- /dev/null
+++ b/firebeeV1/cfg/mem.mem
@@ -0,0 +1,38 @@
+// Memory Configuration File
+//
+// Description:
+//  A memory configuration file contains commands that define the legally accessible
+//  areas of memory for your specific board. Useful for example when the debugger
+//  tries to display the content of a "char *" variable, that has not yet been initialized.
+//  In this case the debugger may try to read from a bogus address, which could cause a
+//  bus error.
+//
+// Board:
+//  LogicPD COLDARI1
+//
+// Reference:
+//  MCF5475RM.pdf
+
+
+// All reserved ranges read back 0xBABA...
+reservedchar 0xBA
+
+address 	MBAR_BASE 		0xFF000000 
+address 	MMUBAR_BASE 	0xFF040000
+
+usederivative "MCF5475"
+
+//         Memory Map:
+//         ----------------------------------------------------------------------
+range		0x00000000 			0x1FFFFFFF 				4 ReadWrite		// 512MB DDR SDRAM
+reserved	0x20000000 			$MBAR_BASE-1
+
+  			$MBAR_BASE 			$MBAR_BASE+0x3FFFF		4 ReadWrite		// Memory Mapped Registers
+range		$MBAR_BASE+0x10000	$MBAR_BASE+0x17FFC		4 ReadWrite		// 32K Internal SRAM
+reserved	$MBAR_BASE+0x17FFD	$MBAR_BASE+0x1FFBF
+
+ 			$MMUBAR_BASE		$MMUBAR_BASE+0x001B
+reserved	$MMUBAR_BASE+0x001C 0xFF0FFFFF				
+
+range      	0xFF100000 			0xFF100FFF 				4 ReadWrite		// 4K SRAM0 (RAMBAR0)
+range      	0xFF101000 			0xFF101FFF 				4 ReadWrite		// 4K SRAM1 (RAMBAR1)
diff --git a/firebeeV1/firebeeV1.mcp b/firebeeV1/firebeeV1.mcp
new file mode 100644
index 0000000..10eb377
Binary files /dev/null and b/firebeeV1/firebeeV1.mcp differ
diff --git a/firebeeV1/firebeeV1_Data/CWSettingsWindows.stg b/firebeeV1/firebeeV1_Data/CWSettingsWindows.stg
new file mode 100644
index 0000000..bc8b554
Binary files /dev/null and b/firebeeV1/firebeeV1_Data/CWSettingsWindows.stg differ
diff --git a/firebeeV1/firebeeV1_Data/DDRAM/TargetDataWindows.tdt b/firebeeV1/firebeeV1_Data/DDRAM/TargetDataWindows.tdt
new file mode 100644
index 0000000..5e7f029
Binary files /dev/null and b/firebeeV1/firebeeV1_Data/DDRAM/TargetDataWindows.tdt differ
diff --git a/firebeeV1/firebeeV1_Data/FLASH/TargetDataWindows.tdt b/firebeeV1/firebeeV1_Data/FLASH/TargetDataWindows.tdt
new file mode 100644
index 0000000..6ab297f
Binary files /dev/null and b/firebeeV1/firebeeV1_Data/FLASH/TargetDataWindows.tdt differ
diff --git a/firebeeV1/flash_config.xml b/firebeeV1/flash_config.xml
new file mode 100644
index 0000000..ce2e67e
--- /dev/null
+++ b/firebeeV1/flash_config.xml
@@ -0,0 +1,47 @@
+<?xml version="1.0" encoding="iso-8859-1" standalone="no" ?>
+<fpconfig>
+
+  <targetconfwindow>
+    <usecustomsettings>true</usecustomsettings>
+    <targetprocessor>5474</targetprocessor>
+    <connection>PEMICRO_USB</connection>
+    <usetargetinit>true</usetargetinit>
+    <targetinitfile>C:\FireBee\codewarrior\firebeeV1\cfg\mem.cfg</targetinitfile>
+    <targetmembuffaddr>0x00000000</targetmembuffaddr>
+    <targetmembuffsize>0x00006000</targetmembuffsize>
+    <enablelogging>true</enablelogging>
+    <verifywrites>false</verifywrites>
+  </targetconfwindow>
+
+  <flashconfwindow>
+    <membaseaddr>0xE0000000</membaseaddr>
+    <device>M29W640DB</device>
+    <organization>4Mx16x1</organization>
+    <flashstart>0xE0000000</flashstart>
+    <flashend>0xE07FFFFF</flashend>
+  </flashconfwindow>
+
+  <programverifywindow>
+    <useselectedfile>true</useselectedfile>
+    <projbuildtargetfile>C:\FireBee\codewarrior\firebeeV1\bin\FLASH.elf.S19</projbuildtargetfile>
+    <fileiotype>Auto Detect</fileiotype>
+    <restrictaddrrange>false</restrictaddrrange>
+    <restrictaddrrangestart>0xFF800000</restrictaddrrangestart>
+    <restrictaddrrangeend>0xFFFFFFFF</restrictaddrrangeend>
+    <applyaddroffset>false</applyaddroffset>
+    <addroffset>0xC0200000</addroffset>
+  </programverifywindow>
+
+  <eraseblankcheckwindow>
+    <eraseallsectors>false</eraseallsectors>
+    <sector/>
+    <processsectorsindividually>false</processsectorsindividually>
+  </eraseblankcheckwindow>
+
+  <checksumwindow>
+    <computechecksumover>FileOnTarg</computechecksumover>
+    <addrstart>0xFF800000</addrstart>
+    <addrsize>0x007FFFFF</addrsize>
+  </checksumwindow>
+
+</fpconfig>
diff --git a/firebeeV1/hardware_diagnostic.xml b/firebeeV1/hardware_diagnostic.xml
new file mode 100644
index 0000000..b45676f
--- /dev/null
+++ b/firebeeV1/hardware_diagnostic.xml
@@ -0,0 +1,40 @@
+<?xml version="1.0" encoding="iso-8859-1" standalone="no" ?>
+<configsettings>
+
+  <confwindow>
+    <usecustomsettings>true</usecustomsettings>
+    <targetprocessor>5474</targetprocessor>
+    <connection>PEMICRO_USB</connection>
+    <usetargetinit>true</usetargetinit>
+    <targetinitfile>{CodeWarrior}\ColdFire_Support\Initialization_Files\MCF5475.cfg</targetinitfile>
+  </confwindow>
+
+  <memoryreadwritewindow>
+    <accesstype>read</accesstype>
+    <accesssize>long_word</accesssize>
+    <targetaddress>0x60001000</targetaddress>
+    <valuetowrite>FFFFFFFF</valuetowrite>
+  </memoryreadwritewindow>
+
+  <scopelooptestwindow>
+    <accesstype>read</accesstype>
+    <accesssize>long_word</accesssize>
+    <targetaddress>0x00100000</targetaddress>
+    <valuetowrite>0x67</valuetowrite>
+    <speed>1000</speed>
+  </scopelooptestwindow>
+
+  <memorytestswindow>
+    <runwalking1s>true</runwalking1s>
+    <runbusnoise>true</runbusnoise>
+    <runaddress>true</runaddress>
+    <startaddress>0x00DE1000</startaddress>
+    <endaddress>0x00DE11FF</endaddress>
+    <accesssize>long_word</accesssize>
+    <passes>1</passes>
+    <usetargetcpu>false</usetargetcpu>
+    <targetscratchmemstart>0x00000100</targetscratchmemstart>
+    <targetscratchmemend>0x0000FFFF</targetscratchmemend>
+  </memorytestswindow>
+
+</configsettings>
diff --git a/firebeeV1/headers/MCF5475.h b/firebeeV1/headers/MCF5475.h
new file mode 100644
index 0000000..8feab2d
--- /dev/null
+++ b/firebeeV1/headers/MCF5475.h
@@ -0,0 +1,93 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_H__
+#define __MCF5475_H__
+
+
+/********************************************************************/
+/*
+ * The basic data types
+ */
+
+typedef unsigned char           uint8;   /*  8 bits */
+typedef unsigned short int      uint16;  /* 16 bits */
+typedef unsigned long int       uint32;  /* 32 bits */
+
+typedef signed char             int8;    /*  8 bits */
+typedef signed short int        int16;   /* 16 bits */
+typedef signed long int         int32;   /* 32 bits */
+
+typedef volatile uint8          vuint8;  /*  8 bits */
+typedef volatile uint16         vuint16; /* 16 bits */
+typedef volatile uint32         vuint32; /* 32 bits */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#pragma define_section system ".system" far_absolute RW
+
+/***
+ * MCF5475 Derivative Memory map definitions from linker command files:
+ * __MBAR, __MMUBAR, __RAMBAR0, __RAMBAR0_SIZE, __RAMBAR1, __RAMBAR1_SIZE
+ * linker symbols must be defined in the linker command file.
+ */
+
+extern __declspec(system) uint8 __MBAR[];
+extern __declspec(system) uint8 __MMUBAR[];
+extern __declspec(system) uint8 __RAMBAR0[];
+extern __declspec(system) uint8 __RAMBAR0_SIZE[];
+extern __declspec(system) uint8 __RAMBAR1[];
+extern __declspec(system) uint8 __RAMBAR1_SIZE[];
+
+#define MBAR_ADDRESS    (uint32)__MBAR
+#define MMUBAR_ADDRESS  (uint32)__MMUBAR
+#define RAMBAR0_ADDRESS (uint32)__RAMBAR0
+#define RAMBAR0_SIZE    (uint32)__RAMBAR0_SIZE
+#define RAMBAR1_ADDRESS (uint32)__RAMBAR1
+#define RAMBAR1_SIZE    (uint32)__RAMBAR1_SIZE
+
+
+#include "MCF5475_SIU.h"
+#include "MCF5475_MMU.h"
+#include "MCF5475_SDRAMC.h"
+#include "MCF5475_XLB.h"
+#include "MCF5475_CLOCK.h"
+#include "MCF5475_FBCS.h"
+#include "MCF5475_INTC.h"
+#include "MCF5475_GPT.h"
+#include "MCF5475_SLT.h"
+#include "MCF5475_GPIO.h"
+#include "MCF5475_PAD.h"
+#include "MCF5475_PCI.h"
+#include "MCF5475_PCIARB.h"
+#include "MCF5475_EPORT.h"
+#include "MCF5475_CTM.h"
+#include "MCF5475_DMA.h"
+#include "MCF5475_PSC.h"
+#include "MCF5475_DSPI.h"
+#include "MCF5475_I2C.h"
+#include "MCF5475_FEC.h"
+#include "MCF5475_USB.h"
+#include "MCF5475_SRAM.h"
+#include "MCF5475_SEC.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif /* __MCF5475_H__ */
diff --git a/firebeeV1/headers/MCF5475_CLOCK.h b/firebeeV1/headers/MCF5475_CLOCK.h
new file mode 100644
index 0000000..96e173f
--- /dev/null
+++ b/firebeeV1/headers/MCF5475_CLOCK.h
@@ -0,0 +1,47 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_CLOCK_H__
+#define __MCF5475_CLOCK_H__
+
+
+/*********************************************************************
+*
+* Clock Module (CLOCK)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_CLOCK_SPCR                       (*(vuint32*)(&__MBAR[0x300]))
+
+
+/* Bit definitions and macros for MCF_CLOCK_SPCR */
+#define MCF_CLOCK_SPCR_MEMEN                 (0x1)
+#define MCF_CLOCK_SPCR_PCIEN                 (0x2)
+#define MCF_CLOCK_SPCR_FBEN                  (0x4)
+#define MCF_CLOCK_SPCR_CAN0EN                (0x8)
+#define MCF_CLOCK_SPCR_DMAEN                 (0x10)
+#define MCF_CLOCK_SPCR_FEC0EN                (0x20)
+#define MCF_CLOCK_SPCR_FEC1EN                (0x40)
+#define MCF_CLOCK_SPCR_USBEN                 (0x80)
+#define MCF_CLOCK_SPCR_PSCEN                 (0x200)
+#define MCF_CLOCK_SPCR_CAN1EN                (0x800)
+#define MCF_CLOCK_SPCR_CRYENA                (0x1000)
+#define MCF_CLOCK_SPCR_CRYENB                (0x2000)
+#define MCF_CLOCK_SPCR_COREN                 (0x4000)
+#define MCF_CLOCK_SPCR_PLLK                  (0x80000000)
+
+
+#endif /* __MCF5475_CLOCK_H__ */
diff --git a/firebeeV1/headers/MCF5475_CTM.h b/firebeeV1/headers/MCF5475_CTM.h
new file mode 100644
index 0000000..1b516fd
--- /dev/null
+++ b/firebeeV1/headers/MCF5475_CTM.h
@@ -0,0 +1,76 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_CTM_H__
+#define __MCF5475_CTM_H__
+
+
+/*********************************************************************
+*
+* Comm Timer Module (CTM)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_CTM_CTCR0                        (*(vuint32*)(&__MBAR[0x7F00]))
+#define MCF_CTM_CTCR1                        (*(vuint32*)(&__MBAR[0x7F04]))
+#define MCF_CTM_CTCR2                        (*(vuint32*)(&__MBAR[0x7F08]))
+#define MCF_CTM_CTCR3                        (*(vuint32*)(&__MBAR[0x7F0C]))
+#define MCF_CTM_CTCR4                        (*(vuint32*)(&__MBAR[0x7F10]))
+#define MCF_CTM_CTCR5                        (*(vuint32*)(&__MBAR[0x7F14]))
+#define MCF_CTM_CTCR6                        (*(vuint32*)(&__MBAR[0x7F18]))
+#define MCF_CTM_CTCR7                        (*(vuint32*)(&__MBAR[0x7F1C]))
+#define MCF_CTM_CTCRF(x)                     (*(vuint32*)(&__MBAR[0x7F00 + ((x)*0x4)]))
+#define MCF_CTM_CTCRV(x)                     (*(vuint32*)(&__MBAR[0x7F10 + ((x-4)*0x4)]))
+
+
+/* Bit definitions and macros for MCF_CTM_CTCRF */
+#define MCF_CTM_CTCRF_CRV(x)                 (((x)&0xFFFF)<<0)
+#define MCF_CTM_CTCRF_S(x)                   (((x)&0xF)<<0x10)
+#define MCF_CTM_CTCRF_S_CLK_1                (0)
+#define MCF_CTM_CTCRF_S_CLK_2                (0x10000)
+#define MCF_CTM_CTCRF_S_CLK_4                (0x20000)
+#define MCF_CTM_CTCRF_S_CLK_8                (0x30000)
+#define MCF_CTM_CTCRF_S_CLK_16               (0x40000)
+#define MCF_CTM_CTCRF_S_CLK_32               (0x50000)
+#define MCF_CTM_CTCRF_S_CLK_64               (0x60000)
+#define MCF_CTM_CTCRF_S_CLK_128              (0x70000)
+#define MCF_CTM_CTCRF_S_CLK_256              (0x80000)
+#define MCF_CTM_CTCRF_S_CLK_EXT              (0x90000)
+#define MCF_CTM_CTCRF_PCT(x)                 (((x)&0x7)<<0x14)
+#define MCF_CTM_CTCRF_PCT_100                (0)
+#define MCF_CTM_CTCRF_PCT_50                 (0x100000)
+#define MCF_CTM_CTCRF_PCT_25                 (0x200000)
+#define MCF_CTM_CTCRF_PCT_12p5               (0x300000)
+#define MCF_CTM_CTCRF_PCT_6p25               (0x400000)
+#define MCF_CTM_CTCRF_PCT_OFF                (0x500000)
+#define MCF_CTM_CTCRF_M                      (0x800000)
+#define MCF_CTM_CTCRF_IM                     (0x1000000)
+#define MCF_CTM_CTCRF_I                      (0x80000000)
+
+/* Bit definitions and macros for MCF_CTM_CTCRV */
+#define MCF_CTM_CTCRV_CRV(x)                 (((x)&0xFFFFFF)<<0)
+#define MCF_CTM_CTCRV_PCT(x)                 (((x)&0x7)<<0x18)
+#define MCF_CTM_CTCRV_PCT_100                (0)
+#define MCF_CTM_CTCRV_PCT_50                 (0x1000000)
+#define MCF_CTM_CTCRV_PCT_25                 (0x2000000)
+#define MCF_CTM_CTCRV_PCT_12p5               (0x3000000)
+#define MCF_CTM_CTCRV_PCT_6p25               (0x4000000)
+#define MCF_CTM_CTCRV_PCT_OFF                (0x5000000)
+#define MCF_CTM_CTCRV_M                      (0x8000000)
+#define MCF_CTM_CTCRV_S                      (0x10000000)
+
+
+#endif /* __MCF5475_CTM_H__ */
diff --git a/firebeeV1/headers/MCF5475_DMA.h b/firebeeV1/headers/MCF5475_DMA.h
new file mode 100644
index 0000000..a9667c1
--- /dev/null
+++ b/firebeeV1/headers/MCF5475_DMA.h
@@ -0,0 +1,202 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_DMA_H__
+#define __MCF5475_DMA_H__
+
+
+/*********************************************************************
+*
+* Multichannel DMA (DMA)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_DMA_TASKBAR                      (*(vuint32*)(&__MBAR[0x8000]))
+#define MCF_DMA_CP                           (*(vuint32*)(&__MBAR[0x8004]))
+#define MCF_DMA_EP                           (*(vuint32*)(&__MBAR[0x8008]))
+#define MCF_DMA_VP                           (*(vuint32*)(&__MBAR[0x800C]))
+#define MCF_DMA_PTD                          (*(vuint32*)(&__MBAR[0x8010]))
+#define MCF_DMA_DIPR                         (*(vuint32*)(&__MBAR[0x8014]))
+#define MCF_DMA_DIMR                         (*(vuint32*)(&__MBAR[0x8018]))
+#define MCF_DMA_TCR0                         (*(vuint16*)(&__MBAR[0x801C]))
+#define MCF_DMA_TCR1                         (*(vuint16*)(&__MBAR[0x801E]))
+#define MCF_DMA_TCR2                         (*(vuint16*)(&__MBAR[0x8020]))
+#define MCF_DMA_TCR3                         (*(vuint16*)(&__MBAR[0x8022]))
+#define MCF_DMA_TCR4                         (*(vuint16*)(&__MBAR[0x8024]))
+#define MCF_DMA_TCR5                         (*(vuint16*)(&__MBAR[0x8026]))
+#define MCF_DMA_TCR6                         (*(vuint16*)(&__MBAR[0x8028]))
+#define MCF_DMA_TCR7                         (*(vuint16*)(&__MBAR[0x802A]))
+#define MCF_DMA_TCR8                         (*(vuint16*)(&__MBAR[0x802C]))
+#define MCF_DMA_TCR9                         (*(vuint16*)(&__MBAR[0x802E]))
+#define MCF_DMA_TCR10                        (*(vuint16*)(&__MBAR[0x8030]))
+#define MCF_DMA_TCR11                        (*(vuint16*)(&__MBAR[0x8032]))
+#define MCF_DMA_TCR12                        (*(vuint16*)(&__MBAR[0x8034]))
+#define MCF_DMA_TCR13                        (*(vuint16*)(&__MBAR[0x8036]))
+#define MCF_DMA_TCR14                        (*(vuint16*)(&__MBAR[0x8038]))
+#define MCF_DMA_TCR15                        (*(vuint16*)(&__MBAR[0x803A]))
+#define MCF_DMA_PRIOR0                       (*(vuint8 *)(&__MBAR[0x803C]))
+#define MCF_DMA_PRIOR1                       (*(vuint8 *)(&__MBAR[0x803D]))
+#define MCF_DMA_PRIOR2                       (*(vuint8 *)(&__MBAR[0x803E]))
+#define MCF_DMA_PRIOR3                       (*(vuint8 *)(&__MBAR[0x803F]))
+#define MCF_DMA_PRIOR4                       (*(vuint8 *)(&__MBAR[0x8040]))
+#define MCF_DMA_PRIOR5                       (*(vuint8 *)(&__MBAR[0x8041]))
+#define MCF_DMA_PRIOR6                       (*(vuint8 *)(&__MBAR[0x8042]))
+#define MCF_DMA_PRIOR7                       (*(vuint8 *)(&__MBAR[0x8043]))
+#define MCF_DMA_PRIOR8                       (*(vuint8 *)(&__MBAR[0x8044]))
+#define MCF_DMA_PRIOR9                       (*(vuint8 *)(&__MBAR[0x8045]))
+#define MCF_DMA_PRIOR10                      (*(vuint8 *)(&__MBAR[0x8046]))
+#define MCF_DMA_PRIOR11                      (*(vuint8 *)(&__MBAR[0x8047]))
+#define MCF_DMA_PRIOR12                      (*(vuint8 *)(&__MBAR[0x8048]))
+#define MCF_DMA_PRIOR13                      (*(vuint8 *)(&__MBAR[0x8049]))
+#define MCF_DMA_PRIOR14                      (*(vuint8 *)(&__MBAR[0x804A]))
+#define MCF_DMA_PRIOR15                      (*(vuint8 *)(&__MBAR[0x804B]))
+#define MCF_DMA_PRIOR16                      (*(vuint8 *)(&__MBAR[0x804C]))
+#define MCF_DMA_PRIOR17                      (*(vuint8 *)(&__MBAR[0x804D]))
+#define MCF_DMA_PRIOR18                      (*(vuint8 *)(&__MBAR[0x804E]))
+#define MCF_DMA_PRIOR19                      (*(vuint8 *)(&__MBAR[0x804F]))
+#define MCF_DMA_PRIOR20                      (*(vuint8 *)(&__MBAR[0x8050]))
+#define MCF_DMA_PRIOR21                      (*(vuint8 *)(&__MBAR[0x8051]))
+#define MCF_DMA_PRIOR22                      (*(vuint8 *)(&__MBAR[0x8052]))
+#define MCF_DMA_PRIOR23                      (*(vuint8 *)(&__MBAR[0x8053]))
+#define MCF_DMA_PRIOR24                      (*(vuint8 *)(&__MBAR[0x8054]))
+#define MCF_DMA_PRIOR25                      (*(vuint8 *)(&__MBAR[0x8055]))
+#define MCF_DMA_PRIOR26                      (*(vuint8 *)(&__MBAR[0x8056]))
+#define MCF_DMA_PRIOR27                      (*(vuint8 *)(&__MBAR[0x8057]))
+#define MCF_DMA_PRIOR28                      (*(vuint8 *)(&__MBAR[0x8058]))
+#define MCF_DMA_PRIOR29                      (*(vuint8 *)(&__MBAR[0x8059]))
+#define MCF_DMA_PRIOR30                      (*(vuint8 *)(&__MBAR[0x805A]))
+#define MCF_DMA_PRIOR31                      (*(vuint8 *)(&__MBAR[0x805B]))
+#define MCF_DMA_IMCR                         (*(vuint32*)(&__MBAR[0x805C]))
+#define MCF_DMA_TSKSZ0                       (*(vuint32*)(&__MBAR[0x8060]))
+#define MCF_DMA_TSKSZ1                       (*(vuint32*)(&__MBAR[0x8064]))
+#define MCF_DMA_DBGCOMP0                     (*(vuint32*)(&__MBAR[0x8070]))
+#define MCF_DMA_DBGCOMP2                     (*(vuint32*)(&__MBAR[0x8074]))
+#define MCF_DMA_DBGCTL                       (*(vuint32*)(&__MBAR[0x8078]))
+#define MCF_DMA_TCR(x)                       (*(vuint16*)(&__MBAR[0x801C + ((x)*0x2)]))
+#define MCF_DMA_PRIOR(x)                     (*(vuint8 *)(&__MBAR[0x803C + ((x)*0x1)]))
+
+
+/* Bit definitions and macros for MCF_DMA_TASKBAR */
+#define MCF_DMA_TASKBAR_TASK_BASE_ADDRESS(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DMA_CP */
+#define MCF_DMA_CP_DESCRIPTOR_POINTER(x)     (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DMA_EP */
+#define MCF_DMA_EP_DESCRIPTOR_POINTER(x)     (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DMA_VP */
+#define MCF_DMA_VP_VARIABLE_POINTER(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DMA_PTD */
+#define MCF_DMA_PTD_PCTL0                    (0x1)
+#define MCF_DMA_PTD_PCTL1                    (0x2)
+#define MCF_DMA_PTD_PCTL13                   (0x2000)
+#define MCF_DMA_PTD_PCTL14                   (0x4000)
+#define MCF_DMA_PTD_PCTL15                   (0x8000)
+
+/* Bit definitions and macros for MCF_DMA_DIPR */
+#define MCF_DMA_DIPR_TASK(x)                 (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DMA_DIMR */
+#define MCF_DMA_DIMR_TASK(x)                 (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DMA_TCR */
+#define MCF_DMA_TCR_ASTSKNUM(x)              (((x)&0xF)<<0)
+#define MCF_DMA_TCR_HLDINITNUM               (0x20)
+#define MCF_DMA_TCR_HIPRITSKEN               (0x40)
+#define MCF_DMA_TCR_ASTRT                    (0x80)
+#define MCF_DMA_TCR_INITNUM(x)               (((x)&0x1F)<<0x8)
+#define MCF_DMA_TCR_ALWINIT                  (0x2000)
+#define MCF_DMA_TCR_V                        (0x4000)
+#define MCF_DMA_TCR_EN                       (0x8000)
+
+/* Bit definitions and macros for MCF_DMA_PRIOR */
+#define MCF_DMA_PRIOR_PRI(x)                 (((x)&0x7)<<0)
+#define MCF_DMA_PRIOR_HLD                    (0x80)
+
+/* Bit definitions and macros for MCF_DMA_IMCR */
+#define MCF_DMA_IMCR_IMC0(x)                 (((x)&0x3)<<0)
+#define MCF_DMA_IMCR_IMC1(x)                 (((x)&0x3)<<0x2)
+#define MCF_DMA_IMCR_IMC2(x)                 (((x)&0x3)<<0x4)
+#define MCF_DMA_IMCR_IMC3(x)                 (((x)&0x3)<<0x6)
+#define MCF_DMA_IMCR_IMC4(x)                 (((x)&0x3)<<0x8)
+#define MCF_DMA_IMCR_IMC5(x)                 (((x)&0x3)<<0xA)
+#define MCF_DMA_IMCR_IMC6(x)                 (((x)&0x3)<<0xC)
+#define MCF_DMA_IMCR_IMC7(x)                 (((x)&0x3)<<0xE)
+#define MCF_DMA_IMCR_IMC8(x)                 (((x)&0x3)<<0x10)
+#define MCF_DMA_IMCR_IMC9(x)                 (((x)&0x3)<<0x12)
+#define MCF_DMA_IMCR_IMC10(x)                (((x)&0x3)<<0x14)
+#define MCF_DMA_IMCR_IMC11(x)                (((x)&0x3)<<0x16)
+#define MCF_DMA_IMCR_IMC12(x)                (((x)&0x3)<<0x18)
+#define MCF_DMA_IMCR_IMC13(x)                (((x)&0x3)<<0x1A)
+#define MCF_DMA_IMCR_IMC14(x)                (((x)&0x3)<<0x1C)
+#define MCF_DMA_IMCR_IMC15(x)                (((x)&0x3)<<0x1E)
+
+/* Bit definitions and macros for MCF_DMA_TSKSZ0 */
+#define MCF_DMA_TSKSZ0_DSTSZ7(x)             (((x)&0x3)<<0)
+#define MCF_DMA_TSKSZ0_SRCSZ7(x)             (((x)&0x3)<<0x2)
+#define MCF_DMA_TSKSZ0_DSTSZ6(x)             (((x)&0x3)<<0x4)
+#define MCF_DMA_TSKSZ0_SRCSZ6(x)             (((x)&0x3)<<0x6)
+#define MCF_DMA_TSKSZ0_DSTSZ5(x)             (((x)&0x3)<<0x8)
+#define MCF_DMA_TSKSZ0_SRCSZ5(x)             (((x)&0x3)<<0xA)
+#define MCF_DMA_TSKSZ0_DSTSZ4(x)             (((x)&0x3)<<0xC)
+#define MCF_DMA_TSKSZ0_SRCSZ4(x)             (((x)&0x3)<<0xE)
+#define MCF_DMA_TSKSZ0_DSTSZ3(x)             (((x)&0x3)<<0x10)
+#define MCF_DMA_TSKSZ0_SRCSZ3(x)             (((x)&0x3)<<0x12)
+#define MCF_DMA_TSKSZ0_DSTSZ2(x)             (((x)&0x3)<<0x14)
+#define MCF_DMA_TSKSZ0_SRCSZ2(x)             (((x)&0x3)<<0x16)
+#define MCF_DMA_TSKSZ0_DSTSZ1(x)             (((x)&0x3)<<0x18)
+#define MCF_DMA_TSKSZ0_SRCSZ1(x)             (((x)&0x3)<<0x1A)
+#define MCF_DMA_TSKSZ0_DSTSZ0(x)             (((x)&0x3)<<0x1C)
+#define MCF_DMA_TSKSZ0_SRCSZ0(x)             (((x)&0x3)<<0x1E)
+
+/* Bit definitions and macros for MCF_DMA_TSKSZ1 */
+#define MCF_DMA_TSKSZ1_DSTSZ15(x)            (((x)&0x3)<<0)
+#define MCF_DMA_TSKSZ1_SRCSZ15(x)            (((x)&0x3)<<0x2)
+#define MCF_DMA_TSKSZ1_DSTSZ14(x)            (((x)&0x3)<<0x4)
+#define MCF_DMA_TSKSZ1_SRCSZ14(x)            (((x)&0x3)<<0x6)
+#define MCF_DMA_TSKSZ1_DSTSZ13(x)            (((x)&0x3)<<0x8)
+#define MCF_DMA_TSKSZ1_SRCSZ13(x)            (((x)&0x3)<<0xA)
+#define MCF_DMA_TSKSZ1_DSTSZ12(x)            (((x)&0x3)<<0xC)
+#define MCF_DMA_TSKSZ1_SRCSZ12(x)            (((x)&0x3)<<0xE)
+#define MCF_DMA_TSKSZ1_DSTSZ11(x)            (((x)&0x3)<<0x10)
+#define MCF_DMA_TSKSZ1_SRCSZ11(x)            (((x)&0x3)<<0x12)
+#define MCF_DMA_TSKSZ1_DSTSZ10(x)            (((x)&0x3)<<0x14)
+#define MCF_DMA_TSKSZ1_SRCSZ10(x)            (((x)&0x3)<<0x16)
+#define MCF_DMA_TSKSZ1_DSTSZ9(x)             (((x)&0x3)<<0x18)
+#define MCF_DMA_TSKSZ1_SRCSZ9(x)             (((x)&0x3)<<0x1A)
+#define MCF_DMA_TSKSZ1_DSTSZ8(x)             (((x)&0x3)<<0x1C)
+#define MCF_DMA_TSKSZ1_SRCSZ8(x)             (((x)&0x3)<<0x1E)
+
+/* Bit definitions and macros for MCF_DMA_DBGCOMP0 */
+#define MCF_DMA_DBGCOMP0_COMPARATOR_VALUE(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DMA_DBGCOMP2 */
+#define MCF_DMA_DBGCOMP2_COMPARATOR_VALUE(x) (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DMA_DBGCTL */
+#define MCF_DMA_DBGCTL_I                     (0x2)
+#define MCF_DMA_DBGCTL_E                     (0x4)
+#define MCF_DMA_DBGCTL_AND_OR                (0x80)
+#define MCF_DMA_DBGCTL_COMPARATOR_TYPE_2(x)  (((x)&0x7)<<0x8)
+#define MCF_DMA_DBGCTL_COMPARATOR_TYPE_1(x)  (((x)&0x7)<<0xB)
+#define MCF_DMA_DBGCTL_B                     (0x4000)
+#define MCF_DMA_DBGCTL_AA                    (0x8000)
+#define MCF_DMA_DBGCTL_BLOCK_TASKS(x)        (((x)&0xFFFF)<<0x10)
+
+
+#endif /* __MCF5475_DMA_H__ */
diff --git a/firebeeV1/headers/MCF5475_DSPI.h b/firebeeV1/headers/MCF5475_DSPI.h
new file mode 100644
index 0000000..ec4369d
--- /dev/null
+++ b/firebeeV1/headers/MCF5475_DSPI.h
@@ -0,0 +1,150 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_DSPI_H__
+#define __MCF5475_DSPI_H__
+
+
+/*********************************************************************
+*
+* DMA Serial Peripheral Interface (DSPI)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_DSPI_DMCR                        (*(vuint32*)(&__MBAR[0x8A00]))
+#define MCF_DSPI_DTCR                        (*(vuint32*)(&__MBAR[0x8A08]))
+#define MCF_DSPI_DCTAR0                      (*(vuint32*)(&__MBAR[0x8A0C]))
+#define MCF_DSPI_DCTAR1                      (*(vuint32*)(&__MBAR[0x8A10]))
+#define MCF_DSPI_DCTAR2                      (*(vuint32*)(&__MBAR[0x8A14]))
+#define MCF_DSPI_DCTAR3                      (*(vuint32*)(&__MBAR[0x8A18]))
+#define MCF_DSPI_DCTAR4                      (*(vuint32*)(&__MBAR[0x8A1C]))
+#define MCF_DSPI_DCTAR5                      (*(vuint32*)(&__MBAR[0x8A20]))
+#define MCF_DSPI_DCTAR6                      (*(vuint32*)(&__MBAR[0x8A24]))
+#define MCF_DSPI_DCTAR7                      (*(vuint32*)(&__MBAR[0x8A28]))
+#define MCF_DSPI_DSR                         (*(vuint32*)(&__MBAR[0x8A2C]))
+#define MCF_DSPI_DIRSR                       (*(vuint32*)(&__MBAR[0x8A30]))
+#define MCF_DSPI_DTFR                        (*(vuint32*)(&__MBAR[0x8A34]))
+#define MCF_DSPI_DRFR                        (*(vuint32*)(&__MBAR[0x8A38]))
+#define MCF_DSPI_DTFDR0                      (*(vuint32*)(&__MBAR[0x8A3C]))
+#define MCF_DSPI_DTFDR1                      (*(vuint32*)(&__MBAR[0x8A40]))
+#define MCF_DSPI_DTFDR2                      (*(vuint32*)(&__MBAR[0x8A44]))
+#define MCF_DSPI_DTFDR3                      (*(vuint32*)(&__MBAR[0x8A48]))
+#define MCF_DSPI_DRFDR0                      (*(vuint32*)(&__MBAR[0x8A7C]))
+#define MCF_DSPI_DRFDR1                      (*(vuint32*)(&__MBAR[0x8A80]))
+#define MCF_DSPI_DRFDR2                      (*(vuint32*)(&__MBAR[0x8A84]))
+#define MCF_DSPI_DRFDR3                      (*(vuint32*)(&__MBAR[0x8A88]))
+#define MCF_DSPI_DCTAR(x)                    (*(vuint32*)(&__MBAR[0x8A0C + ((x)*0x4)]))
+#define MCF_DSPI_DTFDR(x)                    (*(vuint32*)(&__MBAR[0x8A3C + ((x)*0x4)]))
+#define MCF_DSPI_DRFDR(x)                    (*(vuint32*)(&__MBAR[0x8A7C + ((x)*0x4)]))
+
+
+/* Bit definitions and macros for MCF_DSPI_DMCR */
+#define MCF_DSPI_DMCR_HALT                   (0x1)
+#define MCF_DSPI_DMCR_SMPL_PT(x)             (((x)&0x3)<<0x8)
+#define MCF_DSPI_DMCR_SMPL_PT_0CLK           (0)
+#define MCF_DSPI_DMCR_SMPL_PT_1CLK           (0x100)
+#define MCF_DSPI_DMCR_SMPL_PT_2CLK           (0x200)
+#define MCF_DSPI_DMCR_CRXF                   (0x400)
+#define MCF_DSPI_DMCR_CTXF                   (0x800)
+#define MCF_DSPI_DMCR_DRXF                   (0x1000)
+#define MCF_DSPI_DMCR_DTXF                   (0x2000)
+#define MCF_DSPI_DMCR_CSIS0                  (0x10000)
+#define MCF_DSPI_DMCR_CSIS2                  (0x40000)
+#define MCF_DSPI_DMCR_CSIS3                  (0x80000)
+#define MCF_DSPI_DMCR_CSIS5                  (0x200000)
+#define MCF_DSPI_DMCR_ROOE                   (0x1000000)
+#define MCF_DSPI_DMCR_PCSSE                  (0x2000000)
+#define MCF_DSPI_DMCR_MTFE                   (0x4000000)
+#define MCF_DSPI_DMCR_FRZ                    (0x8000000)
+#define MCF_DSPI_DMCR_DCONF(x)               (((x)&0x3)<<0x1C)
+#define MCF_DSPI_DMCR_CSCK                   (0x40000000)
+#define MCF_DSPI_DMCR_MSTR                   (0x80000000)
+
+/* Bit definitions and macros for MCF_DSPI_DTCR */
+#define MCF_DSPI_DTCR_SPI_TCNT(x)            (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_DSPI_DCTAR */
+#define MCF_DSPI_DCTAR_BR(x)                 (((x)&0xF)<<0)
+#define MCF_DSPI_DCTAR_DT(x)                 (((x)&0xF)<<0x4)
+#define MCF_DSPI_DCTAR_ASC(x)                (((x)&0xF)<<0x8)
+#define MCF_DSPI_DCTAR_CSSCK(x)              (((x)&0xF)<<0xC)
+#define MCF_DSPI_DCTAR_PBR(x)                (((x)&0x3)<<0x10)
+#define MCF_DSPI_DCTAR_PBR_1CLK              (0)
+#define MCF_DSPI_DCTAR_PBR_3CLK              (0x10000)
+#define MCF_DSPI_DCTAR_PBR_5CLK              (0x20000)
+#define MCF_DSPI_DCTAR_PBR_7CLK              (0x30000)
+#define MCF_DSPI_DCTAR_PDT(x)                (((x)&0x3)<<0x12)
+#define MCF_DSPI_DCTAR_PDT_1CLK              (0)
+#define MCF_DSPI_DCTAR_PDT_3CLK              (0x40000)
+#define MCF_DSPI_DCTAR_PDT_5CLK              (0x80000)
+#define MCF_DSPI_DCTAR_PDT_7CLK              (0xC0000)
+#define MCF_DSPI_DCTAR_PASC(x)               (((x)&0x3)<<0x14)
+#define MCF_DSPI_DCTAR_PASC_1CLK             (0)
+#define MCF_DSPI_DCTAR_PASC_3CLK             (0x100000)
+#define MCF_DSPI_DCTAR_PASC_5CLK             (0x200000)
+#define MCF_DSPI_DCTAR_PASC_7CLK             (0x300000)
+#define MCF_DSPI_DCTAR_PCSSCK(x)             (((x)&0x3)<<0x16)
+#define MCF_DSPI_DCTAR_LSBFE                 (0x1000000)
+#define MCF_DSPI_DCTAR_CPHA                  (0x2000000)
+#define MCF_DSPI_DCTAR_CPOL                  (0x4000000)
+#define MCF_DSPI_DCTAR_TRSZ(x)               (((x)&0xF)<<0x1B)
+
+/* Bit definitions and macros for MCF_DSPI_DSR */
+#define MCF_DSPI_DSR_RXPTR(x)                (((x)&0xF)<<0)
+#define MCF_DSPI_DSR_RXCTR(x)                (((x)&0xF)<<0x4)
+#define MCF_DSPI_DSR_TXPTR(x)                (((x)&0xF)<<0x8)
+#define MCF_DSPI_DSR_TXCTR(x)                (((x)&0xF)<<0xC)
+#define MCF_DSPI_DSR_RFDF                    (0x20000)
+#define MCF_DSPI_DSR_RFOF                    (0x80000)
+#define MCF_DSPI_DSR_TFFF                    (0x2000000)
+#define MCF_DSPI_DSR_TFUF                    (0x8000000)
+#define MCF_DSPI_DSR_EOQF                    (0x10000000)
+#define MCF_DSPI_DSR_TXRXS                   (0x40000000)
+#define MCF_DSPI_DSR_TCF                     (0x80000000)
+
+/* Bit definitions and macros for MCF_DSPI_DIRSR */
+#define MCF_DSPI_DIRSR_RFDFS                 (0x10000)
+#define MCF_DSPI_DIRSR_RFDFE                 (0x20000)
+#define MCF_DSPI_DIRSR_RFOFE                 (0x80000)
+#define MCF_DSPI_DIRSR_TFFFS                 (0x1000000)
+#define MCF_DSPI_DIRSR_TFFFE                 (0x2000000)
+#define MCF_DSPI_DIRSR_TFUFE                 (0x8000000)
+#define MCF_DSPI_DIRSR_EOQFE                 (0x10000000)
+#define MCF_DSPI_DIRSR_TCFE                  (0x80000000)
+
+/* Bit definitions and macros for MCF_DSPI_DTFR */
+#define MCF_DSPI_DTFR_TXDATA(x)              (((x)&0xFFFF)<<0)
+#define MCF_DSPI_DTFR_CS0                    (0x10000)
+#define MCF_DSPI_DTFR_CS2                    (0x40000)
+#define MCF_DSPI_DTFR_CS3                    (0x80000)
+#define MCF_DSPI_DTFR_CS5                    (0x200000)
+#define MCF_DSPI_DTFR_CTCNT                  (0x4000000)
+#define MCF_DSPI_DTFR_EOQ                    (0x8000000)
+#define MCF_DSPI_DTFR_CTAS(x)                (((x)&0x7)<<0x1C)
+#define MCF_DSPI_DTFR_CONT                   (0x80000000)
+
+/* Bit definitions and macros for MCF_DSPI_DRFR */
+#define MCF_DSPI_DRFR_RXDATA(x)              (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_DSPI_DTFDR */
+#define MCF_DSPI_DTFDR_TXDATA(x)             (((x)&0xFFFF)<<0)
+#define MCF_DSPI_DTFDR_TXCMD(x)              (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_DSPI_DRFDR */
+#define MCF_DSPI_DRFDR_RXDATA(x)             (((x)&0xFFFF)<<0)
+
+
+#endif /* __MCF5475_DSPI_H__ */
diff --git a/firebeeV1/headers/MCF5475_EPORT.h b/firebeeV1/headers/MCF5475_EPORT.h
new file mode 100644
index 0000000..6616406
--- /dev/null
+++ b/firebeeV1/headers/MCF5475_EPORT.h
@@ -0,0 +1,123 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_EPORT_H__
+#define __MCF5475_EPORT_H__
+
+
+/*********************************************************************
+*
+* Edge Port Module (EPORT)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_EPORT_EPPAR                      (*(vuint16*)(&__MBAR[0xF00]))
+#define MCF_EPORT_EPDDR                      (*(vuint8 *)(&__MBAR[0xF04]))
+#define MCF_EPORT_EPIER                      (*(vuint8 *)(&__MBAR[0xF05]))
+#define MCF_EPORT_EPDR                       (*(vuint8 *)(&__MBAR[0xF08]))
+#define MCF_EPORT_EPPDR                      (*(vuint8 *)(&__MBAR[0xF09]))
+#define MCF_EPORT_EPFR                       (*(vuint8 *)(&__MBAR[0xF0C]))
+
+
+
+/* Bit definitions and macros for MCF_EPORT_EPPAR */
+#define MCF_EPORT_EPPAR_EPPA1(x)             (((x)&0x3)<<0x2)
+#define MCF_EPORT_EPPAR_EPPA1_LEVEL          (0)
+#define MCF_EPORT_EPPAR_EPPA1_RISING         (0x4)
+#define MCF_EPORT_EPPAR_EPPA1_FALLING        (0x8)
+#define MCF_EPORT_EPPAR_EPPA1_BOTH           (0xC)
+#define MCF_EPORT_EPPAR_EPPA2(x)             (((x)&0x3)<<0x4)
+#define MCF_EPORT_EPPAR_EPPA2_LEVEL          (0)
+#define MCF_EPORT_EPPAR_EPPA2_RISING         (0x10)
+#define MCF_EPORT_EPPAR_EPPA2_FALLING        (0x20)
+#define MCF_EPORT_EPPAR_EPPA2_BOTH           (0x30)
+#define MCF_EPORT_EPPAR_EPPA3(x)             (((x)&0x3)<<0x6)
+#define MCF_EPORT_EPPAR_EPPA3_LEVEL          (0)
+#define MCF_EPORT_EPPAR_EPPA3_RISING         (0x40)
+#define MCF_EPORT_EPPAR_EPPA3_FALLING        (0x80)
+#define MCF_EPORT_EPPAR_EPPA3_BOTH           (0xC0)
+#define MCF_EPORT_EPPAR_EPPA4(x)             (((x)&0x3)<<0x8)
+#define MCF_EPORT_EPPAR_EPPA4_LEVEL          (0)
+#define MCF_EPORT_EPPAR_EPPA4_RISING         (0x100)
+#define MCF_EPORT_EPPAR_EPPA4_FALLING        (0x200)
+#define MCF_EPORT_EPPAR_EPPA4_BOTH           (0x300)
+#define MCF_EPORT_EPPAR_EPPA5(x)             (((x)&0x3)<<0xA)
+#define MCF_EPORT_EPPAR_EPPA5_LEVEL          (0)
+#define MCF_EPORT_EPPAR_EPPA5_RISING         (0x400)
+#define MCF_EPORT_EPPAR_EPPA5_FALLING        (0x800)
+#define MCF_EPORT_EPPAR_EPPA5_BOTH           (0xC00)
+#define MCF_EPORT_EPPAR_EPPA6(x)             (((x)&0x3)<<0xC)
+#define MCF_EPORT_EPPAR_EPPA6_LEVEL          (0)
+#define MCF_EPORT_EPPAR_EPPA6_RISING         (0x1000)
+#define MCF_EPORT_EPPAR_EPPA6_FALLING        (0x2000)
+#define MCF_EPORT_EPPAR_EPPA6_BOTH           (0x3000)
+#define MCF_EPORT_EPPAR_EPPA7(x)             (((x)&0x3)<<0xE)
+#define MCF_EPORT_EPPAR_EPPA7_LEVEL          (0)
+#define MCF_EPORT_EPPAR_EPPA7_RISING         (0x4000)
+#define MCF_EPORT_EPPAR_EPPA7_FALLING        (0x8000)
+#define MCF_EPORT_EPPAR_EPPA7_BOTH           (0xC000)
+#define MCF_EPORT_EPPAR_LEVEL                (0)
+#define MCF_EPORT_EPPAR_RISING               (0x1)
+#define MCF_EPORT_EPPAR_FALLING              (0x2)
+#define MCF_EPORT_EPPAR_BOTH                 (0x3)
+
+/* Bit definitions and macros for MCF_EPORT_EPDDR */
+#define MCF_EPORT_EPDDR_EPDD1                (0x2)
+#define MCF_EPORT_EPDDR_EPDD2                (0x4)
+#define MCF_EPORT_EPDDR_EPDD3                (0x8)
+#define MCF_EPORT_EPDDR_EPDD4                (0x10)
+#define MCF_EPORT_EPDDR_EPDD5                (0x20)
+#define MCF_EPORT_EPDDR_EPDD6                (0x40)
+#define MCF_EPORT_EPDDR_EPDD7                (0x80)
+
+/* Bit definitions and macros for MCF_EPORT_EPIER */
+#define MCF_EPORT_EPIER_EPIE1                (0x2)
+#define MCF_EPORT_EPIER_EPIE2                (0x4)
+#define MCF_EPORT_EPIER_EPIE3                (0x8)
+#define MCF_EPORT_EPIER_EPIE4                (0x10)
+#define MCF_EPORT_EPIER_EPIE5                (0x20)
+#define MCF_EPORT_EPIER_EPIE6                (0x40)
+#define MCF_EPORT_EPIER_EPIE7                (0x80)
+
+/* Bit definitions and macros for MCF_EPORT_EPDR */
+#define MCF_EPORT_EPDR_EPD1                  (0x2)
+#define MCF_EPORT_EPDR_EPD2                  (0x4)
+#define MCF_EPORT_EPDR_EPD3                  (0x8)
+#define MCF_EPORT_EPDR_EPD4                  (0x10)
+#define MCF_EPORT_EPDR_EPD5                  (0x20)
+#define MCF_EPORT_EPDR_EPD6                  (0x40)
+#define MCF_EPORT_EPDR_EPD7                  (0x80)
+
+/* Bit definitions and macros for MCF_EPORT_EPPDR */
+#define MCF_EPORT_EPPDR_EPPD1                (0x2)
+#define MCF_EPORT_EPPDR_EPPD2                (0x4)
+#define MCF_EPORT_EPPDR_EPPD3                (0x8)
+#define MCF_EPORT_EPPDR_EPPD4                (0x10)
+#define MCF_EPORT_EPPDR_EPPD5                (0x20)
+#define MCF_EPORT_EPPDR_EPPD6                (0x40)
+#define MCF_EPORT_EPPDR_EPPD7                (0x80)
+
+/* Bit definitions and macros for MCF_EPORT_EPFR */
+#define MCF_EPORT_EPFR_EPF1                  (0x2)
+#define MCF_EPORT_EPFR_EPF2                  (0x4)
+#define MCF_EPORT_EPFR_EPF3                  (0x8)
+#define MCF_EPORT_EPFR_EPF4                  (0x10)
+#define MCF_EPORT_EPFR_EPF5                  (0x20)
+#define MCF_EPORT_EPFR_EPF6                  (0x40)
+#define MCF_EPORT_EPFR_EPF7                  (0x80)
+
+
+#endif /* __MCF5475_EPORT_H__ */
diff --git a/firebeeV1/headers/MCF5475_FBCS.h b/firebeeV1/headers/MCF5475_FBCS.h
new file mode 100644
index 0000000..26bb585
--- /dev/null
+++ b/firebeeV1/headers/MCF5475_FBCS.h
@@ -0,0 +1,100 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_FBCS_H__
+#define __MCF5475_FBCS_H__
+
+
+/*********************************************************************
+*
+* FlexBus Chip Select Module (FBCS)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_FBCS0_CSAR                       (*(vuint32*)(&__MBAR[0x500]))
+#define MCF_FBCS0_CSMR                       (*(vuint32*)(&__MBAR[0x504]))
+#define MCF_FBCS0_CSCR                       (*(vuint32*)(&__MBAR[0x508]))
+
+#define MCF_FBCS1_CSAR                       (*(vuint32*)(&__MBAR[0x50C]))
+#define MCF_FBCS1_CSMR                       (*(vuint32*)(&__MBAR[0x510]))
+#define MCF_FBCS1_CSCR                       (*(vuint32*)(&__MBAR[0x514]))
+
+#define MCF_FBCS2_CSAR                       (*(vuint32*)(&__MBAR[0x518]))
+#define MCF_FBCS2_CSMR                       (*(vuint32*)(&__MBAR[0x51C]))
+#define MCF_FBCS2_CSCR                       (*(vuint32*)(&__MBAR[0x520]))
+
+#define MCF_FBCS3_CSAR                       (*(vuint32*)(&__MBAR[0x524]))
+#define MCF_FBCS3_CSMR                       (*(vuint32*)(&__MBAR[0x528]))
+#define MCF_FBCS3_CSCR                       (*(vuint32*)(&__MBAR[0x52C]))
+
+#define MCF_FBCS4_CSAR                       (*(vuint32*)(&__MBAR[0x530]))
+#define MCF_FBCS4_CSMR                       (*(vuint32*)(&__MBAR[0x534]))
+#define MCF_FBCS4_CSCR                       (*(vuint32*)(&__MBAR[0x538]))
+
+#define MCF_FBCS5_CSAR                       (*(vuint32*)(&__MBAR[0x53C]))
+#define MCF_FBCS5_CSMR                       (*(vuint32*)(&__MBAR[0x540]))
+#define MCF_FBCS5_CSCR                       (*(vuint32*)(&__MBAR[0x544]))
+
+#define MCF_FBCS_CSAR(x)                     (*(vuint32*)(&__MBAR[0x500 + ((x)*0xC)]))
+#define MCF_FBCS_CSMR(x)                     (*(vuint32*)(&__MBAR[0x504 + ((x)*0xC)]))
+#define MCF_FBCS_CSCR(x)                     (*(vuint32*)(&__MBAR[0x508 + ((x)*0xC)]))
+
+
+/* Bit definitions and macros for MCF_FBCS_CSAR */
+#define MCF_FBCS_CSAR_BA(x)                  ((x)&0xFFFF0000)
+
+/* Bit definitions and macros for MCF_FBCS_CSMR */
+#define MCF_FBCS_CSMR_V                      (0x1)
+#define MCF_FBCS_CSMR_WP                     (0x100)
+#define MCF_FBCS_CSMR_BAM(x)                 (((x)&0xFFFF)<<0x10)
+#define MCF_FBCS_CSMR_BAM_4G                 (0xFFFF0000)
+#define MCF_FBCS_CSMR_BAM_2G                 (0x7FFF0000)
+#define MCF_FBCS_CSMR_BAM_1G                 (0x3FFF0000)
+#define MCF_FBCS_CSMR_BAM_1024M              (0x3FFF0000)
+#define MCF_FBCS_CSMR_BAM_512M               (0x1FFF0000)
+#define MCF_FBCS_CSMR_BAM_256M               (0xFFF0000)
+#define MCF_FBCS_CSMR_BAM_128M               (0x7FF0000)
+#define MCF_FBCS_CSMR_BAM_64M                (0x3FF0000)
+#define MCF_FBCS_CSMR_BAM_32M                (0x1FF0000)
+#define MCF_FBCS_CSMR_BAM_16M                (0xFF0000)
+#define MCF_FBCS_CSMR_BAM_8M                 (0x7F0000)
+#define MCF_FBCS_CSMR_BAM_4M                 (0x3F0000)
+#define MCF_FBCS_CSMR_BAM_2M                 (0x1F0000)
+#define MCF_FBCS_CSMR_BAM_1M                 (0xF0000)
+#define MCF_FBCS_CSMR_BAM_1024K              (0xF0000)
+#define MCF_FBCS_CSMR_BAM_512K               (0x70000)
+#define MCF_FBCS_CSMR_BAM_256K               (0x30000)
+#define MCF_FBCS_CSMR_BAM_128K               (0x10000)
+#define MCF_FBCS_CSMR_BAM_64K                (0)
+
+/* Bit definitions and macros for MCF_FBCS_CSCR */
+#define MCF_FBCS_CSCR_BSTW                   (0x8)
+#define MCF_FBCS_CSCR_BSTR                   (0x10)
+#define MCF_FBCS_CSCR_BEM                    (0x20)
+#define MCF_FBCS_CSCR_PS(x)                  (((x)&0x3)<<0x6)
+#define MCF_FBCS_CSCR_PS_32                  (0)
+#define MCF_FBCS_CSCR_PS_8                   (0x40)
+#define MCF_FBCS_CSCR_PS_16                  (0x80)
+#define MCF_FBCS_CSCR_AA                     (0x100)
+#define MCF_FBCS_CSCR_WS(x)                  (((x)&0x3F)<<0xA)
+#define MCF_FBCS_CSCR_WRAH(x)                (((x)&0x3)<<0x10)
+#define MCF_FBCS_CSCR_RDAH(x)                (((x)&0x3)<<0x12)
+#define MCF_FBCS_CSCR_ASET(x)                (((x)&0x3)<<0x14)
+#define MCF_FBCS_CSCR_SWSEN                  (0x800000)
+#define MCF_FBCS_CSCR_SWS(x)                 (((x)&0x3F)<<0x1A)
+
+
+#endif /* __MCF5475_FBCS_H__ */
diff --git a/firebeeV1/headers/MCF5475_FEC.h b/firebeeV1/headers/MCF5475_FEC.h
new file mode 100644
index 0000000..01a0ae7
--- /dev/null
+++ b/firebeeV1/headers/MCF5475_FEC.h
@@ -0,0 +1,680 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_FEC_H__
+#define __MCF5475_FEC_H__
+
+
+/*********************************************************************
+*
+* Fast Ethernet Controller(FEC)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_FEC0_EIR                         (*(vuint32*)(&__MBAR[0x9004]))
+#define MCF_FEC0_EIMR                        (*(vuint32*)(&__MBAR[0x9008]))
+#define MCF_FEC0_ECR                         (*(vuint32*)(&__MBAR[0x9024]))
+#define MCF_FEC0_MMFR                        (*(vuint32*)(&__MBAR[0x9040]))
+#define MCF_FEC0_MSCR                        (*(vuint32*)(&__MBAR[0x9044]))
+#define MCF_FEC0_MIBC                        (*(vuint32*)(&__MBAR[0x9064]))
+#define MCF_FEC0_RCR                         (*(vuint32*)(&__MBAR[0x9084]))
+#define MCF_FEC0_RHR                         (*(vuint32*)(&__MBAR[0x9088]))
+#define MCF_FEC0_TCR                         (*(vuint32*)(&__MBAR[0x90C4]))
+#define MCF_FEC0_PALR                        (*(vuint32*)(&__MBAR[0x90E4]))
+#define MCF_FEC0_PAHR                        (*(vuint32*)(&__MBAR[0x90E8]))
+#define MCF_FEC0_OPD                         (*(vuint32*)(&__MBAR[0x90EC]))
+#define MCF_FEC0_IAUR                        (*(vuint32*)(&__MBAR[0x9118]))
+#define MCF_FEC0_IALR                        (*(vuint32*)(&__MBAR[0x911C]))
+#define MCF_FEC0_GAUR                        (*(vuint32*)(&__MBAR[0x9120]))
+#define MCF_FEC0_GALR                        (*(vuint32*)(&__MBAR[0x9124]))
+#define MCF_FEC0_FECTFWR                     (*(vuint32*)(&__MBAR[0x9144]))
+#define MCF_FEC0_FECRFDR                     (*(vuint32*)(&__MBAR[0x9184]))
+#define MCF_FEC0_FECRFSR                     (*(vuint32*)(&__MBAR[0x9188]))
+#define MCF_FEC0_FECRFCR                     (*(vuint32*)(&__MBAR[0x918C]))
+#define MCF_FEC0_FECRLRFP                    (*(vuint32*)(&__MBAR[0x9190]))
+#define MCF_FEC0_FECRLWFP                    (*(vuint32*)(&__MBAR[0x9194]))
+#define MCF_FEC0_FECRFAR                     (*(vuint32*)(&__MBAR[0x9198]))
+#define MCF_FEC0_FECRFRP                     (*(vuint32*)(&__MBAR[0x919C]))
+#define MCF_FEC0_FECRFWP                     (*(vuint32*)(&__MBAR[0x91A0]))
+#define MCF_FEC0_FECTFDR                     (*(vuint32*)(&__MBAR[0x91A4]))
+#define MCF_FEC0_FECTFSR                     (*(vuint32*)(&__MBAR[0x91A8]))
+#define MCF_FEC0_FECTFCR                     (*(vuint32*)(&__MBAR[0x91AC]))
+#define MCF_FEC0_FECTLRFP                    (*(vuint32*)(&__MBAR[0x91B0]))
+#define MCF_FEC0_FECTLWFP                    (*(vuint32*)(&__MBAR[0x91B4]))
+#define MCF_FEC0_FECTFAR                     (*(vuint32*)(&__MBAR[0x91B8]))
+#define MCF_FEC0_FECTFRP                     (*(vuint32*)(&__MBAR[0x91BC]))
+#define MCF_FEC0_FECTFWP                     (*(vuint32*)(&__MBAR[0x91C0]))
+#define MCF_FEC0_FECFRST                     (*(vuint32*)(&__MBAR[0x91C4]))
+#define MCF_FEC0_FECCTCWR                    (*(vuint32*)(&__MBAR[0x91C8]))
+#define MCF_FEC0_RMON_T_DROP                 (*(vuint32*)(&__MBAR[0x9200]))
+#define MCF_FEC0_RMON_T_PACKETS              (*(vuint32*)(&__MBAR[0x9204]))
+#define MCF_FEC0_RMON_T_BC_PKT               (*(vuint32*)(&__MBAR[0x9208]))
+#define MCF_FEC0_RMON_T_MC_PKT               (*(vuint32*)(&__MBAR[0x920C]))
+#define MCF_FEC0_RMON_T_CRC_ALIGN            (*(vuint32*)(&__MBAR[0x9210]))
+#define MCF_FEC0_RMON_T_UNDERSIZE            (*(vuint32*)(&__MBAR[0x9214]))
+#define MCF_FEC0_RMON_T_OVERSIZE             (*(vuint32*)(&__MBAR[0x9218]))
+#define MCF_FEC0_RMON_T_FRAG                 (*(vuint32*)(&__MBAR[0x921C]))
+#define MCF_FEC0_RMON_T_JAB                  (*(vuint32*)(&__MBAR[0x9220]))
+#define MCF_FEC0_RMON_T_COL                  (*(vuint32*)(&__MBAR[0x9224]))
+#define MCF_FEC0_RMON_T_P64                  (*(vuint32*)(&__MBAR[0x9228]))
+#define MCF_FEC0_RMON_T_P65TO127             (*(vuint32*)(&__MBAR[0x922C]))
+#define MCF_FEC0_RMON_T_P128TO255            (*(vuint32*)(&__MBAR[0x9230]))
+#define MCF_FEC0_RMON_T_P256TO511            (*(vuint32*)(&__MBAR[0x9234]))
+#define MCF_FEC0_RMON_T_P512TO1023           (*(vuint32*)(&__MBAR[0x9238]))
+#define MCF_FEC0_RMON_T_P1024TO2047          (*(vuint32*)(&__MBAR[0x923C]))
+#define MCF_FEC0_RMON_T_P_GTE2048            (*(vuint32*)(&__MBAR[0x9240]))
+#define MCF_FEC0_RMON_T_OCTETS               (*(vuint32*)(&__MBAR[0x9244]))
+#define MCF_FEC0_IEEE_T_DROP                 (*(vuint32*)(&__MBAR[0x9248]))
+#define MCF_FEC0_IEEE_T_FRAME_OK             (*(vuint32*)(&__MBAR[0x924C]))
+#define MCF_FEC0_IEEE_T_1COL                 (*(vuint32*)(&__MBAR[0x9250]))
+#define MCF_FEC0_IEEE_T_MCOL                 (*(vuint32*)(&__MBAR[0x9254]))
+#define MCF_FEC0_IEEE_T_DEF                  (*(vuint32*)(&__MBAR[0x9258]))
+#define MCF_FEC0_IEEE_T_LCOL                 (*(vuint32*)(&__MBAR[0x925C]))
+#define MCF_FEC0_IEEE_T_EXCOL                (*(vuint32*)(&__MBAR[0x9260]))
+#define MCF_FEC0_IEEE_T_MACERR               (*(vuint32*)(&__MBAR[0x9264]))
+#define MCF_FEC0_IEEE_T_CSERR                (*(vuint32*)(&__MBAR[0x9268]))
+#define MCF_FEC0_IEEE_T_SQE                  (*(vuint32*)(&__MBAR[0x926C]))
+#define MCF_FEC0_IEEE_T_FDXFC                (*(vuint32*)(&__MBAR[0x9270]))
+#define MCF_FEC0_IEEE_T_OCTETS_OK            (*(vuint32*)(&__MBAR[0x9274]))
+#define MCF_FEC0_RMON_R_DROP                 (*(vuint32*)(&__MBAR[0x9280]))
+#define MCF_FEC0_RMON_R_PACKETS              (*(vuint32*)(&__MBAR[0x9284]))
+#define MCF_FEC0_RMON_R_BC_PKT               (*(vuint32*)(&__MBAR[0x9288]))
+#define MCF_FEC0_RMON_R_MC_PKT               (*(vuint32*)(&__MBAR[0x928C]))
+#define MCF_FEC0_RMON_R_CRC_ALIGN            (*(vuint32*)(&__MBAR[0x9290]))
+#define MCF_FEC0_RMON_R_UNDERSIZE            (*(vuint32*)(&__MBAR[0x9294]))
+#define MCF_FEC0_RMON_R_OVERSIZE             (*(vuint32*)(&__MBAR[0x9298]))
+#define MCF_FEC0_RMON_R_FRAG                 (*(vuint32*)(&__MBAR[0x929C]))
+#define MCF_FEC0_RMON_R_JAB                  (*(vuint32*)(&__MBAR[0x92A0]))
+#define MCF_FEC0_RMON_R_RESVD_0              (*(vuint32*)(&__MBAR[0x92A4]))
+#define MCF_FEC0_RMON_R_P64                  (*(vuint32*)(&__MBAR[0x92A8]))
+#define MCF_FEC0_RMON_R_P65TO127             (*(vuint32*)(&__MBAR[0x92AC]))
+#define MCF_FEC0_RMON_R_P128TO255            (*(vuint32*)(&__MBAR[0x92B0]))
+#define MCF_FEC0_RMON_R_P256TO511            (*(vuint32*)(&__MBAR[0x92B4]))
+#define MCF_FEC0_RMON_R_P512TO1023           (*(vuint32*)(&__MBAR[0x92B8]))
+#define MCF_FEC0_RMON_R_P1024TO2047          (*(vuint32*)(&__MBAR[0x92BC]))
+#define MCF_FEC0_RMON_R_P_GTE2048            (*(vuint32*)(&__MBAR[0x92C0]))
+#define MCF_FEC0_RMON_R_OCTETS               (*(vuint32*)(&__MBAR[0x92C4]))
+#define MCF_FEC0_IEEE_R_DROP                 (*(vuint32*)(&__MBAR[0x92C8]))
+#define MCF_FEC0_IEEE_R_FRAME_OK             (*(vuint32*)(&__MBAR[0x92CC]))
+#define MCF_FEC0_IEEE_R_CRC                  (*(vuint32*)(&__MBAR[0x92D0]))
+#define MCF_FEC0_IEEE_R_ALIGN                (*(vuint32*)(&__MBAR[0x92D4]))
+#define MCF_FEC0_IEEE_R_MACERR               (*(vuint32*)(&__MBAR[0x92D8]))
+#define MCF_FEC0_IEEE_R_FDXFC                (*(vuint32*)(&__MBAR[0x92DC]))
+#define MCF_FEC0_IEEE_R_OCTETS_OK            (*(vuint32*)(&__MBAR[0x92E0]))
+
+#define MCF_FEC1_EIR                         (*(vuint32*)(&__MBAR[0x9804]))
+#define MCF_FEC1_EIMR                        (*(vuint32*)(&__MBAR[0x9808]))
+#define MCF_FEC1_ECR                         (*(vuint32*)(&__MBAR[0x9824]))
+#define MCF_FEC1_MMFR                        (*(vuint32*)(&__MBAR[0x9840]))
+#define MCF_FEC1_MSCR                        (*(vuint32*)(&__MBAR[0x9844]))
+#define MCF_FEC1_MIBC                        (*(vuint32*)(&__MBAR[0x9864]))
+#define MCF_FEC1_RCR                         (*(vuint32*)(&__MBAR[0x9884]))
+#define MCF_FEC1_RHR                         (*(vuint32*)(&__MBAR[0x9888]))
+#define MCF_FEC1_TCR                         (*(vuint32*)(&__MBAR[0x98C4]))
+#define MCF_FEC1_PALR                        (*(vuint32*)(&__MBAR[0x98E4]))
+#define MCF_FEC1_PAHR                        (*(vuint32*)(&__MBAR[0x98E8]))
+#define MCF_FEC1_OPD                         (*(vuint32*)(&__MBAR[0x98EC]))
+#define MCF_FEC1_IAUR                        (*(vuint32*)(&__MBAR[0x9918]))
+#define MCF_FEC1_IALR                        (*(vuint32*)(&__MBAR[0x991C]))
+#define MCF_FEC1_GAUR                        (*(vuint32*)(&__MBAR[0x9920]))
+#define MCF_FEC1_GALR                        (*(vuint32*)(&__MBAR[0x9924]))
+#define MCF_FEC1_FECTFWR                     (*(vuint32*)(&__MBAR[0x9944]))
+#define MCF_FEC1_FECRFDR                     (*(vuint32*)(&__MBAR[0x9984]))
+#define MCF_FEC1_FECRFSR                     (*(vuint32*)(&__MBAR[0x9988]))
+#define MCF_FEC1_FECRFCR                     (*(vuint32*)(&__MBAR[0x998C]))
+#define MCF_FEC1_FECRLRFP                    (*(vuint32*)(&__MBAR[0x9990]))
+#define MCF_FEC1_FECRLWFP                    (*(vuint32*)(&__MBAR[0x9994]))
+#define MCF_FEC1_FECRFAR                     (*(vuint32*)(&__MBAR[0x9998]))
+#define MCF_FEC1_FECRFRP                     (*(vuint32*)(&__MBAR[0x999C]))
+#define MCF_FEC1_FECRFWP                     (*(vuint32*)(&__MBAR[0x99A0]))
+#define MCF_FEC1_FECTFDR                     (*(vuint32*)(&__MBAR[0x99A4]))
+#define MCF_FEC1_FECTFSR                     (*(vuint32*)(&__MBAR[0x99A8]))
+#define MCF_FEC1_FECTFCR                     (*(vuint32*)(&__MBAR[0x99AC]))
+#define MCF_FEC1_FECTLRFP                    (*(vuint32*)(&__MBAR[0x99B0]))
+#define MCF_FEC1_FECTLWFP                    (*(vuint32*)(&__MBAR[0x99B4]))
+#define MCF_FEC1_FECTFAR                     (*(vuint32*)(&__MBAR[0x99B8]))
+#define MCF_FEC1_FECTFRP                     (*(vuint32*)(&__MBAR[0x99BC]))
+#define MCF_FEC1_FECTFWP                     (*(vuint32*)(&__MBAR[0x99C0]))
+#define MCF_FEC1_FECFRST                     (*(vuint32*)(&__MBAR[0x99C4]))
+#define MCF_FEC1_FECCTCWR                    (*(vuint32*)(&__MBAR[0x99C8]))
+#define MCF_FEC1_RMON_T_DROP                 (*(vuint32*)(&__MBAR[0x9A00]))
+#define MCF_FEC1_RMON_T_PACKETS              (*(vuint32*)(&__MBAR[0x9A04]))
+#define MCF_FEC1_RMON_T_BC_PKT               (*(vuint32*)(&__MBAR[0x9A08]))
+#define MCF_FEC1_RMON_T_MC_PKT               (*(vuint32*)(&__MBAR[0x9A0C]))
+#define MCF_FEC1_RMON_T_CRC_ALIGN            (*(vuint32*)(&__MBAR[0x9A10]))
+#define MCF_FEC1_RMON_T_UNDERSIZE            (*(vuint32*)(&__MBAR[0x9A14]))
+#define MCF_FEC1_RMON_T_OVERSIZE             (*(vuint32*)(&__MBAR[0x9A18]))
+#define MCF_FEC1_RMON_T_FRAG                 (*(vuint32*)(&__MBAR[0x9A1C]))
+#define MCF_FEC1_RMON_T_JAB                  (*(vuint32*)(&__MBAR[0x9A20]))
+#define MCF_FEC1_RMON_T_COL                  (*(vuint32*)(&__MBAR[0x9A24]))
+#define MCF_FEC1_RMON_T_P64                  (*(vuint32*)(&__MBAR[0x9A28]))
+#define MCF_FEC1_RMON_T_P65TO127             (*(vuint32*)(&__MBAR[0x9A2C]))
+#define MCF_FEC1_RMON_T_P128TO255            (*(vuint32*)(&__MBAR[0x9A30]))
+#define MCF_FEC1_RMON_T_P256TO511            (*(vuint32*)(&__MBAR[0x9A34]))
+#define MCF_FEC1_RMON_T_P512TO1023           (*(vuint32*)(&__MBAR[0x9A38]))
+#define MCF_FEC1_RMON_T_P1024TO2047          (*(vuint32*)(&__MBAR[0x9A3C]))
+#define MCF_FEC1_RMON_T_P_GTE2048            (*(vuint32*)(&__MBAR[0x9A40]))
+#define MCF_FEC1_RMON_T_OCTETS               (*(vuint32*)(&__MBAR[0x9A44]))
+#define MCF_FEC1_IEEE_T_DROP                 (*(vuint32*)(&__MBAR[0x9A48]))
+#define MCF_FEC1_IEEE_T_FRAME_OK             (*(vuint32*)(&__MBAR[0x9A4C]))
+#define MCF_FEC1_IEEE_T_1COL                 (*(vuint32*)(&__MBAR[0x9A50]))
+#define MCF_FEC1_IEEE_T_MCOL                 (*(vuint32*)(&__MBAR[0x9A54]))
+#define MCF_FEC1_IEEE_T_DEF                  (*(vuint32*)(&__MBAR[0x9A58]))
+#define MCF_FEC1_IEEE_T_LCOL                 (*(vuint32*)(&__MBAR[0x9A5C]))
+#define MCF_FEC1_IEEE_T_EXCOL                (*(vuint32*)(&__MBAR[0x9A60]))
+#define MCF_FEC1_IEEE_T_MACERR               (*(vuint32*)(&__MBAR[0x9A64]))
+#define MCF_FEC1_IEEE_T_CSERR                (*(vuint32*)(&__MBAR[0x9A68]))
+#define MCF_FEC1_IEEE_T_SQE                  (*(vuint32*)(&__MBAR[0x9A6C]))
+#define MCF_FEC1_IEEE_T_FDXFC                (*(vuint32*)(&__MBAR[0x9A70]))
+#define MCF_FEC1_IEEE_T_OCTETS_OK            (*(vuint32*)(&__MBAR[0x9A74]))
+#define MCF_FEC1_RMON_R_DROP                 (*(vuint32*)(&__MBAR[0x9A80]))
+#define MCF_FEC1_RMON_R_PACKETS              (*(vuint32*)(&__MBAR[0x9A84]))
+#define MCF_FEC1_RMON_R_BC_PKT               (*(vuint32*)(&__MBAR[0x9A88]))
+#define MCF_FEC1_RMON_R_MC_PKT               (*(vuint32*)(&__MBAR[0x9A8C]))
+#define MCF_FEC1_RMON_R_CRC_ALIGN            (*(vuint32*)(&__MBAR[0x9A90]))
+#define MCF_FEC1_RMON_R_UNDERSIZE            (*(vuint32*)(&__MBAR[0x9A94]))
+#define MCF_FEC1_RMON_R_OVERSIZE             (*(vuint32*)(&__MBAR[0x9A98]))
+#define MCF_FEC1_RMON_R_FRAG                 (*(vuint32*)(&__MBAR[0x9A9C]))
+#define MCF_FEC1_RMON_R_JAB                  (*(vuint32*)(&__MBAR[0x9AA0]))
+#define MCF_FEC1_RMON_R_RESVD_0              (*(vuint32*)(&__MBAR[0x9AA4]))
+#define MCF_FEC1_RMON_R_P64                  (*(vuint32*)(&__MBAR[0x9AA8]))
+#define MCF_FEC1_RMON_R_P65TO127             (*(vuint32*)(&__MBAR[0x9AAC]))
+#define MCF_FEC1_RMON_R_P128TO255            (*(vuint32*)(&__MBAR[0x9AB0]))
+#define MCF_FEC1_RMON_R_P256TO511            (*(vuint32*)(&__MBAR[0x9AB4]))
+#define MCF_FEC1_RMON_R_P512TO1023           (*(vuint32*)(&__MBAR[0x9AB8]))
+#define MCF_FEC1_RMON_R_P1024TO2047          (*(vuint32*)(&__MBAR[0x9ABC]))
+#define MCF_FEC1_RMON_R_P_GTE2048            (*(vuint32*)(&__MBAR[0x9AC0]))
+#define MCF_FEC1_RMON_R_OCTETS               (*(vuint32*)(&__MBAR[0x9AC4]))
+#define MCF_FEC1_IEEE_R_DROP                 (*(vuint32*)(&__MBAR[0x9AC8]))
+#define MCF_FEC1_IEEE_R_FRAME_OK             (*(vuint32*)(&__MBAR[0x9ACC]))
+#define MCF_FEC1_IEEE_R_CRC                  (*(vuint32*)(&__MBAR[0x9AD0]))
+#define MCF_FEC1_IEEE_R_ALIGN                (*(vuint32*)(&__MBAR[0x9AD4]))
+#define MCF_FEC1_IEEE_R_MACERR               (*(vuint32*)(&__MBAR[0x9AD8]))
+#define MCF_FEC1_IEEE_R_FDXFC                (*(vuint32*)(&__MBAR[0x9ADC]))
+#define MCF_FEC1_IEEE_R_OCTETS_OK            (*(vuint32*)(&__MBAR[0x9AE0]))
+
+#define MCF_FEC_EIR(x)                       (*(vuint32*)(&__MBAR[0x9004 + ((x)*0x800)]))
+#define MCF_FEC_EIMR(x)                      (*(vuint32*)(&__MBAR[0x9008 + ((x)*0x800)]))
+#define MCF_FEC_ECR(x)                       (*(vuint32*)(&__MBAR[0x9024 + ((x)*0x800)]))
+#define MCF_FEC_MMFR(x)                      (*(vuint32*)(&__MBAR[0x9040 + ((x)*0x800)]))
+#define MCF_FEC_MSCR(x)                      (*(vuint32*)(&__MBAR[0x9044 + ((x)*0x800)]))
+#define MCF_FEC_MIBC(x)                      (*(vuint32*)(&__MBAR[0x9064 + ((x)*0x800)]))
+#define MCF_FEC_RCR(x)                       (*(vuint32*)(&__MBAR[0x9084 + ((x)*0x800)]))
+#define MCF_FEC_RHR(x)                       (*(vuint32*)(&__MBAR[0x9088 + ((x)*0x800)]))
+#define MCF_FEC_TCR(x)                       (*(vuint32*)(&__MBAR[0x90C4 + ((x)*0x800)]))
+#define MCF_FEC_PALR(x)                      (*(vuint32*)(&__MBAR[0x90E4 + ((x)*0x800)]))
+#define MCF_FEC_PAHR(x)                      (*(vuint32*)(&__MBAR[0x90E8 + ((x)*0x800)]))
+#define MCF_FEC_OPD(x)                       (*(vuint32*)(&__MBAR[0x90EC + ((x)*0x800)]))
+#define MCF_FEC_IAUR(x)                      (*(vuint32*)(&__MBAR[0x9118 + ((x)*0x800)]))
+#define MCF_FEC_IALR(x)                      (*(vuint32*)(&__MBAR[0x911C + ((x)*0x800)]))
+#define MCF_FEC_GAUR(x)                      (*(vuint32*)(&__MBAR[0x9120 + ((x)*0x800)]))
+#define MCF_FEC_GALR(x)                      (*(vuint32*)(&__MBAR[0x9124 + ((x)*0x800)]))
+#define MCF_FEC_FECTFWR(x)                   (*(vuint32*)(&__MBAR[0x9144 + ((x)*0x800)]))
+#define MCF_FEC_FECRFDR(x)                   (*(vuint32*)(&__MBAR[0x9184 + ((x)*0x800)]))
+#define MCF_FEC_FECRFSR(x)                   (*(vuint32*)(&__MBAR[0x9188 + ((x)*0x800)]))
+#define MCF_FEC_FECRFCR(x)                   (*(vuint32*)(&__MBAR[0x918C + ((x)*0x800)]))
+#define MCF_FEC_FECRLRFP(x)                  (*(vuint32*)(&__MBAR[0x9190 + ((x)*0x800)]))
+#define MCF_FEC_FECRLWFP(x)                  (*(vuint32*)(&__MBAR[0x9194 + ((x)*0x800)]))
+#define MCF_FEC_FECRFAR(x)                   (*(vuint32*)(&__MBAR[0x9198 + ((x)*0x800)]))
+#define MCF_FEC_FECRFRP(x)                   (*(vuint32*)(&__MBAR[0x919C + ((x)*0x800)]))
+#define MCF_FEC_FECRFWP(x)                   (*(vuint32*)(&__MBAR[0x91A0 + ((x)*0x800)]))
+#define MCF_FEC_FECTFDR(x)                   (*(vuint32*)(&__MBAR[0x91A4 + ((x)*0x800)]))
+#define MCF_FEC_FECTFSR(x)                   (*(vuint32*)(&__MBAR[0x91A8 + ((x)*0x800)]))
+#define MCF_FEC_FECTFCR(x)                   (*(vuint32*)(&__MBAR[0x91AC + ((x)*0x800)]))
+#define MCF_FEC_FECTLRFP(x)                  (*(vuint32*)(&__MBAR[0x91B0 + ((x)*0x800)]))
+#define MCF_FEC_FECTLWFP(x)                  (*(vuint32*)(&__MBAR[0x91B4 + ((x)*0x800)]))
+#define MCF_FEC_FECTFAR(x)                   (*(vuint32*)(&__MBAR[0x91B8 + ((x)*0x800)]))
+#define MCF_FEC_FECTFRP(x)                   (*(vuint32*)(&__MBAR[0x91BC + ((x)*0x800)]))
+#define MCF_FEC_FECTFWP(x)                   (*(vuint32*)(&__MBAR[0x91C0 + ((x)*0x800)]))
+#define MCF_FEC_FECFRST(x)                   (*(vuint32*)(&__MBAR[0x91C4 + ((x)*0x800)]))
+#define MCF_FEC_FECCTCWR(x)                  (*(vuint32*)(&__MBAR[0x91C8 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_DROP(x)               (*(vuint32*)(&__MBAR[0x9200 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_PACKETS(x)            (*(vuint32*)(&__MBAR[0x9204 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_BC_PKT(x)             (*(vuint32*)(&__MBAR[0x9208 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_MC_PKT(x)             (*(vuint32*)(&__MBAR[0x920C + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_CRC_ALIGN(x)          (*(vuint32*)(&__MBAR[0x9210 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_UNDERSIZE(x)          (*(vuint32*)(&__MBAR[0x9214 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_OVERSIZE(x)           (*(vuint32*)(&__MBAR[0x9218 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_FRAG(x)               (*(vuint32*)(&__MBAR[0x921C + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_JAB(x)                (*(vuint32*)(&__MBAR[0x9220 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_COL(x)                (*(vuint32*)(&__MBAR[0x9224 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_P64(x)                (*(vuint32*)(&__MBAR[0x9228 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_P65TO127(x)           (*(vuint32*)(&__MBAR[0x922C + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_P128TO255(x)          (*(vuint32*)(&__MBAR[0x9230 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_P256TO511(x)          (*(vuint32*)(&__MBAR[0x9234 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_P512TO1023(x)         (*(vuint32*)(&__MBAR[0x9238 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_P1024TO2047(x)        (*(vuint32*)(&__MBAR[0x923C + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_P_GTE2048(x)          (*(vuint32*)(&__MBAR[0x9240 + ((x)*0x800)]))
+#define MCF_FEC_RMON_T_OCTETS(x)             (*(vuint32*)(&__MBAR[0x9244 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_DROP(x)               (*(vuint32*)(&__MBAR[0x9248 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_FRAME_OK(x)           (*(vuint32*)(&__MBAR[0x924C + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_1COL(x)               (*(vuint32*)(&__MBAR[0x9250 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_MCOL(x)               (*(vuint32*)(&__MBAR[0x9254 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_DEF(x)                (*(vuint32*)(&__MBAR[0x9258 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_LCOL(x)               (*(vuint32*)(&__MBAR[0x925C + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_EXCOL(x)              (*(vuint32*)(&__MBAR[0x9260 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_MACERR(x)             (*(vuint32*)(&__MBAR[0x9264 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_CSERR(x)              (*(vuint32*)(&__MBAR[0x9268 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_SQE(x)                (*(vuint32*)(&__MBAR[0x926C + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_FDXFC(x)              (*(vuint32*)(&__MBAR[0x9270 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_T_OCTETS_OK(x)          (*(vuint32*)(&__MBAR[0x9274 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_DROP(x)               (*(vuint32*)(&__MBAR[0x9280 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_PACKETS(x)            (*(vuint32*)(&__MBAR[0x9284 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_BC_PKT(x)             (*(vuint32*)(&__MBAR[0x9288 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_MC_PKT(x)             (*(vuint32*)(&__MBAR[0x928C + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_CRC_ALIGN(x)          (*(vuint32*)(&__MBAR[0x9290 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_UNDERSIZE(x)          (*(vuint32*)(&__MBAR[0x9294 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_OVERSIZE(x)           (*(vuint32*)(&__MBAR[0x9298 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_FRAG(x)               (*(vuint32*)(&__MBAR[0x929C + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_JAB(x)                (*(vuint32*)(&__MBAR[0x92A0 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_RESVD_0(x)            (*(vuint32*)(&__MBAR[0x92A4 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_P64(x)                (*(vuint32*)(&__MBAR[0x92A8 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_P65TO127(x)           (*(vuint32*)(&__MBAR[0x92AC + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_P128TO255(x)          (*(vuint32*)(&__MBAR[0x92B0 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_P256TO511(x)          (*(vuint32*)(&__MBAR[0x92B4 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_P512TO1023(x)         (*(vuint32*)(&__MBAR[0x92B8 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_P1024TO2047(x)        (*(vuint32*)(&__MBAR[0x92BC + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_P_GTE2048(x)          (*(vuint32*)(&__MBAR[0x92C0 + ((x)*0x800)]))
+#define MCF_FEC_RMON_R_OCTETS(x)             (*(vuint32*)(&__MBAR[0x92C4 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_R_DROP(x)               (*(vuint32*)(&__MBAR[0x92C8 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_R_FRAME_OK(x)           (*(vuint32*)(&__MBAR[0x92CC + ((x)*0x800)]))
+#define MCF_FEC_IEEE_R_CRC(x)                (*(vuint32*)(&__MBAR[0x92D0 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_R_ALIGN(x)              (*(vuint32*)(&__MBAR[0x92D4 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_R_MACERR(x)             (*(vuint32*)(&__MBAR[0x92D8 + ((x)*0x800)]))
+#define MCF_FEC_IEEE_R_FDXFC(x)              (*(vuint32*)(&__MBAR[0x92DC + ((x)*0x800)]))
+#define MCF_FEC_IEEE_R_OCTETS_OK(x)          (*(vuint32*)(&__MBAR[0x92E0 + ((x)*0x800)]))
+
+
+/* Bit definitions and macros for MCF_FEC_EIR */
+#define MCF_FEC_EIR_RFERR                    (0x20000)
+#define MCF_FEC_EIR_XFERR                    (0x40000)
+#define MCF_FEC_EIR_XFUN                     (0x80000)
+#define MCF_FEC_EIR_RL                       (0x100000)
+#define MCF_FEC_EIR_LC                       (0x200000)
+#define MCF_FEC_EIR_MII                      (0x800000)
+#define MCF_FEC_EIR_TXF                      (0x8000000)
+#define MCF_FEC_EIR_GRA                      (0x10000000)
+#define MCF_FEC_EIR_BABT                     (0x20000000)
+#define MCF_FEC_EIR_BABR                     (0x40000000)
+#define MCF_FEC_EIR_HBERR                    (0x80000000)
+#define MCF_FEC_EIR_CLEAR_ALL                (0xFFFFFFFF)
+
+/* Bit definitions and macros for MCF_FEC_EIMR */
+#define MCF_FEC_EIMR_RFERR                   (0x20000)
+#define MCF_FEC_EIMR_XFERR                   (0x40000)
+#define MCF_FEC_EIMR_XFUN                    (0x80000)
+#define MCF_FEC_EIMR_RL                      (0x100000)
+#define MCF_FEC_EIMR_LC                      (0x200000)
+#define MCF_FEC_EIMR_MII                     (0x800000)
+#define MCF_FEC_EIMR_TXF                     (0x8000000)
+#define MCF_FEC_EIMR_GRA                     (0x10000000)
+#define MCF_FEC_EIMR_BABT                    (0x20000000)
+#define MCF_FEC_EIMR_BABR                    (0x40000000)
+#define MCF_FEC_EIMR_HBERR                   (0x80000000)
+#define MCF_FEC_EIMR_MASK_ALL                (0)
+#define MCF_FEC_EIMR_UNMASK_ALL              (0xFFFFFFFF)
+
+/* Bit definitions and macros for MCF_FEC_ECR */
+#define MCF_FEC_ECR_RESET                    (0x1)
+#define MCF_FEC_ECR_ETHER_EN                 (0x2)
+
+/* Bit definitions and macros for MCF_FEC_MMFR */
+#define MCF_FEC_MMFR_DATA(x)                 (((x)&0xFFFF)<<0)
+#define MCF_FEC_MMFR_TA(x)                   (((x)&0x3)<<0x10)
+#define MCF_FEC_MMFR_TA_10                   (0x20000)
+#define MCF_FEC_MMFR_RA(x)                   (((x)&0x1F)<<0x12)
+#define MCF_FEC_MMFR_PA(x)                   (((x)&0x1F)<<0x17)
+#define MCF_FEC_MMFR_OP(x)                   (((x)&0x3)<<0x1C)
+#define MCF_FEC_MMFR_OP_READ                 (0x20000000)
+#define MCF_FEC_MMFR_OP_WRITE                (0x10000000)
+#define MCF_FEC_MMFR_ST(x)                   (((x)&0x3)<<0x1E)
+#define MCF_FEC_MMFR_ST_01                   (0x40000000)
+
+/* Bit definitions and macros for MCF_FEC_MSCR */
+#define MCF_FEC_MSCR_MII_SPEED(x)            (((x)&0x3F)<<0x1)
+#define MCF_FEC_MSCR_DIS_PREAMBLE            (0x80)
+#define MCF_FEC_MSCR_MII_SPEED_133           (0x1B<<0x1)
+#define MCF_FEC_MSCR_MII_SPEED_120           (0x18<<0x1)
+#define MCF_FEC_MSCR_MII_SPEED_66            (0xE<<0x1)
+#define MCF_FEC_MSCR_MII_SPEED_60            (0xC<<0x1)
+
+/* Bit definitions and macros for MCF_FEC_MIBC */
+#define MCF_FEC_MIBC_MIB_IDLE                (0x40000000)
+#define MCF_FEC_MIBC_MIB_DISABLE             (0x80000000)
+
+/* Bit definitions and macros for MCF_FEC_RCR */
+#define MCF_FEC_RCR_LOOP                     (0x1)
+#define MCF_FEC_RCR_DRT                      (0x2)
+#define MCF_FEC_RCR_MII_MODE                 (0x4)
+#define MCF_FEC_RCR_PROM                     (0x8)
+#define MCF_FEC_RCR_BC_REJ                   (0x10)
+#define MCF_FEC_RCR_FCE                      (0x20)
+#define MCF_FEC_RCR_MAX_FL(x)                (((x)&0x7FF)<<0x10)
+
+/* Bit definitions and macros for MCF_FEC_RHR */
+#define MCF_FEC_RHR_HASH(x)                  (((x)&0x3F)<<0x18)
+#define MCF_FEC_RHR_MULTCAST                 (0x40000000)
+#define MCF_FEC_RHR_FCE                      (0x80000000)
+
+/* Bit definitions and macros for MCF_FEC_TCR */
+#define MCF_FEC_TCR_GTS                      (0x1)
+#define MCF_FEC_TCR_HBC                      (0x2)
+#define MCF_FEC_TCR_FDEN                     (0x4)
+#define MCF_FEC_TCR_TFC_PAUSE                (0x8)
+#define MCF_FEC_TCR_RFC_PAUSE                (0x10)
+
+/* Bit definitions and macros for MCF_FEC_PALR */
+#define MCF_FEC_PALR_PADDR1(x)               (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_PAHR */
+#define MCF_FEC_PAHR_TYPE(x)                 (((x)&0xFFFF)<<0)
+#define MCF_FEC_PAHR_PADDR2(x)               (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_FEC_OPD */
+#define MCF_FEC_OPD_PAUSE_DUR(x)             (((x)&0xFFFF)<<0)
+#define MCF_FEC_OPD_OPCODE(x)                (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_FEC_IAUR */
+#define MCF_FEC_IAUR_IADDR1(x)               (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IALR */
+#define MCF_FEC_IALR_IADDR2(x)               (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_GAUR */
+#define MCF_FEC_GAUR_GADDR1(x)               (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_GALR */
+#define MCF_FEC_GALR_GADDR2(x)               (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECTFWR */
+#define MCF_FEC_FECTFWR_X_WMRK(x)            (((x)&0xF)<<0)
+#define MCF_FEC_FECTFWR_X_WMRK_64            (0)
+#define MCF_FEC_FECTFWR_X_WMRK_128           (0x1)
+#define MCF_FEC_FECTFWR_X_WMRK_192           (0x2)
+#define MCF_FEC_FECTFWR_X_WMRK_256           (0x3)
+#define MCF_FEC_FECTFWR_X_WMRK_320           (0x4)
+#define MCF_FEC_FECTFWR_X_WMRK_384           (0x5)
+#define MCF_FEC_FECTFWR_X_WMRK_448           (0x6)
+#define MCF_FEC_FECTFWR_X_WMRK_512           (0x7)
+#define MCF_FEC_FECTFWR_X_WMRK_576           (0x8)
+#define MCF_FEC_FECTFWR_X_WMRK_640           (0x9)
+#define MCF_FEC_FECTFWR_X_WMRK_704           (0xA)
+#define MCF_FEC_FECTFWR_X_WMRK_768           (0xB)
+#define MCF_FEC_FECTFWR_X_WMRK_832           (0xC)
+#define MCF_FEC_FECTFWR_X_WMRK_896           (0xD)
+#define MCF_FEC_FECTFWR_X_WMRK_960           (0xE)
+#define MCF_FEC_FECTFWR_X_WMRK_1024          (0xF)
+
+/* Bit definitions and macros for MCF_FEC_FECRFDR */
+#define MCF_FEC_FECRFDR_FIFO_DATA(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECRFSR */
+#define MCF_FEC_FECRFSR_EMT                  (0x10000)
+#define MCF_FEC_FECRFSR_ALARM                (0x20000)
+#define MCF_FEC_FECRFSR_FU                   (0x40000)
+#define MCF_FEC_FECRFSR_FRMRDY               (0x80000)
+#define MCF_FEC_FECRFSR_OF                   (0x100000)
+#define MCF_FEC_FECRFSR_UF                   (0x200000)
+#define MCF_FEC_FECRFSR_RXW                  (0x400000)
+#define MCF_FEC_FECRFSR_FAE                  (0x800000)
+#define MCF_FEC_FECRFSR_FRM(x)               (((x)&0xF)<<0x18)
+#define MCF_FEC_FECRFSR_IP                   (0x80000000)
+
+/* Bit definitions and macros for MCF_FEC_FECRFCR */
+#define MCF_FEC_FECRFCR_COUNTER(x)           (((x)&0xFFFF)<<0)
+#define MCF_FEC_FECRFCR_OF_MSK               (0x80000)
+#define MCF_FEC_FECRFCR_UF_MSK               (0x100000)
+#define MCF_FEC_FECRFCR_RXW_MSK              (0x200000)
+#define MCF_FEC_FECRFCR_FAE_MSK              (0x400000)
+#define MCF_FEC_FECRFCR_IP_MSK               (0x800000)
+#define MCF_FEC_FECRFCR_GR(x)                (((x)&0x7)<<0x18)
+#define MCF_FEC_FECRFCR_FRMEN                (0x8000000)
+#define MCF_FEC_FECRFCR_TIMER                (0x10000000)
+
+/* Bit definitions and macros for MCF_FEC_FECRLRFP */
+#define MCF_FEC_FECRLRFP_LRFP(x)             (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECRLWFP */
+#define MCF_FEC_FECRLWFP_LWFP(x)             (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECRFAR */
+#define MCF_FEC_FECRFAR_ALARM(x)             (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECRFRP */
+#define MCF_FEC_FECRFRP_READ(x)              (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECRFWP */
+#define MCF_FEC_FECRFWP_WRITE(x)             (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECTFDR */
+#define MCF_FEC_FECTFDR_FIFO_DATA(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECTFSR */
+#define MCF_FEC_FECTFSR_EMT                  (0x10000)
+#define MCF_FEC_FECTFSR_ALARM                (0x20000)
+#define MCF_FEC_FECTFSR_FU                   (0x40000)
+#define MCF_FEC_FECTFSR_FRMRDY               (0x80000)
+#define MCF_FEC_FECTFSR_OF                   (0x100000)
+#define MCF_FEC_FECTFSR_UF                   (0x200000)
+#define MCF_FEC_FECTFSR_FAE                  (0x800000)
+#define MCF_FEC_FECTFSR_FRM(x)               (((x)&0xF)<<0x18)
+#define MCF_FEC_FECTFSR_TXW                  (0x40000000)
+#define MCF_FEC_FECTFSR_IP                   (0x80000000)
+
+/* Bit definitions and macros for MCF_FEC_FECTFCR */
+#define MCF_FEC_FECTFCR_RESERVED             (0x200000)
+#define MCF_FEC_FECTFCR_COUNTER(x)           (((x)&0xFFFF)<<0|0x200000)
+#define MCF_FEC_FECTFCR_TXW_MASK             (0x240000)
+#define MCF_FEC_FECTFCR_OF_MSK               (0x280000)
+#define MCF_FEC_FECTFCR_UF_MSK               (0x300000)
+#define MCF_FEC_FECTFCR_FAE_MSK              (0x600000)
+#define MCF_FEC_FECTFCR_IP_MSK               (0xA00000)
+#define MCF_FEC_FECTFCR_GR(x)                (((x)&0x7)<<0x18|0x200000)
+#define MCF_FEC_FECTFCR_FRMEN                (0x8200000)
+#define MCF_FEC_FECTFCR_TIMER                (0x10200000)
+#define MCF_FEC_FECTFCR_WFR                  (0x20200000)
+#define MCF_FEC_FECTFCR_WCTL                 (0x40200000)
+
+/* Bit definitions and macros for MCF_FEC_FECTLRFP */
+#define MCF_FEC_FECTLRFP_LRFP(x)             (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECTLWFP */
+#define MCF_FEC_FECTLWFP_LWFP(x)             (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECTFAR */
+#define MCF_FEC_FECTFAR_ALARM(x)             (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECTFRP */
+#define MCF_FEC_FECTFRP_READ(x)              (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECTFWP */
+#define MCF_FEC_FECTFWP_WRITE(x)             (((x)&0x3FF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_FECFRST */
+#define MCF_FEC_FECFRST_RST_CTL              (0x1000000)
+#define MCF_FEC_FECFRST_SW_RST               (0x2000000)
+
+/* Bit definitions and macros for MCF_FEC_FECCTCWR */
+#define MCF_FEC_FECCTCWR_TFCW                (0x1000000)
+#define MCF_FEC_FECCTCWR_CRC                 (0x2000000)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_DROP */
+#define MCF_FEC_RMON_T_DROP_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_PACKETS */
+#define MCF_FEC_RMON_T_PACKETS_Value(x)      (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_BC_PKT */
+#define MCF_FEC_RMON_T_BC_PKT_Value(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_MC_PKT */
+#define MCF_FEC_RMON_T_MC_PKT_Value(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_CRC_ALIGN */
+#define MCF_FEC_RMON_T_CRC_ALIGN_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_UNDERSIZE */
+#define MCF_FEC_RMON_T_UNDERSIZE_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_OVERSIZE */
+#define MCF_FEC_RMON_T_OVERSIZE_Value(x)     (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_FRAG */
+#define MCF_FEC_RMON_T_FRAG_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_JAB */
+#define MCF_FEC_RMON_T_JAB_Value(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_COL */
+#define MCF_FEC_RMON_T_COL_Value(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_P64 */
+#define MCF_FEC_RMON_T_P64_Value(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_P65TO127 */
+#define MCF_FEC_RMON_T_P65TO127_Value(x)     (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_P128TO255 */
+#define MCF_FEC_RMON_T_P128TO255_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_P256TO511 */
+#define MCF_FEC_RMON_T_P256TO511_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_P512TO1023 */
+#define MCF_FEC_RMON_T_P512TO1023_Value(x)   (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_P1024TO2047 */
+#define MCF_FEC_RMON_T_P1024TO2047_Value(x)  (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_P_GTE2048 */
+#define MCF_FEC_RMON_T_P_GTE2048_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_T_OCTETS */
+#define MCF_FEC_RMON_T_OCTETS_Value(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_DROP */
+#define MCF_FEC_IEEE_T_DROP_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_FRAME_OK */
+#define MCF_FEC_IEEE_T_FRAME_OK_Value(x)     (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_1COL */
+#define MCF_FEC_IEEE_T_1COL_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_MCOL */
+#define MCF_FEC_IEEE_T_MCOL_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_DEF */
+#define MCF_FEC_IEEE_T_DEF_Value(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_LCOL */
+#define MCF_FEC_IEEE_T_LCOL_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_EXCOL */
+#define MCF_FEC_IEEE_T_EXCOL_Value(x)        (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_MACERR */
+#define MCF_FEC_IEEE_T_MACERR_Value(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_CSERR */
+#define MCF_FEC_IEEE_T_CSERR_Value(x)        (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_SQE */
+#define MCF_FEC_IEEE_T_SQE_Value(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_FDXFC */
+#define MCF_FEC_IEEE_T_FDXFC_Value(x)        (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_T_OCTETS_OK */
+#define MCF_FEC_IEEE_T_OCTETS_OK_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_DROP */
+#define MCF_FEC_RMON_R_DROP_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_PACKETS */
+#define MCF_FEC_RMON_R_PACKETS_Value(x)      (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_BC_PKT */
+#define MCF_FEC_RMON_R_BC_PKT_Value(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_MC_PKT */
+#define MCF_FEC_RMON_R_MC_PKT_Value(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_CRC_ALIGN */
+#define MCF_FEC_RMON_R_CRC_ALIGN_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_UNDERSIZE */
+#define MCF_FEC_RMON_R_UNDERSIZE_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_OVERSIZE */
+#define MCF_FEC_RMON_R_OVERSIZE_Value(x)     (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_FRAG */
+#define MCF_FEC_RMON_R_FRAG_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_JAB */
+#define MCF_FEC_RMON_R_JAB_Value(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_RESVD_0 */
+#define MCF_FEC_RMON_R_RESVD_0_Value(x)      (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_P64 */
+#define MCF_FEC_RMON_R_P64_Value(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_P65TO127 */
+#define MCF_FEC_RMON_R_P65TO127_Value(x)     (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_P128TO255 */
+#define MCF_FEC_RMON_R_P128TO255_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_P256TO511 */
+#define MCF_FEC_RMON_R_P256TO511_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_P512TO1023 */
+#define MCF_FEC_RMON_R_P512TO1023_Value(x)   (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_P1024TO2047 */
+#define MCF_FEC_RMON_R_P1024TO2047_Value(x)  (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_P_GTE2048 */
+#define MCF_FEC_RMON_R_P_GTE2048_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_RMON_R_OCTETS */
+#define MCF_FEC_RMON_R_OCTETS_Value(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_R_DROP */
+#define MCF_FEC_IEEE_R_DROP_Value(x)         (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_R_FRAME_OK */
+#define MCF_FEC_IEEE_R_FRAME_OK_Value(x)     (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_R_CRC */
+#define MCF_FEC_IEEE_R_CRC_Value(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_R_ALIGN */
+#define MCF_FEC_IEEE_R_ALIGN_Value(x)        (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_R_MACERR */
+#define MCF_FEC_IEEE_R_MACERR_Value(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_R_FDXFC */
+#define MCF_FEC_IEEE_R_FDXFC_Value(x)        (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_FEC_IEEE_R_OCTETS_OK */
+#define MCF_FEC_IEEE_R_OCTETS_OK_Value(x)    (((x)&0xFFFFFFFF)<<0)
+
+
+#endif /* __MCF5475_FEC_H__ */
diff --git a/firebeeV1/headers/MCF5475_GPIO.h b/firebeeV1/headers/MCF5475_GPIO.h
new file mode 100644
index 0000000..7ef3dce
--- /dev/null
+++ b/firebeeV1/headers/MCF5475_GPIO.h
@@ -0,0 +1,543 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_GPIO_H__
+#define __MCF5475_GPIO_H__
+
+
+/*********************************************************************
+*
+* General Purpose I/O (GPIO)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_GPIO_PODR_FBCTL                  (*(vuint8 *)(&__MBAR[0xA00]))
+#define MCF_GPIO_PDDR_FBCTL                  (*(vuint8 *)(&__MBAR[0xA10]))
+#define MCF_GPIO_PPDSDR_FBCTL                (*(vuint8 *)(&__MBAR[0xA20]))
+#define MCF_GPIO_PCLRR_FBCTL                 (*(vuint8 *)(&__MBAR[0xA30]))
+
+#define MCF_GPIO_PODR_FBCS                   (*(vuint8 *)(&__MBAR[0xA01]))
+#define MCF_GPIO_PDDR_FBCS                   (*(vuint8 *)(&__MBAR[0xA11]))
+#define MCF_GPIO_PPDSDR_FBCS                 (*(vuint8 *)(&__MBAR[0xA21]))
+#define MCF_GPIO_PCLRR_FBCS                  (*(vuint8 *)(&__MBAR[0xA31]))
+
+#define MCF_GPIO_PODR_DMA                    (*(vuint8 *)(&__MBAR[0xA02]))
+#define MCF_GPIO_PDDR_DMA                    (*(vuint8 *)(&__MBAR[0xA12]))
+#define MCF_GPIO_PPDSDR_DMA                  (*(vuint8 *)(&__MBAR[0xA22]))
+#define MCF_GPIO_PCLRR_DMA                   (*(vuint8 *)(&__MBAR[0xA32]))
+
+#define MCF_GPIO_PODR_FEC0H                  (*(vuint8 *)(&__MBAR[0xA04]))
+#define MCF_GPIO_PDDR_FEC0H                  (*(vuint8 *)(&__MBAR[0xA14]))
+#define MCF_GPIO_PPDSDR_FEC0H                (*(vuint8 *)(&__MBAR[0xA24]))
+#define MCF_GPIO_PCLRR_FEC0H                 (*(vuint8 *)(&__MBAR[0xA34]))
+
+#define MCF_GPIO_PODR_FEC0L                  (*(vuint8 *)(&__MBAR[0xA05]))
+#define MCF_GPIO_PDDR_FEC0L                  (*(vuint8 *)(&__MBAR[0xA15]))
+#define MCF_GPIO_PPDSDR_FEC0L                (*(vuint8 *)(&__MBAR[0xA25]))
+#define MCF_GPIO_PCLRR_FEC0L                 (*(vuint8 *)(&__MBAR[0xA35]))
+
+#define MCF_GPIO_PODR_FEC1H                  (*(vuint8 *)(&__MBAR[0xA06]))
+#define MCF_GPIO_PDDR_FEC1H                  (*(vuint8 *)(&__MBAR[0xA16]))
+#define MCF_GPIO_PPDSDR_FEC1H                (*(vuint8 *)(&__MBAR[0xA26]))
+#define MCF_GPIO_PCLRR_FEC1H                 (*(vuint8 *)(&__MBAR[0xA36]))
+
+#define MCF_GPIO_PODR_FEC1L                  (*(vuint8 *)(&__MBAR[0xA07]))
+#define MCF_GPIO_PDDR_FEC1L                  (*(vuint8 *)(&__MBAR[0xA17]))
+#define MCF_GPIO_PPDSDR_FEC1L                (*(vuint8 *)(&__MBAR[0xA27]))
+#define MCF_GPIO_PCLRR_FEC1L                 (*(vuint8 *)(&__MBAR[0xA37]))
+
+#define MCF_GPIO_PODR_FECI2C                 (*(vuint8 *)(&__MBAR[0xA08]))
+#define MCF_GPIO_PDDR_FECI2C                 (*(vuint8 *)(&__MBAR[0xA18]))
+#define MCF_GPIO_PPDSDR_FECI2C               (*(vuint8 *)(&__MBAR[0xA28]))
+#define MCF_GPIO_PCLRR_FECI2C                (*(vuint8 *)(&__MBAR[0xA38]))
+
+#define MCF_GPIO_PODR_PCIBG                  (*(vuint8 *)(&__MBAR[0xA09]))
+#define MCF_GPIO_PDDR_PCIBG                  (*(vuint8 *)(&__MBAR[0xA19]))
+#define MCF_GPIO_PPDSDR_PCIBG                (*(vuint8 *)(&__MBAR[0xA29]))
+#define MCF_GPIO_PCLRR_PCIBG                 (*(vuint8 *)(&__MBAR[0xA39]))
+
+#define MCF_GPIO_PODR_PCIBR                  (*(vuint8 *)(&__MBAR[0xA0A]))
+#define MCF_GPIO_PDDR_PCIBR                  (*(vuint8 *)(&__MBAR[0xA1A]))
+#define MCF_GPIO_PPDSDR_PCIBR                (*(vuint8 *)(&__MBAR[0xA2A]))
+#define MCF_GPIO_PCLRR_PCIBR                 (*(vuint8 *)(&__MBAR[0xA3A]))
+
+#define MCF_GPIO2_PODR_PSC3PSC               (*(vuint8 *)(&__MBAR[0xA0C]))
+#define MCF_GPIO2_PDDR_PSC3PSC               (*(vuint8 *)(&__MBAR[0xA1C]))
+#define MCF_GPIO2_PPDSDR_PSC3PSC             (*(vuint8 *)(&__MBAR[0xA2C]))
+#define MCF_GPIO2_PCLRR_PSC3PSC              (*(vuint8 *)(&__MBAR[0xA3C]))
+
+#define MCF_GPIO0_PODR_PSC1PSC               (*(vuint8 *)(&__MBAR[0xA0D]))
+#define MCF_GPIO0_PDDR_PSC1PSC               (*(vuint8 *)(&__MBAR[0xA1D]))
+#define MCF_GPIO0_PPDSDR_PSC1PSC             (*(vuint8 *)(&__MBAR[0xA2D]))
+#define MCF_GPIO0_PCLRR_PSC1PSC              (*(vuint8 *)(&__MBAR[0xA3D]))
+
+#define MCF_GPIO_PODR_DSPI                   (*(vuint8 *)(&__MBAR[0xA0E]))
+#define MCF_GPIO_PDDR_DSPI                   (*(vuint8 *)(&__MBAR[0xA1E]))
+#define MCF_GPIO_PPDSDR_DSPI                 (*(vuint8 *)(&__MBAR[0xA2E]))
+#define MCF_GPIO_PCLRR_DSPI                  (*(vuint8 *)(&__MBAR[0xA3E]))
+
+
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FBCTL */
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL0      (0x1)
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL1      (0x2)
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL2      (0x4)
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL3      (0x8)
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL4      (0x10)
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL5      (0x20)
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL6      (0x40)
+#define MCF_GPIO_PODR_FBCTL_PODR_FBCTL7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FBCTL */
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL0      (0x1)
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL1      (0x2)
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL2      (0x4)
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL3      (0x8)
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL4      (0x10)
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL5      (0x20)
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL6      (0x40)
+#define MCF_GPIO_PDDR_FBCTL_PDDR_FBCTL7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCTL */
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL0  (0x1)
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL1  (0x2)
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL2  (0x4)
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL3  (0x8)
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL4  (0x10)
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL5  (0x20)
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL6  (0x40)
+#define MCF_GPIO_PPDSDR_FBCTL_PPDSDR_FBCTL7  (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCTL */
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL0    (0x1)
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL1    (0x2)
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL2    (0x4)
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL3    (0x8)
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL4    (0x10)
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL5    (0x20)
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL6    (0x40)
+#define MCF_GPIO_PCLRR_FBCTL_PCLRR_FBCTL7    (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FBCS */
+#define MCF_GPIO_PODR_FBCS_PODR_FBCS1        (0x2)
+#define MCF_GPIO_PODR_FBCS_PODR_FBCS2        (0x4)
+#define MCF_GPIO_PODR_FBCS_PODR_FBCS3        (0x8)
+#define MCF_GPIO_PODR_FBCS_PODR_FBCS4        (0x10)
+#define MCF_GPIO_PODR_FBCS_PODR_FBCS5        (0x20)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FBCS */
+#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS1        (0x2)
+#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS2        (0x4)
+#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS3        (0x8)
+#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS4        (0x10)
+#define MCF_GPIO_PDDR_FBCS_PDDR_FBCS5        (0x20)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FBCS */
+#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS1    (0x2)
+#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS2    (0x4)
+#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS3    (0x8)
+#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS4    (0x10)
+#define MCF_GPIO_PPDSDR_FBCS_PPDSDR_FBCS5    (0x20)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FBCS */
+#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS1      (0x2)
+#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS2      (0x4)
+#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS3      (0x8)
+#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS4      (0x10)
+#define MCF_GPIO_PCLRR_FBCS_PCLRR_FBCS5      (0x20)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_DMA */
+#define MCF_GPIO_PODR_DMA_PODR_DMA0          (0x1)
+#define MCF_GPIO_PODR_DMA_PODR_DMA1          (0x2)
+#define MCF_GPIO_PODR_DMA_PODR_DMA2          (0x4)
+#define MCF_GPIO_PODR_DMA_PODR_DMA3          (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_DMA */
+#define MCF_GPIO_PDDR_DMA_PDDR_DMA0          (0x1)
+#define MCF_GPIO_PDDR_DMA_PDDR_DMA1          (0x2)
+#define MCF_GPIO_PDDR_DMA_PDDR_DMA2          (0x4)
+#define MCF_GPIO_PDDR_DMA_PDDR_DMA3          (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_DMA */
+#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA0      (0x1)
+#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA1      (0x2)
+#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA2      (0x4)
+#define MCF_GPIO_PPDSDR_DMA_PPDSDR_DMA3      (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_DMA */
+#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA0        (0x1)
+#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA1        (0x2)
+#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA2        (0x4)
+#define MCF_GPIO_PCLRR_DMA_PCLRR_DMA3        (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FEC0H */
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H0      (0x1)
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H1      (0x2)
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H2      (0x4)
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H3      (0x8)
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H4      (0x10)
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H5      (0x20)
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H6      (0x40)
+#define MCF_GPIO_PODR_FEC0H_PODR_FEC0H7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0H */
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H0      (0x1)
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H1      (0x2)
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H2      (0x4)
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H3      (0x8)
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H4      (0x10)
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H5      (0x20)
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H6      (0x40)
+#define MCF_GPIO_PDDR_FEC0H_PDDR_FEC0H7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0H */
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H0  (0x1)
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H1  (0x2)
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H2  (0x4)
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H3  (0x8)
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H4  (0x10)
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H5  (0x20)
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H6  (0x40)
+#define MCF_GPIO_PPDSDR_FEC0H_PPDSDR_FEC0H7  (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0H */
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H0    (0x1)
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H1    (0x2)
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H2    (0x4)
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H3    (0x8)
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H4    (0x10)
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H5    (0x20)
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H6    (0x40)
+#define MCF_GPIO_PCLRR_FEC0H_PCLRR_FEC0H7    (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FEC0L */
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L0      (0x1)
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L1      (0x2)
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L2      (0x4)
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L3      (0x8)
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L4      (0x10)
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L5      (0x20)
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L6      (0x40)
+#define MCF_GPIO_PODR_FEC0L_PODR_FEC0L7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FEC0L */
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L0      (0x1)
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L1      (0x2)
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L2      (0x4)
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L3      (0x8)
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L4      (0x10)
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L5      (0x20)
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L6      (0x40)
+#define MCF_GPIO_PDDR_FEC0L_PDDR_FEC0L7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC0L */
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L0  (0x1)
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L1  (0x2)
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L2  (0x4)
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L3  (0x8)
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L4  (0x10)
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L5  (0x20)
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L6  (0x40)
+#define MCF_GPIO_PPDSDR_FEC0L_PPDSDR_FEC0L7  (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC0L */
+#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L0    (0x1)
+#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L1    (0x2)
+#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L2    (0x4)
+#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L3    (0x8)
+#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L4    (0x10)
+#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L5    (0x20)
+#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L6    (0x40)
+#define MCF_GPIO_PCLRR_FEC0L_PCLRR_FEC0L7    (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FEC1H */
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H0      (0x1)
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H1      (0x2)
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H2      (0x4)
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H3      (0x8)
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H4      (0x10)
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H5      (0x20)
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H6      (0x40)
+#define MCF_GPIO_PODR_FEC1H_PODR_FEC1H7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1H */
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H0      (0x1)
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H1      (0x2)
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H2      (0x4)
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H3      (0x8)
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H4      (0x10)
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H5      (0x20)
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H6      (0x40)
+#define MCF_GPIO_PDDR_FEC1H_PDDR_FEC1H7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1H */
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H0  (0x1)
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H1  (0x2)
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H2  (0x4)
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H3  (0x8)
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H4  (0x10)
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H5  (0x20)
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H6  (0x40)
+#define MCF_GPIO_PPDSDR_FEC1H_PPDSDR_FEC1H7  (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1H */
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H0    (0x1)
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H1    (0x2)
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H2    (0x4)
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H3    (0x8)
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H4    (0x10)
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H5    (0x20)
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H6    (0x40)
+#define MCF_GPIO_PCLRR_FEC1H_PCLRR_FEC1H7    (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FEC1L */
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L0      (0x1)
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L1      (0x2)
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L2      (0x4)
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L3      (0x8)
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L4      (0x10)
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L5      (0x20)
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L6      (0x40)
+#define MCF_GPIO_PODR_FEC1L_PODR_FEC1L7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FEC1L */
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L0      (0x1)
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L1      (0x2)
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L2      (0x4)
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L3      (0x8)
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L4      (0x10)
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L5      (0x20)
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L6      (0x40)
+#define MCF_GPIO_PDDR_FEC1L_PDDR_FEC1L7      (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FEC1L */
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L0  (0x1)
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L1  (0x2)
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L2  (0x4)
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L3  (0x8)
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L4  (0x10)
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L5  (0x20)
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L6  (0x40)
+#define MCF_GPIO_PPDSDR_FEC1L_PPDSDR_FEC1L7  (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FEC1L */
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L0    (0x1)
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L1    (0x2)
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L2    (0x4)
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L3    (0x8)
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L4    (0x10)
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L5    (0x20)
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L6    (0x40)
+#define MCF_GPIO_PCLRR_FEC1L_PCLRR_FEC1L7    (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_FECI2C */
+#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C0    (0x1)
+#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C1    (0x2)
+#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C2    (0x4)
+#define MCF_GPIO_PODR_FECI2C_PODR_FECI2C3    (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_FECI2C */
+#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C0    (0x1)
+#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C1    (0x2)
+#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C2    (0x4)
+#define MCF_GPIO_PDDR_FECI2C_PDDR_FECI2C3    (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_FECI2C */
+#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C0 (0x1)
+#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C1 (0x2)
+#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C2 (0x4)
+#define MCF_GPIO_PPDSDR_FECI2C_PPDSDR_FECI2C3 (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_FECI2C */
+#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C0  (0x1)
+#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C1  (0x2)
+#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C2  (0x4)
+#define MCF_GPIO_PCLRR_FECI2C_PCLRR_FECI2C3  (0x8)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_PCIBG */
+#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG0      (0x1)
+#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG1      (0x2)
+#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG2      (0x4)
+#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG3      (0x8)
+#define MCF_GPIO_PODR_PCIBG_PODR_PCIBG4      (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBG */
+#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG0      (0x1)
+#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG1      (0x2)
+#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG2      (0x4)
+#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG3      (0x8)
+#define MCF_GPIO_PDDR_PCIBG_PDDR_PCIBG4      (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBG */
+#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG0  (0x1)
+#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG1  (0x2)
+#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG2  (0x4)
+#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG3  (0x8)
+#define MCF_GPIO_PPDSDR_PCIBG_PPDSDR_PCIBG4  (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBG */
+#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG0    (0x1)
+#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG1    (0x2)
+#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG2    (0x4)
+#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG3    (0x8)
+#define MCF_GPIO_PCLRR_PCIBG_PCLRR_PCIBG4    (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_PCIBR */
+#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR0      (0x1)
+#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR1      (0x2)
+#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR2      (0x4)
+#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR3      (0x8)
+#define MCF_GPIO_PODR_PCIBR_PODR_PCIBR4      (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_PCIBR */
+#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR0      (0x1)
+#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR1      (0x2)
+#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR2      (0x4)
+#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR3      (0x8)
+#define MCF_GPIO_PDDR_PCIBR_PDDR_PCIBR4      (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_PCIBR */
+#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR0  (0x1)
+#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR1  (0x2)
+#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR2  (0x4)
+#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR3  (0x8)
+#define MCF_GPIO_PPDSDR_PCIBR_PPDSDR_PCIBR4  (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_PCIBR */
+#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR0    (0x1)
+#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR1    (0x2)
+#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR2    (0x4)
+#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR3    (0x8)
+#define MCF_GPIO_PCLRR_PCIBR_PCLRR_PCIBR4    (0x10)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_PSC3PSC */
+#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC20 (0x1)
+#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC21 (0x2)
+#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC22 (0x4)
+#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC23 (0x8)
+#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC24 (0x10)
+#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC25 (0x20)
+#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC26 (0x40)
+#define MCF_GPIO_PODR_PSC3PSC_PODR_PSC3PSC27 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_PSC3PSC */
+#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC20 (0x1)
+#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC21 (0x2)
+#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC22 (0x4)
+#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC23 (0x8)
+#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC24 (0x10)
+#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC25 (0x20)
+#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC26 (0x40)
+#define MCF_GPIO_PDDR_PSC3PSC_PDDR_PSC3PSC27 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC3PSC */
+#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC20 (0x1)
+#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC21 (0x2)
+#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC22 (0x4)
+#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC23 (0x8)
+#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC24 (0x10)
+#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC25 (0x20)
+#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC26 (0x40)
+#define MCF_GPIO_PPDSDR_PSC3PSC_PPDSDR_PSC3PSC27 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC3PSC */
+#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC20 (0x1)
+#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC21 (0x2)
+#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC22 (0x4)
+#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC23 (0x8)
+#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC24 (0x10)
+#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC25 (0x20)
+#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC26 (0x40)
+#define MCF_GPIO_PCLRR_PSC3PSC_PCLRR_PSC3PSC27 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_PSC1PSC */
+#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC00 (0x1)
+#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC01 (0x2)
+#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC02 (0x4)
+#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC03 (0x8)
+#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC04 (0x10)
+#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC05 (0x20)
+#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC06 (0x40)
+#define MCF_GPIO_PODR_PSC1PSC_PODR_PSC1PSC07 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_PSC1PSC */
+#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC00 (0x1)
+#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC01 (0x2)
+#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC02 (0x4)
+#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC03 (0x8)
+#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC04 (0x10)
+#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC05 (0x20)
+#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC06 (0x40)
+#define MCF_GPIO_PDDR_PSC1PSC_PDDR_PSC1PSC07 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_PSC1PSC */
+#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC00 (0x1)
+#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC01 (0x2)
+#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC02 (0x4)
+#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC03 (0x8)
+#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC04 (0x10)
+#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC05 (0x20)
+#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC06 (0x40)
+#define MCF_GPIO_PPDSDR_PSC1PSC_PPDSDR_PSC1PSC07 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_PSC1PSC */
+#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC00 (0x1)
+#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC01 (0x2)
+#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC02 (0x4)
+#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC03 (0x8)
+#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC04 (0x10)
+#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC05 (0x20)
+#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC06 (0x40)
+#define MCF_GPIO_PCLRR_PSC1PSC_PCLRR_PSC1PSC07 (0x80)
+
+/* Bit definitions and macros for MCF_GPIO_PODR_DSPI */
+#define MCF_GPIO_PODR_DSPI_PODR_DSPI0        (0x1)
+#define MCF_GPIO_PODR_DSPI_PODR_DSPI1        (0x2)
+#define MCF_GPIO_PODR_DSPI_PODR_DSPI2        (0x4)
+#define MCF_GPIO_PODR_DSPI_PODR_DSPI3        (0x8)
+#define MCF_GPIO_PODR_DSPI_PODR_DSPI4        (0x10)
+#define MCF_GPIO_PODR_DSPI_PODR_DSPI5        (0x20)
+#define MCF_GPIO_PODR_DSPI_PODR_DSPI6        (0x40)
+
+/* Bit definitions and macros for MCF_GPIO_PDDR_DSPI */
+#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI0        (0x1)
+#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI1        (0x2)
+#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI2        (0x4)
+#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI3        (0x8)
+#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI4        (0x10)
+#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI5        (0x20)
+#define MCF_GPIO_PDDR_DSPI_PDDR_DSPI6        (0x40)
+
+/* Bit definitions and macros for MCF_GPIO_PPDSDR_DSPI */
+#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI0    (0x1)
+#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI1    (0x2)
+#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI2    (0x4)
+#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI3    (0x8)
+#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI4    (0x10)
+#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI5    (0x20)
+#define MCF_GPIO_PPDSDR_DSPI_PPDSDR_DSPI6    (0x40)
+
+/* Bit definitions and macros for MCF_GPIO_PCLRR_DSPI */
+#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI0      (0x1)
+#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI1      (0x2)
+#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI2      (0x4)
+#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI3      (0x8)
+#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI4      (0x10)
+#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI5      (0x20)
+#define MCF_GPIO_PCLRR_DSPI_PCLRR_DSPI6      (0x40)
+
+
+#endif /* __MCF5475_GPIO_H__ */
diff --git a/firebeeV1/headers/MCF5475_GPT.h b/firebeeV1/headers/MCF5475_GPT.h
new file mode 100644
index 0000000..ab99d05
--- /dev/null
+++ b/firebeeV1/headers/MCF5475_GPT.h
@@ -0,0 +1,100 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_GPT_H__
+#define __MCF5475_GPT_H__
+
+
+/*********************************************************************
+*
+* General Purpose Timers (GPT)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_GPT0_GMS                         (*(vuint32*)(&__MBAR[0x800]))
+#define MCF_GPT0_GCIR                        (*(vuint32*)(&__MBAR[0x804]))
+#define MCF_GPT0_GPWM                        (*(vuint32*)(&__MBAR[0x808]))
+#define MCF_GPT0_GSR                         (*(vuint32*)(&__MBAR[0x80C]))
+
+#define MCF_GPT1_GMS                         (*(vuint32*)(&__MBAR[0x810]))
+#define MCF_GPT1_GCIR                        (*(vuint32*)(&__MBAR[0x814]))
+#define MCF_GPT1_GPWM                        (*(vuint32*)(&__MBAR[0x818]))
+#define MCF_GPT1_GSR                         (*(vuint32*)(&__MBAR[0x81C]))
+
+#define MCF_GPT2_GMS                         (*(vuint32*)(&__MBAR[0x820]))
+#define MCF_GPT2_GCIR                        (*(vuint32*)(&__MBAR[0x824]))
+#define MCF_GPT2_GPWM                        (*(vuint32*)(&__MBAR[0x828]))
+#define MCF_GPT2_GSR                         (*(vuint32*)(&__MBAR[0x82C]))
+
+#define MCF_GPT3_GMS                         (*(vuint32*)(&__MBAR[0x830]))
+#define MCF_GPT3_GCIR                        (*(vuint32*)(&__MBAR[0x834]))
+#define MCF_GPT3_GPWM                        (*(vuint32*)(&__MBAR[0x838]))
+#define MCF_GPT3_GSR                         (*(vuint32*)(&__MBAR[0x83C]))
+
+#define MCF_GPT_GMS(x)                       (*(vuint32*)(&__MBAR[0x800 + ((x)*0x10)]))
+#define MCF_GPT_GCIR(x)                      (*(vuint32*)(&__MBAR[0x804 + ((x)*0x10)]))
+#define MCF_GPT_GPWM(x)                      (*(vuint32*)(&__MBAR[0x808 + ((x)*0x10)]))
+#define MCF_GPT_GSR(x)                       (*(vuint32*)(&__MBAR[0x80C + ((x)*0x10)]))
+
+
+/* Bit definitions and macros for MCF_GPT_GMS */
+#define MCF_GPT_GMS_TMS(x)                   (((x)&0x7)<<0)
+#define MCF_GPT_GMS_TMS_DISABLE              (0)
+#define MCF_GPT_GMS_TMS_INCAPT               (0x1)
+#define MCF_GPT_GMS_TMS_OUTCAPT              (0x2)
+#define MCF_GPT_GMS_TMS_PWM                  (0x3)
+#define MCF_GPT_GMS_TMS_GPIO                 (0x4)
+#define MCF_GPT_GMS_GPIO(x)                  (((x)&0x3)<<0x4)
+#define MCF_GPT_GMS_GPIO_INPUT               (0)
+#define MCF_GPT_GMS_GPIO_OUTLO               (0x20)
+#define MCF_GPT_GMS_GPIO_OUTHI               (0x30)
+#define MCF_GPT_GMS_IEN                      (0x100)
+#define MCF_GPT_GMS_OD                       (0x200)
+#define MCF_GPT_GMS_SC                       (0x400)
+#define MCF_GPT_GMS_CE                       (0x1000)
+#define MCF_GPT_GMS_WDEN                     (0x8000)
+#define MCF_GPT_GMS_ICT(x)                   (((x)&0x3)<<0x10)
+#define MCF_GPT_GMS_ICT_ANY                  (0)
+#define MCF_GPT_GMS_ICT_RISE                 (0x10000)
+#define MCF_GPT_GMS_ICT_FALL                 (0x20000)
+#define MCF_GPT_GMS_ICT_PULSE                (0x30000)
+#define MCF_GPT_GMS_OCT(x)                   (((x)&0x3)<<0x14)
+#define MCF_GPT_GMS_OCT_FRCLOW               (0)
+#define MCF_GPT_GMS_OCT_PULSEHI              (0x100000)
+#define MCF_GPT_GMS_OCT_PULSELO              (0x200000)
+#define MCF_GPT_GMS_OCT_TOGGLE               (0x300000)
+#define MCF_GPT_GMS_OCPW(x)                  (((x)&0xFF)<<0x18)
+
+/* Bit definitions and macros for MCF_GPT_GCIR */
+#define MCF_GPT_GCIR_CNT(x)                  (((x)&0xFFFF)<<0)
+#define MCF_GPT_GCIR_PRE(x)                  (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_GPT_GPWM */
+#define MCF_GPT_GPWM_LOAD                    (0x1)
+#define MCF_GPT_GPWM_PWMOP                   (0x100)
+#define MCF_GPT_GPWM_WIDTH(x)                (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_GPT_GSR */
+#define MCF_GPT_GSR_CAPT                     (0x1)
+#define MCF_GPT_GSR_COMP                     (0x2)
+#define MCF_GPT_GSR_PWMP                     (0x4)
+#define MCF_GPT_GSR_TEXP                     (0x8)
+#define MCF_GPT_GSR_PIN                      (0x100)
+#define MCF_GPT_GSR_OVF(x)                   (((x)&0x7)<<0xC)
+#define MCF_GPT_GSR_CAPTURE(x)               (((x)&0xFFFF)<<0x10)
+
+
+#endif /* __MCF5475_GPT_H__ */
diff --git a/firebeeV1/headers/MCF5475_I2C.h b/firebeeV1/headers/MCF5475_I2C.h
new file mode 100644
index 0000000..dbbd626
--- /dev/null
+++ b/firebeeV1/headers/MCF5475_I2C.h
@@ -0,0 +1,69 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_I2C_H__
+#define __MCF5475_I2C_H__
+
+
+/*********************************************************************
+*
+* I2C Module (I2C)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_I2C_I2ADR                        (*(vuint8 *)(&__MBAR[0x8F00]))
+#define MCF_I2C_I2FDR                        (*(vuint8 *)(&__MBAR[0x8F04]))
+#define MCF_I2C_I2CR                         (*(vuint8 *)(&__MBAR[0x8F08]))
+#define MCF_I2C_I2SR                         (*(vuint8 *)(&__MBAR[0x8F0C]))
+#define MCF_I2C_I2DR                         (*(vuint8 *)(&__MBAR[0x8F10]))
+#define MCF_I2C_I2ICR                        (*(vuint8 *)(&__MBAR[0x8F20]))
+
+
+
+/* Bit definitions and macros for MCF_I2C_I2ADR */
+#define MCF_I2C_I2ADR_ADR(x)                 (((x)&0x7F)<<0x1)
+
+/* Bit definitions and macros for MCF_I2C_I2FDR */
+#define MCF_I2C_I2FDR_IC(x)                  (((x)&0x3F)<<0)
+
+/* Bit definitions and macros for MCF_I2C_I2CR */
+#define MCF_I2C_I2CR_RSTA                    (0x4)
+#define MCF_I2C_I2CR_TXAK                    (0x8)
+#define MCF_I2C_I2CR_MTX                     (0x10)
+#define MCF_I2C_I2CR_MSTA                    (0x20)
+#define MCF_I2C_I2CR_IIEN                    (0x40)
+#define MCF_I2C_I2CR_IEN                     (0x80)
+
+/* Bit definitions and macros for MCF_I2C_I2SR */
+#define MCF_I2C_I2SR_RXAK                    (0x1)
+#define MCF_I2C_I2SR_IIF                     (0x2)
+#define MCF_I2C_I2SR_SRW                     (0x4)
+#define MCF_I2C_I2SR_IAL                     (0x10)
+#define MCF_I2C_I2SR_IBB                     (0x20)
+#define MCF_I2C_I2SR_IAAS                    (0x40)
+#define MCF_I2C_I2SR_ICF                     (0x80)
+
+/* Bit definitions and macros for MCF_I2C_I2DR */
+#define MCF_I2C_I2DR_DATA(x)                 (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_I2C_I2ICR */
+#define MCF_I2C_I2ICR_IE                     (0x1)
+#define MCF_I2C_I2ICR_RE                     (0x2)
+#define MCF_I2C_I2ICR_TE                     (0x4)
+#define MCF_I2C_I2ICR_BNBE                   (0x8)
+
+
+#endif /* __MCF5475_I2C_H__ */
diff --git a/firebeeV1/headers/MCF5475_INTC.h b/firebeeV1/headers/MCF5475_INTC.h
new file mode 100644
index 0000000..4dfc6d2
--- /dev/null
+++ b/firebeeV1/headers/MCF5475_INTC.h
@@ -0,0 +1,331 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_INTC_H__
+#define __MCF5475_INTC_H__
+
+
+/*********************************************************************
+*
+* Interrupt Controller (INTC)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_INTC_IPRH                        (*(vuint32*)(&__MBAR[0x700]))
+#define MCF_INTC_IPRL                        (*(vuint32*)(&__MBAR[0x704]))
+#define MCF_INTC_IMRH                        (*(vuint32*)(&__MBAR[0x708]))
+#define MCF_INTC_IMRL                        (*(vuint32*)(&__MBAR[0x70C]))
+#define MCF_INTC_INTFRCH                     (*(vuint32*)(&__MBAR[0x710]))
+#define MCF_INTC_INTFRCL                     (*(vuint32*)(&__MBAR[0x714]))
+#define MCF_INTC_IRLR                        (*(vuint8 *)(&__MBAR[0x718]))
+#define MCF_INTC_IACKLPR                     (*(vuint8 *)(&__MBAR[0x719]))
+#define MCF_INTC_ICR01                       (*(vuint8 *)(&__MBAR[0x741]))
+#define MCF_INTC_ICR02                       (*(vuint8 *)(&__MBAR[0x742]))
+#define MCF_INTC_ICR03                       (*(vuint8 *)(&__MBAR[0x743]))
+#define MCF_INTC_ICR04                       (*(vuint8 *)(&__MBAR[0x744]))
+#define MCF_INTC_ICR05                       (*(vuint8 *)(&__MBAR[0x745]))
+#define MCF_INTC_ICR06                       (*(vuint8 *)(&__MBAR[0x746]))
+#define MCF_INTC_ICR07                       (*(vuint8 *)(&__MBAR[0x747]))
+#define MCF_INTC_ICR08                       (*(vuint8 *)(&__MBAR[0x748]))
+#define MCF_INTC_ICR09                       (*(vuint8 *)(&__MBAR[0x749]))
+#define MCF_INTC_ICR10                       (*(vuint8 *)(&__MBAR[0x74A]))
+#define MCF_INTC_ICR11                       (*(vuint8 *)(&__MBAR[0x74B]))
+#define MCF_INTC_ICR12                       (*(vuint8 *)(&__MBAR[0x74C]))
+#define MCF_INTC_ICR13                       (*(vuint8 *)(&__MBAR[0x74D]))
+#define MCF_INTC_ICR14                       (*(vuint8 *)(&__MBAR[0x74E]))
+#define MCF_INTC_ICR15                       (*(vuint8 *)(&__MBAR[0x74F]))
+#define MCF_INTC_ICR16                       (*(vuint8 *)(&__MBAR[0x750]))
+#define MCF_INTC_ICR17                       (*(vuint8 *)(&__MBAR[0x751]))
+#define MCF_INTC_ICR18                       (*(vuint8 *)(&__MBAR[0x752]))
+#define MCF_INTC_ICR19                       (*(vuint8 *)(&__MBAR[0x753]))
+#define MCF_INTC_ICR20                       (*(vuint8 *)(&__MBAR[0x754]))
+#define MCF_INTC_ICR21                       (*(vuint8 *)(&__MBAR[0x755]))
+#define MCF_INTC_ICR22                       (*(vuint8 *)(&__MBAR[0x756]))
+#define MCF_INTC_ICR23                       (*(vuint8 *)(&__MBAR[0x757]))
+#define MCF_INTC_ICR24                       (*(vuint8 *)(&__MBAR[0x758]))
+#define MCF_INTC_ICR25                       (*(vuint8 *)(&__MBAR[0x759]))
+#define MCF_INTC_ICR26                       (*(vuint8 *)(&__MBAR[0x75A]))
+#define MCF_INTC_ICR27                       (*(vuint8 *)(&__MBAR[0x75B]))
+#define MCF_INTC_ICR28                       (*(vuint8 *)(&__MBAR[0x75C]))
+#define MCF_INTC_ICR29                       (*(vuint8 *)(&__MBAR[0x75D]))
+#define MCF_INTC_ICR30                       (*(vuint8 *)(&__MBAR[0x75E]))
+#define MCF_INTC_ICR31                       (*(vuint8 *)(&__MBAR[0x75F]))
+#define MCF_INTC_ICR32                       (*(vuint8 *)(&__MBAR[0x760]))
+#define MCF_INTC_ICR33                       (*(vuint8 *)(&__MBAR[0x761]))
+#define MCF_INTC_ICR34                       (*(vuint8 *)(&__MBAR[0x762]))
+#define MCF_INTC_ICR35                       (*(vuint8 *)(&__MBAR[0x763]))
+#define MCF_INTC_ICR36                       (*(vuint8 *)(&__MBAR[0x764]))
+#define MCF_INTC_ICR37                       (*(vuint8 *)(&__MBAR[0x765]))
+#define MCF_INTC_ICR38                       (*(vuint8 *)(&__MBAR[0x766]))
+#define MCF_INTC_ICR39                       (*(vuint8 *)(&__MBAR[0x767]))
+#define MCF_INTC_ICR40                       (*(vuint8 *)(&__MBAR[0x768]))
+#define MCF_INTC_ICR41                       (*(vuint8 *)(&__MBAR[0x769]))
+#define MCF_INTC_ICR42                       (*(vuint8 *)(&__MBAR[0x76A]))
+#define MCF_INTC_ICR43                       (*(vuint8 *)(&__MBAR[0x76B]))
+#define MCF_INTC_ICR44                       (*(vuint8 *)(&__MBAR[0x76C]))
+#define MCF_INTC_ICR45                       (*(vuint8 *)(&__MBAR[0x76D]))
+#define MCF_INTC_ICR46                       (*(vuint8 *)(&__MBAR[0x76E]))
+#define MCF_INTC_ICR47                       (*(vuint8 *)(&__MBAR[0x76F]))
+#define MCF_INTC_ICR48                       (*(vuint8 *)(&__MBAR[0x770]))
+#define MCF_INTC_ICR49                       (*(vuint8 *)(&__MBAR[0x771]))
+#define MCF_INTC_ICR50                       (*(vuint8 *)(&__MBAR[0x772]))
+#define MCF_INTC_ICR51                       (*(vuint8 *)(&__MBAR[0x773]))
+#define MCF_INTC_ICR52                       (*(vuint8 *)(&__MBAR[0x774]))
+#define MCF_INTC_ICR53                       (*(vuint8 *)(&__MBAR[0x775]))
+#define MCF_INTC_ICR54                       (*(vuint8 *)(&__MBAR[0x776]))
+#define MCF_INTC_ICR55                       (*(vuint8 *)(&__MBAR[0x777]))
+#define MCF_INTC_ICR56                       (*(vuint8 *)(&__MBAR[0x778]))
+#define MCF_INTC_ICR57                       (*(vuint8 *)(&__MBAR[0x779]))
+#define MCF_INTC_ICR58                       (*(vuint8 *)(&__MBAR[0x77A]))
+#define MCF_INTC_ICR59                       (*(vuint8 *)(&__MBAR[0x77B]))
+#define MCF_INTC_ICR60                       (*(vuint8 *)(&__MBAR[0x77C]))
+#define MCF_INTC_ICR61                       (*(vuint8 *)(&__MBAR[0x77D]))
+#define MCF_INTC_ICR62                       (*(vuint8 *)(&__MBAR[0x77E]))
+#define MCF_INTC_ICR63                       (*(vuint8 *)(&__MBAR[0x77F]))
+#define MCF_INTC_SWIACK                      (*(vuint8 *)(&__MBAR[0x7E0]))
+#define MCF_INTC_L1IACK                      (*(vuint8 *)(&__MBAR[0x7E4]))
+#define MCF_INTC_L2IACK                      (*(vuint8 *)(&__MBAR[0x7E8]))
+#define MCF_INTC_L3IACK                      (*(vuint8 *)(&__MBAR[0x7EC]))
+#define MCF_INTC_L4IACK                      (*(vuint8 *)(&__MBAR[0x7F0]))
+#define MCF_INTC_L5IACK                      (*(vuint8 *)(&__MBAR[0x7F4]))
+#define MCF_INTC_L6IACK                      (*(vuint8 *)(&__MBAR[0x7F8]))
+#define MCF_INTC_L7IACK                      (*(vuint8 *)(&__MBAR[0x7FC]))
+#define MCF_INTC_ICR(x)                      (*(vuint8 *)(&__MBAR[0x741 + ((x-1)*0x1)]))
+#define MCF_INTC_LIACK(x)                    (*(vuint8 *)(&__MBAR[0x7E4 + ((x-1)*0x4)]))
+
+
+
+/* Bit definitions and macros for MCF_INTC_IPRH */
+#define MCF_INTC_IPRH_INT32                  (0x1)
+#define MCF_INTC_IPRH_INT33                  (0x2)
+#define MCF_INTC_IPRH_INT34                  (0x4)
+#define MCF_INTC_IPRH_INT35                  (0x8)
+#define MCF_INTC_IPRH_INT36                  (0x10)
+#define MCF_INTC_IPRH_INT37                  (0x20)
+#define MCF_INTC_IPRH_INT38                  (0x40)
+#define MCF_INTC_IPRH_INT39                  (0x80)
+#define MCF_INTC_IPRH_INT40                  (0x100)
+#define MCF_INTC_IPRH_INT41                  (0x200)
+#define MCF_INTC_IPRH_INT42                  (0x400)
+#define MCF_INTC_IPRH_INT43                  (0x800)
+#define MCF_INTC_IPRH_INT44                  (0x1000)
+#define MCF_INTC_IPRH_INT45                  (0x2000)
+#define MCF_INTC_IPRH_INT46                  (0x4000)
+#define MCF_INTC_IPRH_INT47                  (0x8000)
+#define MCF_INTC_IPRH_INT48                  (0x10000)
+#define MCF_INTC_IPRH_INT49                  (0x20000)
+#define MCF_INTC_IPRH_INT50                  (0x40000)
+#define MCF_INTC_IPRH_INT51                  (0x80000)
+#define MCF_INTC_IPRH_INT52                  (0x100000)
+#define MCF_INTC_IPRH_INT53                  (0x200000)
+#define MCF_INTC_IPRH_INT54                  (0x400000)
+#define MCF_INTC_IPRH_INT55                  (0x800000)
+#define MCF_INTC_IPRH_INT56                  (0x1000000)
+#define MCF_INTC_IPRH_INT57                  (0x2000000)
+#define MCF_INTC_IPRH_INT58                  (0x4000000)
+#define MCF_INTC_IPRH_INT59                  (0x8000000)
+#define MCF_INTC_IPRH_INT60                  (0x10000000)
+#define MCF_INTC_IPRH_INT61                  (0x20000000)
+#define MCF_INTC_IPRH_INT62                  (0x40000000)
+#define MCF_INTC_IPRH_INT63                  (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC_IPRL */
+#define MCF_INTC_IPRL_INT1                   (0x2)
+#define MCF_INTC_IPRL_INT2                   (0x4)
+#define MCF_INTC_IPRL_INT3                   (0x8)
+#define MCF_INTC_IPRL_INT4                   (0x10)
+#define MCF_INTC_IPRL_INT5                   (0x20)
+#define MCF_INTC_IPRL_INT6                   (0x40)
+#define MCF_INTC_IPRL_INT7                   (0x80)
+#define MCF_INTC_IPRL_INT8                   (0x100)
+#define MCF_INTC_IPRL_INT9                   (0x200)
+#define MCF_INTC_IPRL_INT10                  (0x400)
+#define MCF_INTC_IPRL_INT11                  (0x800)
+#define MCF_INTC_IPRL_INT12                  (0x1000)
+#define MCF_INTC_IPRL_INT13                  (0x2000)
+#define MCF_INTC_IPRL_INT14                  (0x4000)
+#define MCF_INTC_IPRL_INT15                  (0x8000)
+#define MCF_INTC_IPRL_INT16                  (0x10000)
+#define MCF_INTC_IPRL_INT17                  (0x20000)
+#define MCF_INTC_IPRL_INT18                  (0x40000)
+#define MCF_INTC_IPRL_INT19                  (0x80000)
+#define MCF_INTC_IPRL_INT20                  (0x100000)
+#define MCF_INTC_IPRL_INT21                  (0x200000)
+#define MCF_INTC_IPRL_INT22                  (0x400000)
+#define MCF_INTC_IPRL_INT23                  (0x800000)
+#define MCF_INTC_IPRL_INT24                  (0x1000000)
+#define MCF_INTC_IPRL_INT25                  (0x2000000)
+#define MCF_INTC_IPRL_INT26                  (0x4000000)
+#define MCF_INTC_IPRL_INT27                  (0x8000000)
+#define MCF_INTC_IPRL_INT28                  (0x10000000)
+#define MCF_INTC_IPRL_INT29                  (0x20000000)
+#define MCF_INTC_IPRL_INT30                  (0x40000000)
+#define MCF_INTC_IPRL_INT31                  (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC_IMRH */
+#define MCF_INTC_IMRH_INT_MASK32             (0x1)
+#define MCF_INTC_IMRH_INT_MASK33             (0x2)
+#define MCF_INTC_IMRH_INT_MASK34             (0x4)
+#define MCF_INTC_IMRH_INT_MASK35             (0x8)
+#define MCF_INTC_IMRH_INT_MASK36             (0x10)
+#define MCF_INTC_IMRH_INT_MASK37             (0x20)
+#define MCF_INTC_IMRH_INT_MASK38             (0x40)
+#define MCF_INTC_IMRH_INT_MASK39             (0x80)
+#define MCF_INTC_IMRH_INT_MASK40             (0x100)
+#define MCF_INTC_IMRH_INT_MASK41             (0x200)
+#define MCF_INTC_IMRH_INT_MASK42             (0x400)
+#define MCF_INTC_IMRH_INT_MASK43             (0x800)
+#define MCF_INTC_IMRH_INT_MASK44             (0x1000)
+#define MCF_INTC_IMRH_INT_MASK45             (0x2000)
+#define MCF_INTC_IMRH_INT_MASK46             (0x4000)
+#define MCF_INTC_IMRH_INT_MASK47             (0x8000)
+#define MCF_INTC_IMRH_INT_MASK48             (0x10000)
+#define MCF_INTC_IMRH_INT_MASK49             (0x20000)
+#define MCF_INTC_IMRH_INT_MASK50             (0x40000)
+#define MCF_INTC_IMRH_INT_MASK51             (0x80000)
+#define MCF_INTC_IMRH_INT_MASK52             (0x100000)
+#define MCF_INTC_IMRH_INT_MASK53             (0x200000)
+#define MCF_INTC_IMRH_INT_MASK54             (0x400000)
+#define MCF_INTC_IMRH_INT_MASK55             (0x800000)
+#define MCF_INTC_IMRH_INT_MASK56             (0x1000000)
+#define MCF_INTC_IMRH_INT_MASK57             (0x2000000)
+#define MCF_INTC_IMRH_INT_MASK58             (0x4000000)
+#define MCF_INTC_IMRH_INT_MASK59             (0x8000000)
+#define MCF_INTC_IMRH_INT_MASK60             (0x10000000)
+#define MCF_INTC_IMRH_INT_MASK61             (0x20000000)
+#define MCF_INTC_IMRH_INT_MASK62             (0x40000000)
+#define MCF_INTC_IMRH_INT_MASK63             (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC_IMRL */
+#define MCF_INTC_IMRL_MASKALL                (0x1)
+#define MCF_INTC_IMRL_INT_MASK1              (0x2)
+#define MCF_INTC_IMRL_INT_MASK2              (0x4)
+#define MCF_INTC_IMRL_INT_MASK3              (0x8)
+#define MCF_INTC_IMRL_INT_MASK4              (0x10)
+#define MCF_INTC_IMRL_INT_MASK5              (0x20)
+#define MCF_INTC_IMRL_INT_MASK6              (0x40)
+#define MCF_INTC_IMRL_INT_MASK7              (0x80)
+#define MCF_INTC_IMRL_INT_MASK8              (0x100)
+#define MCF_INTC_IMRL_INT_MASK9              (0x200)
+#define MCF_INTC_IMRL_INT_MASK10             (0x400)
+#define MCF_INTC_IMRL_INT_MASK11             (0x800)
+#define MCF_INTC_IMRL_INT_MASK12             (0x1000)
+#define MCF_INTC_IMRL_INT_MASK13             (0x2000)
+#define MCF_INTC_IMRL_INT_MASK14             (0x4000)
+#define MCF_INTC_IMRL_INT_MASK15             (0x8000)
+#define MCF_INTC_IMRL_INT_MASK16             (0x10000)
+#define MCF_INTC_IMRL_INT_MASK17             (0x20000)
+#define MCF_INTC_IMRL_INT_MASK18             (0x40000)
+#define MCF_INTC_IMRL_INT_MASK19             (0x80000)
+#define MCF_INTC_IMRL_INT_MASK20             (0x100000)
+#define MCF_INTC_IMRL_INT_MASK21             (0x200000)
+#define MCF_INTC_IMRL_INT_MASK22             (0x400000)
+#define MCF_INTC_IMRL_INT_MASK23             (0x800000)
+#define MCF_INTC_IMRL_INT_MASK24             (0x1000000)
+#define MCF_INTC_IMRL_INT_MASK25             (0x2000000)
+#define MCF_INTC_IMRL_INT_MASK26             (0x4000000)
+#define MCF_INTC_IMRL_INT_MASK27             (0x8000000)
+#define MCF_INTC_IMRL_INT_MASK28             (0x10000000)
+#define MCF_INTC_IMRL_INT_MASK29             (0x20000000)
+#define MCF_INTC_IMRL_INT_MASK30             (0x40000000)
+#define MCF_INTC_IMRL_INT_MASK31             (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC_INTFRCH */
+#define MCF_INTC_INTFRCH_INTFRC32            (0x1)
+#define MCF_INTC_INTFRCH_INTFRC33            (0x2)
+#define MCF_INTC_INTFRCH_INTFRC34            (0x4)
+#define MCF_INTC_INTFRCH_INTFRC35            (0x8)
+#define MCF_INTC_INTFRCH_INTFRC36            (0x10)
+#define MCF_INTC_INTFRCH_INTFRC37            (0x20)
+#define MCF_INTC_INTFRCH_INTFRC38            (0x40)
+#define MCF_INTC_INTFRCH_INTFRC39            (0x80)
+#define MCF_INTC_INTFRCH_INTFRC40            (0x100)
+#define MCF_INTC_INTFRCH_INTFRC41            (0x200)
+#define MCF_INTC_INTFRCH_INTFRC42            (0x400)
+#define MCF_INTC_INTFRCH_INTFRC43            (0x800)
+#define MCF_INTC_INTFRCH_INTFRC44            (0x1000)
+#define MCF_INTC_INTFRCH_INTFRC45            (0x2000)
+#define MCF_INTC_INTFRCH_INTFRC46            (0x4000)
+#define MCF_INTC_INTFRCH_INTFRC47            (0x8000)
+#define MCF_INTC_INTFRCH_INTFRC48            (0x10000)
+#define MCF_INTC_INTFRCH_INTFRC49            (0x20000)
+#define MCF_INTC_INTFRCH_INTFRC50            (0x40000)
+#define MCF_INTC_INTFRCH_INTFRC51            (0x80000)
+#define MCF_INTC_INTFRCH_INTFRC52            (0x100000)
+#define MCF_INTC_INTFRCH_INTFRC53            (0x200000)
+#define MCF_INTC_INTFRCH_INTFRC54            (0x400000)
+#define MCF_INTC_INTFRCH_INTFRC55            (0x800000)
+#define MCF_INTC_INTFRCH_INTFRC56            (0x1000000)
+#define MCF_INTC_INTFRCH_INTFRC57            (0x2000000)
+#define MCF_INTC_INTFRCH_INTFRC58            (0x4000000)
+#define MCF_INTC_INTFRCH_INTFRC59            (0x8000000)
+#define MCF_INTC_INTFRCH_INTFRC60            (0x10000000)
+#define MCF_INTC_INTFRCH_INTFRC61            (0x20000000)
+#define MCF_INTC_INTFRCH_INTFRC62            (0x40000000)
+#define MCF_INTC_INTFRCH_INTFRC63            (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC_INTFRCL */
+#define MCF_INTC_INTFRCL_INTFRC1             (0x2)
+#define MCF_INTC_INTFRCL_INTFRC2             (0x4)
+#define MCF_INTC_INTFRCL_INTFRC3             (0x8)
+#define MCF_INTC_INTFRCL_INTFRC4             (0x10)
+#define MCF_INTC_INTFRCL_INTFRC5             (0x20)
+#define MCF_INTC_INTFRCL_INTFRC6             (0x40)
+#define MCF_INTC_INTFRCL_INTFRC7             (0x80)
+#define MCF_INTC_INTFRCL_INTFRC8             (0x100)
+#define MCF_INTC_INTFRCL_INTFRC9             (0x200)
+#define MCF_INTC_INTFRCL_INTFRC10            (0x400)
+#define MCF_INTC_INTFRCL_INTFRC11            (0x800)
+#define MCF_INTC_INTFRCL_INTFRC12            (0x1000)
+#define MCF_INTC_INTFRCL_INTFRC13            (0x2000)
+#define MCF_INTC_INTFRCL_INTFRC14            (0x4000)
+#define MCF_INTC_INTFRCL_INTFRC15            (0x8000)
+#define MCF_INTC_INTFRCL_INTFRC16            (0x10000)
+#define MCF_INTC_INTFRCL_INTFRC17            (0x20000)
+#define MCF_INTC_INTFRCL_INTFRC18            (0x40000)
+#define MCF_INTC_INTFRCL_INTFRC19            (0x80000)
+#define MCF_INTC_INTFRCL_INTFRC20            (0x100000)
+#define MCF_INTC_INTFRCL_INTFRC21            (0x200000)
+#define MCF_INTC_INTFRCL_INTFRC22            (0x400000)
+#define MCF_INTC_INTFRCL_INTFRC23            (0x800000)
+#define MCF_INTC_INTFRCL_INTFRC24            (0x1000000)
+#define MCF_INTC_INTFRCL_INTFRC25            (0x2000000)
+#define MCF_INTC_INTFRCL_INTFRC26            (0x4000000)
+#define MCF_INTC_INTFRCL_INTFRC27            (0x8000000)
+#define MCF_INTC_INTFRCL_INTFRC28            (0x10000000)
+#define MCF_INTC_INTFRCL_INTFRC29            (0x20000000)
+#define MCF_INTC_INTFRCL_INTFRC30            (0x40000000)
+#define MCF_INTC_INTFRCL_INTFRC31            (0x80000000)
+
+/* Bit definitions and macros for MCF_INTC_IRLR */
+#define MCF_INTC_IRLR_IRQ(x)                 (((x)&0x7F)<<0x1)
+
+/* Bit definitions and macros for MCF_INTC_IACKLPR */
+#define MCF_INTC_IACKLPR_PRI(x)              (((x)&0xF)<<0)
+#define MCF_INTC_IACKLPR_LEVEL(x)            (((x)&0x7)<<0x4)
+
+/* Bit definitions and macros for MCF_INTC_ICR */
+#define MCF_INTC_ICR_IP(x)                   (((x)&0x7)<<0)
+#define MCF_INTC_ICR_IL(x)                   (((x)&0x7)<<0x3)
+
+/* Bit definitions and macros for MCF_INTC_SWIACK */
+#define MCF_INTC_SWIACK_VECTOR(x)            (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_INTC_LIACK */
+#define MCF_INTC_LIACK_VECTOR(x)             (((x)&0xFF)<<0)
+
+
+#endif /* __MCF5475_INTC_H__ */
diff --git a/firebeeV1/headers/MCF5475_MMU.h b/firebeeV1/headers/MCF5475_MMU.h
new file mode 100644
index 0000000..84d57b9
--- /dev/null
+++ b/firebeeV1/headers/MCF5475_MMU.h
@@ -0,0 +1,77 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_MMU_H__
+#define __MCF5475_MMU_H__
+
+
+/*********************************************************************
+*
+* Memory Management Unit (MMU)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_MMU_MMUCR                        (*(vuint32*)(&__MMUBAR[0]))
+#define MCF_MMU_MMUOR                        (*(vuint32*)(&__MMUBAR[0x4]))
+#define MCF_MMU_MMUSR                        (*(vuint32*)(&__MMUBAR[0x8]))
+#define MCF_MMU_MMUAR                        (*(vuint32*)(&__MMUBAR[0x10]))
+#define MCF_MMU_MMUTR                        (*(vuint32*)(&__MMUBAR[0x14]))
+#define MCF_MMU_MMUDR                        (*(vuint32*)(&__MMUBAR[0x18]))
+
+
+/* Bit definitions and macros for MCF_MMU_MMUCR */
+#define MCF_MMU_MMUCR_EN                     (0x1)
+#define MCF_MMU_MMUCR_ASM                    (0x2)
+
+/* Bit definitions and macros for MCF_MMU_MMUOR */
+#define MCF_MMU_MMUOR_UAA                    (0x1)
+#define MCF_MMU_MMUOR_ACC                    (0x2)
+#define MCF_MMU_MMUOR_RW                     (0x4)
+#define MCF_MMU_MMUOR_ADR                    (0x8)
+#define MCF_MMU_MMUOR_ITLB                   (0x10)
+#define MCF_MMU_MMUOR_CAS                    (0x20)
+#define MCF_MMU_MMUOR_CNL                    (0x40)
+#define MCF_MMU_MMUOR_CA                     (0x80)
+#define MCF_MMU_MMUOR_STLB                   (0x100)
+#define MCF_MMU_MMUOR_AA(x)                  (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_MMU_MMUSR */
+#define MCF_MMU_MMUSR_HIT                    (0x2)
+#define MCF_MMU_MMUSR_WF                     (0x8)
+#define MCF_MMU_MMUSR_RF                     (0x10)
+#define MCF_MMU_MMUSR_SPF                    (0x20)
+
+/* Bit definitions and macros for MCF_MMU_MMUAR */
+#define MCF_MMU_MMUAR_FA(x)                  (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_MMU_MMUTR */
+#define MCF_MMU_MMUTR_V                      (0x1)
+#define MCF_MMU_MMUTR_SG                     (0x2)
+#define MCF_MMU_MMUTR_ID(x)                  (((x)&0xFF)<<0x2)
+#define MCF_MMU_MMUTR_VA(x)                  (((x)&0x3FFFFF)<<0xA)
+
+/* Bit definitions and macros for MCF_MMU_MMUDR */
+#define MCF_MMU_MMUDR_LK                     (0x2)
+#define MCF_MMU_MMUDR_X                      (0x4)
+#define MCF_MMU_MMUDR_W                      (0x8)
+#define MCF_MMU_MMUDR_R                      (0x10)
+#define MCF_MMU_MMUDR_SP                     (0x20)
+#define MCF_MMU_MMUDR_CM(x)                  (((x)&0x3)<<0x6)
+#define MCF_MMU_MMUDR_SZ(x)                  (((x)&0x3)<<0x8)
+#define MCF_MMU_MMUDR_PA(x)                  (((x)&0x3FFFFF)<<0xA)
+
+
+#endif /* __MCF5475_MMU_H__ */
diff --git a/firebeeV1/headers/MCF5475_PAD.h b/firebeeV1/headers/MCF5475_PAD.h
new file mode 100644
index 0000000..9c0fcf7
--- /dev/null
+++ b/firebeeV1/headers/MCF5475_PAD.h
@@ -0,0 +1,233 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_PAD_H__
+#define __MCF5475_PAD_H__
+
+
+/*********************************************************************
+*
+* Common GPIO
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_PAD_PAR_FBCTL                    (*(vuint16*)(&__MBAR[0xA40]))
+#define MCF_PAD_PAR_FBCS                     (*(vuint8 *)(&__MBAR[0xA42]))
+#define MCF_PAD_PAR_DMA                      (*(vuint8 *)(&__MBAR[0xA43]))
+#define MCF_PAD_PAR_FECI2CIRQ                (*(vuint16*)(&__MBAR[0xA44]))
+#define MCF_PAD_PAR_PCIBG                    (*(vuint16*)(&__MBAR[0xA48]))
+#define MCF_PAD_PAR_PCIBR                    (*(vuint16*)(&__MBAR[0xA4A]))
+#define MCF_PAD_PAR_PSC3                     (*(vuint8 *)(&__MBAR[0xA4C]))
+#define MCF_PAD_PAR_PSC2                     (*(vuint8 *)(&__MBAR[0xA4D]))
+#define MCF_PAD_PAR_PSC1                     (*(vuint8 *)(&__MBAR[0xA4E]))
+#define MCF_PAD_PAR_PSC0                     (*(vuint8 *)(&__MBAR[0xA4F]))
+#define MCF_PAD_PAR_DSPI                     (*(vuint16*)(&__MBAR[0xA50]))
+#define MCF_PAD_PAR_TIMER                    (*(vuint8 *)(&__MBAR[0xA52]))
+
+
+/* Bit definitions and macros for MCF_PAD_PAR_FBCTL */
+#define MCF_PAD_PAR_FBCTL_PAR_ALE(x)         (((x)&0x3)<<0)
+#define MCF_PAD_PAR_FBCTL_PAR_ALE_GPIO       (0)
+#define MCF_PAD_PAR_FBCTL_PAR_ALE_TBST       (0x2)
+#define MCF_PAD_PAR_FBCTL_PAR_ALE_ALE        (0x3)
+#define MCF_PAD_PAR_FBCTL_PAR_TA             (0x4)
+#define MCF_PAD_PAR_FBCTL_PAR_RWB(x)         (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_FBCTL_PAR_RWB_GPIO       (0)
+#define MCF_PAD_PAR_FBCTL_PAR_RWB_TBST       (0x20)
+#define MCF_PAD_PAR_FBCTL_PAR_RWB_RW         (0x30)
+#define MCF_PAD_PAR_FBCTL_PAR_OE             (0x40)
+#define MCF_PAD_PAR_FBCTL_PAR_BWE0           (0x100)
+#define MCF_PAD_PAR_FBCTL_PAR_BWE1           (0x400)
+#define MCF_PAD_PAR_FBCTL_PAR_BWE2           (0x1000)
+#define MCF_PAD_PAR_FBCTL_PAR_BWE3           (0x4000)
+
+/* Bit definitions and macros for MCF_PAD_PAR_FBCS */
+#define MCF_PAD_PAR_FBCS_PAR_CS1             (0x2)
+#define MCF_PAD_PAR_FBCS_PAR_CS2             (0x4)
+#define MCF_PAD_PAR_FBCS_PAR_CS3             (0x8)
+#define MCF_PAD_PAR_FBCS_PAR_CS4             (0x10)
+#define MCF_PAD_PAR_FBCS_PAR_CS5             (0x20)
+
+/* Bit definitions and macros for MCF_PAD_PAR_DMA */
+#define MCF_PAD_PAR_DMA_PAR_DREQ0(x)         (((x)&0x3)<<0)
+#define MCF_PAD_PAR_DMA_PAR_DREQ0_GPIO       (0)
+#define MCF_PAD_PAR_DMA_PAR_DREQ0_TIN0       (0x2)
+#define MCF_PAD_PAR_DMA_PAR_DREQ0_DREQ0      (0x3)
+#define MCF_PAD_PAR_DMA_PAR_DREQ1(x)         (((x)&0x3)<<0x2)
+#define MCF_PAD_PAR_DMA_PAR_DREQ1_GPIO       (0)
+#define MCF_PAD_PAR_DMA_PAR_DREQ1_IRQ1       (0x4)
+#define MCF_PAD_PAR_DMA_PAR_DREQ1_TIN1       (0x8)
+#define MCF_PAD_PAR_DMA_PAR_DREQ1_DREQ1      (0xC)
+#define MCF_PAD_PAR_DMA_PAR_DACK0(x)         (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_DMA_PAR_DACK0_GPIO       (0)
+#define MCF_PAD_PAR_DMA_PAR_DACK0_TOUT0      (0x20)
+#define MCF_PAD_PAR_DMA_PAR_DACK0_DACK0      (0x30)
+#define MCF_PAD_PAR_DMA_PAR_DACK1(x)         (((x)&0x3)<<0x6)
+#define MCF_PAD_PAR_DMA_PAR_DACK1_GPIO       (0)
+#define MCF_PAD_PAR_DMA_PAR_DACK1_TOUT1      (0x80)
+#define MCF_PAD_PAR_DMA_PAR_DACK1_DACK1      (0xC0)
+
+/* Bit definitions and macros for MCF_PAD_PAR_FECI2CIRQ */
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_IRQ5       (0x1)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_IRQ6       (0x2)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_SCL        (0x4)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_SDA        (0x8)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDC(x)   (((x)&0x3)<<0x6)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDC_SCL  (0x80)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDC_E1MDC (0xC0)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDIO(x)  (((x)&0x3)<<0x8)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDIO_SDA (0x200)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MDIO_E1MDIO (0x300)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E1MII      (0x400)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E17        (0x800)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E0MDC      (0x1000)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E0MDIO     (0x2000)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E0MII      (0x4000)
+#define MCF_PAD_PAR_FECI2CIRQ_PAR_E07        (0x8000)
+
+/* Bit definitions and macros for MCF_PAD_PAR_PCIBG */
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0(x)      (((x)&0x3)<<0)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0_GPIO    (0)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0_TOUT0   (0x2)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG0_PCIBG0  (0x3)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1(x)      (((x)&0x3)<<0x2)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1_GPIO    (0)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1_TOUT1   (0x8)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG1_PCIBG1  (0xC)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2(x)      (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2_GPIO    (0)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2_TOUT2   (0x20)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG2_PCIBG2  (0x30)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3(x)      (((x)&0x3)<<0x6)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3_GPIO    (0)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3_TOUT3   (0x80)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG3_PCIBG3  (0xC0)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4(x)      (((x)&0x3)<<0x8)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4_GPIO    (0)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4_TBST    (0x200)
+#define MCF_PAD_PAR_PCIBG_PAR_PCIBG4_PCIBG4  (0x300)
+
+/* Bit definitions and macros for MCF_PAD_PAR_PCIBR */
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0(x)      (((x)&0x3)<<0)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0_GPIO    (0)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0_TIN0    (0x2)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR0_PCIBR0  (0x3)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1(x)      (((x)&0x3)<<0x2)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1_GPIO    (0)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1_TIN1    (0x8)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR1_PCIBR1  (0xC)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2(x)      (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2_GPIO    (0)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2_TIN2    (0x20)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR2_PCIBR2  (0x30)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3(x)      (((x)&0x3)<<0x6)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3_GPIO    (0)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3_TIN3    (0x80)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR3_PCIBR3  (0xC0)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4(x)      (((x)&0x3)<<0x8)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4_GPIO    (0)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4_IRQ4    (0x200)
+#define MCF_PAD_PAR_PCIBR_PAR_PCIBR4_PCIBR4  (0x300)
+
+/* Bit definitions and macros for MCF_PAD_PAR_PSC3 */
+#define MCF_PAD_PAR_PSC3_PAR_TXD3            (0x4)
+#define MCF_PAD_PAR_PSC3_PAR_RXD3            (0x8)
+#define MCF_PAD_PAR_PSC3_PAR_RTS3(x)         (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_PSC3_PAR_RTS3_GPIO       (0)
+#define MCF_PAD_PAR_PSC3_PAR_RTS3_FSYNC      (0x20)
+#define MCF_PAD_PAR_PSC3_PAR_RTS3_RTS        (0x30)
+#define MCF_PAD_PAR_PSC3_PAR_CTS3(x)         (((x)&0x3)<<0x6)
+#define MCF_PAD_PAR_PSC3_PAR_CTS3_GPIO       (0)
+#define MCF_PAD_PAR_PSC3_PAR_CTS3_BCLK       (0x80)
+#define MCF_PAD_PAR_PSC3_PAR_CTS3_CTS        (0xC0)
+
+/* Bit definitions and macros for MCF_PAD_PAR_PSC2 */
+#define MCF_PAD_PAR_PSC2_PAR_TXD2            (0x4)
+#define MCF_PAD_PAR_PSC2_PAR_RXD2            (0x8)
+#define MCF_PAD_PAR_PSC2_PAR_RTS2(x)         (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_PSC2_PAR_RTS2_GPIO       (0)
+#define MCF_PAD_PAR_PSC2_PAR_RTS2_FSYNC      (0x20)
+#define MCF_PAD_PAR_PSC2_PAR_RTS2_RTS        (0x30)
+#define MCF_PAD_PAR_PSC2_PAR_CTS2(x)         (((x)&0x3)<<0x6)
+#define MCF_PAD_PAR_PSC2_PAR_CTS2_GPIO       (0)
+#define MCF_PAD_PAR_PSC2_PAR_CTS2_BCLK       (0x80)
+#define MCF_PAD_PAR_PSC2_PAR_CTS2_CTS        (0xC0)
+
+/* Bit definitions and macros for MCF_PAD_PAR_PSC1 */
+#define MCF_PAD_PAR_PSC1_PAR_TXD1            (0x4)
+#define MCF_PAD_PAR_PSC1_PAR_RXD1            (0x8)
+#define MCF_PAD_PAR_PSC1_PAR_RTS1(x)         (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_PSC1_PAR_RTS1_GPIO       (0)
+#define MCF_PAD_PAR_PSC1_PAR_RTS1_FSYNC      (0x20)
+#define MCF_PAD_PAR_PSC1_PAR_RTS1_RTS        (0x30)
+#define MCF_PAD_PAR_PSC1_PAR_CTS1(x)         (((x)&0x3)<<0x6)
+#define MCF_PAD_PAR_PSC1_PAR_CTS1_GPIO       (0)
+#define MCF_PAD_PAR_PSC1_PAR_CTS1_BCLK       (0x80)
+#define MCF_PAD_PAR_PSC1_PAR_CTS1_CTS        (0xC0)
+
+/* Bit definitions and macros for MCF_PAD_PAR_PSC0 */
+#define MCF_PAD_PAR_PSC0_PAR_TXD0            (0x4)
+#define MCF_PAD_PAR_PSC0_PAR_RXD0            (0x8)
+#define MCF_PAD_PAR_PSC0_PAR_RTS0(x)         (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_PSC0_PAR_RTS0_GPIO       (0)
+#define MCF_PAD_PAR_PSC0_PAR_RTS0_FSYNC      (0x20)
+#define MCF_PAD_PAR_PSC0_PAR_RTS0_RTS        (0x30)
+#define MCF_PAD_PAR_PSC0_PAR_CTS0(x)         (((x)&0x3)<<0x6)
+#define MCF_PAD_PAR_PSC0_PAR_CTS0_GPIO       (0)
+#define MCF_PAD_PAR_PSC0_PAR_CTS0_BCLK       (0x80)
+#define MCF_PAD_PAR_PSC0_PAR_CTS0_CTS        (0xC0)
+
+/* Bit definitions and macros for MCF_PAD_PAR_DSPI */
+#define MCF_PAD_PAR_DSPI_PAR_SOUT(x)         (((x)&0x3)<<0)
+#define MCF_PAD_PAR_DSPI_PAR_SOUT_GPIO       (0)
+#define MCF_PAD_PAR_DSPI_PAR_SOUT_TXD        (0x2)
+#define MCF_PAD_PAR_DSPI_PAR_SOUT_SOUT       (0x3)
+#define MCF_PAD_PAR_DSPI_PAR_SIN(x)          (((x)&0x3)<<0x2)
+#define MCF_PAD_PAR_DSPI_PAR_SIN_GPIO        (0)
+#define MCF_PAD_PAR_DSPI_PAR_SIN_RXD         (0x8)
+#define MCF_PAD_PAR_DSPI_PAR_SIN_SIN         (0xC)
+#define MCF_PAD_PAR_DSPI_PAR_SCK(x)          (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_DSPI_PAR_SCK_GPIO        (0)
+#define MCF_PAD_PAR_DSPI_PAR_SCK_BCLK        (0x10)
+#define MCF_PAD_PAR_DSPI_PAR_SCK_CTS         (0x20)
+#define MCF_PAD_PAR_DSPI_PAR_SCK_SCK         (0x30)
+#define MCF_PAD_PAR_DSPI_PAR_CS0(x)          (((x)&0x3)<<0x6)
+#define MCF_PAD_PAR_DSPI_PAR_CS0_GPIO        (0)
+#define MCF_PAD_PAR_DSPI_PAR_CS0_FSYNC       (0x40)
+#define MCF_PAD_PAR_DSPI_PAR_CS0_RTS         (0x80)
+#define MCF_PAD_PAR_DSPI_PAR_CS0_DSPICS0     (0xC0)
+#define MCF_PAD_PAR_DSPI_PAR_CS2(x)          (((x)&0x3)<<0x8)
+#define MCF_PAD_PAR_DSPI_PAR_CS2_GPIO        (0)
+#define MCF_PAD_PAR_DSPI_PAR_CS2_TOUT2       (0x200)
+#define MCF_PAD_PAR_DSPI_PAR_CS2_DSPICS2     (0x300)
+#define MCF_PAD_PAR_DSPI_PAR_CS3(x)          (((x)&0x3)<<0xA)
+#define MCF_PAD_PAR_DSPI_PAR_CS3_GPIO        (0)
+#define MCF_PAD_PAR_DSPI_PAR_CS3_TOUT3       (0x800)
+#define MCF_PAD_PAR_DSPI_PAR_CS3_DSPICS3     (0xC00)
+#define MCF_PAD_PAR_DSPI_PAR_CS5             (0x1000)
+
+/* Bit definitions and macros for MCF_PAD_PAR_TIMER */
+#define MCF_PAD_PAR_TIMER_PAR_TOUT2          (0x1)
+#define MCF_PAD_PAR_TIMER_PAR_TIN2(x)        (((x)&0x3)<<0x1)
+#define MCF_PAD_PAR_TIMER_PAR_TIN2_IRQ2      (0x4)
+#define MCF_PAD_PAR_TIMER_PAR_TIN2_TIN2      (0x6)
+#define MCF_PAD_PAR_TIMER_PAR_TOUT3          (0x8)
+#define MCF_PAD_PAR_TIMER_PAR_TIN3(x)        (((x)&0x3)<<0x4)
+#define MCF_PAD_PAR_TIMER_PAR_TIN3_IRQ3      (0x20)
+#define MCF_PAD_PAR_TIMER_PAR_TIN3_TIN3      (0x30)
+
+
+#endif /* __MCF5475_PAD_H__ */
diff --git a/firebeeV1/headers/MCF5475_PCI.h b/firebeeV1/headers/MCF5475_PCI.h
new file mode 100644
index 0000000..47e9e98
--- /dev/null
+++ b/firebeeV1/headers/MCF5475_PCI.h
@@ -0,0 +1,376 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_PCI_H__
+#define __MCF5475_PCI_H__
+
+
+/*********************************************************************
+*
+* PCI Bus Controller (PCI)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_PCI_PCIIDR                       (*(vuint32*)(&__MBAR[0xB00]))
+#define MCF_PCI_PCISCR                       (*(vuint32*)(&__MBAR[0xB04]))
+#define MCF_PCI_PCICCRIR                     (*(vuint32*)(&__MBAR[0xB08]))
+#define MCF_PCI_PCICR1                       (*(vuint32*)(&__MBAR[0xB0C]))
+#define MCF_PCI_PCIBAR0                      (*(vuint32*)(&__MBAR[0xB10]))
+#define MCF_PCI_PCIBAR1                      (*(vuint32*)(&__MBAR[0xB14]))
+#define MCF_PCI_PCICCPR                      (*(vuint32*)(&__MBAR[0xB28]))
+#define MCF_PCI_PCISID                       (*(vuint32*)(&__MBAR[0xB2C]))
+#define MCF_PCI_PCICR2                       (*(vuint32*)(&__MBAR[0xB3C]))
+#define MCF_PCI_PCIGSCR                      (*(vuint32*)(&__MBAR[0xB60]))
+#define MCF_PCI_PCITBATR0                    (*(vuint32*)(&__MBAR[0xB64]))
+#define MCF_PCI_PCITBATR1                    (*(vuint32*)(&__MBAR[0xB68]))
+#define MCF_PCI_PCITCR                       (*(vuint32*)(&__MBAR[0xB6C]))
+#define MCF_PCI_PCIIW0BTAR                   (*(vuint32*)(&__MBAR[0xB70]))
+#define MCF_PCI_PCIIW1BTAR                   (*(vuint32*)(&__MBAR[0xB74]))
+#define MCF_PCI_PCIIW2BTAR                   (*(vuint32*)(&__MBAR[0xB78]))
+#define MCF_PCI_PCIIWCR                      (*(vuint32*)(&__MBAR[0xB80]))
+#define MCF_PCI_PCIICR                       (*(vuint32*)(&__MBAR[0xB84]))
+#define MCF_PCI_PCIISR                       (*(vuint32*)(&__MBAR[0xB88]))
+#define MCF_PCI_PCICAR                       (*(vuint32*)(&__MBAR[0xBF8]))
+#define MCF_PCI_PCITPSR                      (*(vuint32*)(&__MBAR[0x8400]))
+#define MCF_PCI_PCITSAR                      (*(vuint32*)(&__MBAR[0x8404]))
+#define MCF_PCI_PCITTCR                      (*(vuint32*)(&__MBAR[0x8408]))
+#define MCF_PCI_PCITER                       (*(vuint32*)(&__MBAR[0x840C]))
+#define MCF_PCI_PCITNAR                      (*(vuint32*)(&__MBAR[0x8410]))
+#define MCF_PCI_PCITLWR                      (*(vuint32*)(&__MBAR[0x8414]))
+#define MCF_PCI_PCITDCR                      (*(vuint32*)(&__MBAR[0x8418]))
+#define MCF_PCI_PCITSR                       (*(vuint32*)(&__MBAR[0x841C]))
+#define MCF_PCI_PCITFDR                      (*(vuint32*)(&__MBAR[0x8440]))
+#define MCF_PCI_PCITFSR                      (*(vuint32*)(&__MBAR[0x8444]))
+#define MCF_PCI_PCITFCR                      (*(vuint32*)(&__MBAR[0x8448]))
+#define MCF_PCI_PCITFAR                      (*(vuint32*)(&__MBAR[0x844C]))
+#define MCF_PCI_PCITFRPR                     (*(vuint32*)(&__MBAR[0x8450]))
+#define MCF_PCI_PCITFWPR                     (*(vuint32*)(&__MBAR[0x8454]))
+#define MCF_PCI_PCIRPSR                      (*(vuint32*)(&__MBAR[0x8480]))
+#define MCF_PCI_PCIRSAR                      (*(vuint32*)(&__MBAR[0x8484]))
+#define MCF_PCI_PCIRTCR                      (*(vuint32*)(&__MBAR[0x8488]))
+#define MCF_PCI_PCIRER                       (*(vuint32*)(&__MBAR[0x848C]))
+#define MCF_PCI_PCIRNAR                      (*(vuint32*)(&__MBAR[0x8490]))
+#define MCF_PCI_PCIRDCR                      (*(vuint32*)(&__MBAR[0x8498]))
+#define MCF_PCI_PCIRSR                       (*(vuint32*)(&__MBAR[0x849C]))
+#define MCF_PCI_PCIRFDR                      (*(vuint32*)(&__MBAR[0x84C0]))
+#define MCF_PCI_PCIRFSR                      (*(vuint32*)(&__MBAR[0x84C4]))
+#define MCF_PCI_PCIRFCR                      (*(vuint32*)(&__MBAR[0x84C8]))
+#define MCF_PCI_PCIRFAR                      (*(vuint32*)(&__MBAR[0x84CC]))
+#define MCF_PCI_PCIRFRPR                     (*(vuint32*)(&__MBAR[0x84D0]))
+#define MCF_PCI_PCIRFWPR                     (*(vuint32*)(&__MBAR[0x84D4]))
+
+
+/* Bit definitions and macros for MCF_PCI_PCIIDR */
+#define MCF_PCI_PCIIDR_VENDORID(x)           (((x)&0xFFFF)<<0)
+#define MCF_PCI_PCIIDR_DEVICEID(x)           (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_PCI_PCISCR */
+#define MCF_PCI_PCISCR_IO                    (0x1)
+#define MCF_PCI_PCISCR_M                     (0x2)
+#define MCF_PCI_PCISCR_B                     (0x4)
+#define MCF_PCI_PCISCR_SP                    (0x8)
+#define MCF_PCI_PCISCR_MW                    (0x10)
+#define MCF_PCI_PCISCR_V                     (0x20)
+#define MCF_PCI_PCISCR_PER                   (0x40)
+#define MCF_PCI_PCISCR_ST                    (0x80)
+#define MCF_PCI_PCISCR_S                     (0x100)
+#define MCF_PCI_PCISCR_F                     (0x200)
+#define MCF_PCI_PCISCR_C                     (0x100000)
+#define MCF_PCI_PCISCR_66M                   (0x200000)
+#define MCF_PCI_PCISCR_R                     (0x400000)
+#define MCF_PCI_PCISCR_FC                    (0x800000)
+#define MCF_PCI_PCISCR_DP                    (0x1000000)
+#define MCF_PCI_PCISCR_DT(x)                 (((x)&0x3)<<0x19)
+#define MCF_PCI_PCISCR_TS                    (0x8000000)
+#define MCF_PCI_PCISCR_TR                    (0x10000000)
+#define MCF_PCI_PCISCR_MA                    (0x20000000)
+#define MCF_PCI_PCISCR_SE                    (0x40000000)
+#define MCF_PCI_PCISCR_PE                    (0x80000000)
+
+/* Bit definitions and macros for MCF_PCI_PCICCRIR */
+#define MCF_PCI_PCICCRIR_REVISIONID(x)       (((x)&0xFF)<<0)
+#define MCF_PCI_PCICCRIR_CLASSCODE(x)        (((x)&0xFFFFFF)<<0x8)
+
+/* Bit definitions and macros for MCF_PCI_PCICR1 */
+#define MCF_PCI_PCICR1_CACHELINESIZE(x)      (((x)&0xFF)<<0)
+#define MCF_PCI_PCICR1_LATTIMER(x)           (((x)&0xFF)<<0x8)
+#define MCF_PCI_PCICR1_HEADERTYPE(x)         (((x)&0xFF)<<0x10)
+#define MCF_PCI_PCICR1_BIST(x)               (((x)&0xFF)<<0x18)
+
+/* Bit definitions and macros for MCF_PCI_PCIBAR0 */
+#define MCF_PCI_PCIBAR0_IOM                  (0x1)
+#define MCF_PCI_PCIBAR0_RANGE(x)             (((x)&0x3)<<0x1)
+#define MCF_PCI_PCIBAR0_PREF                 (0x8)
+#define MCF_PCI_PCIBAR0_BAR0(x)              (((x)&0x3FFF)<<0x12)
+
+/* Bit definitions and macros for MCF_PCI_PCIBAR1 */
+#define MCF_PCI_PCIBAR1_IOM                  (0x1)
+#define MCF_PCI_PCIBAR1_RANGE(x)             (((x)&0x3)<<0x1)
+#define MCF_PCI_PCIBAR1_PREF                 (0x8)
+#define MCF_PCI_PCIBAR1_BAR1(x)              (((x)&0x3)<<0x1E)
+
+/* Bit definitions and macros for MCF_PCI_PCICCPR */
+#define MCF_PCI_PCICCPR_PCICCP(x)            (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCISID */
+#define MCF_PCI_PCISID_VENDORID(x)           (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCICR2 */
+#define MCF_PCI_PCICR2_INTLINE(x)            (((x)&0xFF)<<0)
+#define MCF_PCI_PCICR2_INTPIN(x)             (((x)&0xFF)<<0x8)
+#define MCF_PCI_PCICR2_MINGNT(x)             (((x)&0xFF)<<0x10)
+#define MCF_PCI_PCICR2_MAXLAT(x)             (((x)&0xFF)<<0x18)
+
+/* Bit definitions and macros for MCF_PCI_PCIGSCR */
+#define MCF_PCI_PCIGSCR_PR                   (0x1)
+#define MCF_PCI_PCIGSCR_SEE                  (0x1000)
+#define MCF_PCI_PCIGSCR_PEE                  (0x2000)
+#define MCF_PCI_PCIGSCR_CLKINRESERVED(x)     (((x)&0x7)<<0x10)
+#define MCF_PCI_PCIGSCR_XLB2CLKIN(x)         (((x)&0x7)<<0x18)
+#define MCF_PCI_PCIGSCR_SE                   (0x10000000)
+#define MCF_PCI_PCIGSCR_PE                   (0x20000000)
+
+/* Bit definitions and macros for MCF_PCI_PCITBATR0 */
+#define MCF_PCI_PCITBATR0_EN                 (0x1)
+#define MCF_PCI_PCITBATR0_BAT0(x)            (((x)&0x3FFF)<<0x12)
+
+/* Bit definitions and macros for MCF_PCI_PCITBATR1 */
+#define MCF_PCI_PCITBATR1_EN                 (0x1)
+#define MCF_PCI_PCITBATR1_BAT1(x)            (((x)&0x3)<<0x1E)
+
+/* Bit definitions and macros for MCF_PCI_PCITCR */
+#define MCF_PCI_PCITCR_P                     (0x10000)
+#define MCF_PCI_PCITCR_LD                    (0x1000000)
+
+/* Bit definitions and macros for MCF_PCI_PCIIW0BTAR */
+#define MCF_PCI_PCIIW0BTAR_WTA0(x)           (((x)&0xFF)<<0x8)
+#define MCF_PCI_PCIIW0BTAR_WAM0(x)           (((x)&0xFF)<<0x10)
+#define MCF_PCI_PCIIW0BTAR_WBA0(x)           (((x)&0xFF)<<0x18)
+
+/* Bit definitions and macros for MCF_PCI_PCIIW1BTAR */
+#define MCF_PCI_PCIIW1BTAR_WTA1(x)           (((x)&0xFF)<<0x8)
+#define MCF_PCI_PCIIW1BTAR_WAM1(x)           (((x)&0xFF)<<0x10)
+#define MCF_PCI_PCIIW1BTAR_WBA1(x)           (((x)&0xFF)<<0x18)
+
+/* Bit definitions and macros for MCF_PCI_PCIIW2BTAR */
+#define MCF_PCI_PCIIW2BTAR_WTA2(x)           (((x)&0xFF)<<0x8)
+#define MCF_PCI_PCIIW2BTAR_WAM2(x)           (((x)&0xFF)<<0x10)
+#define MCF_PCI_PCIIW2BTAR_WBA2(x)           (((x)&0xFF)<<0x18)
+
+/* Bit definitions and macros for MCF_PCI_PCIIWCR */
+#define MCF_PCI_PCIIWCR_WINCTRL2_E           (0x100)
+#define MCF_PCI_PCIIWCR_WINCTRL2_PRC(x)      (((x)&0x3)<<0x9)
+#define MCF_PCI_PCIIWCR_WINCTRL2_IOM         (0x800)
+#define MCF_PCI_PCIIWCR_WINCTRL1_E           (0x10000)
+#define MCF_PCI_PCIIWCR_WINCTRL1_PRC(x)      (((x)&0x3)<<0x11)
+#define MCF_PCI_PCIIWCR_WINCTRL1_IOM         (0x80000)
+#define MCF_PCI_PCIIWCR_WINCTRL0_E           (0x1000000)
+#define MCF_PCI_PCIIWCR_WINCTRL0_PRC(x)      (((x)&0x3)<<0x19)
+#define MCF_PCI_PCIIWCR_WINCTRL0_IOM         (0x8000000)
+#define MCF_PCI_PCIIWCR_WINCTRL2_MEMREAD     (0x100)
+#define MCF_PCI_PCIIWCR_WINCTRL2_MEMRDLINE   (0x300)
+#define MCF_PCI_PCIIWCR_WINCTRL2_MEMRDMUL    (0x500)
+#define MCF_PCI_PCIIWCR_WINCTRL2_IO          (0x900)
+#define MCF_PCI_PCIIWCR_WINCTRL1_MEMREAD     (0x10000)
+#define MCF_PCI_PCIIWCR_WINCTRL1_MEMRDLINE   (0x30000)
+#define MCF_PCI_PCIIWCR_WINCTRL1_MEMRDMUL    (0x50000)
+#define MCF_PCI_PCIIWCR_WINCTRL1_IO          (0x90000)
+#define MCF_PCI_PCIIWCR_WINCTRL0_MEMREAD     (0x1000000)
+#define MCF_PCI_PCIIWCR_WINCTRL0_MEMRDLINE   (0x3000000)
+#define MCF_PCI_PCIIWCR_WINCTRL0_MEMRDMUL    (0x5000000)
+#define MCF_PCI_PCIIWCR_WINCTRL0_IO          (0x9000000)
+
+/* Bit definitions and macros for MCF_PCI_PCIICR */
+#define MCF_PCI_PCIICR_MAXRETRY(x)           (((x)&0xFF)<<0)
+#define MCF_PCI_PCIICR_TAE                   (0x1000000)
+#define MCF_PCI_PCIICR_IAE                   (0x2000000)
+#define MCF_PCI_PCIICR_REE                   (0x4000000)
+
+/* Bit definitions and macros for MCF_PCI_PCIISR */
+#define MCF_PCI_PCIISR_TA                    (0x1000000)
+#define MCF_PCI_PCIISR_IA                    (0x2000000)
+#define MCF_PCI_PCIISR_RE                    (0x4000000)
+
+/* Bit definitions and macros for MCF_PCI_PCICAR */
+#define MCF_PCI_PCICAR_DWORD(x)              (((x)&0x3F)<<0x2)
+#define MCF_PCI_PCICAR_FUNCNUM(x)            (((x)&0x7)<<0x8)
+#define MCF_PCI_PCICAR_DEVNUM(x)             (((x)&0x1F)<<0xB)
+#define MCF_PCI_PCICAR_BUSNUM(x)             (((x)&0xFF)<<0x10)
+#define MCF_PCI_PCICAR_E                     (0x80000000)
+
+/* Bit definitions and macros for MCF_PCI_PCITPSR */
+#define MCF_PCI_PCITPSR_PKTSIZE(x)           (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_PCI_PCITSAR */
+#define MCF_PCI_PCITSAR_STARTADD(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCITTCR */
+#define MCF_PCI_PCITTCR_DI                   (0x1)
+#define MCF_PCI_PCITTCR_W                    (0x10)
+#define MCF_PCI_PCITTCR_MAXBEATS(x)          (((x)&0x7)<<0x8)
+#define MCF_PCI_PCITTCR_MAXRETRY(x)          (((x)&0xFF)<<0x10)
+#define MCF_PCI_PCITTCR_PCICMD(x)            (((x)&0xF)<<0x18)
+
+/* Bit definitions and macros for MCF_PCI_PCITER */
+#define MCF_PCI_PCITER_NE                    (0x10000)
+#define MCF_PCI_PCITER_IAE                   (0x20000)
+#define MCF_PCI_PCITER_TAE                   (0x40000)
+#define MCF_PCI_PCITER_RE                    (0x80000)
+#define MCF_PCI_PCITER_SE                    (0x100000)
+#define MCF_PCI_PCITER_FEE                   (0x200000)
+#define MCF_PCI_PCITER_ME                    (0x1000000)
+#define MCF_PCI_PCITER_BE                    (0x8000000)
+#define MCF_PCI_PCITER_CM                    (0x10000000)
+#define MCF_PCI_PCITER_RF                    (0x40000000)
+#define MCF_PCI_PCITER_RC                    (0x80000000)
+
+/* Bit definitions and macros for MCF_PCI_PCITNAR */
+#define MCF_PCI_PCITNAR_NEXTADDRESS(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCITLWR */
+#define MCF_PCI_PCITLWR_LASTWORD(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCITDCR */
+#define MCF_PCI_PCITDCR_PKTSDONE(x)          (((x)&0xFFFF)<<0)
+#define MCF_PCI_PCITDCR_BYTESDONE(x)         (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_PCI_PCITSR */
+#define MCF_PCI_PCITSR_IA                    (0x10000)
+#define MCF_PCI_PCITSR_TA                    (0x20000)
+#define MCF_PCI_PCITSR_RE                    (0x40000)
+#define MCF_PCI_PCITSR_SE                    (0x80000)
+#define MCF_PCI_PCITSR_FE                    (0x100000)
+#define MCF_PCI_PCITSR_BE1                   (0x200000)
+#define MCF_PCI_PCITSR_BE2                   (0x400000)
+#define MCF_PCI_PCITSR_BE3                   (0x800000)
+#define MCF_PCI_PCITSR_NT                    (0x1000000)
+
+/* Bit definitions and macros for MCF_PCI_PCITFDR */
+#define MCF_PCI_PCITFDR_FIFODATAWORD(x)      (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCITFSR */
+#define MCF_PCI_PCITFSR_EMPTY                (0x10000)
+#define MCF_PCI_PCITFSR_ALARM                (0x20000)
+#define MCF_PCI_PCITFSR_FULL                 (0x40000)
+#define MCF_PCI_PCITFSR_FR                   (0x80000)
+#define MCF_PCI_PCITFSR_OF                   (0x100000)
+#define MCF_PCI_PCITFSR_UF                   (0x200000)
+#define MCF_PCI_PCITFSR_RXW                  (0x400000)
+#define MCF_PCI_PCITFSR_FAE                  (0x800000)
+#define MCF_PCI_PCITFSR_TXW                  (0x40000000)
+#define MCF_PCI_PCITFSR_IP                   (0x80000000)
+
+/* Bit definitions and macros for MCF_PCI_PCITFCR */
+#define MCF_PCI_PCITFCR_TXW_MASK             (0x40000)
+#define MCF_PCI_PCITFCR_OF_MASK              (0x80000)
+#define MCF_PCI_PCITFCR_UF_MASK              (0x100000)
+#define MCF_PCI_PCITFCR_RXW_MASK             (0x200000)
+#define MCF_PCI_PCITFCR_FAE_MASK             (0x400000)
+#define MCF_PCI_PCITFCR_IP_MASK              (0x800000)
+#define MCF_PCI_PCITFCR_GR(x)                (((x)&0x7)<<0x18)
+#define MCF_PCI_PCITFCR_WFR                  (0x20000000)
+
+/* Bit definitions and macros for MCF_PCI_PCITFAR */
+#define MCF_PCI_PCITFAR_ALARM(x)             (((x)&0xFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCITFRPR */
+#define MCF_PCI_PCITFRPR_READPTR(x)          (((x)&0x7F)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCITFWPR */
+#define MCF_PCI_PCITFWPR_WRITEPTR(x)         (((x)&0x7F)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCIRPSR */
+#define MCF_PCI_PCIRPSR_PKTSIZE(x)           (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_PCI_PCIRSAR */
+#define MCF_PCI_PCIRSAR_STARTADD(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCIRTCR */
+#define MCF_PCI_PCIRTCR_DI                   (0x1)
+#define MCF_PCI_PCIRTCR_W                    (0x10)
+#define MCF_PCI_PCIRTCR_MAXBEATS(x)          (((x)&0x7)<<0x8)
+#define MCF_PCI_PCIRTCR_FB                   (0x1000)
+#define MCF_PCI_PCIRTCR_MAXRETRY(x)          (((x)&0xFF)<<0x10)
+#define MCF_PCI_PCIRTCR_PCICMD(x)            (((x)&0xF)<<0x18)
+
+/* Bit definitions and macros for MCF_PCI_PCIRER */
+#define MCF_PCI_PCIRER_NE                    (0x10000)
+#define MCF_PCI_PCIRER_IAE                   (0x20000)
+#define MCF_PCI_PCIRER_TAE                   (0x40000)
+#define MCF_PCI_PCIRER_RE                    (0x80000)
+#define MCF_PCI_PCIRER_SE                    (0x100000)
+#define MCF_PCI_PCIRER_FEE                   (0x200000)
+#define MCF_PCI_PCIRER_ME                    (0x1000000)
+#define MCF_PCI_PCIRER_BE                    (0x8000000)
+#define MCF_PCI_PCIRER_CM                    (0x10000000)
+#define MCF_PCI_PCIRER_FE                    (0x20000000)
+#define MCF_PCI_PCIRER_RF                    (0x40000000)
+#define MCF_PCI_PCIRER_RC                    (0x80000000)
+
+/* Bit definitions and macros for MCF_PCI_PCIRNAR */
+#define MCF_PCI_PCIRNAR_NEXTADDRESS(x)       (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCIRDCR */
+#define MCF_PCI_PCIRDCR_PKTSDONE(x)          (((x)&0xFFFF)<<0)
+#define MCF_PCI_PCIRDCR_BYTESDONE(x)         (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_PCI_PCIRSR */
+#define MCF_PCI_PCIRSR_IA                    (0x10000)
+#define MCF_PCI_PCIRSR_TA                    (0x20000)
+#define MCF_PCI_PCIRSR_RE                    (0x40000)
+#define MCF_PCI_PCIRSR_SE                    (0x80000)
+#define MCF_PCI_PCIRSR_FE                    (0x100000)
+#define MCF_PCI_PCIRSR_BE1                   (0x200000)
+#define MCF_PCI_PCIRSR_BE2                   (0x400000)
+#define MCF_PCI_PCIRSR_BE3                   (0x800000)
+#define MCF_PCI_PCIRSR_NT                    (0x1000000)
+
+/* Bit definitions and macros for MCF_PCI_PCIRFDR */
+#define MCF_PCI_PCIRFDR_FIFODATAWORD(x)      (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCIRFSR */
+#define MCF_PCI_PCIRFSR_EMPTY                (0x10000)
+#define MCF_PCI_PCIRFSR_ALARM                (0x20000)
+#define MCF_PCI_PCIRFSR_FULL                 (0x40000)
+#define MCF_PCI_PCIRFSR_FR                   (0x80000)
+#define MCF_PCI_PCIRFSR_OF                   (0x100000)
+#define MCF_PCI_PCIRFSR_UF                   (0x200000)
+#define MCF_PCI_PCIRFSR_RXW                  (0x400000)
+#define MCF_PCI_PCIRFSR_FAE                  (0x800000)
+#define MCF_PCI_PCIRFSR_TXW                  (0x40000000)
+#define MCF_PCI_PCIRFSR_IP                   (0x80000000)
+
+/* Bit definitions and macros for MCF_PCI_PCIRFCR */
+#define MCF_PCI_PCIRFCR_TXW_MASK             (0x40000)
+#define MCF_PCI_PCIRFCR_OF_MASK              (0x80000)
+#define MCF_PCI_PCIRFCR_UF_MASK              (0x100000)
+#define MCF_PCI_PCIRFCR_RXW_MASK             (0x200000)
+#define MCF_PCI_PCIRFCR_FAE_MASK             (0x400000)
+#define MCF_PCI_PCIRFCR_IP_MASK              (0x800000)
+#define MCF_PCI_PCIRFCR_GR(x)                (((x)&0x7)<<0x18)
+#define MCF_PCI_PCIRFCR_WFR                  (0x20000000)
+
+/* Bit definitions and macros for MCF_PCI_PCIRFAR */
+#define MCF_PCI_PCIRFAR_ALARM(x)             (((x)&0x7F)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCIRFRPR */
+#define MCF_PCI_PCIRFRPR_READPTR(x)          (((x)&0x7F)<<0)
+
+/* Bit definitions and macros for MCF_PCI_PCIRFWPR */
+#define MCF_PCI_PCIRFWPR_WRITEPTR(x)         (((x)&0x7F)<<0)
+
+
+#endif /* __MCF5475_PCI_H__ */
diff --git a/firebeeV1/headers/MCF5475_PCIARB.h b/firebeeV1/headers/MCF5475_PCIARB.h
new file mode 100644
index 0000000..3e793a1
--- /dev/null
+++ b/firebeeV1/headers/MCF5475_PCIARB.h
@@ -0,0 +1,43 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_PCIARB_H__
+#define __MCF5475_PCIARB_H__
+
+
+/*********************************************************************
+*
+* PCI Bus Arbiter Module (PCIARB)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_PCIARB_PACR                      (*(vuint32*)(&__MBAR[0xC00]))
+#define MCF_PCIARB_PASR                      (*(vuint32*)(&__MBAR[0xC04]))
+
+
+/* Bit definitions and macros for MCF_PCIARB_PACR */
+#define MCF_PCIARB_PACR_INTMPRI              (0x1)
+#define MCF_PCIARB_PACR_EXTMPRI(x)           (((x)&0x1F)<<0x1)
+#define MCF_PCIARB_PACR_INTMINTEN            (0x10000)
+#define MCF_PCIARB_PACR_EXTMINTEN(x)         (((x)&0x1F)<<0x11)
+#define MCF_PCIARB_PACR_DS                   (0x80000000)
+
+/* Bit definitions and macros for MCF_PCIARB_PASR */
+#define MCF_PCIARB_PASR_ITLMBK               (0x10000)
+#define MCF_PCIARB_PASR_EXTMBK(x)            (((x)&0x1F)<<0x11)
+
+
+#endif /* __MCF5475_PCIARB_H__ */
diff --git a/firebeeV1/headers/MCF5475_PSC.h b/firebeeV1/headers/MCF5475_PSC.h
new file mode 100644
index 0000000..2165c57
--- /dev/null
+++ b/firebeeV1/headers/MCF5475_PSC.h
@@ -0,0 +1,527 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_PSC_H__
+#define __MCF5475_PSC_H__
+
+
+/*********************************************************************
+*
+* Programmable Serial Controller (PSC)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_PSC0_PSCMR2                      (*(vuint8 *)(&__MBAR[0x8600]))
+#define MCF_PSC0_PSCMR1                      (*(vuint8 *)(&__MBAR[0x8600]))
+#define MCF_PSC0_PSCCSR                      (*(vuint8 *)(&__MBAR[0x8604]))
+#define MCF_PSC0_PSCSR                       (*(vuint16*)(&__MBAR[0x8604]))
+#define MCF_PSC0_PSCCR                       (*(vuint8 *)(&__MBAR[0x8608]))
+#define MCF_PSC0_PSCRB_8BIT                  (*(vuint32*)(&__MBAR[0x860C]))
+#define MCF_PSC0_PSCTB_8BIT                  (*(vuint32*)(&__MBAR[0x860C]))
+#define MCF_PSC0_PSCRB_16BIT                 (*(vuint32*)(&__MBAR[0x860C]))
+#define MCF_PSC0_PSCTB_16BIT                 (*(vuint32*)(&__MBAR[0x860C]))
+#define MCF_PSC0_PSCRB_AC97                  (*(vuint32*)(&__MBAR[0x860C]))
+#define MCF_PSC0_PSCTB_AC97                  (*(vuint32*)(&__MBAR[0x860C]))
+#define MCF_PSC0_PSCIPCR                     (*(vuint8 *)(&__MBAR[0x8610]))
+#define MCF_PSC0_PSCACR                      (*(vuint8 *)(&__MBAR[0x8610]))
+#define MCF_PSC0_PSCIMR                      (*(vuint16*)(&__MBAR[0x8614]))
+#define MCF_PSC0_PSCISR                      (*(vuint16*)(&__MBAR[0x8614]))
+#define MCF_PSC0_PSCCTUR                     (*(vuint8 *)(&__MBAR[0x8618]))
+#define MCF_PSC0_PSCCTLR                     (*(vuint8 *)(&__MBAR[0x861C]))
+#define MCF_PSC0_PSCIP                       (*(vuint8 *)(&__MBAR[0x8634]))
+#define MCF_PSC0_PSCOPSET                    (*(vuint8 *)(&__MBAR[0x8638]))
+#define MCF_PSC0_PSCOPRESET                  (*(vuint8 *)(&__MBAR[0x863C]))
+#define MCF_PSC0_PSCSICR                     (*(vuint8 *)(&__MBAR[0x8640]))
+#define MCF_PSC0_PSCIRCR1                    (*(vuint8 *)(&__MBAR[0x8644]))
+#define MCF_PSC0_PSCIRCR2                    (*(vuint8 *)(&__MBAR[0x8648]))
+#define MCF_PSC0_PSCIRSDR                    (*(vuint8 *)(&__MBAR[0x864C]))
+#define MCF_PSC0_PSCIRMDR                    (*(vuint8 *)(&__MBAR[0x8650]))
+#define MCF_PSC0_PSCIRFDR                    (*(vuint8 *)(&__MBAR[0x8654]))
+#define MCF_PSC0_PSCRFCNT                    (*(vuint16*)(&__MBAR[0x8658]))
+#define MCF_PSC0_PSCTFCNT                    (*(vuint16*)(&__MBAR[0x865C]))
+#define MCF_PSC0_PSCRFDR                     (*(vuint32*)(&__MBAR[0x8660]))
+#define MCF_PSC0_PSCRFSR                     (*(vuint16*)(&__MBAR[0x8664]))
+#define MCF_PSC0_PSCRFCR                     (*(vuint32*)(&__MBAR[0x8668]))
+#define MCF_PSC0_PSCRFAR                     (*(vuint16*)(&__MBAR[0x866E]))
+#define MCF_PSC0_PSCRFRP                     (*(vuint16*)(&__MBAR[0x8672]))
+#define MCF_PSC0_PSCRFWP                     (*(vuint16*)(&__MBAR[0x8676]))
+#define MCF_PSC0_PSCRLRFP                    (*(vuint16*)(&__MBAR[0x867A]))
+#define MCF_PSC0_PSCRLWFP                    (*(vuint16*)(&__MBAR[0x867E]))
+#define MCF_PSC0_PSCTFDR                     (*(vuint32*)(&__MBAR[0x8680]))
+#define MCF_PSC0_PSCTFSR                     (*(vuint16*)(&__MBAR[0x8684]))
+#define MCF_PSC0_PSCTFCR                     (*(vuint32*)(&__MBAR[0x8688]))
+#define MCF_PSC0_PSCTFAR                     (*(vuint16*)(&__MBAR[0x868E]))
+#define MCF_PSC0_PSCTFRP                     (*(vuint16*)(&__MBAR[0x8692]))
+#define MCF_PSC0_PSCTFWP                     (*(vuint16*)(&__MBAR[0x8696]))
+#define MCF_PSC0_PSCTLRFP                    (*(vuint16*)(&__MBAR[0x869A]))
+#define MCF_PSC0_PSCTLWFP                    (*(vuint16*)(&__MBAR[0x869E]))
+
+#define MCF_PSC1_PSCMR2                      (*(vuint8 *)(&__MBAR[0x8700]))
+#define MCF_PSC1_PSCMR1                      (*(vuint8 *)(&__MBAR[0x8700]))
+#define MCF_PSC1_PSCCSR                      (*(vuint8 *)(&__MBAR[0x8704]))
+#define MCF_PSC1_PSCSR                       (*(vuint16*)(&__MBAR[0x8704]))
+#define MCF_PSC1_PSCCR                       (*(vuint8 *)(&__MBAR[0x8708]))
+#define MCF_PSC1_PSCRB_8BIT                  (*(vuint32*)(&__MBAR[0x870C]))
+#define MCF_PSC1_PSCTB_8BIT                  (*(vuint32*)(&__MBAR[0x870C]))
+#define MCF_PSC1_PSCRB_16BIT                 (*(vuint32*)(&__MBAR[0x870C]))
+#define MCF_PSC1_PSCTB_16BIT                 (*(vuint32*)(&__MBAR[0x870C]))
+#define MCF_PSC1_PSCRB_AC97                  (*(vuint32*)(&__MBAR[0x870C]))
+#define MCF_PSC1_PSCTB_AC97                  (*(vuint32*)(&__MBAR[0x870C]))
+#define MCF_PSC1_PSCIPCR                     (*(vuint8 *)(&__MBAR[0x8710]))
+#define MCF_PSC1_PSCACR                      (*(vuint8 *)(&__MBAR[0x8710]))
+#define MCF_PSC1_PSCIMR                      (*(vuint16*)(&__MBAR[0x8714]))
+#define MCF_PSC1_PSCISR                      (*(vuint16*)(&__MBAR[0x8714]))
+#define MCF_PSC1_PSCCTUR                     (*(vuint8 *)(&__MBAR[0x8718]))
+#define MCF_PSC1_PSCCTLR                     (*(vuint8 *)(&__MBAR[0x871C]))
+#define MCF_PSC1_PSCIP                       (*(vuint8 *)(&__MBAR[0x8734]))
+#define MCF_PSC1_PSCOPSET                    (*(vuint8 *)(&__MBAR[0x8738]))
+#define MCF_PSC1_PSCOPRESET                  (*(vuint8 *)(&__MBAR[0x873C]))
+#define MCF_PSC1_PSCSICR                     (*(vuint8 *)(&__MBAR[0x8740]))
+#define MCF_PSC1_PSCIRCR1                    (*(vuint8 *)(&__MBAR[0x8744]))
+#define MCF_PSC1_PSCIRCR2                    (*(vuint8 *)(&__MBAR[0x8748]))
+#define MCF_PSC1_PSCIRSDR                    (*(vuint8 *)(&__MBAR[0x874C]))
+#define MCF_PSC1_PSCIRMDR                    (*(vuint8 *)(&__MBAR[0x8750]))
+#define MCF_PSC1_PSCIRFDR                    (*(vuint8 *)(&__MBAR[0x8754]))
+#define MCF_PSC1_PSCRFCNT                    (*(vuint16*)(&__MBAR[0x8758]))
+#define MCF_PSC1_PSCTFCNT                    (*(vuint16*)(&__MBAR[0x875C]))
+#define MCF_PSC1_PSCRFDR                     (*(vuint32*)(&__MBAR[0x8760]))
+#define MCF_PSC1_PSCRFSR                     (*(vuint16*)(&__MBAR[0x8764]))
+#define MCF_PSC1_PSCRFCR                     (*(vuint32*)(&__MBAR[0x8768]))
+#define MCF_PSC1_PSCRFAR                     (*(vuint16*)(&__MBAR[0x876E]))
+#define MCF_PSC1_PSCRFRP                     (*(vuint16*)(&__MBAR[0x8772]))
+#define MCF_PSC1_PSCRFWP                     (*(vuint16*)(&__MBAR[0x8776]))
+#define MCF_PSC1_PSCRLRFP                    (*(vuint16*)(&__MBAR[0x877A]))
+#define MCF_PSC1_PSCRLWFP                    (*(vuint16*)(&__MBAR[0x877E]))
+#define MCF_PSC1_PSCTFDR                     (*(vuint32*)(&__MBAR[0x8780]))
+#define MCF_PSC1_PSCTFSR                     (*(vuint16*)(&__MBAR[0x8784]))
+#define MCF_PSC1_PSCTFCR                     (*(vuint32*)(&__MBAR[0x8788]))
+#define MCF_PSC1_PSCTFAR                     (*(vuint16*)(&__MBAR[0x878E]))
+#define MCF_PSC1_PSCTFRP                     (*(vuint16*)(&__MBAR[0x8792]))
+#define MCF_PSC1_PSCTFWP                     (*(vuint16*)(&__MBAR[0x8796]))
+#define MCF_PSC1_PSCTLRFP                    (*(vuint16*)(&__MBAR[0x879A]))
+#define MCF_PSC1_PSCTLWFP                    (*(vuint16*)(&__MBAR[0x879E]))
+
+#define MCF_PSC2_PSCMR2                      (*(vuint8 *)(&__MBAR[0x8800]))
+#define MCF_PSC2_PSCMR1                      (*(vuint8 *)(&__MBAR[0x8800]))
+#define MCF_PSC2_PSCCSR                      (*(vuint8 *)(&__MBAR[0x8804]))
+#define MCF_PSC2_PSCSR                       (*(vuint16*)(&__MBAR[0x8804]))
+#define MCF_PSC2_PSCCR                       (*(vuint8 *)(&__MBAR[0x8808]))
+#define MCF_PSC2_PSCRB_8BIT                  (*(vuint32*)(&__MBAR[0x880C]))
+#define MCF_PSC2_PSCTB_8BIT                  (*(vuint32*)(&__MBAR[0x880C]))
+#define MCF_PSC2_PSCRB_16BIT                 (*(vuint32*)(&__MBAR[0x880C]))
+#define MCF_PSC2_PSCTB_16BIT                 (*(vuint32*)(&__MBAR[0x880C]))
+#define MCF_PSC2_PSCRB_AC97                  (*(vuint32*)(&__MBAR[0x880C]))
+#define MCF_PSC2_PSCTB_AC97                  (*(vuint32*)(&__MBAR[0x880C]))
+#define MCF_PSC2_PSCIPCR                     (*(vuint8 *)(&__MBAR[0x8810]))
+#define MCF_PSC2_PSCACR                      (*(vuint8 *)(&__MBAR[0x8810]))
+#define MCF_PSC2_PSCIMR                      (*(vuint16*)(&__MBAR[0x8814]))
+#define MCF_PSC2_PSCISR                      (*(vuint16*)(&__MBAR[0x8814]))
+#define MCF_PSC2_PSCCTUR                     (*(vuint8 *)(&__MBAR[0x8818]))
+#define MCF_PSC2_PSCCTLR                     (*(vuint8 *)(&__MBAR[0x881C]))
+#define MCF_PSC2_PSCIP                       (*(vuint8 *)(&__MBAR[0x8834]))
+#define MCF_PSC2_PSCOPSET                    (*(vuint8 *)(&__MBAR[0x8838]))
+#define MCF_PSC2_PSCOPRESET                  (*(vuint8 *)(&__MBAR[0x883C]))
+#define MCF_PSC2_PSCSICR                     (*(vuint8 *)(&__MBAR[0x8840]))
+#define MCF_PSC2_PSCIRCR1                    (*(vuint8 *)(&__MBAR[0x8844]))
+#define MCF_PSC2_PSCIRCR2                    (*(vuint8 *)(&__MBAR[0x8848]))
+#define MCF_PSC2_PSCIRSDR                    (*(vuint8 *)(&__MBAR[0x884C]))
+#define MCF_PSC2_PSCIRMDR                    (*(vuint8 *)(&__MBAR[0x8850]))
+#define MCF_PSC2_PSCIRFDR                    (*(vuint8 *)(&__MBAR[0x8854]))
+#define MCF_PSC2_PSCRFCNT                    (*(vuint16*)(&__MBAR[0x8858]))
+#define MCF_PSC2_PSCTFCNT                    (*(vuint16*)(&__MBAR[0x885C]))
+#define MCF_PSC2_PSCRFDR                     (*(vuint32*)(&__MBAR[0x8860]))
+#define MCF_PSC2_PSCRFSR                     (*(vuint16*)(&__MBAR[0x8864]))
+#define MCF_PSC2_PSCRFCR                     (*(vuint32*)(&__MBAR[0x8868]))
+#define MCF_PSC2_PSCRFAR                     (*(vuint16*)(&__MBAR[0x886E]))
+#define MCF_PSC2_PSCRFRP                     (*(vuint16*)(&__MBAR[0x8872]))
+#define MCF_PSC2_PSCRFWP                     (*(vuint16*)(&__MBAR[0x8876]))
+#define MCF_PSC2_PSCRLRFP                    (*(vuint16*)(&__MBAR[0x887A]))
+#define MCF_PSC2_PSCRLWFP                    (*(vuint16*)(&__MBAR[0x887E]))
+#define MCF_PSC2_PSCTFDR                     (*(vuint32*)(&__MBAR[0x8880]))
+#define MCF_PSC2_PSCTFSR                     (*(vuint16*)(&__MBAR[0x8884]))
+#define MCF_PSC2_PSCTFCR                     (*(vuint32*)(&__MBAR[0x8888]))
+#define MCF_PSC2_PSCTFAR                     (*(vuint16*)(&__MBAR[0x888E]))
+#define MCF_PSC2_PSCTFRP                     (*(vuint16*)(&__MBAR[0x8892]))
+#define MCF_PSC2_PSCTFWP                     (*(vuint16*)(&__MBAR[0x8896]))
+#define MCF_PSC2_PSCTLRFP                    (*(vuint16*)(&__MBAR[0x889A]))
+#define MCF_PSC2_PSCTLWFP                    (*(vuint16*)(&__MBAR[0x889E]))
+
+#define MCF_PSC3_PSCMR2                      (*(vuint8 *)(&__MBAR[0x8900]))
+#define MCF_PSC3_PSCMR1                      (*(vuint8 *)(&__MBAR[0x8900]))
+#define MCF_PSC3_PSCCSR                      (*(vuint8 *)(&__MBAR[0x8904]))
+#define MCF_PSC3_PSCSR                       (*(vuint16*)(&__MBAR[0x8904]))
+#define MCF_PSC3_PSCCR                       (*(vuint8 *)(&__MBAR[0x8908]))
+#define MCF_PSC3_PSCRB_8BIT                  (*(vuint32*)(&__MBAR[0x890C]))
+#define MCF_PSC3_PSCTB_8BIT                  (*(vuint32*)(&__MBAR[0x890C]))
+#define MCF_PSC3_PSCRB_16BIT                 (*(vuint32*)(&__MBAR[0x890C]))
+#define MCF_PSC3_PSCTB_16BIT                 (*(vuint32*)(&__MBAR[0x890C]))
+#define MCF_PSC3_PSCRB_AC97                  (*(vuint32*)(&__MBAR[0x890C]))
+#define MCF_PSC3_PSCTB_AC97                  (*(vuint32*)(&__MBAR[0x890C]))
+#define MCF_PSC3_PSCIPCR                     (*(vuint8 *)(&__MBAR[0x8910]))
+#define MCF_PSC3_PSCACR                      (*(vuint8 *)(&__MBAR[0x8910]))
+#define MCF_PSC3_PSCIMR                      (*(vuint16*)(&__MBAR[0x8914]))
+#define MCF_PSC3_PSCISR                      (*(vuint16*)(&__MBAR[0x8914]))
+#define MCF_PSC3_PSCCTUR                     (*(vuint8 *)(&__MBAR[0x8918]))
+#define MCF_PSC3_PSCCTLR                     (*(vuint8 *)(&__MBAR[0x891C]))
+#define MCF_PSC3_PSCIP                       (*(vuint8 *)(&__MBAR[0x8934]))
+#define MCF_PSC3_PSCOPSET                    (*(vuint8 *)(&__MBAR[0x8938]))
+#define MCF_PSC3_PSCOPRESET                  (*(vuint8 *)(&__MBAR[0x893C]))
+#define MCF_PSC3_PSCSICR                     (*(vuint8 *)(&__MBAR[0x8940]))
+#define MCF_PSC3_PSCIRCR1                    (*(vuint8 *)(&__MBAR[0x8944]))
+#define MCF_PSC3_PSCIRCR2                    (*(vuint8 *)(&__MBAR[0x8948]))
+#define MCF_PSC3_PSCIRSDR                    (*(vuint8 *)(&__MBAR[0x894C]))
+#define MCF_PSC3_PSCIRMDR                    (*(vuint8 *)(&__MBAR[0x8950]))
+#define MCF_PSC3_PSCIRFDR                    (*(vuint8 *)(&__MBAR[0x8954]))
+#define MCF_PSC3_PSCRFCNT                    (*(vuint16*)(&__MBAR[0x8958]))
+#define MCF_PSC3_PSCTFCNT                    (*(vuint16*)(&__MBAR[0x895C]))
+#define MCF_PSC3_PSCRFDR                     (*(vuint32*)(&__MBAR[0x8960]))
+#define MCF_PSC3_PSCRFSR                     (*(vuint16*)(&__MBAR[0x8964]))
+#define MCF_PSC3_PSCRFCR                     (*(vuint32*)(&__MBAR[0x8968]))
+#define MCF_PSC3_PSCRFAR                     (*(vuint16*)(&__MBAR[0x896E]))
+#define MCF_PSC3_PSCRFRP                     (*(vuint16*)(&__MBAR[0x8972]))
+#define MCF_PSC3_PSCRFWP                     (*(vuint16*)(&__MBAR[0x8976]))
+#define MCF_PSC3_PSCRLRFP                    (*(vuint16*)(&__MBAR[0x897A]))
+#define MCF_PSC3_PSCRLWFP                    (*(vuint16*)(&__MBAR[0x897E]))
+#define MCF_PSC3_PSCTFDR                     (*(vuint32*)(&__MBAR[0x8980]))
+#define MCF_PSC3_PSCTFSR                     (*(vuint16*)(&__MBAR[0x8984]))
+#define MCF_PSC3_PSCTFCR                     (*(vuint32*)(&__MBAR[0x8988]))
+#define MCF_PSC3_PSCTFAR                     (*(vuint16*)(&__MBAR[0x898E]))
+#define MCF_PSC3_PSCTFRP                     (*(vuint16*)(&__MBAR[0x8992]))
+#define MCF_PSC3_PSCTFWP                     (*(vuint16*)(&__MBAR[0x8996]))
+#define MCF_PSC3_PSCTLRFP                    (*(vuint16*)(&__MBAR[0x899A]))
+#define MCF_PSC3_PSCTLWFP                    (*(vuint16*)(&__MBAR[0x899E]))
+
+#define MCF_PSC_PSCMR(x)                     (*(vuint8 *)(&__MBAR[0x8600 + ((x)*0x100)]))
+#define MCF_PSC_PSCCSR(x)                    (*(vuint8 *)(&__MBAR[0x8604 + ((x)*0x100)]))
+#define MCF_PSC_PSCSR(x)                     (*(vuint16*)(&__MBAR[0x8604 + ((x)*0x100)]))
+#define MCF_PSC_PSCCR(x)                     (*(vuint8 *)(&__MBAR[0x8608 + ((x)*0x100)]))
+#define MCF_PSC_PSCRB_8BIT(x)                (*(vuint32*)(&__MBAR[0x860C + ((x)*0x100)]))
+#define MCF_PSC_PSCTB_8BIT(x)                (*(vuint32*)(&__MBAR[0x860C + ((x)*0x100)]))
+#define MCF_PSC_PSCRB_16BIT(x)               (*(vuint32*)(&__MBAR[0x860C + ((x)*0x100)]))
+#define MCF_PSC_PSCTB_16BIT(x)               (*(vuint32*)(&__MBAR[0x860C + ((x)*0x100)]))
+#define MCF_PSC_PSCRB_AC97(x)                (*(vuint32*)(&__MBAR[0x860C + ((x)*0x100)]))
+#define MCF_PSC_PSCTB_AC97(x)                (*(vuint32*)(&__MBAR[0x860C + ((x)*0x100)]))
+#define MCF_PSC_PSCIPCR(x)                   (*(vuint8 *)(&__MBAR[0x8610 + ((x)*0x100)]))
+#define MCF_PSC_PSCACR(x)                    (*(vuint8 *)(&__MBAR[0x8610 + ((x)*0x100)]))
+#define MCF_PSC_PSCIMR(x)                    (*(vuint16*)(&__MBAR[0x8614 + ((x)*0x100)]))
+#define MCF_PSC_PSCISR(x)                    (*(vuint16*)(&__MBAR[0x8614 + ((x)*0x100)]))
+#define MCF_PSC_PSCCTUR(x)                   (*(vuint8 *)(&__MBAR[0x8618 + ((x)*0x100)]))
+#define MCF_PSC_PSCCTLR(x)                   (*(vuint8 *)(&__MBAR[0x861C + ((x)*0x100)]))
+#define MCF_PSC_PSCIP(x)                     (*(vuint8 *)(&__MBAR[0x8634 + ((x)*0x100)]))
+#define MCF_PSC_PSCOPSET(x)                  (*(vuint8 *)(&__MBAR[0x8638 + ((x)*0x100)]))
+#define MCF_PSC_PSCOPRESET(x)                (*(vuint8 *)(&__MBAR[0x863C + ((x)*0x100)]))
+#define MCF_PSC_PSCSICR(x)                   (*(vuint8 *)(&__MBAR[0x8640 + ((x)*0x100)]))
+#define MCF_PSC_PSCIRCR1(x)                  (*(vuint8 *)(&__MBAR[0x8644 + ((x)*0x100)]))
+#define MCF_PSC_PSCIRCR2(x)                  (*(vuint8 *)(&__MBAR[0x8648 + ((x)*0x100)]))
+#define MCF_PSC_PSCIRSDR(x)                  (*(vuint8 *)(&__MBAR[0x864C + ((x)*0x100)]))
+#define MCF_PSC_PSCIRMDR(x)                  (*(vuint8 *)(&__MBAR[0x8650 + ((x)*0x100)]))
+#define MCF_PSC_PSCIRFDR(x)                  (*(vuint8 *)(&__MBAR[0x8654 + ((x)*0x100)]))
+#define MCF_PSC_PSCRFCNT(x)                  (*(vuint16*)(&__MBAR[0x8658 + ((x)*0x100)]))
+#define MCF_PSC_PSCTFCNT(x)                  (*(vuint16*)(&__MBAR[0x865C + ((x)*0x100)]))
+#define MCF_PSC_PSCRFDR(x)                   (*(vuint32*)(&__MBAR[0x8660 + ((x)*0x100)]))
+#define MCF_PSC_PSCRFSR(x)                   (*(vuint16*)(&__MBAR[0x8664 + ((x)*0x100)]))
+#define MCF_PSC_PSCRFCR(x)                   (*(vuint32*)(&__MBAR[0x8668 + ((x)*0x100)]))
+#define MCF_PSC_PSCRFAR(x)                   (*(vuint16*)(&__MBAR[0x866E + ((x)*0x100)]))
+#define MCF_PSC_PSCRFRP(x)                   (*(vuint16*)(&__MBAR[0x8672 + ((x)*0x100)]))
+#define MCF_PSC_PSCRFWP(x)                   (*(vuint16*)(&__MBAR[0x8676 + ((x)*0x100)]))
+#define MCF_PSC_PSCRLRFP(x)                  (*(vuint16*)(&__MBAR[0x867A + ((x)*0x100)]))
+#define MCF_PSC_PSCRLWFP(x)                  (*(vuint16*)(&__MBAR[0x867E + ((x)*0x100)]))
+#define MCF_PSC_PSCTFDR(x)                   (*(vuint32*)(&__MBAR[0x8680 + ((x)*0x100)]))
+#define MCF_PSC_PSCTFSR(x)                   (*(vuint16*)(&__MBAR[0x8684 + ((x)*0x100)]))
+#define MCF_PSC_PSCTFCR(x)                   (*(vuint32*)(&__MBAR[0x8688 + ((x)*0x100)]))
+#define MCF_PSC_PSCTFAR(x)                   (*(vuint16*)(&__MBAR[0x868E + ((x)*0x100)]))
+#define MCF_PSC_PSCTFRP(x)                   (*(vuint16*)(&__MBAR[0x8692 + ((x)*0x100)]))
+#define MCF_PSC_PSCTFWP(x)                   (*(vuint16*)(&__MBAR[0x8696 + ((x)*0x100)]))
+#define MCF_PSC_PSCTLRFP(x)                  (*(vuint16*)(&__MBAR[0x869A + ((x)*0x100)]))
+#define MCF_PSC_PSCTLWFP(x)                  (*(vuint16*)(&__MBAR[0x869E + ((x)*0x100)]))
+
+/* Bit definitions and macros for MCF_PSC_PSCMR */
+#define MCF_PSC_PSCMR_SB(x)                  (((x)&0xF)<<0)
+#define MCF_PSC_PSCMR_TXCTS                  (0x10)
+#define MCF_PSC_PSCMR_TXRTS                  (0x20)
+#define MCF_PSC_PSCMR_CM(x)                  (((x)&0x3)<<0x6)
+#define MCF_PSC_PSCMR_CM_NORMAL              (0)
+#define MCF_PSC_PSCMR_CM_ECHO                (0x40)
+#define MCF_PSC_PSCMR_CM_LOCAL_LOOP          (0x80)
+#define MCF_PSC_PSCMR_CM_REMOTE_LOOP         (0xC0)
+#define MCF_PSC_PSCMR_SB_STOP_BITS_1         (0x7)
+#define MCF_PSC_PSCMR_SB_STOP_BITS_15        (0x8)
+#define MCF_PSC_PSCMR_SB_STOP_BITS_2         (0xF)
+#define MCF_PSC_PSCMR_PM_MULTI_ADDR          (0x1C)
+#define MCF_PSC_PSCMR_PM_MULTI_DATA          (0x18)
+#define MCF_PSC_PSCMR_PM_NONE                (0x10)
+#define MCF_PSC_PSCMR_PM_FORCE_HI            (0xC)
+#define MCF_PSC_PSCMR_PM_FORCE_LO            (0x8)
+#define MCF_PSC_PSCMR_PM_ODD                 (0x4)
+#define MCF_PSC_PSCMR_PM_EVEN                (0)
+#define MCF_PSC_PSCMR_BC(x)                  (((x)&0x3)<<0)
+#define MCF_PSC_PSCMR_BC_5                   (0)
+#define MCF_PSC_PSCMR_BC_6                   (0x1)
+#define MCF_PSC_PSCMR_BC_7                   (0x2)
+#define MCF_PSC_PSCMR_BC_8                   (0x3)
+#define MCF_PSC_PSCMR_PT                     (0x4)
+#define MCF_PSC_PSCMR_PM(x)                  (((x)&0x3)<<0x3)
+#define MCF_PSC_PSCMR_ERR                    (0x20)
+#define MCF_PSC_PSCMR_RXIRQ_FU               (0x40)
+#define MCF_PSC_PSCMR_RXRTS                  (0x80)
+
+/* Bit definitions and macros for MCF_PSC_PSCCSR */
+#define MCF_PSC_PSCCSR_TCSEL(x)              (((x)&0xF)<<0)
+#define MCF_PSC_PSCCSR_RCSEL(x)              (((x)&0xF)<<0x4)
+#define MCF_PSC_PSCCSR_TCSEL_SYS_CLK         (0x0D)
+#define MCF_PSC_PSCCSR_TCSEL_CTM16           (0x0E)
+#define MCF_PSC_PSCCSR_TCSEL_CTM             (0x0F)
+#define MCF_PSC_PSCCSR_RCSEL_SYS_CLK         (0xD0)
+#define MCF_PSC_PSCCSR_RCSEL_CTM16           (0xE0)
+#define MCF_PSC_PSCCSR_RCSEL_CTM             (0xF0)
+
+/* Bit definitions and macros for MCF_PSC_PSCSR */
+#define MCF_PSC_PSCSR_ERR                    (0x40)
+#define MCF_PSC_PSCSR_CDE_DEOF               (0x80)
+#define MCF_PSC_PSCSR_RXRDY                  (0x100)
+#define MCF_PSC_PSCSR_FU                     (0x200)
+#define MCF_PSC_PSCSR_TXRDY                  (0x400)
+#define MCF_PSC_PSCSR_TXEMP_URERR            (0x800)
+#define MCF_PSC_PSCSR_OE                     (0x1000)
+#define MCF_PSC_PSCSR_PE_CRCERR              (0x2000)
+#define MCF_PSC_PSCSR_FE_PHYERR              (0x4000)
+#define MCF_PSC_PSCSR_RB_NEOF                (0x8000)
+
+/* Bit definitions and macros for MCF_PSC_PSCCR */
+#define MCF_PSC_PSCCR_RXC(x)                 (((x)&0x3)<<0)
+#define MCF_PSC_PSCCR_RX_ENABLED             (0x1)
+#define MCF_PSC_PSCCR_RX_DISABLED            (0x2)
+#define MCF_PSC_PSCCR_TXC(x)                 (((x)&0x3)<<0x2)
+#define MCF_PSC_PSCCR_TX_ENABLED             (0x4)
+#define MCF_PSC_PSCCR_TX_DISABLED            (0x8)
+#define MCF_PSC_PSCCR_MISC(x)                (((x)&0x7)<<0x4)
+#define MCF_PSC_PSCCR_NONE                   (0)
+#define MCF_PSC_PSCCR_RESET_MR               (0x10)
+#define MCF_PSC_PSCCR_RESET_RX               (0x20)
+#define MCF_PSC_PSCCR_RESET_TX               (0x30)
+#define MCF_PSC_PSCCR_RESET_ERROR            (0x40)
+#define MCF_PSC_PSCCR_RESET_BKCHGINT         (0x50)
+#define MCF_PSC_PSCCR_START_BREAK            (0x60)
+#define MCF_PSC_PSCCR_STOP_BREAK             (0x70)
+
+/* Bit definitions and macros for MCF_PSC_PSCRB_8BIT */
+#define MCF_PSC_PSCRB_8BIT_RB3(x)            (((x)&0xFF)<<0)
+#define MCF_PSC_PSCRB_8BIT_RB2(x)            (((x)&0xFF)<<0x8)
+#define MCF_PSC_PSCRB_8BIT_RB1(x)            (((x)&0xFF)<<0x10)
+#define MCF_PSC_PSCRB_8BIT_RB0(x)            (((x)&0xFF)<<0x18)
+
+/* Bit definitions and macros for MCF_PSC_PSCTB_8BIT */
+#define MCF_PSC_PSCTB_8BIT_TB3(x)            (((x)&0xFF)<<0)
+#define MCF_PSC_PSCTB_8BIT_TB2(x)            (((x)&0xFF)<<0x8)
+#define MCF_PSC_PSCTB_8BIT_TB1(x)            (((x)&0xFF)<<0x10)
+#define MCF_PSC_PSCTB_8BIT_TB0(x)            (((x)&0xFF)<<0x18)
+
+/* Bit definitions and macros for MCF_PSC_PSCRB_16BIT */
+#define MCF_PSC_PSCRB_16BIT_RB1(x)           (((x)&0xFFFF)<<0)
+#define MCF_PSC_PSCRB_16BIT_RB0(x)           (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_PSC_PSCTB_16BIT */
+#define MCF_PSC_PSCTB_16BIT_TB1(x)           (((x)&0xFFFF)<<0)
+#define MCF_PSC_PSCTB_16BIT_TB0(x)           (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_PSC_PSCRB_AC97 */
+#define MCF_PSC_PSCRB_AC97_SOF               (0x800)
+#define MCF_PSC_PSCRB_AC97_RB(x)             (((x)&0xFFFFF)<<0xC)
+
+/* Bit definitions and macros for MCF_PSC_PSCTB_AC97 */
+#define MCF_PSC_PSCTB_AC97_TB(x)             (((x)&0xFFFFF)<<0xC)
+
+/* Bit definitions and macros for MCF_PSC_PSCIPCR */
+#define MCF_PSC_PSCIPCR_RESERVED             (0xC)
+#define MCF_PSC_PSCIPCR_CTS                  (0xD)
+#define MCF_PSC_PSCIPCR_D_CTS                (0x1C)
+#define MCF_PSC_PSCIPCR_SYNC                 (0x8C)
+
+/* Bit definitions and macros for MCF_PSC_PSCACR */
+#define MCF_PSC_PSCACR_IEC0                  (0x1)
+
+/* Bit definitions and macros for MCF_PSC_PSCIMR */
+#define MCF_PSC_PSCIMR_ERR                   (0x40)
+#define MCF_PSC_PSCIMR_DEOF                  (0x80)
+#define MCF_PSC_PSCIMR_TXRDY                 (0x100)
+#define MCF_PSC_PSCIMR_RXRDY_FU              (0x200)
+#define MCF_PSC_PSCIMR_DB                    (0x400)
+#define MCF_PSC_PSCIMR_IPC                   (0x8000)
+
+/* Bit definitions and macros for MCF_PSC_PSCISR */
+#define MCF_PSC_PSCISR_ERR                   (0x40)
+#define MCF_PSC_PSCISR_DEOF                  (0x80)
+#define MCF_PSC_PSCISR_TXRDY                 (0x100)
+#define MCF_PSC_PSCISR_RXRDY_FU              (0x200)
+#define MCF_PSC_PSCISR_DB                    (0x400)
+#define MCF_PSC_PSCISR_IPC                   (0x8000)
+
+/* Bit definitions and macros for MCF_PSC_PSCCTUR */
+#define MCF_PSC_PSCCTUR_CT(x)                (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCCTLR */
+#define MCF_PSC_PSCCTLR_CT(x)                (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCIP */
+#define MCF_PSC_PSCIP_CTS                    (0x1)
+#define MCF_PSC_PSCIP_TGL                    (0x40)
+#define MCF_PSC_PSCIP_LPWR_B                 (0x80)
+
+/* Bit definitions and macros for MCF_PSC_PSCOPSET */
+#define MCF_PSC_PSCOPSET_RTS                 (0x1)
+
+/* Bit definitions and macros for MCF_PSC_PSCOPRESET */
+#define MCF_PSC_PSCOPRESET_RTS               (0x1)
+
+/* Bit definitions and macros for MCF_PSC_PSCSICR */
+#define MCF_PSC_PSCSICR_SIM(x)               (((x)&0x7)<<0)
+#define MCF_PSC_PSCSICR_SIM_UART             (0)
+#define MCF_PSC_PSCSICR_SIM_MODEM8           (0x1)
+#define MCF_PSC_PSCSICR_SIM_MODEM16          (0x2)
+#define MCF_PSC_PSCSICR_SIM_AC97             (0x3)
+#define MCF_PSC_PSCSICR_SIM_SIR              (0x4)
+#define MCF_PSC_PSCSICR_SIM_MIR              (0x5)
+#define MCF_PSC_PSCSICR_SIM_FIR              (0x6)
+#define MCF_PSC_PSCSICR_SHDIR                (0x10)
+#define MCF_PSC_PSCSICR_DTS1                 (0x20)
+#define MCF_PSC_PSCSICR_AWR                  (0x40)
+#define MCF_PSC_PSCSICR_ACRB                 (0x80)
+
+/* Bit definitions and macros for MCF_PSC_PSCIRCR1 */
+#define MCF_PSC_PSCIRCR1_SPUL                (0x1)
+#define MCF_PSC_PSCIRCR1_SIPEN               (0x2)
+#define MCF_PSC_PSCIRCR1_FD                  (0x4)
+
+/* Bit definitions and macros for MCF_PSC_PSCIRCR2 */
+#define MCF_PSC_PSCIRCR2_NXTEOF              (0x1)
+#define MCF_PSC_PSCIRCR2_ABORT               (0x2)
+#define MCF_PSC_PSCIRCR2_SIPREQ              (0x4)
+
+/* Bit definitions and macros for MCF_PSC_PSCIRSDR */
+#define MCF_PSC_PSCIRSDR_IRSTIM(x)           (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCIRMDR */
+#define MCF_PSC_PSCIRMDR_M_FDIV(x)           (((x)&0x7F)<<0)
+#define MCF_PSC_PSCIRMDR_FREQ                (0x80)
+
+/* Bit definitions and macros for MCF_PSC_PSCIRFDR */
+#define MCF_PSC_PSCIRFDR_F_FDIV(x)           (((x)&0xF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCRFCNT */
+#define MCF_PSC_PSCRFCNT_CNT(x)              (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCTFCNT */
+#define MCF_PSC_PSCTFCNT_CNT(x)              (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCRFDR */
+#define MCF_PSC_PSCRFDR_DATA(x)              (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCRFSR */
+#define MCF_PSC_PSCRFSR_EMT                  (0x1)
+#define MCF_PSC_PSCRFSR_ALARM                (0x2)
+#define MCF_PSC_PSCRFSR_FU                   (0x4)
+#define MCF_PSC_PSCRFSR_FRMRDY               (0x8)
+#define MCF_PSC_PSCRFSR_OF                   (0x10)
+#define MCF_PSC_PSCRFSR_UF                   (0x20)
+#define MCF_PSC_PSCRFSR_RXW                  (0x40)
+#define MCF_PSC_PSCRFSR_FAE                  (0x80)
+#define MCF_PSC_PSCRFSR_FRM(x)               (((x)&0xF)<<0x8)
+#define MCF_PSC_PSCRFSR_FRM_BYTE0            (0x800)
+#define MCF_PSC_PSCRFSR_FRM_BYTE1            (0x400)
+#define MCF_PSC_PSCRFSR_FRM_BYTE2            (0x200)
+#define MCF_PSC_PSCRFSR_FRM_BYTE3            (0x100)
+#define MCF_PSC_PSCRFSR_TAG(x)               (((x)&0x3)<<0xC)
+#define MCF_PSC_PSCRFSR_TXW                  (0x4000)
+#define MCF_PSC_PSCRFSR_IP                   (0x8000)
+
+/* Bit definitions and macros for MCF_PSC_PSCRFCR */
+#define MCF_PSC_PSCRFCR_CNTR(x)              (((x)&0xFFFF)<<0)
+#define MCF_PSC_PSCRFCR_TXW_MSK              (0x40000)
+#define MCF_PSC_PSCRFCR_OF_MSK               (0x80000)
+#define MCF_PSC_PSCRFCR_UF_MSK               (0x100000)
+#define MCF_PSC_PSCRFCR_RXW_MSK              (0x200000)
+#define MCF_PSC_PSCRFCR_FAE_MSK              (0x400000)
+#define MCF_PSC_PSCRFCR_IP_MSK               (0x800000)
+#define MCF_PSC_PSCRFCR_GR(x)                (((x)&0x7)<<0x18)
+#define MCF_PSC_PSCRFCR_FRMEN                (0x8000000)
+#define MCF_PSC_PSCRFCR_TIMER                (0x10000000)
+
+/* Bit definitions and macros for MCF_PSC_PSCRFAR */
+#define MCF_PSC_PSCRFAR_ALARM(x)             (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCRFRP */
+#define MCF_PSC_PSCRFRP_READ(x)              (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCRFWP */
+#define MCF_PSC_PSCRFWP_WRITE(x)             (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCRLRFP */
+#define MCF_PSC_PSCRLRFP_LRFP(x)             (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCRLWFP */
+#define MCF_PSC_PSCRLWFP_LWFP(x)             (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCTFDR */
+#define MCF_PSC_PSCTFDR_DATA(x)              (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCTFSR */
+#define MCF_PSC_PSCTFSR_EMT                  (0x1)
+#define MCF_PSC_PSCTFSR_ALARM                (0x2)
+#define MCF_PSC_PSCTFSR_FU                   (0x4)
+#define MCF_PSC_PSCTFSR_FRMRDY               (0x8)
+#define MCF_PSC_PSCTFSR_OF                   (0x10)
+#define MCF_PSC_PSCTFSR_UF                   (0x20)
+#define MCF_PSC_PSCTFSR_RXW                  (0x40)
+#define MCF_PSC_PSCTFSR_FAE                  (0x80)
+#define MCF_PSC_PSCTFSR_FRM(x)               (((x)&0xF)<<0x8)
+#define MCF_PSC_PSCTFSR_FRM_BYTE0            (0x800)
+#define MCF_PSC_PSCTFSR_FRM_BYTE1            (0x400)
+#define MCF_PSC_PSCTFSR_FRM_BYTE2            (0x200)
+#define MCF_PSC_PSCTFSR_FRM_BYTE3            (0x100)
+#define MCF_PSC_PSCTFSR_TAG(x)               (((x)&0x3)<<0xC)
+#define MCF_PSC_PSCTFSR_TXW                  (0x4000)
+#define MCF_PSC_PSCTFSR_IP                   (0x8000)
+
+/* Bit definitions and macros for MCF_PSC_PSCTFCR */
+#define MCF_PSC_PSCTFCR_CNTR(x)              (((x)&0xFFFF)<<0)
+#define MCF_PSC_PSCTFCR_TXW_MSK              (0x40000)
+#define MCF_PSC_PSCTFCR_OF_MSK               (0x80000)
+#define MCF_PSC_PSCTFCR_UF_MSK               (0x100000)
+#define MCF_PSC_PSCTFCR_RXW_MSK              (0x200000)
+#define MCF_PSC_PSCTFCR_FAE_MSK              (0x400000)
+#define MCF_PSC_PSCTFCR_IP_MSK               (0x800000)
+#define MCF_PSC_PSCTFCR_GR(x)                (((x)&0x7)<<0x18)
+#define MCF_PSC_PSCTFCR_FRMEN                (0x8000000)
+#define MCF_PSC_PSCTFCR_TIMER                (0x10000000)
+#define MCF_PSC_PSCTFCR_WFR                  (0x20000000)
+
+/* Bit definitions and macros for MCF_PSC_PSCTFAR */
+#define MCF_PSC_PSCTFAR_ALARM(x)             (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCTFRP */
+#define MCF_PSC_PSCTFRP_READ(x)              (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCTFWP */
+#define MCF_PSC_PSCTFWP_WRITE(x)             (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCTLRFP */
+#define MCF_PSC_PSCTLRFP_LRFP(x)             (((x)&0x1FF)<<0)
+
+/* Bit definitions and macros for MCF_PSC_PSCTLWFP */
+#define MCF_PSC_PSCTLWFP_LWFP(x)             (((x)&0x1FF)<<0)
+
+
+#endif /* __MCF5475_PSC_H__ */
diff --git a/firebeeV1/headers/MCF5475_SDRAMC.h b/firebeeV1/headers/MCF5475_SDRAMC.h
new file mode 100644
index 0000000..843ac12
--- /dev/null
+++ b/firebeeV1/headers/MCF5475_SDRAMC.h
@@ -0,0 +1,106 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_SDRAMC_H__
+#define __MCF5475_SDRAMC_H__
+
+
+/*********************************************************************
+*
+* Synchronous DRAM Controller (SDRAMC)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_SDRAMC_SDRAMDS                   (*(vuint32*)(&__MBAR[0x4]))
+#define MCF_SDRAMC_CS0CFG                    (*(vuint32*)(&__MBAR[0x20]))
+#define MCF_SDRAMC_CS1CFG                    (*(vuint32*)(&__MBAR[0x24]))
+#define MCF_SDRAMC_CS2CFG                    (*(vuint32*)(&__MBAR[0x28]))
+#define MCF_SDRAMC_CS3CFG                    (*(vuint32*)(&__MBAR[0x2C]))
+#define MCF_SDRAMC_SDMR                      (*(vuint32*)(&__MBAR[0x100]))
+#define MCF_SDRAMC_SDCR                      (*(vuint32*)(&__MBAR[0x104]))
+#define MCF_SDRAMC_SDCFG1                    (*(vuint32*)(&__MBAR[0x108]))
+#define MCF_SDRAMC_SDCFG2                    (*(vuint32*)(&__MBAR[0x10C]))
+#define MCF_SDRAMC_CSCFG(x)                  (*(vuint32*)(&__MBAR[0x20 + ((x)*0x4)]))
+
+
+/* Bit definitions and macros for MCF_SDRAMC_SDRAMDS */
+#define MCF_SDRAMC_SDRAMDS_SB_D(x)           (((x)&0x3)<<0)
+#define MCF_SDRAMC_SDRAMDS_SB_S(x)           (((x)&0x3)<<0x2)
+#define MCF_SDRAMC_SDRAMDS_SB_A(x)           (((x)&0x3)<<0x4)
+#define MCF_SDRAMC_SDRAMDS_SB_C(x)           (((x)&0x3)<<0x6)
+#define MCF_SDRAMC_SDRAMDS_SB_E(x)           (((x)&0x3)<<0x8)
+#define MCF_SDRAMC_SDRAMDS_DRIVE_24MA        (0)
+#define MCF_SDRAMC_SDRAMDS_DRIVE_16MA        (0x1)
+#define MCF_SDRAMC_SDRAMDS_DRIVE_8MA         (0x2)
+#define MCF_SDRAMC_SDRAMDS_DRIVE_NONE        (0x3)
+
+/* Bit definitions and macros for MCF_SDRAMC_CSCFG */
+#define MCF_SDRAMC_CSCFG_CSSZ(x)             (((x)&0x1F)<<0)
+#define MCF_SDRAMC_CSCFG_CSSZ_DISABLED       (0)
+#define MCF_SDRAMC_CSCFG_CSSZ_1MBYTE         (0x13)
+#define MCF_SDRAMC_CSCFG_CSSZ_2MBYTE         (0x14)
+#define MCF_SDRAMC_CSCFG_CSSZ_4MBYTE         (0x15)
+#define MCF_SDRAMC_CSCFG_CSSZ_8MBYTE         (0x16)
+#define MCF_SDRAMC_CSCFG_CSSZ_16MBYTE        (0x17)
+#define MCF_SDRAMC_CSCFG_CSSZ_32MBYTE        (0x18)
+#define MCF_SDRAMC_CSCFG_CSSZ_64MBYTE        (0x19)
+#define MCF_SDRAMC_CSCFG_CSSZ_128MBYTE       (0x1A)
+#define MCF_SDRAMC_CSCFG_CSSZ_256MBYTE       (0x1B)
+#define MCF_SDRAMC_CSCFG_CSSZ_512MBYTE       (0x1C)
+#define MCF_SDRAMC_CSCFG_CSSZ_1GBYTE         (0x1D)
+#define MCF_SDRAMC_CSCFG_CSSZ_2GBYTE         (0x1E)
+#define MCF_SDRAMC_CSCFG_CSSZ_4GBYTE         (0x1F)
+#define MCF_SDRAMC_CSCFG_CSBA(x)             (((x)&0xFFF)<<0x14)
+#define MCF_SDRAMC_CSCFG_BA(x)               ((x)&0xFFF00000)
+
+/* Bit definitions and macros for MCF_SDRAMC_SDMR */
+#define MCF_SDRAMC_SDMR_CMD                  (0x10000)
+#define MCF_SDRAMC_SDMR_AD(x)                (((x)&0xFFF)<<0x12)
+#define MCF_SDRAMC_SDMR_BNKAD(x)             (((x)&0x3)<<0x1E)
+#define MCF_SDRAMC_SDMR_BK_LMR               (0)
+#define MCF_SDRAMC_SDMR_BK_LEMR              (0x40000000)
+
+/* Bit definitions and macros for MCF_SDRAMC_SDCR */
+#define MCF_SDRAMC_SDCR_IPALL                (0x2)
+#define MCF_SDRAMC_SDCR_IREF                 (0x4)
+#define MCF_SDRAMC_SDCR_BUFF                 (0x10)
+#define MCF_SDRAMC_SDCR_DQS_OE(x)            (((x)&0xF)<<0x8)
+#define MCF_SDRAMC_SDCR_RCNT(x)              (((x)&0x3F)<<0x10)
+#define MCF_SDRAMC_SDCR_DRIVE                (0x400000)
+#define MCF_SDRAMC_SDCR_AP                   (0x800000)
+#define MCF_SDRAMC_SDCR_MUX(x)               (((x)&0x3)<<0x18)
+#define MCF_SDRAMC_SDCR_REF                  (0x10000000)
+#define MCF_SDRAMC_SDCR_DDR                  (0x20000000)
+#define MCF_SDRAMC_SDCR_CKE                  (0x40000000)
+#define MCF_SDRAMC_SDCR_MODE_EN              (0x80000000)
+
+/* Bit definitions and macros for MCF_SDRAMC_SDCFG1 */
+#define MCF_SDRAMC_SDCFG1_WTLAT(x)           (((x)&0x7)<<0x4)
+#define MCF_SDRAMC_SDCFG1_REF2ACT(x)         (((x)&0xF)<<0x8)
+#define MCF_SDRAMC_SDCFG1_PRE2ACT(x)         (((x)&0x7)<<0xC)
+#define MCF_SDRAMC_SDCFG1_ACT2RW(x)          (((x)&0x7)<<0x10)
+#define MCF_SDRAMC_SDCFG1_RDLAT(x)           (((x)&0xF)<<0x14)
+#define MCF_SDRAMC_SDCFG1_SWT2RD(x)          (((x)&0x7)<<0x18)
+#define MCF_SDRAMC_SDCFG1_SRD2RW(x)          (((x)&0xF)<<0x1C)
+
+/* Bit definitions and macros for MCF_SDRAMC_SDCFG2 */
+#define MCF_SDRAMC_SDCFG2_BL(x)              (((x)&0xF)<<0x10)
+#define MCF_SDRAMC_SDCFG2_BRD2WT(x)          (((x)&0xF)<<0x14)
+#define MCF_SDRAMC_SDCFG2_BWT2RW(x)          (((x)&0xF)<<0x18)
+#define MCF_SDRAMC_SDCFG2_BRD2PRE(x)         (((x)&0xF)<<0x1C)
+
+
+#endif /* __MCF5475_SDRAMC_H__ */
diff --git a/firebeeV1/headers/MCF5475_SEC.h b/firebeeV1/headers/MCF5475_SEC.h
new file mode 100644
index 0000000..ce02c30
--- /dev/null
+++ b/firebeeV1/headers/MCF5475_SEC.h
@@ -0,0 +1,398 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_SEC_H__
+#define __MCF5475_SEC_H__
+
+
+/*********************************************************************
+*
+* Integrated Security Engine (SEC)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_SEC_EUACRH                       (*(vuint32*)(&__MBAR[0x21000]))
+#define MCF_SEC_EUACRL                       (*(vuint32*)(&__MBAR[0x21004]))
+#define MCF_SEC_SIMRH                        (*(vuint32*)(&__MBAR[0x21008]))
+#define MCF_SEC_SIMRL                        (*(vuint32*)(&__MBAR[0x2100C]))
+#define MCF_SEC_SISRH                        (*(vuint32*)(&__MBAR[0x21010]))
+#define MCF_SEC_SISRL                        (*(vuint32*)(&__MBAR[0x21014]))
+#define MCF_SEC_SICRH                        (*(vuint32*)(&__MBAR[0x21018]))
+#define MCF_SEC_SICRL                        (*(vuint32*)(&__MBAR[0x2101C]))
+#define MCF_SEC_SIDR                         (*(vuint32*)(&__MBAR[0x21020]))
+#define MCF_SEC_EUASRH                       (*(vuint32*)(&__MBAR[0x21028]))
+#define MCF_SEC_EUASRL                       (*(vuint32*)(&__MBAR[0x2102C]))
+#define MCF_SEC_SMCR                         (*(vuint32*)(&__MBAR[0x21030]))
+#define MCF_SEC_MEAR                         (*(vuint32*)(&__MBAR[0x21038]))
+#define MCF_SEC_CCCR0                        (*(vuint32*)(&__MBAR[0x2200C]))
+#define MCF_SEC_CCPSRH0                      (*(vuint32*)(&__MBAR[0x22010]))
+#define MCF_SEC_CCPSRL0                      (*(vuint32*)(&__MBAR[0x22014]))
+#define MCF_SEC_CDPR0                        (*(vuint32*)(&__MBAR[0x22044]))
+#define MCF_SEC_FR0                          (*(vuint32*)(&__MBAR[0x2204C]))
+#define MCF_SEC_CCCR1                        (*(vuint32*)(&__MBAR[0x2300C]))
+#define MCF_SEC_CCPSRH1                      (*(vuint32*)(&__MBAR[0x23010]))
+#define MCF_SEC_CCPSRL1                      (*(vuint32*)(&__MBAR[0x23014]))
+#define MCF_SEC_CDPR1                        (*(vuint32*)(&__MBAR[0x23044]))
+#define MCF_SEC_FR1                          (*(vuint32*)(&__MBAR[0x2304C]))
+#define MCF_SEC_AFRCR                        (*(vuint32*)(&__MBAR[0x28018]))
+#define MCF_SEC_AFSR                         (*(vuint32*)(&__MBAR[0x28028]))
+#define MCF_SEC_AFISR                        (*(vuint32*)(&__MBAR[0x28030]))
+#define MCF_SEC_AFIMR                        (*(vuint32*)(&__MBAR[0x28038]))
+#define MCF_SEC_DRCR                         (*(vuint32*)(&__MBAR[0x2A018]))
+#define MCF_SEC_DSR                          (*(vuint32*)(&__MBAR[0x2A028]))
+#define MCF_SEC_DISR                         (*(vuint32*)(&__MBAR[0x2A030]))
+#define MCF_SEC_DIMR                         (*(vuint32*)(&__MBAR[0x2A038]))
+#define MCF_SEC_MDRCR                        (*(vuint32*)(&__MBAR[0x2C018]))
+#define MCF_SEC_MDSR                         (*(vuint32*)(&__MBAR[0x2C028]))
+#define MCF_SEC_MDISR                        (*(vuint32*)(&__MBAR[0x2C030]))
+#define MCF_SEC_MDIMR                        (*(vuint32*)(&__MBAR[0x2C038]))
+#define MCF_SEC_RNGRCR                       (*(vuint32*)(&__MBAR[0x2E018]))
+#define MCF_SEC_RNGSR                        (*(vuint32*)(&__MBAR[0x2E028]))
+#define MCF_SEC_RNGISR                       (*(vuint32*)(&__MBAR[0x2E030]))
+#define MCF_SEC_RNGIMR                       (*(vuint32*)(&__MBAR[0x2E038]))
+#define MCF_SEC_AESRCR                       (*(vuint32*)(&__MBAR[0x32018]))
+#define MCF_SEC_AESSR                        (*(vuint32*)(&__MBAR[0x32028]))
+#define MCF_SEC_AESISR                       (*(vuint32*)(&__MBAR[0x32030]))
+#define MCF_SEC_AESIMR                       (*(vuint32*)(&__MBAR[0x32038]))
+#define MCF_SEC_CCCRn(x)                     (*(vuint32*)(&__MBAR[0x2200C + ((x)*0x1000)]))
+#define MCF_SEC_CCPSRHn(x)                   (*(vuint32*)(&__MBAR[0x22010 + ((x)*0x1000)]))
+#define MCF_SEC_CCPSRLn(x)                   (*(vuint32*)(&__MBAR[0x22014 + ((x)*0x1000)]))
+#define MCF_SEC_CDPRn(x)                     (*(vuint32*)(&__MBAR[0x22044 + ((x)*0x1000)]))
+#define MCF_SEC_FRn(x)                       (*(vuint32*)(&__MBAR[0x2204C + ((x)*0x1000)]))
+
+
+/* Bit definitions and macros for MCF_SEC_EUACRH */
+#define MCF_SEC_EUACRH_AFEU(x)               (((x)&0xF)<<0)
+#define MCF_SEC_EUACRH_AFFEU_NOASSIGN        (0)
+#define MCF_SEC_EUACRH_AFFEU_CHA0            (0x1)
+#define MCF_SEC_EUACRH_AFFEU_CHA1            (0x2)
+#define MCF_SEC_EUACRH_MDEU(x)               (((x)&0xF)<<0x8)
+#define MCF_SEC_EUACRH_MDEU_NOASSIGN         (0)
+#define MCF_SEC_EUACRH_MDEU_CHA0             (0x100)
+#define MCF_SEC_EUACRH_MDEU_CHA1             (0x200)
+#define MCF_SEC_EUACRH_RNG(x)                (((x)&0xF)<<0x18)
+#define MCF_SEC_EUACRH_RNG_NOASSIGN          (0)
+#define MCF_SEC_EUACRH_RNG_CHA0              (0x1000000)
+#define MCF_SEC_EUACRH_RNG_CHA1              (0x2000000)
+
+/* Bit definitions and macros for MCF_SEC_EUACRL */
+#define MCF_SEC_EUACRL_AESU(x)               (((x)&0xF)<<0x10)
+#define MCF_SEC_EUACRL_AESU_NOASSIGN         (0)
+#define MCF_SEC_EUACRL_AESU_CHA0             (0x10000)
+#define MCF_SEC_EUACRL_AESU_CHA1             (0x20000)
+#define MCF_SEC_EUACRL_DEU(x)                (((x)&0xF)<<0x18)
+
+/* Bit definitions and macros for MCF_SEC_SIMRH */
+#define MCF_SEC_SIMRH_AERR                   (0x8000000)
+#define MCF_SEC_SIMRH_CHA_0_DN               (0x10000000)
+#define MCF_SEC_SIMRH_CHA_0_ERR              (0x20000000)
+#define MCF_SEC_SIMRH_CHA_1_DN               (0x40000000)
+#define MCF_SEC_SIMRH_CHA_1_ERR              (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_SIMRL */
+#define MCF_SEC_SIMRL_TEA                    (0x40)
+#define MCF_SEC_SIMRL_DEU_DN                 (0x100)
+#define MCF_SEC_SIMRL_DEU_ERR                (0x200)
+#define MCF_SEC_SIMRL_AESU_DN                (0x1000)
+#define MCF_SEC_SIMRL_AESU_ERR               (0x2000)
+#define MCF_SEC_SIMRL_MDEU_DN                (0x10000)
+#define MCF_SEC_SIMRL_MDEU_ERR               (0x20000)
+#define MCF_SEC_SIMRL_AFEU_DN                (0x100000)
+#define MCF_SEC_SIMRL_AFEU_ERR               (0x200000)
+#define MCF_SEC_SIMRL_RNG_DN                 (0x1000000)
+#define MCF_SEC_SIMRL_RNG_ERR                (0x2000000)
+
+/* Bit definitions and macros for MCF_SEC_SISRH */
+#define MCF_SEC_SISRH_AERR                   (0x8000000)
+#define MCF_SEC_SISRH_CHA_0_DN               (0x10000000)
+#define MCF_SEC_SISRH_CHA_0_ERR              (0x20000000)
+#define MCF_SEC_SISRH_CHA_1_DN               (0x40000000)
+#define MCF_SEC_SISRH_CHA_1_ERR              (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_SISRL */
+#define MCF_SEC_SISRL_TEA                    (0x40)
+#define MCF_SEC_SISRL_DEU_DN                 (0x100)
+#define MCF_SEC_SISRL_DEU_ERR                (0x200)
+#define MCF_SEC_SISRL_AESU_DN                (0x1000)
+#define MCF_SEC_SISRL_AESU_ERR               (0x2000)
+#define MCF_SEC_SISRL_MDEU_DN                (0x10000)
+#define MCF_SEC_SISRL_MDEU_ERR               (0x20000)
+#define MCF_SEC_SISRL_AFEU_DN                (0x100000)
+#define MCF_SEC_SISRL_AFEU_ERR               (0x200000)
+#define MCF_SEC_SISRL_RNG_DN                 (0x1000000)
+#define MCF_SEC_SISRL_RNG_ERR                (0x2000000)
+
+/* Bit definitions and macros for MCF_SEC_SICRH */
+#define MCF_SEC_SICRH_AERR                   (0x8000000)
+#define MCF_SEC_SICRH_CHA_0_DN               (0x10000000)
+#define MCF_SEC_SICRH_CHA_0_ERR              (0x20000000)
+#define MCF_SEC_SICRH_CHA_1_DN               (0x40000000)
+#define MCF_SEC_SICRH_CHA_1_ERR              (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_SICRL */
+#define MCF_SEC_SICRL_TEA                    (0x40)
+#define MCF_SEC_SICRL_DEU_DN                 (0x100)
+#define MCF_SEC_SICRL_DEU_ERR                (0x200)
+#define MCF_SEC_SICRL_AESU_DN                (0x1000)
+#define MCF_SEC_SICRL_AESU_ERR               (0x2000)
+#define MCF_SEC_SICRL_MDEU_DN                (0x10000)
+#define MCF_SEC_SICRL_MDEU_ERR               (0x20000)
+#define MCF_SEC_SICRL_AFEU_DN                (0x100000)
+#define MCF_SEC_SICRL_AFEU_ERR               (0x200000)
+#define MCF_SEC_SICRL_RNG_DN                 (0x1000000)
+#define MCF_SEC_SICRL_RNG_ERR                (0x2000000)
+
+/* Bit definitions and macros for MCF_SEC_SIDR */
+#define MCF_SEC_SIDR_VERSION(x)              (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_SEC_EUASRH */
+#define MCF_SEC_EUASRH_AFEU(x)               (((x)&0xF)<<0)
+#define MCF_SEC_EUASRH_MDEU(x)               (((x)&0xF)<<0x8)
+#define MCF_SEC_EUASRH_RNG(x)                (((x)&0xF)<<0x18)
+
+/* Bit definitions and macros for MCF_SEC_EUASRL */
+#define MCF_SEC_EUASRL_AESU(x)               (((x)&0xF)<<0x10)
+#define MCF_SEC_EUASRL_DEU(x)                (((x)&0xF)<<0x18)
+
+/* Bit definitions and macros for MCF_SEC_SMCR */
+#define MCF_SEC_SMCR_CURR_CHAN(x)            (((x)&0xF)<<0x4)
+#define MCF_SEC_SMCR_CURR_CHAN_1             (0x10)
+#define MCF_SEC_SMCR_CURR_CHAN_2             (0x20)
+#define MCF_SEC_SMCR_SWR                     (0x1000000)
+
+/* Bit definitions and macros for MCF_SEC_MEAR */
+#define MCF_SEC_MEAR_ADDRESS(x)              (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_SEC_CCCRn */
+#define MCF_SEC_CCCRn_RST                    (0x1)
+#define MCF_SEC_CCCRn_CDIE                   (0x2)
+#define MCF_SEC_CCCRn_NT                     (0x4)
+#define MCF_SEC_CCCRn_NE                     (0x8)
+#define MCF_SEC_CCCRn_WE                     (0x10)
+#define MCF_SEC_CCCRn_BURST_SIZE(x)          (((x)&0x7)<<0x8)
+#define MCF_SEC_CCCRn_BURST_SIZE_2           (0)
+#define MCF_SEC_CCCRn_BURST_SIZE_8           (0x100)
+#define MCF_SEC_CCCRn_BURST_SIZE_16          (0x200)
+#define MCF_SEC_CCCRn_BURST_SIZE_24          (0x300)
+#define MCF_SEC_CCCRn_BURST_SIZE_32          (0x400)
+#define MCF_SEC_CCCRn_BURST_SIZE_40          (0x500)
+#define MCF_SEC_CCCRn_BURST_SIZE_48          (0x600)
+#define MCF_SEC_CCCRn_BURST_SIZE_56          (0x700)
+
+/* Bit definitions and macros for MCF_SEC_CCPSRHn */
+#define MCF_SEC_CCPSRHn_STATE(x)             (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_SEC_CCPSRLn */
+#define MCF_SEC_CCPSRLn_PAIR_PTR(x)          (((x)&0xFF)<<0)
+#define MCF_SEC_CCPSRLn_EUERR                (0x100)
+#define MCF_SEC_CCPSRLn_SERR                 (0x200)
+#define MCF_SEC_CCPSRLn_DERR                 (0x400)
+#define MCF_SEC_CCPSRLn_PERR                 (0x1000)
+#define MCF_SEC_CCPSRLn_TEA                  (0x2000)
+#define MCF_SEC_CCPSRLn_SD                   (0x10000)
+#define MCF_SEC_CCPSRLn_PD                   (0x20000)
+#define MCF_SEC_CCPSRLn_SRD                  (0x40000)
+#define MCF_SEC_CCPSRLn_PRD                  (0x80000)
+#define MCF_SEC_CCPSRLn_SG                   (0x100000)
+#define MCF_SEC_CCPSRLn_PG                   (0x200000)
+#define MCF_SEC_CCPSRLn_SR                   (0x400000)
+#define MCF_SEC_CCPSRLn_PR                   (0x800000)
+#define MCF_SEC_CCPSRLn_MO                   (0x1000000)
+#define MCF_SEC_CCPSRLn_MI                   (0x2000000)
+#define MCF_SEC_CCPSRLn_STAT                 (0x4000000)
+
+/* Bit definitions and macros for MCF_SEC_CDPRn */
+#define MCF_SEC_CDPRn_CDP(x)                 (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_SEC_FRn */
+#define MCF_SEC_FRn_FETCH_ADDR(x)            (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_SEC_AFRCR */
+#define MCF_SEC_AFRCR_SR                     (0x1000000)
+#define MCF_SEC_AFRCR_MI                     (0x2000000)
+#define MCF_SEC_AFRCR_RI                     (0x4000000)
+
+/* Bit definitions and macros for MCF_SEC_AFSR */
+#define MCF_SEC_AFSR_RD                      (0x1000000)
+#define MCF_SEC_AFSR_ID                      (0x2000000)
+#define MCF_SEC_AFSR_IE                      (0x4000000)
+#define MCF_SEC_AFSR_OFR                     (0x8000000)
+#define MCF_SEC_AFSR_IFW                     (0x10000000)
+#define MCF_SEC_AFSR_HALT                    (0x20000000)
+
+/* Bit definitions and macros for MCF_SEC_AFISR */
+#define MCF_SEC_AFISR_DSE                    (0x10000)
+#define MCF_SEC_AFISR_KSE                    (0x20000)
+#define MCF_SEC_AFISR_CE                     (0x40000)
+#define MCF_SEC_AFISR_ERE                    (0x80000)
+#define MCF_SEC_AFISR_IE                     (0x100000)
+#define MCF_SEC_AFISR_OFU                    (0x2000000)
+#define MCF_SEC_AFISR_IFO                    (0x4000000)
+#define MCF_SEC_AFISR_IFE                    (0x10000000)
+#define MCF_SEC_AFISR_OFE                    (0x20000000)
+#define MCF_SEC_AFISR_AE                     (0x40000000)
+#define MCF_SEC_AFISR_ME                     (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_AFIMR */
+#define MCF_SEC_AFIMR_DSE                    (0x10000)
+#define MCF_SEC_AFIMR_KSE                    (0x20000)
+#define MCF_SEC_AFIMR_CE                     (0x40000)
+#define MCF_SEC_AFIMR_ERE                    (0x80000)
+#define MCF_SEC_AFIMR_IE                     (0x100000)
+#define MCF_SEC_AFIMR_OFU                    (0x2000000)
+#define MCF_SEC_AFIMR_IFO                    (0x4000000)
+#define MCF_SEC_AFIMR_IFE                    (0x10000000)
+#define MCF_SEC_AFIMR_OFE                    (0x20000000)
+#define MCF_SEC_AFIMR_AE                     (0x40000000)
+#define MCF_SEC_AFIMR_ME                     (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_DRCR */
+#define MCF_SEC_DRCR_SR                      (0x1000000)
+#define MCF_SEC_DRCR_MI                      (0x2000000)
+#define MCF_SEC_DRCR_RI                      (0x4000000)
+
+/* Bit definitions and macros for MCF_SEC_DSR */
+#define MCF_SEC_DSR_RD                       (0x1000000)
+#define MCF_SEC_DSR_ID                       (0x2000000)
+#define MCF_SEC_DSR_IE                       (0x4000000)
+#define MCF_SEC_DSR_OFR                      (0x8000000)
+#define MCF_SEC_DSR_IFW                      (0x10000000)
+#define MCF_SEC_DSR_HALT                     (0x20000000)
+
+/* Bit definitions and macros for MCF_SEC_DISR */
+#define MCF_SEC_DISR_DSE                     (0x10000)
+#define MCF_SEC_DISR_KSE                     (0x20000)
+#define MCF_SEC_DISR_CE                      (0x40000)
+#define MCF_SEC_DISR_ERE                     (0x80000)
+#define MCF_SEC_DISR_IE                      (0x100000)
+#define MCF_SEC_DISR_KPE                     (0x200000)
+#define MCF_SEC_DISR_OFU                     (0x2000000)
+#define MCF_SEC_DISR_IFO                     (0x4000000)
+#define MCF_SEC_DISR_IFE                     (0x10000000)
+#define MCF_SEC_DISR_OFE                     (0x20000000)
+#define MCF_SEC_DISR_AE                      (0x40000000)
+#define MCF_SEC_DISR_ME                      (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_DIMR */
+#define MCF_SEC_DIMR_DSE                     (0x10000)
+#define MCF_SEC_DIMR_KSE                     (0x20000)
+#define MCF_SEC_DIMR_CE                      (0x40000)
+#define MCF_SEC_DIMR_ERE                     (0x80000)
+#define MCF_SEC_DIMR_IE                      (0x100000)
+#define MCF_SEC_DIMR_KPE                     (0x200000)
+#define MCF_SEC_DIMR_OFU                     (0x2000000)
+#define MCF_SEC_DIMR_IFO                     (0x4000000)
+#define MCF_SEC_DIMR_IFE                     (0x10000000)
+#define MCF_SEC_DIMR_OFE                     (0x20000000)
+#define MCF_SEC_DIMR_AE                      (0x40000000)
+#define MCF_SEC_DIMR_ME                      (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_MDRCR */
+#define MCF_SEC_MDRCR_SR                     (0x1000000)
+#define MCF_SEC_MDRCR_MI                     (0x2000000)
+#define MCF_SEC_MDRCR_RI                     (0x4000000)
+
+/* Bit definitions and macros for MCF_SEC_MDSR */
+#define MCF_SEC_MDSR_RD                      (0x1000000)
+#define MCF_SEC_MDSR_ID                      (0x2000000)
+#define MCF_SEC_MDSR_IE                      (0x4000000)
+#define MCF_SEC_MDSR_IFW                     (0x10000000)
+#define MCF_SEC_MDSR_HALT                    (0x20000000)
+
+/* Bit definitions and macros for MCF_SEC_MDISR */
+#define MCF_SEC_MDISR_DSE                    (0x10000)
+#define MCF_SEC_MDISR_KSE                    (0x20000)
+#define MCF_SEC_MDISR_CE                     (0x40000)
+#define MCF_SEC_MDISR_ERE                    (0x80000)
+#define MCF_SEC_MDISR_IE                     (0x100000)
+#define MCF_SEC_MDISR_IFO                    (0x4000000)
+#define MCF_SEC_MDISR_AE                     (0x40000000)
+#define MCF_SEC_MDISR_ME                     (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_MDIMR */
+#define MCF_SEC_MDIMR_DSE                    (0x10000)
+#define MCF_SEC_MDIMR_KSE                    (0x20000)
+#define MCF_SEC_MDIMR_CE                     (0x40000)
+#define MCF_SEC_MDIMR_ERE                    (0x80000)
+#define MCF_SEC_MDIMR_IE                     (0x100000)
+#define MCF_SEC_MDIMR_IFO                    (0x4000000)
+#define MCF_SEC_MDIMR_AE                     (0x40000000)
+#define MCF_SEC_MDIMR_ME                     (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_RNGRCR */
+#define MCF_SEC_RNGRCR_SR                    (0x1000000)
+#define MCF_SEC_RNGRCR_MI                    (0x2000000)
+#define MCF_SEC_RNGRCR_RI                    (0x4000000)
+
+/* Bit definitions and macros for MCF_SEC_RNGSR */
+#define MCF_SEC_RNGSR_RD                     (0x1000000)
+#define MCF_SEC_RNGSR_IE                     (0x4000000)
+#define MCF_SEC_RNGSR_OFR                    (0x8000000)
+#define MCF_SEC_RNGSR_HALT                   (0x20000000)
+
+/* Bit definitions and macros for MCF_SEC_RNGISR */
+#define MCF_SEC_RNGISR_IE                    (0x100000)
+#define MCF_SEC_RNGISR_OFU                   (0x2000000)
+#define MCF_SEC_RNGISR_AE                    (0x40000000)
+#define MCF_SEC_RNGISR_ME                    (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_RNGIMR */
+#define MCF_SEC_RNGIMR_IE                    (0x100000)
+#define MCF_SEC_RNGIMR_OFU                   (0x2000000)
+#define MCF_SEC_RNGIMR_AE                    (0x40000000)
+#define MCF_SEC_RNGIMR_ME                    (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_AESRCR */
+#define MCF_SEC_AESRCR_SR                    (0x1000000)
+#define MCF_SEC_AESRCR_MI                    (0x2000000)
+#define MCF_SEC_AESRCR_RI                    (0x4000000)
+
+/* Bit definitions and macros for MCF_SEC_AESSR */
+#define MCF_SEC_AESSR_RD                     (0x1000000)
+#define MCF_SEC_AESSR_ID                     (0x2000000)
+#define MCF_SEC_AESSR_IE                     (0x4000000)
+#define MCF_SEC_AESSR_OFR                    (0x8000000)
+#define MCF_SEC_AESSR_IFW                    (0x10000000)
+#define MCF_SEC_AESSR_HALT                   (0x20000000)
+
+/* Bit definitions and macros for MCF_SEC_AESISR */
+#define MCF_SEC_AESISR_DSE                   (0x10000)
+#define MCF_SEC_AESISR_KSE                   (0x20000)
+#define MCF_SEC_AESISR_CE                    (0x40000)
+#define MCF_SEC_AESISR_ERE                   (0x80000)
+#define MCF_SEC_AESISR_IE                    (0x100000)
+#define MCF_SEC_AESISR_OFU                   (0x2000000)
+#define MCF_SEC_AESISR_IFO                   (0x4000000)
+#define MCF_SEC_AESISR_IFE                   (0x10000000)
+#define MCF_SEC_AESISR_OFE                   (0x20000000)
+#define MCF_SEC_AESISR_AE                    (0x40000000)
+#define MCF_SEC_AESISR_ME                    (0x80000000)
+
+/* Bit definitions and macros for MCF_SEC_AESIMR */
+#define MCF_SEC_AESIMR_DSE                   (0x10000)
+#define MCF_SEC_AESIMR_KSE                   (0x20000)
+#define MCF_SEC_AESIMR_CE                    (0x40000)
+#define MCF_SEC_AESIMR_ERE                   (0x80000)
+#define MCF_SEC_AESIMR_IE                    (0x100000)
+#define MCF_SEC_AESIMR_OFU                   (0x2000000)
+#define MCF_SEC_AESIMR_IFO                   (0x4000000)
+#define MCF_SEC_AESIMR_IFE                   (0x10000000)
+#define MCF_SEC_AESIMR_OFE                   (0x20000000)
+#define MCF_SEC_AESIMR_AE                    (0x40000000)
+#define MCF_SEC_AESIMR_ME                    (0x80000000)
+
+
+#endif /* __MCF5475_SEC_H__ */
diff --git a/firebeeV1/headers/MCF5475_SIU.h b/firebeeV1/headers/MCF5475_SIU.h
new file mode 100644
index 0000000..498aa91
--- /dev/null
+++ b/firebeeV1/headers/MCF5475_SIU.h
@@ -0,0 +1,52 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_SIU_H__
+#define __MCF5475_SIU_H__
+
+
+/*********************************************************************
+*
+* System Integration Unit (SIU)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_SIU_SBCR                         (*(vuint32*)(&__MBAR[0x10]))
+#define MCF_SIU_SECSACR                      (*(vuint32*)(&__MBAR[0x38]))
+#define MCF_SIU_RSR                          (*(vuint32*)(&__MBAR[0x44]))
+#define MCF_SIU_JTAGID                       (*(vuint32*)(&__MBAR[0x50]))
+
+
+/* Bit definitions and macros for MCF_SIU_SBCR */
+#define MCF_SIU_SBCR_PIN2DSPI                (0x8000000)
+#define MCF_SIU_SBCR_DMA2CPU                 (0x10000000)
+#define MCF_SIU_SBCR_CPU2DMA                 (0x20000000)
+#define MCF_SIU_SBCR_PIN2DMA                 (0x40000000)
+#define MCF_SIU_SBCR_PIN2CPU                 (0x80000000)
+
+/* Bit definitions and macros for MCF_SIU_SECSACR */
+#define MCF_SIU_SECSACR_SEQEN                (0x1)
+
+/* Bit definitions and macros for MCF_SIU_RSR */
+#define MCF_SIU_RSR_RST                      (0x1)
+#define MCF_SIU_RSR_RSTWD                    (0x2)
+#define MCF_SIU_RSR_RSTJTG                   (0x8)
+
+/* Bit definitions and macros for MCF_SIU_JTAGID */
+#define MCF_SIU_JTAGID_JTAGID(x)             (((x)&0xFFFFFFFF)<<0)
+
+
+#endif /* __MCF5475_SIU_H__ */
diff --git a/firebeeV1/headers/MCF5475_SLT.h b/firebeeV1/headers/MCF5475_SLT.h
new file mode 100644
index 0000000..44a74c6
--- /dev/null
+++ b/firebeeV1/headers/MCF5475_SLT.h
@@ -0,0 +1,59 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_SLT_H__
+#define __MCF5475_SLT_H__
+
+
+/*********************************************************************
+*
+* Slice Timers (SLT)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_SLT0_STCNT                       (*(vuint32*)(&__MBAR[0x900]))
+#define MCF_SLT0_SCR                         (*(vuint32*)(&__MBAR[0x904]))
+#define MCF_SLT0_SCNT                        (*(vuint32*)(&__MBAR[0x908]))
+#define MCF_SLT0_SSR                         (*(vuint32*)(&__MBAR[0x90C]))
+
+#define MCF_SLT1_STCNT                       (*(vuint32*)(&__MBAR[0x910]))
+#define MCF_SLT1_SCR                         (*(vuint32*)(&__MBAR[0x914]))
+#define MCF_SLT1_SCNT                        (*(vuint32*)(&__MBAR[0x918]))
+#define MCF_SLT1_SSR                         (*(vuint32*)(&__MBAR[0x91C]))
+
+#define MCF_SLT_STCNT(x)                     (*(vuint32*)(&__MBAR[0x900 + ((x)*0x10)]))
+#define MCF_SLT_SCR(x)                       (*(vuint32*)(&__MBAR[0x904 + ((x)*0x10)]))
+#define MCF_SLT_SCNT(x)                      (*(vuint32*)(&__MBAR[0x908 + ((x)*0x10)]))
+#define MCF_SLT_SSR(x)                       (*(vuint32*)(&__MBAR[0x90C + ((x)*0x10)]))
+
+
+/* Bit definitions and macros for MCF_SLT_STCNT */
+#define MCF_SLT_STCNT_TC(x)                  (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_SLT_SCR */
+#define MCF_SLT_SCR_TEN                      (0x1000000)
+#define MCF_SLT_SCR_IEN                      (0x2000000)
+#define MCF_SLT_SCR_RUN                      (0x4000000)
+
+/* Bit definitions and macros for MCF_SLT_SCNT */
+#define MCF_SLT_SCNT_CNT(x)                  (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_SLT_SSR */
+#define MCF_SLT_SSR_ST                       (0x1000000)
+#define MCF_SLT_SSR_BE                       (0x2000000)
+
+
+#endif /* __MCF5475_SLT_H__ */
diff --git a/firebeeV1/headers/MCF5475_SRAM.h b/firebeeV1/headers/MCF5475_SRAM.h
new file mode 100644
index 0000000..7e645fe
--- /dev/null
+++ b/firebeeV1/headers/MCF5475_SRAM.h
@@ -0,0 +1,62 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_SRAM_H__
+#define __MCF5475_SRAM_H__
+
+
+/*********************************************************************
+*
+* System SRAM Module (SRAM)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_SRAM_SSCR                        (*(vuint32*)(&__MBAR[0x1FFC0]))
+#define MCF_SRAM_TCCR                        (*(vuint32*)(&__MBAR[0x1FFC4]))
+#define MCF_SRAM_TCCRDR                      (*(vuint32*)(&__MBAR[0x1FFC8]))
+#define MCF_SRAM_TCCRDW                      (*(vuint32*)(&__MBAR[0x1FFCC]))
+#define MCF_SRAM_TCCRSEC                     (*(vuint32*)(&__MBAR[0x1FFD0]))
+
+
+/* Bit definitions and macros for MCF_SRAM_SSCR */
+#define MCF_SRAM_SSCR_INLV                   (0x10000)
+
+/* Bit definitions and macros for MCF_SRAM_TCCR */
+#define MCF_SRAM_TCCR_BANK0_TC(x)            (((x)&0xF)<<0)
+#define MCF_SRAM_TCCR_BANK1_TC(x)            (((x)&0xF)<<0x8)
+#define MCF_SRAM_TCCR_BANK2_TC(x)            (((x)&0xF)<<0x10)
+#define MCF_SRAM_TCCR_BANK3_TC(x)            (((x)&0xF)<<0x18)
+
+/* Bit definitions and macros for MCF_SRAM_TCCRDR */
+#define MCF_SRAM_TCCRDR_BANK0_TC(x)          (((x)&0xF)<<0)
+#define MCF_SRAM_TCCRDR_BANK1_TC(x)          (((x)&0xF)<<0x8)
+#define MCF_SRAM_TCCRDR_BANK2_TC(x)          (((x)&0xF)<<0x10)
+#define MCF_SRAM_TCCRDR_BANK3_TC(x)          (((x)&0xF)<<0x18)
+
+/* Bit definitions and macros for MCF_SRAM_TCCRDW */
+#define MCF_SRAM_TCCRDW_BANK0_TC(x)          (((x)&0xF)<<0)
+#define MCF_SRAM_TCCRDW_BANK1_TC(x)          (((x)&0xF)<<0x8)
+#define MCF_SRAM_TCCRDW_BANK2_TC(x)          (((x)&0xF)<<0x10)
+#define MCF_SRAM_TCCRDW_BANK3_TC(x)          (((x)&0xF)<<0x18)
+
+/* Bit definitions and macros for MCF_SRAM_TCCRSEC */
+#define MCF_SRAM_TCCRSEC_BANK0_TC(x)         (((x)&0xF)<<0)
+#define MCF_SRAM_TCCRSEC_BANK1_TC(x)         (((x)&0xF)<<0x8)
+#define MCF_SRAM_TCCRSEC_BANK2_TC(x)         (((x)&0xF)<<0x10)
+#define MCF_SRAM_TCCRSEC_BANK3_TC(x)         (((x)&0xF)<<0x18)
+
+
+#endif /* __MCF5475_SRAM_H__ */
diff --git a/firebeeV1/headers/MCF5475_USB.h b/firebeeV1/headers/MCF5475_USB.h
new file mode 100644
index 0000000..da9e6db
--- /dev/null
+++ b/firebeeV1/headers/MCF5475_USB.h
@@ -0,0 +1,554 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_USB_H__
+#define __MCF5475_USB_H__
+
+
+/*********************************************************************
+*
+* Universal Serial Bus Interface (USB)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_USB_USBAISR                      (*(vuint8 *)(&__MBAR[0xB000]))
+#define MCF_USB_USBAIMR                      (*(vuint8 *)(&__MBAR[0xB001]))
+#define MCF_USB_EPINFO                       (*(vuint8 *)(&__MBAR[0xB003]))
+#define MCF_USB_CFGR                         (*(vuint8 *)(&__MBAR[0xB004]))
+#define MCF_USB_CFGAR                        (*(vuint8 *)(&__MBAR[0xB005]))
+#define MCF_USB_SPEEDR                       (*(vuint8 *)(&__MBAR[0xB006]))
+#define MCF_USB_FRMNUMR                      (*(vuint16*)(&__MBAR[0xB00E]))
+#define MCF_USB_EPTNR                        (*(vuint16*)(&__MBAR[0xB010]))
+#define MCF_USB_IFUR                         (*(vuint16*)(&__MBAR[0xB014]))
+#define MCF_USB_IFR0                         (*(vuint16*)(&__MBAR[0xB040]))
+#define MCF_USB_IFR1                         (*(vuint16*)(&__MBAR[0xB042]))
+#define MCF_USB_IFR2                         (*(vuint16*)(&__MBAR[0xB044]))
+#define MCF_USB_IFR3                         (*(vuint16*)(&__MBAR[0xB046]))
+#define MCF_USB_IFR4                         (*(vuint16*)(&__MBAR[0xB048]))
+#define MCF_USB_IFR5                         (*(vuint16*)(&__MBAR[0xB04A]))
+#define MCF_USB_IFR6                         (*(vuint16*)(&__MBAR[0xB04C]))
+#define MCF_USB_IFR7                         (*(vuint16*)(&__MBAR[0xB04E]))
+#define MCF_USB_IFR8                         (*(vuint16*)(&__MBAR[0xB050]))
+#define MCF_USB_IFR9                         (*(vuint16*)(&__MBAR[0xB052]))
+#define MCF_USB_IFR10                        (*(vuint16*)(&__MBAR[0xB054]))
+#define MCF_USB_IFR11                        (*(vuint16*)(&__MBAR[0xB056]))
+#define MCF_USB_IFR12                        (*(vuint16*)(&__MBAR[0xB058]))
+#define MCF_USB_IFR13                        (*(vuint16*)(&__MBAR[0xB05A]))
+#define MCF_USB_IFR14                        (*(vuint16*)(&__MBAR[0xB05C]))
+#define MCF_USB_IFR15                        (*(vuint16*)(&__MBAR[0xB05E]))
+#define MCF_USB_IFR16                        (*(vuint16*)(&__MBAR[0xB060]))
+#define MCF_USB_IFR17                        (*(vuint16*)(&__MBAR[0xB062]))
+#define MCF_USB_IFR18                        (*(vuint16*)(&__MBAR[0xB064]))
+#define MCF_USB_IFR19                        (*(vuint16*)(&__MBAR[0xB066]))
+#define MCF_USB_IFR20                        (*(vuint16*)(&__MBAR[0xB068]))
+#define MCF_USB_IFR21                        (*(vuint16*)(&__MBAR[0xB06A]))
+#define MCF_USB_IFR22                        (*(vuint16*)(&__MBAR[0xB06C]))
+#define MCF_USB_IFR23                        (*(vuint16*)(&__MBAR[0xB06E]))
+#define MCF_USB_IFR24                        (*(vuint16*)(&__MBAR[0xB070]))
+#define MCF_USB_IFR25                        (*(vuint16*)(&__MBAR[0xB072]))
+#define MCF_USB_IFR26                        (*(vuint16*)(&__MBAR[0xB074]))
+#define MCF_USB_IFR27                        (*(vuint16*)(&__MBAR[0xB076]))
+#define MCF_USB_IFR28                        (*(vuint16*)(&__MBAR[0xB078]))
+#define MCF_USB_IFR29                        (*(vuint16*)(&__MBAR[0xB07A]))
+#define MCF_USB_IFR30                        (*(vuint16*)(&__MBAR[0xB07C]))
+#define MCF_USB_IFR31                        (*(vuint16*)(&__MBAR[0xB07E]))
+#define MCF_USB_PPCNT                        (*(vuint16*)(&__MBAR[0xB080]))
+#define MCF_USB_DPCNT                        (*(vuint16*)(&__MBAR[0xB082]))
+#define MCF_USB_CRCECNT                      (*(vuint16*)(&__MBAR[0xB084]))
+#define MCF_USB_BSECNT                       (*(vuint16*)(&__MBAR[0xB086]))
+#define MCF_USB_PIDECNT                      (*(vuint16*)(&__MBAR[0xB088]))
+#define MCF_USB_FRMECNT                      (*(vuint16*)(&__MBAR[0xB08A]))
+#define MCF_USB_TXPCNT                       (*(vuint16*)(&__MBAR[0xB08C]))
+#define MCF_USB_CNTOVR                       (*(vuint8 *)(&__MBAR[0xB08E]))
+#define MCF_USB_EP0ACR                       (*(vuint8 *)(&__MBAR[0xB101]))
+#define MCF_USB_EP0MPSR                      (*(vuint16*)(&__MBAR[0xB102]))
+#define MCF_USB_EP0IFR                       (*(vuint8 *)(&__MBAR[0xB104]))
+#define MCF_USB_EP0SR                        (*(vuint8 *)(&__MBAR[0xB105]))
+#define MCF_USB_BMRTR                        (*(vuint8 *)(&__MBAR[0xB106]))
+#define MCF_USB_BRTR                         (*(vuint8 *)(&__MBAR[0xB107]))
+#define MCF_USB_WVALUER                      (*(vuint16*)(&__MBAR[0xB108]))
+#define MCF_USB_WINDEXR                      (*(vuint16*)(&__MBAR[0xB10A]))
+#define MCF_USB_WLENGTHR                     (*(vuint16*)(&__MBAR[0xB10C]))
+#define MCF_USB_EP1OUTACR                    (*(vuint8 *)(&__MBAR[0xB131]))
+#define MCF_USB_EP1OUTMPSR                   (*(vuint16*)(&__MBAR[0xB132]))
+#define MCF_USB_EP1OUTIFR                    (*(vuint8 *)(&__MBAR[0xB134]))
+#define MCF_USB_EP1OUTSR                     (*(vuint8 *)(&__MBAR[0xB135]))
+#define MCF_USB_EP1OUTSFR                    (*(vuint16*)(&__MBAR[0xB13E]))
+#define MCF_USB_EP1INACR                     (*(vuint8 *)(&__MBAR[0xB149]))
+#define MCF_USB_EP1INMPSR                    (*(vuint16*)(&__MBAR[0xB14A]))
+#define MCF_USB_EP1INIFR                     (*(vuint8 *)(&__MBAR[0xB14C]))
+#define MCF_USB_EP1INSR                      (*(vuint8 *)(&__MBAR[0xB14D]))
+#define MCF_USB_EP1INSFR                     (*(vuint16*)(&__MBAR[0xB156]))
+#define MCF_USB_EP2OUTACR                    (*(vuint8 *)(&__MBAR[0xB161]))
+#define MCF_USB_EP2OUTMPSR                   (*(vuint16*)(&__MBAR[0xB162]))
+#define MCF_USB_EP2OUTIFR                    (*(vuint8 *)(&__MBAR[0xB164]))
+#define MCF_USB_EP2OUTSR                     (*(vuint8 *)(&__MBAR[0xB165]))
+#define MCF_USB_EP2OUTSFR                    (*(vuint16*)(&__MBAR[0xB16E]))
+#define MCF_USB_EP2INACR                     (*(vuint8 *)(&__MBAR[0xB179]))
+#define MCF_USB_EP2INMPSR                    (*(vuint16*)(&__MBAR[0xB17A]))
+#define MCF_USB_EP2INIFR                     (*(vuint8 *)(&__MBAR[0xB17C]))
+#define MCF_USB_EP2INSR                      (*(vuint8 *)(&__MBAR[0xB17D]))
+#define MCF_USB_EP2INSFR                     (*(vuint16*)(&__MBAR[0xB186]))
+#define MCF_USB_EP3OUTACR                    (*(vuint8 *)(&__MBAR[0xB191]))
+#define MCF_USB_EP3OUTMPSR                   (*(vuint16*)(&__MBAR[0xB192]))
+#define MCF_USB_EP3OUTIFR                    (*(vuint8 *)(&__MBAR[0xB194]))
+#define MCF_USB_EP3OUTSR                     (*(vuint8 *)(&__MBAR[0xB195]))
+#define MCF_USB_EP3OUTSFR                    (*(vuint16*)(&__MBAR[0xB19E]))
+#define MCF_USB_EP3INACR                     (*(vuint8 *)(&__MBAR[0xB1A9]))
+#define MCF_USB_EP3INMPSR                    (*(vuint16*)(&__MBAR[0xB1AA]))
+#define MCF_USB_EP3INIFR                     (*(vuint8 *)(&__MBAR[0xB1AC]))
+#define MCF_USB_EP3INSR                      (*(vuint8 *)(&__MBAR[0xB1AD]))
+#define MCF_USB_EP3INSFR                     (*(vuint16*)(&__MBAR[0xB1B6]))
+#define MCF_USB_EP4OUTACR                    (*(vuint8 *)(&__MBAR[0xB1C1]))
+#define MCF_USB_EP4OUTMPSR                   (*(vuint16*)(&__MBAR[0xB1C2]))
+#define MCF_USB_EP4OUTIFR                    (*(vuint8 *)(&__MBAR[0xB1C4]))
+#define MCF_USB_EP4OUTSR                     (*(vuint8 *)(&__MBAR[0xB1C5]))
+#define MCF_USB_EP4OUTSFR                    (*(vuint16*)(&__MBAR[0xB1CE]))
+#define MCF_USB_EP4INACR                     (*(vuint8 *)(&__MBAR[0xB1D9]))
+#define MCF_USB_EP4INMPSR                    (*(vuint16*)(&__MBAR[0xB1DA]))
+#define MCF_USB_EP4INIFR                     (*(vuint8 *)(&__MBAR[0xB1DC]))
+#define MCF_USB_EP4INSR                      (*(vuint8 *)(&__MBAR[0xB1DD]))
+#define MCF_USB_EP4INSFR                     (*(vuint16*)(&__MBAR[0xB1E6]))
+#define MCF_USB_EP5OUTACR                    (*(vuint8 *)(&__MBAR[0xB1F1]))
+#define MCF_USB_EP5OUTMPSR                   (*(vuint16*)(&__MBAR[0xB1F2]))
+#define MCF_USB_EP5OUTIFR                    (*(vuint8 *)(&__MBAR[0xB1F4]))
+#define MCF_USB_EP5OUTSR                     (*(vuint8 *)(&__MBAR[0xB1F5]))
+#define MCF_USB_EP5OUTSFR                    (*(vuint16*)(&__MBAR[0xB1FE]))
+#define MCF_USB_EP5INACR                     (*(vuint8 *)(&__MBAR[0xB209]))
+#define MCF_USB_EP5INMPSR                    (*(vuint16*)(&__MBAR[0xB20A]))
+#define MCF_USB_EP5INIFR                     (*(vuint8 *)(&__MBAR[0xB20C]))
+#define MCF_USB_EP5INSR                      (*(vuint8 *)(&__MBAR[0xB20D]))
+#define MCF_USB_EP5INSFR                     (*(vuint16*)(&__MBAR[0xB216]))
+#define MCF_USB_EP6OUTACR                    (*(vuint8 *)(&__MBAR[0xB221]))
+#define MCF_USB_EP6OUTMPSR                   (*(vuint16*)(&__MBAR[0xB222]))
+#define MCF_USB_EP6OUTIFR                    (*(vuint8 *)(&__MBAR[0xB224]))
+#define MCF_USB_EP6OUTSR                     (*(vuint8 *)(&__MBAR[0xB225]))
+#define MCF_USB_EP6OUTSFR                    (*(vuint16*)(&__MBAR[0xB22E]))
+#define MCF_USB_EP6INACR                     (*(vuint8 *)(&__MBAR[0xB239]))
+#define MCF_USB_EP6INMPSR                    (*(vuint16*)(&__MBAR[0xB23A]))
+#define MCF_USB_EP6INIFR                     (*(vuint8 *)(&__MBAR[0xB23C]))
+#define MCF_USB_EP6INSR                      (*(vuint8 *)(&__MBAR[0xB23D]))
+#define MCF_USB_EP6INSFR                     (*(vuint16*)(&__MBAR[0xB246]))
+#define MCF_USB_USBSR                        (*(vuint32*)(&__MBAR[0xB400]))
+#define MCF_USB_USBCR                        (*(vuint32*)(&__MBAR[0xB404]))
+#define MCF_USB_DRAMCR                       (*(vuint32*)(&__MBAR[0xB408]))
+#define MCF_USB_DRAMDR                       (*(vuint32*)(&__MBAR[0xB40C]))
+#define MCF_USB_USBISR                       (*(vuint32*)(&__MBAR[0xB410]))
+#define MCF_USB_USBIMR                       (*(vuint32*)(&__MBAR[0xB414]))
+#define MCF_USB_EP0STAT                      (*(vuint32*)(&__MBAR[0xB440]))
+#define MCF_USB_EP0ISR                       (*(vuint32*)(&__MBAR[0xB444]))
+#define MCF_USB_EP0IMR                       (*(vuint32*)(&__MBAR[0xB448]))
+#define MCF_USB_EP0FRCFGR                    (*(vuint32*)(&__MBAR[0xB44C]))
+#define MCF_USB_EP0FDR                       (*(vuint32*)(&__MBAR[0xB450]))
+#define MCF_USB_EP0FSR                       (*(vuint32*)(&__MBAR[0xB454]))
+#define MCF_USB_EP0FCR                       (*(vuint32*)(&__MBAR[0xB458]))
+#define MCF_USB_EP0FAR                       (*(vuint32*)(&__MBAR[0xB45C]))
+#define MCF_USB_EP0FRP                       (*(vuint32*)(&__MBAR[0xB460]))
+#define MCF_USB_EP0FWP                       (*(vuint32*)(&__MBAR[0xB464]))
+#define MCF_USB_EP0LRFP                      (*(vuint32*)(&__MBAR[0xB468]))
+#define MCF_USB_EP0LWFP                      (*(vuint32*)(&__MBAR[0xB46C]))
+#define MCF_USB_EP1STAT                      (*(vuint32*)(&__MBAR[0xB470]))
+#define MCF_USB_EP1ISR                       (*(vuint32*)(&__MBAR[0xB474]))
+#define MCF_USB_EP1IMR                       (*(vuint32*)(&__MBAR[0xB478]))
+#define MCF_USB_EP1FRCFGR                    (*(vuint32*)(&__MBAR[0xB47C]))
+#define MCF_USB_EP1FDR                       (*(vuint32*)(&__MBAR[0xB480]))
+#define MCF_USB_EP1FSR                       (*(vuint32*)(&__MBAR[0xB484]))
+#define MCF_USB_EP1FCR                       (*(vuint32*)(&__MBAR[0xB488]))
+#define MCF_USB_EP1FAR                       (*(vuint32*)(&__MBAR[0xB48C]))
+#define MCF_USB_EP1FRP                       (*(vuint32*)(&__MBAR[0xB490]))
+#define MCF_USB_EP1FWP                       (*(vuint32*)(&__MBAR[0xB494]))
+#define MCF_USB_EP1LRFP                      (*(vuint32*)(&__MBAR[0xB498]))
+#define MCF_USB_EP1LWFP                      (*(vuint32*)(&__MBAR[0xB49C]))
+#define MCF_USB_EP2STAT                      (*(vuint32*)(&__MBAR[0xB4A0]))
+#define MCF_USB_EP2ISR                       (*(vuint32*)(&__MBAR[0xB4A4]))
+#define MCF_USB_EP2IMR                       (*(vuint32*)(&__MBAR[0xB4A8]))
+#define MCF_USB_EP2FRCFGR                    (*(vuint32*)(&__MBAR[0xB4AC]))
+#define MCF_USB_EP2FDR                       (*(vuint32*)(&__MBAR[0xB4B0]))
+#define MCF_USB_EP2FSR                       (*(vuint32*)(&__MBAR[0xB4B4]))
+#define MCF_USB_EP2FCR                       (*(vuint32*)(&__MBAR[0xB4B8]))
+#define MCF_USB_EP2FAR                       (*(vuint32*)(&__MBAR[0xB4BC]))
+#define MCF_USB_EP2FRP                       (*(vuint32*)(&__MBAR[0xB4C0]))
+#define MCF_USB_EP2FWP                       (*(vuint32*)(&__MBAR[0xB4C4]))
+#define MCF_USB_EP2LRFP                      (*(vuint32*)(&__MBAR[0xB4C8]))
+#define MCF_USB_EP2LWFP                      (*(vuint32*)(&__MBAR[0xB4CC]))
+#define MCF_USB_EP3STAT                      (*(vuint32*)(&__MBAR[0xB4D0]))
+#define MCF_USB_EP3ISR                       (*(vuint32*)(&__MBAR[0xB4D4]))
+#define MCF_USB_EP3IMR                       (*(vuint32*)(&__MBAR[0xB4D8]))
+#define MCF_USB_EP3FRCFGR                    (*(vuint32*)(&__MBAR[0xB4DC]))
+#define MCF_USB_EP3FDR                       (*(vuint32*)(&__MBAR[0xB4E0]))
+#define MCF_USB_EP3FSR                       (*(vuint32*)(&__MBAR[0xB4E4]))
+#define MCF_USB_EP3FCR                       (*(vuint32*)(&__MBAR[0xB4E8]))
+#define MCF_USB_EP3FAR                       (*(vuint32*)(&__MBAR[0xB4EC]))
+#define MCF_USB_EP3FRP                       (*(vuint32*)(&__MBAR[0xB4F0]))
+#define MCF_USB_EP3FWP                       (*(vuint32*)(&__MBAR[0xB4F4]))
+#define MCF_USB_EP3LRFP                      (*(vuint32*)(&__MBAR[0xB4F8]))
+#define MCF_USB_EP3LWFP                      (*(vuint32*)(&__MBAR[0xB4FC]))
+#define MCF_USB_EP4STAT                      (*(vuint32*)(&__MBAR[0xB500]))
+#define MCF_USB_EP4ISR                       (*(vuint32*)(&__MBAR[0xB504]))
+#define MCF_USB_EP4IMR                       (*(vuint32*)(&__MBAR[0xB508]))
+#define MCF_USB_EP4FRCFGR                    (*(vuint32*)(&__MBAR[0xB50C]))
+#define MCF_USB_EP4FDR                       (*(vuint32*)(&__MBAR[0xB510]))
+#define MCF_USB_EP4FSR                       (*(vuint32*)(&__MBAR[0xB514]))
+#define MCF_USB_EP4FCR                       (*(vuint32*)(&__MBAR[0xB518]))
+#define MCF_USB_EP4FAR                       (*(vuint32*)(&__MBAR[0xB51C]))
+#define MCF_USB_EP4FRP                       (*(vuint32*)(&__MBAR[0xB520]))
+#define MCF_USB_EP4FWP                       (*(vuint32*)(&__MBAR[0xB524]))
+#define MCF_USB_EP4LRFP                      (*(vuint32*)(&__MBAR[0xB528]))
+#define MCF_USB_EP4LWFP                      (*(vuint32*)(&__MBAR[0xB52C]))
+#define MCF_USB_EP5STAT                      (*(vuint32*)(&__MBAR[0xB530]))
+#define MCF_USB_EP5ISR                       (*(vuint32*)(&__MBAR[0xB534]))
+#define MCF_USB_EP5IMR                       (*(vuint32*)(&__MBAR[0xB538]))
+#define MCF_USB_EP5FRCFGR                    (*(vuint32*)(&__MBAR[0xB53C]))
+#define MCF_USB_EP5FDR                       (*(vuint32*)(&__MBAR[0xB540]))
+#define MCF_USB_EP5FSR                       (*(vuint32*)(&__MBAR[0xB544]))
+#define MCF_USB_EP5FCR                       (*(vuint32*)(&__MBAR[0xB548]))
+#define MCF_USB_EP5FAR                       (*(vuint32*)(&__MBAR[0xB54C]))
+#define MCF_USB_EP5FRP                       (*(vuint32*)(&__MBAR[0xB550]))
+#define MCF_USB_EP5FWP                       (*(vuint32*)(&__MBAR[0xB554]))
+#define MCF_USB_EP5LRFP                      (*(vuint32*)(&__MBAR[0xB558]))
+#define MCF_USB_EP5LWFP                      (*(vuint32*)(&__MBAR[0xB55C]))
+#define MCF_USB_EP6STAT                      (*(vuint32*)(&__MBAR[0xB560]))
+#define MCF_USB_EP6ISR                       (*(vuint32*)(&__MBAR[0xB564]))
+#define MCF_USB_EP6IMR                       (*(vuint32*)(&__MBAR[0xB568]))
+#define MCF_USB_EP6FRCFGR                    (*(vuint32*)(&__MBAR[0xB56C]))
+#define MCF_USB_EP6FDR                       (*(vuint32*)(&__MBAR[0xB570]))
+#define MCF_USB_EP6FSR                       (*(vuint32*)(&__MBAR[0xB574]))
+#define MCF_USB_EP6FCR                       (*(vuint32*)(&__MBAR[0xB578]))
+#define MCF_USB_EP6FAR                       (*(vuint32*)(&__MBAR[0xB57C]))
+#define MCF_USB_EP6FRP                       (*(vuint32*)(&__MBAR[0xB580]))
+#define MCF_USB_EP6FWP                       (*(vuint32*)(&__MBAR[0xB584]))
+#define MCF_USB_EP6LRFP                      (*(vuint32*)(&__MBAR[0xB588]))
+#define MCF_USB_EP6LWFP                      (*(vuint32*)(&__MBAR[0xB58C]))
+#define MCF_USB_IFR(x)                       (*(vuint16*)(&__MBAR[0xB040 + ((x)*0x2)]))
+#define MCF_USB_EPOUTACR(x)                  (*(vuint8 *)(&__MBAR[0xB131 + ((x-1)*0x30)]))
+#define MCF_USB_EPOUTMPSR(x)                 (*(vuint16*)(&__MBAR[0xB132 + ((x-1)*0x30)]))
+#define MCF_USB_EPOUTIFR(x)                  (*(vuint8 *)(&__MBAR[0xB134 + ((x-1)*0x30)]))
+#define MCF_USB_EPOUTSR(x)                   (*(vuint8 *)(&__MBAR[0xB135 + ((x-1)*0x30)]))
+#define MCF_USB_EPOUTSFR(x)                  (*(vuint16*)(&__MBAR[0xB13E + ((x-1)*0x30)]))
+#define MCF_USB_EPINACR(x)                   (*(vuint8 *)(&__MBAR[0xB149 + ((x-1)*0x30)]))
+#define MCF_USB_EPINMPSR(x)                  (*(vuint16*)(&__MBAR[0xB14A + ((x-1)*0x30)]))
+#define MCF_USB_EPINIFR(x)                   (*(vuint8 *)(&__MBAR[0xB14C + ((x-1)*0x30)]))
+#define MCF_USB_EPINSR(x)                    (*(vuint8 *)(&__MBAR[0xB14D + ((x-1)*0x30)]))
+#define MCF_USB_EPINSFR(x)                   (*(vuint16*)(&__MBAR[0xB156 + ((x-1)*0x30)]))
+#define MCF_USB_EPSTAT(x)                    (*(vuint32*)(&__MBAR[0xB440 + ((x)*0x30)]))
+#define MCF_USB_EPISR(x)                     (*(vuint32*)(&__MBAR[0xB444 + ((x)*0x30)]))
+#define MCF_USB_EPIMR(x)                     (*(vuint32*)(&__MBAR[0xB448 + ((x)*0x30)]))
+#define MCF_USB_EPFRCFGR(x)                  (*(vuint32*)(&__MBAR[0xB44C + ((x)*0x30)]))
+#define MCF_USB_EPFDR(x)                     (*(vuint32*)(&__MBAR[0xB450 + ((x)*0x30)]))
+#define MCF_USB_EPFSR(x)                     (*(vuint32*)(&__MBAR[0xB454 + ((x)*0x30)]))
+#define MCF_USB_EPFCR(x)                     (*(vuint32*)(&__MBAR[0xB458 + ((x)*0x30)]))
+#define MCF_USB_EPFAR(x)                     (*(vuint32*)(&__MBAR[0xB45C + ((x)*0x30)]))
+#define MCF_USB_EPFRP(x)                     (*(vuint32*)(&__MBAR[0xB460 + ((x)*0x30)]))
+#define MCF_USB_EPFWP(x)                     (*(vuint32*)(&__MBAR[0xB464 + ((x)*0x30)]))
+#define MCF_USB_EPLRFP(x)                    (*(vuint32*)(&__MBAR[0xB468 + ((x)*0x30)]))
+#define MCF_USB_EPLWFP(x)                    (*(vuint32*)(&__MBAR[0xB46C + ((x)*0x30)]))
+
+
+/* Bit definitions and macros for MCF_USB_USBAISR */
+#define MCF_USB_USBAISR_SETUP                (0x1)
+#define MCF_USB_USBAISR_IN                   (0x2)
+#define MCF_USB_USBAISR_OUT                  (0x4)
+#define MCF_USB_USBAISR_EPHALT               (0x8)
+#define MCF_USB_USBAISR_TRANSERR             (0x10)
+#define MCF_USB_USBAISR_ACK                  (0x20)
+#define MCF_USB_USBAISR_CTROVFL              (0x40)
+#define MCF_USB_USBAISR_EPSTALL              (0x80)
+
+/* Bit definitions and macros for MCF_USB_USBAIMR */
+#define MCF_USB_USBAIMR_SETUPEN              (0x1)
+#define MCF_USB_USBAIMR_INEN                 (0x2)
+#define MCF_USB_USBAIMR_OUTEN                (0x4)
+#define MCF_USB_USBAIMR_EPHALTEN             (0x8)
+#define MCF_USB_USBAIMR_TRANSERREN           (0x10)
+#define MCF_USB_USBAIMR_ACKEN                (0x20)
+#define MCF_USB_USBAIMR_CTROVFLEN            (0x40)
+#define MCF_USB_USBAIMR_EPSTALLEN            (0x80)
+
+/* Bit definitions and macros for MCF_USB_EPINFO */
+#define MCF_USB_EPINFO_EPDIR                 (0x1)
+#define MCF_USB_EPINFO_EPNUM(x)              (((x)&0x7)<<0x1)
+
+/* Bit definitions and macros for MCF_USB_CFGR */
+#define MCF_USB_CFGR_Configuration_Value(x)  (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_CFGAR */
+#define MCF_USB_CFGAR_RESERVED               (0xA0)
+#define MCF_USB_CFGAR_RMTWKEUP               (0xE0)
+
+/* Bit definitions and macros for MCF_USB_SPEEDR */
+#define MCF_USB_SPEEDR_SPEED(x)              (((x)&0x3)<<0)
+
+/* Bit definitions and macros for MCF_USB_FRMNUMR */
+#define MCF_USB_FRMNUMR_FRMNUM(x)            (((x)&0xFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_EPTNR */
+#define MCF_USB_EPTNR_EP1T(x)                (((x)&0x3)<<0)
+#define MCF_USB_EPTNR_EP2T(x)                (((x)&0x3)<<0x2)
+#define MCF_USB_EPTNR_EP3T(x)                (((x)&0x3)<<0x4)
+#define MCF_USB_EPTNR_EP4T(x)                (((x)&0x3)<<0x6)
+#define MCF_USB_EPTNR_EP5T(x)                (((x)&0x3)<<0x8)
+#define MCF_USB_EPTNR_EP6T(x)                (((x)&0x3)<<0xA)
+#define MCF_USB_EPTNR_EPnT1                  (0)
+#define MCF_USB_EPTNR_EPnT2                  (0x1)
+#define MCF_USB_EPTNR_EPnT3                  (0x2)
+
+/* Bit definitions and macros for MCF_USB_IFUR */
+#define MCF_USB_IFUR_ALTSET(x)               (((x)&0xFF)<<0)
+#define MCF_USB_IFUR_IFNUM(x)                (((x)&0xFF)<<0x8)
+
+/* Bit definitions and macros for MCF_USB_IFR */
+#define MCF_USB_IFR_ALTSET(x)                (((x)&0xFF)<<0)
+#define MCF_USB_IFR_IFNUM(x)                 (((x)&0xFF)<<0x8)
+
+/* Bit definitions and macros for MCF_USB_PPCNT */
+#define MCF_USB_PPCNT_PPCNT(x)               (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_DPCNT */
+#define MCF_USB_DPCNT_DPCNT(x)               (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_CRCECNT */
+#define MCF_USB_CRCECNT_CRCECNT(x)           (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_BSECNT */
+#define MCF_USB_BSECNT_BSECNT(x)             (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_PIDECNT */
+#define MCF_USB_PIDECNT_PIDECNT(x)           (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_FRMECNT */
+#define MCF_USB_FRMECNT_FRMECNT(x)           (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_TXPCNT */
+#define MCF_USB_TXPCNT_TXPCNT(x)             (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_CNTOVR */
+#define MCF_USB_CNTOVR_PPCNT                 (0x1)
+#define MCF_USB_CNTOVR_DPCNT                 (0x2)
+#define MCF_USB_CNTOVR_CRCECNT               (0x4)
+#define MCF_USB_CNTOVR_BSECNT                (0x8)
+#define MCF_USB_CNTOVR_PIDECNT               (0x10)
+#define MCF_USB_CNTOVR_FRMECNT               (0x20)
+#define MCF_USB_CNTOVR_TXPCNT                (0x40)
+
+/* Bit definitions and macros for MCF_USB_EP0ACR */
+#define MCF_USB_EP0ACR_TTYPE(x)              (((x)&0x3)<<0)
+#define MCF_USB_EP0ACR_TTYPE_CTRL            (0)
+#define MCF_USB_EP0ACR_TTYPE_ISOC            (0x1)
+#define MCF_USB_EP0ACR_TTYPE_BULK            (0x2)
+#define MCF_USB_EP0ACR_TTYPE_INT             (0x3)
+
+/* Bit definitions and macros for MCF_USB_EP0MPSR */
+#define MCF_USB_EP0MPSR_MAXPKTSZ(x)          (((x)&0x7FF)<<0)
+#define MCF_USB_EP0MPSR_ADDTRANS(x)          (((x)&0x3)<<0xB)
+
+/* Bit definitions and macros for MCF_USB_EP0IFR */
+#define MCF_USB_EP0IFR_IFNUM(x)              (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_EP0SR */
+#define MCF_USB_EP0SR_HALT                   (0x1)
+#define MCF_USB_EP0SR_ACTIVE                 (0x2)
+#define MCF_USB_EP0SR_PSTALL                 (0x4)
+#define MCF_USB_EP0SR_CCOMP                  (0x8)
+#define MCF_USB_EP0SR_TXZERO                 (0x20)
+#define MCF_USB_EP0SR_INT                    (0x80)
+
+/* Bit definitions and macros for MCF_USB_BMRTR */
+#define MCF_USB_BMRTR_REC(x)                 (((x)&0x1F)<<0)
+#define MCF_USB_BMRTR_REC_DEVICE             (0)
+#define MCF_USB_BMRTR_REC_INTERFACE          (0x1)
+#define MCF_USB_BMRTR_REC_ENDPOINT           (0x2)
+#define MCF_USB_BMRTR_REC_OTHER              (0x3)
+#define MCF_USB_BMRTR_TYPE(x)                (((x)&0x3)<<0x5)
+#define MCF_USB_BMRTR_TYPE_STANDARD          (0)
+#define MCF_USB_BMRTR_TYPE_CLASS             (0x20)
+#define MCF_USB_BMRTR_TYPE_VENDOR            (0x40)
+#define MCF_USB_BMRTR_DIR                    (0x80)
+
+/* Bit definitions and macros for MCF_USB_BRTR */
+#define MCF_USB_BRTR_BREQ(x)                 (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_WVALUER */
+#define MCF_USB_WVALUER_WVALUE(x)            (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_WINDEXR */
+#define MCF_USB_WINDEXR_WINDEX(x)            (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_WLENGTHR */
+#define MCF_USB_WLENGTHR_WLENGTH(x)          (((x)&0xFFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_EPOUTACR */
+#define MCF_USB_EPOUTACR_TTYPE(x)            (((x)&0x3)<<0)
+#define MCF_USB_EPOUTACR_TTYPE_ISOC          (0x1)
+#define MCF_USB_EPOUTACR_TTYPE_BULK          (0x2)
+#define MCF_USB_EPOUTACR_TTYPE_INT           (0x3)
+
+/* Bit definitions and macros for MCF_USB_EPOUTMPSR */
+#define MCF_USB_EPOUTMPSR_MAXPKTSZ(x)        (((x)&0x7FF)<<0)
+#define MCF_USB_EPOUTMPSR_ADDTRANS(x)        (((x)&0x3)<<0xB)
+
+/* Bit definitions and macros for MCF_USB_EPOUTIFR */
+#define MCF_USB_EPOUTIFR_IFNUM(x)            (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_EPOUTSR */
+#define MCF_USB_EPOUTSR_HALT                 (0x1)
+#define MCF_USB_EPOUTSR_ACTIVE               (0x2)
+#define MCF_USB_EPOUTSR_PSTALL               (0x4)
+#define MCF_USB_EPOUTSR_CCOMP                (0x8)
+#define MCF_USB_EPOUTSR_TXZERO               (0x20)
+#define MCF_USB_EPOUTSR_INT                  (0x80)
+
+/* Bit definitions and macros for MCF_USB_EPOUTSFR */
+#define MCF_USB_EPOUTSFR_FRMNUM(x)           (((x)&0x7FF)<<0)
+
+/* Bit definitions and macros for MCF_USB_EPINACR */
+#define MCF_USB_EPINACR_TTYPE(x)             (((x)&0x3)<<0)
+#define MCF_USB_EPINACR_TTYPE_ISOC           (0x1)
+#define MCF_USB_EPINACR_TTYPE_BULK           (0x2)
+#define MCF_USB_EPINACR_TTYPE_INT            (0x3)
+
+/* Bit definitions and macros for MCF_USB_EPINMPSR */
+#define MCF_USB_EPINMPSR_MAXPKTSZ(x)         (((x)&0x7FF)<<0)
+#define MCF_USB_EPINMPSR_ADDTRANS(x)         (((x)&0x3)<<0xB)
+
+/* Bit definitions and macros for MCF_USB_EPINIFR */
+#define MCF_USB_EPINIFR_IFNUM(x)             (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_EPINSR */
+#define MCF_USB_EPINSR_HALT                  (0x1)
+#define MCF_USB_EPINSR_ACTIVE                (0x2)
+#define MCF_USB_EPINSR_PSTALL                (0x4)
+#define MCF_USB_EPINSR_CCOMP                 (0x8)
+#define MCF_USB_EPINSR_TXZERO                (0x20)
+#define MCF_USB_EPINSR_INT                   (0x80)
+
+/* Bit definitions and macros for MCF_USB_EPINSFR */
+#define MCF_USB_EPINSFR_FRMNUM(x)            (((x)&0x7FF)<<0)
+
+/* Bit definitions and macros for MCF_USB_USBSR */
+#define MCF_USB_USBSR_ISOERREP(x)            (((x)&0xF)<<0)
+#define MCF_USB_USBSR_SUSP                   (0x80)
+
+/* Bit definitions and macros for MCF_USB_USBCR */
+#define MCF_USB_USBCR_RESUME                 (0x1)
+#define MCF_USB_USBCR_APPLOCK                (0x2)
+#define MCF_USB_USBCR_RST                    (0x4)
+#define MCF_USB_USBCR_RAMEN                  (0x8)
+#define MCF_USB_USBCR_RAMSPLIT               (0x20)
+
+/* Bit definitions and macros for MCF_USB_DRAMCR */
+#define MCF_USB_DRAMCR_DADR(x)               (((x)&0x3FF)<<0)
+#define MCF_USB_DRAMCR_DSIZE(x)              (((x)&0x7FF)<<0x10)
+#define MCF_USB_DRAMCR_BSY                   (0x40000000)
+#define MCF_USB_DRAMCR_START                 (0x80000000)
+
+/* Bit definitions and macros for MCF_USB_DRAMDR */
+#define MCF_USB_DRAMDR_DDAT(x)               (((x)&0xFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_USBISR */
+#define MCF_USB_USBISR_ISOERR                (0x1)
+#define MCF_USB_USBISR_FTUNLCK               (0x2)
+#define MCF_USB_USBISR_SUSP                  (0x4)
+#define MCF_USB_USBISR_RES                   (0x8)
+#define MCF_USB_USBISR_UPDSOF                (0x10)
+#define MCF_USB_USBISR_RSTSTOP               (0x20)
+#define MCF_USB_USBISR_SOF                   (0x40)
+#define MCF_USB_USBISR_MSOF                  (0x80)
+
+/* Bit definitions and macros for MCF_USB_USBIMR */
+#define MCF_USB_USBIMR_ISOERR                (0x1)
+#define MCF_USB_USBIMR_FTUNLCK               (0x2)
+#define MCF_USB_USBIMR_SUSP                  (0x4)
+#define MCF_USB_USBIMR_RES                   (0x8)
+#define MCF_USB_USBIMR_UPDSOF                (0x10)
+#define MCF_USB_USBIMR_RSTSTOP               (0x20)
+#define MCF_USB_USBIMR_SOF                   (0x40)
+#define MCF_USB_USBIMR_MSOF                  (0x80)
+
+/* Bit definitions and macros for MCF_USB_EPSTAT */
+#define MCF_USB_EPSTAT_RST                   (0x1)
+#define MCF_USB_EPSTAT_FLUSH                 (0x2)
+#define MCF_USB_EPSTAT_DIR                   (0x80)
+#define MCF_USB_EPSTAT_BYTECNT(x)            (((x)&0xFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_USB_EPISR */
+#define MCF_USB_EPISR_EOF                    (0x1)
+#define MCF_USB_EPISR_EOT                    (0x4)
+#define MCF_USB_EPISR_FIFOLO                 (0x10)
+#define MCF_USB_EPISR_FIFOHI                 (0x20)
+#define MCF_USB_EPISR_ERR                    (0x40)
+#define MCF_USB_EPISR_EMT                    (0x80)
+#define MCF_USB_EPISR_FU                     (0x100)
+
+/* Bit definitions and macros for MCF_USB_EPIMR */
+#define MCF_USB_EPIMR_EOF                    (0x1)
+#define MCF_USB_EPIMR_EOT                    (0x4)
+#define MCF_USB_EPIMR_FIFOLO                 (0x10)
+#define MCF_USB_EPIMR_FIFOHI                 (0x20)
+#define MCF_USB_EPIMR_ERR                    (0x40)
+#define MCF_USB_EPIMR_EMT                    (0x80)
+#define MCF_USB_EPIMR_FU                     (0x100)
+
+/* Bit definitions and macros for MCF_USB_EPFRCFGR */
+#define MCF_USB_EPFRCFGR_DEPTH(x)            (((x)&0x1FFF)<<0)
+#define MCF_USB_EPFRCFGR_BASE(x)             (((x)&0xFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_USB_EPFDR */
+#define MCF_USB_EPFDR_RX_TXDATA(x)           (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_EPFSR */
+#define MCF_USB_EPFSR_EMT                    (0x10000)
+#define MCF_USB_EPFSR_ALRM                   (0x20000)
+#define MCF_USB_EPFSR_FU                     (0x40000)
+#define MCF_USB_EPFSR_FR                     (0x80000)
+#define MCF_USB_EPFSR_OF                     (0x100000)
+#define MCF_USB_EPFSR_UF                     (0x200000)
+#define MCF_USB_EPFSR_RXW                    (0x400000)
+#define MCF_USB_EPFSR_FAE                    (0x800000)
+#define MCF_USB_EPFSR_FRM(x)                 (((x)&0xF)<<0x18)
+#define MCF_USB_EPFSR_TXW                    (0x40000000)
+#define MCF_USB_EPFSR_IP                     (0x80000000)
+
+/* Bit definitions and macros for MCF_USB_EPFCR */
+#define MCF_USB_EPFCR_COUNTER(x)             (((x)&0xFFFF)<<0)
+#define MCF_USB_EPFCR_TXWMSK                 (0x40000)
+#define MCF_USB_EPFCR_OFMSK                  (0x80000)
+#define MCF_USB_EPFCR_UFMSK                  (0x100000)
+#define MCF_USB_EPFCR_RXWMSK                 (0x200000)
+#define MCF_USB_EPFCR_FAEMSK                 (0x400000)
+#define MCF_USB_EPFCR_IPMSK                  (0x800000)
+#define MCF_USB_EPFCR_GR(x)                  (((x)&0x7)<<0x18)
+#define MCF_USB_EPFCR_FRM                    (0x8000000)
+#define MCF_USB_EPFCR_TMR                    (0x10000000)
+#define MCF_USB_EPFCR_WFR                    (0x20000000)
+#define MCF_USB_EPFCR_SHAD                   (0x80000000)
+
+/* Bit definitions and macros for MCF_USB_EPFAR */
+#define MCF_USB_EPFAR_ALRMP(x)               (((x)&0xFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_EPFRP */
+#define MCF_USB_EPFRP_RP(x)                  (((x)&0xFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_EPFWP */
+#define MCF_USB_EPFWP_WP(x)                  (((x)&0xFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_EPLRFP */
+#define MCF_USB_EPLRFP_LRFP(x)               (((x)&0xFFF)<<0)
+
+/* Bit definitions and macros for MCF_USB_EPLWFP */
+#define MCF_USB_EPLWFP_LWFP(x)               (((x)&0xFFF)<<0)
+
+
+#endif /* __MCF5475_USB_H__ */
diff --git a/firebeeV1/headers/MCF5475_XLB.h b/firebeeV1/headers/MCF5475_XLB.h
new file mode 100644
index 0000000..f13a20c
--- /dev/null
+++ b/firebeeV1/headers/MCF5475_XLB.h
@@ -0,0 +1,101 @@
+/* Coldfire C Header File
+ * Copyright Freescale Semiconductor Inc
+ * All rights reserved.
+ *
+ * 2008/05/23 Revision: 0.81
+ *
+ * (c) Copyright UNIS, a.s. 1997-2008
+ * UNIS, a.s.
+ * Jundrovska 33
+ * 624 00 Brno
+ * Czech Republic
+ * http      : www.processorexpert.com
+ * mail      : info@processorexpert.com
+ */
+
+#ifndef __MCF5475_XLB_H__
+#define __MCF5475_XLB_H__
+
+
+/*********************************************************************
+*
+* XL Bus Arbiter (XLB)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_XLB_XARB_CFG                     (*(vuint32*)(&__MBAR[0x240]))
+#define MCF_XLB_XARB_VER                     (*(vuint32*)(&__MBAR[0x244]))
+#define MCF_XLB_XARB_SR                      (*(vuint32*)(&__MBAR[0x248]))
+#define MCF_XLB_XARB_IMR                     (*(vuint32*)(&__MBAR[0x24C]))
+#define MCF_XLB_XARB_ADRCAP                  (*(vuint32*)(&__MBAR[0x250]))
+#define MCF_XLB_XARB_SIGCAP                  (*(vuint32*)(&__MBAR[0x254]))
+#define MCF_XLB_XARB_ADRTO                   (*(vuint32*)(&__MBAR[0x258]))
+#define MCF_XLB_XARB_DATTO                   (*(vuint32*)(&__MBAR[0x25C]))
+#define MCF_XLB_XARB_BUSTO                   (*(vuint32*)(&__MBAR[0x260]))
+#define MCF_XLB_XARB_PRIEN                   (*(vuint32*)(&__MBAR[0x264]))
+#define MCF_XLB_XARB_PRI                     (*(vuint32*)(&__MBAR[0x268]))
+
+
+/* Bit definitions and macros for MCF_XLB_XARB_CFG */
+#define MCF_XLB_XARB_CFG_AT                  (0x2)
+#define MCF_XLB_XARB_CFG_DT                  (0x4)
+#define MCF_XLB_XARB_CFG_BA                  (0x8)
+#define MCF_XLB_XARB_CFG_PM(x)               (((x)&0x3)<<0x5)
+#define MCF_XLB_XARB_CFG_SP(x)               (((x)&0x7)<<0x8)
+#define MCF_XLB_XARB_CFG_PLDIS               (0x80000000)
+
+/* Bit definitions and macros for MCF_XLB_XARB_VER */
+#define MCF_XLB_XARB_VER_VER(x)              (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_XLB_XARB_SR */
+#define MCF_XLB_XARB_SR_AT                   (0x1)
+#define MCF_XLB_XARB_SR_DT                   (0x2)
+#define MCF_XLB_XARB_SR_BA                   (0x4)
+#define MCF_XLB_XARB_SR_TTM                  (0x8)
+#define MCF_XLB_XARB_SR_ECW                  (0x10)
+#define MCF_XLB_XARB_SR_TTR                  (0x20)
+#define MCF_XLB_XARB_SR_TTA                  (0x40)
+#define MCF_XLB_XARB_SR_MM                   (0x80)
+#define MCF_XLB_XARB_SR_SEA                  (0x100)
+
+/* Bit definitions and macros for MCF_XLB_XARB_IMR */
+#define MCF_XLB_XARB_IMR_ATE                 (0x1)
+#define MCF_XLB_XARB_IMR_DTE                 (0x2)
+#define MCF_XLB_XARB_IMR_BAE                 (0x4)
+#define MCF_XLB_XARB_IMR_TTME                (0x8)
+#define MCF_XLB_XARB_IMR_ECWE                (0x10)
+#define MCF_XLB_XARB_IMR_TTRE                (0x20)
+#define MCF_XLB_XARB_IMR_TTAE                (0x40)
+#define MCF_XLB_XARB_IMR_MME                 (0x80)
+#define MCF_XLB_XARB_IMR_SEAE                (0x100)
+
+/* Bit definitions and macros for MCF_XLB_XARB_ADRCAP */
+#define MCF_XLB_XARB_ADRCAP_ADRCAP(x)        (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_XLB_XARB_SIGCAP */
+#define MCF_XLB_XARB_SIGCAP_TT(x)            (((x)&0x1F)<<0)
+#define MCF_XLB_XARB_SIGCAP_TBST             (0x20)
+#define MCF_XLB_XARB_SIGCAP_TSIZ(x)          (((x)&0x7)<<0x7)
+
+/* Bit definitions and macros for MCF_XLB_XARB_ADRTO */
+#define MCF_XLB_XARB_ADRTO_ADRTO(x)          (((x)&0xFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_XLB_XARB_DATTO */
+#define MCF_XLB_XARB_DATTO_DATTO(x)          (((x)&0xFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_XLB_XARB_BUSTO */
+#define MCF_XLB_XARB_BUSTO_BUSTO(x)          (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_XLB_XARB_PRIEN */
+#define MCF_XLB_XARB_PRIEN_M0                (0x1)
+#define MCF_XLB_XARB_PRIEN_M2                (0x4)
+#define MCF_XLB_XARB_PRIEN_M3                (0x8)
+
+/* Bit definitions and macros for MCF_XLB_XARB_PRI */
+#define MCF_XLB_XARB_PRI_M0P(x)              (((x)&0x7)<<0)
+#define MCF_XLB_XARB_PRI_M2P(x)              (((x)&0x7)<<0x8)
+#define MCF_XLB_XARB_PRI_M3P(x)              (((x)&0x7)<<0xC)
+
+
+#endif /* __MCF5475_XLB_H__ */
diff --git a/firebeeV1/lcf/DDRAM.lcf b/firebeeV1/lcf/DDRAM.lcf
new file mode 100644
index 0000000..795732d
--- /dev/null
+++ b/firebeeV1/lcf/DDRAM.lcf
@@ -0,0 +1,88 @@
+# Sample Linker Command File for CodeWarrior for ColdFire
+
+KEEP_SECTION {.vectortable}
+
+# Memory ranges	
+
+MEMORY {
+   code	        (RWX) : ORIGIN = 0x00000000, LENGTH = 0x0
+}
+
+SECTIONS {
+ 
+#BaS Basis adresse
+	___Bas_base	= 	0x1FE00000;
+	
+# Board Memory map definitions from linker command files:
+# __SDRAM,__SDRAM_SIZE, __CODE_FLASH, __CODE_FLASH_SIZE 
+# linker symbols must be defined in the linker command file.
+
+#Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes)
+   ___BOOT_FLASH           = 0xE0000000;
+   ___BOOT_FLASH_SIZE      = 0x00800000;
+#SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes	
+   ___SDRAM                = 0x00000000;
+   ___SDRAM_SIZE           = 0x20000000;
+   
+#VIDEO RAM BASIS
+   ___VRAM                = 0x60000000;
+   
+# MCF5475 Derivative Memory map definitions from linker command files:
+# __MBAR, __MMUBAR, __RAMBAR0, __RAMBAR0_SIZE, __RAMBAR1, __RAMBAR1_SIZE
+# linker symbols must be defined in the linker command file.
+
+# Memory mapped registers
+   ___MBAR                 = 0xFF000000;
+   ___MMUBAR               = 0xFF040000;
+# 4KB on-chip Core SRAM0: -> exception table and exception stack
+   ___RAMBAR0              = 0xFF100000;
+   ___RAMBAR0_SIZE         = 0x00001000;
+
+   ___SUP_SP = ___RAMBAR0 + ___RAMBAR0_SIZE - 4;
+   
+# 4KB on-chip Core SRAM1: -> modified code
+   ___RAMBAR1              = 0xFF101000;
+   ___RAMBAR1_SIZE         = 0x00001000;
+
+# Systemveriablem:******************************************
+# RAMBAR0 0 bis 0x7FF -> exception vectoren
+_rt_mod    = ___RAMBAR0 + 0x800;   
+_rt_ssp    = ___RAMBAR0 + 0x804;   
+_rt_usp    = ___RAMBAR0 + 0x808;   
+_rt_vbr    = ___RAMBAR0 + 0x80C;  	# (8)01 
+_rt_cacr   = ___RAMBAR0 + 0x810;   	# 002
+_rt_asid   = ___RAMBAR0 + 0x814;   	# 003
+_rt_acr0   = ___RAMBAR0 + 0x818;   	# 004
+_rt_acr1   = ___RAMBAR0 + 0x81c;   	# 005
+_rt_acr2   = ___RAMBAR0 + 0x820;   	# 006
+_rt_acr3   = ___RAMBAR0 + 0x824;   	# 007
+_rt_mmubar = ___RAMBAR0 + 0x828;	# 008
+_rt_sr     = ___RAMBAR0 + 0x82c;   
+_d0_save   = ___RAMBAR0 + 0x830;
+_a7_save   = ___RAMBAR0 + 0x834;
+_video_tlb = ___RAMBAR0 + 0x838;
+_video_sbt = ___RAMBAR0 + 0x83C;
+_rt_mbar   = ___RAMBAR0 + 0x844;   	# (c)0f
+#***********************************************************
+
+# 32KB on-chip System SRAM
+   ___SYS_SRAM             = 0xFF010000;
+   ___SYS_SRAM_SIZE        = 0x00008000;
+  
+  
+	.text :
+	{
+		startcf.c(.text)
+		sysinit.c(.text)
+		BaS.c(.text)
+		sd_card.c(.text)
+		mmu.s(.text)
+		exceptions.s(.text)
+		supervisor.s(.text)
+		ewf.s(.text)
+		illegal_instruction.s(.text)
+		last.c(.text)
+		. = ALIGN (0x4);
+	} > code
+
+}
\ No newline at end of file
diff --git a/firebeeV1/lcf/FLASH.lcf b/firebeeV1/lcf/FLASH.lcf
new file mode 100644
index 0000000..0315e2f
--- /dev/null
+++ b/firebeeV1/lcf/FLASH.lcf
@@ -0,0 +1,88 @@
+# Sample Linker Command File for CodeWarrior for ColdFire
+
+KEEP_SECTION {.vectortable}
+
+# Memory ranges	
+
+MEMORY {
+   code        (RX)  : ORIGIN = 0xE0000000, LENGTH = 0x00200000
+}
+
+SECTIONS {
+ 
+#BaS Basis adresse
+	___Bas_base		  = 0x1FE00000;
+
+# Board Memory map definitions from linker command files:
+# __SDRAM,__SDRAM_SIZE, __CODE_FLASH, __CODE_FLASH_SIZE 
+# linker symbols must be defined in the linker command file.
+
+#Init CS0 (BootFLASH @ E000_0000 - E07F_FFFF 8Mbytes)
+   ___BOOT_FLASH           = 0xE0000000;
+   ___BOOT_FLASH_SIZE      = 0x00800000;
+#SDRAM Initialization @ 0000_0000 - 1FFF_FFFF 512Mbytes	
+   ___SDRAM                = 0x00000000;
+   ___SDRAM_SIZE           = 0x20000000;
+   
+#VIDEO RAM BASIS
+   ___VRAM                = 0x60000000;
+
+# MCF5475 Derivative Memory map definitions from linker command files:
+# __MBAR, __MMUBAR, __RAMBAR0, __RAMBAR0_SIZE, __RAMBAR1, __RAMBAR1_SIZE
+# linker symbols must be defined in the linker command file.
+
+# Memory mapped registers
+   ___MBAR                 = 0xFF000000;
+   ___MMUBAR               = 0xFF040000;
+# 4KB on-chip Core SRAM0: -> exception table and exception stack
+   ___RAMBAR0              = 0xFF100000;
+   ___RAMBAR0_SIZE         = 0x00001000;
+
+   ___SUP_SP = ___RAMBAR0 + ___RAMBAR0_SIZE - 4;
+   
+# 4KB on-chip Core SRAM1: -> modified code
+   ___RAMBAR1              = 0xFF101000;
+   ___RAMBAR1_SIZE         = 0x00001000;
+
+# Systemveriablem:******************************************
+# RAMBAR0 0 bis 0x7FF -> exception vectoren
+_rt_mod    = ___RAMBAR0 + 0x800;   
+_rt_ssp    = ___RAMBAR0 + 0x804;   
+_rt_usp    = ___RAMBAR0 + 0x808;   
+_rt_vbr    = ___RAMBAR0 + 0x80C;  	# (8)01 
+_rt_cacr   = ___RAMBAR0 + 0x810;   	# 002
+_rt_asid   = ___RAMBAR0 + 0x814;   	# 003
+_rt_acr0   = ___RAMBAR0 + 0x818;   	# 004
+_rt_acr1   = ___RAMBAR0 + 0x81c;   	# 005
+_rt_acr2   = ___RAMBAR0 + 0x820;   	# 006
+_rt_acr3   = ___RAMBAR0 + 0x824;   	# 007
+_rt_mmubar = ___RAMBAR0 + 0x828;	# 008
+_rt_sr     = ___RAMBAR0 + 0x82c;   
+_d0_save   = ___RAMBAR0 + 0x830;
+_a7_save   = ___RAMBAR0 + 0x834;
+_video_tlb = ___RAMBAR0 + 0x838;
+_video_sbt = ___RAMBAR0 + 0x83C;
+_rt_mbar   = ___RAMBAR0 + 0x844;   	# (c)0f
+#***********************************************************
+
+# 32KB on-chip System SRAM
+   ___SYS_SRAM             = 0xFF010000;
+   ___SYS_SRAM_SIZE        = 0x00008000;
+
+  .code	    : {} > code		
+
+	.text :
+	{
+		startcf.c(.text)
+		sysinit.c(.text)
+		BaS.c(.text)
+		sd_card.c(.text)
+		mmu.s(.text)
+		exceptions.s(.text)
+		supervisor.s(.text)
+		ewf.s(.text)
+		illegal_instruction.s(.text)
+		last.c(.text)
+	} >> code
+
+}
\ No newline at end of file
diff --git a/firebeeV1/sources/BaS.c b/firebeeV1/sources/BaS.c
new file mode 100644
index 0000000..2b2699d
--- /dev/null
+++ b/firebeeV1/sources/BaS.c
@@ -0,0 +1,287 @@
+/*
+ * BaS
+ *
+ */
+
+
+#include "MCF5475.h"
+#include "startcf.h"
+
+extern unsigned long far __SP_AFTER_RESET[];
+extern unsigned long far __Bas_base[];
+
+	/* imported routines */
+extern int mmu_init();
+extern int mmutr_miss();
+extern int vec_init();
+extern int illegal_table_make();
+extern int cf68k_initialize();
+
+/********************************************************************/
+	/* warte_routinen /*
+********************************************************************/
+
+void warte_10ms(void)
+{
+	asm
+	{
+warte_10ms:
+		move.l		d0,-(sp) 		
+  		move.l		MCF_SLT0_SCNT,d0
+  		sub.l		#1320000,d0
+ warte_d6:
+		cmp.l		MCF_SLT0_SCNT,d0
+		bcs			warte_d6
+		move.l		(sp)+,d0
+	}
+}
+
+void warte_1ms(void)
+{
+	asm
+	{
+warte_1ms:
+		move.l		d0,-(sp) 		
+  		move.l		MCF_SLT0_SCNT,d0
+  		sub.l		#132000,d0
+ warte_d6:
+		cmp.l		MCF_SLT0_SCNT,d0
+		bcs			warte_d6
+		move.l		(sp)+,d0
+	}
+}
+
+void warte_100us(void)
+{
+	asm
+	{
+ warte_100us:
+		move.l		d0,-(sp) 		
+  		move.l		MCF_SLT0_SCNT,d0
+  		sub.l		#13200,d0
+ warte_d6:
+		cmp.l		MCF_SLT0_SCNT,d0
+		bcs			warte_d6
+		move.l		(sp)+,d0
+	}
+}
+
+void warte_50us(void)
+{
+	asm
+	{
+warte_50us:
+		move.l		d0,-(sp) 		
+  		move.l		MCF_SLT0_SCNT,d0
+  		sub.l		#6600,d0
+ warte_d6:
+		cmp.l		MCF_SLT0_SCNT,d0
+		bcs			warte_d6
+		move.l		(sp)+,d0
+	}
+}
+void warte_10us(void)
+{
+	asm
+	{
+warte_10us:
+		move.l		d0,-(sp) 		
+  		move.l		MCF_SLT0_SCNT,d0
+  		sub.l		#1320,d0
+ warte_d6:
+		cmp.l		MCF_SLT0_SCNT,d0
+		bcs			warte_d6
+		move.l		(sp)+,d0
+	}
+}
+
+void warte_1us(void)
+{
+	asm
+	{
+warte_1us:
+		move.l		d0,-(sp) 		
+  		move.l		MCF_SLT0_SCNT,d0
+  		sub.l		#132,d0
+ warte_d6:
+		cmp.l		MCF_SLT0_SCNT,d0
+		bcs			warte_d6
+		move.l		(sp)+,d0
+	}
+}
+
+/********************************************************************/
+void BaS(void)
+{
+		int		az_sectors;
+		int		sd_status,i;
+
+		az_sectors = sd_card_init();
+		
+		if(az_sectors>0)
+		{
+			sd_card_idle();
+		}
+	
+	asm
+{
+		move.b	DIP_SWITCH,d0				// dip schalter adresse
+		btst.b	#6,d0
+		beq		firetos_kopieren
+		lea		MCF_PSC0_PSCTB_8BIT,a6
+		lea		MCF_PSC3_PSCTB_8BIT,a3
+		lea		MCF_PSC3_PSCRB_8BIT,a4
+		lea		MCF_PSC3_PSCRFCNT,a5
+		move.l 	#'ACPF',(a3)					// SEND SYNC MARKE, MCF BEREIT
+		bsr 	warte_10ms
+		move.l 	#'PIC ',(a6)
+		move.b 	(a4),d0
+		move.b	d0,(a6)
+		move.b 	(a4),d1
+		move.b	d1,(a6)
+		move.b 	(a4),d2
+		move.b	d2,(a6)
+		move.l	#0x0a0d,(a6)
+		move.b 	#0x01,(a3)						// RTC DATEN ANFORDERN
+// TOS kopieren
+		lea		0x00e00000,a0
+		lea		0xe0600000,a1					// default tos
+		lea		0xe0700000,a2					// 1MB
+		move.b	DIP_SWITCH,d0					// dip schalter adresse
+		btst.b	#6,d0
+		bne		cptos_loop
+firetos_kopieren:
+		lea		0x00e00000,a0
+		lea		0xe0400000,a1
+		lea		0xe0500000,a2					// 1MB
+cptos_loop:
+		move.l	(a1)+,(a0)+
+		cmp.l	a2,a1
+		blt		cptos_loop
+/***************************************************************/
+/*   div inits       
+/***************************************************************/
+div_inits:
+		move.b	DIP_SWITCH,d0				// dip schalter adresse
+		btst.b	#6,d0
+		beq		video_setup
+// rtc daten, mmu set, etc nur wenn switch 6 = off
+		lea		0xffff8961,a0
+		clr.l	d1	
+		moveq	#64,d2
+		move.b	(a4),d0
+		cmp.b	#0x81,d0
+		bne		not_rtc	
+loop_sr:
+		move.b	(a4),d0
+		move.b  d1,(a0)
+		move.b	d0,2(a0)
+		addq.l	#1,d1
+		cmp.b	d1,d2
+		bne		loop_sr
+		
+		move.b	#63,(a0)
+		move.b	2(a0),d0
+		add		#1,d0
+		move.b	d0,2(a0)
+not_rtc:
+		bsr		mmu_init
+		bsr		vec_init
+		bsr		illegal_table_make
+		
+// interrupts
+		clr.l	0xf0010004					// disable all interrupts
+		lea		MCF_EPORT_EPPAR,a0
+		move.w	#0xaaa8,(a0)				// falling edge all,
+
+// timer 0 on mit int -> video change -------------------------------------------
+		move.l	#MCF_GPT_GMS_ICT(1)|MCF_GPT_GMS_IEN|MCF_GPT_GMS_TMS(1),d0	//caputre mit int on rising edge
+		move.l	d0,MCF_GPT0_GMS
+		moveq.l	#0x3f,d0					// max prority interrutp
+ 		move.b	d0,MCF_INTC_ICR62			// setzen
+// -------------------------------------------------
+		move.b	#0xfe,d0
+		move.b	d0,0xf0010004				// enable int 1-7
+		nop
+		lea		MCF_EPORT_EPIER,a0
+		move.b	#0xfe,(a0)					// int 1-7 on
+		nop
+		lea		MCF_EPORT_EPFR,a0
+		move.b	#0xff,(a0)					// alle pending interrupts löschen
+		nop
+		lea		MCF_INTC_IMRL,a0
+		move.l	#0xFFFFFF00,(a0)			// int 1-7 on
+		lea		MCF_INTC_IMRH,a0
+		move.l	#0xBFFFFFFE,(a0)			// psc3 and timer 0 int on
+
+		move.l	#MCF_MMU_MMUCR_EN,d0
+  		move.l	d0,MCF_MMU_MMUCR			// mmu on
+		nop
+		nop
+/********************************************************************/
+/* IDE reset
+/********************************************************************/
+		lea		0xffff8802,a0
+		move.b	#14,-2(a0)
+		move.b	#0x80,(a0)
+		bsr		warte_1ms
+		clr.b	(a0)
+/********************************************************************/
+/* video setup
+/********************************************************************/
+video_setup:
+		lea		0xf0000410,a0
+// 25MHz
+ 		move.l	#0x032002ba,(a0)+			// horizontal 640x480
+		move.l	#0x020c020a,(a0)+			// vertikal 640x480
+		move.l	#0x0190015d,(a0)+			// horizontal 320x240
+		move.l	#0x020C020A,(a0)+			// vertikal 320x240 */
+/*
+//  32MHz
+		move.l	#0x037002ba,(a0)+			// horizontal 640x480
+		move.l	#0x020d020a,(a0)+			// vertikal 640x480
+		move.l	#0x02A001e0,(a0)+			// horizontal 320x240
+		move.l	#0x05a00160,(a0)+			// vertikal 320x240 
+*/
+		lea		-0x20(a0),a0
+		move.l	#0x01070002,(a0)			// fifo on, refresh on, ddrcs und cke on, video dac on,
+/********************************************************************/
+/* memory setup
+/********************************************************************/
+ 		lea		0x400,a0
+		lea		0x800,a1
+mem_clr_loop:
+		clr.l	(a0)+
+		clr.l	(a0)+
+		clr.l	(a0)+
+		clr.l	(a0)+
+		cmp.l	a0,a1
+		bgt		mem_clr_loop
+
+		moveq	#0x48,d0
+		move.b	d0,0xffff8007
+// stram
+		move.l	#0xe00000,d0				// ende stram
+		move.l	d0,0x42e
+		move.l	#0x752019f3,d0				// memvalid
+		move.l	d0,0x420
+		move.l	#0x237698aa,d0				// memval2
+		move.l	d0,0x43a
+		move.l	#0x5555aaaa,d0				// memval3
+		move.l	d0,0x51a
+// ttram
+   		move.l	#__Bas_base,d0				// ende ttram		
+  		move.l	d0,0x5a4
+  		move.l	#0x1357bd13,d0				// ramvalid
+   		move.l	d0,0x5a8
+   		
+// test auf protect mode ---------------------
+		move.b	DIP_SWITCH,d0
+		btst	#7,d0 
+		beq		no_protect					// nein->
+		move.w	#0x0700,sr
+no_protect:
+		jmp		0xe00030
+
+}
+}
diff --git a/firebeeV1/sources/div.s b/firebeeV1/sources/div.s
new file mode 100644
index 0000000..f5f151c
--- /dev/null
+++ b/firebeeV1/sources/div.s
@@ -0,0 +1,1326 @@
+
+/********************************************************************/
+// sd card
+/********************************************************************/
+#define	dspi_dtar0	0x0c
+#define	dspi_dsr	0x2c	
+#define	dspi_dtfr	0x34	
+#define	dspi_drfr	0x38
+	
+sd_test:
+		lea			0x40000,a5					// basis addresse
+		move.l		#0x1fffffff,d0				// normal dspi
+		move.l		d0,MCF_PAD_PAR_DSPI
+		lea			MCF_DSPI_DMCR,a0
+		move.l		#0x802d3c00,(a0)			// 8 bit 4MHz
+		move.l		#0x38551120,d0
+		move.l		d0,dspi_dtar0(a0)				// 
+		move.l		#0x08200000,d4				// tx vorbesetzen
+		mov3q.l		#-1,dspi_dsr(a0)
+		
+		move.b		#0xc0,(a0)			// 8 bit 4MHz
+		bsr			warte_1ms
+		move.b		#0x80,(a0)			// 8 bit 4MHz
+// sd idle
+		moveq.l		#100,d6				// 100 versuche
+sd_idle:
+		bsr			sd_16clk
+		move.b		#0x40,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#0x95,d4
+		bsr			sd_com
+		
+		bsr			sd_get_status
+		cmp.b		#0x01,d5
+		beq			wait_of_aktiv
+		subq.l		#1,d6
+		beq			sd_not
+		bra			sd_idle
+				
+// acdm 41
+wait_of_aktiv:
+		bsr			sd_16clk
+		move.b		#0x77,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#0x01,d4
+		bsr			sd_com
+
+		bsr			sd_get_status
+		cmp.b		#0x05,d5
+		beq			wait_of_aktiv	
+
+
+wait_of_aktiv2:
+		bsr			sd_16clk
+		move.b		#0x69,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#0x02,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#0x01,d4
+		bsr			sd_com
+
+		bsr			sd_get_status
+		tst.b		d5
+		beq			sd_init_ok
+		cmp.b		#0x05,d5
+		beq			wait_of_aktiv2	
+		bra			wait_of_aktiv
+
+sd_init_ok:
+
+// blockgrösse 512byt
+sd_bg:
+		bsr			sd_16clk
+		move.b		#0x50,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#02,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#0x01,d4
+		bsr			sd_com
+		
+		bsr			sd_get_status
+		tst.b		d5
+		bne			sd_bg
+		
+// read block
+sd_rb:
+		bsr			sd_16clk
+		move.b		#0x51,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#0x08,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#0x01,d4
+		bsr			sd_com
+		
+		bsr			sd_get_status
+		tst.b		d5
+		bne			sd_rb
+
+		move.l		a5,a4				// adresse setzen
+		bsr			sd_rcv_block
+
+// write block
+sd_wb:
+		bsr			sd_16clk
+		move.b		#0x58,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#0x08,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#0x01,d4
+		bsr			sd_com
+		
+		bsr			sd_get_status
+		tst.b		d5
+		bne			sd_wb
+		
+		bsr			sd_send_block		
+
+// read block 2
+sd_rb2:
+		bsr			sd_16clk
+		move.b		#0x51,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#0x08,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#0x01,d4
+		bsr			sd_com
+		
+		bsr			sd_get_status
+		tst.b		d5
+		bne			sd_rb
+
+		bsr			sd_rcv_block
+		clr.l		d0
+		halt
+		halt
+		rts
+// status holen -------------------------------
+sd_not:
+		moveq.l		#-1,d0
+		halt
+		halt
+		rts
+
+// status holen -------------------------------
+sd_get_status:
+		move.b		#0xff,d4
+		bsr			sd_com
+		cmp.b		#0xff,d5
+		beq			sd_get_status
+		rts
+// byt senden und holen ---------------------		
+sd_com:
+		move.l		d4,dspi_dtfr(a0)
+wait_auf_complett:
+		btst.b		#7,dspi_dsr(a0)
+		beq			wait_auf_complett
+		move.l		dspi_drfr(a0),d5
+		mov3q.l		#-1,dspi_dsr(a0)		// clr status register
+		rts
+
+// daten holen ----------------------------
+sd_rcv_block:
+		move.l		#512,d3				// 512 byts + 2 ccr byts
+		move.b		#0xff,d4
+sd_rcv_rb_w:		
+		bsr			sd_get_status 
+		cmp.b		#0xfe,d5			// daten bereit?
+		bne			sd_rcv_rb_w		// nein->
+sd_rcv_rd_rb:
+		bsr			sd_com
+		move.b		d5,(a4)+
+		subq.l		#1,d3
+		bne			sd_rcv_rd_rb
+// crc holen
+		bsr			sd_com				// crc 1.byt
+		move.b		d5,d1
+		bsr			sd_com				// crc 2.byt
+		move.b		d5,d2
+		rts
+
+// daten schreiben -----------------------
+sd_send_block:
+		move.l		#512,d3		
+		move.b		#0xfe,d4			// start token
+		bsr			sd_com				// senden
+sd_send_wr_wb:
+		move.b		#0xc7,d4			// data
+		bsr			sd_com				// senden
+		subq.l		#1,d3
+		bne			sd_send_wr_wb	
+// send crc
+		move.b		d1,d4			
+		bsr			sd_com				// crc 1.byt
+		move.b		d2,d4
+		bsr			sd_com				// crc 2.byt
+sd_send_wr_ww:
+		bsr			sd_get_status
+		and.l		#0x1f,d5
+		cmp.b		#0x05,d5
+		bne			sd_send_wr_ww
+sd_sendwait_wr_f:
+		bsr			sd_com
+		cmp.b		#0xff,d5
+		bne			sd_sendwait_wr_f
+		rts
+// clock einfügen -------------------------------------
+sd_16clk:
+		move.b		#0xc0,(a0)			// 8 bit 4MHz
+		nop
+		move.b		#0x80,(a0)			// 8 bit 4MHz
+		rts
+// cdm 58
+read_ocr:
+		bsr			sd_16clk
+		move.b		#0x7a,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#0x01,d4
+		bsr			sd_com
+		move.b		#0xaa,d4
+		bsr			sd_com
+		move.b		#0x87,d4
+		bsr			sd_com
+		
+		bsr			sd_get_status
+
+		halt
+		
+		move.l		#'Ver1',d6
+		cmp.b		#5,d5
+		beq			sd_v1
+		cmp.b		#1,d5
+		bne			read_csd
+		
+		move.b		#0xff,d4
+		bsr			sd_com
+		move.b		d5,d0
+		bsr			sd_com
+		move.b		d5,d1
+		bsr			sd_com
+		move.b		d5,d2
+		bsr			sd_com
+/******************************************/
+#include "MCF5475.h"
+#include "startcf.h"
+
+extern unsigned long far __SP_AFTER_RESET[];
+extern unsigned long far __Bas_base[];
+
+	/* imported routines */
+//extern int warten_20ms();
+//extern int warten_200us();
+//extern int warten_10us();
+ 
+/********************************************************************/
+void asm sd_test(void)
+{
+		clr.w		MCF_PAD_PAR_DSPI
+		lea			MCF_GPIO_PPDSDR_DSPI,a2		// data in
+		lea			MCF_GPIO_PODR_DSPI,a1		// data out
+		move.b		#0x00,(a1)					// alle auf 0
+		lea			MCF_GPIO_PDDR_DSPI,a0
+		move.b		#0x7d,(a0)					// din = input rest output
+		
+		bsr			warten_20ms
+		
+		move.b		#0x7f,(a1)					// alle auf 1
+
+		bsr			sd_16clk
+		bsr			sd_16clk
+		bsr			sd_16clk
+		bsr			sd_16clk
+		bsr			sd_16clk
+		bsr			sd_16clk
+		bsr			sd_16clk
+		bsr			sd_16clk
+// sd idle
+sd_idle:
+		bsr			sd_16clk
+		moveq		#0x40,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#0x95,d4
+		bsr			sd_com
+		
+		bsr			sd_receive
+
+		cmp.b		#0x05,d5
+		beq			sd_test
+		cmp.b		#0x01,d5
+		beq			wait_of_aktiv
+		cmp.b		#0x04,d5
+		beq			sd_init_ok
+		cmp.b		#0x00,d5
+		beq			sd_init_ok
+		bra			sd_idle
+				
+// acdm 41
+wait_of_aktiv:
+		bsr			sd_16clk
+
+		moveq		#0x77,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#0x01,d4
+		bsr			sd_com
+
+		bsr			sd_receive
+
+		bsr			sd_16clk
+
+		move.l		#0xff,d6
+		moveq		#0x69,d4
+		bsr			sd_com
+		and			d5,d6
+		moveq		#00,d4
+		bsr			sd_com
+		and			d5,d6
+		moveq		#00,d4
+		bsr			sd_com
+		and			d5,d6
+		moveq		#0x02,d4
+		bsr			sd_com
+		and			d5,d6
+		moveq		#00,d4
+		bsr			sd_com
+		and			d5,d6
+		moveq		#0x01,d4
+		bsr			sd_com
+		and			d5,d6
+
+		bsr			sd_receive
+				
+		cmp.b		#0x00,d5
+		beq			sd_init_ok
+		cmp.b		#0x05,d5
+		beq			sd_test	
+		bra			wait_of_aktiv
+
+sd_init_ok:
+
+// blockgrösse 512byt
+sd_bg:
+		bsr			sd_16clk
+		moveq		#0x50,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#02,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#0x01,d4
+		bsr			sd_com
+		
+		bsr			sd_receive
+
+		cmp.b		#0x00,d5
+		bne			sd_bg
+
+// read block
+sd_rb:
+		bsr			sd_16clk
+		moveq		#0x51,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#0x08,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#0x01,d4
+		bsr			sd_com
+		
+		bsr			sd_receive
+
+		cmp.b		#0x00,d5
+		bne			sd_rb
+		
+		lea			0xc00000,a4
+		move.l		#513,d7
+rd_rb:
+		bsr			sd_receive
+		move.b		d5,(a4)+
+		subq.l		#1,d7
+		bne			rd_rb	
+
+// write block
+sd_wb:
+		bsr			sd_16clk
+		moveq		#0x58,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#0x08,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#0x01,d4
+		bsr			sd_com
+		
+		bsr			sd_receive
+
+		cmp.b		#0x00,d5
+		bne			sd_wb
+		
+		lea			0xc00000,a4
+		move.l		#513,d7
+		moveq.l		#0x66,d4
+wr_wb:
+		bsr			sd_com
+//		subq.l		#1,d4
+		moveq		#0x66,d4
+		subq.l		#1,d7
+		bne			wr_wb	
+
+		bsr			sd_receive
+		
+wr_wb_el:	
+		moveq		#0xff,d4
+		bsr			sd_com
+		cmp.b		#0xff,d5
+		bne			wr_wb_el
+		
+
+// read block 2
+sd_rb2:
+		bsr			sd_16clk
+		moveq		#0x51,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#0x08,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#0x01,d4
+		bsr			sd_com
+		
+		bsr			sd_receive
+
+		cmp.b		#0x00,d5
+		bne			sd_rb2
+		
+		lea			0xc00400,a4
+		move.l		#513,d7
+rd_rb2:
+		bsr			sd_receive
+		move.b		d5,(a4)+
+		subq.l		#1,d7
+		bne			rd_rb2	
+
+
+		nop
+		nop
+
+		rts
+		
+sd_receive:
+		moveq		#0xff,d4
+		bsr			sd_com
+		cmp.b		#0xff,d5
+		beq			sd_receive
+		rts
+		
+sd_com:
+		bclr.b		#6,(a1)
+sd_comb:
+		bsr			warten_10us
+		moveq		#7,d2
+		clr.l		d5
+sd_com_loop:
+		btst		d2,d4
+		beq			sd_com2
+		bset.b		#0,(a1)
+		bra			sd_com2_1
+sd_com2:
+		bclr.b		#0,(a1)
+sd_com2_1:
+		bsr			sd_clk
+		and.l		#0x02,d3
+		beq			sd_com3
+		bset.b		d2,d5
+sd_com3:
+		subq.l		#1,d2
+		bge			sd_com_loop
+		bsr			warten_10us
+		bset.b		#6,(a1)
+		bset.b		#0,(a1)
+		bsr			warten_200us
+		rts
+sd_clk:
+		tst.b		0xfffff700
+		tst.b		0xfffff700
+		bset.b		#2,(a1)
+		tst.b		0xfffff700
+		tst.b		0xfffff700
+		move.b		(a2),d3
+		tst.b		0xfffff700
+		bclr.b		#2,(a1)
+		rts
+
+sd_15clk:
+		move		#15,d0
+		bra			sd_16clk
+sd_16clk:
+		moveq		#16,d0
+sd_16clk1:
+		bsr			sd_clk
+		subq.l		#1,d0
+		bne			sd_16clk1
+		bsr			warten_10us
+		rts
+// warteschleife ca. 20ms  
+warten_20ms:  		
+		move.l		a0,-(sp)
+		move.l		d6,-(sp) 		
+		move.l		d1,-(sp) 		
+		move.l		d0,-(sp) 		
+  		lea			MCF_SLT0_SCNT,a0
+  		move.l		(a0),d0
+  		move.l		#700000,d6
+  		bra			warten_loop
+// warteschleife ca. 200us  
+warten_200us: 
+		move.l		a0,-(sp)
+		move.l		d6,-(sp) 		
+		move.l		d1,-(sp) 		
+		move.l		d0,-(sp) 		
+  		lea			MCF_SLT0_SCNT,a0
+  		move.l		(a0),d0
+  		move.l		#7000,d6
+  		bra			warten_loop
+// warteschleife ca. 10us  
+warten_10us:  		
+		move.l		a0,-(sp)
+		move.l		d6,-(sp) 		
+		move.l		d1,-(sp) 		
+		move.l		d0,-(sp) 		
+  		lea			MCF_SLT0_SCNT,a0
+  		move.l		(a0),d0
+  		move.l		#333,d6
+warten_loop:
+		move.l		(a0),d1
+		sub.l		d0,d1
+		add.l		d6,d1
+		bpl			warten_loop
+		move.l		(sp)+,d0
+		move.l		(sp)+,d1
+		move.l		(sp)+,d6
+		move.l		(sp)+,a0
+		rts;
+}
+
+
+/**************************************************/
+void asm ide_test(void)
+{
+		lea			MCF_PAD_PAR_DSPI,a0
+		move.w		#0x1fff,(a0)
+		lea			MCF_DSPI_DCTAR0,a0
+		move.l		#0x38a644e4,(a0)
+		lea			MCF_DSPI_DMCR,a0
+		move.l		#0x802d3c00,(a0)
+		clr.l		MCF_DSPI_DTCR
+		bsr			warten_20ms
+		lea			MCF_DSPI_DTFR,a0
+		lea			MCF_DSPI_DRFR,a1
+
+		moveq		#10,d0		
+sd_reset:
+		move.l		#0x000100ff,(a0)
+		bsr			warten_20ms
+		and.l		(a1),d0
+		subq.l		#1,d0
+		bne			sd_reset
+		
+		moveq		#10,d1
+sd_loop1:
+		bsr			warten_20ms
+		moveq		#-1,d0		
+// cmd 0 set to idle
+		move.l		#0x00200040,(a0)
+		bsr			warten_20ms
+		and.l		(a1),d0
+		move.l		#0x00200000,(a0)
+		bsr			warten_20ms
+		and.l		(a1),d0
+		move.l		#0x00200000,(a0)
+		bsr			warten_20ms
+		and.l		(a1),d0
+		move.l		#0x00200000,(a0)
+		bsr			warten_20ms
+		and.l		(a1),d0
+		move.l		#0x00200000,(a0)
+		bsr			warten_20ms
+		and.l		(a1),d0
+		move.l		#0x00200095,(a0)
+		bsr			warten_20ms
+		and.l		(a1),d0
+		cmp.w		#0x0001,d0
+		beq			sd_loop2
+		subq.l		#1,d1
+		bne			sd_loop1
+		moveq		#10,d1
+		bra			sd_test
+sd_loop2:
+		moveq		#-1,d0		
+// cmd 41		
+		move.l		#0x00200069,(a0)
+		bsr			warten_20ms
+		and.l		(a1),d0
+		move.l		#0x00200000,(a0)
+		bsr			warten_20ms
+		and.l		(a1),d0
+		move.l		#0x00200000,(a0)
+		bsr			warten_20ms
+		and.l		(a1),d0
+		move.l		#0x00200000,(a0)
+		bsr			warten_20ms
+		and.l		(a1),d0
+		move.l		#0x00200000,(a0)
+		bsr			warten_20ms
+		and.l		(a1),d0
+		move.l		#0x00200001,(a0)
+		bsr			warten_20ms
+		and.l		(a1),d0
+		tst.w		d0
+		bne			sd_loop2
+
+		nop
+		nop
+/********************************************************************/
+#define		cmd_reg		(0x1d)
+#define		status_reg	(0x1d)
+#define		seccnt		(0x09)
+
+ide_test:
+		lea			0xfff00040,a0
+		lea			0xc00000,a1
+		move.b		#0xec,cmd_reg(a0)		//identify devcie cmd
+		bsr			wait_int
+		bsr			ds_rx
+// read sector normal		
+		move.b		#1,seccnt(a0)			// 1 sector
+		move.b		#0x20,cmd_reg(a0)		// read cmd
+		bsr			wait_int
+		bsr			ds_rx
+
+// write testpattern sector
+		move.b		#1,seccnt(a0)			// 1 sector
+		move.b		#0x30,cmd_reg(a0)		// write cmd
+		bsr			drq_wait
+// write pattern
+		move.l		#256,d0
+ide_test_loop3:		
+		move.w		#0xa55a,(a0)
+		subq.l		#1,d0
+		bne			ide_test_loop3
+		bsr			wait_int
+// read testpattern sector
+		move.b		#1,seccnt(a0)			// 1 sector
+		move.b		#0x20,cmd_reg(a0)		// read
+		bsr			wait_int
+		bsr			ds_rx
+// sector restauriern
+		move.b		#1,seccnt(a0)			// 1 sector
+		move.b		#0x30,cmd_reg(a0)		// write
+		lea			-0x400(a1),a1			// vorletzer
+		bsr			drq_wait
+		bsr			ds_tx
+		bsr			wait_int
+// fertig und zurück		
+		nop
+		rts
+// wait auf int
+wait_int:
+		move.b		0xfffffa01,d0
+		btst.b		#5,d0
+		bne			wait_int
+		move.b		status_reg(a0),d0
+		rts
+// wait auf drq
+drq_wait:
+		move.b		status_reg(a0),d0
+		btst		#3,d0
+		beq			drq_wait
+		rts
+
+// 1 sector lesen word
+ds_rx:
+		move.l		#256,d0
+ds_rx_loop:		
+		move.w		(a0),(a1)+
+		subq.l		#1,d0
+		bne			ds_rx_loop
+		rts
+// 1 sector lesen long
+ds_rxl:
+		move.l		#128,d0
+ds_rxl_loop:		
+		move.l		(a0),(a1)+
+		subq.l		#1,d0
+		bne			ds_rxl_loop
+		rts
+// 1 sector schreiben word
+ds_tx:
+		move.l		#256,d0
+ds_tx_loop:		
+		move.w		(a1)+,(a0)
+		subq.l		#1,d0
+		bne			ds_tx_loop
+		rts
+// 1 sector schreiben word
+ds_txl:
+		move.l		#128,d0
+ds_txl_loop:		
+		move.l		(a1)+,(a0)
+		subq.l		#1,d0
+		bne			ds_txl_loop
+		rts
+// warteschleife ca. 20ms  
+warten_20ms:  		
+		move.l		a0,-(sp)
+		move.l		d6,-(sp) 		
+		move.l		d1,-(sp) 		
+		move.l		d0,-(sp) 		
+  		lea			MCF_SLT0_SCNT,a0
+  		move.l		(a0),d0
+  		move.l		#700000,d6
+  		bra			warten_loop
+// warteschleife ca. 200us  
+warten_200us: 
+		move.l		a0,-(sp)
+		move.l		d6,-(sp) 		
+		move.l		d1,-(sp) 		
+		move.l		d0,-(sp) 		
+  		lea			MCF_SLT0_SCNT,a0
+  		move.l		(a0),d0
+  		move.l		#7000,d6
+  		bra			warten_loop
+// warteschleife ca. 10us  
+warten_10us:  		
+		move.l		a0,-(sp)
+		move.l		d6,-(sp) 		
+		move.l		d1,-(sp) 		
+		move.l		d0,-(sp) 		
+  		lea			MCF_SLT0_SCNT,a0
+  		move.l		(a0),d0
+  		move.l		#333,d6
+warten_loop:
+		move.l		(a0),d1
+		sub.l		d0,d1
+		add.l		d6,d1
+		bpl			warten_loop
+		move.l		(sp)+,d0
+		move.l		(sp)+,d1
+		move.l		(sp)+,d6
+		move.l		(sp)+,a0
+		rts;
+}
+/********************************************************************/
+//.include "startcf.h"
+
+//.extern ___MBAR
+//#define MCF_SLT0_SCNT	___MBAR+0x908
+
+//.global ide_test
+
+.text
+/********************************************************************/
+// sd card
+/********************************************************************/
+sd_test:
+		lea			0x40000,a5					// basis addresse
+		clr.w		MCF_PAD_PAR_DSPI
+		lea			MCF_GPIO_PPDSDR_DSPI,a2		// data in
+		lea			MCF_GPIO_PODR_DSPI,a1		// data out
+		move.b		#0x00,(a1)					// alle auf 0
+		lea			MCF_GPIO_PDDR_DSPI,a0
+		move.b		#0x7d,(a0)					// din = input rest output
+		
+		bsr			warten_20ms
+		
+		move.b		#0x7f,(a1)					// alle auf 1
+
+		bsr			sd_16clk
+		
+// sd idle
+sd_idle:
+		bsr			sd_16clk
+		moveq		#0x40,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#0x95,d4
+		bsr			sd_com
+		
+		bsr			sd_receive
+		
+		cmp.b		#0x05,d5
+		beq			sd_test
+		cmp.b		#0x01,d5
+		beq			wait_of_aktiv
+		cmp.b		#0x04,d5
+		beq			sd_init_ok
+		cmp.b		#0x00,d5
+		beq			sd_init_ok
+		bra			sd_idle
+				
+// acdm 41
+wait_of_aktiv:
+		bsr			sd_16clk
+
+		moveq		#0x77,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#0x01,d4
+		bsr			sd_com
+
+		bsr			sd_receive
+
+		bsr			sd_16clk
+
+		move.l		#0xff,d6
+		moveq		#0x69,d4
+		bsr			sd_com
+		and			d5,d6
+		moveq		#00,d4
+		bsr			sd_com
+		and			d5,d6
+		moveq		#00,d4
+		bsr			sd_com
+		and			d5,d6
+		moveq		#0x02,d4
+		bsr			sd_com
+		and			d5,d6
+		moveq		#00,d4
+		bsr			sd_com
+		and			d5,d6
+		moveq		#0x01,d4
+		bsr			sd_com
+		and			d5,d6
+
+		bsr			sd_receive
+				
+		cmp.b		#0x00,d5
+		beq			sd_init_ok
+		cmp.b		#0x05,d5
+		beq			sd_test	
+		bra			wait_of_aktiv
+
+sd_init_ok:
+
+// blockgrösse 512byt
+sd_bg:
+		bsr			sd_16clk
+		moveq		#0x50,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#02,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#0x01,d4
+		bsr			sd_com
+		
+		bsr			sd_receive
+
+		cmp.b		#0x00,d5
+		bne			sd_bg
+
+// read block
+sd_rb:
+		bsr			sd_16clk
+		moveq		#0x51,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#0x08,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#0x01,d4
+		bsr			sd_com
+		
+		bsr			sd_receive
+
+		cmp.b		#0x00,d5
+		bne			sd_rb
+		
+		move.l		a5,a4
+		move.l		#513,d7
+rd_rb:
+		bsr			sd_receive
+		move.b		d5,(a4)+
+		subq.l		#1,d7
+		bne			rd_rb	
+		
+// write block
+sd_wb:
+		bsr			sd_16clk
+		moveq		#0x58,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#0x08,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#0x01,d4
+		bsr			sd_com
+		
+		bsr			sd_receive
+
+		cmp.b		#0x00,d5
+		bne			sd_wb
+		
+		move.l		#513,d7
+		moveq.l		#0xbb,d4
+wr_wb:
+		bsr			sd_com
+//		subq.l		#1,d4
+		moveq		#0xbb,d4
+		subq.l		#1,d7
+		bne			wr_wb	
+
+		bsr			sd_receive
+		
+wr_wb_el:	
+		moveq		#0xff,d4
+		bsr			sd_com
+		cmp.b		#0xff,d5
+		bne			wr_wb_el
+		
+
+// read block 2
+sd_rb2:
+		bsr			sd_16clk
+		moveq		#0x51,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#0x08,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#0x01,d4
+		bsr			sd_com
+		
+		bsr			sd_receive
+
+		cmp.b		#0x00,d5
+		bne			sd_rb2
+		
+		move.l		#513,d7
+rd_rb2:
+		bsr			sd_receive
+		move.b		d5,(a4)+
+		subq.l		#1,d7
+		bne			rd_rb2	
+
+halt
+halt
+		nop
+		nop
+
+		rts
+		
+sd_receive:
+		moveq		#0xff,d4
+		bsr			sd_com
+		cmp.b		#0xff,d5
+		beq			sd_receive
+		rts
+		
+sd_com:
+		bclr.b		#6,(a1)			// nCS=0
+sd_comb:
+		bsr			warten_10us
+		moveq		#7,d2
+		clr.l		d5
+sd_com_loop:
+		bclr.b		#0,(a1)			// default 0 bit senden
+		btst		d2,d4			// ist 0?
+		beq			sd_com2			// ja->
+		bset.b		#0,(a1)			// sonst auf 1
+sd_com2:
+		bsr			sd_clk			// clocken
+		and.l		#0x02,d3
+		beq			sd_com3
+		bset.b		d2,d5
+sd_com3:
+		subq.l		#1,d2
+		bge			sd_com_loop
+		bsr			warten_10us
+		bset.b		#6,(a1)			// nCS=1
+		bset.b		#0,(a1)			// daten = 0
+		bsr			warten_200us
+		rts
+// clocken
+sd_clk:
+		tst.b		0xfffff700		// wait
+		tst.b		0xfffff700
+		bset.b		#2,(a1)			// clock high
+		tst.b		0xfffff700		// wait
+		tst.b		0xfffff700		// wait
+		move.b		(a2),d3			// bit holen
+		bclr.b		#2,(a1)			// clock low
+		rts
+
+sd_16clk:
+		move.l		#160,d0
+sd_16clk1:
+		bsr			sd_clk
+		subq.l		#1,d0
+		bne			sd_16clk1
+		bsr			warten_10us
+		rts
+/********************************************************************/
+// video pll
+/********************************************************************/
+		lea		0xf0000800,a1
+
+		lea		0xf0000600,a0
+		move.l	#128,d0
+clr_pll:
+		bsr		wait_pll
+		clr.w	(a0)
+		addq.l	#4,a0
+		subq.l	#1,d0
+		bne		clr_pll
+		
+		lea		0xf0000600,a0
+		bsr		wait_pll
+		move.w	#27,0x48(a0)		// loopfilter r
+		bsr		wait_pll
+		move.w	#1,0x08(a0)			// charge pump I
+		bsr		wait_pll
+		move.w	#12,0x0(a0)			// N counter high = 12
+		bsr		wait_pll
+		move.w	#12,0x40(a0)		// N counter low = 12
+		bsr		wait_pll
+		move.w	#1,0x114(a0)		// ck1 bypass
+		bsr		wait_pll
+		move.w	#1,0x118(a0)		// ck2 bypass
+		bsr		wait_pll
+		move.w	#1,0x11c(a0)		// ck3 bypass
+		bsr		wait_pll
+		move.w	#1,0x10(a0)			// ck0 high = 1
+		bsr		wait_pll
+		move.w	#1,0x50(a0)			// ck0 low	= 1
+		
+		bsr		wait_pll
+		move.w	#1,0x144(a0)		// M odd division
+		bsr		wait_pll
+		move.w	#1,0x44(a0)			// M low = 1
+
+		bsr		wait_pll
+		move.w	#99,0x04(a0)		// M high = 100
+
+		bsr		wait_pll
+		clr.b	(a1)				// set
+
+set_pll:
+		bsr		read_pll
+		halt
+		move.w	d0,(a0)
+		bsr		wait_pll
+		clr.b	(a1)
+		bra		set_pll
+
+read_pll:
+		lea		0xf0000600,a3
+		lea		0x10000,a2
+		move.l	#128,d3
+read1_pll:
+		bsr		wait_pll
+		move.w	(a3),d1
+		bsr		wait_pll
+		move.w	(a3),(a2)
+		addq.l	#4,a3
+		addq.l	#4,a2
+		subq.l	#1,d3
+		bne		read1_pll
+		rts
+wait_pll:
+		tst.w	(a1)
+		bmi		wait_pll
+		rts
+
+/********************************************************************/
+void ide_test(void)
+/********************************************************************/
+{
+	asm
+	{
+		halt
+		lea			0xfff00000,a0
+		lea			0x80000,a1
+		move.b		#0xec,cmd_reg(a0)		//identify devcie cmd
+		bsr			wait_int
+		bsr			ds_rxl
+// read sector normal		
+		move.b		#1,seccnt(a0)			// 1 sector 0x200
+		move.b		#0x20,cmd_reg(a0)		// read cmd
+		bsr			wait_int
+		bsr			ds_rxl
+// write pattern 0x400
+		move.l		a1,a4	//a4=400
+		move.l		#256,d0
+		clr.l		d1
+ide_test_loop3:		
+		move.w		d1,(a1)+
+		addq.l		#1,d1
+		subq.l		#1,d0
+		bne			ide_test_loop3
+		move.l		a4,a1
+// write testpattern sector 0x400
+		move.b		#10,sector(a0)			// sector 10
+		move.b		#1,seccnt(a0)			// 1 sector
+		move.b		#0x30,cmd_reg(a0)		// write cmd
+		bsr			drq_wait
+		bsr			ds_txl
+		bsr			wait_int
+		move.l		a1,a2	//a2=600
+		move.l		#256,d4
+loop_rw:
+// read testpattern sector 0x600
+		move.l		a2,a1
+//		halt
+		move.b		#10,sector(a0)			// sector 10
+		move.b		#1,seccnt(a0)			// 1 sector
+		move.b		#0x20,cmd_reg(a0)		// read
+		bsr			wait_int
+		bsr			ds_rxl
+// verändere testpattern
+		move.l		a2,a1
+//		halt
+		move.l		#256,d0
+		move.l		#0x100,d1
+verae_loop:
+		move.w		(a1),d2
+		add.l		d1,d2
+		move.w		d2,(a1)+
+		subq.l		#1,d0
+		bne			verae_loop
+// write testpattern sector 0x600
+		move.l		a2,a1
+//		halt
+		move.b		#10,sector(a0)			// sector 10
+		move.b		#1,seccnt(a0)			// 1 sector
+		move.b		#0x30,cmd_reg(a0)		// write cmd
+		bsr			drq_wait
+		bsr			ds_txl
+		bsr			wait_int
+		subq.l		#1,d4
+//		bra			verae_loop
+		bne			loop_rw
+// sector vergleichen
+//		halt
+		move.l		#128,d0
+		moveq.l		#-1,d1
+verg_loop:
+		move.l		(a2)+,d2
+		cmp.l		(a4)+,d2
+		bne			error
+		subq.l		#1,d0
+		bne			verg_loop
+		clr.l		d1
+error:
+		halt
+		rts
+// sector restauriern
+		move.b		#1,seccnt(a0)			// 1 sector
+		move.b		#0x30,cmd_reg(a0)		// write
+		lea			-0x400(a1),a1			// vorletzer
+		bsr			drq_wait
+		bsr			ds_txl
+		
+		bsr			wait_int
+// fertig und zurück		
+		nop
+		rts
+// wait auf int
+wait_int:
+		move.b		0xfffffa01,d0
+		btst		#5,d0
+		bne			wait_int
+		move.b		status_reg(a0),d0
+		rts
+// wait auf drq
+drq_wait:
+		move.b		status_reg(a0),d0
+		btst		#3,d0
+		beq			drq_wait
+		rts
+
+// 1 sector lesen word
+ds_rx:
+		move.l		#256,d0
+ds_rx_loop:		
+		move.w		(a0),(a1)+
+		subq.l		#1,d0
+		bne			ds_rx_loop
+		rts
+// 1 sector lesen long
+ds_rxl:
+		move.l		#128,d0
+ds_rxl_loop:		
+		move.l		(a0),(a1)+
+		subq.l		#1,d0
+		bne			ds_rxl_loop
+		rts
+// 1 sector schreiben word
+ds_tx:
+		move.l		#256,d0
+ds_tx_loop:		
+		move.w		(a1)+,(a0)
+		subq.l		#1,d0
+		bne			ds_tx_loop
+		rts
+// 1 sector schreiben long
+ds_txl:
+		move.l		#128,d0
+ds_txl_loop:		
+		move.l		(a1)+,(a0)
+		subq.l		#1,d0
+		bne			ds_txl_loop
+		rts
+	}
+}
+/********************************************************************/
diff --git a/firebeeV1/sources/ewf.s b/firebeeV1/sources/ewf.s
new file mode 100644
index 0000000..7f5a644
--- /dev/null
+++ b/firebeeV1/sources/ewf.s
@@ -0,0 +1,1565 @@
+/*************************************************************************************************/
+// extension word format: a0 zeigt auf code, in a1 ist ay, d0/d1 wird zerstört
+//------------------------------------------------------------------------------
+
+.include	"ii_macro.h"
+
+.global	ewf
+//-----------------------------------------------------------
+.text
+ewferr:
+	nop
+	halt
+	nop
+//-----------------------------------------------------------
+ewf:
+		mvz.b	(a0)+,d1							// 1. byt ewf
+		mvs.w	ewf_table-*-2(pc,d1*2),d1
+		jmp		ewf_table-*-2(pc,d1)
+ewf_table:				
+	.short		ewf_00-ewf_table,ewf_01-ewf_table,ewf_02-ewf_table,ewf_03-ewf_table
+	.short		ewf_04-ewf_table,ewf_05-ewf_table,ewf_06-ewf_table,ewf_07-ewf_table
+	.short		ewferr-ewf_table,ewf_09-ewf_table,ewferr-ewf_table,ewf_0b-ewf_table
+	.short		ewferr-ewf_table,ewf_0d-ewf_table,ewferr-ewf_table,ewf_0f-ewf_table
+	.short		ewf_10-ewf_table,ewf_11-ewf_table,ewf_12-ewf_table,ewf_13-ewf_table
+	.short		ewf_14-ewf_table,ewf_15-ewf_table,ewf_16-ewf_table,ewf_17-ewf_table
+	.short		ewferr-ewf_table,ewf_19-ewf_table,ewferr-ewf_table,ewf_1b-ewf_table
+	.short		ewferr-ewf_table,ewf_1d-ewf_table,ewferr-ewf_table,ewf_1f-ewf_table
+	.short		ewf_20-ewf_table,ewf_21-ewf_table,ewf_22-ewf_table,ewf_23-ewf_table
+	.short		ewf_24-ewf_table,ewf_25-ewf_table,ewf_26-ewf_table,ewf_27-ewf_table
+	.short		ewferr-ewf_table,ewf_29-ewf_table,ewferr-ewf_table,ewf_2b-ewf_table
+	.short		ewferr-ewf_table,ewf_2d-ewf_table,ewferr-ewf_table,ewf_2f-ewf_table
+	.short		ewf_30-ewf_table,ewf_31-ewf_table,ewf_32-ewf_table,ewf_33-ewf_table
+	.short		ewf_34-ewf_table,ewf_35-ewf_table,ewf_36-ewf_table,ewf_37-ewf_table
+	.short		ewferr-ewf_table,ewf_39-ewf_table,ewferr-ewf_table,ewf_3b-ewf_table
+	.short		ewferr-ewf_table,ewf_3d-ewf_table,ewferr-ewf_table,ewf_3f-ewf_table
+	.short		ewf_40-ewf_table,ewf_41-ewf_table,ewf_42-ewf_table,ewf_43-ewf_table
+	.short		ewf_44-ewf_table,ewf_45-ewf_table,ewf_46-ewf_table,ewf_47-ewf_table
+	.short		ewferr-ewf_table,ewf_49-ewf_table,ewferr-ewf_table,ewf_4b-ewf_table
+	.short		ewferr-ewf_table,ewf_4d-ewf_table,ewferr-ewf_table,ewf_4f-ewf_table
+	.short		ewf_50-ewf_table,ewf_51-ewf_table,ewf_52-ewf_table,ewf_53-ewf_table
+	.short		ewf_54-ewf_table,ewf_55-ewf_table,ewf_56-ewf_table,ewf_57-ewf_table
+	.short		ewferr-ewf_table,ewf_59-ewf_table,ewferr-ewf_table,ewf_5b-ewf_table
+	.short		ewferr-ewf_table,ewf_5d-ewf_table,ewferr-ewf_table,ewf_5f-ewf_table
+	.short		ewf_60-ewf_table,ewf_61-ewf_table,ewf_62-ewf_table,ewf_63-ewf_table
+	.short		ewf_64-ewf_table,ewf_65-ewf_table,ewf_66-ewf_table,ewf_67-ewf_table
+	.short		ewferr-ewf_table,ewf_69-ewf_table,ewferr-ewf_table,ewf_6b-ewf_table
+	.short		ewferr-ewf_table,ewf_6d-ewf_table,ewferr-ewf_table,ewf_6f-ewf_table
+	.short		ewf_70-ewf_table,ewf_71-ewf_table,ewf_72-ewf_table,ewf_73-ewf_table
+	.short		ewf_74-ewf_table,ewf_75-ewf_table,ewf_76-ewf_table,ewf_77-ewf_table
+	.short		ewferr-ewf_table,ewf_79-ewf_table,ewferr-ewf_table,ewf_7b-ewf_table
+	.short		ewferr-ewf_table,ewf_7d-ewf_table,ewferr-ewf_table,ewf_7f-ewf_table
+	.short		ewf_80-ewf_table,ewf_81-ewf_table,ewf_82-ewf_table,ewf_83-ewf_table
+	.short		ewf_84-ewf_table,ewf_85-ewf_table,ewf_86-ewf_table,ewf_87-ewf_table
+	.short		ewferr-ewf_table,ewf_89-ewf_table,ewferr-ewf_table,ewf_8b-ewf_table
+	.short		ewferr-ewf_table,ewf_8d-ewf_table,ewferr-ewf_table,ewf_8f-ewf_table
+	.short		ewf_90-ewf_table,ewf_91-ewf_table,ewf_92-ewf_table,ewf_93-ewf_table
+	.short		ewf_94-ewf_table,ewf_95-ewf_table,ewf_96-ewf_table,ewf_97-ewf_table
+	.short		ewferr-ewf_table,ewf_99-ewf_table,ewferr-ewf_table,ewf_9b-ewf_table
+	.short		ewferr-ewf_table,ewf_9d-ewf_table,ewferr-ewf_table,ewf_9f-ewf_table
+	.short		ewf_a0-ewf_table,ewf_a1-ewf_table,ewf_a2-ewf_table,ewf_a3-ewf_table
+	.short		ewf_a4-ewf_table,ewf_a5-ewf_table,ewf_a6-ewf_table,ewf_a7-ewf_table
+	.short		ewferr-ewf_table,ewf_a9-ewf_table,ewferr-ewf_table,ewf_ab-ewf_table
+	.short		ewferr-ewf_table,ewf_ad-ewf_table,ewferr-ewf_table,ewf_af-ewf_table
+	.short		ewf_b0-ewf_table,ewf_b1-ewf_table,ewf_b2-ewf_table,ewf_b3-ewf_table
+	.short		ewf_b4-ewf_table,ewf_b5-ewf_table,ewf_b6-ewf_table,ewf_b7-ewf_table
+	.short		ewferr-ewf_table,ewf_b9-ewf_table,ewferr-ewf_table,ewf_bb-ewf_table
+	.short		ewferr-ewf_table,ewf_bd-ewf_table,ewferr-ewf_table,ewf_bf-ewf_table
+	.short		ewf_c0-ewf_table,ewf_c1-ewf_table,ewf_c2-ewf_table,ewf_c3-ewf_table
+	.short		ewf_c4-ewf_table,ewf_c5-ewf_table,ewf_c6-ewf_table,ewf_c7-ewf_table
+	.short		ewferr-ewf_table,ewf_c9-ewf_table,ewferr-ewf_table,ewf_cb-ewf_table
+	.short		ewferr-ewf_table,ewf_cd-ewf_table,ewferr-ewf_table,ewf_cf-ewf_table
+	.short		ewf_d0-ewf_table,ewf_d1-ewf_table,ewf_d2-ewf_table,ewf_d3-ewf_table
+	.short		ewf_d4-ewf_table,ewf_d5-ewf_table,ewf_d6-ewf_table,ewf_d7-ewf_table
+	.short		ewferr-ewf_table,ewf_d9-ewf_table,ewferr-ewf_table,ewf_db-ewf_table
+	.short		ewferr-ewf_table,ewf_dd-ewf_table,ewferr-ewf_table,ewf_df-ewf_table
+	.short		ewf_e0-ewf_table,ewf_e1-ewf_table,ewf_e2-ewf_table,ewf_e3-ewf_table
+	.short		ewf_e4-ewf_table,ewf_e5-ewf_table,ewf_e6-ewf_table,ewf_e7-ewf_table
+	.short		ewferr-ewf_table,ewf_e9-ewf_table,ewferr-ewf_table,ewf_eb-ewf_table
+	.short		ewferr-ewf_table,ewf_ed-ewf_table,ewferr-ewf_table,ewf_ef-ewf_table
+	.short		ewf_f0-ewf_table,ewf_f1-ewf_table,ewf_f2-ewf_table,ewf_f3-ewf_table
+	.short		ewf_f4-ewf_table,ewf_f5-ewf_table,ewf_f6-ewf_table,ewf_f7-ewf_table
+	.short		ewferr-ewf_table,ewf_f9-ewf_table,ewferr-ewf_table,ewf_fb-ewf_table
+	.short		ewferr-ewf_table,ewf_fd-ewf_table,ewferr-ewf_table,ewf_ff-ewf_table
+//d0.w * 1
+ewf_00:
+	mvs.b		(a0)+,d1
+	mvs.w		d0_off+6(a7),d0
+	add.l		d0,a1
+	add.l		d1,a1
+	rts
+ewf_01:
+	mvs.w		d0_off+6(a7),d0
+	bra			ewf_full
+//d0.w * 2
+ewf_02:
+	mvs.b		(a0)+,d1
+	mvs.w		d0_off+6(a7),d0
+	lea			0(a1,d0*2),a1
+	add.l		d1,a1
+	rts
+ewf_03:
+	mvs.w		d0_off+6(a7),d0
+	move.w		ccr,d1
+	asl.l		#1,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//d0.w * 4
+ewf_04:
+	mvs.b		(a0)+,d1
+	mvs.w		d0_off+6(a7),d0
+	lea			0(a1,d0*4),a1
+	add.l		d1,a1
+	rts
+ewf_05:
+	mvs.w		d0_off+6(a7),d0
+	move.w		ccr,d1
+	asl.l		#2,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//d0.w * 8
+ewf_06:
+	mvs.b		(a0)+,d1
+	mvs.w		d0_off+6(a7),d0
+	lea			0(a1,d0*4),a1
+	lea			0(a1,d0*4),a1
+	add.l		d1,a1
+	rts
+ewf_07:
+	mvs.w		d0_off+6(a7),d0
+	move.w		ccr,d1
+	asl.l		#3,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//d0.l * 1
+ewf_09:
+	move.l		d0_off+4(a7),d0
+	bra			ewf_full
+//d0.l * 2
+ewf_0b:
+	move.l		d0_off+4(a7),d0
+	move.w		ccr,d1
+	asl.l		#1,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//d0.l * 4
+ewf_0d:
+	move.l		d0_off+4(a7),d0
+	move.w		ccr,d1
+	asl.l		#2,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//d0.l * 8
+ewf_0f:
+	move.l		d0_off+4(a7),d0
+	move.w		ccr,d1
+	asl.l		#3,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//d1.w * 1
+ewf_10:
+	mvs.b		(a0)+,d1
+	mvs.w		d1_off+6(a7),d0
+	add.l		d0,a1
+	add.l		d1,a1
+	rts
+ewf_11:
+	mvs.w		d1_off+6(a7),d0
+	bra			ewf_full
+//d1.w * 2
+ewf_12:
+	mvs.b		(a0)+,d1
+	mvs.w		d1_off+6(a7),d0
+	lea			0(a1,d0*2),a1
+	add.l		d1,a1
+	rts
+ewf_13:
+	mvs.w		d1_off+6(a7),d0
+	move.w		ccr,d1
+	asl.l		#1,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//d1.w * 4
+ewf_14:
+	mvs.b		(a0)+,d1
+	mvs.w		d1_off+6(a7),d0
+	lea			0(a1,d0*4),a1
+	add.l		d1,a1
+	rts
+ewf_15:
+	mvs.w		d1_off+6(a7),d0
+	move.w		ccr,d1
+	asl.l		#2,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//d1.w * 8
+ewf_16:
+	mvs.b		(a0)+,d1
+	mvs.w		d1_off+6(a7),d0
+	lea			0(a1,d0*4),a1
+	lea			0(a1,d0*4),a1
+	add.l		d1,a1
+	rts
+ewf_17:
+	mvs.w		d1_off+6(a7),d0
+	move.w		ccr,d1
+	asl.l		#3,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//d1.l * 1
+ewf_19:
+	move.l		d1_off+4(a7),d0
+	bra			ewf_full
+//d1.l * 2
+ewf_1b:
+	move.l		d1_off+4(a7),d0
+	move.w		ccr,d1
+	asl.l		#1,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//d1.l * 4
+ewf_1d:
+	move.l		d1_off+4(a7),d0
+	move.w		ccr,d1
+	asl.l		#2,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//d1.l * 8
+ewf_1f:
+	move.l		d1_off+4(a7),d0
+	move.w		ccr,d1
+	asl.l		#3,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//d2.w * 1
+ewf_20:
+	mvs.b		(a0)+,d1
+	mvs.w		d2,d0
+	add.l		d0,a1
+	add.l		d1,a1
+	rts
+ewf_21:
+	mvs.w		d2,d0
+	bra			ewf_full
+//d2.w * 2
+ewf_22:
+	mvs.b		(a0)+,d1
+	mvs.w		d2,d0
+	lea			0(a1,d0*2),a1
+	add.l		d1,a1
+	rts
+ewf_23:
+	mvs.w		d2,d0
+	move.w		ccr,d1
+	asl.l		#1,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//d2.w * 4
+ewf_24:
+	mvs.b		(a0)+,d1
+	mvs.w		d2,d0
+	lea			0(a1,d0*4),a1
+	add.l		d1,a1
+	rts
+ewf_25:
+	mvs.w		d2,d0
+	move.w		ccr,d1
+	asl.l		#2,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//d2.w * 8
+ewf_26:
+	mvs.b		(a0)+,d1
+	mvs.w		d2,d0
+	lea			0(a1,d0*4),a1
+	lea			0(a1,d0*4),a1
+	add.l		d1,a1
+	rts
+ewf_27:
+	mvs.w		d2,d0
+	move.w		ccr,d1
+	asl.l		#3,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//d2.l * 1
+ewf_29:
+	move.l		d2,d0
+	bra			ewf_full
+//d2.l * 2
+ewf_2b:
+	move.l		d2,d0
+	move.w		ccr,d1
+	asl.l		#1,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//d2.l * 4
+ewf_2d:
+	move.l		d2,d0
+	move.w		ccr,d1
+	asl.l		#2,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//d2.l * 8
+ewf_2f:
+	move.l		d2,d0
+	move.w		ccr,d1
+	asl.l		#3,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//d3.w * 1
+ewf_30:
+	mvs.b		(a0)+,d1
+	mvs.w		d3,d0
+	add.l		d0,a1
+	add.l		d1,a1
+	rts
+ewf_31:
+	mvs.w		d3,d0
+	bra			ewf_full
+//d3.w * 2
+ewf_32:
+	mvs.b		(a0)+,d1
+	mvs.w		d3,d0
+	lea			0(a1,d0*2),a1
+	add.l		d1,a1
+	rts
+ewf_33:
+	mvs.w		d3,d0
+	move.w		ccr,d1
+	asl.l		#1,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//d3.w * 4
+ewf_34:
+	mvs.b		(a0)+,d1
+	mvs.w		d3,d0
+	lea			0(a1,d0*4),a1
+	add.l		d1,a1
+	rts
+ewf_35:
+	mvs.w		d3,d0
+	move.w		ccr,d1
+	asl.l		#2,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//d3.w * 8
+ewf_36:
+	mvs.b		(a0)+,d1
+	mvs.w		d3,d0
+	lea			0(a1,d0*4),a1
+	lea			0(a1,d0*4),a1
+	add.l		d1,a1
+	rts
+ewf_37:
+	mvs.w		d3,d0
+	move.w		ccr,d1
+	asl.l		#3,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//d3.l * 1
+ewf_39:
+	move.l		d3,d0
+	bra			ewf_full
+//d3.l * 3
+ewf_3b:
+	move.l		d3,d0
+	move.w		ccr,d1
+	asl.l		#1,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//d3.l * 4
+ewf_3d:
+	move.l		d3,d0
+	move.w		ccr,d1
+	asl.l		#2,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//d3.l * 8
+ewf_3f:
+	move.l		d3,d0
+	move.w		ccr,d1
+	asl.l		#3,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//d4.w * 1
+ewf_40:
+	mvs.b		(a0)+,d1
+	mvs.w		d4,d0
+	add.l		d0,a1
+	add.l		d1,a1
+	rts
+ewf_41:
+	mvs.w		d4,d0
+	bra			ewf_full
+//d4.w * 2
+ewf_42:
+	mvs.b		(a0)+,d1
+	mvs.w		d4,d0
+	lea			0(a1,d0*2),a1
+	add.l		d1,a1
+	rts
+ewf_43:
+	mvs.w		d4,d0
+	move.w		ccr,d1
+	asl.l		#1,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//d4.w * 4
+ewf_44:
+	mvs.b		(a0)+,d1
+	mvs.w		d4,d0
+	lea			0(a1,d0*4),a1
+	add.l		d1,a1
+	rts
+ewf_45:
+	mvs.w		d4,d0
+	move.w		ccr,d1
+	asl.l		#2,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//d4.w * 8
+ewf_46:
+	mvs.b		(a0)+,d1
+	mvs.w		d4,d0
+	lea			0(a1,d0*4),a1
+	lea			0(a1,d0*4),a1
+	add.l		d1,a1
+	rts
+ewf_47:
+	mvs.w		d4,d0
+	move.w		ccr,d1
+	asl.l		#3,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//d4.l * 1
+ewf_49:
+	move.l		d4,d0
+	bra			ewf_full
+//d4.l * 4
+ewf_4b:
+	move.l		d4,d0
+	move.w		ccr,d1
+	asl.l		#1,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//d4.l * 4
+ewf_4d:
+	move.l		d4,d0
+	move.w		ccr,d1
+	asl.l		#2,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//d4.l * 8
+ewf_4f:
+	move.l		d4,d0
+	move.w		ccr,d1
+	asl.l		#3,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//d5.w * 1
+ewf_50:
+	mvs.b		(a0)+,d1
+	mvs.w		d5,d0
+	add.l		d0,a1
+	add.l		d1,a1
+	rts
+ewf_51:
+	mvs.w		d5,d0
+	bra			ewf_full
+//d5.w * 2
+ewf_52:
+	mvs.b		(a0)+,d1
+	mvs.w		d5,d0
+	lea			0(a1,d0*2),a1
+	add.l		d1,a1
+	rts
+ewf_53:
+	mvs.w		d5,d0
+	move.w		ccr,d1
+	asl.l		#1,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//d5.w * 4
+ewf_54:
+	mvs.b		(a0)+,d1
+	mvs.w		d5,d0
+	lea			0(a1,d0*4),a1
+	add.l		d1,a1
+	rts
+ewf_55:
+	mvs.w		d5,d0
+	move.w		ccr,d1
+	asl.l		#2,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//d5.w * 8
+ewf_56:
+	mvs.b		(a0)+,d1
+	mvs.w		d5,d0
+	lea			0(a1,d0*4),a1
+	lea			0(a1,d0*4),a1
+	add.l		d1,a1
+	rts
+ewf_57:
+	mvs.w		d5,d0
+	move.w		ccr,d1
+	asl.l		#3,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//d5.l * 1
+ewf_59:
+	move.l		d5,d0
+	bra			ewf_full
+//d5.l * 5
+ewf_5b:
+	move.l		d5,d0
+	move.w		ccr,d1
+	asl.l		#1,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//d5.l * 4
+ewf_5d:
+	move.l		d5,d0
+	move.w		ccr,d1
+	asl.l		#2,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//d5.l * 8
+ewf_5f:
+	move.l		d5,d0
+	move.w		ccr,d1
+	asl.l		#3,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//d6.w * 1
+ewf_60:
+	mvs.b		(a0)+,d1
+	mvs.w		d6,d0
+	add.l		d0,a1
+	add.l		d1,a1
+	rts
+ewf_61:
+	mvs.w		d6,d0
+	bra			ewf_full
+//d6.w * 2
+ewf_62:
+	mvs.b		(a0)+,d1
+	mvs.w		d6,d0
+	lea			0(a1,d0*2),a1
+	add.l		d1,a1
+	rts
+ewf_63:
+	mvs.w		d6,d0
+	move.w		ccr,d1
+	asl.l		#1,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//d6.w * 4
+ewf_64:
+	mvs.b		(a0)+,d1
+	mvs.w		d6,d0
+	lea			0(a1,d0*4),a1
+	add.l		d1,a1
+	rts
+ewf_65:
+	mvs.w		d6,d0
+	move.w		ccr,d1
+	asl.l		#2,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//d6.w * 8
+ewf_66:
+	mvs.b		(a0)+,d1
+	mvs.w		d6,d0
+	lea			0(a1,d0*4),a1
+	lea			0(a1,d0*4),a1
+	add.l		d1,a1
+	rts
+ewf_67:
+	mvs.w		d6,d0
+	move.w		ccr,d1
+	asl.l		#3,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//d6.l * 1
+ewf_69:
+	move.l		d6,d0
+	bra			ewf_full
+//d6.l * 6
+ewf_6b:
+	move.l		d6,d0
+	move.w		ccr,d1
+	asl.l		#1,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//d6.l * 4
+ewf_6d:
+	move.l		d6,d0
+	move.w		ccr,d1
+	asl.l		#2,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//d6.l * 8
+ewf_6f:
+	move.l		d6,d0
+	move.w		ccr,d1
+	asl.l		#3,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//d7.w * 1
+ewf_70:
+	mvs.b		(a0)+,d1
+	mvs.w		d7,d0
+	add.l		d0,a1
+	add.l		d1,a1
+	rts
+ewf_71:
+	mvs.w		d7,d0
+	bra			ewf_full
+//d7.w * 2
+ewf_72:
+	mvs.b		(a0)+,d1
+	mvs.w		d7,d0
+	lea			0(a1,d0*2),a1
+	add.l		d1,a1
+	rts
+ewf_73:
+	mvs.w		d7,d0
+	move.w		ccr,d1
+	asl.l		#1,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//d7.w * 4
+ewf_74:
+	mvs.b		(a0)+,d1
+	mvs.w		d7,d0
+	lea			0(a1,d0*4),a1
+	add.l		d1,a1
+	rts
+ewf_75:
+	mvs.w		d7,d0
+	move.w		ccr,d1
+	asl.l		#2,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//d7.w * 8
+ewf_76:
+	mvs.b		(a0)+,d1
+	mvs.w		d7,d0
+	lea			0(a1,d0*4),a1
+	lea			0(a1,d0*4),a1
+	add.l		d1,a1
+	rts
+ewf_77:
+	mvs.w		d7,d0
+	move.w		ccr,d1
+	asl.l		#3,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//d7.l * 1
+ewf_79:
+	move.l		d7,d0
+	bra			ewf_full
+//d7.l * 7
+ewf_7b:
+	move.l		d7,d0
+	move.w		ccr,d1
+	asl.l		#1,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//d7.l * 4
+ewf_7d:
+	move.l		d7,d0
+	move.w		ccr,d1
+	asl.l		#2,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//d7.l * 8
+ewf_7f:
+	move.l		d7,d0
+	move.w		ccr,d1
+	asl.l		#3,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//a0.w * 1
+ewf_80:
+	mvs.b		(a0)+,d1
+	mvs.w		a0_off+6(a7),d0
+	add.l		d0,a1
+	add.l		d1,a1
+	rts
+ewf_81:
+	mvs.w		a0_off+6(a7),d0
+	bra			ewf_full
+//a0.w * 2
+ewf_82:
+	mvs.b		(a0)+,d1
+	mvs.w		a0_off+6(a7),d0
+	lea			0(a1,d0*2),a1
+	add.l		d1,a1
+	rts
+ewf_83:
+	mvs.w		a0_off+6(a7),d0
+	move.w		ccr,d1
+	asl.l		#1,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//a0.w * 4
+ewf_84:
+	mvs.b		(a0)+,d1
+	mvs.w		a0_off+6(a7),d0
+	lea			0(a1,d0*4),a1
+	add.l		d1,a1
+	rts
+ewf_85:
+	mvs.w		a0_off+6(a7),d0
+	move.w		ccr,d1
+	asl.l		#2,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//a0.w * 8
+ewf_86:
+	mvs.b		(a0)+,d1
+	mvs.w		a0_off+6(a7),d0
+	lea			0(a1,d0*4),a1
+	lea			0(a1,d0*4),a1
+	add.l		d1,a1
+	rts
+ewf_87:
+	mvs.w		a0_off+6(a7),d0
+	move.w		ccr,d1
+	asl.l		#3,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//a0.l * 1
+ewf_89:
+	move.l		a0_off+4(a7),d0
+	bra			ewf_full
+//a0.l * 2
+ewf_8b:
+	move.l		a0_off+4(a7),d0
+	move.w		ccr,d1
+	asl.l		#1,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//a0.l * 4
+ewf_8d:
+	move.l		a0_off+4(a7),d0
+	move.w		ccr,d1
+	asl.l		#2,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//a0.l * 8
+ewf_8f:
+	move.l		a0_off+4(a7),d0
+	move.w		ccr,d1
+	asl.l		#3,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//a1.w * 1
+ewf_90:
+	mvs.b		(a0)+,d1
+	mvs.w		a1_off+6(a7),d0
+	add.l		d0,a1
+	add.l		d1,a1
+	rts
+ewf_91:
+	mvs.w		a1_off+6(a7),d0
+	bra			ewf_full
+//a1.w * 2
+ewf_92:
+	mvs.b		(a0)+,d1
+	mvs.w		a1_off+6(a7),d0
+	lea			0(a1,d0*2),a1
+	add.l		d1,a1
+	rts
+ewf_93:
+	mvs.w		a1_off+6(a7),d0
+	move.w		ccr,d1
+	asl.l		#1,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//a1.w * 4
+ewf_94:
+	mvs.b		(a0)+,d1
+	mvs.w		a1_off+6(a7),d0
+	lea			0(a1,d0*4),a1
+	add.l		d1,a1
+	rts
+ewf_95:
+	mvs.w		a1_off+6(a7),d0
+	move.w		ccr,d1
+	asl.l		#2,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//a1.w * 8
+ewf_96:
+	mvs.b		(a0)+,d1
+	mvs.w		a1_off+6(a7),d0
+	lea			0(a1,d0*4),a1
+	lea			0(a1,d0*4),a1
+	add.l		d1,a1
+	rts
+ewf_97:
+	mvs.w		a1_off+6(a7),d0
+	move.w		ccr,d1
+	asl.l		#3,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//a1.l * 1
+ewf_99:
+	move.l		a1_off+4(a7),d0
+	bra			ewf_full
+//a1.l * 2
+ewf_9b:
+	move.l		a1_off+4(a7),d0
+	move.w		ccr,d1
+	asl.l		#1,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//a1.l * 4
+ewf_9d:
+	move.l		a1_off+4(a7),d0
+	move.w		ccr,d1
+	asl.l		#2,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//a1.l * 8
+ewf_9f:
+	move.l		a1_off+4(a7),d0
+	move.w		ccr,d1
+	asl.l		#3,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//a2.w * 1
+ewf_a0:
+	mvs.b		(a0)+,d1
+	mvs.w		a2,d0
+	add.l		d0,a1
+	add.l		d1,a1
+	rts
+ewf_a1:
+	mvs.w		a2,d0
+	bra			ewf_full
+//a2.w * 2
+ewf_a2:
+	mvs.b		(a0)+,d1
+	mvs.w		a2,d0
+	lea			0(a1,d0*2),a1
+	add.l		d1,a1
+	rts
+ewf_a3:
+	mvs.w		a2,d0
+	move.w		ccr,d1
+	asl.l		#1,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//a2.w * 4
+ewf_a4:
+	mvs.b		(a0)+,d1
+	mvs.w		a2,d0
+	lea			0(a1,d0*4),a1
+	add.l		d1,a1
+	rts
+ewf_a5:
+	mvs.w		a2,d0
+	move.w		ccr,d1
+	asl.l		#2,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//a2.w * 8
+ewf_a6:
+	mvs.b		(a0)+,d1
+	mvs.w		a2,d0
+	lea			0(a1,d0*4),a1
+	lea			0(a1,d0*4),a1
+	add.l		d1,a1
+	rts
+ewf_a7:
+	mvs.w		a2,d0
+	move.w		ccr,d1
+	asl.l		#3,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//a2.l * 1
+ewf_a9:
+	move.l		a2,d0
+	bra			ewf_full
+//a2.l * 2
+ewf_ab:
+	move.l		a2,d0
+	move.w		ccr,d1
+	asl.l		#1,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//a2.l * 4
+ewf_ad:
+	move.l		a2,d0
+	move.w		ccr,d1
+	asl.l		#2,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//a2.l * 8
+ewf_af:
+	move.l		a2,d0
+	move.w		ccr,d1
+	asl.l		#3,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//a3.w * 1
+ewf_b0:
+	mvs.b		(a0)+,d1
+	mvs.w		a3,d0
+	add.l		d0,a1
+	add.l		d1,a1
+	rts
+ewf_b1:
+	mvs.w		a3,d0
+	bra			ewf_full
+//a3.w * 2
+ewf_b2:
+	mvs.b		(a0)+,d1
+	mvs.w		a3,d0
+	lea			0(a1,d0*2),a1
+	add.l		d1,a1
+	rts
+ewf_b3:
+	mvs.w		a3,d0
+	move.w		ccr,d1
+	asl.l		#1,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//a3.w * 4
+ewf_b4:
+	mvs.b		(a0)+,d1
+	mvs.w		a3,d0
+	lea			0(a1,d0*4),a1
+	add.l		d1,a1
+	rts
+ewf_b5:
+	mvs.w		a3,d0
+	move.w		ccr,d1
+	asl.l		#2,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//a3.w * 8
+ewf_b6:
+	mvs.b		(a0)+,d1
+	mvs.w		a3,d0
+	lea			0(a1,d0*4),a1
+	lea			0(a1,d0*4),a1
+	add.l		d1,a1
+	rts
+ewf_b7:
+	mvs.w		a3,d0
+	move.w		ccr,d1
+	asl.l		#3,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//a3.l * 1
+ewf_b9:
+	move.l		a3,d0
+	bra			ewf_full
+//a3.l * 3
+ewf_bb:
+	move.l		a3,d0
+	move.w		ccr,d1
+	asl.l		#1,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//a3.l * 4
+ewf_bd:
+	move.l		a3,d0
+	move.w		ccr,d1
+	asl.l		#2,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//a3.l * 8
+ewf_bf:
+	move.l		a3,d0
+	move.w		ccr,d1
+	asl.l		#3,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//a4.w * 1
+ewf_c0:
+	mvs.b		(a0)+,d1
+	mvs.w		a4,d0
+	add.l		d0,a1
+	add.l		d1,a1
+	rts
+ewf_c1:
+	mvs.w		a4,d0
+	bra			ewf_full
+//a4.w * 2
+ewf_c2:
+	mvs.b		(a0)+,d1
+	mvs.w		a4,d0
+	lea			0(a1,d0*2),a1
+	add.l		d1,a1
+	rts
+ewf_c3:
+	mvs.w		a4,d0
+	move.w		ccr,d1
+	asl.l		#1,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//a4.w * 4
+ewf_c4:
+	mvs.b		(a0)+,d1
+	mvs.w		a4,d0
+	lea			0(a1,d0*4),a1
+	add.l		d1,a1
+	rts
+ewf_c5:
+	mvs.w		a4,d0
+	move.w		ccr,d1
+	asl.l		#2,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//a4.w * 8
+ewf_c6:
+	mvs.b		(a0)+,d1
+	mvs.w		a4,d0
+	lea			0(a1,d0*4),a1
+	lea			0(a1,d0*4),a1
+	add.l		d1,a1
+	rts
+ewf_c7:
+	mvs.w		a4,d0
+	move.w		ccr,d1
+	asl.l		#3,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//a4.l * 1
+ewf_c9:
+	move.l		a4,d0
+	bra			ewf_full
+//a4.l * 4
+ewf_cb:
+	move.l		a4,d0
+	move.w		ccr,d1
+	asl.l		#1,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//a4.l * 4
+ewf_cd:
+	move.l		a4,d0
+	move.w		ccr,d1
+	asl.l		#2,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//a4.l * 8
+ewf_cf:
+	move.l		a4,d0
+	move.w		ccr,d1
+	asl.l		#3,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//a5.w * 1
+ewf_d0:
+	mvs.b		(a0)+,d1
+	mvs.w		a5,d0
+	add.l		d0,a1
+	add.l		d1,a1
+	rts
+ewf_d1:
+	mvs.w		a5,d0
+	bra			ewf_full
+//a5.w * 2
+ewf_d2:
+	mvs.b		(a0)+,d1
+	mvs.w		a5,d0
+	lea			0(a1,d0*2),a1
+	add.l		d1,a1
+	rts
+ewf_d3:
+	mvs.w		a5,d0
+	move.w		ccr,d1
+	asl.l		#1,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//a5.w * 4
+ewf_d4:
+	mvs.b		(a0)+,d1
+	mvs.w		a5,d0
+	lea			0(a1,d0*4),a1
+	add.l		d1,a1
+	rts
+ewf_d5:
+	mvs.w		a5,d0
+	move.w		ccr,d1
+	asl.l		#2,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//a5.w * 8
+ewf_d6:
+	mvs.b		(a0)+,d1
+	mvs.w		a5,d0
+	lea			0(a1,d0*4),a1
+	lea			0(a1,d0*4),a1
+	add.l		d1,a1
+	rts
+ewf_d7:
+	mvs.w		a5,d0
+	move.w		ccr,d1
+	asl.l		#3,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//a5.l * 1
+ewf_d9:
+	move.l		a5,d0
+	bra			ewf_full
+//a5.l * 5
+ewf_db:
+	move.l		a5,d0
+	move.w		ccr,d1
+	asl.l		#1,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//a5.l * 4
+ewf_dd:
+	move.l		a5,d0
+	move.w		ccr,d1
+	asl.l		#2,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//a5.l * 8
+ewf_df:
+	move.l		a5,d0
+	move.w		ccr,d1
+	asl.l		#3,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//a6.w * 1
+ewf_e0:
+	mvs.b		(a0)+,d1
+	mvs.w		a6,d0
+	add.l		d0,a1
+	add.l		d1,a1
+	rts
+ewf_e1:
+	mvs.w		a6,d0
+	bra			ewf_full
+//a6.w * 2
+ewf_e2:
+	mvs.b		(a0)+,d1
+	mvs.w		a6,d0
+	lea			0(a1,d0*2),a1
+	add.l		d1,a1
+	rts
+ewf_e3:
+	mvs.w		a6,d0
+	move.w		ccr,d1
+	asl.l		#1,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//a6.w * 4
+ewf_e4:
+	mvs.b		(a0)+,d1
+	mvs.w		a6,d0
+	lea			0(a1,d0*4),a1
+	add.l		d1,a1
+	rts
+ewf_e5:
+	mvs.w		a6,d0
+	move.w		ccr,d1
+	asl.l		#2,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//a6.w * 8
+ewf_e6:
+	mvs.b		(a0)+,d1
+	mvs.w		a6,d0
+	lea			0(a1,d0*4),a1
+	lea			0(a1,d0*4),a1
+	add.l		d1,a1
+	rts
+ewf_e7:
+	mvs.w		a6,d0
+	move.w		ccr,d1
+	asl.l		#3,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//a6.l * 1
+ewf_e9:
+	move.l		a6,d0
+	bra			ewf_full
+//a6.l * 6
+ewf_eb:
+	move.l		a6,d0
+	move.w		ccr,d1
+	asl.l		#1,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//a6.l * 4
+ewf_ed:
+	move.l		a6,d0
+	move.w		ccr,d1
+	asl.l		#2,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//a6.l * 8
+ewf_ef:
+	move.l		a6,d0
+	move.w		ccr,d1
+	asl.l		#3,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//usp.w * 1
+ewf_f0:
+	mvs.b		(a0)+,d1
+	move.l		a1,-(a7)
+	move.l		usp,a1
+	add.l		(a7)+,a1
+	add.l		d1,a1
+	rts
+ewf_f1:
+	move.l		a1,-(a7)
+	move.l		usp,a1
+	mvs.w		a1,d0
+	move.l		(a7)+,a1
+	bra			ewf_full
+//usp.w * 2
+ewf_f2:
+	mvs.b		(a0)+,d1
+	move.l		usp,a1
+	mvs.w		a1,d0
+	move.l		(a7)+,a1
+	lea			0(a1,d0*2),a1
+	add.l		d1,a1
+	rts
+ewf_f3:
+	move.l		usp,a1
+	move.l		a1,-(a7)
+	move.l		usp,a1
+	add.l		(a7)+,a1
+	move.w		ccr,d1
+	asl.l		#1,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//usp.w * 4
+ewf_f4:
+	mvs.b		(a0)+,d1
+	move.l		a1,-(a7)
+	move.l		usp,a1
+	add.l		(a7)+,a1
+	lea			0(a1,d0*4),a1
+	add.l		d1,a1
+	rts
+ewf_f5:
+	move.l		a1,-(a7)
+	move.l		usp,a1
+	add.l		(a7)+,a1
+	move.w		ccr,d1
+	asl.l		#2,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//usp.w * 8
+ewf_f6:
+	mvs.b		(a0)+,d1
+	move.l		a1,-(a7)
+	move.l		usp,a1
+	add.l		(a7)+,a1
+	lea			0(a1,d0*4),a1
+	lea			0(a1,d0*4),a1
+	add.l		d1,a1
+	rts
+ewf_f7:
+	move.l		a1,-(a7)
+	move.l		usp,a1
+	add.l		(a7)+,a1
+	move.w		ccr,d1
+	asl.l		#3,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//usp.l * 1
+ewf_f9:
+	move.l		a1,-(a7)
+	move.l		usp,a1
+	add.l		(a7)+,a1
+	bra			ewf_full
+//usp.l * 7
+ewf_fb:
+	move.l		a1,-(a7)
+	move.l		usp,a1
+	add.l		(a7)+,a1
+	move.w		ccr,d1
+	asl.l		#1,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//usp.l * 4
+ewf_fd:
+	move.l		a1,-(a7)
+	move.l		usp,a1
+	add.l		(a7)+,a1
+	move.w		ccr,d1
+	asl.l		#2,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//usp.l * 8
+ewf_ff:
+	move.l		a1,-(a7)
+	move.l		usp,a1
+	add.l		(a7)+,a1
+	move.w		ccr,d1
+	asl.l		#3,d0
+	move.w		d1,ccr
+	bra			ewf_full
+//-----------------------------------------------------------------------------------
+// extension full format rest von ewf
+//--------------------------------------------------------------------
+ewf_full:
+	mvz.b		(a0)+,d1
+	mvs.w		ewff_table-*-2(pc,d1*2),d1
+	jmp			ewff_table-*-2(pc,d1)
+ewff_table:				
+	.short		ewff_end-ewff_table,ewff_i0v-ewff_table,ewff_iwv-ewff_table,ewff_ilv-ewff_table	//00
+	.short		ewff_end-ewff_table,ewff_i0n-ewff_table,ewff_iwn-ewff_table,ewff_iln-ewff_table
+	.short		ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table
+	.short		ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table
+	.short		ewff_end-ewff_table,ewff_i0v-ewff_table,ewff_iwv-ewff_table,ewff_ilv-ewff_table	//10
+	.short		ewff_end-ewff_table,ewff_i0n-ewff_table,ewff_iwn-ewff_table,ewff_iln-ewff_table
+	.short		ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table
+	.short		ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table
+	.short		ewff_bsw-ewff_table,ewff_w0v-ewff_table,ewff_wwv-ewff_table,ewff_wlv-ewff_table	//20
+	.short		ewff_end-ewff_table,ewff_w0n-ewff_table,ewff_wwn-ewff_table,ewff_wln-ewff_table
+	.short		ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table
+	.short		ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table
+	.short		ewff_bsl-ewff_table,ewff_l0v-ewff_table,ewff_lwv-ewff_table,ewff_llv-ewff_table	//30
+	.short		ewff_end-ewff_table,ewff_l0n-ewff_table,ewff_lwn-ewff_table,ewff_lln-ewff_table
+	.short		ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table
+	.short		ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table
+	.short		ewff_end-ewff_table,ewff_mi0-ewff_table,ewff_miw-ewff_table,ewff_mil-ewff_table	//40
+	.short		ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table
+	.short		ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table
+	.short		ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table
+	.short		ewff_end-ewff_table,ewff_mi0-ewff_table,ewff_miw-ewff_table,ewff_mil-ewff_table	//50
+	.short		ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table
+	.short		ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table
+	.short		ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table
+	.short		ewff_bsw-ewff_table,ewff_wi0-ewff_table,ewff_wiw-ewff_table,ewff_wil-ewff_table	//60
+	.short		ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table
+	.short		ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table
+	.short		ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table
+	.short		ewff_bsl-ewff_table,ewff_li0-ewff_table,ewff_liw-ewff_table,ewff_lil-ewff_table	//70
+	.short		ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table
+	.short		ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table
+	.short		ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table
+	.short		ewff_end-ewff_table,ewff_i0v-ewff_table,ewff_iwv-ewff_table,ewff_ilv-ewff_table	//80
+	.short		ewff_end-ewff_table,ewff_i0n-ewff_table,ewff_iwn-ewff_table,ewff_iln-ewff_table
+	.short		ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table
+	.short		ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table
+	.short		ewff_end-ewff_table,ewff_i0v-ewff_table,ewff_iwv-ewff_table,ewff_ilv-ewff_table	//90
+	.short		ewff_end-ewff_table,ewff_i0n-ewff_table,ewff_iwn-ewff_table,ewff_iln-ewff_table
+	.short		ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table
+	.short		ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table
+	.short		ewff_end-ewff_table,ewff_i0v-ewff_table,ewff_iwv-ewff_table,ewff_ilv-ewff_table	//a0
+	.short		ewff_end-ewff_table,ewff_i0n-ewff_table,ewff_iwn-ewff_table,ewff_iln-ewff_table
+	.short		ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table
+	.short		ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table
+	.short		ewff_end-ewff_table,ewff_i0v-ewff_table,ewff_iwv-ewff_table,ewff_ilv-ewff_table	//b0
+	.short		ewff_end-ewff_table,ewff_i0n-ewff_table,ewff_iwn-ewff_table,ewff_iln-ewff_table
+	.short		ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table
+	.short		ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table
+	.short		ewff_end-ewff_table,ewff_mi0-ewff_table,ewff_miw-ewff_table,ewff_mil-ewff_table	//c0
+	.short		ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table
+	.short		ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table
+	.short		ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table
+	.short		ewff_end-ewff_table,ewff_mi0-ewff_table,ewff_miw-ewff_table,ewff_mil-ewff_table	//d0
+	.short		ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table
+	.short		ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table
+	.short		ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table
+	.short		ewff_end-ewff_table,ewff_mi0-ewff_table,ewff_miw-ewff_table,ewff_mil-ewff_table	//e0
+	.short		ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table
+	.short		ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table
+	.short		ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table
+	.short		ewff_end-ewff_table,ewff_mi0-ewff_table,ewff_miw-ewff_table,ewff_mil-ewff_table	//f0
+	.short		ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table
+	.short		ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table
+	.short		ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table,ewff_end-ewff_table
+ewff_end:
+	rts
+ewff_bsw:
+	mvs.w		(a0)+,d1
+	add.l		d1,a1
+	add.l		d0,a1
+	rts
+ewff_bsl:
+	move.l		(a0)+,d1
+	add.l		d1,a1
+	add.l		d0,a1
+	rts
+ewff_i0v:
+	add.l		d0,a1
+	move.l		(a1),a1
+	rts
+ewff_iwv:
+	add.l		d0,a1
+	move.l		(a1),a1
+	mvs.w		(a0)+,d0
+	add.l		d0,a1
+	rts
+ewff_ilv:
+	add.l		d0,a1
+	move.l		(a1),a1
+	move.l		(a0)+,d0
+	add.l		d0,a1
+	rts
+ewff_i0n:
+	move.l		(a1),a1
+	add.l		d0,a1
+	rts
+ewff_iwn:
+	move.l		(a1),a1
+	add.l		d0,a1
+	mvs.w		(a0)+,d0
+	add.l		d0,a1
+	rts
+ewff_iln:
+	move.l		(a1),a1
+	add.l		d0,a1
+	move.l		(a0)+,d0
+	add.l		d0,a1
+	rts
+ewff_mi0:
+	add.l		d0,a1
+	rts
+ewff_miw:
+	mvs.w		(a0)+,d1
+	add.l		d0,a1
+	add.l		d1,a1
+	rts
+ewff_mil:
+	move.l		(a0)+,d1
+	add.l		d0,a1
+	add.l		d1,a1
+	rts
+ewff_wi0:
+	mvs.w		(a0)+,d1
+	add.l		d1,a1
+	add.l		d0,a1
+	rts
+ewff_wiw:
+	mvs.w		(a0)+,d1
+	add.l		d1,a1
+	mvs.w		(a0)+,d1
+	add.l		d0,a1
+	add.l		d1,a1
+	rts
+ewff_wil:
+	mvs.w		(a0)+,d1
+	add.l		d1,a1
+	move.l		(a0)+,d1
+	add.l		d0,a1
+	add.l		d1,a1
+	rts
+ewff_li0:
+	move.l		(a0)+,d1
+	add.l		d1,a1
+	add.l		d0,a1
+	rts
+ewff_liw:
+	move.l		(a0)+,d1
+	add.l		d1,a1
+	mvs.w		(a0)+,d1
+	add.l		d0,a1
+	add.l		d1,a1
+	rts
+ewff_lil:
+	move.l		(a0)+,d1
+	add.l		d1,a1
+	move.l		(a0)+,d1
+	add.l		d0,a1
+	add.l		d1,a1
+	rts
+ewff_w0v:
+	mvs.w		(a0)+,d1
+	add.l		d0,a1
+	add.l		d1,a1
+	move.l		(a1),a1
+	rts
+ewff_wwv:
+	mvs.w		(a0)+,d1
+	add.l		d0,a1
+	add.l		d1,a1
+	move.l		(a1),a1
+	mvs.w		(a0)+,d0
+	add.l		d0,a1
+	rts
+ewff_wlv:
+	mvs.w		(a0)+,d1
+	add.l		d0,a1
+	add.l		d1,a1
+	move.l		(a1),a1
+	move.l		(a0)+,d0
+	add.l		d0,a1
+	rts
+ewff_l0v:
+	move.l		(a0)+,d1
+	add.l		d0,a1
+	add.l		d1,a1
+	move.l		(a1),a1
+	rts
+ewff_lwv:
+	move.l		(a0)+,d1
+	add.l		d0,a1
+	add.l		d1,a1
+	move.l		(a1),a1
+	mvs.w		(a0)+,d0
+	add.l		d0,a1
+	rts
+ewff_llv:
+	move.l		(a0)+,d1
+	add.l		d0,a1
+	add.l		d1,a1
+	move.l		(a1),a1
+	move.l		(a0)+,d0
+	add.l		d0,a1
+	rts
+ewff_w0n:
+	mvs.w		(a0)+,d1
+	add.l		d1,a1
+	move.l		(a1),a1
+	add.l		d0,a1
+	rts
+ewff_wwn:
+	mvs.w		(a0)+,d1
+	add.l		d1,a1
+	move.l		(a1),a1
+	mvs.w		(a0)+,d0
+	add.l		d0,a1
+	add.l		d0,a1
+	rts
+ewff_wln:
+	mvs.w		(a0)+,d1
+	add.l		d1,a1
+	move.l		(a1),a1
+	move.l		(a0)+,d0
+	add.l		d0,a1
+	add.l		d0,a1
+	rts
+ewff_l0n:
+	move.l		(a0)+,d1
+	add.l		d1,a1
+	move.l		(a1),a1
+	add.l		d0,a1
+	rts
+ewff_lwn:
+	move.l		(a0)+,d1
+	add.l		d1,a1
+	move.l		(a1),a1
+	mvs.w		(a0)+,d0
+	add.l		d0,a1
+	add.l		d0,a1
+	rts
+ewff_lln:
+	move.l		(a0)+,d1
+	add.l		d1,a1
+	move.l		(a1),a1
+	move.l		(a0)+,d0
+	add.l		d0,a1
+	add.l		d0,a1
+	rts
+/****************************************************************************************************************
+
diff --git a/firebeeV1/sources/exceptions.s b/firebeeV1/sources/exceptions.s
new file mode 100644
index 0000000..9f23af4
--- /dev/null
+++ b/firebeeV1/sources/exceptions.s
@@ -0,0 +1,799 @@
+/********************************************************/
+/*   exception vectoren intialisieren
+/********************************************************/
+
+.include "startcf.h"
+
+.extern ___Bas_base
+.extern ___SUP_SP
+.extern ___BOOT_FLASH
+.extern ___RAMBAR0
+.extern _rt_cacr
+.extern _rt_mod
+.extern _rt_ssp
+.extern _rt_usp
+.extern _rt_vbr
+.extern _illegal_instruction
+.extern _privileg_violation
+.extern _mmutr_miss
+.extern ___MBAR
+.extern ___MMUBAR
+.extern _video_tlb
+.extern _video_sbt
+.extern cpusha
+
+/* Register read/write macros */
+#define MCF_MMU_MMUCR            			___MMUBAR
+#define MCF_MMU_MMUOR                       ___MMUBAR+0x04
+#define MCF_MMU_MMUSR                       ___MMUBAR+0x08
+#define MCF_MMU_MMUAR                       ___MMUBAR+0x10
+#define MCF_MMU_MMUTR                       ___MMUBAR+0x14
+#define MCF_MMU_MMUDR                       ___MMUBAR+0x18  
+
+#define MCF_EPORT_EPPAR                     ___MBAR+0xF00
+#define MCF_EPORT_EPDDR                     ___MBAR+0xF04
+#define MCF_EPORT_EPIER                     ___MBAR+0xF05
+#define MCF_EPORT_EPDR                      ___MBAR+0xF08
+#define MCF_EPORT_EPPDR                     ___MBAR+0xF09
+#define MCF_EPORT_EPFR                      ___MBAR+0xF0C
+
+#define MCF_GPIO_PODR_FEC1L                 ___MBAR+0xA07
+
+#define MCF_PSC0_PSCTB_8BIT                 ___MBAR+0x860C
+
+#define MCF_PSC3_PSCRB_8BIT                 ___MBAR+0x890C
+#define MCF_PSC3_PSCTB_8BIT                 ___MBAR+0x890C
+
+.public	_vec_init
+
+//mmu ---------------------------------------------------
+/* Register read/write macros */
+#define MCF_MMU_MMUCR            			___MMUBAR
+#define MCF_MMU_MMUOR                       ___MMUBAR+0x04
+#define MCF_MMU_MMUSR                       ___MMUBAR+0x08
+#define MCF_MMU_MMUAR                       ___MMUBAR+0x10
+#define MCF_MMU_MMUTR                       ___MMUBAR+0x14
+#define MCF_MMU_MMUDR                       ___MMUBAR+0x18
+
+
+/* Bit definitions and macros for MCF_MMU_MMUCR */
+#define MCF_MMU_MMUCR_EN                     (0x1)
+#define MCF_MMU_MMUCR_ASM                    (0x2)
+
+/* Bit definitions and macros for MCF_MMU_MMUOR */
+#define MCF_MMU_MMUOR_UAA                    (0x1)
+#define MCF_MMU_MMUOR_ACC                    (0x2)
+#define MCF_MMU_MMUOR_RW                     (0x4)
+#define MCF_MMU_MMUOR_ADR                    (0x8)
+#define MCF_MMU_MMUOR_ITLB                   (0x10)
+#define MCF_MMU_MMUOR_CAS                    (0x20)
+#define MCF_MMU_MMUOR_CNL                    (0x40)
+#define MCF_MMU_MMUOR_CA                     (0x80)
+#define MCF_MMU_MMUOR_STLB                   (0x100)
+#define MCF_MMU_MMUOR_AA(x)                  (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_MMU_MMUSR */
+#define MCF_MMU_MMUSR_HIT                    (0x2)
+#define MCF_MMU_MMUSR_WF                     (0x8)
+#define MCF_MMU_MMUSR_RF                     (0x10)
+#define MCF_MMU_MMUSR_SPF                    (0x20)
+
+/* Bit definitions and macros for MCF_MMU_MMUAR */
+#define MCF_MMU_MMUAR_FA(x)                  (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_MMU_MMUTR */
+#define MCF_MMU_MMUTR_V                      (0x1)
+#define MCF_MMU_MMUTR_SG                     (0x2)
+#define MCF_MMU_MMUTR_ID(x)                  (((x)&0xFF)<<0x2)
+#define MCF_MMU_MMUTR_VA(x)                  (((x)&0x3FFFFF)<<0xA)
+
+/* Bit definitions and macros for MCF_MMU_MMUDR */
+#define MCF_MMU_MMUDR_LK                     (0x2)
+#define MCF_MMU_MMUDR_X                      (0x4)
+#define MCF_MMU_MMUDR_W                      (0x8)
+#define MCF_MMU_MMUDR_R                      (0x10)
+#define MCF_MMU_MMUDR_SP                     (0x20)
+#define MCF_MMU_MMUDR_CM(x)                  (((x)&0x3)<<0x6)
+#define MCF_MMU_MMUDR_SZ(x)                  (((x)&0x3)<<0x8)
+#define MCF_MMU_MMUDR_PA(x)                  (((x)&0x3FFFFF)<<0xA)
+
+#define	 std_mmutr	(MCF_MMU_MMUTR_SG|MCF_MMU_MMUTR_V)
+#define	 mmuord_d	(                   MCF_MMU_MMUOR_ACC|MCF_MMU_MMUOR_UAA)
+#define	 mmuord_i	(MCF_MMU_MMUOR_ITLB|MCF_MMU_MMUOR_ACC|MCF_MMU_MMUOR_UAA)
+#define	 wt_mmudr	(MCF_MMU_MMUDR_SZ(00)|MCF_MMU_MMUDR_CM(00)|MCF_MMU_MMUDR_R|MCF_MMU_MMUDR_W|MCF_MMU_MMUDR_X)
+#define	 cb_mmudr	(MCF_MMU_MMUDR_SZ(00)|MCF_MMU_MMUDR_CM(01)|MCF_MMU_MMUDR_R|MCF_MMU_MMUDR_W|MCF_MMU_MMUDR_X)
+#define	 nc_mmudr	(MCF_MMU_MMUDR_SZ(00)|MCF_MMU_MMUDR_CM(10)|MCF_MMU_MMUDR_R|MCF_MMU_MMUDR_W|MCF_MMU_MMUDR_X)
+//---------------------------------------------------
+/*********************************************************************
+*
+* General Purpose Timers (GPT)
+*
+*********************************************************************/
+
+/* Register read/write macros */
+#define MCF_GPT0_GMS                         ___MBAR+0x800
+
+/*********************************************************************
+*
+* Slice Timers (SLT)
+*
+*********************************************************************/
+
+#define MCF_SLT0_SCNT                        ___MBAR+0x908
+
+/**********************************************************/
+// macros
+/**********************************************************/
+irq:	.macro	vector,int_mask,clr_int
+		move.w	#0x2700,sr			// disable interrupt
+		subq.l	#8,a7
+		movem.l	d0/a5,(a7)			// register sichern
+		lea		MCF_EPORT_EPFR,a5
+		move.b	#clr_int,(a5)		// clear int pending
+// test auf protect mode ---------------------
+		move.b	DIP_SWITCHa,d0
+		btst	#7,d0 
+		bne		@irq_protect		// ja->
+// -------------------------------------------		
+		movem.l	(a7),d0/a5			// register zurück
+		addq.l	#8,a7
+		move.l	vector,-(a7)
+		move	#0x2\200,sr
+		rts
+@irq_protect:
+		move.l	usp,a5				// usp holen  
+		tst.b	_rt_mod				// supervisor? 
+		bne		@sev_supint			// ja -> 
+		mov3q.l	#-1,_rt_mod			// auf supervisor setzen
+		move.l	a5,_rt_usp			// rt_usp speichern 
+		move.l	_rt_ssp,a5			// rt_ssp holen
+#ifdef cf_stack
+		move.l	12(a7),-(a5)		// pc transferieren 
+		move.l	8(a7),-(a5)			// sr,vec
+#else
+		move.w	8(a7),-(a5)			// vector nr.
+		move.l	12(a7),-(a5)		// pc verschieben
+		move.w	10(a7),-(a5)		// sr verschieben
+#endif
+		bra		@irq_end
+@sev_supint:
+#ifdef cf_stack
+		move.l	12(a7),-(a5)		// pc transferieren 
+		move.l	8(a7),-(a5)			// sr,vec
+		bset	#5,2(a5)			// auf super setzen
+#else
+		move.w	8(a7),-(a5)			// vector nr.
+		move.l	12(a7),-(a5)		// pc verschieben
+		move.w	10(a7),-(a5)		// sr verschieben
+		bset	#5,(a5)				// auf super
+#endif
+@irq_end:
+		move.l	a5,usp				// usp setzen
+		lea		vector,a5
+		adda.l	_rt_vbr,a5
+		move.l	(a5),12(a7)			// vectoradresse eintragen
+		move.b	#int_mask,10(a7)	// intmaske setzen
+		movem.l	(a7),d0/a5			// register zurück
+		addq.l	#8,a7
+		rte							// und weg 
+		.endm
+/*********************************************************/
+.text
+_vec_init:
+ 		mov3q.l	#-1,_rt_mod			// rt_mod auf super
+ 		clr.l	_rt_ssp
+ 		clr.l	_rt_usp
+ 		clr.l	_rt_vbr
+		move.l	#___RAMBAR0,d0		// sind in rambar0
+		movec	d0,VBR
+		move.l	d0,a0
+		move.l	a0,a2
+init_vec:
+		move.l	#256,d0
+		lea		std_exc_vec(pc),a1		// standard vector
+init_vec_loop:
+		move.l	a1,(a2)+			// mal standard vector für alle setzen
+		subq.l	#1,d0
+		bne		init_vec_loop
+
+		move.l	#___SUP_SP,(a0)
+		lea		reset_vector(pc),a1
+		move.l	a1,0x04(a0)
+		lea		acess(pc),a1
+		move.l	a1,0x08(a0)
+		
+		move.b	DIP_SWITCHa,d0		// ++ vr
+		btst	#7,d0 
+		beq		no_protect_vectors
+		
+		lea		_illegal_instruction(pc),a1
+		move.l	a1,0x0c(a0)
+		lea		_illegal_instruction(pc),a1
+		move.l	a1,0x10(a0)
+		lea		zero_divide(pc),a1
+		move.l	a1,0x14(a0)
+		lea		_privileg_violation(pc),a1
+		move.l	a1,0x20(a0)
+		lea		linea(pc),a1
+  		move.l	a1,0x28(a0)
+		lea		linef(pc),a1
+  		move.l	a1,0x2c(a0)
+		lea		format(pc),a1
+ 		move.l	a1,0x38(a0)
+ 		
+ // floating point overflow
+ 		lea		flpoow(pc),a1
+  		move.l	a1,0xc0(a0)
+ 		lea		flpoow(pc),a1
+  		move.l	a1,0xc4(a0)
+ 		lea		flpoow(pc),a1
+  		move.l	a1,0xc8(a0)
+ 		lea		flpoow(pc),a1
+  		move.l	a1,0xcc(a0)
+ 		lea		flpoow(pc),a1
+  		move.l	a1,0xd0(a0)
+ 		lea		flpoow(pc),a1
+  		move.l	a1,0xd4(a0)
+ 		lea		flpoow(pc),a1
+  		move.l	a1,0xd8(a0)
+ 		lea		flpoow(pc),a1
+  		move.l	a1,0xdc(a0)
+no_protect_vectors:
+		
+
+// int 1-7
+		lea		irq1(pc),a1
+		move.l	a1,0x104(a0)
+		lea		irq2(pc),a1
+		move.l	a1,0x108(a0)
+		lea		irq3(pc),a1
+		move.l	a1,0x10c(a0)
+		lea		irq4(pc),a1
+		move.l	a1,0x110(a0)
+		lea		irq5(pc),a1
+		move.l	a1,0x114(a0)
+		lea		irq6(pc),a1
+		move.l	a1,0x118(a0)
+		lea		irq7(pc),a1
+		move.l	a1,0x11c(a0)
+//psc_vectors
+		lea		psc3(pc),a1
+		move.l	a1,0x180(a0)
+//timer 1 vectors
+		lea		timer0(pc),a1
+		move.l	a1,0x1f8(a0)
+		rts
+/********************************************************/
+/*   exception vector routinen
+/********************************************************/
+vector_table_start:
+std_exc_vec:
+		move.w	#0x2700,sr			// disable interrupt
+		subq.l	#8,a7
+		movem.l	d0/a5,(a7)			// register sichern
+// test auf protect mode -------------------------------
+		move.b	DIP_SWITCHa,d0
+		btst	#7,d0 
+		bne		stv_protect			// ja->
+//------------------------------------------------------
+		move.w	8(a7),d0			// vector holen
+		and.l	#0x3fc,d0			// vector nummer ausmaskieren
+		add.l	_rt_vbr,d0			// + basis
+		move.l	d0,a5
+		move.l	(a5),d0
+		move.l	4(a7),a5			// a5 zurück
+		move.l	d0,4(a7)
+		move.w	10(a7),d0
+		bset	#13,d0				// super
+		move.w	d0,sr				// orginal sr wert in super setzen
+		move.l	(a7)+,d0			// d0 zurück
+		rts
+stv_protect:
+		move.l	usp,a5				// usp holen  
+		tst.b	_rt_mod				// supervisor? 
+		bne		sev_sup				// ja -> 
+		mov3q.l	#-1,_rt_mod			// auf supervisor setzen
+		move.l	a5,_rt_usp			// rt_usp speichern 
+		move.l	_rt_ssp,a5			// rt_ssp holen
+#ifdef cf_stack
+		move.l	12(a7),-(a5)		// pc transferieren 
+		move.l	8(a7),d0			// sr holen
+		move.l	d0,-(a5)			// sr transferieren 
+		swap	d0					// vec -> lw
+#else
+		move.w	8(a7),d0			// vector holen
+		move.w	d0,-(a5)			// ablegen
+		move.l	12(a7),-(a5)		// pc transferieren 
+		move.w	10(a7),-(a5)		// sr transferieren
+#endif
+		move.l	a5,usp				// usp setzen
+		and.l	#0x3fc,d0			// vector nummer ausmaskieren
+		add.l	_rt_vbr,d0			// + basis
+		move.l	d0,a5
+		move.l	(a5),12(a7)			// hier geht's weiter
+		movem.l	(a7),d0/a5			// register zurück
+		addq.l	#8,a7
+		rte							// und weg 
+sev_sup:
+#ifdef cf_stack
+		move.l	12(a7),-(a5)		// pc transferieren 
+		move.l	8(a7),d0			// sr holen
+		bset	#13,d0				// war aus rt super
+		move.l	d0,-(a5)			// sr transferieren 
+		swap	d0					// vec -> lw
+#else
+		move.w	8(a7),d0			// vector holen
+		move.w	d0,-(a5)			// ablegen
+		move.l	12(a7),-(a5)		// pc transferieren 
+		move.w	10(a7),-(a5)		// sr transferieren
+		bset	#5,(a5)				// war aus super
+#endif
+		move.l	a5,usp				// usp setzen
+		and.l	#0x3fc,d0			// vector nummer ausmaskieren
+		add.l	_rt_vbr,d0			// + basis
+		move.l	d0,a5
+		move.l	(a5),12(a7)			// hier geht's weiter
+		movem.l	(a7),d0/a5			// register zurück
+		addq.l	#8,a7
+		rte							// und weg 
+//*******************************************
+reset_vector:
+		move.w	#0x2700,sr			// disable interrupt
+		move.l	#0x31415926,d0
+		cmp.l	0x426,d0			// reset vector gültg?
+		beq		std_exc_vec			// ja->
+		jmp		___BOOT_FLASH 		// sonst kaltstart
+acess:
+		move.w	#0x2700,sr			// disable interrupt
+		move.l	d0,-(sp)			// ++ vr
+		move.w	4(sp),d0
+		andi.l	#0x0c03,d0
+		cmpi.l	#0x0401,d0
+		beq		access_mmu
+		cmpi.l	#0x0402,d0
+		beq		access_mmu
+		cmpi.l	#0x0802,d0
+		beq		access_mmu
+		cmpi.l	#0x0c02,d0
+		beq		access_mmu
+		bra		bus_error
+access_mmu:
+		move.l	MCF_MMU_MMUSR,d0
+		btst	#1,d0
+		bne		bus_error
+		move.l	MCF_MMU_MMUAR,d0
+		cmp.l	#___Bas_base,d0		// max User RAM Bereich
+		bge		bus_error			// grösser -> bus error
+		bra		_mmutr_miss
+bus_error:
+		move.l	(sp)+,d0
+		bra		std_exc_vec
+		
+zero_divide:
+		move.w	#0x2700,sr			// disable interrupt
+		move.l	a0,-(a7)
+		move.l	d0,-(a7)
+		move.l	12(a7),a0			// pc
+		move.w	(a0)+,d0			// befehlscode
+		btst	#7,d0				// long?
+		beq		zd_word				// nein->
+		addq.l	#2,a0
+zd_word:
+		and.l	0x3f,d0				// ea ausmaskieren
+		cmp.w	#0x08,d0			// -(ax) oder weniger
+		ble		zd_end
+		addq.l	#2,a0
+		cmp.w	#0x39,d0			// xxx.L
+		bne		zd_nal
+		addq.l	#2,a0
+		bra		zd_end
+zd_nal:	cmp.w	#0x3c,d0			// immediate?
+		bne		zd_end				// nein->
+		btst	#7,d0				// long?
+		beq		zd_end				// nein
+		addq.l	#2,a0
+zd_end:
+		move.l	a0,12(a7)
+		move.l	(a7)+,d0
+		move.l	(a7)+,a0		
+		rte
+		
+linea:	
+		move.w	#0x2700,sr			// disable interrupt
+		halt
+		nop
+		nop
+linef:	
+		move.w	#0x2700,sr			// disable interrupt
+		halt
+		nop
+		nop
+format:
+		move.w	#0x2700,sr			// disable interrupt
+		halt
+		nop
+		nop
+//floating point		
+flpoow:
+		move.w	#0x2700,sr			// disable interrupt
+		halt
+		nop
+		nop
+irq1:
+		irq		0x64,1,0x02
+irq2:				//vsync
+								//		move.b	#3,2(a7)
+								//		rte
+		irq		0x68,2,0x04
+irq3:
+		irq		0x6c,3,0x08
+irq4:				// vsync
+		irq		0x70,4,0x10
+irq5:				// acp
+		irq		0x74,5,0x20
+irq6:				// mfp
+		move.w	#0x2700,sr			// disable interrupt
+		subq.l	#8,a7
+		movem.l	d0/a5,(a7)			// register sichern
+		lea		MCF_EPORT_EPFR,a5
+		move.b	#0x40,(a5)			// clear int6
+// test auf timeout screen adr change -------------------------------------------------------
+		move.l	_video_sbt,d0
+  		beq		irq6_non_sca		// wenn 0 nichts zu tun
+  		sub.l	#0x70000000,d0		// 14 sec abzählen
+		lea		MCF_SLT0_SCNT,a5
+  		cmp.l	(a5),d0				// aktuelle zeit weg
+  		ble		irq6_non_sca		// noch nicht abgelaufen
+  		lea		-28(a7),a7
+  		movem.l	d0-d4/a0-a1,(a7)	// register sichern
+  		clr.l	d3					// beginn mit 0
+		bsr		cpusha				// cache leeren
+ // eintrag suchen
+ irq6_next_sca:
+ 		move.l	d3,d0
+		move.l	d0,MCF_MMU_MMUAR	// addresse
+ 		move.l	#0x106,d4
+ 		move.l	d4,MCF_MMU_MMUOR	// suchen -> 
+ 		nop
+ 		move.l	MCF_MMU_MMUOR,d4
+ 		clr.w	d4
+ 		swap	d4
+ 		move.l	d4,MCF_MMU_MMUAR
+		mvz.w	#0x10e,d4
+ 		move.l	d4,MCF_MMU_MMUOR	// einträge holen aus mmu
+ 		nop
+ 		move.l	MCF_MMU_MMUTR,d4	// ID holen
+ 		lsr.l	#2,d4				// bit 9 bis 2
+ 		cmp.w	#sca_page_ID,d4		// ist screen change ID?
+ 		bne		irq6_sca_pn			// nein -> page keine screen area next
+// eintrag ändern 		
+		add.l	#std_mmutr,d0
+		move.l	d3,d1				// page 0?
+		beq		irq6_sca_pn0		// ja ->
+		add.l	#cb_mmudr,d1		// sonst page cb
+		bra		irq6_sca_pn1c
+irq6_sca_pn0:
+		add.l	#wt_mmudr|MCF_MMU_MMUDR_LK,d1	// page wt and locked
+irq6_sca_pn1c:
+		mvz.w	#0x10b,d2			// MMU update 
+		move.l	d0,MCF_MMU_MMUTR	
+		move.l	d1,MCF_MMU_MMUDR
+		move.l	d2,MCF_MMU_MMUOR	// setze tlb data only  
+		nop
+// page copy
+		move.l	d3,a0
+		add.l	#0x60000000,a0
+		move.l	d3,a1
+		move.l	#0x10000,d4			// die ganze page
+irq6_vcd0_loop:						
+		move.l	(a0)+,(a1)+			// page copy
+		move.l	(a0)+,(a1)+
+		move.l	(a0)+,(a1)+
+		move.l	(a0)+,(a1)+
+		subq.l	#1,d4
+		bne		irq6_vcd0_loop
+		nop
+irq6_sca_pn:
+		add.l	#0x00100000,d3		// next
+		cmp.l	#0x00d00000,d3		// ende?
+		blt		irq6_next_sca		// nein->
+
+		move.l	#0x2000,d0
+		move.l	d0,_video_tlb		// anfangszustand wieder herstellen
+  		clr.l	_video_sbt			// zeit löschen
+
+  		movem.l	(a7),d0-d4/a0-a1	// register zurück
+  		lea		28(a7),a7
+irq6_non_sca:
+// test auf acsi dma -----------------------------------------------------------------
+		lea		0xfffffa0b,a5
+ 		bset	#7,-4(a5)			// int ena
+		btst.b	#7,(a5)				// acsi dma int?
+		beq		non_acsi_dma
+		bsr		acsi_dma
+non_acsi_dma:
+// ----------------------------------------------------------------------------------
+		tst.b	(a5)
+		bne		irq6_1
+		tst.b	2(a5)
+		bne		irq6_1
+		movem.l	(a7),d0/a5
+		addq.l	#8,a7
+		rte	
+irq6_1:
+		lea		MCF_GPIO_PODR_FEC1L,a5
+		bclr.b	#4,(a5)					// led on
+		lea		blinker(pc),a5
+		addq.l	#1,(a5)					// +1
+		move.l	(a5),d0
+		and.l	#0x80,d0
+		bne		irq6_2
+		lea		MCF_GPIO_PODR_FEC1L,a5
+		bset.b	#4,(a5)					// led off
+irq6_2:
+// test auf protect mode ---------------------
+		move.b	DIP_SWITCHa,d0
+		btst	#7,d0 
+		bne		irq6_3				// ja->
+// -------------------------------------------		
+		move.l	0xF0020000,a5		// vector holen
+		add.l	_rt_vbr,a5			// basis
+		move.l	(a5),d0				// vector holen
+		move.l	4(a7),a5			// a5 zurück
+		move.l	d0,4(a7)			// vector eintragen
+		move.l	(a7)+,d0			// d0 zurück
+		move	#0x2600,sr
+		rts
+irq6_3:
+		move.l	usp,a5				// usp holen  
+		tst.b	_rt_mod				// supervisor? 
+		bne		sev_sup6			// ja -> 
+		mov3q.l	#-1,_rt_mod			// auf supervisor setzen
+		move.l	a5,_rt_usp			// rt_usp speichern 
+		move.l	_rt_ssp,a5			// rt_ssp holen
+#ifdef cf_stack
+		move.l	12(a7),-(a5)		// pc transferieren 
+		move.l	8(a7),-(a5)			// sr transferieren 
+#else
+		move.w	8(a7),-(a5)			// vector transferieren
+		move.l	12(a7),-(a5)		// pc transferieren 
+		move.w	10(a7),-(a5)		// sr transferieren
+#endif
+		move.l	a5,usp				// usp setzen
+		move.l  0xF0020000,a5		// vector holen: intack routine
+		add.l	_rt_vbr,a5			// virtuelle VBR des Systems
+		move.l	(a5),12(a7)			// hier gehts weiter
+		movem.l	(a7),d0/a5			// register zurück
+		addq.l	#8,a7
+		move.b	#6,2(a7)			// intmaske setzen
+		rte 						// und weg 
+sev_sup6:
+#ifdef cf_stack
+		move.l	12(a7),-(a5)		// pc transferieren 
+		move.l	8(a7),-(a5)			// sr,vec
+		bset	#5,2(a5)			// auf super setzen
+#else
+		move.w	8(a7),-(a5)			// vector nr.
+		move.l	12(a7),-(a5)		// pc verschieben
+		move.w	10(a7),-(a5)		// sr verschieben
+		bset	#5,(a5)				// auf super
+#endif
+		move.l	a5,usp				// usp setzen
+		move.l  0xF0020000,a5		// vector holen: intack routine
+		add.l	_rt_vbr,a5			// virtuelle VBR des Systems
+		move.l	(a5),12(a7)			// hier gehts weiter
+		movem.l	(a7),d0/a5			// register zurück
+		rts
+blinker:.long	0
+/**************************************************/
+/* pseudo dma */
+/**************************************************/
+acsi_dma:				// atari dma
+		move.l  a1,-(a7)
+		move.l  d1,-(a7)
+		
+	lea	MCF_PSC0_PSCTB_8BIT,a1		// ++ vr
+	move.l	#'DMA ',(a1)
+	move.l	#'INT!',(a1)
+
+		lea 	0xf0020110,a5		// fifo daten
+acsi_dma_start:
+		move.l	-12(a5),a1			// dma adresse
+		move.l	-8(a5),d0			// byt counter
+     	ble		acsi_dma_end
+     	btst.b	#0,-16(a5)			// write? (dma modus reg)
+		bne		acsi_dma_wl			// ja->
+acsi_dma_rl:
+ 		tst.b	-4(a5) 				// dma req?
+  		bpl		acsi_dma_fertig		// nein->
+		move.l	(a5),(a1)+			// read 4 bytes	 
+		move.l	(a5),(a1)+			// read 4 bytes	 
+		move.l	(a5),(a1)+			// read 4 bytes	 
+		move.l	(a5),(a1)+			// read 4 bytes	
+		
+ 		moveq	#'.',d1
+ 		move.b	d1,MCF_PSC0_PSCTB_8BIT
+
+		sub.l	#16,d0				// byt counter -16
+ 		bpl		acsi_dma_rl
+		bra		acsi_dma_fertig	
+acsi_dma_wl:
+ 		tst.b	-4(a5) 				// dma req?
+  		bpl		acsi_dma_fertig		// nein->
+		move.l	(a1)+,(a5)			// write 4 byts
+		move.l	(a1)+,(a5)			// write 4 byts
+		move.l	(a1)+,(a5)			// write 4 byts
+		move.l	(a1)+,(a5)			// write 4 byts
+		
+ 		moveq	#'.',d1
+ 		move.b	d1,MCF_PSC0_PSCTB_8BIT
+
+		sub.l	#16,d0				// byt counter -16
+		bpl		acsi_dma_wl
+acsi_dma_fertig:
+		move.l	a1,-12(a5)			// adresse zurück
+		move.l	d0,-8(a5)			// byt counter zurück
+acsi_dma_end:
+		tst.b	-4(a5) 				// dma req?
+ 		bmi		acsi_dma_start		// ja->
+		lea		0xfffffa0b,a5
+		bclr.b	#7,4(a5)			// clear int in service mfp
+		bclr.b	#7,(a5)				// clear int pending mfp 0xfffffa0b
+	
+		move.w	#0x0d0a,d1
+		move.w	d1,MCF_PSC0_PSCTB_8BIT
+		
+		move.l	(a7)+,d1
+		move.l	(a7)+,a1
+		rts
+/**************************************************/
+/* irq 7 = pseudo bus error */
+/**************************************************/
+irq7:
+		lea			-12(sp),sp
+		movem.l		d0/a0,(sp)
+
+		move.l		___RAMBAR0+0x008,a0	// Real Access Error handler
+		move.l		a0,8(sp)			// This will be the return address for rts
+
+		move.w		12(sp),d0			// Format/Vector word
+		andi.l		#0xf000,d0			// Keep only the Format
+		ori.l		#2*4,d0				// Simulate Vector #2, no Fault
+		move.w		d0,12(sp)
+
+		// TODO: Inside an interrupt handler, 16(sp) is the return address.
+		// For an Access Error, it should be the address of the fault instruction instead
+
+		lea			MCF_EPORT_EPFR,a0
+		move.b		#0x80,(a0)			// clear int7
+		move.l		(sp)+,d0
+		move.l		(sp)+,a0
+		rts								// Forward to the Access Error handler
+
+/**************************************************/
+/* psc3 com PIC MCF */
+/**************************************************/
+psc3:
+		move.w	#0x2700,sr			// disable interrupt
+		lea		-20(a7),a7
+		movem.l	d0-d2/a0/a3,(a7)	
+		lea		MCF_PSC3_PSCRB_8BIT,a3
+		move.b	(a3),d1
+		cmp.b	#2,d1				// anforderung rtc daten?
+		bne		psc3_fertig
+
+	lea	MCF_PSC0_PSCTB_8BIT,a0		// ++ vr
+	move.l	#'PIC ',(a0)
+	move.l	#'INT ',(a0)
+	move.l	#'RTC!',(a0)
+	move.l	#0x0d0a,(a0)
+
+		lea		0xffff8961,a0
+		lea		MCF_PSC3_PSCTB_8BIT,a3
+		clr.l	d1	
+		moveq	#64,d2
+		move.b	#0x82,(a3)			// header: rtcd mcf->pic
+loop_sr2:
+		move.b  d1,(a0)
+		move.b	2(a0),d0
+		move.b	d0,(a3)
+		addq.l	#1,d1
+		cmp.b	d1,d2
+		bne		loop_sr2
+psc3_fertig:
+		movem.l	(a7),d0-d2/a0/a3	// register zurück
+		lea		20(a7),a7
+		RTE
+/**************************************************/
+/* timer 0: video change later also others
+/**************************************************/
+timer0:
+		move	#0x2700,sr
+//		halt
+		lea		-28(a7),a7
+		movem.l	d0-d4/a0-a1,(a7)
+		mvz.b	0xffff8201,d0		// löschen und high byt
+		cmp.w	#2,d0
+		blt		video_chg_end
+		cmp.w	#0xd0,d0			// normale addresse
+		blt		sca_other			// nein->
+		lea		MCF_SLT0_SCNT,a0
+  		move.l	(a0),d4
+		move.l	d4,_video_sbt		// time sichern
+sca_other:
+		lsl.l	#8,d0				
+		move.b	0xffff8203,d0		// mid byt
+		lsl.l	#8,d0
+		move.b  0xffff820d,d0		// low byt
+		move.l	d0,d3
+video_chg_1page:
+// test ob page schon gesetzt
+		moveq	#20,d4
+		move.l	d0,d2
+		lsr.l	d4,d2				// neue page
+		move.l	_video_tlb,d4
+		bset.l	d2,d4				// setzen als geändert
+		bne		video_chg_2page		// schon gesetzt gewesen? ja->weg
+		move.l	d4,_video_tlb
+		bsr		cpusha				// cache leeren
+// daten copieren 
+video_copy_data:
+		move.l	d4,_video_tlb
+		and.l	#0x00f00000,d0
+		move.l	d0,a0
+		move.l	a0,a1
+		add.l	#0x60000000,a1
+		move.l	#0x10000,d4			// die ganze page
+video_copy_data_loop:
+		move.l	(a0)+,(a1)+
+		move.l	(a0)+,(a1)+
+		move.l	(a0)+,(a1)+
+		move.l	(a0)+,(a1)+
+		subq.l	#1,d4
+		bne		video_copy_data_loop
+// eintrag suchen
+		move.l	d0,MCF_MMU_MMUAR	// addresse
+ 		move.l	#0x106,d4
+ 		move.l	d4,MCF_MMU_MMUOR	// suchen -> schlägt neuen vor wenn keiner
+ 		nop
+ 		move.l	MCF_MMU_MMUOR,d4
+ 		clr.w	d4
+ 		swap	d4
+ 		move.l	d4,MCF_MMU_MMUAR
+		move.l	d0,d1
+		add.l	#MCF_MMU_MMUTR_ID(sca_page_ID)|std_mmutr,d0
+		add.l	#0x60000000|wt_mmudr|MCF_MMU_MMUDR_LK,d1
+		mvz.w	#0x10b,d2								// MMU update 
+		move.l	d0,MCF_MMU_MMUTR		
+		move.l	d1,MCF_MMU_MMUDR
+		move.l	d2,MCF_MMU_MMUOR					// setzen vidoe maped to 60xxx only data  
+		nop
+video_chg_2page:
+// test ob evt. anschliessende page gesetzt werden muss
+		move.l	d3,d0
+		mvz.w	0xffff8210,d4		// byts pro zeile
+		mvz.w	0xffff82aa,d2		// zeilen ende
+		mvz.w	0xffff82a8,d1		// zeilenstart
+		sub.l	d1,d2				// differenz = anzahl zeilen
+		mulu	d2,d4				// maximal 480 zeilen
+		add.l	d4,d0				// video grösse
+		cmp.l	#0xe00000,d0		// maximale addresse
+		bge		video_chg_end		// wenn gleich oder grösser -> fertig
+		moveq	#20,d4
+		move.l	d0,d2
+		lsr.l	d4,d2				// neue page
+		move.l	_video_tlb,d4
+		bset.l	d2,d4				// setzen als geändert
+		beq		video_copy_data		// nein nochmal
+video_chg_end:
+// int pending löschen
+		lea		MCF_GPT0_GMS,a0
+		bclr.b	#0,3(a0)
+		nop
+		bset.b	#0,3(a0)
+
+		movem.l	(a7),d0-d4/a0-a1
+		lea		28(a7),a7
+//--------------------------------------------------------------------------------------------------------
+		RTE
+
diff --git a/firebeeV1/sources/ii_add.h b/firebeeV1/sources/ii_add.h
new file mode 100644
index 0000000..bc23f63
--- /dev/null
+++ b/firebeeV1/sources/ii_add.h
@@ -0,0 +1,581 @@
+//--------------------------------------------------------------------
+// add
+//--------------------------------------------------------------------
+/*****************************************************************************************/
+//--------------------------------------------------------------------
+// byt
+//--------------------------------------------------------------------
+//--------------------------------------------------------------------
+// add.b	#im,dx
+//--------------------------------------------------------------------
+addbir_macro:.macro
+	move.w		(a0)+,d0
+	extb.l		d0
+	mvs.b		\2,d1
+	add.l		d0,d1
+	set_cc0
+	move.b		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // add	ea,dx
+//--------------------------------------------------------------------
+adddd:.macro
+#ifdef	halten_add
+	halt
+#endif
+	mvs.\3		\1,d0
+	mvs.\3		\2,d1
+	add.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // add	ea,dx (first ea->a1 z.B. für a0,a1,USP)
+//--------------------------------------------------------------------
+addddd:.macro
+#ifdef	halten_add
+	halt
+#endif
+	move.l		\1,a1
+	mvs.\3		a1,d0
+	mvs.\3		\2,d1
+	add.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // add	(ea),dx (first ea->a1 z.B. für a0,a1,USP)
+//--------------------------------------------------------------------
+adddda:.macro
+#ifdef	halten_add
+	halt
+#endif
+	move.l		\1,a1
+	mvs.\3		(a1),d0
+	mvs.\3		\2,d1
+	add.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // add	(ay)+,dx (first ea->a1 z.B. für a0,a1,USP)
+//--------------------------------------------------------------------
+addddai:.macro
+#ifdef	halten_add
+	halt
+#endif
+	move.l		\1,a1
+	mvs.\3		(a1)+,d0
+	move.l		a1,\1
+	mvs.\3		\2,d1
+	add.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // add	-(ay),dx (first ea->a1 z.B. für a0,a1,USP)
+//--------------------------------------------------------------------
+addddad:.macro
+#ifdef	halten_add
+	halt
+#endif
+	move.l		\1,a1
+	mvs.\3		-(a1),d0
+	move.l		a1,\1
+	mvs.\3		\2,d1
+	add.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // add	d16(ay),dx
+//--------------------------------------------------------------------
+addd16ad:.macro
+#ifdef	halten_add
+	halt
+#endif
+	move.l		\1,a1
+	mvs.w		(a0)+,d0
+	add.l		d0,a1
+	mvs.\3		(a1),d0		
+	mvs.\3		\2,d1
+	add.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // add	d8(ay,dy),dx
+//--------------------------------------------------------------------
+addd8ad:.macro
+#ifdef	halten_add
+	halt
+#endif
+	move.l		\1,a1
+	jsr			ewf
+.ifc	\3,l
+	move.l		(a1),d0
+	move.l		\2,d1
+.else
+	mvs.\3		(a1),d0
+	mvs.\3		\2,d1
+.endif
+	add.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // add	xxx.w,dx
+//--------------------------------------------------------------------
+addxwd:.macro
+#ifdef	halten_add
+	halt
+#endif
+	move.w		(a0)+,a1
+	mvs.\3		(a1),d0
+	mvs.\3		\2,d1
+	add.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // add	xxx.l,dx
+//--------------------------------------------------------------------
+addxld:.macro
+#ifdef	halten_add
+	halt
+#endif
+	move.l		(a0)+,a1
+	mvs.\3		(a1),d0
+	mvs.\3		\2,d1
+	add.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // add	d16(pc),dx
+//--------------------------------------------------------------------
+addd16pcd:.macro
+#ifdef	halten_add
+	halt
+#endif
+	move.l		a0,a1
+	mvs.w		(a0)+,d0
+	add.l		d0,a1
+	mvs.\3		(a1),d0
+	mvs.\3		\2,d1
+	add.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // add	d8(pc,dy),dx
+//--------------------------------------------------------------------
+addd8pcd:.macro
+#ifdef	halten_add
+	halt
+#endif
+	move.l		a0,a1
+	jsr			ewf
+.ifc	\3,l
+	move.l		(a1),d0
+	move.l		\2,d1
+.else
+	mvs.\3		(a1),d0
+	mvs.\3		\2,d1
+.endif
+	add.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+//  add dy,ea
+//--------------------------------------------------------------------
+//--------------------------------------------------------------------
+// // add	dx,(ay)  (first ea->a1 z.B. für a0,a1,USP)
+//--------------------------------------------------------------------
+addeda:.macro
+#ifdef	halten_add
+	halt
+#endif
+	mvs.\3		\1,d0
+	move.l		\2,a1
+	mvs.\3		(a1),d1
+	add.l		d0,d1
+	set_cc0
+	move.\3		d1,(a1)
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // add	dx,(ay)+  (first ea->a1 z.B. für a0,a1,USP)
+//--------------------------------------------------------------------
+addedai:.macro
+#ifdef	halten_add
+	halt
+#endif
+	mvs.\3		\1,d0
+	move.l		\2,a1
+	mvs.\3		(a1),d1
+	add.l		d0,d1
+	set_cc0
+	move.\3		d1,(a1)+
+	move.l		a1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // add	dx,(ay)+  
+//--------------------------------------------------------------------
+addedaid:.macro
+#ifdef	halten_add
+	halt
+#endif
+	mvs.\3		\1,d0
+	mvs.\3		\2,d1
+	add.l		d0,d1
+	set_cc0
+	move.\3		d1,\2+
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // add	dx,-(ay)
+//--------------------------------------------------------------------
+addedad:.macro
+#ifdef	halten_add
+	halt
+#endif
+	mvs.\3		\1,d0
+	move.l		\2,a1
+	mvs.\3		-(a1),d1
+	move.l		a1,\2
+	add.l		d0,d1
+	set_cc0
+	move.\3		d1,(a1)
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // add	dx,-(ay)
+//--------------------------------------------------------------------
+addedadd:.macro
+#ifdef	halten_add
+	halt
+#endif
+	mvs.\3		\1,d0
+	mvs.\3		-\2,d1
+	add.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // add	dx,d16(ay)
+//--------------------------------------------------------------------
+adde16ad:.macro
+#ifdef	halten_add
+	halt
+#endif
+	mvs.\3		\1,d0
+	move.l		\2,a1
+	mvs.w		(a0)+,d1
+	add.l		d1,a1
+	mvs.\3		(a1),d1		
+	add.l		d0,d1
+	set_cc0
+	move.\3		d1,(a1)
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // add.w	d8(ay,dy),dx
+//--------------------------------------------------------------------
+adde8ad:.macro
+#ifdef	halten_add
+	halt
+#endif
+	move.l		\2,a1
+	jsr			ewf
+.ifc	\3,l
+	move.l		(a1),d1
+	move.l		\1,d0
+.else
+	mvs.\3		(a1),d1
+	mvs.\3		\1,d0
+.endif
+	add.l		d0,d1
+	set_cc0
+	move.\3		d1,(a1)
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // add	dx,xxx.w
+//--------------------------------------------------------------------
+addxwe:.macro
+#ifdef	halten_add
+	halt
+#endif
+	mvs.\3		\1,d0
+	move.w		(a0)+,a1
+	mvs.\3		(a1),d1
+	add.l		d0,d1
+	set_cc0
+	move.\3		d1,(a1)
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // add	dx,xxx.l
+//--------------------------------------------------------------------
+addxle:.macro
+#ifdef	halten_add
+	halt
+#endif
+	mvs.\3		\1,d0
+	move.l		(a0)+,a1
+	mvs.\3		(a1),d1
+	add.l		d0,d1
+	set_cc0
+	move.\3		d1,(a1)
+	ii_end
+	.endm;
+/******************************************************/
+// adress register
+/******************************************************/
+//--------------------------------------------------------------------
+// // adda.w	ea,ax (ea = dx;ax;(ax);(ax)+,-(ax)
+//--------------------------------------------------------------------
+addaw:.macro
+#ifdef	halten_add
+	halt
+#endif
+	move.l		a0,pc_off(a7)			// pc auf next
+	movem.l		(a7),d0/d1/a0/a1		// register zurpück
+	mvs.w		\1,d0
+	adda.l		d0,\2
+	move.l		d0_off(a7),d0
+	lea			ii_ss(a7),a7			// stack erhöhen
+	rte
+	.endm;
+//--------------------------------------------------------------------
+// add.w ea,usp
+//--------------------------------------------------------------------
+addawa7:.macro
+#ifdef	halten_add
+	halt
+#endif
+	mvs.w		\1,d0
+	move.l		usp,a1
+	add.l		d0,a1
+	move.l		a1,usp
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // adda.w	ea,usp (ea = dx;ax;(ax);(ax)+,-(ax)
+//--------------------------------------------------------------------
+addawu:.macro
+#ifdef	halten_add
+	halt
+#endif
+	move.l		a0,pc_off(a7)			// pc auf next
+	movem.l		(a7),d0/d1/a0/a1		// register zurpück
+	move.l		a7,_a7_save
+	move.l		usp,a7
+	move.l		\1,d0
+	adda.l		d0,\2
+	move.l		a7,usp
+	move.l		_a7_save,a7
+	move.l		d0_off(a7),d0
+	lea			ii_ss(a7),a7			// stack erhöhen
+	rte
+	.endm;
+//--------------------------------------------------------------------
+// // adda.w	ea,usp (ea = a7 => dx;ax;(ax);(ax)+,-(ax)
+//--------------------------------------------------------------------
+addawua7:.macro
+	addawu		\1,\2
+	.endm;
+//--------------------------------------------------------------------
+// // adda.w	d16(ay),ax
+//--------------------------------------------------------------------
+addawd16a:.macro
+#ifdef	halten_add
+	halt
+#endif
+	move.l		\1,a1
+	mvs.w		(a0)+,d0
+	adda.l		d0,a1
+	mvs.w		(a1),d0
+	move.l		\2,a1
+	add.l		d0,a1
+	move.l		a1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // adda.w	d8(ay,dy),ax
+//--------------------------------------------------------------------
+addawd8a:.macro
+#ifdef	halten_add
+	halt
+#endif
+	move.l		\1,a1
+	jsr			ewf
+	mvs.w		(a1),d0
+	move.l		\2,a1
+	add.l		d0,a1
+	move.l		a1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // adda.w	xxx.w,ax
+//--------------------------------------------------------------------
+addawxwax:.macro
+#ifdef	halten_add
+	halt
+#endif
+	move.w		\1,a1
+	mvs.w		(a1),d0
+	move.l		\2,a1
+	adda.l		d0,a1
+	move.l		a1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // adda.w	xxx.l,ax
+//--------------------------------------------------------------------
+addawxlax:.macro
+#ifdef	halten_add
+	halt
+#endif
+	move.l		\1,a1
+	mvs.w		(a1),d0
+	move.l		\2,a1
+	adda.l		d0,a1
+	move.l		a1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // adda.w	d16(pc),ax
+//--------------------------------------------------------------------
+addawd16pcax:.macro
+#ifdef	halten_add
+	halt
+#endif
+	move.w		\1,a1
+	adda.l		a0,a1
+	mvs.w		(a1),d0
+	move.l		\2,a1
+	adda.l		d0,a1
+	move.l		a1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // adda.w	d8(pc,dy),ax
+//--------------------------------------------------------------------
+addawd8pcax:.macro
+#ifdef	halten_add
+	halt
+#endif
+	move.l		a0,a1
+	jsr			ewf
+	mvs.w		(a1),d0
+	move.l		\2,a1
+	adda.l		d0,a1
+	move.l		a1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // adda.w	#im,ax
+//--------------------------------------------------------------------
+addawim:.macro
+#ifdef	halten_add
+	halt
+#endif
+	mvs.w		\1,d0
+	move.l		\2,a1
+	adda.l		d0,a1
+	move.l		a1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // adda.l	d8(ay,dy),ax
+//--------------------------------------------------------------------
+addald8a:.macro
+#ifdef	halten_add
+	halt
+#endif
+	move.l		\1,a1
+	jsr			ewf
+	move.l		(a1),d0
+	move.l		\2,a1
+	adda.l		d0,a1
+	move.l		a1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // adda.l	d8(pc,dy),ax
+//--------------------------------------------------------------------
+addakd8pcax:.macro
+#ifdef	halten_add
+	halt
+#endif
+	move.l		a0,a1
+	jsr			ewf
+	move.l		(a1),d0
+	move.l		\2,a1
+	adda.l		d0,a1
+	move.l		a1,\2
+	ii_end
+	.endm;
+//*****************************************************************************************
+// addx 
+//*****************************************************************************************
+//--------------------------------------------------------------------
+// // addx	dy,dx
+//--------------------------------------------------------------------
+adddx:.macro
+#ifdef	halten_add
+	halt
+#endif
+	move.b		sr_off+1(a7),d0			//ccr holen
+	move		d0,ccr					//setzen		
+	mvs.\3		\2,d0
+	mvs.\3		\1,d1
+	addx.l		d0,d1
+	set_cc0
+	move.\3		d1,\1
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // addx	-(ay),-(ax)
+//--------------------------------------------------------------------
+adddax:.macro
+#ifdef	halten_add
+	halt
+#endif
+	move.b		sr_off+1(a7),d0			//ccr holen
+	move		d0,ccr					//setzen		
+	move.l		\1,a1
+.ifc	\3,l
+	move.l		-(a1),d0
+.else
+	mvs.\3		-(a1),d0
+.endif
+	move.l		\2,a1
+.ifc	\3,l
+	move.l		-(a1),d0
+.else
+	mvs.\3		-(a1),d1
+.endif
+	addx.l		d0,d1
+	set_cc0
+	move.\3		d1,(a1)
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
diff --git a/firebeeV1/sources/ii_and.h b/firebeeV1/sources/ii_and.h
new file mode 100644
index 0000000..f74afde
--- /dev/null
+++ b/firebeeV1/sources/ii_and.h
@@ -0,0 +1,441 @@
+//--------------------------------------------------------------------
+// and
+//--------------------------------------------------------------------
+/*****************************************************************************************/
+//--------------------------------------------------------------------
+// byt
+//--------------------------------------------------------------------
+//--------------------------------------------------------------------
+// and.b	#im,dx
+//--------------------------------------------------------------------
+andbir_macro:.macro
+	move.w		(a0)+,d0
+	extb.l		d0
+	mvs.b		\2,d1
+	and.l		d0,d1
+	set_cc0
+	move.b		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // and	ea,dx
+//--------------------------------------------------------------------
+anddd:.macro
+#ifdef	halten_and
+	halt
+#endif
+	mvs.\3		\1,d0
+	mvs.\3		\2,d1
+	and.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // and	ea(l)->dy(w),dx z.B. für USP
+//--------------------------------------------------------------------
+andddd:.macro
+#ifdef	halten_and
+	halt
+#endif
+	move.l		\1,a1
+	mvs.\3		a1,d0
+	mvs.\3		\2,d1
+	and.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // and	(ea)->dy,dx
+//--------------------------------------------------------------------
+anddda:.macro
+#ifdef	halten_and
+	halt
+#endif
+	move.l		\1,a1
+	mvs.\3		(a1),d0
+	mvs.\3		\2,d1
+	and.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // and	ea->ay,(ay)+,dx
+//--------------------------------------------------------------------
+andddai:.macro
+#ifdef	halten_and
+	halt
+#endif
+	move.l		\1,a1
+	mvs.\3		(a1)+,d0
+	move.l		a1,\1
+	mvs.\3		\2,d1
+	and.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // and	ea->ay,-(ay),dx
+//--------------------------------------------------------------------
+andddad:.macro
+#ifdef	halten_and
+	halt
+#endif
+	move.l		\1,a1
+	mvs.\3		-(a1),d0
+	move.l		a1,\1
+	mvs.\3		\2,d1
+	and.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // and	d16(ay),dx
+//--------------------------------------------------------------------
+andd16ad:.macro
+#ifdef	halten_and
+	halt
+#endif
+	move.l		\1,a1
+	mvs.w		(a0)+,d0
+	add.l		d0,a1
+	mvs.\3		(a1),d0		
+	mvs.\3		\2,d1
+	and.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // and	d8(ay,dy),dx
+//--------------------------------------------------------------------
+andd8ad:.macro
+#ifdef	halten_and
+	halt
+#endif
+	move.l		\1,a1
+	jsr			ewf
+.ifc	\3,l
+	move.l		(a1),d0
+	move.l		\2,d1
+.else
+	mvs.\3		(a1),d0
+	mvs.\3		\2,d1
+.endif
+	and.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // and	xxx.w,dx
+//--------------------------------------------------------------------
+andxwd:.macro
+#ifdef	halten_and
+	halt
+#endif
+	move.w		(a0)+,a1
+	mvs.\3		(a1),d0
+	mvs.\3		\2,d1
+	and.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // and	xxx.l,dx
+//--------------------------------------------------------------------
+andxld:.macro
+#ifdef	halten_and
+	halt
+#endif
+	move.l		(a0)+,a1
+	mvs.\3		(a1),d0
+	mvs.\3		\2,d1
+	and.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // and	d16(pc),dx
+//--------------------------------------------------------------------
+andd16pcd:.macro
+#ifdef	halten_and
+	halt
+#endif
+	move.l		a0,a1
+	mvs.w		(a0)+,d0
+	add.l		d0,a1
+	mvs.\3		(a1),d0
+	mvs.\3		\2,d1
+	and.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // and	d8(pc,dy),dx
+//--------------------------------------------------------------------
+andd8pcd:.macro
+#ifdef	halten_and
+	halt
+#endif
+	move.l		a0,a1
+	jsr			ewf
+.ifc	\3,l
+	move.l		(a1),d0
+	move.l		\2,d1
+.else
+	mvs.\3		(a1),d0
+	mvs.\3		\2,d1
+.endif
+	and.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+//  and dx,ea
+//--------------------------------------------------------------------
+//--------------------------------------------------------------------
+// // and	dx,(ea)->dy
+//--------------------------------------------------------------------
+andeda:.macro
+#ifdef	halten_and
+	halt
+#endif
+	mvs.\3		\1,d0
+	move.l		\2,a1
+	mvs.\3		(a1),d1
+	and.l		d0,d1
+	set_cc0
+	move.\3		d1,(a1)
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // and	dx,ea->ay,(ay)+
+//--------------------------------------------------------------------
+andedai:.macro
+#ifdef	halten_and
+	halt
+#endif
+	mvs.\3		\1,d0
+	move.l		\2,a1
+	mvs.\3		(a1),d1
+	and.l		d0,d1
+	set_cc0
+	move.\3		d1,(a1)+
+	move.l		a1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // and	dx,ea->ay,(ay)+
+//--------------------------------------------------------------------
+andedaid:.macro
+#ifdef	halten_and
+	halt
+#endif
+	mvs.\3		\1,d0
+	mvs.\3		\2,d1
+	and.l		d0,d1
+	set_cc0
+	move.\3		d1,\2+
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // and	dx,ea->ay,-(ay)
+//--------------------------------------------------------------------
+andedad:.macro
+#ifdef	halten_and
+	halt
+#endif
+	mvs.\3		\1,d0
+	move.l		\2,a1
+	mvs.\3		-(a1),d1
+	move.l		a1,\2
+	and.l		d0,d1
+	set_cc0
+	move.\3		d1,(a1)
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // and	dx,ea->ay,-(ay)
+//--------------------------------------------------------------------
+andedadd:.macro
+#ifdef	halten_and
+	halt
+#endif
+	mvs.\3		\1,d0
+	mvs.\3		-\2,d1
+	and.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // and	dx,d16(ay)
+//--------------------------------------------------------------------
+ande16ad:.macro
+#ifdef	halten_and
+	halt
+#endif
+	mvs.\3		\1,d0
+	move.l		\2,a1
+	mvs.w		(a0)+,d1
+	add.l		d1,a1
+	mvs.\3		(a1),d1		
+	and.l		d0,d1
+	set_cc0
+	move.\3		d1,(a1)
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // and.w	dx,d8(ay,dy)
+//--------------------------------------------------------------------
+ande8ad:.macro
+#ifdef	halten_and
+	halt
+#endif
+	move.l		\2,a1
+	jsr			ewf
+.ifc	\3,l
+	move.l		(a1),d1
+	move.l		\1,d0
+.else
+	mvs.\3		(a1),d1
+	mvs.\3		\1,d0
+.endif
+	and.l		d0,d1
+	set_cc0
+	move.\3		d1,(a1)
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // and	dx,xxx.w
+//--------------------------------------------------------------------
+andxwe:.macro
+#ifdef	halten_and
+	halt
+#endif
+	mvs.\3		\1,d0
+	move.w		(a0)+,a1
+	mvs.\3		(a1),d1
+	and.l		d0,d1
+	set_cc0
+	move.\3		d1,(a1)
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // and	dx,xxx.l
+//--------------------------------------------------------------------
+andxle:.macro
+#ifdef	halten_and
+	halt
+#endif
+	mvs.\3		\1,d0
+	move.l		(a0)+,a1
+	mvs.\3		(a1),d1
+	and.l		d0,d1
+	set_cc0
+	move.\3		d1,(a1)
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // anda.w	ea,ax
+//--------------------------------------------------------------------
+andaw:.macro
+	jmp			ii_error
+	.endm;
+//--------------------------------------------------------------------
+// and.w ea,usp
+//--------------------------------------------------------------------
+andawa7:.macro
+	jmp			ii_error
+	.endm;
+//--------------------------------------------------------------------
+// // anda.w	usp?,ax
+//--------------------------------------------------------------------
+andawu:.macro
+	jmp			ii_error
+	.endm;
+//--------------------------------------------------------------------
+// // anda.w	usp?,usp
+//--------------------------------------------------------------------
+andawua7:.macro
+	andawu		\1,\2
+	.endm;
+//--------------------------------------------------------------------
+// // anda.w	d16(ay),ax
+//--------------------------------------------------------------------
+andawd16a:.macro
+	jmp			ii_error
+	.endm;
+//--------------------------------------------------------------------
+// // anda.w	d8(ay,dy),ax
+//--------------------------------------------------------------------
+andawd8a:.macro
+	jmp			ii_error
+	.endm;
+//--------------------------------------------------------------------
+// // anda.w	xxx.w,ax
+//--------------------------------------------------------------------
+andawxwax:.macro
+	jmp			ii_error
+	.endm;
+//--------------------------------------------------------------------
+// // anda.w	xxx.l,ax
+//--------------------------------------------------------------------
+andawxlax:.macro
+	jmp			ii_error
+	.endm;
+//--------------------------------------------------------------------
+// // anda.w	d16(pc),ax
+//--------------------------------------------------------------------
+andawd16pcax:.macro
+	jmp			ii_error
+	.endm;
+//--------------------------------------------------------------------
+// // anda.w	d8(pc,dy),ax
+//--------------------------------------------------------------------
+andawd8pcax:.macro
+	jmp			ii_error
+	.endm;
+//--------------------------------------------------------------------
+// // anda.w	#im,ax
+//--------------------------------------------------------------------
+andawim:.macro
+	jmp			ii_error
+	.endm;
+//--------------------------------------------------------------------
+// // anda.l	d8(ay,dy),ax
+//--------------------------------------------------------------------
+andald8a:.macro
+	jmp			ii_error
+	.endm;
+//--------------------------------------------------------------------
+// // anda.l	d8(pc,dy),ax
+//--------------------------------------------------------------------
+andald8pcax:.macro
+	jmp			ii_error
+	.endm;
+//*****************************************************************************************
+// spezial addx subx etc.
+//--------------------------------------------------------------------
+//--------------------------------------------------------------------
+// // addx	dy,dx
+//--------------------------------------------------------------------
+anddx:.macro
+	jmp			ii_error
+	.endm;
+//--------------------------------------------------------------------
+// // addx	-(ay),-(ax)
+//--------------------------------------------------------------------
+anddax:.macro
+	jmp			ii_error
+	.endm;
+//--------------------------------------------------------------------
diff --git a/firebeeV1/sources/ii_dbcc.h b/firebeeV1/sources/ii_dbcc.h
new file mode 100644
index 0000000..652cdbe
--- /dev/null
+++ b/firebeeV1/sources/ii_dbcc.h
@@ -0,0 +1,117 @@
+//--------------------------------------------------------------------
+// dbcc,trapcc
+//--------------------------------------------------------------------
+.text
+ii_lset_dbcc:.macro 
+// dbra
+	ii_lset_opeau	51,c
+	ii_lset_opeau	52,c
+	ii_lset_opeau	53,c
+	ii_lset_opeau	54,c
+	ii_lset_opeau	55,c
+	ii_lset_opeau	56,c
+	ii_lset_opeau	57,c
+	ii_lset_opeau	58,c
+	ii_lset_opeau	59,c
+	ii_lset_opeau	5a,c
+	ii_lset_opeau	5b,c
+	ii_lset_opeau	5c,c
+	ii_lset_opeau	5d,c
+	ii_lset_opeau	5e,c
+	ii_lset_opeau	5f,c
+.endm
+
+ii_dbcc_func:.macro
+ii_0x51c8:
+		dbra_macro	d0_off+2(a7)
+ii_0x51c9:
+		dbra_macro	d1_off+2(a7)
+ii_0x51ca:
+		dbra_macro	d2
+ii_0x51cb:
+		dbra_macro	d3
+ii_0x51cc:
+		dbra_macro	d4
+ii_0x51cd:
+		dbra_macro	d5
+ii_0x51ce:
+		dbra_macro	d6
+ii_0x51cf:
+		dbra_macro	d7
+//---------------------------------------------------------------------------------------------
+// dbcc dx
+//---------------------------------------------------------------------------------------------
+		ii_dbcc	2,hi
+		ii_dbcc 3,ls
+		ii_dbcc	4,cc
+		ii_dbcc 5,cs
+		ii_dbcc	6,ne
+		ii_dbcc	7,eq
+		ii_dbcc	8,vc
+		ii_dbcc 9,vs
+		ii_dbcc a,pl
+		ii_dbcc b,mi
+		ii_dbcc c,ge
+		ii_dbcc	d,lt
+		ii_dbcc	e,gt
+		ii_dbcc	f,le
+.endm		
+//---------------------------------------------------------------------------------------------
+// dbra dx
+//---------------------------------------------------------------------------------------------
+dbra_macro:.macro
+#ifdef	halten_dbcc
+	halt
+#endif
+		mvz.w	\1,d1				// dx holen
+		subq.l	#1,d1				// dx-1
+		bcc		dbra\@				// bra if plus?
+		addq.l	#2,a0				// offset überspringen		
+		move.w	d1,\1				// dx sichern
+ 		ii_end
+dbra\@:
+		move.w	(a0),a1				// offset (wird auf long erweitert)
+		add.l	a1,a0				// dazuadieren
+		move.w	d1,\1				// dx sichern
+ 		ii_end
+.endm
+//---------------------------------------------------------------------------------------------
+// dbcc dx
+//---------------------------------------------------------------------------------------------
+dbcc_macro:.macro
+#ifdef	halten_dbcc
+	halt
+#endif
+		b\2		dbncc\@		
+		mvz.w	\1,d1				// dx holen
+		subq.l	#1,d1				// dx-1
+		bcc		dbcc\@				// bra if plus?
+dbncc\@:
+		addq.l	#2,a0				// offset überspringen		
+		move.w	d1,\1				// dx sichern
+ 		ii_end
+dbcc\@:
+		move.w	(a0),a1				// offset (wird auf long erweitert)
+		add.l	a1,a0				// dazuadieren
+		move.w	d1,\1				// dx sichern
+ 		ii_end
+.endm
+//db
+ii_dbcc:.macro
+ii_0x5\1c8:
+		dbcc_macro	d0_off+2(a7),\2
+ii_0x5\1c9:
+		dbcc_macro	d1_off+2(a7),\2
+ii_0x5\1ca:
+		dbcc_macro	d2,\2
+ii_0x5\1cb:
+		dbcc_macro	d3,\2
+ii_0x5\1cc:
+		dbcc_macro	d4,\2
+ii_0x5\1cd:
+		dbcc_macro	d5,\2
+ii_0x5\1ce:
+		dbcc_macro	d6,\2
+ii_0x5\1cf:
+		dbcc_macro	d7,\2
+.endm
\ No newline at end of file
diff --git a/firebeeV1/sources/ii_ewf.h b/firebeeV1/sources/ii_ewf.h
new file mode 100644
index 0000000..34d2483
--- /dev/null
+++ b/firebeeV1/sources/ii_ewf.h
@@ -0,0 +1,181 @@
+//--------------------------------------------------------------------
+// extension word format missing
+//--------------------------------------------------------------------
+.text
+ii_ewf_lset:.macro
+// pea
+	ii_lset_opeag	48,7
+	ii_lset	0x487b 
+// jmp
+	ii_lset_opeag	4e,f
+	ii_lset	0x4efb 
+// jsr
+	ii_lset_opeag	4e,b
+	ii_lset	0x4ebb 
+// tas
+	ii_lset_opeag	4a,f
+	ii_lset	0x4ebb 
+// tst.b
+	ii_lset_opeag	4a,3
+	ii_lset	0x4ebb 
+// tst.w
+	ii_lset_opeag	4a,7
+	ii_lset	0x4ebb 
+// tst.l
+	ii_lset_opeag	4a,b
+	ii_lset	0x4ebb 
+// clr.b
+	ii_lset_opeag	42,3
+	ii_lset	0x423b 
+// clr.w
+	ii_lset_opeag	42,7
+	ii_lset	0x423b 
+// clr.l
+	ii_lset_opeag	42,b
+	ii_lset	0x423b 
+.endm
+//---------------------------------------------------------------------------------------------
+ii_ewf_func:.macro
+	ewf_func_macro	pea,487
+	ewf_func_macro	jmp,4ef
+	ewf_func_macro	jsr,4eb
+	ewf_func_macro	tas,4af
+	ewf_func_macro	tstb,4a3
+	ewf_func_macro	tstw,4a7
+	ewf_func_macro	tstl,4ab
+	ewf_func_macro	clrb,423
+	ewf_func_macro	clrw,427
+	ewf_func_macro	clrl,42b
+.endm
+//---------------------------------------------------------------------------------------------
+pea_macro:.macro
+	jsr		ewf
+	move.l	(a1),d0
+	move.l	usp,a1
+	move.l	d0,-(a1)
+	move.l	a1,usp
+	ii_end
+.endm
+
+jmp_macro:.macro
+	jsr		ewf
+	move.l	a1,a0
+	ii_end
+.endm
+
+jsr_macro:.macro
+	jsr		ewf
+	move.l	a1,d0
+	move.l	usp,a1
+	move.l	a0,-(a1)
+	move.l	a1,usp
+	move.l	d0,a0
+	ii_end
+.endm
+	
+tas_macro:.macro
+	jsr		ewf
+	tas		(a1)
+	set_cc0
+	ii_end
+.endm
+	
+tstb_macro:.macro
+	jsr		ewf
+	tst.b	(a1)
+	set_cc0
+	ii_end
+.endm
+	
+tstw_macro:.macro
+	jsr		ewf
+	tst.w	(a1)
+	set_cc0
+	ii_end
+.endm
+	
+tstl_macro:.macro
+	jsr		ewf
+	tst.l	(a1)
+	set_cc0
+	ii_end
+.endm
+	
+clrb_macro:.macro
+	jsr		ewf
+	clr.b	(a1)
+	set_cc0
+	ii_end
+.endm
+	
+clrw_macro:.macro
+	jsr		ewf
+	clr.w	(a1)
+	set_cc0
+	ii_end
+.endm
+	
+clrl_macro:.macro
+	jsr		ewf
+	clr.l	(a1)
+	set_cc0
+	ii_end
+.endm
+//--------------------------------------------------------------------
+ewf_func_macro:.macro	//1=art 2=code
+ii_0x\20:
+#ifdef	halten_ewf
+	halt
+#endif
+	move.l	a0_off(a7),a1
+	\1_macro
+ii_0x\21:
+#ifdef	halten_ewf
+	halt
+#endif
+	move.l	a1_off(a7),a1
+	\1_macro
+ii_0x\22:
+#ifdef	halten_ewf
+	halt
+#endif
+	move.l	a2,a1
+	\1_macro
+ii_0x\23:
+#ifdef	halten_ewf
+	halt
+#endif
+	move.l	a3,a1
+	\1_macro
+ii_0x\24:
+#ifdef	halten_ewf
+	halt
+#endif
+	move.l	a4,a1
+	\1_macro
+ii_0x\25:
+#ifdef	halten_ewf
+	halt
+#endif
+	move.l	a5,a1
+	\1_macro
+ii_0x\26:
+#ifdef	halten_ewf
+	halt
+#endif
+	move.l	a6,a1
+	\1_macro
+ii_0x\27:
+#ifdef	halten_ewf
+	halt
+#endif
+	move.l	usp,a1
+	\1_macro
+ii_0x\2b:
+#ifdef	halten_ewf
+	halt
+#endif
+	move.l	a0,a1
+	\1_macro
+.endm		
+
diff --git a/firebeeV1/sources/ii_exg.h b/firebeeV1/sources/ii_exg.h
new file mode 100644
index 0000000..a0544af
--- /dev/null
+++ b/firebeeV1/sources/ii_exg.h
@@ -0,0 +1,120 @@
+//--------------------------------------------------------------------
+// exg
+//--------------------------------------------------------------------
+.text
+ii_exg_lset:.macro 
+/*	ii_lset_dxu	c,40	//dx,d0
+	ii_lset_dxu	c,41	//dx,d1
+	ii_lset_dxu	c,42	//dx,d2
+	ii_lset_dxu	c,43	//dx,d3
+	ii_lset_dxu	c,44	//dx,d4
+	ii_lset_dxu	c,45	//dx,d5
+	ii_lset_dxu	c,46	//dx,d6
+	ii_lset_dxu	c,47	//dx,d7
+ 	ii_lset_dxu	c,48	//ax,a0
+	ii_lset_dxu	c,49	//ax,a1
+	ii_lset_dxu	c,4a	//ax,a2
+	ii_lset_dxu	c,4b	//ax,a3
+	ii_lset_dxu	c,4c	//ax,a4
+	ii_lset_dxu	c,4d	//ax,a5
+	ii_lset_dxu	c,4e	//ax,a6
+	ii_lset_dxu	c,4f	//ax,a7 */ -->setting by "and"
+ 	ii_lset_dxu	c,88	//dx,a0
+	ii_lset_dxu	c,89	//dx,a1
+	ii_lset_dxu	c,8a	//dx,a2
+	ii_lset_dxu	c,8b	//dx,a3
+	ii_lset_dxu	c,8c	//dx,a4
+	ii_lset_dxu	c,8d	//dx,a5
+	ii_lset_dxu	c,8e	//dx,a6
+	ii_lset_dxu	c,8f	//dx,a7  
+.endm
+//---------------------------------------------------------------------------------------------
+ii_exg_func:.macro
+// exg dx,dy
+	ii_exg_dx_dx 14,d0_off(a7)
+	ii_exg_dx_dx 34,d1_off(a7)
+	ii_exg_dx_dx 54,d2
+	ii_exg_dx_dx 74,d3
+	ii_exg_dx_dx 94,d4
+	ii_exg_dx_dx b4,d5
+	ii_exg_dx_dx d4,d6
+	ii_exg_dx_dx f4,d7
+// exg ax,ay
+	ii_exg_to_ax 14,a0_off(a7)
+	ii_exg_to_ax 34,a1_off(a7)
+	ii_exg_to_ax 54,a2
+	ii_exg_to_ax 74,a3
+	ii_exg_to_ax 94,a4
+	ii_exg_to_ax b4,a5
+	ii_exg_to_ax d4,a6
+	ii_exg_to_ax f4,usp
+// exg dx,ay
+	ii_exg_to_ax 18,d0_off(a7)
+	ii_exg_to_ax 38,d1_off(a7)
+	ii_exg_to_ax 58,d2
+	ii_exg_to_ax 78,d3
+	ii_exg_to_ax 98,d4
+	ii_exg_to_ax b8,d5
+	ii_exg_to_ax d8,d6
+	ii_exg_to_ax f8,d7
+.endm		
+//---------------------------------------------------------------------------------------------
+exg_macro:.macro
+#ifdef	halten_exg
+	halt
+#endif
+	move.l	\1,a1
+.ifc	\2,usp
+	move.l	a1,d0
+	move.l	\2,a1
+	move.l	a1,\1	
+	move.l	d0,a1
+.else
+	.ifc	\1,usp
+		move.l	a1,d0
+		move.l	\2,a1
+		move.l	a1,\1	
+		move.l	d0,a1
+	.else
+		move.l	\2,\1
+	.endif
+.endif
+	move.l	a1,\2
+	ii_end
+.endm
+ii_exg_dx_dx:.macro
+ii_0xc\10:
+	exg_macro	\2,d0_off(a7)
+ii_0xc\11:
+	exg_macro	\2,d1_off(a7)
+ii_0xc\12:
+	exg_macro	\2,d2
+ii_0xc\13:
+	exg_macro	\2,d3
+ii_0xc\14:
+	exg_macro	\2,d4
+ii_0xc\15:
+	exg_macro	\2,d5
+ii_0xc\16:
+	exg_macro	\2,d6
+ii_0xc\17:
+	exg_macro	\2,d7
+.endm
+ii_exg_to_ax:.macro
+ii_0xc\18:
+	exg_macro	\2,a0_off(a7)
+ii_0xc\19:
+	exg_macro	\2,a1_off(a7)
+ii_0xc\1a:
+	exg_macro	\2,a2
+ii_0xc\1b:
+	exg_macro	\2,a3
+ii_0xc\1c:
+	exg_macro	\2,a4
+ii_0xc\1d:
+	exg_macro	\2,a5
+ii_0xc\1e:
+	exg_macro	\2,a6
+ii_0xc\1f:
+	exg_macro	\2,usp
+.endm
\ No newline at end of file
diff --git a/firebeeV1/sources/ii_func.h b/firebeeV1/sources/ii_func.h
new file mode 100644
index 0000000..f545f47
--- /dev/null
+++ b/firebeeV1/sources/ii_func.h
@@ -0,0 +1,945 @@
+//--------------------------------------------------------------------
+// functionen macros
+//--------------------------------------------------------------------
+ii_lset_func:.macro
+/******************************************************/
+// byt
+/******************************************************/
+// func.b dy,dx
+	ii_lset_dx	\1,00						// 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c			
+	ii_lset_dx	\1,01			
+	ii_lset_dx	\1,02			
+	ii_lset_dx	\1,03			
+	ii_lset_dx	\1,04			
+	ii_lset_dx	\1,05			
+	ii_lset_dx	\1,06			
+	ii_lset_dx	\1,07			
+// func.b ax,dx
+	ii_lset_dxu	\1,08			
+	ii_lset_dxu	\1,09			
+	ii_lset_dxu	\1,0a			
+	ii_lset_dxu	\1,0b			
+	ii_lset_dxu	\1,0c			
+	ii_lset_dxu	\1,0d			
+	ii_lset_dxu	\1,0e			
+	ii_lset_dxu	\1,0f			
+// func.b (ax),dx
+	ii_lset_dx	\1,10			
+	ii_lset_dx	\1,11			
+	ii_lset_dx	\1,12			
+	ii_lset_dx	\1,13			
+	ii_lset_dx	\1,14			
+	ii_lset_dx	\1,15			
+	ii_lset_dx	\1,16			
+	ii_lset_dx	\1,17			
+// func.b (ax)+,dx
+	ii_lset_dx	\1,18			
+	ii_lset_dx	\1,19			
+	ii_lset_dx	\1,1a			
+	ii_lset_dx	\1,1b			
+	ii_lset_dx	\1,1c			
+	ii_lset_dx	\1,1d			
+	ii_lset_dx	\1,1e			
+	ii_lset_dx	\1,1f			
+// func.b -(ax),dx
+	ii_lset_dx	\1,20			
+	ii_lset_dx	\1,21			
+	ii_lset_dx	\1,22			
+	ii_lset_dx	\1,23			
+	ii_lset_dx	\1,24			
+	ii_lset_dx	\1,25			
+	ii_lset_dx	\1,26			
+	ii_lset_dx	\1,27			
+// func.b d16(ax),dx
+	ii_lset_dx	\1,28			
+	ii_lset_dx	\1,29			
+	ii_lset_dx	\1,2a			
+	ii_lset_dx	\1,2b			
+	ii_lset_dx	\1,2c			
+	ii_lset_dx	\1,2d			
+	ii_lset_dx	\1,2e			
+	ii_lset_dx	\1,2f			
+// func.b dd8(ax,dy),dx
+	ii_lset_dx	\1,30			
+	ii_lset_dx	\1,31			
+	ii_lset_dx	\1,32			
+	ii_lset_dx	\1,33			
+	ii_lset_dx	\1,34			
+	ii_lset_dx	\1,35			
+	ii_lset_dx	\1,36			
+	ii_lset_dx	\1,37			
+// func.b xxx.w,dx
+	ii_lset_dx	\1,38						// 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c
+// func.b xxx.l,dx
+	ii_lset_dx	\1,39						// 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c
+// func.b d16(pc),dx
+	ii_lset_dxg	\1,7a						// 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c
+// func.b d8(pc,dy),dx
+	ii_lset_dxg	\1,3b						// 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c
+// func.b #im,dx
+	ii_lset_dxg	\1,3c						// 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c
+/******************************************************/
+// word
+/******************************************************/
+// func.w dy,dx
+	ii_lset_dx	\1,40						// 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c			
+	ii_lset_dx	\1,41			
+	ii_lset_dx	\1,42			
+	ii_lset_dx	\1,43			
+	ii_lset_dx	\1,44			
+	ii_lset_dx	\1,45			
+	ii_lset_dx	\1,46			
+	ii_lset_dx	\1,47			
+// func.w ax,dx
+	ii_lset_dx	\1,48			
+	ii_lset_dx	\1,49			
+	ii_lset_dx	\1,4a			
+	ii_lset_dx	\1,4b			
+	ii_lset_dx	\1,4c			
+	ii_lset_dx	\1,4d			
+	ii_lset_dx	\1,4e			
+	ii_lset_dx	\1,4f			
+// func.w (ax),dx
+	ii_lset_dx	\1,50			
+	ii_lset_dx	\1,51			
+	ii_lset_dx	\1,52			
+	ii_lset_dx	\1,53			
+	ii_lset_dx	\1,54			
+	ii_lset_dx	\1,55			
+	ii_lset_dx	\1,56			
+	ii_lset_dx	\1,57			
+// func.w (ax)+,dx
+	ii_lset_dx	\1,58			
+	ii_lset_dx	\1,59			
+	ii_lset_dx	\1,5a			
+	ii_lset_dx	\1,5b			
+	ii_lset_dx	\1,5c			
+	ii_lset_dx	\1,5d			
+	ii_lset_dx	\1,5e			
+	ii_lset_dx	\1,5f			
+// func.w -(ax),dx
+	ii_lset_dx	\1,60			
+	ii_lset_dx	\1,61			
+	ii_lset_dx	\1,62			
+	ii_lset_dx	\1,63			
+	ii_lset_dx	\1,64			
+	ii_lset_dx	\1,65			
+	ii_lset_dx	\1,66			
+	ii_lset_dx	\1,67			
+// func.w d16(ax),dx
+	ii_lset_dx	\1,68			
+	ii_lset_dx	\1,69			
+	ii_lset_dx	\1,6a			
+	ii_lset_dx	\1,6b			
+	ii_lset_dx	\1,6c			
+	ii_lset_dx	\1,6d			
+	ii_lset_dx	\1,6e			
+	ii_lset_dx	\1,6f			
+// func.w d8(ax,dy),dx
+	ii_lset_dx	\1,70			
+	ii_lset_dx	\1,71			
+	ii_lset_dx	\1,72			
+	ii_lset_dx	\1,73			
+	ii_lset_dx	\1,74			
+	ii_lset_dx	\1,75			
+	ii_lset_dx	\1,76			
+	ii_lset_dx	\1,77			
+// func.w xxx.w,dx
+	ii_lset_dx	\1,78						// 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c
+// func.w xxx.l,dx
+	ii_lset_dx	\1,79						// 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c
+// func.w d16(pc),dx
+	ii_lset_dxg	\1,7a						// 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c
+// func.w d8(pc,dy),dx
+	ii_lset_dxg	\1,7b						// 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c
+// func.w #im,dx
+	ii_lset_dxg	\1,7c						// 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c
+/******************************************************/
+// long
+/******************************************************/
+// func.l ax,dx		-> -(ay),-(ax)
+	ii_lset_dxu	\1,c8			
+	ii_lset_dxu	\1,c9			
+	ii_lset_dxu	\1,ca			
+	ii_lset_dxu	\1,cb			
+	ii_lset_dxu	\1,cc			
+	ii_lset_dxu	\1,cd			
+	ii_lset_dxu	\1,ce			
+	ii_lset_dxu	\1,cf			
+// func.w d8(ax,dy),dx
+	ii_lset_dx	\1,b0			
+	ii_lset_dx	\1,b1			
+	ii_lset_dx	\1,b2			
+	ii_lset_dx	\1,b3			
+	ii_lset_dx	\1,b4			
+	ii_lset_dx	\1,b5			
+	ii_lset_dx	\1,b6			
+	ii_lset_dx	\1,b7			
+// func.l d8(pc,dy),dx
+	ii_lset_dxg	\1,bb						// 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c
+/******************************************************/
+// adress register
+/******************************************************/
+//func.w dy,ax
+	ii_lset_dxg	\1,c0			
+	ii_lset_dxg	\1,c1			
+	ii_lset_dxg	\1,c2			
+	ii_lset_dxg	\1,c3			
+	ii_lset_dxg	\1,c4			
+	ii_lset_dxg	\1,c5			
+	ii_lset_dxg	\1,c6			
+	ii_lset_dxg	\1,c7			
+//func.w ay,ax
+	ii_lset_dxg	\1,c8			
+	ii_lset_dxg	\1,c9			
+	ii_lset_dxg	\1,ca			
+	ii_lset_dxg	\1,cb			
+	ii_lset_dxg	\1,cc			
+	ii_lset_dxg	\1,cd			
+	ii_lset_dxg	\1,ce			
+	ii_lset_dxg	\1,cf			
+//func.w (ay),ax
+	ii_lset_dxg	\1,d0			
+	ii_lset_dxg	\1,d1			
+	ii_lset_dxg	\1,d2			
+	ii_lset_dxg	\1,d3			
+	ii_lset_dxg	\1,d4			
+	ii_lset_dxg	\1,d5			
+	ii_lset_dxg	\1,d6			
+	ii_lset_dxg	\1,d7			
+//func.w (ay)+,ax
+	ii_lset_dxg	\1,d8			
+	ii_lset_dxg	\1,d9			
+	ii_lset_dxg	\1,da			
+	ii_lset_dxg	\1,db			
+	ii_lset_dxg	\1,dc			
+	ii_lset_dxg	\1,dd			
+	ii_lset_dxg	\1,de			
+	ii_lset_dxg	\1,df			
+//func.w -(ay),ax
+	ii_lset_dxg	\1,e0			
+	ii_lset_dxg	\1,e1			
+	ii_lset_dxg	\1,e2			
+	ii_lset_dxg	\1,e3			
+	ii_lset_dxg	\1,e4			
+	ii_lset_dxg	\1,e5			
+	ii_lset_dxg	\1,e6			
+	ii_lset_dxg	\1,e7			
+//func.w d16(ay),ax
+	ii_lset_dxg	\1,e8			
+	ii_lset_dxg	\1,e9			
+	ii_lset_dxg	\1,ea			
+	ii_lset_dxg	\1,eb			
+	ii_lset_dxg	\1,ec			
+	ii_lset_dxg	\1,ed			
+	ii_lset_dxg	\1,ee			
+	ii_lset_dxg	\1,ef			
+//func.w d8(ay,dy),ax
+	ii_lset_dxg	\1,f0			
+	ii_lset_dxg	\1,f1			
+	ii_lset_dxg	\1,f2			
+	ii_lset_dxg	\1,f3			
+	ii_lset_dxg	\1,f4			
+	ii_lset_dxg	\1,f5			
+	ii_lset_dxg	\1,f6			
+	ii_lset_dxg	\1,f7			
+// func.w xxx.w,ax
+	ii_lset_dxg	\1,f8
+// func.w xxx.l,ax
+	ii_lset_dxg	\1,f9
+// func.w d16(pc),ax
+	ii_lset_dxg	\1,fa
+// func.w d8(pc,dy),ax
+	ii_lset_dxg	\1,fb
+// func.w #im,ax
+	ii_lset_dxg	\1,fc
+//--------------------------------------------------------------------
+// ende
+	.endm;	
+/*****************************************************************************************/
+ii_func:.macro
+//--------------------------------------------------------------------
+// byt
+//--------------------------------------------------------------------
+///--------------------------------------------------------------------
+//  func.b	ds,dx
+//--------------------------------------------------------------------
+	funcbeadx	\1,00,\2dd,d0_off+3(a7)		
+	funcbeadx	\1,01,\2dd,d1_off+3(a7)		
+	funcbeadx	\1,02,\2dd,d2		
+	funcbeadx	\1,03,\2dd,d3		
+	funcbeadx	\1,04,\2dd,d4		
+	funcbeadx	\1,05,\2dd,d5		
+	funcbeadx	\1,06,\2dd,d6		
+	funcbeadx	\1,07,\2dd,d7
+//--------------------------------------------------------------------
+//  func.b	(ax),dx
+//--------------------------------------------------------------------
+	funcbeadx	\1,10,\2dda,a0_off(a7)		
+	funcbeadx	\1,11,\2dda,a1_off(a7)		
+	funcbeadx	\1,12,\2dd,(a2)		
+	funcbeadx	\1,13,\2dd,(a3)		
+	funcbeadx	\1,14,\2dd,(a4)		
+	funcbeadx	\1,15,\2dd,(a5)		
+	funcbeadx	\1,16,\2dd,(a6)		
+	funcbeadx	\1,17,\2dda,usp
+//--------------------------------------------------------------------
+//  func.b	(ax)+,dx
+//--------------------------------------------------------------------
+	funcbeadx	\1,18,\2ddai,a0_off(a7)		
+	funcbeadx	\1,19,\2ddai,a1_off(a7)		
+	funcbeadx	\1,1a,\2dd,(a2)+		
+	funcbeadx	\1,1b,\2dd,(a3)+		
+	funcbeadx	\1,1c,\2dd,(a4)+		
+	funcbeadx	\1,1d,\2dd,(a5)+		
+	funcbeadx	\1,1e,\2dd,(a6)+		
+	funcbeadx	\1,1f,\2ddai,usp
+//--------------------------------------------------------------------
+//  func.b	-(ax),dx
+//--------------------------------------------------------------------
+	funcbeadx	\1,20,\2ddad,a0_off(a7)		
+	funcbeadx	\1,21,\2ddad,a1_off(a7)		
+	funcbeadx	\1,22,\2dd,-(a2)		
+	funcbeadx	\1,23,\2dd,-(a3)		
+	funcbeadx	\1,24,\2dd,-(a4)		
+	funcbeadx	\1,25,\2dd,-(a5)		
+	funcbeadx	\1,26,\2dd,-(a6)		
+	funcbeadx	\1,27,\2ddad,usp
+//--------------------------------------------------------------------
+//  func.b	d16(ax),dx
+//--------------------------------------------------------------------
+	funcbeadx	\1,28,\2d16ad,a0_off(a7)		
+	funcbeadx	\1,29,\2d16ad,a1_off(a7)		
+	funcbeadx	\1,2a,\2d16ad,a2		
+	funcbeadx	\1,2b,\2d16ad,a3		
+	funcbeadx	\1,2c,\2d16ad,a4		
+	funcbeadx	\1,2d,\2d16ad,a5		
+	funcbeadx	\1,2e,\2d16ad,a6		
+	funcbeadx	\1,2f,\2d16ad,usp
+//--------------------------------------------------------------------
+//  func.b	d8(ax,dy),dx
+//--------------------------------------------------------------------
+	funcbeadx	\1,30,\2d8ad,a0_off(a7)		
+	funcbeadx	\1,31,\2d8ad,a1_off(a7)		
+	funcbeadx	\1,32,\2d8ad,a2		
+	funcbeadx	\1,33,\2d8ad,a3		
+	funcbeadx	\1,34,\2d8ad,a4		
+	funcbeadx	\1,35,\2d8ad,a5		
+	funcbeadx	\1,36,\2d8ad,a6		
+	funcbeadx	\1,37,\2d8ad,usp
+//--------------------------------------------------------------------
+// func.b xxx.w,dx
+//--------------------------------------------------------------------
+	funcbeadx	\1,38,\2xwd,(a0)+
+//--------------------------------------------------------------------
+// func.b xxx.w,dx
+//--------------------------------------------------------------------
+	funcbeadx	\1,39,\2xld,(a0)+
+//--------------------------------------------------------------------
+// func.b d16(pc),dx
+//--------------------------------------------------------------------
+	funcbeadx	\1,3a,\2d16pcd,(a0)+
+//--------------------------------------------------------------------
+// func.b d8(pc,dy),dx
+//--------------------------------------------------------------------
+	funcbeadx	\1,3b,\2d8pcd,(a0)+	(a0 wird nicht verwendet)
+//--------------------------------------------------------------------
+// func.b	#im,dx
+//--------------------------------------------------------------------
+	funcbeadx	\1,3c,\2bir_macro,(a0)+
+//--------------------------------------------------------------------
+//  func.b	dy,ea
+//--------------------------------------------------------------------
+///--------------------------------------------------------------------
+//  func.b	dx,dd -> addx subx etc. src und dest vertauscht!
+//--------------------------------------------------------------------
+	funcbdxea	\1,00,\2dx,d0_off+3(a7)		
+	funcbdxea	\1,01,\2dx,d1_off+3(a7)		
+	funcbdxea	\1,02,\2dx,d2		
+	funcbdxea	\1,03,\2dx,d3		
+	funcbdxea	\1,04,\2dx,d4		
+	funcbdxea	\1,05,\2dx,d5		
+	funcbdxea	\1,06,\2dx,d6		
+	funcbdxea	\1,07,\2dx,d7
+//--------------------------------------------------------------------
+//  func.b	-(ax),-(ay) addx subx etc. src und dest vertauscht!
+//--------------------------------------------------------------------
+	funcaxay	\1,08,\2dax,a0_off(a7),b		
+	funcaxay	\1,09,\2dax,a1_off(a7).b		
+	funcaxay	\1,0a,\2dax,a2,b		
+	funcaxay	\1,0b,\2dax,a3,b		
+	funcaxay	\1,0c,\2dax,a4,b		
+	funcaxay	\1,0d,\2dax,a5,b		
+	funcaxay	\1,0e,\2dax,a6,b		
+	funcaxay	\1,0f,\2dax,usp,b
+//--------------------------------------------------------------------
+//  func.b	dy,(ax)
+//--------------------------------------------------------------------
+	funcbdxea	\1,10,\2eda,a0_off(a7)		
+	funcbdxea	\1,11,\2eda,a1_off(a7)		
+	funcbdxea	\1,12,\2dd,(a2)		
+	funcbdxea	\1,13,\2dd,(a3)		
+	funcbdxea	\1,14,\2dd,(a4)		
+	funcbdxea	\1,15,\2dd,(a5)		
+	funcbdxea	\1,16,\2dd,(a6)		
+	funcbdxea	\1,17,\2eda,usp
+//--------------------------------------------------------------------
+//  func.b	dy,(ax)+
+//--------------------------------------------------------------------
+	funcbdxea	\1,18,\2edai,a0_off(a7)		
+	funcbdxea	\1,19,\2edai,a1_off(a7)		
+	funcbdxea	\1,1a,\2edaid,(a2)		
+	funcbdxea	\1,1b,\2edaid,(a3)	
+	funcbdxea	\1,1c,\2edaid,(a4)	
+	funcbdxea	\1,1d,\2edaid,(a5)	
+	funcbdxea	\1,1e,\2edaid,(a6)		
+	funcbdxea	\1,1f,\2edai,usp
+//--------------------------------------------------------------------
+//  func.b	dy,-(ax)
+//--------------------------------------------------------------------
+	funcbdxea	\1,20,\2edad,a0_off(a7)		
+	funcbdxea	\1,21,\2edad,a1_off(a7)		
+	funcbdxea	\1,22,\2edadd,(a2)		
+	funcbdxea	\1,23,\2edadd,(a3)		
+	funcbdxea	\1,24,\2edadd,(a4)		
+	funcbdxea	\1,25,\2edadd,(a5)		
+	funcbdxea	\1,26,\2edadd,(a6)		
+	funcbdxea	\1,27,\2edad,usp
+//--------------------------------------------------------------------
+//  func.b	dy,d16(ax)
+//--------------------------------------------------------------------
+	funcbdxea	\1,28,\2e16ad,a0_off(a7)		
+	funcbdxea	\1,29,\2e16ad,a1_off(a7)		
+	funcbdxea	\1,2a,\2e16ad,a2		
+	funcbdxea	\1,2b,\2e16ad,a3		
+	funcbdxea	\1,2c,\2e16ad,a4		
+	funcbdxea	\1,2d,\2e16ad,a5		
+	funcbdxea	\1,2e,\2e16ad,a6		
+	funcbdxea	\1,2f,\2e16ad,usp
+//--------------------------------------------------------------------
+//  func.b	dy,d8(ax,dy)
+//--------------------------------------------------------------------
+	funcbdxea	\1,30,\2e8ad,a0_off(a7)		
+	funcbdxea	\1,31,\2e8ad,a1_off(a7)		
+	funcbdxea	\1,32,\2e8ad,a2		
+	funcbdxea	\1,33,\2e8ad,a3		
+	funcbdxea	\1,34,\2e8ad,a4		
+	funcbdxea	\1,35,\2e8ad,a5		
+	funcbdxea	\1,36,\2e8ad,a6		
+	funcbdxea	\1,37,\2e8ad,usp
+//--------------------------------------------------------------------
+// func.w dy,xxx.w
+//--------------------------------------------------------------------
+	funcwdxea	\1,38,\2xwe,(a0)+
+//--------------------------------------------------------------------
+// func.w dy,xxx.w
+//--------------------------------------------------------------------
+	funcwdxea	\1,39,\2xld,(a0)+
+/*****************************************************************************************/
+// word
+/*****************************************************************************************/
+//  func.w	ds,dx
+//--------------------------------------------------------------------
+	funcweadx	\1,40,\2dd,d0_off+2(a7)		
+	funcweadx	\1,41,\2dd,d1_off+2(a7)		
+	funcweadx	\1,42,\2dd,d2		
+	funcweadx	\1,43,\2dd,d3		
+	funcweadx	\1,44,\2dd,d4		
+	funcweadx	\1,45,\2dd,d5		
+	funcweadx	\1,46,\2dd,d6		
+	funcweadx	\1,47,\2dd,d7
+//--------------------------------------------------------------------
+//  func.w	ax,dx
+//--------------------------------------------------------------------
+	funcweadx	\1,48,\2dd,a0_off+2(a7)		
+	funcweadx	\1,49,\2dd,a1_off+2(a7)		
+	funcweadx	\1,4a,\2dd,a2		
+	funcweadx	\1,4b,\2dd,a3		
+	funcweadx	\1,4c,\2dd,a4		
+	funcweadx	\1,4d,\2dd,a5		
+	funcweadx	\1,4e,\2dd,a6		
+	funcweadx	\1,4f,\2ddd,usp
+//--------------------------------------------------------------------
+//  func.w	(ax),dx
+//--------------------------------------------------------------------
+	funcweadx	\1,50,\2dda,a0_off(a7)		
+	funcweadx	\1,51,\2dda,a1_off(a7)		
+	funcweadx	\1,52,\2dd,(a2)		
+	funcweadx	\1,53,\2dd,(a3)		
+	funcweadx	\1,54,\2dd,(a4)		
+	funcweadx	\1,55,\2dd,(a5)		
+	funcweadx	\1,56,\2dd,(a6)		
+	funcweadx	\1,57,\2dda,usp
+//--------------------------------------------------------------------
+//  func.w	(ax)+,dx
+//--------------------------------------------------------------------
+	funcweadx	\1,58,\2ddai,a0_off(a7)		
+	funcweadx	\1,59,\2ddai,a1_off(a7)		
+	funcweadx	\1,5a,\2dd,(a2)+		
+	funcweadx	\1,5b,\2dd,(a3)+		
+	funcweadx	\1,5c,\2dd,(a4)+		
+	funcweadx	\1,5d,\2dd,(a5)+		
+	funcweadx	\1,5e,\2dd,(a6)+		
+	funcweadx	\1,5f,\2ddai,usp
+//--------------------------------------------------------------------
+//  func.w	-(ax),dx
+//--------------------------------------------------------------------
+	funcweadx	\1,60,\2ddad,a0_off(a7)		
+	funcweadx	\1,61,\2ddad,a1_off(a7)		
+	funcweadx	\1,62,\2dd,-(a2)		
+	funcweadx	\1,63,\2dd,-(a3)		
+	funcweadx	\1,64,\2dd,-(a4)		
+	funcweadx	\1,65,\2dd,-(a5)		
+	funcweadx	\1,66,\2dd,-(a6)		
+	funcweadx	\1,67,\2ddad,usp
+//--------------------------------------------------------------------
+//  func.w	d16(ax),dx
+//--------------------------------------------------------------------
+	funcweadx	\1,68,\2d16ad,a0_off(a7)		
+	funcweadx	\1,69,\2d16ad,a1_off(a7)		
+	funcweadx	\1,6a,\2d16ad,a2		
+	funcweadx	\1,6b,\2d16ad,a3		
+	funcweadx	\1,6c,\2d16ad,a4		
+	funcweadx	\1,6d,\2d16ad,a5		
+	funcweadx	\1,6e,\2d16ad,a6		
+	funcweadx	\1,6f,\2d16ad,usp
+//--------------------------------------------------------------------
+//  func.w	d8(ax,dy),dx
+//--------------------------------------------------------------------
+	funcweadx	\1,70,\2d8ad,a0_off(a7)		
+	funcweadx	\1,71,\2d8ad,a1_off(a7)		
+	funcweadx	\1,72,\2d8ad,a2		
+	funcweadx	\1,73,\2d8ad,a3		
+	funcweadx	\1,74,\2d8ad,a4		
+	funcweadx	\1,75,\2d8ad,a5		
+	funcweadx	\1,76,\2d8ad,a6		
+	funcweadx	\1,77,\2d8ad,usp
+//--------------------------------------------------------------------
+// func.w xxx.w,dx
+//--------------------------------------------------------------------
+	funcweadx	\1,78,\2xwd,(a0)+
+//--------------------------------------------------------------------
+// func.w xxx.w,dx
+//--------------------------------------------------------------------
+	funcweadx	\1,79,\2xld,(a0)+
+//--------------------------------------------------------------------
+// func.w d16(pc),dx
+//--------------------------------------------------------------------
+	funcweadx	\1,7a,\2d16pcd,(a0)+
+//--------------------------------------------------------------------
+// func.w d8(pc,dy),dx
+//--------------------------------------------------------------------
+	funcweadx	\1,7b,\2d8pcd,(a0)+	(a0 wird nicht verwendet)
+//--------------------------------------------------------------------
+// func.w #im,dx
+//--------------------------------------------------------------------
+	funcweadx	\1,7c,\2dd,(a0)+
+//--------------------------------------------------------------------
+//  func.w	dy,ea
+//--------------------------------------------------------------------
+///--------------------------------------------------------------------
+//  func.w	dx,dd -> addx subx etc.
+//--------------------------------------------------------------------
+.ifnc	\2,and			//platz für exg
+	funcwdxea	\1,40,\2dx,d0_off+2(a7)		
+	funcwdxea	\1,41,\2dx,d1_off+2(a7)		
+	funcwdxea	\1,42,\2dx,d2		
+	funcwdxea	\1,43,\2dx,d3		
+	funcwdxea	\1,44,\2dx,d4		
+	funcwdxea	\1,45,\2dx,d5		
+	funcwdxea	\1,46,\2dx,d6		
+	funcwdxea	\1,47,\2dx,d7
+//--------------------------------------------------------------------
+//  func.w	-(ax),-(ay) -> addx,subx
+//--------------------------------------------------------------------
+	funcaxay	\1,48,\2dax,a0_off(a7),w		
+	funcaxay	\1,49,\2dax,a1_off(a7).w		
+	funcaxay	\1,4a,\2dax,a2,w		
+	funcaxay	\1,4b,\2dax,a3,w		
+	funcaxay	\1,4c,\2dax,a4,w		
+	funcaxay	\1,4d,\2dax,a5,w		
+	funcaxay	\1,4e,\2dax,a6,w		
+	funcaxay	\1,4f,\2dax,usp,w
+.endif
+//--------------------------------------------------------------------
+//  func.w	dy,(ax)
+//--------------------------------------------------------------------
+	funcwdxea	\1,50,\2eda,a0_off(a7)		
+	funcwdxea	\1,51,\2eda,a1_off(a7)		
+	funcwdxea	\1,52,\2dd,(a2)		
+	funcwdxea	\1,53,\2dd,(a3)		
+	funcwdxea	\1,54,\2dd,(a4)		
+	funcwdxea	\1,55,\2dd,(a5)		
+	funcwdxea	\1,56,\2dd,(a6)		
+	funcwdxea	\1,57,\2eda,usp
+//--------------------------------------------------------------------
+//  func.w	dy,(ax)+
+//--------------------------------------------------------------------
+	funcwdxea	\1,58,\2edai,a0_off(a7)		
+	funcwdxea	\1,59,\2edai,a1_off(a7)		
+	funcwdxea	\1,5a,\2edaid,(a2)		
+	funcwdxea	\1,5b,\2edaid,(a3)		
+	funcwdxea	\1,5c,\2edaid,(a4)		
+	funcwdxea	\1,5d,\2edaid,(a5)		
+	funcwdxea	\1,5e,\2edaid,(a6)		
+	funcwdxea	\1,5f,\2edai,usp
+//--------------------------------------------------------------------
+//  func.w	dy,-(ax)
+//--------------------------------------------------------------------
+	funcwdxea	\1,60,\2edad,a0_off(a7)		
+	funcwdxea	\1,61,\2edad,a1_off(a7)		
+	funcwdxea	\1,62,\2edadd,(a2)		
+	funcwdxea	\1,63,\2edadd,(a3)		
+	funcwdxea	\1,64,\2edadd,(a4)		
+	funcwdxea	\1,65,\2edadd,(a5)		
+	funcwdxea	\1,66,\2edadd,(a6)		
+	funcwdxea	\1,67,\2edad,usp
+//--------------------------------------------------------------------
+//  func.w	dy,d16(ax)
+//--------------------------------------------------------------------
+	funcwdxea	\1,68,\2e16ad,a0_off(a7)		
+	funcwdxea	\1,69,\2e16ad,a1_off(a7)		
+	funcwdxea	\1,6a,\2e16ad,a2		
+	funcwdxea	\1,6b,\2e16ad,a3		
+	funcwdxea	\1,6c,\2e16ad,a4		
+	funcwdxea	\1,6d,\2e16ad,a5		
+	funcwdxea	\1,6e,\2e16ad,a6		
+	funcwdxea	\1,6f,\2e16ad,usp
+//--------------------------------------------------------------------
+//  func.w	dy,d8(ax,dy)
+//--------------------------------------------------------------------
+	funcwdxea	\1,70,\2e8ad,a0_off(a7)		
+	funcwdxea	\1,71,\2e8ad,a1_off(a7)		
+	funcwdxea	\1,72,\2e8ad,a2		
+	funcwdxea	\1,73,\2e8ad,a3		
+	funcwdxea	\1,74,\2e8ad,a4		
+	funcwdxea	\1,75,\2e8ad,a5		
+	funcwdxea	\1,76,\2e8ad,a6		
+	funcwdxea	\1,77,\2e8ad,usp
+//--------------------------------------------------------------------
+// func.w dy,xxx.w
+//--------------------------------------------------------------------
+	funcwdxea	\1,78,\2xwe,(a0)+
+//--------------------------------------------------------------------
+// func.w dy,xxx.w
+//--------------------------------------------------------------------
+	funcwdxea	\1,79,\2xld,(a0)+
+/*****************************************************************************************/
+// long
+/*****************************************************************************************/
+//--------------------------------------------------------------------
+//  func.l	-(ax),-(ay)
+//--------------------------------------------------------------------
+	funcaxay	\1,c8,\2dax,a0_off(a7),l		
+	funcaxay	\1,c9,\2dax,a1_off(a7).l		
+	funcaxay	\1,ca,\2dax,a2,l		
+	funcaxay	\1,cb,\2dax,a3,l		
+	funcaxay	\1,cc,\2dax,a4,l		
+	funcaxay	\1,cd,\2dax,a5,l		
+	funcaxay	\1,ce,\2dax,a6,l		
+	funcaxay	\1,cf,\2dax,usp,l
+//--------------------------------------------------------------------
+//  func.l	d8(ax,dy),dx
+//--------------------------------------------------------------------
+	funcleadx	\1,b0,\2d8ad,a0_off(a7)		
+	funcleadx	\1,b1,\2d8ad,a1_off(a7)		
+	funcleadx	\1,b2,\2d8ad,a2		
+	funcleadx	\1,b3,\2d8ad,a3		
+	funcleadx	\1,b4,\2d8ad,a4		
+	funcleadx	\1,b5,\2d8ad,a5		
+	funcleadx	\1,b6,\2d8ad,a6		
+	funcleadx	\1,b7,\2d8ad,usp
+//--------------------------------------------------------------------
+// func.l d8(pc,dy),dx
+//--------------------------------------------------------------------
+	funcleadx	\1,bb,\2d8pcd,(a0)+	(a0 wird nicht verwendet)
+//--------------------------------------------------------------------
+//  func.l	dy,d8(ax,dy)
+//--------------------------------------------------------------------
+	funcldxea	\1,b0,\2e8ad,a0_off(a7)		
+	funcldxea	\1,b1,\2e8ad,a1_off(a7)		
+	funcldxea	\1,b2,\2e8ad,a2		
+	funcldxea	\1,b3,\2e8ad,a3		
+	funcldxea	\1,b4,\2e8ad,a4		
+	funcldxea	\1,b5,\2e8ad,a5		
+	funcldxea	\1,b6,\2e8ad,a6		
+	funcldxea	\1,b7,\2e8ad,usp
+/******************************************************/
+// adress register
+/******************************************************/
+//--------------------------------------------------------------------
+// func.w ea,ax
+//--------------------------------------------------------------------
+//--------------------------------------------------------------------
+// func.w	dx,ax
+//--------------------------------------------------------------------
+	funcweaax	\1,c0,\2aw,d0		
+	funcweaax	\1,c1,\2aw,d1		
+	funcweaax	\1,c2,\2aw,d2		
+	funcweaax	\1,c3,\2aw,d3		
+	funcweaax	\1,c4,\2aw,d4		
+	funcweaax	\1,c5,\2aw,d5		
+	funcweaax	\1,c6,\2aw,d6		
+	funcweaax	\1,c7,\2aw,d7		
+//--------------------------------------------------------------------
+// func.w	ay,ax
+//--------------------------------------------------------------------
+	funcweaax	\1,c8,\2aw,a0		
+	funcweaax	\1,c9,\2aw,a1		
+	funcweaax	\1,ca,\2aw,a2		
+	funcweaax	\1,cb,\2aw,a3		
+	funcweaax	\1,cc,\2aw,a4		
+	funcweaax	\1,cd,\2aw,a5		
+	funcweaax	\1,ce,\2aw,a6		
+	funcweaax	\1,cf,\2awu,a7	
+//--------------------------------------------------------------------
+// func.w	(ay),ax
+//--------------------------------------------------------------------
+	funcweaax	\1,d0,\2aw,(a0)		
+	funcweaax	\1,d1,\2aw,(a1)	
+	funcweaax	\1,d2,\2aw,(a2)		
+	funcweaax	\1,d3,\2aw,(a3)		
+	funcweaax	\1,d4,\2aw,(a4)		
+	funcweaax	\1,d5,\2aw,(a5)		
+	funcweaax	\1,d6,\2aw,(a6)		
+	funcweaax	\1,d7,\2awu,(a7)	
+//--------------------------------------------------------------------
+// func.w	(ay)+,ax
+//--------------------------------------------------------------------
+	funcweaax	\1,d8,\2aw,(a0)+		
+	funcweaax	\1,d9,\2aw,(a1)+
+	funcweaax	\1,da,\2aw,(a2)+	
+	funcweaax	\1,db,\2aw,(a3)+		
+	funcweaax	\1,dc,\2aw,(a4)+	
+	funcweaax	\1,dd,\2aw,(a5)+	
+	funcweaax	\1,de,\2aw,(a6)+	
+	funcweaax	\1,df,\2awu,(a7)+	
+//--------------------------------------------------------------------
+// func.w	-(ay),ax
+//--------------------------------------------------------------------
+	funcweaax	\1,e0,\2aw,-(a0)		
+	funcweaax	\1,e1,\2aw,-(a1)
+	funcweaax	\1,e2,\2aw,-(a2)	
+	funcweaax	\1,e3,\2aw,-(a3)		
+	funcweaax	\1,e4,\2aw,-(a4)	
+	funcweaax	\1,e5,\2aw,-(a5)	
+	funcweaax	\1,e6,\2aw,-(a6)	
+	funcweaax	\1,e7,\2awu,-(a7)	
+//--------------------------------------------------------------------
+// func.w	d16(ay),ax
+//--------------------------------------------------------------------
+	funcweaaxn	\1,e8,\2awd16a,a0_off(a7)		
+	funcweaaxn	\1,e9,\2awd16a,a1_off(a7)
+	funcweaaxn	\1,ea,\2awd16a,a2	
+	funcweaaxn	\1,eb,\2awd16a,a3		
+	funcweaaxn	\1,ec,\2awd16a,a4	
+	funcweaaxn	\1,ed,\2awd16a,a5	
+	funcweaaxn	\1,ee,\2awd16a,a6	
+	funcweaaxn	\1,ef,\2awd16a,usp	
+//--------------------------------------------------------------------
+// func.w	d8(ay,dy),ax
+//--------------------------------------------------------------------
+	funcweaaxn	\1,f0,\2awd8a,a0_off(a7)		
+	funcweaaxn	\1,f1,\2awd8a,a1_off(a7)
+	funcweaaxn	\1,f2,\2awd8a,a2	
+	funcweaaxn	\1,f3,\2awd8a,a3		
+	funcweaaxn	\1,f4,\2awd8a,a4	
+	funcweaaxn	\1,f5,\2awd8a,a5	
+	funcweaaxn	\1,f6,\2awd8a,a6	
+	funcweaaxn	\1,f7,\2awd8a,usp	
+//--------------------------------------------------------------------
+// func.w xxx.w,ax
+//--------------------------------------------------------------------
+	funcweaaxn	\1,f8,\2awxwax,(a0)+
+//--------------------------------------------------------------------
+// func.w xxxlw,ax
+//--------------------------------------------------------------------
+	funcweaaxn	\1,f9,\2awxlax,(a0)+
+//--------------------------------------------------------------------
+// func.w d16(pc),ax
+//--------------------------------------------------------------------
+	funcweaaxn	\1,fa,\2awd16pcax,(a0)+
+//--------------------------------------------------------------------
+// func.w d8(pc,dy),ax
+//--------------------------------------------------------------------
+	funcweaaxn	\1,fb,\2awd8pcax,(a0)+	//(a0 wird nicht verwendet)
+//--------------------------------------------------------------------
+// func.w #im,ax
+//--------------------------------------------------------------------
+	funcweaaxn	\1,fc,\2awim,(a0)+	
+//--------------------------------------------------------------------
+// ende
+	.endm;	
+//--------------------------------------------------------------------
+// byt
+funcbeadx:.macro					// function byt: im,dx 
+ii_0x\10\2:			 
+	\3		\4,d0_off+3(a7),b
+ii_0x\12\2:				 
+	\3		\4,d1_off+3(a7),b
+ii_0x\14\2:			 
+	\3		\4,d2,b
+ii_0x\16\2:			 
+	\3		\4,d3,b 
+ii_0x\18\2:			 
+	\3		\4,d4,b 
+ii_0x\1a\2:				 
+	\3		\4,d5,b
+ii_0x\1c\2:			 
+	\3		\4,d6,b
+ii_0x\1e\2:			 
+	\3		\4,d7,b
+	.endm;
+funcbdxea:.macro	// ea(\4) function(\3) dx -> ea
+ii_0x\11\2:
+	\3	d0_off+3(a7),\4,b
+ii_0x\13\2:
+	\3	d1_off+3(a7),\4,b
+ii_0x\15\2:
+	\3	d2,\4,b
+ii_0x\17\2:
+	\3	d3,\4,b
+ii_0x\19\2:
+	\3	d4,\4,b
+ii_0x\1b\2:
+	\3	d5,\4,b
+ii_0x\1d\2:
+	\3	d6,\4,b
+ii_0x\1f\2:
+	\3	d7,\4,b
+	.endm;
+//--------------------------------------------------------------------
+// word
+funcweadx:.macro	// dx function(\3) ea(\4) -> dx 
+ii_0x\10\2:
+	\3	\4,d0_off+2(a7),w
+ii_0x\12\2:
+	\3	\4,d1_off+2(a7),w
+ii_0x\14\2:
+	\3	\4,d2,w
+ii_0x\16\2:
+	\3	\4,d3,w
+ii_0x\18\2:
+	\3	\4,d4,w
+ii_0x\1a\2:
+	\3	\4,d5,w
+ii_0x\1c\2:
+	\3	\4,d6,w
+ii_0x\1e\2:
+	\3	\4,d7,w
+	.endm;
+funcwdxea:.macro	// ea(\4) function(\3) dx -> ea 
+ii_0x\11\2:
+	\3	d0_off+2(a7),\4,w
+ii_0x\13\2:
+	\3	d1_off+2(a7),\4,w
+ii_0x\15\2:
+	\3	d2,\4,w
+ii_0x\17\2:
+	\3	d3,\4,w
+ii_0x\19\2:
+	\3	d4,\4,w
+ii_0x\1b\2:
+	\3	d5,\4,w
+ii_0x\1d\2:
+	\3	d6,\4,w
+ii_0x\1f\2:
+	\3	d7,\4,w
+	.endm;
+//--------------------------------------------------------------------
+// long
+funcleadx:.macro	// dx function(\3) ea(\4) -> dx 
+ii_0x\10\2:
+	\3	\4,d0_off(a7),w
+ii_0x\12\2:
+	\3	\4,d1_off(a7),w
+ii_0x\14\2:
+	\3	\4,d2,w
+ii_0x\16\2:
+	\3	\4,d3,w
+ii_0x\18\2:
+	\3	\4,d4,w
+ii_0x\1a\2:
+	\3	\4,d5,w
+ii_0x\1c\2:
+	\3	\4,d6,w
+ii_0x\1e\2:
+	\3	\4,d7,w
+	.endm;
+funcldxea:.macro	// ea(\4) function(\3) dx -> ea 
+ii_0x\11\2:
+	\3	d0_off(a7),\4,w
+ii_0x\13\2:
+	\3	d1_off(a7),\4,w
+ii_0x\15\2:
+	\3	d2,\4,w
+ii_0x\17\2:
+	\3	d3,\4,w
+ii_0x\19\2:
+	\3	d4,\4,w
+ii_0x\1b\2:
+	\3	d5,\4,w
+ii_0x\1d\2:
+	\3	d6,\4,w
+ii_0x\1f\2:
+	\3	d7,\4,w
+	.endm;
+//--------------------------------------------------------------
+// address
+funcweaax:.macro	// ax function(\3) ea(\4)(ext long!) -> ax 
+ii_0x\10\2:
+	\3	\4,a0
+ii_0x\12\2:
+	\3	\4,a1
+ii_0x\14\2:
+	\3	\4,a2 
+ii_0x\16\2:
+	\3	\4,a3 
+ii_0x\18\2:
+	\3	\4,a4 
+ii_0x\1a\2:
+	\3	\4,a5 
+ii_0x\1c\2:
+	\3	\4,a6 
+ii_0x\1e\2:
+	\3a7 \4,a7 		// "a7" beachten wegen usp
+	.endm;
+funcweaaxn:.macro	// ax function(\3) ea(\4)(ext long!) -> ax 
+ii_0x\10\2:
+	\3	\4,a0_off(a7) 
+ii_0x\12\2:
+	\3	\4,a1_off(a7) 
+ii_0x\14\2:
+	\3	\4,a2 
+ii_0x\16\2:
+	\3	\4,a3 
+ii_0x\18\2:
+	\3	\4,a4 
+ii_0x\1a\2:
+	\3	\4,a5 
+ii_0x\1c\2:
+	\3	\4,a6 
+ii_0x\1e\2:
+	\3	\4,usp 
+	.endm;
+//--------------------------------------------------------------
+// byt, word, long
+//--------------------------------------------------------------
+funcaxay:.macro	// ea(\4) function(\3) dx -> ea,\5 = size
+ii_0x\11\2:
+	\3	a0_off(a7),\4,\5
+ii_0x\13\2:
+	\3	a1_off(a7),\4,\5
+ii_0x\15\2:
+	\3	a2,\4,\5
+ii_0x\17\2:
+	\3	a3,\4,\5
+ii_0x\19\2:
+	\3	a4,\4,\5
+ii_0x\1b\2:
+	\3	a5,\4,\5
+ii_0x\1d\2:
+	\3	a6,\4,\5
+ii_0x\1f\2:
+	\3	usp,\4,\5
+	.endm;
diff --git a/firebeeV1/sources/ii_jmp.h b/firebeeV1/sources/ii_jmp.h
new file mode 100644
index 0000000..1896118
--- /dev/null
+++ b/firebeeV1/sources/ii_jmp.h
@@ -0,0 +1,59 @@
+//--------------------------------------------------------------------
+// extension word format missing
+//--------------------------------------------------------------------
+ii_\1_func:.macro
+ii_0x\20:
+#ifdef	halten_\1
+	halt
+#endif
+	move.l	a0_off(a7),a1
+	\1_macro
+ii_0x\21:
+#ifdef	halten_\1
+	halt
+#endif
+	move.l	a1_off(a7),a1
+	\1_macro
+ii_0x\22:
+#ifdef	halten_\1
+	halt
+#endif
+	move.l	a2,a1
+	\1_macro
+ii_0x\23:
+#ifdef	halten_\1
+	halt
+#endif
+	move.l	a3,a1
+	\1_macro
+ii_0x\24:
+#ifdef	halten_\1
+	halt
+#endif
+	move.l	a4,a1
+	\1_macro
+ii_0x\25:
+#ifdef	halten_\1
+	halt
+#endif
+	move.l	a5,a1
+	\1_macro
+ii_0x\26:
+#ifdef	halten_\1
+	halt
+#endif
+	move.l	a6,a1
+	\1_macro
+ii_0x\27:
+#ifdef	halten_\1
+	halt
+#endif
+	move.l	usp,a1
+	\1_macro
+ii_0x\2b:
+#ifdef	halten_\1
+	halt
+#endif
+	move.l	a0,a1
+	\1_macro
+.endm		
diff --git a/firebeeV1/sources/ii_lea.h b/firebeeV1/sources/ii_lea.h
new file mode 100644
index 0000000..7a422a7
--- /dev/null
+++ b/firebeeV1/sources/ii_lea.h
@@ -0,0 +1,105 @@
+//-------------------------------------------------------------------
+// lea
+//-------------------------------------------------------------------
+.text
+ii_lea_lset:.macro
+	ii_lset_dxu 4,f0			// lea d8(a0,dy.w),a0-a7
+	ii_lset_dxu 4,f1			// lea d8(a1,dy.w),a0-a7
+	ii_lset_dxu 4,f2			// lea d8(a2,dy.w),a0-a7
+	ii_lset_dxu 4,f3			// lea d8(a3,dy.w),a0-a7
+	ii_lset_dxu 4,f4			// lea d8(a4,dy.w),a0-a7
+	ii_lset_dxu 4,f5			// lea d8(a5,dy.w),a0-a7
+	ii_lset_dxu 4,f6			// lea d8(a6,dy.w),a0-a7
+	ii_lset_dxu 4,f7			// lea d8(a7,dy.w),a0-a7
+	ii_lset_dxu 4,fb			// lea d8(pc,dy.w),a0-a7
+.endm
+
+//---------------------------------------------------------------------------------------------
+// function
+//---------------------------------------------------------------------------------------------
+ii_lea_sub:.macro
+ii_0x4\1\2:
+#ifdef	halten_lea
+	halt
+#endif
+	move.l	\4,a1
+	jsr		ewf
+	move.l	a1,\3
+	ii_end
+.endm
+ii_lea_func:.macro
+//lea d8(ax,dy.w),a0-a7
+	ii_lea_sub	1,f0,a0_off(a7),a0_off(a7)
+	ii_lea_sub	1,f1,a0_off(a7),a1_off(a7)
+	ii_lea_sub	1,f2,a0_off(a7),a2
+	ii_lea_sub	1,f3,a0_off(a7),a3
+	ii_lea_sub	1,f4,a0_off(a7),a4
+	ii_lea_sub	1,f5,a0_off(a7),a5
+	ii_lea_sub	1,f6,a0_off(a7),a6
+	ii_lea_sub	1,f7,a0_off(a7),usp
+	ii_lea_sub	3,f0,a1_off(a7),a0_off(a7)
+	ii_lea_sub	3,f1,a1_off(a7),a1_off(a7)
+	ii_lea_sub	3,f2,a1_off(a7),a2
+	ii_lea_sub	3,f3,a1_off(a7),a3
+	ii_lea_sub	3,f4,a1_off(a7),a4
+	ii_lea_sub	3,f5,a1_off(a7),a5
+	ii_lea_sub	3,f6,a1_off(a7),a6
+	ii_lea_sub	3,f7,a1_off(a7),usp
+	ii_lea_sub	5,f0,a2,a0_off(a7)
+	ii_lea_sub	5,f1,a2,a1_off(a7)
+	ii_lea_sub	5,f2,a2,a2
+	ii_lea_sub	5,f3,a2,a3
+	ii_lea_sub	5,f4,a2,a4
+	ii_lea_sub	5,f5,a2,a5
+	ii_lea_sub	5,f6,a2,a6
+	ii_lea_sub	5,f7,a2,usp
+	ii_lea_sub	7,f0,a3,a0_off(a7)
+	ii_lea_sub	7,f1,a3,a1_off(a7)
+	ii_lea_sub	7,f2,a3,a2
+	ii_lea_sub	7,f3,a3,a3
+	ii_lea_sub	7,f4,a3,a4
+	ii_lea_sub	7,f5,a3,a5
+	ii_lea_sub	7,f6,a3,a6
+	ii_lea_sub	7,f7,a3,usp
+	ii_lea_sub	9,f0,a4,a0_off(a7)
+	ii_lea_sub	9,f1,a4,a1_off(a7)
+	ii_lea_sub	9,f2,a4,a2
+	ii_lea_sub	9,f3,a4,a3
+	ii_lea_sub	9,f4,a4,a4
+	ii_lea_sub	9,f5,a4,a5
+	ii_lea_sub	9,f6,a4,a6
+	ii_lea_sub	9,f7,a4,usp
+	ii_lea_sub	b,f0,a5,a0_off(a7)
+	ii_lea_sub	b,f1,a5,a1_off(a7)
+	ii_lea_sub	b,f2,a5,a2
+	ii_lea_sub	b,f3,a5,a3
+	ii_lea_sub	b,f4,a5,a4
+	ii_lea_sub	b,f5,a5,a5
+	ii_lea_sub	b,f6,a5,a6
+	ii_lea_sub	b,f7,a6,usp
+	ii_lea_sub	d,f0,a6,a0_off(a7)
+	ii_lea_sub	d,f1,a6,a1_off(a7)
+	ii_lea_sub	d,f2,a6,a2
+	ii_lea_sub	d,f3,a6,a3
+	ii_lea_sub	d,f4,a6,a4
+	ii_lea_sub	d,f5,a6,a5
+	ii_lea_sub	d,f6,a6,a6
+	ii_lea_sub	d,f7,a6,usp
+	ii_lea_sub	f,f0,usp,a0_off(a7)
+	ii_lea_sub	f,f1,usp,a1_off(a7)
+	ii_lea_sub	f,f2,usp,a2
+	ii_lea_sub	f,f3,usp,a3
+	ii_lea_sub	f,f4,usp,a4
+	ii_lea_sub	f,f5,usp,a5
+	ii_lea_sub	f,f6,usp,a6
+	ii_lea_sub	f,f7,usp,usp
+// lea d8(pc,dy.w),az
+	ii_lea_sub	1,fb,a0_off(a7),a0
+	ii_lea_sub	3,fb,a1_off(a7),a0
+	ii_lea_sub	5,fb,a2,a0
+	ii_lea_sub	7,fb,a3,a0
+	ii_lea_sub	9,fb,a4,a0
+	ii_lea_sub	b,fb,a5,a0
+	ii_lea_sub	d,fb,a6,a0
+	ii_lea_sub	f,fb,usp,a0
+.endm
\ No newline at end of file
diff --git a/firebeeV1/sources/ii_macro.h b/firebeeV1/sources/ii_macro.h
new file mode 100644
index 0000000..5db7460
--- /dev/null
+++ b/firebeeV1/sources/ii_macro.h
@@ -0,0 +1,144 @@
+/*******************************************************/
+// constanten
+/*******************************************************/
+.extern ___RAMBAR1
+.extern _rt_cacr
+.extern _rt_mod
+.extern _rt_ssp
+.extern _rt_usp
+.extern _rt_vbr
+.extern _d0_save
+.extern _a7_save
+
+ii_ss	=		16
+d0_off	=		0
+d1_off	=		4
+a0_off	=		8
+a1_off	=		12
+format_off =	16
+sr_off	=		18
+ccr_off =		19
+pc_off	=		20
+
+#define 	table 	0x20000000-0x8000-0xF000*4 // Adresse Sprungtabelle 	-> 8000=Sprungbereich mod cod, 61k(ohne 0xFxxx!)x4= tabelle
+
+/*******************************************************/
+// allgemeine macros
+/*******************************************************/
+ii_end:	.macro
+		move.l a0,pc_off(a7)
+		movem.l (a7),d0/d1/a0/a1
+		lea ii_ss(a7),a7
+		rte
+		.endm;
+
+set_cc0:.macro
+		move.w	ccr,d0 
+		move.b	d0,ccr_off(a7)
+		.endm;
+
+ii_esr:	.macro					// geht nicht!!??
+		movem.l		(a7),d0/d1/a0/a1
+		lea			ii_ss+8(a7),a7		// stack erhöhen
+		move.w		d0,_d0_save			// d0.w sicheren
+		move.w		-6(a7),d0			// sr holen
+		move.w		d0,sr				// sr setzen
+		nop
+		move.w		_d0_save,d0			// d0.w zurück
+		.endm;
+
+ii_end_mvm:.macro
+		move.l	a0_off(a7),a0
+		lea		16(a7),a7
+		rte
+		.endm;
+
+ii_endj:.macro
+		movem.l	(a7),d0/d1/a0/a1		// register zurück
+		lea		ii_ss(a7),a7			// korr
+		rte								// ende
+		.endm;
+		
+set_nzvc:.macro							// set ccr bits nzvc
+		move.w	ccr,d1
+		bclr	#4,d1
+		btst	#4,ccr_off(a7)
+		beq		snzvc2\@
+		bset	#4,d1
+snzvc2\@:
+		move.b	d1,ccr_off(a7)
+		.endm;
+		
+set_cc1:.macro
+		move.w	ccr,d1
+		move.b	d1,ccr_off(a7)
+		.endm;
+
+set_cc_b:.macro
+		move.w	ccr,d1
+		btst	#7,d0					// byt negativ?
+		beq		set_cc_b2\@
+		bset	#3,d1					// make negativ
+set_cc_b2\@:
+		move.b	d1,ccr_off(a7)
+		.endm;
+		
+set_cc_w:.macro
+		move.w	ccr,d1
+		btst	#15,d0					// byt negativ?
+		beq		set_cc_w2\@
+		bset	#3,d1					// make negativ
+set_cc_w2\@:
+		move.b	d1,ccr_off(a7)
+		.endm;
+		
+get_pc:	.macro
+		lea.l		(a0),a1
+		.endm;
+
+//--------------------------------------------------------------------
+ii_lset:.macro
+		lea	table+\1*4,a0
+		move.l #ii_\1,(a0)
+		.endm;
+ii_lset_dx:.macro				// 0x1.22 -> z.B. 1=d,2=4 ->0xd040 -> 0xde40
+		ii_lset_dxg	\1,\2
+		ii_lset_dxu	\1,\2
+		.endm;
+ii_lset_dxg:.macro				// gerade: 0x1.22 -> z.B. 1=d,2=4 ->0xd040 -> 0xde40
+		lea 	table+0x\10\2*4,a0
+		move.l	#ii_0x\10\2,(a0)
+		lea		0x800(a0),a0	// 4 * 0x200
+		move.l	#ii_0x\12\2,(a0)
+		lea		0x800(a0),a0
+		move.l	#ii_0x\14\2,(a0)
+		lea		0x800(a0),a0
+		move.l	#ii_0x\16\2,(a0)
+		lea		0x800(a0),a0
+		move.l	#ii_0x\18\2,(a0)
+		lea		0x800(a0),a0
+		move.l	#ii_0x\1a\2,(a0)
+		lea		0x800(a0),a0
+		move.l	#ii_0x\1c\2,(a0)
+		lea		0x800(a0),a0
+		move.l	#ii_0x\1e\2,(a0)
+		.endm;
+ii_lset_dxu:.macro				// ungerade: 0x1.22 -> z.B. 1=d,2=4 ->0xd140 -> 0xdf40
+		lea	table+0x\11\2*4,a0
+		move.l	#ii_0x\11\2,(a0)
+		lea		0x800(a0),a0
+		move.l	#ii_0x\13\2,(a0)
+		lea		0x800(a0),a0
+		move.l	#ii_0x\15\2,(a0)
+		lea		0x800(a0),a0
+		move.l	#ii_0x\17\2,(a0)
+		lea		0x800(a0),a0
+		move.l	#ii_0x\19\2,(a0)
+		lea		0x800(a0),a0
+		move.l	#ii_0x\1b\2,(a0)
+		lea		0x800(a0),a0
+		move.l	#ii_0x\1d\2,(a0)
+		lea		0x800(a0),a0
+		move.l	#ii_0x\1f\2,(a0)
+		.endm;
+
diff --git a/firebeeV1/sources/ii_move.h b/firebeeV1/sources/ii_move.h
new file mode 100644
index 0000000..1ae8213
--- /dev/null
+++ b/firebeeV1/sources/ii_move.h
@@ -0,0 +1,1271 @@
+//-------------------------------------------------------------------
+// move
+//-------------------------------------------------------------------
+.extern		ewf
+
+.text
+ii_move_lset:.macro
+//-------------------------------------------------------------------------
+// 0x1000 move.b
+//-------------------------------------------------------------------------
+// move.x	d16(ax),xxx.w 1=size 2=adress register 
+	ii_lset_opeau	11,e
+// move.x   d16(ax),xxx.l
+	ii_lset_opeau	13,e
+// move.x	d16(pc),xxx.w
+	ii_lset	0x11fa
+// move.x	d16(pc),xxx.l
+	ii_lset	0x13fa
+// move.x	xxx.w,d16(ax)
+	ii_lset_dxu	1,78
+// move.x	xxx.l,d16(ax)
+	ii_lset_dxu	1,79
+// move.x	#xx,d16(ax)
+	ii_lset_dxu	1,7c
+// move.x	xxx.w,xxx.w; 1=size 2=size source adr 3=size dest adr 4=code
+	ii_lset	0x11f8
+// move.x	xxx.l,xxx.w
+	ii_lset	0x11f9
+// move.x	xxx.w,xxx.l
+	ii_lset	0x13f8
+// move.x	xxx.l,xxx.l
+	ii_lset	0x13f9
+// move.x	#xx,xxx.w 	//1=size 2=size dest adr 3=code
+	ii_lset	0x11fc
+// move.x	#xx,xxx.l 	//1=size 2=size dest adr 3=code
+	ii_lset	0x13fc
+//---------------------------------------------------------------------
+// move.x	ea,d8(ax,dy) -------------------------------------------
+//---------------------------------------------------------------------
+// move.x	dx,d8(a0-a7,dy)
+	ii_lset_opeag	11,8
+	ii_lset_opeag	13,8
+	ii_lset_opeag	15,8
+	ii_lset_opeag	17,8
+	ii_lset_opeag	19,8
+	ii_lset_opeag	1b,8
+	ii_lset_opeag	1d,8
+	ii_lset_opeag	1f,8
+// move.x	(ax),d8(a0-a7,dy)
+// move.x	(ax)+,d8(a0-a7,dy)
+	ii_lset_opea	11,9
+	ii_lset_opea	13,9
+	ii_lset_opea	15,9
+	ii_lset_opea	17,9
+	ii_lset_opea	19,9
+	ii_lset_opea	1b,9
+	ii_lset_opea	1d,9
+	ii_lset_opea	1f,9
+// move.x	-(ax),d8(a0-a7,dy)
+	ii_lset_opeag	11,a
+	ii_lset_opeag	13,a
+	ii_lset_opeag	15,a
+	ii_lset_opeag	17,a
+	ii_lset_opeag	19,a
+	ii_lset_opeag	1b,a
+	ii_lset_opeag	1d,a
+	ii_lset_opeag	1f,a
+//---------------------------------------------------------------------
+// move.x	ea,d8(pc,dy) -------------------------------------------
+//---------------------------------------------------------------------
+// move.x	dx,d8(pc,dy)
+	ii_lset_opeag	17,c
+// move.x	(ax),d8(pc,dy)
+// move.x	(ax)+,d8(pc,dy)
+	ii_lset_opea	17,d
+// move.x	-(ax),d8(pc,dy)
+	ii_lset_opeag	17,e
+//---------------------------------------------------------------------
+// move.x	d8(ax,dy),ea --------------------------------------------
+//---------------------------------------------------------------------
+// move.x	d8(ax,dy),d0-d7
+	ii_lset_opeag	10,3
+	ii_lset_opeag	12,3
+	ii_lset_opeag	14,3
+	ii_lset_opeag	16,3
+	ii_lset_opeag	18,3
+	ii_lset_opeag	1a,3
+	ii_lset_opeag	1c,3
+	ii_lset_opeag	1e,3
+// move.x	d8(ax,dy),a0-a7
+	ii_lset_opeag	10,7
+	ii_lset_opeag	12,7
+	ii_lset_opeag	14,7
+	ii_lset_opeag	16,7
+	ii_lset_opeag	18,7
+	ii_lset_opeag	1a,7
+	ii_lset_opeag	1c,7
+	ii_lset_opeag	1e,7
+// move.x	d8(ax,dy),(a0)-(a7)
+	ii_lset_opeag	10,b
+	ii_lset_opeag	12,b
+	ii_lset_opeag	14,b
+	ii_lset_opeag	16,b
+	ii_lset_opeag	18,b
+	ii_lset_opeag	1a,b
+	ii_lset_opeag	1c,b
+	ii_lset_opeag	1e,b
+// move.x	d8(ax,dy),(a0)+-(a7)+
+	ii_lset_opeag	10,f
+	ii_lset_opeag	12,f
+	ii_lset_opeag	14,f
+	ii_lset_opeag	16,f
+	ii_lset_opeag	18,f
+	ii_lset_opeag	1a,f
+	ii_lset_opeag	1c,f
+	ii_lset_opeag	1e,f
+// move.x	d8(ax,dy),-(a0) bis -(a7)
+	ii_lset_opeag	11,3
+	ii_lset_opeag	13,3
+	ii_lset_opeag	15,3
+	ii_lset_opeag	17,3
+	ii_lset_opeag	19,3
+	ii_lset_opeag	1b,3
+	ii_lset_opeag	1d,3
+	ii_lset_opeag	1f,3
+//---------------------------------------------------------------------
+// move.x	d8(pc,dy),ea --------------------------------------------
+//---------------------------------------------------------------------
+// move.x	d8(pc,dy),d0-d7
+	ii_lset_dxg		1,3b
+// move.x	d8(pc,dy),a0-a7
+	ii_lset_dxg		1,7b
+// move.x	d8(pc,dy),(a0-a7)
+	ii_lset_dxg		1,bb
+// move.x	d8(pc,dy),(a0-a7)+
+	ii_lset_dxg		1,fb
+// move.x	d8(pc,dy),(a0-a7)+
+	ii_lset_dxu		1,3b
+//-------------------------------------------------------------------------
+// 0x2000 move.l
+//-------------------------------------------------------------------------
+// move.x	d16(ax),xxx.w 1=size 2=adress register 
+	ii_lset_opeau	21,e
+// move.x   d16(ax),xxx.l
+	ii_lset_opeau	23,e
+// move.x	d16(pc),xxx.w
+	ii_lset	0x21fa
+// move.x	d16(pc),xxx.l
+	ii_lset	0x23fa
+// move.x	xxx.w,d16(ax)
+	ii_lset_dxu	2,78
+// move.x	xxx.l,d16(ax)
+	ii_lset_dxu	2,79
+// move.x	#xx,d16(ax)
+	ii_lset_dxu	2,7c
+// move.x	xxx.w,xxx.w; 1=size 2=size source adr 3=size dest adr 4=code
+	ii_lset	0x21f8
+// move.x	xxx.l,xxx.w
+	ii_lset	0x21f9
+// move.x	xxx.w,xxx.l
+	ii_lset	0x23f8
+// move.x	xxx.l,xxx.l
+	ii_lset	0x23f9
+// move.x	#xx,xxx.w 	//1=size 2=size dest adr 3=code
+	ii_lset	0x21fc
+// move.x	#xx,xxx.l 	//1=size 2=size dest adr 3=code
+	ii_lset	0x23fc
+// move.x	ea,d8(ax,dy) -------------------------------------------
+// move.x	dx,d8(a0-a7,dy)
+	ii_lset_opeag	21,8
+	ii_lset_opeag	23,8
+	ii_lset_opeag	25,8
+	ii_lset_opeag	27,8
+	ii_lset_opeag	29,8
+	ii_lset_opeag	2b,8
+	ii_lset_opeag	2d,8
+	ii_lset_opeag	2f,8
+// move.x	(ax),d8(a0-a7,dy)
+// move.x	(ax)+,d8(a0-a7,dy)
+	ii_lset_opea	21,9
+	ii_lset_opea	23,9
+	ii_lset_opea	25,9
+	ii_lset_opea	27,9
+	ii_lset_opea	29,9
+	ii_lset_opea	2b,9
+	ii_lset_opea	2d,9
+	ii_lset_opea	2f,9
+// move.x	-(ax),d8(a0-a7,dy)
+	ii_lset_opeag	21,a
+	ii_lset_opeag	23,a
+	ii_lset_opeag	25,a
+	ii_lset_opeag	27,a
+	ii_lset_opeag	29,a
+	ii_lset_opeag	2b,a
+	ii_lset_opeag	2d,a
+	ii_lset_opeag	2f,a
+//---------------------------------------------------------------------
+// move.x	ea,d8(pc,dy) -------------------------------------------
+//---------------------------------------------------------------------
+// move.x	dx,d8(pc,dy)
+// move.x	ax,d8(pc,dy)
+	ii_lset_opea	27,c
+// move.x	(ax),d8(pc,dy)
+// move.x	(ax)+,d8(pc,dy)
+	ii_lset_opea	27,d
+// move.x	-(ax),d8(pc,dy)
+	ii_lset_opeag	27,e
+//---------------------------------------------------------------------
+// move.x	d8(ax,dy),ea --------------------------------------------
+//---------------------------------------------------------------------
+// move.x	d8(ax,dy),d0-d7
+	ii_lset_opeag	20,3
+	ii_lset_opeag	22,3
+	ii_lset_opeag	24,3
+	ii_lset_opeag	26,3
+	ii_lset_opeag	28,3
+	ii_lset_opeag	2a,3
+	ii_lset_opeag	2c,3
+	ii_lset_opeag	2e,3
+// move.x	d8(ax,dy),a0-a7
+	ii_lset_opeag	20,7
+	ii_lset_opeag	22,7
+	ii_lset_opeag	24,7
+	ii_lset_opeag	26,7
+	ii_lset_opeag	28,7
+	ii_lset_opeag	2a,7
+	ii_lset_opeag	2c,7
+	ii_lset_opeag	2e,7
+// move.x	d8(ax,dy),(a0)-(a7)
+	ii_lset_opeag	20,b
+	ii_lset_opeag	22,b
+	ii_lset_opeag	24,b
+	ii_lset_opeag	26,b
+	ii_lset_opeag	28,b
+	ii_lset_opeag	2a,b
+	ii_lset_opeag	2c,b
+	ii_lset_opeag	2e,b
+// move.x	d8(ax,dy),(a0)+-(a7)+
+	ii_lset_opeag	20,f
+	ii_lset_opeag	22,f
+	ii_lset_opeag	24,f
+	ii_lset_opeag	26,f
+	ii_lset_opeag	28,f
+	ii_lset_opeag	2a,f
+	ii_lset_opeag	2c,f
+	ii_lset_opeag	2e,f
+// move.x	d8(ax,dy),-(a0) bis -(a7)
+	ii_lset_opeag	21,3
+	ii_lset_opeag	23,3
+	ii_lset_opeag	25,3
+	ii_lset_opeag	27,3
+	ii_lset_opeag	29,3
+	ii_lset_opeag	2b,3
+	ii_lset_opeag	2d,3
+	ii_lset_opeag	2f,3
+//---------------------------------------------------------------------
+// move.x	d8(pc,dy),ea --------------------------------------------
+//---------------------------------------------------------------------
+// move.x	d8(pc,dy),d0-d7
+	ii_lset_dxg		2,3b
+// move.x	d8(pc,dy),a0-a7
+	ii_lset_dxg		2,7b
+// move.x	d8(pc,dy),(a0-a7)
+	ii_lset_dxg		2,bb
+// move.x	d8(pc,dy),(a0-a7)+
+	ii_lset_dxg		2,fb
+// move.x	d8(pc,dy),(a0-a7)+
+	ii_lset_dxu		2,3b
+//-------------------------------------------------------------------------
+// 0x3000 move.w
+///-------------------------------------------------------------------------
+// move.x	d16(ax),xxx.w 1=size 2=adress register 
+	ii_lset_opeau	31,e
+// move.x   d16(ax),xxx.l
+	ii_lset_opeau	33,e
+// move.x	d16(pc),xxx.w
+	ii_lset	0x31fa
+// move.x	d16(pc),xxx.l
+	ii_lset	0x33fa
+// move.x	xxx.w,d16(ax)
+	ii_lset_dxu	3,78
+// move.x	xxx.l,d16(ax)
+	ii_lset_dxu	3,79
+// move.x	#xx,d16(ax)
+	ii_lset_dxu	3,7c
+// move.x	xxx.w,xxx.w; 1=size 2=size source adr 3=size dest adr 4=code
+	ii_lset	0x31f8
+// move.x	xxx.l,xxx.w
+	ii_lset	0x31f9
+// move.x	xxx.w,xxx.l
+	ii_lset	0x33f8
+// move.x	xxx.l,xxx.l
+	ii_lset	0x33f9
+// move.x	#xx,xxx.w 	//1=size 2=size dest adr 3=code
+	ii_lset	0x31fc
+// move.x	#xx,xxx.l 	//1=size 2=size dest adr 3=code
+	ii_lset	0x33fc
+// move.x	ea,d8(ax,dy) -------------------------------------------
+// move.x	dx,d8(a0-a7,dy)
+	ii_lset_opeag	31,8
+	ii_lset_opeag	33,8
+	ii_lset_opeag	35,8
+	ii_lset_opeag	37,8
+	ii_lset_opeag	39,8
+	ii_lset_opeag	3b,8
+	ii_lset_opeag	3d,8
+	ii_lset_opeag	3f,8
+// move.x	(ax),d8(a0-a7,dy)
+// move.x	(ax)+,d8(a0-a7,dy)
+	ii_lset_opea	31,9
+	ii_lset_opea	33,9
+	ii_lset_opea	35,9
+	ii_lset_opea	37,9
+	ii_lset_opea	39,9
+	ii_lset_opea	3b,9
+	ii_lset_opea	3d,9
+	ii_lset_opea	3f,9
+// move.x	-(ax),d8(a0-a7,dy)
+	ii_lset_opeag	31,a
+	ii_lset_opeag	33,a
+	ii_lset_opeag	35,a
+	ii_lset_opeag	37,a
+	ii_lset_opeag	39,a
+	ii_lset_opeag	3b,a
+	ii_lset_opeag	3d,a
+	ii_lset_opeag	3f,a
+//---------------------------------------------------------------------
+// move.x	ea,d8(pc,dy) -------------------------------------------
+//---------------------------------------------------------------------
+// move.x	dx,d8(pc,dy)
+// move.x	ax,d8(pc,dy)
+	ii_lset_opea	37,c
+// move.x	(ax),d8(pc,dy)
+// move.x	(ax)+,d8(pc,dy)
+	ii_lset_opea	37,d
+// move.x	-(ax),d8(pc,dy)
+	ii_lset_opeag	37,e
+//---------------------------------------------------------------------
+// move.x	d8(ax,dy),ea --------------------------------------------
+//---------------------------------------------------------------------
+// move.x	d8(ax,dy),d0-d7
+	ii_lset_opeag	30,3
+	ii_lset_opeag	32,3
+	ii_lset_opeag	34,3
+	ii_lset_opeag	36,3
+	ii_lset_opeag	38,3
+	ii_lset_opeag	3a,3
+	ii_lset_opeag	3c,3
+	ii_lset_opeag	3e,3
+// move.x	d8(ax,dy),a0-a7
+	ii_lset_opeag	30,7
+	ii_lset_opeag	32,7
+	ii_lset_opeag	34,7
+	ii_lset_opeag	36,7
+	ii_lset_opeag	38,7
+	ii_lset_opeag	3a,7
+	ii_lset_opeag	3c,7
+	ii_lset_opeag	3e,7
+// move.x	d8(ax,dy),(a0)-(a7)
+	ii_lset_opeag	30,b
+	ii_lset_opeag	32,b
+	ii_lset_opeag	34,b
+	ii_lset_opeag	36,b
+	ii_lset_opeag	38,b
+	ii_lset_opeag	3a,b
+	ii_lset_opeag	3c,b
+	ii_lset_opeag	3e,b
+// move.x	d8(ax,dy),(a0)+-(a7)+
+	ii_lset_opeag	30,f
+	ii_lset_opeag	32,f
+	ii_lset_opeag	34,f
+	ii_lset_opeag	36,f
+	ii_lset_opeag	38,f
+	ii_lset_opeag	3a,f
+	ii_lset_opeag	3c,f
+	ii_lset_opeag	3e,f
+// move.x	d8(ax,dy),-(a0) bis -(a7)
+	ii_lset_opeag	31,3
+	ii_lset_opeag	33,3
+	ii_lset_opeag	35,3
+	ii_lset_opeag	37,3
+	ii_lset_opeag	39,3
+	ii_lset_opeag	3b,3
+	ii_lset_opeag	3d,3
+	ii_lset_opeag	3f,3
+//---------------------------------------------------------------------
+// move.x	d8(pc,dy),ea --------------------------------------------
+//---------------------------------------------------------------------
+// move.x	d8(pc,dy),d0-d7
+	ii_lset_dxg		3,3b
+// move.x	d8(pc,dy),a0-a7
+	ii_lset_dxg		3,7b
+// move.x	d8(pc,dy),(a0-a7)
+	ii_lset_dxg		3,bb
+// move.x	d8(pc,dy),(a0-a7)+
+	ii_lset_dxg		3,fb
+// move.x	d8(pc,dy),(a0-a7)+
+	ii_lset_dxu		3,3b
+.endm
+//---------------------------------------------------------------------------------------------
+// function
+//---------------------------------------------------------------------------------------------
+ii_move_op:.macro
+// move.x	d16(ax),xxx.w 1=size 2=adress register 
+	ii_move_d16ax_xxx	1e8,a0_off(a7),w
+	ii_move_d16ax_xxx	1e9,a1_off(a7),w
+	ii_move_d16ax_xxx	1ea,a2,w
+	ii_move_d16ax_xxx	1eb,a3,w
+	ii_move_d16ax_xxx	1ec,a4,w
+	ii_move_d16ax_xxx	1ed,a5,w
+	ii_move_d16ax_xxx	1ee,a6,w
+	ii_move_d16ax_xxx	1ef,usp,w
+// move.x   d16(ax),xxx.l
+	ii_move_d16ax_xxx	3e8,a0_off(a7),l
+	ii_move_d16ax_xxx	3e9,a1_off(a7),l
+	ii_move_d16ax_xxx	3ea,a2,l
+	ii_move_d16ax_xxx	3eb,a3,l
+	ii_move_d16ax_xxx	3ec,a4,l
+	ii_move_d16ax_xxx	3ed,a5,l
+	ii_move_d16ax_xxx	3ee,a6,l
+	ii_move_d16ax_xxx	3ef,usp,l
+// move.x	d16(pc),xxx.w
+	ii_move_d16ax_xxx	1fa,a0,w
+// move.x	d16(pc),xxx.l
+	ii_move_d16ax_xxx	3fa,a0,l
+// move.x	xxx.w,d16(ax)
+// move.x	xxx.l,d16(ax)
+// move.x	#xx,d16(ax)
+	ii_move_xxx_d16ax	1,a0_off(a7)
+	ii_move_xxx_d16ax	3,a1_off(a7)
+	ii_move_xxx_d16ax	5,a2
+	ii_move_xxx_d16ax	7,a3
+	ii_move_xxx_d16ax	9,a4
+	ii_move_xxx_d16ax	b,a5
+	ii_move_xxx_d16ax	d,a6
+	ii_move_xxx_d16ax	f,usp
+// move.x	xxx.w,xxx.w; 1=size 2=size source adr 3=size dest adr 4=code
+	ii_move_xxx_xxx		b,w,w,11f8
+	ii_move_xxx_xxx		l,w,w,21f8
+	ii_move_xxx_xxx		w,w,w,31f8
+// move.x	xxx.l,xxx.w
+	ii_move_xxx_xxx		b,l,w,11f9
+	ii_move_xxx_xxx		l,l,w,21f9
+	ii_move_xxx_xxx		w,l,w,31f9
+// move.x	xxx.w,xxx.l
+	ii_move_xxx_xxx		b,w,l,13f8
+	ii_move_xxx_xxx		l,w,l,23f8
+	ii_move_xxx_xxx		w,w,l,33f8
+// move.x	xxx.l,xxx.l
+	ii_move_xxx_xxx		b,l,l,13f9
+	ii_move_xxx_xxx		l,l,l,23f9
+	ii_move_xxx_xxx		w,l,l,33f9
+// move.x	#xx,xxx.w 	//1=size 2=size dest adr 3=code
+	ii_move_im_xxx		b,w,11fc
+	ii_move_im_xxx		l,w,21fc
+	ii_move_im_xxx		w,w,31fc
+// move.x	#xx,xxx.l 	//1=size 2=size dest adr 3=code
+	ii_move_im_xxx		b,l,13fc
+	ii_move_im_xxx		l,l,23fc
+	ii_move_im_xxx		w,l,33fc
+//---------------------------------------------------------------------
+// move.x	ea,d8(ax,dy) -------------------------------------------
+//---------------------------------------------------------------------
+// move.x	dx,d8(ax/pc,dy)
+	ii_move_dxxia	d0_off(a7),80,id,d,c0
+	ii_move_dxxia	d1_off(a7),81,id,d,c1
+	ii_move_dxxia	d2,82,d,d,c2
+	ii_move_dxxia	d3,83,d,d,c3
+	ii_move_dxxia	d4,84,d,d,c4
+	ii_move_dxxia	d5,85,d,d,c5
+	ii_move_dxxia	d6,86,d,d,c6
+	ii_move_dxxia	d7,87,d,d,c7
+// move.x	ax,d8(ax/pc,dy)
+	ii_move_dxxia	a0_off(a7),88,id,d,c8
+	ii_move_dxxia	a1_off(a7),89,id,d,c9
+	ii_move_dxxia	a2,8a,d,da,ca
+	ii_move_dxxia	a3,8b,d,da,cb
+	ii_move_dxxia	a4,8c,d,da,cc
+	ii_move_dxxia	a5,8d,d,da,cd
+	ii_move_dxxia	a6,8e,d,da,ce
+	ii_move_dxxia	a7,8f,a7,da,cf
+// move.x	(ax),d8(ax/pc,dy)
+	ii_move_dxxia	a0_off(a7),90,ia,d,d0
+	ii_move_dxxia	a1_off(a7),91,ia,d,d1
+	ii_move_dxxia	(a2),92,d,d,d2
+	ii_move_dxxia	(a3),93,d,d,d3
+	ii_move_dxxia	(a4),94,d,d,d4
+	ii_move_dxxia	(a5),95,d,d,d5
+	ii_move_dxxia	(a6),96,d,d,d6
+	ii_move_dxxia	(a7),97,a7,d,d7
+// move.x	(ax)+,d8(ax/pc,dy)
+	ii_move_dxxia	a0_off(a7),98,iap,d,d8
+	ii_move_dxxia	a1_off(a7),99,iap,d,d9
+	ii_move_dxxia	(a2)+,9a,d,d,da
+	ii_move_dxxia	(a3)+,9b,d,d,db
+	ii_move_dxxia	(a4)+,9c,d,d,dc
+	ii_move_dxxia	(a5)+,9d,d,d,dd
+	ii_move_dxxia	(a6)+,9e,d,d,de
+	ii_move_dxxia	(a7)+,9f,a7,d,df
+// move.x	-(ax),d8(ax/pc,dy)
+	ii_move_dxxia	a0_off(a7),a0,iam,d,e0
+	ii_move_dxxia	a1_off(a7),a1,iam,d,e1
+	ii_move_dxxia	-(a2),a2,d,d,e2
+	ii_move_dxxia	-(a3),a3,d,d,e3
+	ii_move_dxxia	-(a4),a4,d,d,e4
+	ii_move_dxxia	-(a5),a5,d,d,e5
+	ii_move_dxxia	-(a6),a6,d,d,e6
+	ii_move_dxxia	-(a7),a7,a7,d,e7
+//---------------------------------------------------------------------
+// move.x	d8(ax/pc,dy),ea --------------------------------------------
+//---------------------------------------------------------------------
+// move.x	d8(ax/pc,dy),dz
+	ii_move_d8_dest	d0,id,03,dx	
+	ii_move_d8_dest	d1,id,23,dx	
+	ii_move_d8_dest	d2,d,43,dx	
+	ii_move_d8_dest	d3,d,63,dx	
+	ii_move_d8_dest	d4,d,83,dx	
+	ii_move_d8_dest	d5,d,a3,dx
+	ii_move_d8_dest	d6,d,c3,dx
+	ii_move_d8_dest	d7,d,e3,dx
+// move.x	d8(ax/pc,dy),az
+	ii_move_d8_dest	a0,id,07,ax	
+	ii_move_d8_dest	a1,id,27,ax	
+	ii_move_d8_dest	a2,d,47,ax	
+	ii_move_d8_dest	a3,d,67,ax	
+	ii_move_d8_dest	a4,d,87,ax	
+	ii_move_d8_dest	a5,d,a7,ax	
+	ii_move_d8_dest	a6,d,c7,ax	
+	ii_move_d8_dest	usp,id,e7,ax	
+// move.x	d8(ax/pc,dy),(az)
+	ii_move_d8_dest	a0_off(a7),id,0b,ia	
+	ii_move_d8_dest	a1_off(a7),id,2b,ia	
+	ii_move_d8_dest	(a2),d,4b,ia	
+	ii_move_d8_dest	(a3),d,6b,ia	
+	ii_move_d8_dest	(a4),d,8b,ia	
+	ii_move_d8_dest	(a5),d,ab,ia	
+	ii_move_d8_dest	(a6),d,cb,ia	
+	ii_move_d8_dest	usp,id,eb,ia	
+// move.x	d8(ax/pc,dy),(az)+
+	ii_move_d8_dest	a0_off(a7),id,0f,iap	
+	ii_move_d8_dest	a1_off(a7),id,2f,iap	
+	ii_move_d8_dest	(a2)+,d,4f,iap	
+	ii_move_d8_dest	(a3)+,d,6f,iap	
+	ii_move_d8_dest	(a4)+,d,8f,iap	
+	ii_move_d8_dest	(a5)+,d,af,iap	
+	ii_move_d8_dest	(a6)+,d,cf,iap	
+	ii_move_d8_dest	usp,id,ef,iap	
+// move.x	d8(ax/pc,dy),-(az)
+	ii_move_d8_dest	a0_off(a7),id,13,iam	
+	ii_move_d8_dest	a1_off(a7),id,33,iam	
+	ii_move_d8_dest	-(a2),d,53,iam	
+	ii_move_d8_dest	-(a3),d,73,iam	
+	ii_move_d8_dest	-(a4),d,93,iam	
+	ii_move_d8_dest	-(a5),d,b3,iam	
+	ii_move_d8_dest	-(a6),d,d3,iam	
+	ii_move_d8_dest	usp,id,f3,iam	
+.endm //end function
+//====================================================================
+// subs ----------------------------------------------------------
+//====================================================================
+// move.x	d16(ax),xxx.w/l 1=code 2=adress register 3=dest adr size
+ii_move_d16ax_xxx:.macro
+ii_0x1\1:			//byt:
+#ifdef	halten_move
+	halt
+#endif
+	mvs.w	(a0)+,d0
+	move.l	\2,a1
+	add.l	d0,a1
+	move.b	(a1),d0
+	move.\3	(a0)+,a1
+	move.b	d0,(a1)
+	set_cc0
+	ii_end
+ii_0x2\1:			//long:
+#ifdef	halten_move
+	halt
+#endif
+	mvs.w	(a0)+,d0
+	move.l	\2,a1
+	add.l	d0,a1
+	move.l	(a1),d0
+	move.\3	(a0)+,a1
+	move.l	d0,(a1)
+	set_cc0
+	ii_end
+ii_0x3\1:			//word:
+#ifdef	halten_move
+	halt
+#endif
+	mvs.w	(a0)+,d0
+	move.l	\2,a1
+	add.l	d0,a1
+	move.w	(a1),d0
+	move.\3	(a0)+,a1
+	move.w	d0,(a1)
+	set_cc0
+	ii_end
+.endm
+//----------------------------------------
+// move.x	xxx.w,d16(ax)
+// move.x	xxx.l,d16(ax)
+// move.x	#xx,d16(ax)
+ii_move_xxx_d16ax:.macro	//1=code 2=adress register
+ii_0x1\178:			//byt xxx.w
+#ifdef	halten_move
+	halt
+#endif
+	move.w	(a0)+,a1
+	move.b	(a1),d0
+	move.l	\2,a1
+	mvs.w	(a0)+,d1
+	add.l	d1,a1
+	move.b	d0,(a1)
+	set_cc0
+	ii_end
+ii_0x1\179:			//byt xxx.l
+#ifdef	halten_move
+	halt
+#endif
+	move.l	(a0)+,a1
+	move.b	(a1),d0
+	move.l	\2,a1
+	mvs.w	(a0)+,d1
+	add.l	d1,a1
+	move.b	d0,(a1)
+	set_cc0
+	ii_end
+ii_0x1\17c:			//byt #x
+#ifdef	halten_move
+	halt
+#endif
+	mvs.b	(a0)+,d0
+	move.l	\2,a1
+	mvs.w	(a0)+,d1
+	add.l	d1,a1
+	move.b	d0,(a1)
+	set_cc0
+	ii_end
+ii_0x2\178:			//long xxx.w
+#ifdef	halten_move
+	halt
+#endif
+	move.w	(a0)+,a1
+	move.l	(a1),d0
+	move.l	\2,a1
+	mvs.w	(a0)+,d1
+	add.l	d1,a1
+	move.l	d0,(a1)
+	set_cc0
+	ii_end
+ii_0x2\179:			//long xxx.l
+#ifdef	halten_move
+	halt
+#endif
+	move.l	(a0)+,a1
+	move.l	(a1),d0
+	move.l	\2,a1
+	mvs.w	(a0)+,d1
+	add.l	d1,a1
+	move.l	d0,(a1)
+	set_cc0
+	ii_end
+ii_0x2\17c:			//long #x
+#ifdef	halten_move
+	halt
+#endif
+	move.l	(a0)+,d0
+	move.l	\2,a1
+	mvs.w	(a0)+,d1
+	add.l	d1,a1
+	move.l	d0,(a1)
+	set_cc0
+	ii_end
+	ii_end
+ii_0x3\178:			//word xxx.w
+#ifdef	halten_move
+	halt
+#endif
+	move.w	(a0)+,a1
+	move.w	(a1),d0
+	move.l	\2,a1
+	mvs.w	(a0)+,d1
+	add.l	d1,a1
+	move.w	d0,(a1)
+	set_cc0
+	ii_end
+ii_0x3\179:			//word xxx.l
+#ifdef	halten_move
+	halt
+#endif
+	move.l	(a0)+,a1
+	move.w	(a1),d0
+	move.l	\2,a1
+	mvs.w	(a0)+,d1
+	add.l	d1,a1
+	move.w	d0,(a1)
+	set_cc0
+	ii_end
+ii_0x3\17c:			//word #x
+#ifdef	halten_move
+	halt
+#endif
+	move.w	(a0)+,d0
+	move.l	\2,a1
+	mvs.w	(a0)+,d1
+	add.l	d1,a1
+	move.w	d0,(a1)
+	set_cc0
+	ii_end
+.endm
+// move.x	xxx,xxx
+ii_move_xxx_xxx:.macro	//1=size 2=size source adr 3=size dest adr 4=code
+ii_0x\4:	
+#ifdef	halten_move
+	halt
+#endif
+	move.\2	(a0)+,a1
+	move.\1	(a1),d0
+	move.\3	(a0)+,d1
+	move.\1	d0,(a1)
+	set_cc0
+	ii_end
+.endm
+// move.x	im,xxx
+ii_move_im_xxx:.macro	//1=size 2=size dest adr 3=code
+ii_0x\3:	
+#ifdef	halten_move
+	halt
+#endif
+.ifc	1,b
+	move.w	(a0)+,d0
+.else
+	move.\1	(a0)+,d0
+.endif
+	move.\2	(a0)+,a1
+	move.\1	d0,(a1)
+	set_cc0
+	ii_end
+.endm
+//---------------------------------------------------------------------
+// move.x	ea,d8(ax,dy) -------------------------------------------
+//---------------------------------------------------------------------
+// ea=dx,ax,(ax),(ax)+,-(ax) 
+//---------------------------------------------------------------------
+ii_move_dxxia:.macro  //1=source 2=code 1.stelle 3=code 2 letzte Stellen 4=art 5=code d8(pc,dy)	
+.ifc	\3,id 
+	ii_move_dxxi	b,\1+3,1,\2,\3,\5
+	ii_move_dxxi	w,\1+2,2,\2,\3,\5
+	ii_move_dxxi	l,\1,3,\2,\3,\5
+.else
+	.ifc	\4,da 
+		ii_move_dxxi	w,\1,2,\2,\3,\5
+		ii_move_dxxi	l,\1,3,\2,\3,\5
+	.else
+ 		ii_move_dxxi	b,\1,1,\2,\3,\5
+		ii_move_dxxi	w,\1,2,\2,\3,\5
+		ii_move_dxxi	l,\1,3,\2,\3,\5
+	.endif
+.endif
+.endm 
+
+ii_move_dxxi:.macro
+ii_0x\31\4:	//1=size 2=source 3=code 1.stelle 4=code 2 letzte Stellen
+#ifdef	halten_move
+	halt
+#endif
+	move.l	a0_off(a7),a1
+	move_end	\1,\2,\5
+ii_0x\33\4:	//1=size 2=source 3=code 1.stelle 4=code 2 letzte Stellen
+#ifdef	halten_move
+	halt
+#endif
+	move.l	a1_off(a7),a1
+	move_end	\1,\2,\5
+ii_0x\35\4:	//1=size 2=source 3=code 1.stelle 4=code 2 letzte Stellen
+#ifdef	halten_move
+	halt
+#endif
+	move.l	a2,a1
+	move_end	\1,\2,\5
+ii_0x\37\4:	//1=size 2=source 3=code 1.stelle 4=code 2 letzte Stellen
+#ifdef	halten_move
+	halt
+#endif
+	move.l	a3,a1
+	move_end	\1,\2,\5
+ii_0x\39\4:	//1=size 2=source 3=code 1.stelle 4=code 2 letzte Stellen
+#ifdef	halten_move
+	halt
+#endif
+	move.l	a4,a1
+	move_end	\1,\2,\5
+ii_0x\3b\4:	//1=size 2=source 3=code 1.stelle 4=code 2 letzte Stellen
+#ifdef	halten_move
+	halt
+#endif
+	move.l	a5,a1
+	move_end	\1,\2,\5
+ii_0x\3d\4:	//1=size 2=source 3=code 1.stelle 4=code 2 letzte Stellen
+#ifdef	halten_move
+	halt
+#endif
+	move.l	a6,a1
+	move_end	\1,\2,\5
+ii_0x\3f\4:	//1=size 2=source 3=code 1.stelle 4=code 2 letzte Stellen
+#ifdef	halten_move
+	halt
+#endif
+	move.l	usp,a1
+	move_end	\1,\2,\5
+ii_0x\37\6:	//1=size 2=source 3=code 1.stelle 4=code 2 letzte Stellen
+#ifdef	halten_move
+	halt
+#endif
+	move.l	a0,a1
+	move_end	\1,\2,\5
+.endm
+//------------------------------------
+move_end:.macro
+	jsr		ewf
+.ifc	3,a7
+	move.l	a7,d1		// a7 sichern
+	move.l 	usp,a7		// a7 holen
+.endif
+.ifc	3,ia
+	move.l	a2,d1		// a2 sichern
+	move.l	\2,a2
+	move.\2	(a2),(a1)
+	move.l	d1,a2		// a2 zurück
+.else
+	.ifc	3,iap
+		move.l	a2,d1		// a2 sichern
+		move.l	\2,a2
+		move.\2	(a2)+,(a1)
+	.else
+		.ifc	3,iam
+			move.l	a2,d1		// a2 sichern
+			move.l	\2,a2
+			move.\2	-(a2),(a1)
+		.else
+			move.\1	\2,(a1)
+		.endif
+	.endif
+.endif
+.ifc	3,a7
+	movea.l	a7,usp		// a7 zurück
+	movea.l d1,a7		// a7 setzen
+.endif
+	set_cc0
+.ifc	3,iap
+	move.l	d1,a2		// a2 zurück
+.endif
+.ifc	3,iam
+	move.l	d1,a2		// a2 zurück
+.endif
+	ii_end
+.endm
+//---------------------------------------------------------------------
+// move.x 	ea,d8(pc,dy)
+//---------------------------------------------------------------------
+
+//---------------------------------------------------------------------
+// move.x	d8(ax,dy),ea ---------------------------------------------
+//---------------------------------------------------------------------
+ii_move_d8_dest:.macro	//1=dest 2=art 3=code 2.+3.stelle 4=art adresse
+//byt
+ii_0x1\30:	
+#ifdef	halten_move
+	halt
+#endif
+			move.l	a0_off(a7),a1
+			moveb_a1_src\4	\1,\2
+ii_0x1\31:	
+#ifdef	halten_move
+	halt
+#endif
+			move.l	a1_off(a7),a1
+			moveb_a1_src\4	\1,\2
+ii_0x1\32:	
+#ifdef	halten_move
+	halt
+#endif
+			move.l	a2,a1
+			moveb_a1_src\4	\1,\2
+ii_0x1\33:	
+#ifdef	halten_move
+	halt
+#endif
+			move.l	a3,a1
+			moveb_a1_src\4	\1,\2
+ii_0x1\34:	
+#ifdef	halten_move
+	halt
+#endif
+			move.l	a4,a1
+			moveb_a1_src\4	\1,\2
+ii_0x1\35:	
+#ifdef	halten_move
+	halt
+#endif
+			move.l	a5,a1
+			moveb_a1_src\4	\1,\2
+ii_0x1\36:	
+#ifdef	halten_move
+	halt
+#endif
+			move.l	a6,a1
+			moveb_a1_src\4	\1,\2
+ii_0x1\37:	
+#ifdef	halten_move
+	halt
+#endif
+			move.l	usp,a1
+			moveb_a1_src\4	\1,\2
+ii_0x1\3b:	
+#ifdef	halten_move
+	halt
+#endif
+			move.l	a0,a1
+			moveb_a1_src\4	\1,\2
+//long
+ii_0x2\30:	
+#ifdef	halten_move
+	halt
+#endif
+			move.l	a0_off(a7),a1
+			movel_a1_src\4	\1,\2
+ii_0x2\31:	
+#ifdef	halten_move
+	halt
+#endif
+			move.l	a1_off(a7),a1
+			movel_a1_src\4	\1,\2
+ii_0x2\32:	
+#ifdef	halten_move
+	halt
+#endif
+			move.l	a2,a1
+			movel_a1_src\4	\1,\2
+ii_0x2\33:	
+#ifdef	halten_move
+	halt
+#endif
+			move.l	a3,a1
+			movel_a1_src\4	\1,\2
+ii_0x2\34:	
+#ifdef	halten_move
+	halt
+#endif
+			move.l	a4,a1
+			movel_a1_src\4	\1,\2
+ii_0x2\35:	
+#ifdef	halten_move
+	halt
+#endif
+			move.l	a5,a1
+			movel_a1_src\4	\1,\2
+ii_0x2\36:	
+#ifdef	halten_move
+	halt
+#endif
+			move.l	a6,a1
+			movel_a1_src\4	\1,\2
+ii_0x2\37:	
+#ifdef	halten_move
+	halt
+#endif
+			move.l	usp,a1
+			movel_a1_src\4	\1,\2
+ii_0x2\3b:	
+#ifdef	halten_move
+	halt
+#endif
+			move.l	a0,a1
+			moveb_a1_src\4	\1,\2
+//word
+ii_0x3\30:	
+#ifdef	halten_move
+	halt
+#endif
+			move.l	a0_off(a7),a1
+			movew_a1_src\4	\1,\2
+ii_0x3\31:	
+#ifdef	halten_move
+	halt
+#endif
+			move.l	a1_off(a7),a1
+			movew_a1_src\4	\1,\2
+ii_0x3\32:	
+#ifdef	halten_move
+	halt
+#endif
+			move.l	a2,a1
+			movew_a1_src\4	\1,\2
+ii_0x3\33:	
+#ifdef	halten_move
+	halt
+#endif
+			move.l	a3,a1
+			movew_a1_src\4	\1,\2
+ii_0x3\34:	
+#ifdef	halten_move
+	halt
+#endif
+			move.l	a4,a1
+			movew_a1_src\4	\1,\2
+ii_0x3\35:	
+#ifdef	halten_move
+	halt
+#endif
+			move.l	a5,a1
+			movew_a1_src\4	\1,\2
+ii_0x3\36:	
+#ifdef	halten_move
+	halt
+#endif
+			move.l	a6,a1
+			movew_a1_src\4	\1,\2
+ii_0x3\37:	
+#ifdef	halten_move
+	halt
+#endif
+			move.l	usp,a1
+			movew_a1_src\4	\1,\2
+ii_0x3\3b:	
+#ifdef	halten_move
+	halt
+#endif
+			move.l	a0,a1
+			moveb_a1_src\4	\1,\2
+.endm
+//---------------------------------------------------------------------
+//dx
+moveb_a1_srcdx:.macro
+			jsr		ewf
+.ifc	\2,id
+			move.b	(a1),\1_off+3(a7)
+.else
+			move.b	(a1),\1
+.endif
+			set_cc0
+			ii_end
+.endm
+movel_a1_srcdx:.macro
+			jsr		ewf
+.ifc	\2,id
+			move.l	(a1),\1_off(a7)
+.else
+			move.l	(a1),\1
+.endif
+			set_cc0
+			ii_end
+.endm
+movew_a1_srcdx:.macro
+			jsr		ewf
+.ifc	\2,id
+			move.w	(a1),\1_off+2(a7)
+.else
+			move.w	(a1),\1
+.endif
+			set_cc0
+			ii_end
+.endm
+// ax
+moveb_a1_srcax:.macro
+			jsr		ewf
+.ifc	\2,id
+	.ifc	\1,usp
+			move.w	(a1),a1
+			move.l	a1,usp
+	.else
+			move.w	(a1),\1_off+2(a7)
+	.endif
+.else
+			move.w	(a1),\1
+.endif
+			set_cc0
+			ii_end
+.endm
+movel_a1_srcax:.macro
+			jsr		ewf
+.ifc	\2,id
+	.ifc	\1,usp
+			move.l	(a1),a1
+			move.l	a1,usp
+	.else
+			move.l	(a1),\1_off(a7)
+	.endif
+.else
+			move.l	(a1),\1
+.endif
+			set_cc0
+			ii_end
+.endm
+movew_a1_srcax:.macro
+			jsr		ewf
+.ifc	\2,id
+	.ifc	\1,usp
+			move.w	(a1),a1
+			move.l	a1,usp
+	.else
+			move.w	(a1),\1_off+2(a7)
+	.endif
+.else
+			move.w	(a1),\1
+.endif
+			set_cc0
+			ii_end
+.endm
+// (ax)
+moveb_a1_srcia:.macro
+			jsr		ewf
+.ifc	\2,id
+			move.b	(a1),d0
+			move.l	\1,a1
+			move.b	d0,(a1)
+.else
+			move.b	(a1),\1
+.endif
+			set_cc0
+			ii_end
+.endm
+movel_a1_srcia:.macro
+			jsr		ewf
+.ifc	\2,id
+			move.l	(a1),d0
+			move.l	\1,a1
+			move.l	d0,(a1)
+.else
+			move.l	(a1),\1
+.endif
+			set_cc0
+			ii_end
+.endm
+movew_a1_srcia:.macro
+			jsr		ewf
+.ifc	\2,id
+			move.w	(a1),d0
+			move.l	\1,a1
+			move.w	d0,(a1)
+.else
+			move.w	(a1),\1
+.endif
+			set_cc0
+			ii_end
+.endm
+// (ax)+
+moveb_a1_srciap:.macro
+			jsr		ewf
+.ifc	\2,id
+			move.b	(a1),d0
+			move.l	\1,a1
+			move.b	d0,(a1)+
+			move.l	a1,\1
+.else
+			move.b	(a1),\1
+.endif
+			set_cc0
+			ii_end
+.endm
+movel_a1_srciap:.macro
+			jsr		ewf
+.ifc	\2,id
+			move.l	(a1),d0
+			move.l	\1,a1
+			move.l	d0,(a1)+
+			move.l	a1,\1
+.else
+			move.l	(a1),\1
+.endif
+			set_cc0
+			ii_end
+.endm
+movew_a1_srciap:.macro
+			jsr		ewf
+.ifc	\2,id
+			move.w	(a1),d0
+			move.l	\1,a1
+			move.w	d0,(a1)+
+			move.l	a1,\1
+.else
+			move.w	(a1),\1
+.endif
+			set_cc0
+			ii_end
+.endm
+// -(ax)
+moveb_a1_srciam:.macro
+			jsr		ewf
+.ifc	\2,id
+			move.b	(a1),d0
+			move.l	\1,a1
+			move.b	d0,-(a1)
+			move.l	a1,\1
+.else
+			move.b	(a1),\1
+.endif
+			set_cc0
+			ii_end
+.endm
+movel_a1_srciam:.macro
+			jsr		ewf
+.ifc	\2,id
+			move.l	(a1),d0
+			move.l	\1,a1
+			move.l	d0,-(a1)
+			move.l	a1,\1
+.else
+			move.l	(a1),\1
+.endif
+			set_cc0
+			ii_end
+.endm
+movew_a1_srciam:.macro
+			jsr		ewf
+.ifc	\2,id
+			move.w	(a1),d0
+			move.l	\1,a1
+			move.w	d0,-(a1)
+			move.l	a1,\1
+.else
+			move.w	(a1),\1
+.endif
+			set_cc0
+			ii_end
+.endm
+
+//---------------------------------------------------------------------
+// move.x	d8(pc,dy),ea
+//---------------------------------------------------------------------
+
+
+ 
+/*============================================================
+// move.w dx,(a0,dx.w*SF)
+	ii_lset		0x3180
+	ii_lset		0x3181
+	ii_lset		0x3182
+	ii_lset		0x3183
+	ii_lset		0x3184
+	ii_lset		0x3185
+	ii_lset		0x3186
+	ii_lset		0x3187 
+
+//--------------------------------------------------------------------
+// // move.w	dx,d(ay,dz.w*sf)
+//--------------------------------------------------------------------
+movew_ewfw:.macro
+	move.l		\2,a1
+	jsr			ewf
+	move.w		\1,(a1)
+	set_cc0
+	ii_end
+	.endm
+ii_0x3180:
+	movew_ewfw 	d0_off+2(a7),a0_off(a7)
+ii_0x3181:
+	movew_ewfw 	d0_off+2(a7),a0_off(a7)
+ii_0x3182:
+	movew_ewfw 	d2,a0_off(a7)
+ii_0x3183:
+	movew_ewfw 	d3,a0_off(a7)
+ii_0x3184:
+	movew_ewfw 	d4,a0_off(a7)
+ii_0x3185:
+	movew_ewfw 	d5,a0_off(a7)
+ii_0x3186:
+	movew_ewfw 	d6,a0_off(a7)
+ii_0x3187:
+	movew_ewfw 	d7,a0_off(a7)
diff --git a/firebeeV1/sources/ii_movem.h b/firebeeV1/sources/ii_movem.h
new file mode 100644
index 0000000..5e8a470
--- /dev/null
+++ b/firebeeV1/sources/ii_movem.h
@@ -0,0 +1,374 @@
+//***********************************************************************************/
+// movem
+//***********************************************************************************/
+ii_movem_lset: .macro
+// movem.l rx,xxx.L
+	ii_lset		0x48f9
+// movem.l xxx.L,rx
+	ii_lset		0x4cf9
+// movem.w rx,xxx.L
+	ii_lset		0x48b9
+// movem.w xxx.L,rx
+	ii_lset		0x4cb9
+// movem.l rx,-(ax)
+	ii_lset		0x48e0
+	ii_lset		0x48e1
+	ii_lset		0x48e2
+	ii_lset		0x48e3
+	ii_lset		0x48e4
+	ii_lset		0x48e5
+	ii_lset		0x48e6
+	ii_lset		0x48e7
+// movem.l (ax)+,rx
+	ii_lset		0x4cd8
+	ii_lset		0x4cd9
+	ii_lset		0x4cda
+	ii_lset		0x4cdb
+	ii_lset		0x4cdc
+	ii_lset		0x4cdd
+	ii_lset		0x4cde
+	ii_lset		0x4cdf
+.endm
+//***********************************************************************************/
+ii_movem_func: .macro
+//-------------------------------------------------------------------
+// movem.l
+//--------------------------------------------------------------------
+// movem.l (ax)+,reg
+//--------------------------------------------------------------------
+	.long		0
+az_reg_table:
+	.byte		0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4		// 0-f
+	.byte		1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5		// 10-1f
+	.byte		1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5		// 20-2f
+	.byte		2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6		// 30-3f
+	.byte		1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5		// 40-4f
+	.byte		2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6		// 50
+	.byte		2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6		// 60
+	.byte		3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7		// 70
+	.byte		1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5		// 80-8f
+	.byte		2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6		// 90
+	.byte		2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6		// a0
+	.byte		3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7		// b0
+	.byte		2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6		// c0
+	.byte		3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7		// d0
+	.byte		3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7		// e0
+	.byte		4,5,5,6,5,6,6,7,5,6,6,7,6,7,7,8		// f0
+//-------------------------------------------------------------------------------
+ii_0x48e0:		// movem.l reglist,-(a0)
+	mvm_mem_macro	0x48d0,a0_off(a7),2
+ii_0x48e1:		// movem.l reglist,-(a1)
+	mvm_mem_macro	0x48d1,a1_off(a7),2
+ii_0x48e2:		// movem.l reglist,-(a2)
+	mvm_mem_macro	0x48d2,a2,2
+ii_0x48e3:		// movem.l reglist,-(a3)
+	mvm_mem_macro	0x48d3,a3,2
+ii_0x48e4:		// movem.l reglist,-(a4)
+	mvm_mem_macro	0x48d4,a4,2
+ii_0x48e5:		// movem.l reglist,-(a5)
+	mvm_mem_macro	0x48d5,a5,2
+ii_0x48e6:		// movem.l reglist,-(a6)
+	mvm_mem_macro	0x48d6,a6,2
+ii_0x48e7:		// movem.l reglist,-(a7)
+	mvm_mem_macro	0x48d7,usp,2
+//-------------------------------------------------------------------------------
+ii_0x4cd8:		// movem.l (a0)+,reglist
+	mvm_reg_macro	0x4cd0,0x41e8,2
+ii_0x4cd9:		// movem.l (a1)+,reglist
+	mvm_reg_macro	0x4cd1,0x43e9,2
+ii_0x4cda:		// movem.l (a2)+,reglist
+	mvm_reg_macro	0x4cd2,0x45ea,2
+ii_0x4cdb:		// movem.l (a3)+,reglist
+	mvm_reg_macro	0x4cd3,0x47eb,2
+ii_0x4cdc:		// movem.l (a4)+,reglist
+	mvm_reg_macro	0x4cd4,0x49ec,2
+ii_0x4cdd:		// movem.l (a5)+,reglist
+	mvm_reg_macro	0x4cd5,0x4bed,2
+ii_0x4cde:		// movem.l (a6)+,reglist
+	mvm_reg_macro	0x4cd6,0x4dee,2
+ii_0x4cdf:		// movem.l (a7)+,reglist
+	mvm_reg_macro	0x4cd7,0x4fef,2
+//----------------------------------------------------------------------------
+ii_0x48f9:		// movem.l reg,xxx.L
+#ifdef	halten_movem
+	halt
+#endif
+		move.w		(a0)+,d0
+		move.l		(a0)+,a1
+		movemrm_macro	l
+//---------------------------------------------------------------------------------------------
+ii_0x4cf9:		// movem.l xxx.L,reg
+#ifdef	halten_movem
+	halt
+#endif
+		move.w		(a0)+,d0
+		move.l		(a0)+,a1
+		movemmr_macro	l
+//----------------------------------------------------------------------------
+ii_0x48b9:		// movem.w reg,xxx.L
+#ifdef	halten_movem
+	halt
+#endif
+		move.w		(a0)+,d0
+		move.l		(a0)+,a1
+		movemrm_macro	w
+//---------------------------------------------------------------------------------------------
+ii_0x4cb9:		// movem.w xxx.L,reg
+#ifdef	halten_movem
+	halt
+#endif
+		move.w		(a0)+,d0
+		move.l		(a0)+,a1
+		movemmr_macro	w
+.endm
+//==============================================================
+mvm_mem_macro:.macro
+#ifdef	halten_movem
+	halt
+#endif
+	lea			az_reg_table,a1
+	mvz.b		(a0),d1
+	mvz.b		0(a1,d1)+,d0
+	mvz.b		1(a0),d1
+	mvz.b		0(a1,d1)+,d1
+	add.l		d0,d1
+	lsl.l		#\3,d1				// * anzahl byts pro wert
+	move.l		\2,a1
+	sub.l		d1,a1				// ax-anzahl byts
+	move.l		a1,\2
+	lea			___RAMBAR1,a1
+	move.l		a1,pc_off(a7)
+	move.l		a1,d0
+	addq.l		#1,d0
+   	movec      	d0,RAMBAR1
+	move.w		#\1,(a1)+			// movem.x reg_list,-(a7)
+	move.w		(a0)+,(a1)+			// register list
+	move.w		#0x4ef9,(a1)+		// jmp.l
+	move.l		a0,(a1)				// rücksprungadresse
+   	move.l 		#___RAMBAR1 + 0x81,d0	// instruction
+   	movec      	d0,RAMBAR1
+	movem.l		(a7),d0/d1/a0/a1
+	lea			ii_ss(a7),a7		// stack erhöhen
+	rte
+.endm
+//---------------------------------------------------------------------------------
+mvm_reg_macro:.macro
+#ifdef	halten_movem
+	halt
+#endif
+	lea			az_reg_table,a1
+	mvz.b		(a0),d1
+	mvz.b		0(a1,d1)+,d0
+	mvz.b		1(a0),d1
+	mvz.b		0(a1,d1)+,d1
+	add.l		d0,d1
+	lea			___RAMBAR1,a1
+	move.l		a1,pc_off(a7)
+	move.l		a1,d0
+	addq.l		#1,d0
+   	movec      	d0,RAMBAR1
+	move.w		#\1,(a1)+			// movem.x (ax),reg_list
+	move.w		(a0)+,(a1)+			// register list
+	move.w		#\2,(a1)+			// lea 0(ax),ax
+	lsl.l		#\3,d1				// * anzahl byts pro wert
+	move.w		d1,(a1)+			// offset von lea
+	move.w		#0x4ef9,(a1)+		// jmp.l
+	move.l		a0,(a1)				// rücksprungadresse
+   	move.l 		#___RAMBAR1 + 0x81,d0	// instruction
+   	movec      	d0,RAMBAR1
+	movem.l		(a7),d0/d1/a0/a1
+	lea			ii_ss(a7),a7		// stack erhöhen
+	rte
+.endm
+//---------------------------------------------------------------------------------
+movemrm_macro:.macro				// in d0 register liste, in a1 zieladresse
+#ifdef	halten_movem
+	halt
+#endif
+		tst.b	d0					// datenregister zu verschieben?
+		bne		mrm_dx\@				// ja->
+		lsr.l	#8,d0				// sonst zu addressregister
+		jmp		mmrm_nd7\@			// ->
+mrm_dx\@:
+		lsr.l	#1,d0
+		bcc		mmrm_nd0\@
+.ifc	1,l
+		move.l	d0_off(a7),(a1)+
+.else
+		move.w	d0_off+2(a7),(a1)+
+.endif
+mmrm_nd0\@:
+		lsr.l	#1,d0
+		bcc		mmrm_nd1\@
+.ifc	1,l
+		move.l	d1_off(a7),(a1)+
+.else
+		move.w	d1_off+2(a7),(a1)+
+.endif
+mmrm_nd1\@:
+		lsr.l	#1,d0
+		bcc		mmrm_nd2\@
+		move.\1	d2,(a1)+
+mmrm_nd2\@:
+		lsr.l	#1,d0
+		bcc		mmrm_nd3\@
+		move.\1	d3,(a1)+
+mmrm_nd3\@:
+		lsr.l	#1,d0
+		bcc		mmrm_nd4\@
+		move.\1	d4,(a1)+
+mmrm_nd4\@:
+		lsr.l	#1,d0
+		bcc		mmrm_nd5\@
+		move.\1	d5,(a1)+
+mmrm_nd5\@:
+		lsr.l	#1,d0
+		bcc		mmrm_nd6\@
+		move.l	d6,(a1)+
+mmrm_nd6\@:
+		lsr.l	#1,d0
+		bcc		mmrm_nd7\@
+		move.\1	d7,(a1)+
+mmrm_nd7\@:
+		tst.b	d0					// addressregister zu verschieben?
+		beq		mmrm_na7\@
+		lsr.l	#1,d0
+		bcc		mmrm_na0\@
+.ifc	1,l
+		move.l	a0_off(a7),(a1)+
+.else
+		move.w	a0_off+2(a7),(a1)+
+.endif
+mmrm_na0\@:
+		lsr.l	#1,d0
+		bcc		mmrm_na1\@
+.ifc	1,l
+		move.l	a1_off(a7),(a1)+
+.else
+		move.w	a1_off+2(a7),(a1)+
+.endif
+mmrm_na1\@:
+		lsr.l	#1,d0
+		bcc		mmrm_na2\@
+		move.\1	a2,(a1)+
+mmrm_na2\@:
+		lsr.l	#1,d0
+		bcc		mmrm_na3\@
+		move.\1	a3,(a1)+
+mmrm_na3\@:
+		lsr.l	#1,d0
+		bcc		mmrm_na4\@
+		move.\1	a4,(a1)+
+mmrm_na4\@:
+		lsr.l	#1,d0
+		bcc		mmrm_na5\@
+		move.\1	a5,(a1)+
+mmrm_na5\@:
+		lsr.l	#1,d0
+		bcc		mmrm_na6\@
+		move.\1	a6,(a1)+
+mmrm_na6\@:
+		lsr.l	#1,d0
+		bcc		mmrm_na7\@
+		move.l	a0,d1		// sichern
+		move.l	usp,a0		// ist ja usp
+		move.\1	a0,(a1)+	// nach a0
+		move.l	d1,a0		// pc zurück
+mmrm_na7\@:
+		ii_end
+		.endm
+//---------------------------------------------------------------------------------------------
+movemmr_macro:.macro				// in d0 register liste, in a1 source adr
+#ifdef	halten_movem
+	halt
+#endif
+		tst.b	d0					// datenregister zu verschieben?
+		bne		mmr_dx\@				// ja->
+		lsr.l	#8,d0				// sonst zu addressregister
+		bra		mmmr_nd7\@			// ->
+mmr_dx\@:
+		lsr.l	#1,d0
+		bcc		mmmr_nd0\@
+.ifc	1,l
+		move.l	(a1)+,d0_off(a7)
+.else
+		move.w	(a1)+,d0_off+2(a7)
+.endif
+mmmr_nd0\@:
+		lsr.l	#1,d0
+		bcc		mmmr_nd1\@
+.ifc	1,l
+		move.l	(a1)+,d1_off(a7)
+.else
+		move.w	(a1)+,d1_off+2(a7)
+.endif
+mmmr_nd1\@:
+		lsr.l	#1,d0
+		bcc		mmmr_nd2\@
+		move.\1	(a1)+,d2
+mmmr_nd2\@:
+		lsr.l	#1,d0
+		bcc		mmmr_nd3\@
+		move.\1	(a1)+,d3
+mmmr_nd3\@:
+		lsr.l	#1,d0
+		bcc		mmmr_nd4\@
+		move.\1	(a1)+,d4
+mmmr_nd4\@:
+		lsr.l	#1,d0
+		bcc		mmmr_nd5\@
+		move.\1	(a1)+,d5
+mmmr_nd5\@:
+		lsr.l	#1,d0
+		bcc		mmmr_nd6\@
+		move.\1	(a1)+,d6
+mmmr_nd6\@:
+		lsr.l	#1,d0
+		bcc		mmmr_nd7\@
+		move.\1	(a1)+,d7
+mmmr_nd7\@:
+		tst.b	d0					// addressregister zu verschieben?
+		beq		mmmr_na7\@			// nein->
+		lsr.l	#1,d0
+		bcc		mmmr_na0\@
+.ifc	1,l
+		move.l	(a1)+,a0_off(a7)
+.else
+		move.w	(a1)+,a0_off+2(a7)
+.endif
+mmmr_na0\@:
+		lsr.l	#1,d0
+		bcc		mmmr_na1\@
+.ifc	1,l
+		move.l	(a1)+,a1_off(a7)
+.else
+		move.w	(a1)+,a1_off+2(a7)
+.endif
+mmmr_na1\@:
+		lsr.l	#1,d0
+		bcc		mmmr_na2\@
+		move.\1	(a1)+,a2
+mmmr_na2\@:
+		lsr.l	#1,d0
+		bcc		mmmr_na3\@
+		move.\1	(a1)+,a3
+mmmr_na3\@:
+		lsr.l	#1,d0
+		bcc		mmmr_na4\@
+		move.\1	(a1)+,a4
+mmmr_na4\@:
+		lsr.l	#1,d0
+		bcc		mmmr_na5\@
+		move.\1	(a1)+,a5
+mmmr_na5\@:
+		lsr.l	#1,d0
+		bcc		mmmr_na6\@
+		move.\1	(a1)+,a6
+mmmr_na6\@:
+		lsr.l	#1,d0
+		bcc		mmmr_na7\@
+		move.\1	(a1)+,a1	// nach a0
+		move.l	a1,usp		// war ja usp
+mmmr_na7\@:
+		ii_end
+		.endm		
diff --git a/firebeeV1/sources/ii_movep.h b/firebeeV1/sources/ii_movep.h
new file mode 100644
index 0000000..830fdf7
--- /dev/null
+++ b/firebeeV1/sources/ii_movep.h
@@ -0,0 +1,179 @@
+//--------------------------------------------------------------------
+// movep
+//--------------------------------------------------------------------
+.text
+ii_movep_lset:.macro 
+	ii_lset_opeau	01,0	//movep.w d(a0-7),d0
+	ii_lset_opeau	03,0	//movep.w d(a0-7),d1
+	ii_lset_opeau	05,0	//movep.w d(a0-7),d2
+	ii_lset_opeau	07,0	//movep.w d(a0-7),d3
+	ii_lset_opeau	09,0	//movep.w d(a0-7),d4
+	ii_lset_opeau	0b,0	//movep.w d(a0-7),d5
+	ii_lset_opeau	0d,0	//movep.w d(a0-7),d6
+	ii_lset_opeau	0f,0	//movep.w d(a0-7),d7
+
+	ii_lset_opeau	01,4	//movep.w d0,d(a0-7)
+	ii_lset_opeau	03,4	//movep.w d1,d(a0-7)
+	ii_lset_opeau	05,4	//movep.w d2,d(a0-7)
+	ii_lset_opeau	07,4	//movep.w d3,d(a0-7)
+	ii_lset_opeau	09,4	//movep.w d4,d(a0-7)
+	ii_lset_opeau	0b,4	//movep.w d5,d(a0-7)
+	ii_lset_opeau	0d,4	//movep.w d6,d(a0-7)
+	ii_lset_opeau	0f,4	//movep.w d7,d(a0-7)
+
+	ii_lset_opeau	01,8	//movep.l d(a0-7),d0
+	ii_lset_opeau	03,8	//movep.l d(a0-7),d1
+	ii_lset_opeau	05,8	//movep.l d(a0-7),d2
+	ii_lset_opeau	07,8	//movep.l d(a0-7),d3
+	ii_lset_opeau	09,8	//movep.l d(a0-7),d4
+	ii_lset_opeau	0b,8	//movep.l d(a0-7),d5
+	ii_lset_opeau	0d,8	//movep.l d(a0-7),d6
+	ii_lset_opeau	0f,8	//movep.l d(a0-7),d7
+
+	ii_lset_opeau	01,c	//movep.l d0,d(a0-7)
+	ii_lset_opeau	03,c	//movep.l d1,d(a0-7)
+	ii_lset_opeau	05,c	//movep.l d2,d(a0-7)
+	ii_lset_opeau	07,c	//movep.l d3,d(a0-7)
+	ii_lset_opeau	09,c	//movep.l d4,d(a0-7)
+	ii_lset_opeau	0b,c	//movep.l d5,d(a0-7)
+	ii_lset_opeau	0d,c	//movep.l d6,d(a0-7)
+	ii_lset_opeau	0f,c	//movep.l d7,d(a0-7)
+.endm
+//---------------------------------------------------------------------------------------------
+ii_movep_func:.macro
+//movep.w d(a0-7),d0-7
+	ii_movep		010,d0_off(a7),wad
+	ii_movep		030,d1_off(a7),wad
+	ii_movep		050,d2,wad
+	ii_movep		070,d3,wad
+	ii_movep		090,d4,wad
+	ii_movep		0b0,d5,wad
+	ii_movep		0d0,d6,wad
+	ii_movep		0f0,d7,wad
+//movep.w d0-7,d(a0-7)
+	ii_movep		014,d0_off(a7),wda
+	ii_movep		034,d1_off(a7),wda
+	ii_movep		054,d2,wda
+	ii_movep		074,d3,wda
+	ii_movep		094,d4,wda
+	ii_movep		0b4,d5,wda
+	ii_movep		0d4,d6,wda
+	ii_movep		0f4,d7,wda
+//movep.l d(a0-7),d0-7
+	ii_movep		018,d0_off(a7),lad
+	ii_movep		038,d1_off(a7),lad
+	ii_movep		058,d2,lad
+	ii_movep		078,d3,lad
+	ii_movep		098,d4,lad
+	ii_movep		0b8,d5,lad
+	ii_movep		0d8,d6,lad
+	ii_movep		0f8,d7,lad
+//movep.l d0-7,d(a0-7)
+	ii_movep		01c,d0_off(a7),lda
+	ii_movep		03c,d1_off(a7),lda
+	ii_movep		05c,d2,lda
+	ii_movep		07c,d3,lda
+	ii_movep		09c,d4,lda
+	ii_movep		0bc,d5,lda
+	ii_movep		0dc,d6,lda
+	ii_movep		0fc,d7,lda
+.endm		
+//---------------------------------------------------------------------------------------------
+ii_movep:.macro	//1=code ziffer 1-3 2=register 3=art
+ii_0x\18:
+#ifdef	halten_movep
+	halt
+#endif
+	move.l			a0_off(a7),a1
+	ii_movep\3_up1	\2
+ii_0x\19:
+#ifdef	halten_movep
+	halt
+#endif
+	move.l			a1_off(a7),a1
+	ii_movep\3_up1	\2
+ii_0x\1a:
+#ifdef	halten_movep
+	halt
+#endif
+	move.l			a2,a1
+	ii_movep\3_up1	\2
+ii_0x\1b:
+#ifdef	halten_movep
+	halt
+#endif
+	move.l			a3,a1
+	ii_movep\3_up1	\2
+ii_0x\1c:
+#ifdef	halten_movep
+	halt
+#endif
+	move.l			a4,a1
+	ii_movep\3_up1	\2
+ii_0x\1d:
+#ifdef	halten_movep
+	halt
+#endif
+	move.l			a5,a1
+	ii_movep\3_up1	\2
+ii_0x\1e:
+#ifdef	halten_movep
+	halt
+#endif
+	move.l			a6,a1
+	ii_movep\3_up1	\2
+ii_0x\1f:
+#ifdef	halten_movep
+	halt
+#endif
+	move.l			usp,a1
+	ii_movep\3_up1	\2
+.endm	
+	
+ii_movepwad_up1:.macro
+	mvs.w			(a0)+,d1
+	add.l			d1,a1
+	move.b			(a1),d0
+	lsl.l			#8,d0
+	move.b			2(a1,d1.l),d0
+	move.w			d0,\1
+	ii_end
+.endm
+
+ii_movepwda_up1:.macro
+	mvs.w			(a0)+,d1
+	add.l			d1,a1
+	move.w			\1,d0
+	move.b			d0,2(a1)
+	lsr.l			#8,d0
+	move.b			d0,(a1)
+	ii_end
+.endm
+	
+ii_moveplad_up1:.macro
+	mvs.w			(a0)+,d1
+	add.l			d1,a1
+	move.b			(a1),d0
+	lsl.l			#8,d0
+	move.b			2(a1),d0
+	lsl.l			#8,d0
+	move.b			4(a1),d0
+	lsl.l			#8,d0
+	move.b			6(a1),d0
+	move.l			d0,\1
+	ii_end
+.endm
+
+ii_moveplda_up1:.macro
+	mvs.w			(a0)+,d1
+	add.l			d1,a1
+	move.l			\1,d0
+	move.b			d0,6(a1)
+	lsr.l			#8,d0
+	move.b			d0,4(a1)
+	lsr.l			#8,d0
+	move.b			d0,2(a1)
+	lsr.l			#8,d0
+	move.b			d0,(a1)
+	ii_end
+.endm
diff --git a/firebeeV1/sources/ii_op.h b/firebeeV1/sources/ii_op.h
new file mode 100644
index 0000000..a3fc0cf
--- /dev/null
+++ b/firebeeV1/sources/ii_op.h
@@ -0,0 +1,661 @@
+/*****************************************************************************************/
+// opertionen
+/*****************************************************************************************/
+ii_lset_op:.macro
+//byt
+	ii_lset_opea	\1,0			// dx,ax
+	ii_lset_opea	\1,1			// (ax), (ax)+
+	ii_lset_opea	\1,2			// -(ax),d16(ax)
+	ii_lset_opeag	\1,3			// d8(ax,dy)
+	lea	table+0x\1\238*4,a0
+	move.l	#ii_0x\138,(a0)+		// xxx.w
+	move.l	#ii_0x\139,(a0)+		// xxx.l
+//word
+	ii_lset_opea	\1,4			// dx,ax
+	ii_lset_opea	\1,5			// (ax), (ax)+
+	ii_lset_opea	\1,6			// -(ax),d16(ax)
+	ii_lset_opeag	\1,7			// d8(ax,dy)
+	lea	table+0x\178*4,a0
+	move.l	#ii_0x\178,(a0)+		// xxx.w
+	move.l	#ii_0x\179,(a0)+		// xxx.l
+//long
+	ii_lset_opea	\1,8			// dx,ax
+	ii_lset_opea	\1,9			// (ax), (ax)+
+	ii_lset_opea	\1,a			// -(ax),d16(ax)
+	ii_lset_opeag	\1,b			// d8(ax,dy)
+	lea	table+0x\1b8*4,a0
+	move.l	#ii_0x\1b8,(a0)+		// xxx.w
+	move.l	#ii_0x\1b9,(a0)+		// xxx.l
+	.endm
+
+ii_lset_opeag:.macro				// 0x1120-0x1127 
+	lea	table+0x\1\20*4,a0
+	move.l	#ii_0x\1\20,(a0)+
+	move.l	#ii_0x\1\21,(a0)+
+	move.l	#ii_0x\1\22,(a0)+
+	move.l	#ii_0x\1\23,(a0)+
+	move.l	#ii_0x\1\24,(a0)+
+	move.l	#ii_0x\1\25,(a0)+
+	move.l	#ii_0x\1\26,(a0)+
+	move.l	#ii_0x\1\27,(a0)+
+	.endm;
+	
+ii_lset_opeau:.macro				// 0x1128-0x112f 
+	lea	table+0x\1\28*4,a0
+	move.l	#ii_0x\1\28,(a0)+
+	move.l	#ii_0x\1\29,(a0)+
+	move.l	#ii_0x\1\2a,(a0)+
+	move.l	#ii_0x\1\2b,(a0)+
+	move.l	#ii_0x\1\2c,(a0)+
+	move.l	#ii_0x\1\2d,(a0)+
+	move.l	#ii_0x\1\2e,(a0)+
+	move.l	#ii_0x\1\2f,(a0)+
+	.endm;
+
+ii_lset_opea:.macro
+	ii_lset_opeag	\1,\2
+	ii_lset_opeau	\1,\2
+	.endm
+/******************************************************/
+ii_op:.macro	// 1=code 2=operation 3 = normal oder immediat/quick
+// byt
+	opdx	\1,\2,b,0,\3		// dx,ax
+	opia	\1,\2,b,1,\3		// (ax),(ax)+
+	opdia	\1,\2,b,2,\3		// -(ax),d16(ax)
+	opd8a	\1,\2,b,3,\3		// d8(ax),xxx
+// word
+	opdx	\1,\2,w,4,\3		// dx,ax
+	opia	\1,\2,w,5,\3		// (ax),(ax)+
+	opdia	\1,\2,w,6,\3		// -(ax),d16(ax)
+	opd8a	\1,\2,w,7,\3		// d8(ax),xxx
+// long
+	opdx	\1,\2,l,8,\3		// dx,ax
+	opia	\1,\2,l,9,\3		// (ax),(ax)+
+	opdia	\1,\2,l,a,\3		// -(ax),d16(ax)
+	opd8a	\1,\2,l,b,\3		// d8(ax),xxx
+	.endm
+/******************************************************/
+// byt word long
+/******************************************************/
+opdx:	.macro	//register: \1=code \2 = operation \3 = size \4=size and adressierungsart 5 = immediate oder normal
+ii_0x\1\40:
+	.ifc	\3,b
+		op\5smd	\2,d0_off+3(a7),d0_off+3(a7),\3
+	.else
+		.ifc		\3,w
+			op\5smd	\2,d0_off+2(a7),d0_off+2(a7),\3
+		.else
+			op\5smd	\2,d0_off(a7),d0_off(a7),\3
+		.endif
+	.endif
+ii_0x\1\41:
+	.ifc	\3,b
+		op\5smd	\2,d1_off+3(a7),d1_off+3(a7),\3
+	.else
+		.ifc		\3,w
+			op\5smd	\2,d1_off+2(a7),d1_off+2(a7),\3
+		.else
+			op\5smd	\2,d1_off(a7),d1_off(a7),\3
+		.endif
+.endif
+ii_0x\1\42:
+	op\5smd	\2,d2,d2,\3
+ii_0x\1\43:
+	op\5smd	\2,d3,d3,\3
+ii_0x\1\44:
+	op\5smd	\2,d4,d4,\3
+ii_0x\1\45:
+	op\5smd	\2,d5,d5,\3
+ii_0x\1\46:
+	op\5smd	\2,d6,d6,\3
+ii_0x\1\47:
+	op\5smd	\2,d7,d7,\3
+//ax
+ii_0x\1\48:
+	opa\5smd	\2,a0_off(a7),a0_off(a7),\3
+ii_0x\1\49:
+	opa\5smd	\2,a1_off(a7),a1_off(a7),\3
+ii_0x\1\4a:
+	opa\5smd	\2,a2,a2,\3
+ii_0x\1\4b:
+	opa\5smd	\2,a3,a3,\3
+ii_0x\1\4c:
+	opa\5smd	\2,a4,a4,\3
+ii_0x\1\4d:
+	opa\5smd	\2,a5,a5,\3
+ii_0x\1\4e:
+	opa\5smd	\2,a6,a6,\3
+ii_0x\1\4f:
+	opa\5smd	\2,usp,usp,\3
+.endm;
+//-----------------------------------------------
+opia:	.macro	// (ax) \1=code \2 = operation \3 = size \4=size and adressierungsart 5 = immediate oder normal
+//(ax)
+ii_0x\1\40:
+	op\5sia	\2,a0_off(a7),(a1),(a1),\3
+ii_0x\1\41:
+	op\5sia	\2,a1_off(a7),(a1),(a1),\3
+ii_0x\1\42:
+	op\5smd	\2,(a2),(a2),\3
+ii_0x\1\43:
+	op\5smd	\2,(a3),(a3),\3
+ii_0x\1\44:
+	op\5smd	\2,(a4),(a4),\3
+ii_0x\1\45:
+	op\5smd	\2,(a5),(a5),\3
+ii_0x\1\46:
+	op\5smd	\2,(a6),(a6),\3
+ii_0x\1\47:
+	op\5sia	\2,usp,(a1),(a1),\3
+//(ax)+
+ii_0x\1\48:
+	op\5sia	\2,a0_off(a7),(a1),(a1)+,\3
+ii_0x\1\49:
+	op\5sia	\2,a1_off(a7),(a1),(a1)+,\3
+ii_0x\1\4a:
+	op\5smd	\2,(a2),(a2)+,\3
+ii_0x\1\4b:
+	op\5smd	\2,(a3),(a3)+,\3
+ii_0x\1\4c:
+	op\5smd	\2,(a4),(a4)+,\3
+ii_0x\1\4d:
+	op\5smd	\2,(a5),(a5)+,\3
+ii_0x\1\4e:
+	op\5smd	\2,(a6),(a6)+,\3
+ii_0x\1\4f:
+	op\5sia	\2,usp,(a1),(a1)+,\3
+.endm;
+//-----------------------------------------------
+opdia:	.macro	// -(ax) \1=code \2 = operation \3 = size \4 size and adressierungsart 5 = immediate oder normal
+ii_0x\1\40:
+	op\5sia	\2,a0_off(a7),-(a1),(a1),\3
+ii_0x\1\41:
+	op\5sia	\2,a1_off(a7),-(a1),(a1),\3
+ii_0x\1\42:
+	op\5smd	\2,-(a2),(a2),\3
+ii_0x\1\43:
+	op\5smd	\2,-(a3),(a3),\3
+ii_0x\1\44:
+	op\5smd	\2,-(a4),(a4),\3
+ii_0x\1\45:
+	op\5smd	\2,-(a5),(a5),\3
+ii_0x\1\46:
+	op\5smd	\2,-(a6),(a6),\3
+ii_0x\1\47:
+	op\5sia	\2,usp,-(a1),(a1),\3
+
+ii_0x\1\48:
+	op\5sd16a	\2,a0_off(a7),\3
+ii_0x\1\49:
+	op\5sd16a	\2,a1_off(a7),\3
+ii_0x\1\4a:
+	op\5sd16a	\2,a2,\3
+ii_0x\1\4b:
+	op\5sd16a	\2,a3,\3
+ii_0x\1\4c:
+	op\5sd16a	\2,a4,\3
+ii_0x\1\4d:
+	op\5sd16a	\2,a5,\3
+ii_0x\1\4e:
+	op\5sd16a	\2,a6,\3
+ii_0x\1\4f:
+	op\5sd16a	\2,usp,\3
+.endm;
+//-----------------------------------------------
+opd8a:	.macro	// d8(ax,dy) \1=code \2 = operation \3 = size \4=size and adressierungsart 5 = immediate oder normal
+ii_0x\1\40:
+	op\5sd8a	\2,a0_off(a7),\3
+ii_0x\1\41:
+	op\5sd8a	\2,a1_off(a7),\3
+ii_0x\1\42:
+	op\5sd8a	\2,a2,\3
+ii_0x\1\43:
+	op\5sd8a	\2,a3,\3
+ii_0x\1\44:
+	op\5sd8a	\2,a4,\3
+ii_0x\1\45:
+	op\5sd8a	\2,a5,\3
+ii_0x\1\46:
+	op\5sd8a	\2,a6,\3
+ii_0x\1\47:
+	op\5sd8a	\2,usp,\3
+
+ii_0x\1\48:
+	op\5sxx		\2,\3,w
+ii_0x\1\49:
+	op\5sxx		\2,\3,l
+.endm;
+//-----------------------------------------------
+opnsmd:.macro		// direct dx: 1=operation	2=ea src 3=ea dest 4=size
+#ifdef	halten_op
+	halt
+#endif
+.ifc	\4,l
+	move.l	\2,d1
+.else
+	mvs.\4	\2,d1
+.endif
+	.ifc	\1,negx
+		move.b		sr_off+1(a7),d1			//ccr holen
+		move		d1,ccr					//setzen
+	.endif		
+	\1	d1
+	set_cc0
+	move.\4		d1,\3
+	ii_end
+	.endm;
+
+opansmd:.macro		// direct ax: 1=operation	2=ea src 3=ea dest 4=size
+#ifdef	halten_op
+	halt
+#endif
+
+.ifc	\2,usp
+		move.l	usp,a1
+		move.l	a1,d1
+.else
+		move.l		\2,d1
+.endif
+	\1	d1
+.ifc	\3,usp
+	move.l		d1,a1
+	move.l		a1,usp
+.else
+	move.l		d1,\3
+.endif
+	ii_end
+.endm;
+
+opnsia:.macro		// indirect: 1=operation 2=adress register 3= src 4=dest 5=size
+#ifdef	halten_op
+	halt
+#endif
+	move.l	\2,a1
+.ifc	\5,l
+	move.l	\3,d1
+.else
+	mvs.\5	\3,d1
+.endif
+	.ifc	\1,negx
+		move.b		sr_off+1(a7),d1			//ccr holen
+		move		d1,ccr					//setzen
+	.endif		
+	\1	d1
+	set_cc0
+	move.\5	d1,\4
+	ii_end
+	.endm;
+
+opnsd16a:.macro		// indirect: 1=operation 2=adress register 3=size
+#ifdef	halten_op
+	halt
+#endif
+	move.l	\2,a1
+	mvs.w	(a0)+,d1
+	add.l	d1,a1
+.ifc	\3,l
+	move.l	(a1),d1
+.else
+	mvs.\3	(a1),d1
+.endif
+	.ifc	\1,negx
+		move.b		sr_off+1(a7),d1			//ccr holen
+		move		d1,ccr					//setzen
+	.endif		
+	\1	d1
+	set_cc0
+	move.\3	d1,(a1)
+	ii_end
+	.endm;
+
+opnsd8a:.macro		// indirect: 1=operation 2=adress register 3=size
+#ifdef	halten_op
+	halt
+#endif
+	move.l	\2,a1
+	jsr		ewf
+.ifc	\3,l
+	move.l	(a1),d1
+.else
+	mvs.\3	(a1),d1
+.endif
+	.ifc	\1,negx
+		move.b		sr_off+1(a7),d1			//ccr holen
+		move		d1,ccr					//setzen
+	.endif		
+	\1	d1
+	set_cc0
+	move.\3	d1,(a1)
+	ii_end
+	.endm;
+
+opnsxx:.macro		// indirect: 1=operation 2=size 3=size adresse
+#ifdef	halten_op
+	halt
+#endif
+
+.ifc	\2,l
+	move.l	(a1),d1
+.else
+	mvs.\2	(a1),d1
+.endif
+	move.\3	(a0)+,a1
+	.ifc	\1,negx
+		move.b		sr_off+1(a7),d1			//ccr holen
+		move		d1,ccr					//setzen
+	.endif		
+	\1	d1
+	set_cc0
+	move.\2	d1,(a1)
+	ii_end
+	.endm;
+//*******************************************************************************3
+opismd:.macro		// immediate dx: 1=opieration	2=ea src 3=ea dest 4=size
+#ifdef	halten_op
+	halt
+#endif
+
+.ifc	\4,l
+	move.l	(a0)+,d0
+.else
+	.ifc	\4,w
+		mvs.w	(a0)+,d0
+	.else
+		move.w	(a0)+,d0
+		extb.l	d0
+	.endif
+.endif
+.ifc	\4,l
+	move.l	\2,d1
+.else
+	mvs.\4	\2,d1
+.endif
+	\1	d0,d1
+	set_cc0
+.ifnc	\1,cmp.l
+	move.\4		d1,\3
+.endif
+	ii_end
+.endm;
+
+opaismd:.macro		// immediate ax: 1=opieration	2=ea src 3=ea dest 4=size
+#ifdef	halten_op
+	halt
+#endif
+
+.ifc	\4,l
+	move.l	(a0)+,d0
+.else
+	.ifc	\4,w
+		mvs.w	(a0)+,d0
+	.else
+		move.w	(a0)+,d0
+		extb.l	d0
+	.endif
+.endif
+.ifc	\2,usp
+		move.l	usp,a1
+		move.l	a1,d1
+.else
+		move.l		\2,d1
+.endif
+	\1	d0,d1
+.ifnc	\1,cmp.l
+.ifc	\3,usp
+	move.l		d1,a1
+	move.l		a1,usp
+.else
+	move.l		d1,\3
+.endif
+.endif
+	ii_end
+.endm;
+
+opisia:.macro		// indirect: 1=opieration 2=adress register 3= src 4=dest 5=size
+#ifdef	halten_op
+	halt
+#endif
+
+.ifc	\5,l
+	move.l	(a0)+,d0
+.else
+	.ifc	\5,w
+		mvs.w	(a0)+,d0
+	.else
+		move.w	(a0)+,d0
+		extb.l	d0
+	.endif
+.endif
+	move.l	\2,a1
+.ifc	\5,l
+	move.l	\3,d1
+.else
+	mvs.\5	\3,d1
+.endif
+	\1	d0,d1
+	set_cc0
+.ifnc	\1,cmp.l
+	move.\5	d1,\4
+.endif
+	ii_end
+.endm;
+
+opisd16a:.macro		// indirect: 1=opieration 2=adress register 3=size
+#ifdef	halten_op
+	halt
+#endif
+
+.ifc	\3,l
+	move.l	(a0)+,d0
+.else
+	.ifc	\3,w
+		mvs.w	(a0)+,d0
+	.else
+		move.w	(a0)+,d0
+		extb.l	d0
+	.endif
+.endif
+	move.l	\2,a1
+	mvs.w	(a0)+,d1
+	add.l	d1,a1
+.ifc	\3,l
+	move.l	(a1),d1
+.else
+	mvs.\3	(a1),d1
+.endif
+	\1	d0,d1
+	set_cc0
+.ifnc	\1,cmp.l
+	move.\3	d1,(a1)
+.endif
+	ii_end
+	.endm;
+
+opisd8a:.macro		// indirect: 1=opieration 2=adress register 3=size
+#ifdef	halten_op
+	halt
+#endif
+
+.ifc	\3,l
+	move.l	(a0)+,d0
+.else
+	.ifc	\3,w
+		mvs.w	(a0)+,d0
+	.else
+		move.w	(a0)+,d0
+		extb.l	d0
+	.endif
+.endif
+	move.l	d0,_d0_save
+	move.l	\2,a1
+	jsr		ewf
+	move.l	_d0_save,d0
+.ifc	\3,l
+	move.l	(a1),d1
+.else
+	mvs.\3	(a1),d1
+.endif
+	\1	d0,d1
+	set_cc0
+.ifnc	\1,cmp.l
+	move.\3	d1,(a1)
+.endif
+	ii_end
+	.endm;
+
+opisxx:.macro		// immediate: 1=opieration 2=size 3=size adresse
+.ifc	\2,l
+	move.l	(a0)+,d0
+.else
+	.ifc	\2,w
+		mvs.w	(a0)+,d0
+	.else
+		move.w	(a0)+,d0
+		extb.l	d0
+	.endif
+.endif
+	move.\3	(a0)+,a1
+.ifc	\2,l
+	move.l	(a1),d1
+.else
+	mvs.\2	(a1),d1
+.endif
+	\1	d0,d1
+	set_cc0
+.ifnc	\1,cmp.l
+	move.\2	d1,(a1)
+.endif
+	ii_end
+	.endm;
+//*******************************************************************************3
+opqsmd:.macro		// quick: 1=opieration	2=ea src 3=ea dest 4=size
+.ifc	\4,l
+	move.l	\2,d1
+.else
+	mvs.\4	\2,d1
+.endif
+.ifc	\1,eor.l d0
+	move.l	d0_off(a7),d0
+.endif
+.ifc	\1,eor.l d1
+	move.l	d1_off(a7),d1
+.endif
+	\1	,d1
+	set_cc0
+	move.\4		d1,\3
+	ii_end
+	.endm;
+
+opaqsmd:.macro		// quick: 1=opieration	2=ea src 3=ea dest 4=size
+.ifc	\2,usp
+		move.l	usp,a1
+		move.l	a1,d1
+.else
+		move.l		\2,d1
+.endif
+	\1	,d1
+.ifc	\3,usp
+	move.l		d1,a1
+	move.l		a1,usp
+.else
+	move.l		d1,\3
+.endif
+	ii_end
+	.endm;
+
+opqsia:.macro		// indirect: 1=opieration 2=adress register 3= src 4=dest 5=size
+#ifdef	halten_op
+	halt
+#endif
+
+	move.l	\2,a1
+.ifc	\5,l
+	move.l	\3,d1
+.else
+	mvs.\5	\3,d1
+.endif
+.ifc	\1,eor.l d0
+	move.l	d0_off(a7),d0
+.endif
+.ifc	\1,eor.l d1
+	move.l	d1_off(a7),d1
+.endif
+	\1	,d1
+	set_cc0
+	move.\5	d1,\4
+	ii_end
+	.endm;
+
+opqsd16a:.macro		// indirect: 1=opieration 2=adress register 3=size
+#ifdef	halten_op
+	halt
+#endif
+
+	move.l	\2,a1
+	mvs.w	(a0)+,d1
+	add.l	d1,a1
+.ifc	\3,l
+	move.l	(a1),d1
+.else
+	mvs.\3	(a1),d1
+.endif
+.ifc	\1,eor.l d0
+	move.l	d0_off(a7),d0
+.endif
+.ifc	\1,eor.l d1
+	move.l	d1_off(a7),d1
+.endif
+	\1	,d1
+	set_cc0
+	move.\3	d1,(a1)
+	ii_end
+	.endm;
+
+opqsd8a:.macro		// indirect: 1=opieration 2=adress register 3=size
+#ifdef	halten_op
+	halt
+#endif
+
+	move.l	d0,_d0_save
+	move.l	\2,a1
+	jsr		ewf
+	move.l	_d0_save,d0
+.ifc	\3,l
+	move.l	(a1),d1
+.else
+	mvs.\3	(a1),d1
+.endif
+.ifc	\1,eor.l d0
+	move.l	d0_off(a7),d0
+.endif
+.ifc	\1,eor.l d1
+	move.l	d1_off(a7),d1
+.endif
+	\1	,d1
+	set_cc0
+	move.\3	d1,(a1)
+	ii_end
+	.endm;
+
+opqsxx:.macro		// quick: 1=opieration 2=size 3=size adresse
+#ifdef	halten_op
+	halt
+#endif
+
+	move.\3	(a0)+,a1
+.ifc	\2,l
+	move.l	(a1),d1
+.else
+	mvs.\2	(a1),d1
+.endif
+.ifc	\1,eor.l d0
+	move.l	d0_off(a7),d0
+.endif
+.ifc	\1,eor.l d1
+	move.l	d1_off(a7),d1
+.endif
+	\1	,d1
+	set_cc0
+	move.\2	d1,(a1)
+	ii_end
+	.endm;
diff --git a/firebeeV1/sources/ii_opc.h b/firebeeV1/sources/ii_opc.h
new file mode 100644
index 0000000..8b887ce
--- /dev/null
+++ b/firebeeV1/sources/ii_opc.h
@@ -0,0 +1,263 @@
+/*****************************************************************************************/
+// functionen macros: fehlende adressierungsarte (MCF nur Dx support) ohne ax
+// zusammen mit op.h
+/*****************************************************************************************/
+ii_lset_opc:.macro
+	ii_lset_opeag	\1,c			// dx,ax
+	ii_lset_opea	\1,d			// (ax), (ax)+
+	ii_lset_opea	\1,e			// -(ax),d16(ax)
+	ii_lset_opeag	\1,f			// d8(ax,dy)
+	lea	table+0x\1b8*4,a0
+	move.l	#ii_0x\1b8,(a0)+		// xxx.w
+	move.l	#ii_0x\1b9,(a0)+		// xxx.l
+	.endm
+
+/******************************************************/
+ii_opc:.macro	// 1=code 2=operation 3 = normal oder immediat
+	opcdx	\1,\2,l,c,\3		// dx,ax
+	opia	\1,\2,l,d,\3		// (ax),(ax)+
+	opdia	\1,\2,l,e,\3		// -(ax),d16(ax)
+	opd8a	\1,\2,l,f,\3		// d8(ax),xxx
+	.endm
+//*******************************************************************************3
+/******************************************************/
+// byt word long
+/******************************************************/
+opcdx:	.macro	//register: \1=code \2 = operation \3 = size \4=size and adressierungsart 5 = immediate oder normal
+ii_0x\1\40:
+#ifdef	halten_opc
+	halt
+#endif
+	.ifc	\3,b
+		op\5smd	\2,d0_off+3(a7),d0_off+3(a7),\3
+	.else
+		.ifc		\3,w
+			op\5smd	\2,d0_off+2(a7),d0_off+2(a7),\3
+		.else
+			op\5smd	\2,d0_off(a7),d0_off(a7),\3
+		.endif
+	.endif
+ii_0x\1\41:
+	.ifc	\3,b
+		op\5smd	\2,d1_off+3(a7),d1_off+3(a7),\3
+	.else
+		.ifc		\3,w
+			op\5smd	\2,d1_off+2(a7),d1_off+2(a7),\3
+		.else
+			op\5smd	\2,d1_off(a7),d1_off(a7),\3
+		.endif
+.endif
+ii_0x\1\42:
+	op\5smd	\2,d2,d2,\3
+ii_0x\1\43:
+	op\5smd	\2,d3,d3,\3
+ii_0x\1\44:
+	op\5smd	\2,d4,d4,\3
+ii_0x\1\45:
+	op\5smd	\2,d5,d5,\3
+ii_0x\1\46:
+	op\5smd	\2,d6,d6,\3
+ii_0x\1\47:
+	op\5smd	\2,d7,d7,\3
+.endm
+//-----------------------------------------------------
+opcsmd:.macro		// dx: 1=opieration	2=ea src 3=ea dest 4=size
+#ifdef	halten_opc
+	halt
+#endif
+
+.ifc	\4,l
+	move.l	(a0)+,d0
+.else
+	.ifc	\4,w
+		mvs.w	(a0)+,d0
+	.else
+		move.w	(a0)+,d0
+		extb.l	d0
+	.endif
+.endif
+.ifc	\4,l
+	move.l	\2,d1
+.else
+	mvs.\4	\2,d1
+.endif
+.ifc	\1,eor.l d0
+	move.l	d0_off(a7),d1
+.endif
+.ifc	\1,eor.l d1
+	move.l	d1_off(a7),d1
+.endif
+	\1	d1
+	set_cc0
+	move.\4		d1,\3
+	ii_end
+	.endm;
+
+opacsmd:.macro		// ax: 1=opieration	2=ea src 3=ea dest 4=size
+#ifdef	halten_opc
+	halt
+#endif
+
+.ifc	\4,l
+	move.l	(a0)+,d0
+.else
+	.ifc	\4,w
+		mvs.w	(a0)+,d0
+	.else
+		move.w	(a0)+,d0
+		extb.l	d0
+	.endif
+.endif
+.ifc	\2,usp
+		move.l	usp,a1
+		move.l	a1,d1
+.else
+		move.l		\2,d1
+.endif
+	\1	d1
+	set_cc0
+.ifc	\3,usp
+	move.l		d1,a1
+	move.l		a1,usp
+.else
+	move.l		d1,\3
+.endif
+	ii_end
+	.endm;
+
+opcsia:.macro		// (ax) (ax)+ -(ax): 1=opieration 2=adress register 3= src 4=dest 5=size
+#ifdef	halten_opc
+	halt
+#endif
+
+.ifc	\4,l
+	move.l	(a0)+,d0
+.else
+	.ifc	\4,w
+		mvs.w	(a0)+,d0
+	.else
+		move.w	(a0)+,d0
+		extb.l	d0
+	.endif
+.endif
+	move.l	\2,a1
+.ifc	\5,l
+	move.l	\3,d1
+.else
+	mvs.\5	\3,d1
+.endif
+.ifc	\1,eor.l d0
+	move.l	d0_off(a7),d1
+.endif
+.ifc	\1,eor.l d1
+	move.l	d1_off(a7),d1
+.endif
+	\1	d1
+	set_cc0
+	move.\5	d1,\4
+	ii_end
+	.endm;
+
+opcsd16a:.macro		// d16(ax): 1=opieration 2=adress register 3=size
+#ifdef	halten_opc
+	halt
+#endif
+
+.ifc	\4,l
+	move.l	(a0)+,d0
+.else
+	.ifc	\4,w
+		mvs.w	(a0)+,d0
+	.else
+		move.w	(a0)+,d0
+		extb.l	d0
+	.endif
+.endif
+	move.l	\2,a1
+	mvs.w	(a0)+,d1
+	add.l	d1,a1
+.ifc	\3,l
+	move.l	(a1),d1
+.else
+	mvs.\3	(a1),d1
+.endif
+.ifc	\1,eor.l d0
+	move.l	d0_off(a7),d1
+.endif
+.ifc	\1,eor.l d1
+	move.l	d1_off(a7),d1
+.endif
+	\1	d1
+	set_cc0
+	move.\3	d1,(a1)
+	ii_end
+	.endm;
+
+opcsd8a:.macro		// indirect: 1=opieration 2=adress register 3=size
+#ifdef	halten_opc
+	halt
+#endif
+
+.ifc	\4,l
+	move.l	(a0)+,d0
+.else
+	.ifc	\4,w
+		mvs.w	(a0)+,d0
+	.else
+		move.w	(a0)+,d0
+		extb.l	d0
+	.endif
+.endif
+	move.l	d0,_d0_save
+	move.l	\2,a1
+	jsr		ewf
+	move.l	_d0_save,d0
+.ifc	\3,l
+	move.l	(a1),d1
+.else
+	mvs.\3	(a1),d1
+.endif
+.ifc	\1,eor.l d0
+	move.l	d0_off(a7),d1
+.endif
+.ifc	\1,eor.l d1
+	move.l	d1_off(a7),d1
+.endif
+	\1	d1
+	set_cc0
+	move.\3	d1,(a1)
+	ii_end
+	.endm;
+
+opcsxx:.macro		// indirect: 1=opieration 2=size 3=size adresse
+#ifdef	halten_opc
+	halt
+#endif
+
+.ifc	\2,l
+	move.l	(a0)+,d0
+.else
+	.ifc	\2,w
+		mvs.w	(a0)+,d0
+	.else
+		move.w	(a0)+,d0
+		extb.l	d0
+	.endif
+.endif
+	move.\3	(a0)+,a1
+.ifc	\2,l
+	move.l	(a1),d1
+.else
+	mvs.\2	(a1),d1
+.endif
+.ifc	\1,eor.l d0
+	move.l	d0_off(a7),d1
+.endif
+.ifc	\1,eor.l d1
+	move.l	d1_off(a7),d1
+.endif
+	\1	d1
+	set_cc0
+	move.\2	d1,(a1)
+	ii_end
+	.endm;
diff --git a/firebeeV1/sources/ii_or.h b/firebeeV1/sources/ii_or.h
new file mode 100644
index 0000000..dfe4450
--- /dev/null
+++ b/firebeeV1/sources/ii_or.h
@@ -0,0 +1,442 @@
+//--------------------------------------------------------------------
+// or
+//--------------------------------------------------------------------
+/*****************************************************************************************/
+//--------------------------------------------------------------------
+// byt
+//--------------------------------------------------------------------
+//--------------------------------------------------------------------
+// or.b	#im,dx
+//--------------------------------------------------------------------
+orbir_macro:.macro
+#ifdef	halten_or
+	halt
+#endif
+	move.w		(a0)+,d0
+	extb.l		d0
+	mvs.b		\2,d1
+	or.l		d0,d1
+	set_cc0
+	move.b		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // or	ea,dx
+//--------------------------------------------------------------------
+ordd:.macro
+#ifdef	halten_or
+	halt
+#endif
+	mvs.\3		\1,d0
+	mvs.\3		\2,d1
+	or.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // or	ea(l)->dy(w),dx z.B. für USP
+//--------------------------------------------------------------------
+orddd:.macro
+#ifdef	halten_or
+	halt
+#endif
+	move.l		\1,a1
+	mvs.\3		a1,d0
+	mvs.\3		\2,d1
+	or.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // or	(ea)->dy,dx
+//--------------------------------------------------------------------
+ordda:.macro
+#ifdef	halten_or
+	halt
+#endif
+	move.l		\1,a1
+	mvs.\3		(a1),d0
+	mvs.\3		\2,d1
+	or.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // or	ea->ay,(ay)+,dx
+//--------------------------------------------------------------------
+orddai:.macro
+#ifdef	halten_or
+	halt
+#endif
+	move.l		\1,a1
+	mvs.\3		(a1)+,d0
+	move.l		a1,\1
+	mvs.\3		\2,d1
+	or.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // or	ea->ay,-(ay),dx
+//--------------------------------------------------------------------
+orddad:.macro
+#ifdef	halten_or
+	halt
+#endif
+	move.l		\1,a1
+	mvs.\3		-(a1),d0
+	move.l		a1,\1
+	mvs.\3		\2,d1
+	or.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // or	d16(ay),dx
+//--------------------------------------------------------------------
+ord16ad:.macro
+#ifdef	halten_or
+	halt
+#endif
+	move.l		\1,a1
+	mvs.w		(a0)+,d0
+	add.l		d0,a1
+	mvs.\3		(a1),d0		
+	mvs.\3		\2,d1
+	or.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // or	d8(ay,dy),dx
+//--------------------------------------------------------------------
+ord8ad:.macro
+#ifdef	halten_or
+	halt
+#endif
+	move.l		\1,a1
+	jsr			ewf
+.ifc	\3,l
+	move.l		(a1),d0
+	move.l		\2,d1
+.else
+	mvs.\3		(a1),d0
+	mvs.\3		\2,d1
+.endif
+	or.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // or	xxx.w,dx
+//--------------------------------------------------------------------
+orxwd:.macro
+#ifdef	halten_or
+	halt
+#endif
+	move.w		(a0)+,a1
+	mvs.\3		(a1),d0
+	mvs.\3		\2,d1
+	or.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // or	xxx.l,dx
+//--------------------------------------------------------------------
+orxld:.macro
+#ifdef	halten_or
+	halt
+#endif
+	move.l		(a0)+,a1
+	mvs.\3		(a1),d0
+	mvs.\3		\2,d1
+	or.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // or	d16(pc),dx
+//--------------------------------------------------------------------
+ord16pcd:.macro
+	halt
+	move.l		a0,a1
+	mvs.w		(a0)+,d0
+	add.l		d0,a1
+	mvs.\3		(a1),d0
+	mvs.\3		\2,d1
+	or.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // or	d8(pc,dy),dx
+//--------------------------------------------------------------------
+ord8pcd:.macro
+#ifdef	halten_or
+	halt
+#endif
+	move.l		a0,a1
+	jsr			ewf
+.ifc	\3,l
+	move.l		(a1),d0
+	move.l		\2,d1
+.else
+	mvs.\3		(a1),d0
+	mvs.\3		\2,d1
+.endif
+	or.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+//  or dy,ea
+//--------------------------------------------------------------------
+//--------------------------------------------------------------------
+// // or	(ea)->dy,dx
+//--------------------------------------------------------------------
+oreda:.macro
+#ifdef	halten_or
+	halt
+#endif
+	mvs.\3		\1,d0
+	move.l		\2,a1
+	mvs.\3		(a1),d1
+	or.l		d0,d1
+	set_cc0
+	move.\3		d1,(a1)
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // or	dx,ea->ay,(ay)+
+//--------------------------------------------------------------------
+oredai:.macro
+#ifdef	halten_or
+	halt
+#endif
+	mvs.\3		\1,d0
+	move.l		\2,a1
+	mvs.\3		(a1),d1
+	or.l		d0,d1
+	set_cc0
+	move.\3		d1,(a1)+
+	move.l		a1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // or	dx,ea->ay,(ay)+
+//--------------------------------------------------------------------
+oredaid:.macro
+#ifdef	halten_or
+	halt
+#endif
+	mvs.\3		\1,d0
+	mvs.\3		\2,d1
+	or.l		d0,d1
+	set_cc0
+	move.\3		d1,\2+
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // or	dx,ea->ay,-(ay)
+//--------------------------------------------------------------------
+oredad:.macro
+#ifdef	halten_or
+	halt
+#endif
+	mvs.\3		\1,d0
+	move.l		\2,a1
+	mvs.\3		-(a1),d1
+	move.l		a1,\2
+	or.l		d0,d1
+	set_cc0
+	move.\3		d1,(a1)
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // or	dx,ea->ay,-(ay)
+//--------------------------------------------------------------------
+oredadd:.macro
+#ifdef	halten_or
+	halt
+#endif
+	mvs.\3		\1,d0
+	mvs.\3		-\2,d1
+	or.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // or	dx,d16(ay)
+//--------------------------------------------------------------------
+ore16ad:.macro
+#ifdef	halten_or
+	halt
+#endif
+	mvs.\3		\1,d0
+	move.l		\2,a1
+	mvs.w		(a0)+,d1
+	add.l		d1,a1
+	mvs.\3		(a1),d1		
+	or.l		d0,d1
+	set_cc0
+	move.\3		d1,(a1)
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // or.w	dx,d8(ay,dy)
+//--------------------------------------------------------------------
+ore8ad:.macro
+#ifdef	halten_or
+	halt
+#endif
+	move.l		\2,a1
+	jsr			ewf
+.ifc	\3,l
+	move.l		(a1),d1
+	move.l		\1,d0
+.else
+	mvs.\3		(a1),d1
+	mvs.\3		\1,d0
+.endif
+	or.l		d0,d1
+	set_cc0
+	move.\3		d1,(a1)
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // or	dx,xxx.w
+//--------------------------------------------------------------------
+orxwe:.macro
+#ifdef	halten_or
+	halt
+#endif
+	mvs.\3		\1,d0
+	move.w		(a0)+,a1
+	mvs.\3		(a1),d1
+	or.l		d0,d1
+	set_cc0
+	move.\3		d1,(a1)
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // or	dx,xxx.l
+//--------------------------------------------------------------------
+orxle:.macro
+#ifdef	halten_or
+	halt
+#endif
+	mvs.\3		\1,d0
+	move.l		(a0)+,a1
+	mvs.\3		(a1),d1
+	or.l		d0,d1
+	set_cc0
+	move.\3		d1,(a1)
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // ora.w	ea,ax
+//--------------------------------------------------------------------
+oraw:.macro
+	jmp			ii_error
+	.endm;
+//--------------------------------------------------------------------
+// or.w ea,usp
+//--------------------------------------------------------------------
+orawa7:.macro
+	jmp			ii_error
+	.endm;
+//--------------------------------------------------------------------
+// // ora.w	usp?,ax
+//--------------------------------------------------------------------
+orawu:.macro
+	jmp			ii_error
+	.endm;
+//--------------------------------------------------------------------
+// // ora.w	usp?,usp
+//--------------------------------------------------------------------
+orawua7:.macro
+	orawu		\1,\2
+	.endm;
+//--------------------------------------------------------------------
+// // ora.w	d16(ay),ax
+//--------------------------------------------------------------------
+orawd16a:.macro
+	jmp			ii_error
+	.endm;
+//--------------------------------------------------------------------
+// // ora.w	d8(ay,dy),ax
+//--------------------------------------------------------------------
+orawd8a:.macro
+	jmp			ii_error
+	.endm;
+//--------------------------------------------------------------------
+// // ora.w	xxx.w,ax
+//--------------------------------------------------------------------
+orawxwax:.macro
+	jmp			ii_error
+	.endm;
+//--------------------------------------------------------------------
+// // ora.w	xxx.l,ax
+//--------------------------------------------------------------------
+orawxlax:.macro
+	jmp			ii_error
+	.endm;
+//--------------------------------------------------------------------
+// // ora.w	d16(pc),ax
+//--------------------------------------------------------------------
+orawd16pcax:.macro
+	jmp			ii_error
+	.endm;
+//--------------------------------------------------------------------
+// // ora.w	d8(pc,dy),ax
+//--------------------------------------------------------------------
+orawd8pcax:.macro
+	jmp			ii_error
+	.endm;
+//--------------------------------------------------------------------
+// // ora.w	#im,ax
+//--------------------------------------------------------------------
+orawim:.macro
+	jmp			ii_error
+	.endm;
+//--------------------------------------------------------------------
+// // ora.l	d8(ay,dy),ax
+//--------------------------------------------------------------------
+orald8a:.macro
+	jmp			ii_error
+	.endm;
+//--------------------------------------------------------------------
+// // ora.l	d8(pc,dy),ax
+//--------------------------------------------------------------------
+orald8pcax:.macro
+	jmp			ii_error
+	.endm;
+//*****************************************************************************************
+// spezial addx subx etc.
+//--------------------------------------------------------------------
+//--------------------------------------------------------------------
+// // addx	dy,dx
+//--------------------------------------------------------------------
+ordx:.macro
+	jmp			ii_error
+	.endm;
+//--------------------------------------------------------------------
+// // addx	-(ay),-(ax)
+//--------------------------------------------------------------------
+ordax:.macro
+	jmp			ii_error
+	.endm;
+//--------------------------------------------------------------------
diff --git a/firebeeV1/sources/ii_pea.h b/firebeeV1/sources/ii_pea.h
new file mode 100644
index 0000000..69f69d0
--- /dev/null
+++ b/firebeeV1/sources/ii_pea.h
@@ -0,0 +1,74 @@
+//--------------------------------------------------------------------
+// pea
+//--------------------------------------------------------------------
+.text
+ii_pea_lset:.macro
+	ii_lset_opeag	48,7
+	ii_lset	0x487b 
+.endm
+//---------------------------------------------------------------------------------------------
+ii_pea_func:.macro
+ii_0x4870:
+#ifdef	halten_pea
+	halt
+#endif
+	move.l	a0_off(a7),a1
+	pea_macro
+ii_0x4871:
+#ifdef	halten_pea
+	halt
+#endif
+	move.l	a1_off(a7),a1
+	pea_macro
+ii_0x4872:
+#ifdef	halten_pea
+	halt
+#endif
+	move.l	a2,a1
+	pea_macro
+ii_0x4873:
+#ifdef	halten_pea
+	halt
+#endif
+	move.l	a3,a1
+	pea_macro
+ii_0x4874:
+#ifdef	halten_pea
+	halt
+#endif
+	move.l	a4,a1
+	pea_macro
+ii_0x4875:
+#ifdef	halten_pea
+	halt
+#endif
+	move.l	a5,a1
+	pea_macro
+ii_0x4876:
+#ifdef	halten_pea
+	halt
+#endif
+	move.l	a6,a1
+	pea_macro
+ii_0x4877:
+#ifdef	halten_pea
+	halt
+#endif
+	move.l	usp,a1
+	pea_macro
+ii_0x487b:
+#ifdef	halten_pea
+	halt
+#endif
+	move.l	a0,a1
+	pea_macro
+.endm		
+//---------------------------------------------------------------------------------------------
+pea_macro:.macro
+	jsr		ewf
+	move.l	(a1),d0
+	move.l	usp,a1
+	move.l	d0,-(a1)
+	move.l	a1,usp
+	ii_end
+.endm
\ No newline at end of file
diff --git a/firebeeV1/sources/ii_shd.h b/firebeeV1/sources/ii_shd.h
new file mode 100644
index 0000000..ecace29
--- /dev/null
+++ b/firebeeV1/sources/ii_shd.h
@@ -0,0 +1,247 @@
+/*****************************************************************************************/
+// opertionen
+/*****************************************************************************************/
+ii_lset_shd:.macro
+	ii_lset_shdx	e0			//r d0
+	ii_lset_shdx	e2			//r d1
+	ii_lset_shdx	e4			//r d2
+	ii_lset_shdx	e6			//r d3
+	ii_lset_shdx	e8			//r d4
+	ii_lset_shdx	ea			//r d5
+	ii_lset_shdx	ec			//r d6
+	ii_lset_shdx	ee			//r d7
+	
+	ii_lset_shdx	e1			//l d0
+	ii_lset_shdx	e3			//l d1
+	ii_lset_shdx	e4			//l d2
+	ii_lset_shdx	e5			//l d3
+	ii_lset_shdx	e9			//l d4
+	ii_lset_shdx	eb			//l d5
+	ii_lset_shdx	ed			//l d6
+	ii_lset_shdx	ef			//l d7
+	.endm
+	
+ii_lset_shdx:.macro
+//byt
+	ii_lset_opea	\1,0			// as,ls #im,dx
+	ii_lset_opea	\1,1			// rox,ro #im,dx
+	ii_lset_opea	\1,2			// as,ls dy,dx
+	ii_lset_opea	\1,3			// rox,ro dy,dx
+//word
+	ii_lset_opea	\1,4			// as,ls #im,dx
+	ii_lset_opea	\1,5			// rox,ro #im,dx
+	ii_lset_opea	\1,6			// as,ls dy,dx
+	ii_lset_opea	\1,7			// rox,ro dy,dx
+//long
+//	ii_lset_opea	\1,8			// as,ls #im,dx -> vorhanden
+	ii_lset_opea	\1,9			// rox,ro #im,dx
+//	ii_lset_opea	\1,a			// as,ls dy,dx	-> vorhanden
+	ii_lset_opea	\1,b			// rox,ro dy,dx
+	.endm
+/******************************************************/
+ii_shd:.macro	// 1=code 2=operation 3 = normal, direct oder immediat
+// byt
+	opdx	\1,\2,b,0,\3		// dx
+// word
+	opdx	\1,\2,w,4,\3		// dx
+// long
+	opdx	\1,\2,l,8,\3		// dx
+	.endm
+/******************************************************/
+// byt word long routinen
+/******************************************************/
+sh_asr:	.macro		// asr -> 1=operation 2 = dx 3 = dy/im 4 = size b/w
+	mvs.\4		\2,d1
+	sh_shal		\1,\2,\3,\4
+	.endm	
+
+sh_lsr:	.macro		// asl -> 1=operation 2 = dx 3 = dy/im 4 = size b/w
+	mvz.\4		\2,d1
+	sh_shal		\1,\2,\3,\4
+	.endm
+	
+sh_shal:.macro
+	move.w		\3,d0
+	\1.l		d0,d1
+	set_cc0
+	move.\4		d1,\2
+	.endm	
+	
+sh_all:	.macro		// asl/lsl -> 1=operation 2 = dx 3 = dy/im 4 = size b/w
+	mvz.\4		\2,d1
+.ifc	\4,b
+	byterev.l	d1
+.else
+	swap.w		d1
+.endif
+	sh_asr		\1,\2,\3,\4
+	.endm	
+	
+sh_ror:	.macro		// ror -> 1=operation 2 = dx 3 = dy/im 4 = size b/w/l
+	move.\4	\2,d1	/
+	move.w	\3,d0
+.ifc	\4,b
+	lsl.l	#8,d1
+	move.b	\2,d1
+	and.l	#0x7,d0
+	lsr.l	d0,d1
+.else
+	.ifc	\4,w
+		swap.w	d1
+		move.w	\2,d1
+		and.l	#0xf,d0
+		lsr.l	d0,d1
+	.else
+		and.l	#0x1f,d0
+		lsr.l	d0,d1
+		move.l	d1,a1
+		move.l	\2,d1
+		sub.l	#32,d0
+		neg.l	d0
+		lsl.l	d0,d1
+		add.l	a1,d1
+	.endif
+.endif
+	move.\4	d1,\2
+	move.w	ccr,d0
+	and.l	#1,d1	// ist auch carry bit
+	or.l	d1,d0	
+	move.b	d0,ccr_off(a7)
+	.endm
+	
+sh_rol:	.macro		// rol -> 1=operation 2 = dx 3 = dy/im 4 = size b/w/l
+	move.\4	\2,d1	
+	move.w	\3,d0
+.ifc	\4,b
+	lsl.l	#8,d1
+	move.b	\2,d1
+	and.l	#0x7,d0
+	lsl.l	d0,d1
+	lsr.l	#8,d1
+	moveq	#7,d0
+.else
+	.ifc	\4,w
+		swap.w	d1
+		move.w	\2,d1
+		and.l	#0xf,d0
+		lsr.l	d0,d1
+		swap.w	d1
+		moveq	#15,d0
+	.else
+		and.l	#0x1f,d0
+		lsl.l	d0,d1
+		move.l	d1,a1
+		move.l	\2,d1
+		sub.l	#32,d0
+		neg.l	d0
+		lsr.l	d0,d1
+		add.l	a1,d1
+		moveq	#31,d0
+	.endif
+.endif
+	move.\4	d1,\2
+	lsr.l	d0,d1		// carry bit schieben
+	move.w	ccr,d0
+	and.l	#1,d1
+	or.l	d1,d0	
+	move.b	d0,ccr_off(a7)
+	.endm
+	
+sh_roxr:	.macro		// roxr -> 1=operation 2 = dx 3 = dy/im 4 = size b/w/l
+	clr.l	d0
+	addx.l	d0,d0
+ifc	\4,b
+	mvz.b	\2,d1
+	lsl.l	#1,d1
+	add.l	d0,d1
+	lsl.l	#8,d1
+	move.b	\2,d1
+	move.w	\3,d0
+	and.l	#0x7,d0
+	lsr.l	d0,d1
+	set_cc0
+else
+	.ifc	\4,w
+		mvz.b	\2,d1
+		lsl.l	#1,d1
+		add.l	d0,d1
+		lsl.l	#8,d1
+		lsl.l	#8,d1
+		move.w	\2,d1
+		move.w	\3,d0
+		and.l	#0xf,d0
+		lsr.l	d0,d1
+		set_cc0
+	.else
+		bitrev.l d0
+		move.l	\2,d1
+		lsr.l	#1,d1
+		add.l	d0,d1
+		move.w	\3,d0
+		subq.l	#1,d0
+		and.l	#0x1f,d0
+		lsr.l	d0,d1
+		move.l	d1,a1
+		set_cc1
+		move.l	\2,d1
+		sub.l	#32,d0
+		neg.l	d0
+		lsl.l	d0,d1
+		add.l	a1,d1
+	.endif
+.endif
+	move.\4	d1,\2
+	.endm
+	
+sh_roxl:	.macro		// roxl -> 1=operation 2 = dx 3 = dy/im 4 = size b/w/l
+	clr.l	d0
+	addx.l	d0,d0
+ifc	\4,b
+	mvz.b	\2,d1
+	lsl.l	#1,d1
+	add.l	d0,d1
+	lsl.l	#8,d1
+	move.b	\2,d1
+	lsl.l	#8,d1
+	lsl.l	#7,d1
+	move.w	\3,d0
+	and.l	#0x7,d0
+	lsl.l	d0,d1
+	set_cc0
+	byterev.l d1
+else
+	.ifc	\4,w
+		mvz.b	\2,d1
+		lsl.l	#1,d1
+		add.l	d0,d1
+		lsl.l	#8,d1
+		lsl.l	#7,d1
+		mvz.w	\2,d0
+		lsr.l	#1,d0
+		add.l	d0,d1
+		move.w	\3,d0
+		and.l	#0xf,d0
+		lsl.l	d0,d1
+		set_cc0
+		swap.w	d1
+	.else
+		move.l	\2,d1
+		lsl.l	#1,d1
+		add.l	d0,d1
+		move.w	\3,d0
+		subq.l	#1,d0
+		and.l	#0x1f,d0
+		lsl.l	d0,d1
+		move.l	d1,a1
+		set_cc1
+		move.l	\2,d1
+		sub.l	#32,d0
+		neg.l	d0
+		lsr.l	d0,d1
+		add.l	a1,d1
+	.endif
+.endif
+	move.\4	d1,\2
+	.endm
+	
+	
\ No newline at end of file
diff --git a/firebeeV1/sources/ii_shift.h b/firebeeV1/sources/ii_shift.h
new file mode 100644
index 0000000..f83bfcb
--- /dev/null
+++ b/firebeeV1/sources/ii_shift.h
@@ -0,0 +1,687 @@
+/*****************************************************************************************/
+// opertionen
+/*****************************************************************************************/
+ii_shift_lset:.macro
+/******************************************************/
+// byt
+/******************************************************/
+//  asx.b #,dx
+	ii_lset_dx	\1,00						// 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c			
+	ii_lset_dx	\1,01			
+	ii_lset_dx	\1,02			
+	ii_lset_dx	\1,03			
+	ii_lset_dx	\1,04			
+	ii_lset_dx	\1,05			
+	ii_lset_dx	\1,06			
+	ii_lset_dx	\1,07			
+// lsx.b #,dx
+	ii_lset_dxu	\1,08			
+	ii_lset_dxu	\1,09			
+	ii_lset_dxu	\1,0a			
+	ii_lset_dxu	\1,0b			
+	ii_lset_dxu	\1,0c			
+	ii_lset_dxu	\1,0d			
+	ii_lset_dxu	\1,0e			
+	ii_lset_dxu	\1,0f			
+// roxx.b #,dx
+	ii_lset_dx	\1,10			
+	ii_lset_dx	\1,11			
+	ii_lset_dx	\1,12			
+	ii_lset_dx	\1,13			
+	ii_lset_dx	\1,14			
+	ii_lset_dx	\1,15			
+	ii_lset_dx	\1,16			
+	ii_lset_dx	\1,17			
+// rox.b #,dx
+	ii_lset_dx	\1,18			
+	ii_lset_dx	\1,19			
+	ii_lset_dx	\1,1a			
+	ii_lset_dx	\1,1b			
+	ii_lset_dx	\1,1c			
+	ii_lset_dx	\1,1d			
+	ii_lset_dx	\1,1e			
+	ii_lset_dx	\1,1f			
+// asx.b dy,dx
+	ii_lset_dx	\1,20			
+	ii_lset_dx	\1,21			
+	ii_lset_dx	\1,22			
+	ii_lset_dx	\1,23			
+	ii_lset_dx	\1,24			
+	ii_lset_dx	\1,25			
+	ii_lset_dx	\1,26			
+	ii_lset_dx	\1,27			
+// lsx.b dy,dx
+	ii_lset_dx	\1,28			
+	ii_lset_dx	\1,29			
+	ii_lset_dx	\1,2a			
+	ii_lset_dx	\1,2b			
+	ii_lset_dx	\1,2c			
+	ii_lset_dx	\1,2d			
+	ii_lset_dx	\1,2e			
+	ii_lset_dx	\1,2f			
+// roxx.dy,dx
+	ii_lset_dx	\1,30			
+	ii_lset_dx	\1,31			
+	ii_lset_dx	\1,32			
+	ii_lset_dx	\1,33			
+	ii_lset_dx	\1,34			
+	ii_lset_dx	\1,35			
+	ii_lset_dx	\1,36			
+	ii_lset_dx	\1,37			
+// rox.b dy,dx
+	ii_lset_dx	\1,38			
+	ii_lset_dx	\1,39			
+	ii_lset_dx	\1,3a			
+	ii_lset_dx	\1,3b			
+	ii_lset_dx	\1,3c			
+	ii_lset_dx	\1,3d			
+	ii_lset_dx	\1,3e			
+	ii_lset_dx	\1,3f			
+/******************************************************/
+// word
+/******************************************************/
+// asx.w #x,dx
+	ii_lset_dx	\1,40						// 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c			
+	ii_lset_dx	\1,41			
+	ii_lset_dx	\1,42			
+	ii_lset_dx	\1,43			
+	ii_lset_dx	\1,44			
+	ii_lset_dx	\1,45			
+	ii_lset_dx	\1,46			
+	ii_lset_dx	\1,47			
+// lsx.w #,dx
+	ii_lset_dx	\1,48			
+	ii_lset_dx	\1,49			
+	ii_lset_dx	\1,4a			
+	ii_lset_dx	\1,4b			
+	ii_lset_dx	\1,4c			
+	ii_lset_dx	\1,4d			
+	ii_lset_dx	\1,4e			
+	ii_lset_dx	\1,4f			
+// roxx.w #,dx
+	ii_lset_dx	\1,50			
+	ii_lset_dx	\1,51			
+	ii_lset_dx	\1,52			
+	ii_lset_dx	\1,53			
+	ii_lset_dx	\1,54			
+	ii_lset_dx	\1,55			
+	ii_lset_dx	\1,56			
+	ii_lset_dx	\1,57			
+// rox.w #xdx
+	ii_lset_dx	\1,58			
+	ii_lset_dx	\1,59			
+	ii_lset_dx	\1,5a			
+	ii_lset_dx	\1,5b			
+	ii_lset_dx	\1,5c			
+	ii_lset_dx	\1,5d			
+	ii_lset_dx	\1,5e			
+	ii_lset_dx	\1,5f			
+// asx.w dy,dx
+	ii_lset_dx	\1,60			
+	ii_lset_dx	\1,61			
+	ii_lset_dx	\1,62			
+	ii_lset_dx	\1,63			
+	ii_lset_dx	\1,64			
+	ii_lset_dx	\1,65			
+	ii_lset_dx	\1,66			
+	ii_lset_dx	\1,67			
+// lsx.w dy,dx
+	ii_lset_dx	\1,68			
+	ii_lset_dx	\1,69			
+	ii_lset_dx	\1,6a			
+	ii_lset_dx	\1,6b			
+	ii_lset_dx	\1,6c			
+	ii_lset_dx	\1,6d			
+	ii_lset_dx	\1,6e			
+	ii_lset_dx	\1,6f			
+// roxx.w dy,dx
+	ii_lset_dx	\1,70			
+	ii_lset_dx	\1,71			
+	ii_lset_dx	\1,72			
+	ii_lset_dx	\1,73			
+	ii_lset_dx	\1,74			
+	ii_lset_dx	\1,75			
+	ii_lset_dx	\1,76			
+	ii_lset_dx	\1,77			
+// rox.w dy,dx
+	ii_lset_dx	\1,78			
+	ii_lset_dx	\1,79			
+	ii_lset_dx	\1,7a			
+	ii_lset_dx	\1,7b			
+	ii_lset_dx	\1,7c			
+	ii_lset_dx	\1,7d			
+	ii_lset_dx	\1,7e			
+	ii_lset_dx	\1,7f			
+/******************************************************/
+// long
+/******************************************************/
+// roxx.l #,dx
+	ii_lset_dx	\1,90			
+	ii_lset_dx	\1,91			
+	ii_lset_dx	\1,92			
+	ii_lset_dx	\1,93			
+	ii_lset_dx	\1,94			
+	ii_lset_dx	\1,95			
+	ii_lset_dx	\1,96			
+	ii_lset_dx	\1,97			
+// rox.l #xdx
+	ii_lset_dx	\1,98			
+	ii_lset_dx	\1,99			
+	ii_lset_dx	\1,9a			
+	ii_lset_dx	\1,9b			
+	ii_lset_dx	\1,9c			
+	ii_lset_dx	\1,9d			
+	ii_lset_dx	\1,9e			
+	ii_lset_dx	\1,9f			
+// roxx.l dy,dx
+	ii_lset_dx	\1,b0			
+	ii_lset_dx	\1,b1			
+	ii_lset_dx	\1,b2			
+	ii_lset_dx	\1,b3			
+	ii_lset_dx	\1,b4			
+	ii_lset_dx	\1,b5			
+	ii_lset_dx	\1,b6			
+	ii_lset_dx	\1,b7			
+// rox.l dy,dx
+	ii_lset_dx	\1,b8			
+	ii_lset_dx	\1,b9			
+	ii_lset_dx	\1,ba			
+	ii_lset_dx	\1,bb			
+	ii_lset_dx	\1,bc			
+	ii_lset_dx	\1,bd			
+	ii_lset_dx	\1,be			
+	ii_lset_dx	\1,bf
+//--------------------------------------------------------------------
+// asr.w ea
+	ii_lset_opea	\10,d			// (ax), (ax)+
+	ii_lset_opea	\10,e			// -(ax),d16(ax)
+	ii_lset_opeag	\10,f			// d8(ax,dy)
+	lea	table+0x\10\2f8*4,a0
+	move.l	#ii_0x\10f8,(a0)+		// xxx.w
+	move.l	#ii_0x\10f9,(a0)+		// xxx.l
+// asl.w ea
+	ii_lset_opea	\11,d			// (ax), (ax)+
+	ii_lset_opea	\11,e			// -(ax),d16(ax)
+	ii_lset_opeag	\11,f			// d8(ax,dy)
+	lea	table+0x\11\2f8*4,a0
+	move.l	#ii_0x\11f8,(a0)+		// xxx.w
+	move.l	#ii_0x\11f9,(a0)+		// xxx.l
+// lsr.w ea
+	ii_lset_opea	\12,d			// (ax), (ax)+
+	ii_lset_opea	\12,e			// -(ax),d16(ax)
+	ii_lset_opeag	\12,f			// d8(ax,dy)
+	lea	table+0x\12\2f8*4,a0
+	move.l	#ii_0x\12f8,(a0)+		// xxx.w
+	move.l	#ii_0x\12f9,(a0)+		// xxx.l
+// lsr.w ea
+	ii_lset_opea	\13,d			// (ax), (ax)+
+	ii_lset_opea	\13,e			// -(ax),d16(ax)
+	ii_lset_opeag	\13,f			// d8(ax,dy)
+	lea	table+0x\13\2f8*4,a0
+	move.l	#ii_0x\13f8,(a0)+		// xxx.w
+	move.l	#ii_0x\13f9,(a0)+		// xxx.l
+// roxr.w ea
+	ii_lset_opea	\14,d			// (ax), (ax)+
+	ii_lset_opea	\14,e			// -(ax),d16(ax)
+	ii_lset_opeag	\14,f			// d8(ax,dy)
+	lea	table+0x\14\2f8*4,a0
+	move.l	#ii_0x\14f8,(a0)+		// xxx.w
+	move.l	#ii_0x\14f9,(a0)+		// xxx.l
+// roxl.w ea
+	ii_lset_opea	\15,e			// (ax), (ax)+
+	ii_lset_opea	\15,e			// -(ax),d16(ax)
+	ii_lset_opeag	\15,f			// d8(ax,dy)
+	lea	table+0x\15\2f8*4,a0
+	move.l	#ii_0x\15f8,(a0)+		// xxx.w
+	move.l	#ii_0x\15f9,(a0)+		// xxx.l
+// ror.w ea
+	ii_lset_opea	\16,d			// (ax), (ax)+
+	ii_lset_opea	\16,e			// -(ax),d16(ax)
+	ii_lset_opeag	\16,f			// d8(ax,dy)
+	lea	table+0x\16\2f8*4,a0
+	move.l	#ii_0x\16f8,(a0)+		// xxx.w
+	move.l	#ii_0x\16f9,(a0)+		// xxx.l
+// rol.w ea
+	ii_lset_opea	\17,d			// (ax), (ax)+
+	ii_lset_opea	\17,e			// -(ax),d16(ax)
+	ii_lset_opeag	\17,f			// d8(ax,dy)
+	lea	table+0x\17\2f8*4,a0
+	move.l	#ii_0x\17f8,(a0)+		// xxx.w
+	move.l	#ii_0x\17f9,(a0)+		// xxx.l
+// ende
+.endm;	
+/******************************************************/
+ii_shift_op:.macro	// 1=code 
+//byt-------------------------------
+//asx.b	#x,dx
+	ii_shift_op2agb	0,as,a
+//lsx.b	#x,dx
+	ii_shift_op2aub	0,ls,a
+//roxx.b	#x,dx
+	ii_shift_op2agb	1,rox,a
+//rox.b	#x,dx
+	ii_shift_op2aub	1,ro,a
+//asx.b	dy,dx
+	ii_shift_op2agb	2,as,b
+//lsx.b	dy,dx
+	ii_shift_op2aub	2,ls,b
+//roxx.b dy,dx
+	ii_shift_op2agb	3,rox,b
+//rox.b	dy,dx
+	ii_shift_op2aub	3,ro,b
+// word ---------------------------------------
+//asx.w	#x,dx
+	ii_shift_op2agw	4,as,a
+//lsx.w	#x,dx
+	ii_shift_op2auw	4,ls,a
+//roxx.w	#x,dx
+	ii_shift_op2agw	5,rox,a
+//rox.w	#x,dx
+	ii_shift_op2auw	5,ro,a
+//asx.w	dy,dx
+	ii_shift_op2agw	6,as,b
+//lsx.w	dy,dx
+	ii_shift_op2auw	6,ls,b
+//roxx.w dy,dx
+	ii_shift_op2agw	7,rox,b
+//rox.w	dy,dx
+	ii_shift_op2auw	7,ro,b
+// long ---------------------------------------
+//roxx.l #x,dx
+	ii_shift_op2agw	9,rox,a
+//rox.l	#x,dx
+	ii_shift_op2auw	9,ro,a
+//roxx.l dy,dx
+	ii_shift_op2agw	b,rox,b
+//rox.l	dy,dx
+	ii_shift_op2auw	b,ro,b
+// ea ---------------------------------------
+//asr.w	#1,ea
+	ii_shift_op2ea	0,asr
+//asl.w	#1,ea
+	ii_shift_op2ea	1,asl
+//lsr.w	#1,ea
+	ii_shift_op2ea	2,lsr,
+//lsl.w	#1,ea
+	ii_shift_op2ea	3,lsl
+//roxr.w #1,ea
+	ii_shift_op2ea	4,roxr
+//roxl.w #1,ea
+	ii_shift_op2ea	5,roxl
+//ror.w	#1,ea
+	ii_shift_op2ea	6,ror
+//rol.w	#1,ea
+	ii_shift_op2ea	7,rol
+.endm
+//byt ============================================
+ii_shift_op2agb:.macro	//byt: 1=code 2=operation 3=quick(a) oder register(b)
+	ii_shift_op1\3b	\1,0,\2,d0_off+3(a7)
+	ii_shift_op1\3b	\1,1,\2,d1_off+3(a7)
+	ii_shift_op1\3b	\1,2,\2,d2
+	ii_shift_op1\3b	\1,3,\2,d3
+	ii_shift_op1\3b	\1,4,\2,d4
+	ii_shift_op1\3b	\1,5,\2,d5
+	ii_shift_op1\3b	\1,6,\2,d6
+	ii_shift_op1\3b	\1,7,\2,d7
+.endm
+
+ii_shift_op2aub:.macro	//byt: 1=code 2=operation
+	ii_shift_op1\3b	\1,8,\2,d0_off+3(a7)
+	ii_shift_op1\3b	\1,9,\2,d1_off+3(a7)
+	ii_shift_op1\3b	\1,a,\2,d2
+	ii_shift_op1\3b	\1,b,\2,d3
+	ii_shift_op1\3b	\1,c,\2,d4
+	ii_shift_op1\3b	\1,d,\2,d5
+	ii_shift_op1\3b	\1,e,\2,d6
+	ii_shift_op1\3b	\1,f,\2,d7
+.endm
+
+ii_shift_op1ab:.macro	// z.B. asr.w. #x,dx 1=code 3.ziffer 2=code 4.ziffer 3=shift art 4=dx
+	ii_shift_op0	0\1\2,b,\3r,#8,\4
+	ii_shift_op0	2\1\2,b,\3r,#1,\4
+	ii_shift_op0	4\1\2,b,\3r,#2,\4
+	ii_shift_op0	6\1\2,b,\3r,#3,\4
+	ii_shift_op0	8\1\2,b,\3r,#4,\4
+	ii_shift_op0	a\1\2,b,\3r,#5,\4
+	ii_shift_op0	c\1\2,b,\3r,#6,\4
+	ii_shift_op0	e\1\2,b,\3r,#7,\4
+	ii_shift_op0	1\1\2,b,\3l,#8,\4
+	ii_shift_op0	3\1\2,b,\3l,#1,\4
+	ii_shift_op0	5\1\2,b,\3l,#2,\4
+	ii_shift_op0	7\1\2,b,\3l,#3,\4
+	ii_shift_op0	9\1\2,b,\3l,#4,\4
+	ii_shift_op0	b\1\2,b,\3l,#5,\4
+	ii_shift_op0	d\1\2,b,\3l,#6,\4
+	ii_shift_op0	f\1\2,b,\3l,#7,\4
+.endm
+	
+ii_shift_op1bb:.macro	// z.B. asr.w. #x,dx 1=code 3.ziffer 2=code 4.ziffer 3=shift art 4=dx
+	ii_shift_op0b	0\1\2,b,\3r,d0_off(a7),\4
+	ii_shift_op0b	2\1\2,b,\3r,d1_off(a7),\4
+	ii_shift_op0	4\1\2,b,\3r,d2,\4
+	ii_shift_op0	6\1\2,b,\3r,d3,\4
+	ii_shift_op0	8\1\2,b,\3r,d4,\4
+	ii_shift_op0	a\1\2,b,\3r,d5,\4
+	ii_shift_op0	c\1\2,b,\3r,d6,\4
+	ii_shift_op0	e\1\2,b,\3r,d7,\4
+	ii_shift_op0b	1\1\2,b,\3l,d0_off(a7),\4
+	ii_shift_op0b	3\1\2,b,\3l,d1_off(a7),\4
+	ii_shift_op0	5\1\2,b,\3l,d2,\4
+	ii_shift_op0	7\1\2,b,\3l,d3,\4
+	ii_shift_op0	9\1\2,b,\3l,d4,\4
+	ii_shift_op0	b\1\2,b,\3l,d5,\4
+	ii_shift_op0	d\1\2,b,\3l,d6,\4
+	ii_shift_op0	f\1\2,b,\3l,d7,\4
+.endm
+// word ---------------------------------------
+ii_shift_op2agw:.macro	//byt: 1=code 2=operation 3=quick(a) oder register(b)
+	ii_shift_op1\3w	\1,0,\2,d0_off+2(a7)
+	ii_shift_op1\3w	\1,1,\2,d1_off+2(a7)
+	ii_shift_op1\3w	\1,2,\2,d2
+	ii_shift_op1\3w	\1,3,\2,d3
+	ii_shift_op1\3w	\1,4,\2,d4
+	ii_shift_op1\3w	\1,5,\2,d5
+	ii_shift_op1\3w	\1,6,\2,d6
+	ii_shift_op1\3w	\1,7,\2,d7
+.endm
+
+ii_shift_op2auw:.macro	//byt: 1=code 2=operation
+	ii_shift_op1\3w	\1,8,\2,d0_off+2(a7)
+	ii_shift_op1\3w	\1,9,\2,d1_off+2(a7)
+	ii_shift_op1\3w	\1,a,\2,d2
+	ii_shift_op1\3w	\1,b,\2,d3
+	ii_shift_op1\3w	\1,c,\2,d4
+	ii_shift_op1\3w	\1,d,\2,d5
+	ii_shift_op1\3w	\1,e,\2,d6
+	ii_shift_op1\3w	\1,f,\2,d7
+.endm
+
+ii_shift_op1aw:.macro	// z.B. asr.w. #x,dx 1=code 3.ziffer 2=code 4.ziffer 3=shift art 4=dx
+	ii_shift_op0	0\1\2,w,\3r,#8,\4
+	ii_shift_op0	2\1\2,w,\3r,#1,\4
+	ii_shift_op0	4\1\2,w,\3r,#2,\4
+	ii_shift_op0	6\1\2,w,\3r,#3,\4
+	ii_shift_op0	8\1\2,w,\3r,#4,\4
+	ii_shift_op0	a\1\2,w,\3r,#5,\4
+	ii_shift_op0	c\1\2,w,\3r,#6,\4
+	ii_shift_op0	e\1\2,w,\3r,#7,\4
+	ii_shift_op0	1\1\2,w,\3l,#8,\4
+	ii_shift_op0	3\1\2,w,\3l,#1,\4
+	ii_shift_op0	5\1\2,w,\3l,#2,\4
+	ii_shift_op0	7\1\2,w,\3l,#3,\4
+	ii_shift_op0	9\1\2,w,\3l,#4,\4
+	ii_shift_op0	b\1\2,w,\3l,#5,\4
+	ii_shift_op0	d\1\2,w,\3l,#6,\4
+	ii_shift_op0	f\1\2,w,\3l,#7,\4
+.endm
+	
+ii_shift_op1bw:.macro	// z.B. asr.w. #x,dx 1=code 3.ziffer 2=code 4.ziffer 3=shift art 4=dx
+	ii_shift_op0b	0\1\2,w,\3r,d0_off(a7),\4
+	ii_shift_op0b	2\1\2,w,\3r,d1_off(a7),\4
+	ii_shift_op0	4\1\2,w,\3r,d2,\4
+	ii_shift_op0	6\1\2,w,\3r,d3,\4
+	ii_shift_op0	8\1\2,w,\3r,d4,\4
+	ii_shift_op0	a\1\2,w,\3r,d5,\4
+	ii_shift_op0	c\1\2,w,\3r,d6,\4
+	ii_shift_op0	e\1\2,w,\3r,d7,\4
+	ii_shift_op0b	1\1\2,w,\3l,d0_off(a7),\4
+	ii_shift_op0b	3\1\2,w,\3l,d1_off(a7),\4
+	ii_shift_op0	5\1\2,w,\3l,d2,\4
+	ii_shift_op0	7\1\2,w,\3l,d3,\4
+	ii_shift_op0	9\1\2,w,\3l,d4,\4
+	ii_shift_op0	b\1\2,w,\3l,d5,\4
+	ii_shift_op0	d\1\2,w,\3l,d6,\4
+	ii_shift_op0	f\1\2,w,\3l,d7,\4
+.endm
+// long ---------------------------------------
+ii_shift_op2agl:.macro	//byt: 1=code 2=operation 3=quick(a) oder register(b)
+	ii_shift_op1\3l	\1,0,\2,d0_off(a7)
+	ii_shift_op1\3l	\1,1,\2,d1_off(a7)
+	ii_shift_op1\3l	\1,2,\2,d2
+	ii_shift_op1\3l	\1,3,\2,d3
+	ii_shift_op1\3l	\1,4,\2,d4
+	ii_shift_op1\3l	\1,5,\2,d5
+	ii_shift_op1\3l	\1,6,\2,d6
+	ii_shift_op1\3l	\1,7,\2,d7
+.endm
+
+ii_shift_op2aul:.macro	//byt: 1=code 2=operation
+	ii_shift_op1\3l	\1,8,\2,d0_off(a7)
+	ii_shift_op1\3l	\1,9,\2,d1_off(a7)
+	ii_shift_op1\3l	\1,a,\2,d2
+	ii_shift_op1\3l	\1,b,\2,d3
+	ii_shift_op1\3l	\1,c,\2,d4
+	ii_shift_op1\3l	\1,d,\2,d5
+	ii_shift_op1\3l	\1,e,\2,d6
+	ii_shift_op1\3l	\1,f,\2,d7
+.endm
+
+ii_shift_op1al:.macro	// z.B. asr.w. #x,dx 1=code 3.ziffer 2=code 4.ziffer 3=shift art 4=dx
+	ii_shift_op0	0\1\2,l,\3r,#8,\4
+	ii_shift_op0	2\1\2,l,\3r,#1,\4
+	ii_shift_op0	4\1\2,l,\3r,#2,\4
+	ii_shift_op0	6\1\2,l,\3r,#3,\4
+	ii_shift_op0	8\1\2,l,\3r,#4,\4
+	ii_shift_op0	a\1\2,l,\3r,#5,\4
+	ii_shift_op0	c\1\2,l,\3r,#6,\4
+	ii_shift_op0	e\1\2,l,\3r,#7,\4
+	ii_shift_op0	1\1\2,l,\3l,#8,\4
+	ii_shift_op0	3\1\2,l,\3l,#1,\4
+	ii_shift_op0	5\1\2,l,\3l,#2,\4
+	ii_shift_op0	7\1\2,l,\3l,#3,\4
+	ii_shift_op0	9\1\2,l,\3l,#4,\4
+	ii_shift_op0	b\1\2,l,\3l,#5,\4
+	ii_shift_op0	d\1\2,l,\3l,#6,\4
+	ii_shift_op0	f\1\2,l,\3l,#7,\4
+.endm
+	
+ii_shift_op1bl:.macro	// z.B. asr.w. #x,dx 1=code 3.ziffer 2=code 4.ziffer 3=shift art 4=dx
+	ii_shift_op0b	0\1\2,l,\3r,d0_off(a7),\4
+	ii_shift_op0b	2\1\2,l,\3r,d1_off(a7),\4
+	ii_shift_op0	4\1\2,l,\3r,d2,\4
+	ii_shift_op0	6\1\2,l,\3r,d3,\4
+	ii_shift_op0	8\1\2,l,\3r,d4,\4
+	ii_shift_op0	a\1\2,l,\3r,d5,\4
+	ii_shift_op0	c\1\2,l,\3r,d6,\4
+	ii_shift_op0	e\1\2,l,\3r,d7,\4
+	ii_shift_op0b	1\1\2,l,\3l,d0_off(a7),\4
+	ii_shift_op0b	3\1\2,l,\3l,d1_off(a7),\4
+	ii_shift_op0	5\1\2,l,\3l,d2,\4
+	ii_shift_op0	7\1\2,l,\3l,d3,\4
+	ii_shift_op0	9\1\2,l,\3l,d4,\4
+	ii_shift_op0	b\1\2,l,\3l,d5,\4
+	ii_shift_op0	d\1\2,l,\3l,d6,\4
+	ii_shift_op0	f\1\2,l,\3l,d7,\4
+.endm
+// .word ea ============================================
+ii_shift_op2ea:.macro		//1=code 2.ziffer 2=shiftart
+// (a0) bis (a7) ----------------------------
+ii_0xe\1d0:				 
+	move.l	a0_off(a7),a1
+	ii_shift_typ	w,\2,#1,(a1),(a1).
+ii_0xe\1d1:				 
+	move.l	a1_off(a7),a1
+	ii_shift_typ	w,\2,#1,(a1),(a1).
+ii_0xe\1d2:	
+	ii_shift_typ	w,\2,#1,(a2),(a2).
+ii_0xe\1d3:	
+	ii_shift_typ	w,\2,#1,(a3),(a3).
+ii_0xe\1d4:	
+	ii_shift_typ	w,\2,#1,(a4),(a4).
+ii_0xe\1d5:	
+	ii_shift_typ	w,\2,#1,(a5),(a5).
+ii_0xe\1d6:	
+	ii_shift_typ	w,\2,#1,(a6),(a6).
+ii_0xe\1d7:	
+	move.l	usp,a1
+	ii_shift_typ	w,\2,#1,(a1),(a1).
+// (a0)+ bis (a7)+ -----------------------------
+ii_0xe\1d8:				 
+	move.l	a0_off(a7),a1
+	addq.l	#2,a0_off(a7)
+	ii_shift_typ	w,\2,#1,(a1),(a1).
+ii_0xe\1d9:				 
+	move.l	a1_off(a7),a1
+	addq.l	#2,a0_off(a7)
+	ii_shift_typ	w,\2,#1,(a1),(a1).
+ii_0xe\1da:	
+	ii_shift_typ	w,\2,#1,(a2),(a2)+.
+ii_0xe\1db:	
+	ii_shift_typ	w,\2,#1,(a3),(a3)+
+ii_0xe\1dc:	
+	ii_shift_typ	w,\2,#1,(a4),(a4)+
+ii_0xe\1dd:	
+	ii_shift_typ	w,\2,#1,(a5),(a5)+
+ii_0xe\1de:	
+	ii_shift_typ	w,\2,#1,(a6),(a6)+
+ii_0xe\1df:	
+	move.l	usp,a1
+	addq.l	#2,a1
+	move.l	a1,usp
+	subq.l	#2,a1
+	ii_shift_typ	w,\2,#1,(a1),(a1).
+// -(a0) bis -(a7) -----------------------------
+ii_0xe\1e0:				 
+	move.l	a0_off(a7),a1
+	subq.l	#2,a1
+	move.l	a1,a0_off(a7)
+	ii_shift_typ	w,\2,#1,(a1),(a1).
+ii_0xe\1e1:				 
+	move.l	a1_off(a7),a1
+	subq.l	#2,a1
+	move.l	a1,a1_off(a7)
+	ii_shift_typ	w,\2,#1,(a1),(a1).
+ii_0xe\1e2:	
+	ii_shift_typ	w,\2,#1,-(a2),(a2).
+ii_0xe\1e3:	
+	ii_shift_typ	w,\2,#1,-(a3),(a3)
+ii_0xe\1e4:	
+	ii_shift_typ	w,\2,#1,-(a4),(a4)
+ii_0xe\1e5:	
+	ii_shift_typ	w,\2,#1,-(a5),(a5)
+ii_0xe\1e6:	
+	ii_shift_typ	w,\2,#1,-(a6),(a6)
+ii_0xe\1e7:	
+	move.l	usp,a1
+	subq.l	#2,a1
+	move.l	a1,usp
+	ii_shift_typ	w,\2,#1,(a1),(a1).
+// d16(a0) bis d16(a7) -----------------------------
+ii_0xe\1e8:	
+	move.w	(a0)+,a1			 
+	add.l	a0_off(a7),a1
+	ii_shift_typ	w,\2,#1,(a1),(a1).
+ii_0xe\1e9:				 
+	move.w	(a0)+,a1			 
+	add.l	a1_off(a7),a1
+	ii_shift_typ	w,\2,#1,(a1),(a1).
+ii_0xe\1ea:	
+	move.w	(a0)+,a1			 
+	add.l	a2,a1
+	ii_shift_typ	w,\2,#1,(a1),(a1).
+ii_0xe\1eb:	
+	move.w	(a0)+,a1			 
+	add.l	a3,a1
+	ii_shift_typ	w,\2,#1,(a1),(a1)
+ii_0xe\1ec:	
+	move.w	(a0)+,a1			 
+	add.l	a4,a1
+	ii_shift_typ	w,\2,#1,(a1),(a1)
+ii_0xe\1ed:	
+	move.w	(a0)+,a1			 
+	add.l	a5,a1
+	ii_shift_typ	w,\2,#1,(a1),(a1)
+ii_0xe\1ee:	
+	move.w	(a0)+,a1			 
+	add.l	a6,a1
+	ii_shift_typ	w,\2,#1,(a1),(a1)
+ii_0xe\1ef:	
+	mvs.w	(a0)+,d0
+	move.l	usp,a1			 
+	add.l	d0,a1
+	ii_shift_typ	w,\2,#1,(a1),(a1).
+// d8(a0,dy) bis d8(a7,dy) -----------------------------
+ii_0xe\1f0:	
+	move.l	a0_off(a0),a1			 
+	jsr	ewf
+	ii_shift_typ	w,\2,#1,(a1),(a1).
+ii_0xe\1f1:				 
+	move.l	a1_off(a0),a1			 
+	jsr	ewf
+	ii_shift_typ	w,\2,#1,(a1),(a1).
+ii_0xe\1f2:	
+	move.l	a2,a1			 
+	jsr	ewf
+	ii_shift_typ	w,\2,#1,(a1),(a1).
+ii_0xe\1f3:	
+	move.l	a3,a1			 
+	jsr	ewf
+	ii_shift_typ	w,\2,#1,(a1),(a1).
+ii_0xe\1f4:	
+	move.l	a4,a1			 
+	jsr	ewf
+	ii_shift_typ	w,\2,#1,(a1),(a1).
+ii_0xe\1f5:	
+	move.l	a5,a1			 
+	jsr	ewf
+	ii_shift_typ	w,\2,#1,(a1),(a1).
+ii_0xe\1f6:	
+	move.l	a6,a1			 
+	jsr	ewf
+	ii_shift_typ	w,\2,#1,(a1),(a1).
+ii_0xe\1f7:	
+	move.l	usp,a1			 
+	jsr	ewf
+	ii_shift_typ	w,\2,#1,(a1),(a1).
+// xxx.w xxx.l
+ii_0xe\1f8:	
+	move.w	(a0)+,a1			 
+	ii_shift_typ	w,\2,#1,(a1),(a1).
+ii_0xe\1f9:				 
+	move.l	(a0)+,a1			 
+	ii_shift_typ	w,\2,#1,(a1),(a1).
+.endm
+//============================================================================
+//subroutine
+//------------------------------
+ii_shift_op0:.macro	// shift: 1=code 2=size 3=shift art 4=shift wert 5=ea
+ii_0xe\1:
+	ii_shift_typ	\2,\3,\4,\5,\5
+.endm	
+
+ii_shift_op0b:.macro	// shift wert nach d0 holen: 1=code 2=size 3=shift art 4=shift wert 5=ea
+ii_0xe\1:
+	move.l	\4,d0
+	ii_shift_typ	\2,\3,d0,\5,\5
+.endm	
+
+ii_shift_typ:.macro	//1=size 2=shift art 3=shift wert 4=source 5=dest
+#ifdef	halten
+	halt
+#endif
+.ifc	asr,\2
+	mvs.\1	\4,d1
+.else
+	mvz.\1	\4,d1
+.endif
+.ifc	roxr,\2
+	nop
+.else
+	.ifc	roxl,\2
+		nop
+	.else
+		.ifc	ror,\2
+			nop
+		.else
+			.ifc	rol,\2
+				nop
+			.else
+				\2.l	\3,d1
+			.endif
+		.endif
+	.endif
+.endif
+	set_cc0
+	move.\1	d1,\5
+	ii_end
+.endm
diff --git a/firebeeV1/sources/ii_sub.h b/firebeeV1/sources/ii_sub.h
new file mode 100644
index 0000000..1405e1a
--- /dev/null
+++ b/firebeeV1/sources/ii_sub.h
@@ -0,0 +1,584 @@
+//--------------------------------------------------------------------
+// sub
+//--------------------------------------------------------------------
+/*****************************************************************************************/
+//--------------------------------------------------------------------
+// byt
+//--------------------------------------------------------------------
+//--------------------------------------------------------------------
+// sub.b	#im,dx
+//--------------------------------------------------------------------
+subbir_macro:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	move.w		(a0)+,d0
+	extb.l		d0
+	mvs.b		\2,d1
+	sub.l		d0,d1
+	set_cc0
+	move.b		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // sub	ea,dx
+//--------------------------------------------------------------------
+subdd:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	mvs.\3		\1,d0
+	mvs.\3		\2,d1
+	sub.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // sub	ea(l)->dy(w),dx z.B. für USP
+//--------------------------------------------------------------------
+subddd:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	move.l		\1,a1
+	mvs.\3		a1,d0
+	mvs.\3		\2,d1
+	sub.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // sub	(ea)->dy,dx
+//--------------------------------------------------------------------
+subdda:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	move.l		\1,a1
+	mvs.\3		(a1),d0
+	mvs.\3		\2,d1
+	sub.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // sub	ea->ay,(ay)+,dx
+//--------------------------------------------------------------------
+subddai:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	move.l		\1,a1
+	mvs.\3		(a1)+,d0
+	move.l		a1,\1
+	mvs.\3		\2,d1
+	sub.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // sub	ea->ay,-(ay),dx
+//--------------------------------------------------------------------
+subddad:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	move.l		\1,a1
+	mvs.\3		-(a1),d0
+	move.l		a1,\1
+	mvs.\3		\2,d1
+	sub.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // sub	d16(ay),dx
+//--------------------------------------------------------------------
+subd16ad:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	move.l		\1,a1
+	mvs.w		(a0)+,d0
+	add.l		d0,a1
+	mvs.\3		(a1),d0		
+	mvs.\3		\2,d1
+	sub.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // sub	d8(ay,dy),dx
+//--------------------------------------------------------------------
+subd8ad:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	move.l		\1,a1
+	jsr			ewf
+.ifc	\3,l
+	move.l		(a1),d0
+	move.l		\2,d1
+.else
+	mvs.\3		(a1),d0
+	mvs.\3		\2,d1
+.endif
+	sub.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // sub	xxx.w,dx
+//--------------------------------------------------------------------
+subxwd:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	move.w		(a0)+,a1
+	mvs.\3		(a1),d0
+	mvs.\3		\2,d1
+	sub.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // sub	xxx.l,dx
+//--------------------------------------------------------------------
+subxld:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	move.l		(a0)+,a1
+	mvs.\3		(a1),d0
+	mvs.\3		\2,d1
+	sub.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // sub	d16(pc),dx
+//--------------------------------------------------------------------
+subd16pcd:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	move.l		a0,a1
+	mvs.w		(a0)+,d0
+	add.l		d0,a1
+	mvs.\3		(a1),d0
+	mvs.\3		\2,d1
+	sub.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // sub	d8(pc,dy),dx
+//--------------------------------------------------------------------
+subd8pcd:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	move.l		a0,a1
+	jsr			ewf
+.ifc	\3,l
+	move.l		(a1),d0
+	move.l		\2,d1
+.else
+	mvs.\3		(a1),d0
+	mvs.\3		\2,d1
+.endif
+	sub.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+//  sub dy,ea
+//--------------------------------------------------------------------
+//--------------------------------------------------------------------
+// // sub	(ea)->dy,dx
+//--------------------------------------------------------------------
+subeda:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	mvs.\3		\1,d0
+	move.l		\2,a1
+	mvs.\3		(a1),d1
+	sub.l		d0,d1
+	set_cc0
+	move.\3		d1,(a1)
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // sub	dx,ea->ay,(ay)+
+//--------------------------------------------------------------------
+subedai:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	mvs.\3		\1,d0
+	move.l		\2,a1
+	mvs.\3		(a1),d1
+	sub.l		d0,d1
+	set_cc0
+	move.\3		d1,(a1)+
+	move.l		a1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // sub	dx,ea->ay,(ay)+
+//--------------------------------------------------------------------
+subedaid:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	mvs.\3		\1,d0
+	mvs.\3		\2,d1
+	sub.l		d0,d1
+	set_cc0
+	move.\3		d1,\2+
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // sub	dx,ea->ay,-(ay)
+//--------------------------------------------------------------------
+subedad:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	mvs.\3		\1,d0
+	move.l		\2,a1
+	mvs.\3		-(a1),d1
+	move.l		a1,\2
+	sub.l		d0,d1
+	set_cc0
+	move.\3		d1,(a1)
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // sub	dx,ea->ay,-(ay)
+//--------------------------------------------------------------------
+subedadd:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	mvs.\3		\1,d0
+	mvs.\3		-\2,d1
+	sub.l		d0,d1
+	set_cc0
+	move.\3		d1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // sub	dx,d16(ay)
+//--------------------------------------------------------------------
+sube16ad:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	mvs.\3		\1,d0
+	move.l		\2,a1
+	mvs.w		(a0)+,d1
+	add.l		d1,a1
+	mvs.\3		(a1),d1		
+	sub.l		d0,d1
+	set_cc0
+	move.\3		d1,(a1)
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // sub	dx,d8(ay,dy)
+//--------------------------------------------------------------------
+sube8ad:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	move.l		\2,a1
+	jsr			ewf
+.ifc	\3,l
+	move.l		(a1),d1
+	move.l		\1,d0
+.else
+	mvs.\3		(a1),d1
+	mvs.\3		\1,d0
+.endif
+	sub.l		d0,d1
+	set_cc0
+	move.\3		d1,(a1)
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // sub	dx,xxx.w
+//--------------------------------------------------------------------
+subxwe:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	mvs.\3		\1,d0
+	move.w		(a0)+,a1
+	mvs.\3		(a1),d1
+	sub.l		d0,d1
+	set_cc0
+	move.\3		d1,(a1)
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // sub	dx,xxx.l
+//--------------------------------------------------------------------
+subxle:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	mvs.\3		\1,d0
+	move.l		(a0)+,a1
+	mvs.\3		(a1),d1
+	sub.l		d0,d1
+	set_cc0
+	move.\3		d1,(a1)
+	ii_end
+	.endm;
+/******************************************************/
+// adress register
+/******************************************************/
+//--------------------------------------------------------------------
+// // suba.w	ea,ax
+//--------------------------------------------------------------------
+subaw:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	move.l		a0,pc_off(a7)			// pc auf next
+	movem.l		(a7),d0/d1/a0/a1		// register zurpück
+	mvs.w		\1,d0
+	suba.l		d0,\2
+	move.l		d0_off(a7),d0
+	lea			ii_ss(a7),a7			// stack erhöhen
+	rte
+	.endm;
+//--------------------------------------------------------------------
+// sub.w ea,usp
+//--------------------------------------------------------------------
+subawa7:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	mvs.w		\1,d0
+	move.l		usp,a1
+	sub.l		d0,a1
+	move.l		a1,usp
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // suba.w	usp?,ax
+//--------------------------------------------------------------------
+subawu:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	move.l		a0,pc_off(a7)			// pc auf next
+	movem.l		(a7),d0/d1/a0/a1		// register zurpück
+	move.l		a7,_a7_save
+	move.l		usp,a7
+	move.l		\1,d0
+	suba.l		d0,\2
+	move.l		a7,usp
+	move.l		_a7_save,a7
+	move.l		d0_off(a7),d0
+	lea			ii_ss(a7),a7			// stack erhöhen
+	rte
+	.endm;
+//--------------------------------------------------------------------
+// // suba.w	usp?,usp
+//--------------------------------------------------------------------
+subawua7:.macro
+	subawu		\1,\2
+	.endm;
+//--------------------------------------------------------------------
+// // suba.w	d16(ay),ax
+//--------------------------------------------------------------------
+subawd16a:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	move.l		\1,a1
+	mvs.w		(a0)+,d0
+	adda.l		d0,a1
+	mvs.w		(a1),d0
+	move.l		\2,a1
+	sub.l		d0,a1
+	move.l		a1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // suba.w	d8(ay,dy),ax
+//--------------------------------------------------------------------
+subawd8a:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	move.l		\1,a1
+	jsr			ewf
+	mvs.w		(a1),d0
+	move.l		\2,a1
+	sub.l		d0,a1
+	move.l		a1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // suba.w	xxx.w,ax
+//--------------------------------------------------------------------
+subawxwax:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	move.w		(a0)+,a1
+	mvs.w		(a1),d0
+	move.l		\2,a1
+	suba.l		d0,a1
+	move.l		a1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // suba.w	xxx.l,ax
+//--------------------------------------------------------------------
+subawxlax:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	move.l		(a0)+,a1
+	mvs.w		(a1),d0
+	move.l		\2,a1
+	suba.l		d0,a1
+	move.l		a1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // suba.w	d16(pc),ax
+//--------------------------------------------------------------------
+subawd16pcax:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	move.w		(a0)+,a1
+	adda.l		a0,a1
+	mvs.w		(a1),d0
+	move.l		\2,a1
+	suba.l		d0,a1
+	move.l		a1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // suba.w	d8(pc,dy),ax
+//--------------------------------------------------------------------
+subawd8pcax:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	move.l		a0,a1
+	jsr			ewf
+	mvs.w		(a1),d0
+	move.l		\2,a1
+	sub.l		d0,a1
+	move.l		a1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // suba.w	#im,ax
+//--------------------------------------------------------------------
+subawim:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	mvs.w		\1,d0
+	move.l		\2,a1
+	sub.l		d0,a1
+	move.l		a1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // suba.l	d8(ay,dy),ax
+//--------------------------------------------------------------------
+subald8a:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	move.l		\1,a1
+	jsr			ewf
+	move.l		(a1),d0
+	move.l		\2,a1
+	sub.l		d0,a1
+	move.l		a1,\2
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // suba.l	d8(pc,dy),ax
+//--------------------------------------------------------------------
+subakd8pcax:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	move.l		a0,a1
+	jsr			ewf
+	move.l		(a1),d0
+	move.l		\2,a1
+	sub.l		d0,a1
+	move.l		a1,\2
+	ii_end
+	.endm;
+//*****************************************************************************************
+// subx 
+//*****************************************************************************************
+//--------------------------------------------------------------------
+// // subx	dy,dx
+//--------------------------------------------------------------------
+subdx:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	move.b		sr_off+1(a7),d0			//ccr holen
+	move		d0,ccr					//setzen		
+	mvs.\3		\2,d0
+	mvs.\3		\1,d1
+	subx.l		d0,d1
+	set_cc0
+	move.\3		d1,\1
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
+// // subx	-(ay),-(ax)
+//--------------------------------------------------------------------
+subdax:.macro
+#ifdef	halten_sub
+	halt
+#endif
+	move.b		sr_off+1(a7),d0			//ccr holen
+	move		d0,ccr					//setzen		
+	move.l		\1,a1
+.ifc	\3,l
+	move.l		-(a1),d0
+.else
+	mvs.\3		-(a1),d0
+.endif
+	move.l		\2,a1
+.ifc	\3,l
+	move.l		-(a1),d0
+.else
+	mvs.\3		-(a1),d1
+.endif
+	subx.l		d0,d1
+	set_cc0
+	move.\3		d1,(a1)
+	ii_end
+	.endm;
+//--------------------------------------------------------------------
diff --git a/firebeeV1/sources/illegal_instruction.s b/firebeeV1/sources/illegal_instruction.s
new file mode 100644
index 0000000..21461b3
--- /dev/null
+++ b/firebeeV1/sources/illegal_instruction.s
@@ -0,0 +1,328 @@
+.public 	_illegal_instruction
+.public 	_illegal_table_make
+
+.include 	"startcf.h"
+.include	"ii_macro.h"
+.include	"ii_func.h"
+.include	"ii_op.h"
+.include	"ii_opc.h"
+.include	"ii_add.h"
+.include	"ii_sub.h"
+.include	"ii_or.h"
+.include	"ii_and.h"
+.include	"ii_dbcc.h"
+.include	"ii_shd.h"
+.include	"ii_movem.h"
+.include	"ii_lea.h"
+.include	"ii_shift.h"
+.include	"ii_exg.h"
+.include	"ii_movep.h"
+.include	"ii_ewf.h"
+.include	"ii_move.h"
+
+.extern		_ii_shift_vec
+.extern		ewf
+
+/*******************************************************/
+.text
+ii_error:
+	nop
+	halt
+	nop
+	nop
+	
+_illegal_instruction:
+#ifdef	ii_on
+	move.w		#0x2700,sr
+	lea			-ii_ss(a7),a7
+	movem.l		d0/d1/a0/a1,(a7)
+	move.l		pc_off(a7),a0			// pc
+	mvz.w		(a0)+,d0				// code
+	lea			table,a1
+	move.l		0(a1,d0*4),a1
+	jmp			(a1)
+/*************************************************************************************************/
+#endif
+_illegal_table_make:
+#ifdef	ii_on
+	lea			table,a0
+	moveq		#0,d0
+_itm_loop:
+	move.l		#ii_error,(a0)+
+	addq.l		#1,d0
+	cmp.l		#0xF000,d0
+	bne			_itm_loop
+//-------------------------------------------------------------------------
+	ii_ewf_lset		// diverse fehlende adressierungn
+//-------------------------------------------------------------------------
+// 0x0000 
+// ori
+	ii_lset_op	00
+// andi
+	ii_lset_op	02
+// subi
+	ii_lset_op	04
+// addi
+	ii_lset_op	06
+// eori
+	ii_lset_op	0a
+// cmpi
+	ii_lset_op	0c
+// movep
+	ii_movep_lset	
+//-------------------------------------------------------------------------
+// 0x1000 move.b
+// 0x2000 move.l
+// 0x3000 move.w
+	ii_move_lset
+//-------------------------------------------------------------------------
+// 0x4000 
+//-------------------------------------------------------------------------
+// negx
+	ii_lset_op	40
+// neg
+	ii_lset_op	44
+// not
+	ii_lset_op	46
+//---------------------------------------------------------------------------------------------
+// lea	d8(ax,dy.w),az; d8(pc,dy.w),az
+//-------------------------------------------------------------------
+	ii_lea_lset
+//-------------------------------------------------------------------
+// movem 
+//-------------------------------------------------------------------
+	ii_movem_lset
+//-------------------------------------------------------------------------
+// 0x5000
+//-------------------------------------------------------------------------
+// addq, subq
+	ii_lset_op	50
+	ii_lset_op	51
+	ii_lset_op	52
+	ii_lset_op	53
+	ii_lset_op	54
+	ii_lset_op	55
+	ii_lset_op	56
+	ii_lset_op	57
+	ii_lset_op	58
+	ii_lset_op	59
+	ii_lset_op	5a
+	ii_lset_op	5b
+	ii_lset_op	5c
+	ii_lset_op	5d
+	ii_lset_op	5e
+	ii_lset_op	5f
+// dbcc
+	ii_lset_dbcc
+// scc
+	ii_lset_opc	50
+	ii_lset_opc	51
+	ii_lset_opc	52
+	ii_lset_opc	53
+	ii_lset_opc	54
+	ii_lset_opc	55
+	ii_lset_opc	56
+	ii_lset_opc	57
+	ii_lset_opc	58
+	ii_lset_opc	59
+	ii_lset_opc	5a
+	ii_lset_opc	5b
+	ii_lset_opc	5c
+	ii_lset_opc	5d
+	ii_lset_opc	5e
+	ii_lset_opc	5f
+//-------------------------------------------------------------------------
+// 0x8000		or
+//-------------------------------------------------------------------------
+	ii_lset_func	8
+//-------------------------------------------------------------------------
+// 0x9000		sub
+//-------------------------------------------------------------------------
+	ii_lset_func	9
+//-------------------------------------------------------------------------
+// 0xb000		
+//-------------------------------------------------------------------------
+// eor
+	ii_lset_op	b1
+	ii_lset_op	b3
+	ii_lset_op	b5
+	ii_lset_op	b7
+	ii_lset_op	b9
+	ii_lset_op	bb
+	ii_lset_op	bd
+	ii_lset_op	bf
+//-------------------------------------------------------------------------
+// 0xc000		
+//-------------------------------------------------------------------------
+// and
+	ii_lset_func	c
+// exg
+	ii_exg_lset
+//-------------------------------------------------------------------------
+// 0xd000		add
+//-------------------------------------------------------------------------
+	ii_lset_func	d
+//-------------------------------------------------------------------------
+// 0xe000
+//-------------------------------------------------------------------------
+// shift register
+	ii_shift_lset	e	
+//-------------------------------------------------
+// differenz zwischen orginal und gemoved korrigieren
+	lea			ii_error(pc),a1
+	move.l		a1,d1
+	sub.l		#ii_error,d1
+	lea			table,a0
+	moveq		#0,d0
+_itkorr_loop:
+	add.l		d1,(a0)+
+	addq.l		#1,d0
+	cmp.l		#0xF000,d0
+	bne			_itkorr_loop
+#endif
+	rts
+#ifdef	ii_on
+//***********************************************************************************/
+//-------------------------------------------------------------------------
+		ii_ewf_func		// diverse fehlende adressierungn
+//-------------------------------------------------------------------------
+//---------------------------------------------------------------------------------------------
+// 0x0000
+//--------------------------------------------------------------------
+// ori 00
+		ii_op		00,or.l,i
+//--------------------------------------------------------------------
+// andi 02
+		ii_op		02,and.l,i
+//--------------------------------------------------------------------
+// subi 04
+		ii_op		04,and.l,i
+//--------------------------------------------------------------------
+// addi 06
+		ii_op		06,add.l,i
+//--------------------------------------------------------------------
+// eori 0a
+		ii_op		0a,eor.l,i
+//--------------------------------------------------------------------
+// cmpi 0c
+		ii_op		0c,cmp.l,i
+//--------------------------------------------------------------------
+// movep
+	ii_movep_func	
+///---------------------------------------------------------------------------------------------
+// 0x1000 move.b
+// 0x2000 move.l	
+// 0x3000 move.w
+		ii_move_op
+//---------------------------------------------------------------------------------------------
+// 0x4000
+//---------------------------------------------------------------------------------------------
+// neg 0x40..
+		ii_op		40,negx.l,n
+//---------------------------------------------------------------------------------------------
+// neg 0x44..
+		ii_op		44,neg.l,n
+//---------------------------------------------------------------------------------------------
+// not 0x46..
+		ii_op		46,not.l,n
+//---------------------------------------------------------------------------------------------
+// lea	d8(ax,dy.w),az; d8(pc,dy.w),az
+//-------------------------------------------------------------------
+		ii_lea_func
+//-------------------------------------------------------------------
+// movem
+//--------------------------------------------------------------------
+ii_movem_func
+//---------------------------------------------------------------------------------------------
+// 0x5000
+//---------------------------------------------------------------------------------------------
+//dbcc
+		ii_dbcc_func
+// addq 0x5...
+		ii_op		50,addq.l #8,q
+		ii_op		52,addq.l #1,q
+		ii_op		54,addq.l #2,q
+		ii_op		56,addq.l #3,q
+		ii_op		58,addq.l #4,q
+		ii_op		5a,addq.l #5,q
+		ii_op		5c,addq.l #6,q
+		ii_op		5e,addq.l #7,q
+//---------------------------------------------------------------------------------------------
+// subq 0x5...
+		ii_op		51,subq.l #8,q
+		ii_op		53,subq.l #1,q
+		ii_op		55,subq.l #2,q
+		ii_op		57,subq.l #3,q
+		ii_op		59,subq.l #4,q
+		ii_op		5b,subq.l #5,q
+		ii_op		5d,subq.l #6,q
+		ii_op		5f,subq.l #7,q
+//---------------------------------------------------------------------------------------------
+// 0x5... scc
+		ii_opc		50,st,c
+		ii_opc		51,sf,c
+		ii_opc		52,shi,c
+		ii_opc		53,sls,c
+		ii_opc		54,scc,c
+		ii_opc		55,scs,c
+		ii_opc		56,sne,c
+		ii_opc		57,seq,c
+		ii_opc		58,svc,c
+		ii_opc		59,svs,c
+		ii_opc		5a,spl,c
+		ii_opc		5b,smi,c
+		ii_opc		5c,sge,c
+		ii_opc		5d,slt,c
+		ii_opc		5e,sgt,c
+		ii_opc		5f,sle,c
+//---------------------------------------------------------------------------------------------
+// 0x6000
+//--------------------------------------------------------------------
+//---------------------------------------------------------------------------------------------
+// 0x7000
+//--------------------------------------------------------------------
+//---------------------------------------------------------------------------------------------
+// 0x8000
+//---------------------------------------------------------------------------------------------
+// or
+		ii_func		8,or
+//---------------------------------------------------------------------------------------------
+// 0x9000
+//---------------------------------------------------------------------------------------------
+// sub
+		ii_func		9,sub
+//---------------------------------------------------------------------------------------------
+// 0xa000
+//--------------------------------------------------------------------
+//---------------------------------------------------------------------------------------------
+// 0xb000
+//---------------------------------------------------------------------------------------------
+// eor
+		ii_op		b1,eor.l d0,q
+		ii_op		b3,eor.l d1,q
+		ii_op		b5,eor.l d2,q
+		ii_op		b7,eor.l d3,q
+		ii_op		b9,eor.l d4,q
+		ii_op		bb,eor.l d5,q
+		ii_op		bd,eor.l d6,q
+		ii_op		bf,eor.l d7,q
+//---------------------------------------------------------------------------------------------
+// 0xc000
+//---------------------------------------------------------------------------------------------
+// and
+		ii_func		c,and
+// exg
+		ii_exg_func
+//---------------------------------------------------------------------------------------------
+// 0xd000
+//---------------------------------------------------------------------------------------------
+// add
+		ii_func		d,add
+//---------------------------------------------------------------------------------------------
+// 0xe000 shift
+//--------------------------------------------------------------------
+		ii_shift_op
+//--------------------------------------------------------------------
+// 0xf000
+//--------------------------------------------------------------------
+#endif
\ No newline at end of file
diff --git a/firebeeV1/sources/last.c b/firebeeV1/sources/last.c
new file mode 100644
index 0000000..0cb3a3e
--- /dev/null
+++ b/firebeeV1/sources/last.c
@@ -0,0 +1,11 @@
+// letztes file der liste
+// wichtig als endpunkt des kopierens
+
+void copy_end(void)
+{
+	asm
+	{
+copy_end:
+		nop
+	}
+}
\ No newline at end of file
diff --git a/firebeeV1/sources/last.s b/firebeeV1/sources/last.s
new file mode 100644
index 0000000..c9dfe7a
--- /dev/null
+++ b/firebeeV1/sources/last.s
@@ -0,0 +1,10 @@
+// letztes file der liste
+// wichtig als endpunkt des kopierens
+
+.global	copy_end
+
+.text
+	nop
+copy_end:
+	nop
+.asciz	'ende copy';
\ No newline at end of file
diff --git a/firebeeV1/sources/macro.h b/firebeeV1/sources/macro.h
new file mode 100644
index 0000000..2afa44e
--- /dev/null
+++ b/firebeeV1/sources/macro.h
@@ -0,0 +1,10 @@
+/*******************************************************/
+// allgemeine macros
+/*******************************************************/
+.text
+wait_pll: .macro
+wait1_pll\@:
+		tst.w	(a1)
+		bmi		wait1_pll\@
+		rts
+.endm
diff --git a/firebeeV1/sources/mmu.s b/firebeeV1/sources/mmu.s
new file mode 100644
index 0000000..0d3fade
--- /dev/null
+++ b/firebeeV1/sources/mmu.s
@@ -0,0 +1,196 @@
+/********************************************************************/
+	/* INIT ACR und MMU /*
+/********************************************************************/
+
+.include "startcf.h"
+
+.extern _rt_vbr
+.extern _rt_cacr
+.extern _rt_asid
+.extern _rt_acr0
+.extern _rt_acr1
+.extern _rt_acr2
+.extern _rt_acr3
+.extern _rt_mmubar
+.extern ___MMUBAR
+.extern cpusha
+.extern _video_tlb
+.extern _video_sbt
+
+/* Register read/write macros */
+#define MCF_MMU_MMUCR            			___MMUBAR
+#define MCF_MMU_MMUOR                       ___MMUBAR+0x04
+#define MCF_MMU_MMUSR                       ___MMUBAR+0x08
+#define MCF_MMU_MMUAR                       ___MMUBAR+0x10
+#define MCF_MMU_MMUTR                       ___MMUBAR+0x14
+#define MCF_MMU_MMUDR                       ___MMUBAR+0x18
+
+
+/* Bit definitions and macros for MCF_MMU_MMUCR */
+#define MCF_MMU_MMUCR_EN                     (0x1)
+#define MCF_MMU_MMUCR_ASM                    (0x2)
+
+/* Bit definitions and macros for MCF_MMU_MMUOR */
+#define MCF_MMU_MMUOR_UAA                    (0x1)
+#define MCF_MMU_MMUOR_ACC                    (0x2)
+#define MCF_MMU_MMUOR_RW                     (0x4)
+#define MCF_MMU_MMUOR_ADR                    (0x8)
+#define MCF_MMU_MMUOR_ITLB                   (0x10)
+#define MCF_MMU_MMUOR_CAS                    (0x20)
+#define MCF_MMU_MMUOR_CNL                    (0x40)
+#define MCF_MMU_MMUOR_CA                     (0x80)
+#define MCF_MMU_MMUOR_STLB                   (0x100)
+#define MCF_MMU_MMUOR_AA(x)                  (((x)&0xFFFF)<<0x10)
+
+/* Bit definitions and macros for MCF_MMU_MMUSR */
+#define MCF_MMU_MMUSR_HIT                    (0x2)
+#define MCF_MMU_MMUSR_WF                     (0x8)
+#define MCF_MMU_MMUSR_RF                     (0x10)
+#define MCF_MMU_MMUSR_SPF                    (0x20)
+
+/* Bit definitions and macros for MCF_MMU_MMUAR */
+#define MCF_MMU_MMUAR_FA(x)                  (((x)&0xFFFFFFFF)<<0)
+
+/* Bit definitions and macros for MCF_MMU_MMUTR */
+#define MCF_MMU_MMUTR_V                      (0x1)
+#define MCF_MMU_MMUTR_SG                     (0x2)
+#define MCF_MMU_MMUTR_ID(x)                  (((x)&0xFF)<<0x2)
+#define MCF_MMU_MMUTR_VA(x)                  (((x)&0x3FFFFF)<<0xA)
+
+/* Bit definitions and macros for MCF_MMU_MMUDR */
+#define MCF_MMU_MMUDR_LK                     (0x2)
+#define MCF_MMU_MMUDR_X                      (0x4)
+#define MCF_MMU_MMUDR_W                      (0x8)
+#define MCF_MMU_MMUDR_R                      (0x10)
+#define MCF_MMU_MMUDR_SP                     (0x20)
+#define MCF_MMU_MMUDR_CM(x)                  (((x)&0x3)<<0x6)
+#define MCF_MMU_MMUDR_SZ(x)                  (((x)&0x3)<<0x8)
+#define MCF_MMU_MMUDR_PA(x)                  (((x)&0x3FFFFF)<<0xA)
+
+#define	 std_mmutr	(MCF_MMU_MMUTR_SG|MCF_MMU_MMUTR_V)
+#define	 mmuord_d	(                   MCF_MMU_MMUOR_ACC|MCF_MMU_MMUOR_UAA)
+#define	 mmuord_i	(MCF_MMU_MMUOR_ITLB|MCF_MMU_MMUOR_ACC|MCF_MMU_MMUOR_UAA)
+#define	 wt_mmudr	(MCF_MMU_MMUDR_SZ(00)|MCF_MMU_MMUDR_CM(00)|MCF_MMU_MMUDR_R|MCF_MMU_MMUDR_W|MCF_MMU_MMUDR_X)
+#define	 cb_mmudr	(MCF_MMU_MMUDR_SZ(00)|MCF_MMU_MMUDR_CM(01)|MCF_MMU_MMUDR_R|MCF_MMU_MMUDR_W|MCF_MMU_MMUDR_X)
+#define	 nc_mmudr	(MCF_MMU_MMUDR_SZ(00)|MCF_MMU_MMUDR_CM(10)|MCF_MMU_MMUDR_R|MCF_MMU_MMUDR_W|MCF_MMU_MMUDR_X)
+
+.public _mmu_init
+.public _mmutr_miss
+
+.text
+_mmu_init:
+ 		clr.l	d0
+		movec	d0,ASID				// ASID allways 0
+		move.l	d0,_rt_asid			// sichern
+		movec	d0,cacr				// cache aus
+		move.l	d0,_rt_cacr			// sichern
+		nop
+		
+		move.l	#0xC03FC040,d0		// data r/w precise  c000'0000-ffff'ffff
+		movec	d0,ACR0
+		move.l	d0,_rt_acr0			// sichern
+		
+		move.l	#0x601FC000,d0		// data r/w wt 6000'0000-7fff'ffff
+		movec	d0,ACR1
+		move.l	d0,_rt_acr1			// sichern
+		
+		move.l	#0xe007C400,d0		// instruction r wt e000'0000-e07f'ffff
+		movec	d0,ACR2
+		move.l	d0,_rt_acr2			// sichern
+
+		clr.l	d0					// acr3 aus
+		movec	d0,ACR3
+		move.l	d0,_rt_acr3			// sichern
+
+		move.l	#___MMUBAR+1,d0	
+		movec	d0,MMUBAR			//mmubar setzen
+		move.l	d0,_rt_mmubar		// sichern
+		
+		nop
+		
+		move.l	#MCF_MMU_MMUOR_CA,d0	// clear all entries, 
+		move.l	d0,MCF_MMU_MMUOR		
+		nop
+// 0000'0000 locked
+  		moveq.l	#0x00000000|std_mmutr,d0
+  		moveq.l	#0x00000000|cb_mmudr|MCF_MMU_MMUDR_LK,d1						 
+		moveq.l	#mmuord_d,d2								// MMU update date
+		moveq.l	#mmuord_i,d3								// MMU update instruction
+ 		move.l	d0,MCF_MMU_MMUTR		
+ 		move.l	d1,MCF_MMU_MMUDR
+ 		move.l	d2,MCF_MMU_MMUOR						// MMU update date
+ 		move.l	d3,MCF_MMU_MMUOR						// MMU update instruction
+
+//---------------------------------------------------------------------------------------
+// 00d0'0000 locked ID=6
+// video ram: read write execute normal write true
+ 		move.l	#0x00d00000|MCF_MMU_MMUTR_ID(sca_page_ID)|std_mmutr,d0
+		move.l	#0x60d00000|wt_mmudr|MCF_MMU_MMUDR_LK,d1						 
+		move.l	d0,MCF_MMU_MMUTR		
+		move.l	d1,MCF_MMU_MMUDR
+		move.l	d2,MCF_MMU_MMUOR						// MMU update date
+ 		move.l	#0x00d00000|std_mmutr,d0
+		move.l	d3,MCF_MMU_MMUOR						// MMU update instruction  
+		
+		move.l	#0x2000,d0
+		move.l	d0,_video_tlb							// setze page als video page
+  		clr.l	_video_sbt			// zeit löschen
+//-------------------------------------------------------------------------------------
+// 00e0'0000 locked		
+ 		move.l	#0x00e00000|std_mmutr,d0
+		move.l	#0x00e00000|cb_mmudr|MCF_MMU_MMUDR_LK,d1						 
+		move.l	d0,MCF_MMU_MMUTR		
+		move.l	d1,MCF_MMU_MMUDR
+ 		move.l	d2,MCF_MMU_MMUOR						// setzen read only ?????? noch nicht
+		move.l	d3,MCF_MMU_MMUOR						// setzen
+// 00f0'0000 locked		
+		move.l	#0x00f00000|std_mmutr,d0
+		move.l	#0xfff00000|nc_mmudr|MCF_MMU_MMUDR_LK,d1						 
+		move.l	d0,MCF_MMU_MMUTR		
+		move.l	d1,MCF_MMU_MMUDR
+		move.l	d2,MCF_MMU_MMUOR						// maped to ffffxxx, precise,  
+		move.l	d3,MCF_MMU_MMUOR						// maped to ffffxxx, precise,  
+// 1fe0'0000 locked
+		move.l	#0x1FE00000|std_mmutr,d0
+		move.l	#0x1FE00000|cb_mmudr|MCF_MMU_MMUDR_LK,d1						 
+		move.l	d0,MCF_MMU_MMUTR		
+		move.l	d1,MCF_MMU_MMUDR
+		move.l	d2,MCF_MMU_MMUOR						// setzen data
+		move.l	d3,MCF_MMU_MMUOR						// setzen instr
+// 1ff0'0000 locked
+		move.l	#0x1FF00000|std_mmutr,d0
+		move.l	#0x1FF00000|cb_mmudr|MCF_MMU_MMUDR_LK,d1						 
+		move.l	d0,MCF_MMU_MMUTR		
+		move.l	d1,MCF_MMU_MMUDR
+		move.l	d2,MCF_MMU_MMUOR						// setzen data
+		move.l	d3,MCF_MMU_MMUOR						// setzen instr 
+// instr 0xFFF0'0000 nach 0x1FF0'0000 umleiten -->> short sprung 
+/*		move.l	#0xFFF00000|std_mmutr,d0
+		move.l	#0x1FF00000|cb_mmudr|MCF_MMU_MMUDR_LK,d1						 
+		move.l	d0,MCF_MMU_MMUTR		
+		move.l	d1,MCF_MMU_MMUDR
+		move.l	d3,MCF_MMU_MMUOR						// setzen instr
+*/
+		move.l	#0xa10ca120,d0
+		move.l	d0,_rt_cacr								// sichern
+ 		movec	d0,cacr
+		nop
+		rts
+
+/********************************************************************/
+	/* MMU table search /*
+/********************************************************************/
+_mmutr_miss:
+		bsr		cpusha
+		and.l	#0xFFF00000,d0
+		or.l	#std_mmutr,d0	
+		move.l	d0,MCF_MMU_MMUTR
+		and.l	#0xFFF00000,d0
+		or.l	#cb_mmudr,d0		
+		move.l	d0,MCF_MMU_MMUDR
+		moveq.l	#mmuord_d,d0					// MMU update data
+		move.l	d0,MCF_MMU_MMUOR				// setzen  
+		moveq.l	#mmuord_i,d0					// MMU update instruction
+		move.l	d0,MCF_MMU_MMUOR				// setzen  
+		move.l	(sp)+,d0
+		rte
diff --git a/firebeeV1/sources/movem.h b/firebeeV1/sources/movem.h
new file mode 100644
index 0000000..b79349d
--- /dev/null
+++ b/firebeeV1/sources/movem.h
@@ -0,0 +1,256 @@
+// movem
+_ii_movem_lset: .macro
+// movem rx,xxx.L
+	ii_lset		0x48f9
+// movem rx,-(ax)
+	
+// movem (ax)+,rx
+	ii_lset		0x4cd8
+	ii_lset		0x4cd9
+	ii_lset		0x4cda
+	ii_lset		0x4cdb
+	ii_lset		0x4cdc
+	ii_lset		0x4cdd
+	ii_lset		0x4cde
+	ii_lset		0x4cdf
+// movem xxx.L,rx
+	ii_lset		0x4cf9
+.endm
+//***********************************************************************************/
+_ii_movem_func: .macro
+//-------------------------------------------------------------------
+// movem.l
+//--------------------------------------------------------------------
+// movem.l (ax)+,reg
+//--------------------------------------------------------------------
+//-------------------------------------------------------------------------------
+ii_0x4cd8:		// movem.l (a0)+,reglist
+	mvm_macro	0x4cd0,0x41e8,2
+ii_0x4cd9:		// movem.l (a1)+,reglist
+	mvm_macro	0x4cd1,0x43e9,2
+ii_0x4cda:		// movem.l (a2)+,reglist
+	mvm_macro	0x4cd2,0x45ea,2
+ii_0x4cdb:		// movem.l (a3)+,reglist
+	mvm_macro	0x4cd3,0x47eb,2
+ii_0x4cdc:		// movem.l (a4)+,reglist
+	mvm_macro	0x4cd4,0x49ec,2
+ii_0x4cdd:		// movem.l (a5)+,reglist
+	mvm_macro	0x4cd5,0x4bed,2
+ii_0x4cde:		// movem.l (a6)+,reglist
+	mvm_macro	0x4cd6,0x4dee,2
+ii_0x4cdf:		// movem.l (a7)+,reglist
+	mvm_macro	0x4cd7,0x4fef,2
+//----------------------------------------------------------------------------
+ii_0x48f9:		// movem.l reg,xxx.L
+		move.w		(a0)+,d0
+		move.l		(a0)+,a1
+		movemrm_macro
+		ii_end
+//---------------------------------------------------------------------------------------------
+ii_0x4cf9:		// movem.l xxx.L,reg
+		move.w		(a0)+,d0
+		move.l		(a0)+,a1
+		movemmr_macro
+		ii_end
+.endm
+//==============================================================
+mvm_macro:.macro
+halt
+	lea			az_reg_table,a1
+	mvz.b		(a0),d1
+	mvz.b		0(a1,d1)+,d0
+	mvz.b		1(a0),d1
+	mvz.b		0(a1,d1)+,d1
+	add.l		d0,d1
+	lea			___RAMBAR1,a1
+	move.l		a1,pc_off(a7)
+	move.l		a1,d0
+	addq.l		#1,d0
+   	movec      	d0,RAMBAR1
+	move.w		#\1,(a1)+			// movem.x (ax),reg_list
+	move.w		(a0)+,(a1)+			// register list
+	move.w		#\2,(a1)+			// lea 0(ax),ax
+	lsl.l		#\3,d1				// * anzahl byts pro wert
+	move.w		d1,(a1)+			// offset von lea
+	move.w		#0x4ef9,(a1)+		// jmp.l
+	move.l		a0,(a1)				// rücksprungadresse
+   	move.l 		#___RAMBAR1 + 0x81,d0	// instruction
+   	movec      	d0,RAMBAR1
+	movem.l		(a7),d0/d1/a0/a1
+	lea			ii_ss(a7),a7		// stack erhöhen
+	rte
+	.endm
+	.long		0
+az_reg_table:
+	.byte		0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4		// 0-f
+	.byte		1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5		// 10-1f
+	.byte		1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5		// 20-2f
+	.byte		2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6		// 30-3f
+	.byte		1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5		// 40-4f
+	.byte		2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6		// 50
+	.byte		2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6		// 60
+	.byte		3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7		// 70
+	.byte		1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5		// 80-8f
+	.byte		2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6		// 90
+	.byte		2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6		// a0
+	.byte		3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7		// b0
+	.byte		2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6		// c0
+	.byte		3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7		// d0
+	.byte		3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7		// e0
+	.byte		4,5,5,6,5,6,6,7,5,6,6,7,6,7,7,8		// f0
+//---------------------------------------------------------------------------------
+movemrm_macro:.macro				// in d0 register liste, in a1 zieladresse
+halt
+		tst.b	d0					// datenregister zu verschieben?
+		bne		mrm_dx				// ja->
+		lsr.l	#8,d0				// sonst zu addressregister
+		jmp		mmrm_nd7			// ->
+mrm_dx:
+		lsr.l	#1,d0
+		bcc		mmrm_nd0
+		move.l	d0_off(a7),(a1)+
+mmrm_nd0:
+		lsr.l	#1,d0
+		bcc		mmrm_nd1
+		move.l	d1_off(a7),(a1)+
+mmrm_nd1:
+		lsr.l	#1,d0
+		bcc		mmrm_nd2
+		move.l	d2,(a1)+
+mmrm_nd2:
+		lsr.l	#1,d0
+		bcc		mmrm_nd3
+		move.l	d3,(a1)+
+mmrm_nd3:
+		lsr.l	#1,d0
+		bcc		mmrm_nd4
+		move.l	d4,(a1)+
+mmrm_nd4:
+		lsr.l	#1,d0
+		bcc		mmrm_nd5
+		move.l	d5,(a1)+
+mmrm_nd5:
+		lsr.l	#1,d0
+		bcc		mmrm_nd6
+		move.l	d6,(a1)+
+mmrm_nd6:
+		lsr.l	#1,d0
+		bcc		mmrm_nd7
+		move.l	d7,(a1)+
+mmrm_nd7:
+		tst.b	d0					// addressregister zu verschieben?
+		beq		mmrm_na7
+		lsr.l	#1,d0
+		bcc		mmrm_na0
+		move.l	a0_off(a7),(a1)+
+mmrm_na0:
+		lsr.l	#1,d0
+		bcc		mmrm_na1
+		move.l	a1_off(a7),(a1)+
+mmrm_na1:
+		lsr.l	#1,d0
+		bcc		mmrm_na2
+		move.l	a2,(a1)+
+mmrm_na2:
+		lsr.l	#1,d0
+		bcc		mmrm_na3
+		move.l	a3,(a1)+
+mmrm_na3:
+		lsr.l	#1,d0
+		bcc		mmrm_na4
+		move.l	a4,(a1)+
+mmrm_na4:
+		lsr.l	#1,d0
+		bcc		mmrm_na5
+		move.l	a5,(a1)+
+mmrm_na5:
+		lsr.l	#1,d0
+		bcc		mmrm_na6
+		move.l	a6,(a1)+
+mmrm_na6:
+		lsr.l	#1,d0
+		bcc		mmrm_na7
+		move.l	a0,d1		// sichern
+		move.l	usp,a0		// ist ja usp
+		move.l	a0,(a1)+	// nach a0
+		move.l	d1,a0		// pc zurück
+mmrm_na7:
+		.endm
+//---------------------------------------------------------------------------------------------
+movemmr_macro:.macro				// in d0 register liste, in a1 source adr
+halt
+		tst.b	d0					// datenregister zu verschieben?
+		bne		mmr_dx				// ja->
+		lsr.l	#8,d0				// sonst zu addressregister
+		bra		mmmr_nd7			// ->
+mmr_dx:
+		lsr.l	#1,d0
+		bcc		mmmr_nd0
+		move.l	(a1)+,d0_off(a7)
+mmmr_nd0:
+		lsr.l	#1,d0
+		bcc		mmmr_nd1
+		move.l	(a1)+,d1_off(a7)
+mmmr_nd1:
+		lsr.l	#1,d0
+		bcc		mmmr_nd2
+		move.l	(a1)+,d2
+mmmr_nd2:
+		lsr.l	#1,d0
+		bcc		mmmr_nd3
+		move.l	(a1)+,d3
+mmmr_nd3:
+		lsr.l	#1,d0
+		bcc		mmmr_nd4
+		move.l	(a1)+,d4
+mmmr_nd4:
+		lsr.l	#1,d0
+		bcc		mmmr_nd5
+		move.l	(a1)+,d5
+mmmr_nd5:
+		lsr.l	#1,d0
+		bcc		mmmr_nd6
+		move.l	(a1)+,d6
+mmmr_nd6:
+		lsr.l	#1,d0
+		bcc		mmmr_nd7
+		move.l	(a1)+,d7
+mmmr_nd7:
+		tst.b	d0					// addressregister zu verschieben?
+		beq		mmmr_na7			// nein->
+		lsr.l	#1,d0
+		bcc		mmmr_na0
+		move.l	(a1)+,a0_off(a7)
+mmmr_na0:
+		lsr.l	#1,d0
+		bcc		mmmr_na1
+		move.l	(a1)+,a1_off(a7)
+mmmr_na1:
+		lsr.l	#1,d0
+		bcc		mmmr_na2
+		move.l	(a1)+,a2
+mmmr_na2:
+		lsr.l	#1,d0
+		bcc		mmmr_na3
+		move.l	(a1)+,a3
+mmmr_na3:
+		lsr.l	#1,d0
+		bcc		mmmr_na4
+		move.l	(a1)+,a4
+mmmr_na4:
+		lsr.l	#1,d0
+		bcc		mmmr_na5
+		move.l	(a1)+,a5
+mmmr_na5:
+		lsr.l	#1,d0
+		bcc		mmmr_na6
+		move.l	(a1)+,a6
+mmmr_na6:
+		lsr.l	#1,d0
+		bcc		mmmr_na7
+		move.l	a0,d1		// sichern
+		move.l	(a1)+,a0	// nach a0
+		move.l	a0,usp		// war ja usp
+		move.l	d1,a0		// pc zurück
+mmmr_na7:
+		.endm		
diff --git a/firebeeV1/sources/sd_card.c b/firebeeV1/sources/sd_card.c
new file mode 100644
index 0000000..58c48bd
--- /dev/null
+++ b/firebeeV1/sources/sd_card.c
@@ -0,0 +1,605 @@
+/********************************************************************/
+// sd card
+/********************************************************************/
+
+#define __MBAR  				0xff000000
+#define MCF_SLT0_SCNT           __MBAR + 0x908
+#define MCF_PSC0_PSCTB_8BIT		__MBAR + 0x860C
+#define MCF_PAD_PAR_DSPI        __MBAR + 0xA50
+#define MCF_DSPI_DMCR		    __MBAR + 0x8A00		//dspi control
+
+#define	dspi_dtar0	0x0c
+#define	dspi_dsr	0x2c	
+#define	dspi_dtfr	0x34	
+#define	dspi_drfr	0x38
+#define	time1us		1320
+
+
+void wait_10ms(void)
+{
+	asm
+	{
+warte_10ms:
+		move.l		d0,-(sp) 		
+  		move.l		MCF_SLT0_SCNT,d0
+  		sub.l		#1320000,d0
+ warte_d6:
+		cmp.l		MCF_SLT0_SCNT,d0
+		bcs			warte_d6
+		move.l		(sp)+,d0
+	}
+}
+
+void sd_com(void)		// byt senden und holen ---------------------
+{
+
+	asm
+	{
+
+		move.l		d4,dspi_dtfr(a0)
+wait_auf_complett:
+		btst.b		#7,dspi_dsr(a0)
+		beq			wait_auf_complett
+		move.l		dspi_drfr(a0),d5
+		mov3q.l		#-1,dspi_dsr(a0)		// clr status register
+	}
+}
+
+void sd_get_status(void)	// status holen -------------------------------
+{
+	asm
+	{
+sd_get_status:
+		move.b		#0xff,d4
+		bsr			sd_com
+		cmp.b		#0xff,d5
+		beq			sd_get_status
+	}
+}
+
+void sd_rcv_info(void)	 // daten holen ----------------------------
+{
+	asm
+	{
+		moveq		#18,d3						// 16 byts + 2 byts crc
+		move.b		#0xff,d4
+sd_rcv_rb_w:		
+		bsr			sd_get_status 
+		cmp.b		#0xfe,d5				// daten bereit?
+		bne			sd_rcv_rb_w				// nein->
+sd_rcv_rd_rb:
+		bsr			sd_com
+		move.b		d5,(a2)+
+		subq.l		#1,d3
+		bne			sd_rcv_rd_rb
+	}
+}
+
+void sd_card_idle(void)
+{
+
+	asm
+	{
+// sd idle
+// speed =400kHz
+		move.l		#0x082000ff,d4			// tx vorbesetzen
+		lea			MCF_DSPI_DMCR,a0
+		move.l		#0x38558897,d0				
+		move.l		d0,dspi_dtar0(a0)		// 400kHz 
+
+		move.b		#0xff,d4
+		bsr			sd_com					// clocks 
+		move.b		#0x40,d4				// cmd idle
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#0x95,d4
+		bsr			sd_com
+	}
+}
+
+int sd_card_init(void)
+{
+
+		long		az_sectors;
+
+	asm
+	{
+		lea			MCF_PSC0_PSCTB_8BIT,a1
+		move.l  	#'SD-C',(a1)
+		move.l  	#'ard ',(a1)
+
+		move.l		buffer,a5					// basis addresse (diesen bereich brauchen wir nicht mehr!)
+		move.l		#0x1fffffff,d0				// normal dspi
+		move.l		d0,MCF_PAD_PAR_DSPI
+		lea			MCF_DSPI_DMCR,a0
+		move.l		#0x802d3c00,(a0)			// 8 bit cs off clear fifo
+		move.l		#0x38558897,d0				
+		move.l		d0,dspi_dtar0(a0)			// 400kHz 
+		move.l		#0x082000ff,d4				// tx vorbesetzen
+		move.l		d4,dspi_dtfr				// und setzen
+		mov3q.l		#-1,dspi_dsr(a0)			// status register löschen
+		
+		move.l		#0xc00d3c00,(a0)			// clock on cs ist on
+		bsr			wait_10ms
+		move.l		#0x802d3c00,(a0)			// clock off cs off
+		bsr			sd_com
+		bsr			sd_com
+		bsr			sd_com
+		bsr			sd_com
+		bsr			sd_com
+		bsr			sd_com
+		bsr			sd_com
+		bsr			sd_com
+		bsr			sd_com
+		bsr			sd_com
+		move.l		#0x800d3c00,(a0)			// cs on
+		bsr			sd_com						
+		bsr			sd_com
+		move.l		#0x802d3c00,(a0)			// cs off
+		bsr			sd_com
+		bsr			sd_com
+		bsr			wait_10ms
+
+// sd idle
+		move.l		#100,d6						// 100 versuche
+		move.l		#10,d3						// 10 versuche
+sd_idle:
+		bsr			sd_card_idle
+
+		move.l		#10,d7
+		move.b		#0xff,d4
+sd_idle_leeren:
+		bsr			sd_com
+		cmp.b		#0x01,d5
+		beq			idle_end
+		subq.l		#1,d7
+		bne			sd_idle_leeren
+		subq.l		#1,d6
+		beq			sd_not
+		bra			sd_idle
+idle_end:
+
+// cdm 8
+read_ic:
+		move.b		#0xff,d4			// clocks 
+		bsr			sd_com
+		move.b		#0x48,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#0x01,d4
+		bsr			sd_com
+		move.b		#0xaa,d4
+		bsr			sd_com
+		move.b		#0x87,d4
+		bsr			sd_com
+		
+		bsr			sd_get_status
+		cmp.b		#5,d5
+		beq			sd_v1
+		cmp.b		#1,d5
+		bne			read_ic
+		
+		bsr			sd_com			// 4byts zum wegwerfen
+		bsr			sd_com
+		bsr			sd_com
+		bsr			sd_com
+		cmp.b		#0xaa,d5		// pattern zurückgekommen?
+		bne			sd_testd3		// nein ->
+
+		move.l		#'SDHC',(a1)
+		move.b		#' ',(a1)
+sd_v1:
+		
+// cdm 58
+read_ocr:
+		move.b		#0xff,d4			// clocks 
+		bsr			sd_com
+		move.b		#0x7a,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#0x00,d4
+		bsr			sd_com
+		move.b		#0x00,d4
+		bsr			sd_com
+		move.b		#0x01,d4
+		bsr			sd_com
+		
+		bsr			sd_get_status
+		move.l		#'Ver1',d6
+		cmp.b		#5,d5
+		beq			read_ocr
+		cmp.b		#1,d5
+		bne			read_ocr
+		
+		bsr			sd_com				// 4 byts zum wegwerfen
+		bsr			sd_com
+		bsr			sd_com
+		bsr			sd_com
+
+// acdm 41
+		move.l		#20000,d6			// 20000 versuche ready can bis 1 sec gehen
+wait_of_aktiv:
+		move.b		#0xff,d4			// clocks 
+		bsr			sd_com
+		move.b		#0x77,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#0x95,d4
+		bsr			sd_com
+
+		bsr			sd_get_status
+		cmp.b		#0x05,d5
+		beq			wait_of_aktiv
+
+wait_of_aktiv2:
+		move.b		#0xff,d4			// clocks 
+		bsr			sd_com
+		move.b		#0x69,d4
+		bsr			sd_com
+		move.b		#0x40,d4
+		bsr			sd_com
+		move.b		#0x00,d4
+		bsr			sd_com
+		move.b		#0x00,d4
+		bsr			sd_com
+		move.b		#0x00,d4
+		bsr			sd_com
+		move.b		#0x95,d4
+		bsr			sd_com
+
+		bsr			sd_get_status
+		tst.b		d5
+		beq			sd_init_ok
+		cmp.b		#0x05,d5
+		beq			wait_of_aktiv2	
+		subq.l		#1,d6
+		bne			wait_of_aktiv
+sd_testd3:
+		subq.l		#1,d3
+		bne			sd_idle
+		bra			sd_error
+
+sd_init_ok:
+// fullspeed 
+		move.l		#0x38551120,d0				// 22Mbit/sec
+		move.l		d0,dspi_dtar0(a0)			// setzen 
+
+// cdm 10
+read_cid:
+		move.b		#0xff,d4			// clocks 
+		bsr			sd_com
+		move.b		#0x4a,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#0x00,d4
+		bsr			sd_com
+		move.b		#0x00,d4
+		bsr			sd_com
+		move.b		#0x95,d4
+		bsr			sd_com
+		
+		move.l		a5,a2				// adresse setzen
+		bsr			sd_rcv_info
+
+// name ausgeben
+		lea			1(a5),a2
+		moveq		#7,d7
+sd_nam_loop:
+		move.b		(a2)+,(a1)
+		subq.l		#1,d7
+		bne			sd_nam_loop
+		move.b		#' ',(a1)
+
+// cdm 9
+read_csd:
+		move.b		#0xff,d4			// clocks 
+		bsr			sd_com
+		move.b		#0x49,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#0x00,d4
+		bsr			sd_com
+		move.b		#0x00,d4
+		bsr			sd_com
+		move.b		#0x01,d4
+		bsr			sd_com
+		
+		move.l		a5,a2				// adresse setzen
+		bsr			sd_rcv_info
+
+		mvz.b		(a5),d0
+		lsr.l		#6,d0
+		
+		bne			sd_csd2				// format v2
+		move.l		6(a5),d1
+		moveq		#14,d0				// bit 73..62 c_size
+		lsr.l		d0,d1				// bits extrahieren
+		and.l		#0xfff,d1			// 12 bits
+		addq.l		#1,d1
+		mvz.w		9(a5),d0
+		lsr.l		#7,d0				// bits 49..47
+		and.l		#0x7,d0				// 3 bits
+		moveq.l		#8,d2				// x256 (dif v1 v2)
+		sub.l		d0,d2		
+		lsr.l		d2,d1
+		bra			sd_print_size
+sd_csd2:
+		mvz.w		8(a5),d1
+		addq.l		#1,d1
+sd_print_size:
+		swap		d1
+		move.l		d1,d3
+		lsr.l		#6,d3				//x65636 /64 -> anzahl sectors
+		move.l		d3,az_sectors
+		lsl.l		#1,d1
+		bcc			sd_16G
+		move.l		#'32GB',(a1)
+		bra			sd_ok
+sd_16G:
+		lsl.l		#1,d1
+		bcc			sd_8G
+		move.l		#'16GB',(a1)
+		bra			sd_ok
+sd_8G:
+		lsl.l		#1,d1
+		bcc			sd_4G
+		move.l		#' 8GB',(a1)
+		bra			sd_ok
+sd_4G:
+		lsl.l		#1,d1
+		bcc			sd_2G
+		move.l		#' 4GB',(a1)
+		bra			sd_ok
+sd_2G:
+		lsl.l		#1,d1
+		bcc			sd_1G
+		move.l		#' 2GB',(a1)
+		bra			sd_ok
+sd_1G:
+		lsl.l		#1,d1
+		bcc			sd_512M
+		move.l		#' 1GB',(a1)
+		bra			sd_ok
+sd_512M:
+		lsl.l		#1,d1
+		bcc			sd_256M
+		move.b		#'5',(a1)
+		move.l		#'12MB',(a1)
+		bra			sd_ok
+sd_256M:
+		lsl.l		#1,d1
+		bcc			sd_128M
+		move.b		#'2',(a1)
+		move.l		#'56MB',(a1)
+		bra			sd_ok
+sd_128M:
+		lsl.l		#1,d1
+		bcc			sd_64M
+		move.b		#'1',(a1)
+		move.l		#'28MB',(a1)
+		bra			sd_ok
+sd_64M:
+		lsl.l		#1,d1
+		bcc			sd_32M
+		move.l		#'64MB',(a1)
+		bra			sd_ok
+sd_32M:
+		lsl.l		#1,d1
+		bcc			sd_16M
+		move.l		#'32MB',(a1)
+		bra			sd_ok
+sd_16M:
+		lsl.l		#1,d1
+		bcc			sd_8M
+		move.l		#'16MB',(a1)
+		bra			sd_ok
+sd_8M:
+		move.l		#'<9MB',(a1)
+sd_ok:		
+		move.l  	#' OK!',(a1)
+		move.l		#0x0a0d,(a1)
+		bra			sd_c_ok
+// subs ende -------------------------------
+sd_error:
+		move.l  	#'Erro',(a1)
+		move.l  	#'r!',(a1)
+		move.l		#0x0a0d,(a1)
+		bra			sd_c_error
+sd_not:
+		move.l  	#'non!',(a1)
+		move.l		#0x0a0d,(a1)
+		bra			sd_c_not
+buffer:	dc.l		0,0,0,0,0,0,0,0
+	}
+sd_c_ok:
+		return		az_sectors;
+sd_c_not:
+		return		-2;
+sd_c_error:
+		return		-1;
+}
+
+void sd_rcv_sector(void)	 // 1 sector daten holen ----------------------------
+{
+	asm
+	{
+		bsr			sd_get_status 
+		cmp.b		#0xfe,d5				// daten bereit?
+		bne			sd_rs_end				// nein-> error
+		move.l		#512,d3					// sonst 512 byts abholen
+sd_rs_loop:
+		bsr			sd_com
+		move.b		d5,(a2)+
+		subq.l		#1,d3
+		bne			sd_rs_loop
+// crc holen
+		bsr			sd_com
+		bsr			sd_com
+		clr.l		d5						// alles ok
+sd_rs_end:
+	}
+}
+
+int sd_card_sector_read(long sec_nr,long buf_adr)
+{
+		int			status ;
+	asm
+	{
+		lea			MCF_DSPI_DMCR,a0
+		move.l		#0x082000ff,d4				// tx vorbesetzen
+
+		move.l		sec_nr,d0
+		move.l		buf_adr,a2
+
+		lsl.l		#8,d0
+		add.l		d0,d0						// x 512 !
+		move.l		d0,d1						// byts kehren
+		swap		d1
+		move.l		d1,d2
+		lsr.l		#8,d1
+		
+		move.b		#0xff,d4			// clocks 
+		bsr			sd_com
+		
+		move.b		#0x51,d4
+		bsr			sd_com
+		move.b		d1,d4
+		bsr			sd_com
+		move.b		d2,d4
+		bsr			sd_com
+		move.l		d0,d2
+		lsr.l		#8,d2
+		move.b		d2,d4
+		bsr			sd_com
+		move.b		d0,d4
+		bsr			sd_com
+		move.b		#0x01,d4
+		bsr			sd_com
+
+		clr.l		d5					// alles auf no error
+		clr.l		status
+		
+		bsr			sd_get_status		// status holen
+		tst.b		d5
+		bne			sd_csr_end			// wenn nicht ok -> weg
+// sector holen
+		bsr			sd_rcv_sector
+sd_csr_end:
+		tst.b		d5
+		beq			sd_csr_ok
+		neg.l		d5					// wenn nicht ok status auf negativ
+		move.l		d5,status
+sd_csr_ok:
+	}
+	return	status;
+}
+
+void sd_send_sector(void)	 // 1 sector daten senden ----------------------------
+{
+	asm
+	{
+		move.l		#512,d3		
+		move.b		#0xfe,d4			// start token
+		bsr			sd_com				// senden
+sd_send_wr_wb:
+		move.b		(a2)+,d4			// data
+		bsr			sd_com				// senden
+		subq.l		#1,d3
+		bne			sd_send_wr_wb	
+// send crc
+		move.b		#1,d4			
+		bsr			sd_com				// crc 1.byt
+		move.b		#1,d4			
+		bsr			sd_com				// crc 2.byt
+sd_send_wr_ww:
+		bsr			sd_get_status
+		and.l		#0x1f,d5
+		clr.l		d6					//status auf OK
+		cmp.b		#5,d5				//data accepted?
+		beq			sd_send_end			//ja ->
+		move.l		d5,d6				//sonst status sichern
+sd_send_end:
+		bsr			sd_com
+		tst.b		d5					// warte auf geschrieben
+		beq			sd_send_end
+		move.l		d6,d5				// status zurück
+	}
+}
+
+int sd_card_sector_write(long sec_nr,long buf_adr)
+{
+		int			status;
+	asm
+	{
+		lea			MCF_DSPI_DMCR,a0
+		move.l		#0x082000ff,d4				// tx vorbesetzen
+
+		move.l		sec_nr,d0
+		move.l		buf_adr,a2
+
+		lsl.l		#8,d0
+		add.l		d0,d0						// x 512 !
+		move.l		d0,d1						// byts kehren
+		swap		d1
+		move.l		d1,d2
+		lsr.l		#8,d1
+		
+		move.b		#0xff,d4			// clocks 
+		bsr			sd_com
+		move.b		#0x58,d4
+		bsr			sd_com
+		move.b		d1,d4
+		bsr			sd_com
+		move.b		d2,d4
+		bsr			sd_com
+		move.l		d0,d2
+		lsr.l		#8,d2
+		move.b		d2,d4
+		bsr			sd_com
+		move.b		d0,d4
+		bsr			sd_com
+		move.b		#0x01,d4
+		bsr			sd_com
+
+		clr.l		d5					// alles auf no error
+		clr.l		status
+		bsr			sd_get_status		// status holen
+		tst.b		d5
+		bne			sd_csw_end			// wenn nicht ok -> weg
+// sector schreiben
+		bsr			sd_send_sector
+sd_csw_end:
+		tst.b		d5
+		beq			sd_csw_ok
+		neg.l		d5					// wenn nicht ok status auf negativ
+		move.l		d5,status
+sd_csw_ok:
+	}
+	return	status;
+}
diff --git a/firebeeV1/sources/sd_card.s b/firebeeV1/sources/sd_card.s
new file mode 100644
index 0000000..c51147c
--- /dev/null
+++ b/firebeeV1/sources/sd_card.s
@@ -0,0 +1,406 @@
+/********************************************************************/
+// sd card
+/********************************************************************/
+#define	dspi_dtar0	0x0c
+#define	dspi_dsr	0x2c	
+#define	dspi_dtfr	0x34	
+#define	dspi_drfr	0x38
+
+.text	
+sd_test:
+		lea			MCF_PSC0_PSCTB_8BIT,a6
+		move.l  	#'SD-C',(a6)
+		move.l  	#'ard ',(a6)
+
+		move.l		#__Bas_base,a5					// basis addresse (diesen bereich brauchen wir nicht mehr!)
+		move.l		#0x1fffffff,d0				// normal dspi
+		move.l		d0,MCF_PAD_PAR_DSPI
+		lea			MCF_DSPI_DMCR,a0
+		move.l		#0x800d3c00,(a0)			// 8 bit cs5 on
+		move.l		#0x38558897,d0				
+		move.l		d0,dspi_dtar0(a0)			// 400kHz 
+		move.l		#0x082000ff,d4				// tx vorbesetzen
+		mov3q.l		#-1,dspi_dsr(a0)
+		
+		bsr			warte_1ms
+		move.l		#0xc00d3c00,(a0)			// 8 bit 4MHz clocken cs off
+		bsr			warte_10ms
+		move.l		#0x800d3c00,(a0)			// 8 bit 4MHz normal cs on
+		bsr			sd_com
+		bsr			sd_com
+		bsr			sd_com
+		bsr			sd_com
+		bsr			sd_com
+		bsr			sd_com
+		bsr			sd_com
+		bsr			sd_com
+		bsr			sd_com
+		bsr			sd_com
+		move.l		#0x802d3c00,(a0)			// 8 bit 4MHz normal cs off
+		clr.b		d4
+		bsr			sd_com
+		bsr			sd_com
+		move.l		#0x800d3c00,(a0)			// 8 bit 4MHz normal cs on
+		move.b		#0xff,d4
+		bsr			sd_com
+		bsr			sd_com
+		move.l		#0x802d3c00,(a0)			// 8 bit 4MHz normal cs off
+		bsr			warte_10ms
+
+// sd idle
+		move.l		#100,d6				// 100 versuche
+		move.l		#10,d3				// 10 versuche
+sd_idle:
+		move.b		#0xff,d4			// receive byt
+		bsr			sd_com
+		move.b		#0x40,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#0x95,d4
+		bsr			sd_com
+		
+		move.b		#0xff,d4			// receive byt
+		bsr			sd_com
+		cmp.b		#0x01,d5
+		beq			idle_end
+		bsr			sd_com
+		cmp.b		#0x01,d5
+		beq			idle_end
+		bsr			sd_com
+		cmp.b		#0x01,d5
+		beq			idle_end
+		bsr			sd_com
+		cmp.b		#0x01,d5
+		beq			idle_end
+		bsr			sd_com
+		cmp.b		#0x01,d5
+		beq			idle_end
+		bsr			sd_com
+		cmp.b		#0x01,d5
+		beq			idle_end
+		subq.l		#1,d6
+		beq			sd_not
+		bra			sd_idle
+idle_end:
+// cdm 8
+read_ic:
+		move.b		#0xff,d4			// receive byt
+		bsr			sd_com
+		move.b		#0x48,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#0x01,d4
+		bsr			sd_com
+		move.b		#0xaa,d4
+		bsr			sd_com
+		move.b		#0x87,d4
+		bsr			sd_com
+		
+		bsr			sd_get_status
+		cmp.b		#5,d5
+		beq			sd_v1
+		cmp.b		#1,d5
+		bne			read_ic
+		
+		move.b		#0xff,d4
+		bsr			sd_com
+		move.b		d5,d0
+		bsr			sd_com
+		move.b		d5,d1
+		bsr			sd_com
+		move.b		d5,d2
+		bsr			sd_com
+		cmp.b		#0xaa,d5
+		bne			sd_testd3
+
+		move.l		#'SDHC',(a6)
+		move.b		#' ',(a6)
+sd_v1:
+		
+// cdm 58
+read_ocr:
+		move.b		#0xff,d4			// receive byt
+		bsr			sd_com
+		move.b		#0x7a,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#0x00,d4
+		bsr			sd_com
+		move.b		#0x00,d4
+		bsr			sd_com
+		move.b		#0x01,d4
+		bsr			sd_com
+		
+		bsr			sd_get_status
+		move.l		#'Ver1',d6
+		cmp.b		#5,d5
+		beq			read_ocr
+		cmp.b		#1,d5
+		bne			read_ocr
+		
+		move.b		#0xff,d4
+		bsr			sd_com
+		move.b		d5,d0
+		bsr			sd_com
+		move.b		d5,d1
+		bsr			sd_com
+		move.b		d5,d2
+		bsr			sd_com
+
+// acdm 41
+		move.l		#20000,d6			// 20000 versuche ready can bis 1 sec gehen
+wait_of_aktiv:
+		move.b		#0xff,d4			// receive byt
+		bsr			sd_com
+		move.b		#0x77,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#0x95,d4
+		bsr			sd_com
+
+		bsr			sd_get_status
+		cmp.b		#0x05,d5
+		beq			wait_of_aktiv
+
+wait_of_aktiv2:
+		move.b		#0xff,d4			// receive byt
+		bsr			sd_com
+		move.b		#0x69,d4
+		bsr			sd_com
+		move.b		#0x40,d4
+		bsr			sd_com
+		move.b		#0x00,d4
+		bsr			sd_com
+		move.b		#0x00,d4
+		bsr			sd_com
+		move.b		#0x00,d4
+		bsr			sd_com
+		move.b		#0x95,d4
+		bsr			sd_com
+
+		bsr			sd_get_status
+		tst.b		d5
+		beq			sd_init_ok
+		cmp.b		#0x05,d5
+		beq			wait_of_aktiv2	
+		subq.l		#1,d6
+		bne			wait_of_aktiv
+sd_testd3:
+		subq.l		#1,d3
+		bne			sd_idle
+		bra			sd_error
+
+sd_init_ok:
+// cdm 10
+read_cid:
+		move.b		#0xff,d4			// receive byt
+		bsr			sd_com
+		move.b		#0x4a,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#0x00,d4
+		bsr			sd_com
+		move.b		#0x00,d4
+		bsr			sd_com
+		move.b		#0x95,d4
+		bsr			sd_com
+		
+		move.l		a5,a4				// adresse setzen
+		bsr			sd_rcv_info
+
+// name ausgeben
+		lea			1(a5),a4
+		moveq		#7,d7
+sd_nam_loop:
+		move.b		(a4)+,(a6)
+		subq.l		#1,d7
+		bne			sd_nam_loop
+		move.b		#' ',(a6)
+
+// cdm 9
+read_csd:
+		move.b		#0xff,d4			// receive byt
+		bsr			sd_com
+		move.b		#0x49,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#00,d4
+		bsr			sd_com
+		move.b		#0x00,d4
+		bsr			sd_com
+		move.b		#0x00,d4
+		bsr			sd_com
+		move.b		#0x01,d4
+		bsr			sd_com
+		
+		move.l		a5,a4				// adresse setzen
+		bsr			sd_rcv_info
+
+		mvz.b		(a5),d0
+		lsr.l		#6,d0
+		
+		bne			sd_csd2				// format v2
+		move.l		6(a5),d1
+		moveq		#14,d0				// bit 73..62 c_size
+		lsr.l		d0,d1				// bits extrahieren
+		and.l		#0xfff,d1			// 12 bits
+		addq.l		#1,d1
+		mvz.w		9(a5),d0
+		lsr.l		#7,d0				// bits 49..47
+		and.l		#0x7,d0				// 3 bits
+		moveq.l		#8,d2				// x256 (dif v1 v2)
+		sub.l		d0,d2		
+		lsr.l		d2,d1
+		bra			sd_print_size
+sd_csd2:
+		mvz.w		8(a5),d1
+		addq.l		#1,d1
+sd_print_size:		
+		swap		d1
+		lsl.l		#1,d1
+		bcc			sd_16G
+		move.l		#'32GB',(a6)
+		bra			sd_ok
+sd_16G:
+		lsl.l		#1,d1
+		bcc			sd_8G
+		move.l		#'16GB',(a6)
+		bra			sd_ok
+sd_8G:
+		lsl.l		#1,d1
+		bcc			sd_4G
+		move.l		#' 8GB',(a6)
+		bra			sd_ok
+sd_4G:
+		lsl.l		#1,d1
+		bcc			sd_2G
+		move.l		#' 4GB',(a6)
+		bra			sd_ok
+sd_2G:
+		lsl.l		#1,d1
+		bcc			sd_1G
+		move.l		#' 2GB',(a6)
+		bra			sd_ok
+sd_1G:
+		lsl.l		#1,d1
+		bcc			sd_512M
+		move.l		#' 1GB',(a6)
+		bra			sd_ok
+sd_512M:
+		lsl.l		#1,d1
+		bcc			sd_256M
+		move.b		#'5',(a6)
+		move.l		#'12MB',(a6)
+		bra			sd_ok
+sd_256M:
+		lsl.l		#1,d1
+		bcc			sd_128M
+		move.b		#'2',(a6)
+		move.l		#'56MB',(a6)
+		bra			sd_ok
+sd_128M:
+		lsl.l		#1,d1
+		bcc			sd_64M
+		move.b		#'1',(a6)
+		move.l		#'28MB',(a6)
+		bra			sd_ok
+sd_64M:
+		lsl.l		#1,d1
+		bcc			sd_32M
+		move.l		#'64MB',(a6)
+		bra			sd_ok
+sd_32M:
+		lsl.l		#1,d1
+		bcc			sd_16M
+		move.l		#'32MB',(a6)
+		bra			sd_ok
+sd_16M:
+		lsl.l		#1,d1
+		bcc			sd_8M
+		move.l		#'16MB',(a6)
+		bra			sd_ok
+sd_8M:
+		move.l		#'<9MB',(a6)
+sd_ok:		
+		move.l  	#' OK!',(a6)
+		move.l		#0x0a0d,(a6)
+		halt
+		halt
+		rts
+// subs ende -------------------------------
+sd_V1:
+		move.l  #'non!',(a6)
+		move.l	#0x0a0d,(a6)
+		halt
+		halt
+		rts
+sd_error:
+		move.l  #'Erro',(a6)
+		move.l  #'r!',(a6)
+		move.l	#0x0a0d,(a6)
+		halt
+		halt
+		rts
+sd_not:
+		move.l  #'non!',(a6)
+		move.l	#0x0a0d,(a6)
+		halt
+		halt
+		rts
+
+// status holen -------------------------------
+sd_get_status:
+		move.b		#0xff,d4
+		bsr			sd_com
+		cmp.b		#0xff,d5
+		beq			sd_get_status
+		rts
+// byt senden und holen ---------------------		
+sd_com:
+		move.l		d4,dspi_dtfr(a0)
+wait_auf_complett:
+		btst.b		#7,dspi_dsr(a0)
+		beq			wait_auf_complett
+		move.l		dspi_drfr(a0),d5
+		mov3q.l		#-1,dspi_dsr(a0)		// clr status register
+		rts
+
+// daten holen ----------------------------
+sd_rcv_info:		
+		moveq		#18,d3						// 16 byts + 2 byts crc
+		move.b		#0xff,d4
+sd_rcv_rb_w:		
+		bsr			sd_get_status 
+		cmp.b		#0xfe,d5				// daten bereit?
+		bne			sd_rcv_rb_w				// nein->
+sd_rcv_rd_rb:
+		bsr			sd_com
+		move.b		d5,(a4)+
+		subq.l		#1,d3
+		bne			sd_rcv_rd_rb
+		rts
+/******************************************/
diff --git a/firebeeV1/sources/sd_ide.c b/firebeeV1/sources/sd_ide.c
new file mode 100644
index 0000000..092f95e
--- /dev/null
+++ b/firebeeV1/sources/sd_ide.c
@@ -0,0 +1,543 @@
+
+
+#include "MCF5475.h"
+#include "startcf.h"
+
+extern unsigned long far __SP_AFTER_RESET[];
+extern unsigned long far __Bas_base[];
+
+	/* imported routines */
+//extern int warten_20ms();
+//extern int warten_200us();
+//extern int warten_10us();
+ 
+/********************************************************************/
+void asm sd_test(void)
+{
+		clr.w		MCF_PAD_PAR_DSPI
+		lea			MCF_GPIO_PPDSDR_DSPI,a2		// data in
+		lea			MCF_GPIO_PODR_DSPI,a1		// data out
+		move.b		#0x00,(a1)					// alle auf 0
+		lea			MCF_GPIO_PDDR_DSPI,a0
+		move.b		#0x7d,(a0)					// din = input rest output
+		
+		bsr			warten_20ms
+		
+		move.b		#0x7f,(a1)					// alle auf 1
+
+		bsr			sd_16clk
+		bsr			sd_16clk
+		bsr			sd_16clk
+		bsr			sd_16clk
+		bsr			sd_16clk
+		bsr			sd_16clk
+		bsr			sd_16clk
+		bsr			sd_16clk
+// sd idle
+sd_idle:
+		bsr			sd_16clk
+		moveq		#0x40,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#0x95,d4
+		bsr			sd_com
+		
+		bsr			sd_receive
+
+		cmp.b		#0x05,d5
+		beq			sd_test
+		cmp.b		#0x01,d5
+		beq			wait_of_aktiv
+		cmp.b		#0x04,d5
+		beq			sd_init_ok
+		cmp.b		#0x00,d5
+		beq			sd_init_ok
+		bra			sd_idle
+				
+// acdm 41
+wait_of_aktiv:
+		bsr			sd_16clk
+
+		moveq		#0x77,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#0x01,d4
+		bsr			sd_com
+
+		bsr			sd_receive
+
+		bsr			sd_16clk
+
+		move.l		#0xff,d6
+		moveq		#0x69,d4
+		bsr			sd_com
+		and			d5,d6
+		moveq		#00,d4
+		bsr			sd_com
+		and			d5,d6
+		moveq		#00,d4
+		bsr			sd_com
+		and			d5,d6
+		moveq		#0x02,d4
+		bsr			sd_com
+		and			d5,d6
+		moveq		#00,d4
+		bsr			sd_com
+		and			d5,d6
+		moveq		#0x01,d4
+		bsr			sd_com
+		and			d5,d6
+
+		bsr			sd_receive
+				
+		cmp.b		#0x00,d5
+		beq			sd_init_ok
+		cmp.b		#0x05,d5
+		beq			sd_test	
+		bra			wait_of_aktiv
+
+sd_init_ok:
+
+// blockgrösse 512byt
+sd_bg:
+		bsr			sd_16clk
+		moveq		#0x50,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#02,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#0x01,d4
+		bsr			sd_com
+		
+		bsr			sd_receive
+
+		cmp.b		#0x00,d5
+		bne			sd_bg
+
+// read block
+sd_rb:
+		bsr			sd_16clk
+		moveq		#0x51,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#0x08,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#0x01,d4
+		bsr			sd_com
+		
+		bsr			sd_receive
+
+		cmp.b		#0x00,d5
+		bne			sd_rb
+		
+		lea			0xc00000,a4
+		move.l		#513,d7
+rd_rb:
+		bsr			sd_receive
+		move.b		d5,(a4)+
+		subq.l		#1,d7
+		bne			rd_rb	
+
+// write block
+sd_wb:
+		bsr			sd_16clk
+		moveq		#0x58,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#0x08,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#0x01,d4
+		bsr			sd_com
+		
+		bsr			sd_receive
+
+		cmp.b		#0x00,d5
+		bne			sd_wb
+		
+		lea			0xc00000,a4
+		move.l		#513,d7
+		moveq.l		#0x66,d4
+wr_wb:
+		bsr			sd_com
+//		subq.l		#1,d4
+		moveq		#0x66,d4
+		subq.l		#1,d7
+		bne			wr_wb	
+
+		bsr			sd_receive
+		
+wr_wb_el:	
+		moveq		#0xff,d4
+		bsr			sd_com
+		cmp.b		#0xff,d5
+		bne			wr_wb_el
+		
+
+// read block 2
+sd_rb2:
+		bsr			sd_16clk
+		moveq		#0x51,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#0x08,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#0x01,d4
+		bsr			sd_com
+		
+		bsr			sd_receive
+
+		cmp.b		#0x00,d5
+		bne			sd_rb2
+		
+		lea			0xc00400,a4
+		move.l		#513,d7
+rd_rb2:
+		bsr			sd_receive
+		move.b		d5,(a4)+
+		subq.l		#1,d7
+		bne			rd_rb2	
+
+
+		nop
+		nop
+
+		rts
+		
+sd_receive:
+		moveq		#0xff,d4
+		bsr			sd_com
+		cmp.b		#0xff,d5
+		beq			sd_receive
+		rts
+		
+sd_com:
+		bclr.b		#6,(a1)
+sd_comb:
+		bsr			warten_10us
+		moveq		#7,d2
+		clr.l		d5
+sd_com_loop:
+		btst		d2,d4
+		beq			sd_com2
+		bset.b		#0,(a1)
+		bra			sd_com2_1
+sd_com2:
+		bclr.b		#0,(a1)
+sd_com2_1:
+		bsr			sd_clk
+		and.l		#0x02,d3
+		beq			sd_com3
+		bset.b		d2,d5
+sd_com3:
+		subq.l		#1,d2
+		bge			sd_com_loop
+		bsr			warten_10us
+		bset.b		#6,(a1)
+		bset.b		#0,(a1)
+		bsr			warten_200us
+		rts
+sd_clk:
+		tst.b		0xfffff700
+		tst.b		0xfffff700
+		bset.b		#2,(a1)
+		tst.b		0xfffff700
+		tst.b		0xfffff700
+		move.b		(a2),d3
+		tst.b		0xfffff700
+		bclr.b		#2,(a1)
+		rts
+
+sd_15clk:
+		move		#15,d0
+		bra			sd_16clk
+sd_16clk:
+		moveq		#16,d0
+sd_16clk1:
+		bsr			sd_clk
+		subq.l		#1,d0
+		bne			sd_16clk1
+		bsr			warten_10us
+		rts
+// warteschleife ca. 20ms  
+warten_20ms:  		
+		move.l		a0,-(sp)
+		move.l		d6,-(sp) 		
+		move.l		d1,-(sp) 		
+		move.l		d0,-(sp) 		
+  		lea			MCF_SLT0_SCNT,a0
+  		move.l		(a0),d0
+  		move.l		#700000,d6
+  		bra			warten_loop
+// warteschleife ca. 200us  
+warten_200us: 
+		move.l		a0,-(sp)
+		move.l		d6,-(sp) 		
+		move.l		d1,-(sp) 		
+		move.l		d0,-(sp) 		
+  		lea			MCF_SLT0_SCNT,a0
+  		move.l		(a0),d0
+  		move.l		#7000,d6
+  		bra			warten_loop
+// warteschleife ca. 10us  
+warten_10us:  		
+		move.l		a0,-(sp)
+		move.l		d6,-(sp) 		
+		move.l		d1,-(sp) 		
+		move.l		d0,-(sp) 		
+  		lea			MCF_SLT0_SCNT,a0
+  		move.l		(a0),d0
+  		move.l		#333,d6
+warten_loop:
+		move.l		(a0),d1
+		sub.l		d0,d1
+		add.l		d6,d1
+		bpl			warten_loop
+		move.l		(sp)+,d0
+		move.l		(sp)+,d1
+		move.l		(sp)+,d6
+		move.l		(sp)+,a0
+		rts;
+}
+
+
+/**************************************************/
+void asm ide_test(void)
+{
+		lea			MCF_PAD_PAR_DSPI,a0
+		move.w		#0x1fff,(a0)
+		lea			MCF_DSPI_DCTAR0,a0
+		move.l		#0x38a644e4,(a0)
+		lea			MCF_DSPI_DMCR,a0
+		move.l		#0x802d3c00,(a0)
+		clr.l		MCF_DSPI_DTCR
+		bsr			warten_20ms
+		lea			MCF_DSPI_DTFR,a0
+		lea			MCF_DSPI_DRFR,a1
+
+		moveq		#10,d0		
+sd_reset:
+		move.l		#0x000100ff,(a0)
+		bsr			warten_20ms
+		and.l		(a1),d0
+		subq.l		#1,d0
+		bne			sd_reset
+		
+		moveq		#10,d1
+sd_loop1:
+		bsr			warten_20ms
+		moveq		#-1,d0		
+// cmd 0 set to idle
+		move.l		#0x00200040,(a0)
+		bsr			warten_20ms
+		and.l		(a1),d0
+		move.l		#0x00200000,(a0)
+		bsr			warten_20ms
+		and.l		(a1),d0
+		move.l		#0x00200000,(a0)
+		bsr			warten_20ms
+		and.l		(a1),d0
+		move.l		#0x00200000,(a0)
+		bsr			warten_20ms
+		and.l		(a1),d0
+		move.l		#0x00200000,(a0)
+		bsr			warten_20ms
+		and.l		(a1),d0
+		move.l		#0x00200095,(a0)
+		bsr			warten_20ms
+		and.l		(a1),d0
+		cmp.w		#0x0001,d0
+		beq			sd_loop2
+		subq.l		#1,d1
+		bne			sd_loop1
+		moveq		#10,d1
+		bra			sd_test
+sd_loop2:
+		moveq		#-1,d0		
+// cmd 41		
+		move.l		#0x00200069,(a0)
+		bsr			warten_20ms
+		and.l		(a1),d0
+		move.l		#0x00200000,(a0)
+		bsr			warten_20ms
+		and.l		(a1),d0
+		move.l		#0x00200000,(a0)
+		bsr			warten_20ms
+		and.l		(a1),d0
+		move.l		#0x00200000,(a0)
+		bsr			warten_20ms
+		and.l		(a1),d0
+		move.l		#0x00200000,(a0)
+		bsr			warten_20ms
+		and.l		(a1),d0
+		move.l		#0x00200001,(a0)
+		bsr			warten_20ms
+		and.l		(a1),d0
+		tst.w		d0
+		bne			sd_loop2
+
+		nop
+		nop
+/********************************************************************/
+#define		cmd_reg		(0x1d)
+#define		status_reg	(0x1d)
+#define		seccnt		(0x09)
+
+ide_test:
+		lea			0xfff00040,a0
+		lea			0xc00000,a1
+		move.b		#0xec,cmd_reg(a0)		//identify devcie cmd
+		bsr			wait_int
+		bsr			ds_rx
+// read sector normal		
+		move.b		#1,seccnt(a0)			// 1 sector
+		move.b		#0x20,cmd_reg(a0)		// read cmd
+		bsr			wait_int
+		bsr			ds_rx
+
+// write testpattern sector
+		move.b		#1,seccnt(a0)			// 1 sector
+		move.b		#0x30,cmd_reg(a0)		// write cmd
+		bsr			drq_wait
+// write pattern
+		move.l		#256,d0
+ide_test_loop3:		
+		move.w		#0xa55a,(a0)
+		subq.l		#1,d0
+		bne			ide_test_loop3
+		bsr			wait_int
+// read testpattern sector
+		move.b		#1,seccnt(a0)			// 1 sector
+		move.b		#0x20,cmd_reg(a0)		// read
+		bsr			wait_int
+		bsr			ds_rx
+// sector restauriern
+		move.b		#1,seccnt(a0)			// 1 sector
+		move.b		#0x30,cmd_reg(a0)		// write
+		lea			-0x400(a1),a1			// vorletzer
+		bsr			drq_wait
+		bsr			ds_tx
+		bsr			wait_int
+// fertig und zurück		
+		nop
+		rts
+// wait auf int
+wait_int:
+		move.b		0xfffffa01,d0
+		btst.b		#5,d0
+		bne			wait_int
+		move.b		status_reg(a0),d0
+		rts
+// wait auf drq
+drq_wait:
+		move.b		status_reg(a0),d0
+		btst		#3,d0
+		beq			drq_wait
+		rts
+
+// 1 sector lesen word
+ds_rx:
+		move.l		#256,d0
+ds_rx_loop:		
+		move.w		(a0),(a1)+
+		subq.l		#1,d0
+		bne			ds_rx_loop
+		rts
+// 1 sector lesen long
+ds_rxl:
+		move.l		#128,d0
+ds_rxl_loop:		
+		move.l		(a0),(a1)+
+		subq.l		#1,d0
+		bne			ds_rxl_loop
+		rts
+// 1 sector schreiben word
+ds_tx:
+		move.l		#256,d0
+ds_tx_loop:		
+		move.w		(a1)+,(a0)
+		subq.l		#1,d0
+		bne			ds_tx_loop
+		rts
+// 1 sector schreiben word
+ds_txl:
+		move.l		#128,d0
+ds_txl_loop:		
+		move.l		(a1)+,(a0)
+		subq.l		#1,d0
+		bne			ds_txl_loop
+		rts
+// warteschleife ca. 20ms  
+warten_20ms:  		
+		move.l		a0,-(sp)
+		move.l		d6,-(sp) 		
+		move.l		d1,-(sp) 		
+		move.l		d0,-(sp) 		
+  		lea			MCF_SLT0_SCNT,a0
+  		move.l		(a0),d0
+  		move.l		#700000,d6
+  		bra			warten_loop
+// warteschleife ca. 200us  
+warten_200us: 
+		move.l		a0,-(sp)
+		move.l		d6,-(sp) 		
+		move.l		d1,-(sp) 		
+		move.l		d0,-(sp) 		
+  		lea			MCF_SLT0_SCNT,a0
+  		move.l		(a0),d0
+  		move.l		#7000,d6
+  		bra			warten_loop
+// warteschleife ca. 10us  
+warten_10us:  		
+		move.l		a0,-(sp)
+		move.l		d6,-(sp) 		
+		move.l		d1,-(sp) 		
+		move.l		d0,-(sp) 		
+  		lea			MCF_SLT0_SCNT,a0
+  		move.l		(a0),d0
+  		move.l		#333,d6
+warten_loop:
+		move.l		(a0),d1
+		sub.l		d0,d1
+		add.l		d6,d1
+		bpl			warten_loop
+		move.l		(sp)+,d0
+		move.l		(sp)+,d1
+		move.l		(sp)+,d6
+		move.l		(sp)+,a0
+		rts;
+}
+/********************************************************************/
diff --git a/firebeeV1/sources/sd_ide.s b/firebeeV1/sources/sd_ide.s
new file mode 100644
index 0000000..4d31184
--- /dev/null
+++ b/firebeeV1/sources/sd_ide.s
@@ -0,0 +1,458 @@
+
+
+//.include "startcf.h"
+
+//.extern ___MBAR
+//#define MCF_SLT0_SCNT	___MBAR+0x908
+
+//.global ide_test
+
+.text
+/*
+sd_test:
+		clr.w		MCF_PAD_PAR_DSPI
+		lea			MCF_GPIO_PPDSDR_DSPI,a2		// data in
+		lea			MCF_GPIO_PODR_DSPI,a1		// data out
+		move.b		#0x00,(a1)					// alle auf 0
+		lea			MCF_GPIO_PDDR_DSPI,a0
+		move.b		#0x7d,(a0)					// din = input rest output
+		
+		bsr			warten_20ms
+		
+		move.b		#0x7f,(a1)					// alle auf 1
+
+		bsr			sd_16clk
+		bsr			sd_16clk
+		bsr			sd_16clk
+		bsr			sd_16clk
+		bsr			sd_16clk
+		bsr			sd_16clk
+		bsr			sd_16clk
+		bsr			sd_16clk
+// sd idle
+sd_idle:
+		bsr			sd_16clk
+		moveq		#0x40,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#0x95,d4
+		bsr			sd_com
+		
+		bsr			sd_receive
+
+		cmp.b		#0x05,d5
+		beq			sd_test
+		cmp.b		#0x01,d5
+		beq			wait_of_aktiv
+		cmp.b		#0x04,d5
+		beq			sd_init_ok
+		cmp.b		#0x00,d5
+		beq			sd_init_ok
+		bra			sd_idle
+				
+// acdm 41
+wait_of_aktiv:
+		bsr			sd_16clk
+
+		moveq		#0x77,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#0x01,d4
+		bsr			sd_com
+
+		bsr			sd_receive
+
+		bsr			sd_16clk
+
+		move.l		#0xff,d6
+		moveq		#0x69,d4
+		bsr			sd_com
+		and			d5,d6
+		moveq		#00,d4
+		bsr			sd_com
+		and			d5,d6
+		moveq		#00,d4
+		bsr			sd_com
+		and			d5,d6
+		moveq		#0x02,d4
+		bsr			sd_com
+		and			d5,d6
+		moveq		#00,d4
+		bsr			sd_com
+		and			d5,d6
+		moveq		#0x01,d4
+		bsr			sd_com
+		and			d5,d6
+
+		bsr			sd_receive
+				
+		cmp.b		#0x00,d5
+		beq			sd_init_ok
+		cmp.b		#0x05,d5
+		beq			sd_test	
+		bra			wait_of_aktiv
+
+sd_init_ok:
+
+// blockgrösse 512byt
+sd_bg:
+		bsr			sd_16clk
+		moveq		#0x50,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#02,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#0x01,d4
+		bsr			sd_com
+		
+		bsr			sd_receive
+
+		cmp.b		#0x00,d5
+		bne			sd_bg
+
+// read block
+sd_rb:
+		bsr			sd_16clk
+		moveq		#0x51,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#0x08,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#0x01,d4
+		bsr			sd_com
+		
+		bsr			sd_receive
+
+		cmp.b		#0x00,d5
+		bne			sd_rb
+		
+		lea			0xc00000,a4
+		move.l		#513,d7
+rd_rb:
+		bsr			sd_receive
+		move.b		d5,(a4)+
+		subq.l		#1,d7
+		bne			rd_rb	
+
+// write block
+sd_wb:
+		bsr			sd_16clk
+		moveq		#0x58,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#0x08,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#0x01,d4
+		bsr			sd_com
+		
+		bsr			sd_receive
+
+		cmp.b		#0x00,d5
+		bne			sd_wb
+		
+		lea			0xc00000,a4
+		move.l		#513,d7
+		moveq.l		#0x66,d4
+wr_wb:
+		bsr			sd_com
+//		subq.l		#1,d4
+		moveq		#0x66,d4
+		subq.l		#1,d7
+		bne			wr_wb	
+
+		bsr			sd_receive
+		
+wr_wb_el:	
+		moveq		#0xff,d4
+		bsr			sd_com
+		cmp.b		#0xff,d5
+		bne			wr_wb_el
+		
+
+// read block 2
+sd_rb2:
+		bsr			sd_16clk
+		moveq		#0x51,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#0x08,d4
+		bsr			sd_com
+		moveq		#00,d4
+		bsr			sd_com
+		moveq		#0x01,d4
+		bsr			sd_com
+		
+		bsr			sd_receive
+
+		cmp.b		#0x00,d5
+		bne			sd_rb2
+		
+		lea			0xc00400,a4
+		move.l		#513,d7
+rd_rb2:
+		bsr			sd_receive
+		move.b		d5,(a4)+
+		subq.l		#1,d7
+		bne			rd_rb2	
+
+
+		nop
+		nop
+
+		rts
+		
+sd_receive:
+		moveq		#0xff,d4
+		bsr			sd_com
+		cmp.b		#0xff,d5
+		beq			sd_receive
+		rts
+		
+sd_com:
+		bclr.b		#6,(a1)
+sd_comb:
+		bsr			warten_10us
+		moveq		#7,d2
+		clr.l		d5
+sd_com_loop:
+		btst		d2,d4
+		beq			sd_com2
+		bset.b		#0,(a1)
+		bra			sd_com2_1
+sd_com2:
+		bclr.b		#0,(a1)
+sd_com2_1:
+		bsr			sd_clk
+		and.l		#0x02,d3
+		beq			sd_com3
+		bset.b		d2,d5
+sd_com3:
+		subq.l		#1,d2
+		bge			sd_com_loop
+		bsr			warten_10us
+		bset.b		#6,(a1)
+		bset.b		#0,(a1)
+		bsr			warten_200us
+		rts
+sd_clk:
+		tst.b		0xfffff700
+		tst.b		0xfffff700
+		bset.b		#2,(a1)
+		tst.b		0xfffff700
+		tst.b		0xfffff700
+		move.b		(a2),d3
+		tst.b		0xfffff700
+		bclr.b		#2,(a1)
+		rts
+
+sd_15clk:
+		move		#15,d0
+		bra			sd_16clk
+sd_16clk:
+		moveq		#16,d0
+sd_16clk1:
+		bsr			sd_clk
+		subq.l		#1,d0
+		bne			sd_16clk1
+		bsr			warten_10us
+		rts
+// warteschleife ca. 20ms  
+warten_20ms:  		
+		move.l		a0,-(sp)
+		move.l		d6,-(sp) 		
+		move.l		d1,-(sp) 		
+		move.l		d0,-(sp) 		
+  		lea			MCF_SLT0_SCNT,a0
+  		move.l		(a0),d0
+  		move.l		#700000,d6
+  		bra			warten_loop
+// warteschleife ca. 200us  
+warten_200us: 
+		move.l		a0,-(sp)
+		move.l		d6,-(sp) 		
+		move.l		d1,-(sp) 		
+		move.l		d0,-(sp) 		
+  		lea			MCF_SLT0_SCNT,a0
+  		move.l		(a0),d0
+  		move.l		#7000,d6
+  		bra			warten_loop
+// warteschleife ca. 10us  
+warten_10us:  		
+		move.l		a0,-(sp)
+		move.l		d6,-(sp) 		
+		move.l		d1,-(sp) 		
+		move.l		d0,-(sp) 		
+  		lea			MCF_SLT0_SCNT,a0
+  		move.l		(a0),d0
+  		move.l		#333,d6
+warten_loop:
+		move.l		(a0),d1
+		sub.l		d0,d1
+		add.l		d6,d1
+		bpl			warten_loop
+		move.l		(sp)+,d0
+		move.l		(sp)+,d1
+		move.l		(sp)+,d6
+		move.l		(sp)+,a0
+		rts;
+/********************************************************************/
+#define		cmd_reg		(0x1d)
+#define		status_reg	(0x1d)
+#define		seccnt		(0x09)
+
+ide_test:
+		lea			0xfff00040,a0
+		lea			0xc00000,a1
+		move.b		#0xec,cmd_reg(a0)		//identify devcie cmd
+		bsr			wait_int
+		bsr			ds_rx
+// read sector normal		
+		move.b		#1,seccnt(a0)			// 1 sector
+		move.b		#0x20,cmd_reg(a0)		// read cmd
+		bsr			wait_int
+		bsr			ds_rx
+
+// write testpattern sector
+		move.b		#1,seccnt(a0)			// 1 sector
+		move.b		#0x30,cmd_reg(a0)		// write cmd
+		bsr			drq_wait
+// write pattern
+		move.l		#256,d0
+ide_test_loop3:		
+		move.w		#0xa55a,(a0)
+		subq.l		#1,d0
+		bne			ide_test_loop3
+		bsr			wait_int
+// read testpattern sector
+		move.b		#1,seccnt(a0)			// 1 sector
+		move.b		#0x20,cmd_reg(a0)		// read
+		bsr			wait_int
+		bsr			ds_rx
+// sector restauriern
+		move.b		#1,seccnt(a0)			// 1 sector
+		move.b		#0x30,cmd_reg(a0)		// write
+		lea			-0x400(a1),a1			// vorletzer
+		bsr			drq_wait
+		bsr			ds_tx
+		bsr			wait_int
+// fertig und zurück		
+		nop
+		rts
+// wait auf int
+wait_int:
+		move.b		0xfffffa01,d0
+		btst		#5,d0
+		bne			wait_int
+		move.b		status_reg(a0),d0
+		rts
+// wait auf drq
+drq_wait:
+		move.b		status_reg(a0),d0
+		btst		#3,d0
+		beq			drq_wait
+		rts
+
+// 1 sector lesen word
+ds_rx:
+		move.l		#256,d0
+ds_rx_loop:		
+		move.w		(a0),(a1)+
+		subq.l		#1,d0
+		bne			ds_rx_loop
+		rts
+// 1 sector lesen long
+ds_rxl:
+		move.l		#128,d0
+ds_rxl_loop:		
+		move.l		(a0),(a1)+
+		subq.l		#1,d0
+		bne			ds_rxl_loop
+		rts
+// 1 sector schreiben word
+ds_tx:
+		move.l		#256,d0
+ds_tx_loop:		
+		move.w		(a1)+,(a0)
+		subq.l		#1,d0
+		bne			ds_tx_loop
+		rts
+// 1 sector schreiben word
+ds_txl:
+		move.l		#128,d0
+ds_txl_loop:		
+		move.l		(a1)+,(a0)
+		subq.l		#1,d0
+		bne			ds_txl_loop
+		rts
+// warteschleife ca. 20ms  
+warten_20ms:  		
+		move.l		a0,-(sp)
+		move.l		d6,-(sp) 		
+		move.l		d1,-(sp) 		
+		move.l		d0,-(sp) 		
+  		lea			MCF_SLT0_SCNT,a0
+  		move.l		(a0),d0
+  		move.l		#700000,d6
+  		bra			warten_loop
+// warteschleife ca. 200us  
+warten_200us: 
+		move.l		a0,-(sp)
+		move.l		d6,-(sp) 		
+		move.l		d1,-(sp) 		
+		move.l		d0,-(sp) 		
+  		lea			MCF_SLT0_SCNT,a0
+  		move.l		(a0),d0
+  		move.l		#7000,d6
+  		bra			warten_loop
+// warteschleife ca. 10us  
+warten_10us:  		
+		move.l		a0,-(sp)
+		move.l		d6,-(sp) 		
+		move.l		d1,-(sp) 		
+		move.l		d0,-(sp) 		
+  		lea			MCF_SLT0_SCNT,a0
+  		move.l		(a0),d0
+  		move.l		#333,d6
+warten_loop:
+		move.l		(a0),d1
+		sub.l		d0,d1
+		add.l		d6,d1
+		bpl			warten_loop
+		move.l		(sp)+,d0
+		move.l		(sp)+,d1
+		move.l		(sp)+,d6
+		move.l		(sp)+,a0
+		rts;
+/********************************************************************/
diff --git a/firebeeV1/sources/startcf.c b/firebeeV1/sources/startcf.c
new file mode 100644
index 0000000..7249338
--- /dev/null
+++ b/firebeeV1/sources/startcf.c
@@ -0,0 +1,83 @@
+/*
+ *    CF_Startup.c - Default init/startup/termination routines for
+ *                     Embedded Metrowerks C++
+ *
+ *    Copyright © 1993-1998 Metrowerks, Inc. All Rights Reserved.
+ *    Copyright © 2005 Freescale semiConductor Inc. All Rights Reserved.
+ *
+ *
+ *    THEORY OF OPERATION
+ *
+ *    This version of thestartup code is intended for linker relocated
+ *    executables.  The startup code will assign the stack pointer to
+ *    __SP_INIT, assign the address of the data relative base address
+ *    to a5, initialize the .bss/.sbss sections to zero, call any
+ *    static C++ initializers and then call main.  Upon returning from
+ *    main it will call C++ destructors and call exit to terminate.
+ */
+
+#ifdef __cplusplus
+#pragma cplusplus off
+#endif
+#pragma PID off
+#pragma PIC off
+
+#include "MCF5475.h"
+
+
+	/* imported data */
+
+extern unsigned long far _SP_INIT, _SDA_BASE;
+extern unsigned long far _START_BSS, _END_BSS;
+extern unsigned long far _START_SBSS, _END_SBSS;
+extern unsigned long far __DATA_RAM, __DATA_ROM, __DATA_END;
+extern unsigned long far __Bas_base;
+
+extern unsigned long far __SUP_SP,__BOOT_FLASH;
+extern unsigned long far rt_mbar;
+
+	/* imported routines */
+
+extern int BaS(int, char **);
+
+	/* exported routines */
+extern void __initialize_hardware(void);
+extern void init_slt(void);
+
+
+void _startup(void)
+{
+	asm
+{
+	bra			warmstart
+	jmp			__BOOT_FLASH + 8					// ist zugleich reset vector 
+	/* disable interrupts */
+warmstart:	
+// disable interrupts 
+	move.w     	#0x2700,sr
+// Initialize MBAR
+	MOVE.L		#__MBAR,D0
+	MOVEC		D0,MBAR
+	move.l		d0,rt_mbar
+// mmu off   	
+	move.l		#__MMUBAR+1,d0	
+	movec		d0,MMUBAR				//mmubar setzen
+	clr.l		d0
+	move.l		d0,MCF_MMU_MMUCR		// mmu off
+        /* Initialize RAMBARs: locate SRAM and validate it */ \
+   	move.l 		#__RAMBAR0 + 0x7,d0		// supervisor only
+   	movec      	d0,RAMBAR0
+   	move.l 		#__RAMBAR1 + 0x1,d0		// on for all
+   	movec      	d0,RAMBAR1
+   	
+// STACKPOINTER AUF ENDE SRAM1
+	lea 			__SUP_SP,a7
+	
+// instruction cache on
+	move.l		#0x000C8100,d0
+ 	movec		d0,cacr
+ 	nop
+// initialize any hardware specific issues 
+	bra          __initialize_hardware   
+}
+}
\ No newline at end of file
diff --git a/firebeeV1/sources/startcf.h b/firebeeV1/sources/startcf.h
new file mode 100644
index 0000000..c538f16
--- /dev/null
+++ b/firebeeV1/sources/startcf.h
@@ -0,0 +1,47 @@
+/******************************************************************************
+  FILE    : startcf.h
+  PURPOSE : startup code for ColdFire
+  LANGUAGE: C
+
+
+  Notes:
+        1) Default entry point is _startup. 
+           . disable interrupts
+           . the SP is set to __SP_AFTER_RESET
+           . SP must be initialized to valid memory 
+             in case the memory it points to is not valid using MEMORY_INIT macro
+        2) __initialize_hardware is called. Here you can initialize memory and some peripherics
+           at this point global variables are not initialized yet
+        3) After __initialize_hardware memory is setup; initialize SP to _SP_INIT and perform 
+           needed initialisations for the language (clear memory, data rom copy).
+        4) void __initialize_system(void); is called
+           to allow additional hardware initialization (UART, GPIOs, etc...)
+        5) Jump to main 
+
+*/
+/********************************************************************************/
+
+#define cf_stack
+
+//#define ii_on
+#define halten
+#define halten_dbcc
+#define halten_and
+#define halten_add
+#define halten_sub
+#define halten_or
+#define halten_op
+#define halten_opc
+#define halten_movem
+#define halten_lea
+#define halten_shift
+#define halten_move
+#define halten_exg
+#define halten_movep
+#define halten_ewf
+
+#define DIP_SWITCH		(*(vuint8 *)(&__MBAR[0xA2C]))
+#define DIP_SWITCHa		___MBAR + 0xA2C
+
+#define sca_page_ID 	6
+
diff --git a/firebeeV1/sources/supervisor.s b/firebeeV1/sources/supervisor.s
new file mode 100644
index 0000000..29cd97f
--- /dev/null
+++ b/firebeeV1/sources/supervisor.s
@@ -0,0 +1,585 @@
+/********************************************************/
+/*   user/supervisor handler
+/********************************************************/
+
+.include "startcf.h"
+
+.extern _rt_cacr;
+.extern _rt_mod;
+.extern _rt_ssp;
+.extern _rt_usp;
+.extern ___MMUBAR
+
+/* Register read/write macros */
+#define MCF_MMU_MMUCR            			___MMUBAR
+#define MCF_MMU_MMUOR                       ___MMUBAR+0x04
+#define MCF_MMU_MMUSR                       ___MMUBAR+0x08
+#define MCF_MMU_MMUAR                       ___MMUBAR+0x10
+#define MCF_MMU_MMUTR                       ___MMUBAR+0x14
+#define MCF_MMU_MMUDR                       ___MMUBAR+0x18
+
+.public _privileg_violation
+.public cpusha
+
+.text
+_privileg_violation:
+	move.w		#0x2700,sr
+	lea			-12(a7),a7
+	movem.l		d0/a0/a5,(a7)
+#ifndef cf_stack
+	lea			0x52f0,a0
+	move.l		#0x20,(a0)		// set auf 68030
+#endif
+	lea			_rt_mod,a0		// zugriff setzen
+	tst.b		(a0)			// vom rt_supervisormodus?
+	bne			pv_work			// ja->
+// tatsächlich privileg violation
+	mov3q.l		#-1,(a0)		// sr_mod setzen
+	move.l		usp,a5			// usp holen
+	move.l		a5,8(a0)		// sichern
+	move.l		4(a0),a5		// rt_ssp holen
+#ifdef cf_stack
+	move.l		16(a7),-(a5)	// pc verschieben
+	move.l		12(a7),-(a5)	// sr verschieben
+	bset		#5,2(a5)		// auf super setzen
+#else
+	move.w		12(a7),-(a5)	// vector nr.
+	move.l		16(a7),-(a5)	// pc verschieben
+	move.w		14(a7),-(a5)	// sr verschieben
+	bset		#5,(a5)			// auf super
+#endif
+	move.l		a5,usp
+	move.l		12(a0),a5		// rt_vbr
+	lea			0x18(a5),a5		// vector
+	move.l		(a5),16(a7)		// vector privileg violation
+	movem.l		(a7),d0/a0/a5	// register zurück
+	lea			12(a7),a7
+	rte
+// privileg violation
+pv_work:	
+	move.l		16(a7),a5		// fault pc
+	move.b		(a5),d0			// fault code
+	cmp.b		#0x4e,d0		// 1.byt 0x4e
+	beq			pv_4e			// ja->
+	cmp.b		#0x46,d0		// 1.byt 0x46
+	beq			pv_46			// ja->
+	cmp.b		#0x40,d0		// 1.byt 0x40
+	beq			pv_40			// ja->
+	cmp.b		#0xf4,d0		// 0xf4?
+	beq			pv_f4
+	cmp.b		#0xf3,d0		// 0xf3?
+	beq			pv_f3
+// hierher sollt man nicht kommen
+	nop
+	halt
+	nop
+// code 0x4exx  ********************************************
+pv_4e:
+	move.b		1(a5),d0
+	cmp.b		#0x73,d0		//rte?
+	beq			pv_rte			//ja->
+	cmp.b		#0x72,d0		//stop?
+	beq			pv_stop			//ja->
+	cmp.b		#0x7B,d0		//movec?
+	beq			pv_movec		//ja->
+// move usp	
+	btst		#3,d0			// to or from
+	bne			pv_usp_to_ax	// usp -> ax
+// move ax->usp	
+	cmp.b		#0x60,d0		//movec?
+	beq			pv_a0_usp		//ja->
+	cmp.b		#0x61,d0		//movec?
+	beq			pv_a1_usp		//ja->
+	cmp.b		#0x62,d0		//movec?
+	beq			pv_a2_usp		//ja->
+	cmp.b		#0x63,d0		//movec?
+	beq			pv_a3_usp		//ja->
+	cmp.b		#0x64,d0		//movec?
+	beq			pv_a4_usp		//ja->
+	cmp.b		#0x65,d0		//movec?
+	beq			pv_a5_usp		//ja->
+	cmp.b		#0x66,d0		//movec?
+	beq			pv_a6_usp		//ja->
+	halt
+	bra			pv_a7_usp		//ja->
+// move usp->ax	
+pv_usp_to_ax:
+	move.l		8(a0),a5		//rt_usp holen
+	cmp.b		#0x68,d0		//movec?
+	beq			pv_usp_a0		//ja->
+	cmp.b		#0x69,d0		//movec?
+	beq			pv_usp_a1		//ja->
+	cmp.b		#0x6a,d0		//movec?
+	beq			pv_usp_a2		//ja->
+	cmp.b		#0x6b,d0		//movec?
+	beq			pv_usp_a3		//ja->
+	cmp.b		#0x6c,d0		//movec?
+	beq			pv_usp_a4		//ja->
+	cmp.b		#0x6d,d0		//movec?
+	beq			pv_usp_a5		//ja->
+	cmp.b		#0x6e,d0		//movec?
+	beq			pv_usp_a6		//ja->
+// usp->a7
+	move.l		a5,4(a0)		// rt usp -> rt ssp
+	move.l		a5,usp			// und setzen
+	bra			pv_usp_ax
+// a0->usp
+pv_a0_usp:		move.l 4(a7),a5
+	bra			pv_ax_usp	
+// a1->usp
+pv_a1_usp:		move.l a1,a5
+	bra			pv_ax_usp	
+// a2->usp
+pv_a2_usp:		move.l a2,a5
+	bra			pv_ax_usp	
+// a3->usp
+pv_a3_usp:		move.l a3,a5
+	bra			pv_ax_usp	
+// a4->usp
+pv_a4_usp:		move.l a4,a5
+	bra			pv_ax_usp	
+// a5->usp
+pv_a5_usp:		move.l 8(a7),a5
+	bra			pv_ax_usp	
+// a6->usp
+pv_a6_usp:		move.l a6,a5
+	bra			pv_ax_usp	
+// a7->usp
+pv_a7_usp:		move.l 4(a0),a5		// rt_ssp -> a5
+pv_ax_usp:
+	move.l		a5,8(a0)			// usp -> rt_usp
+	addq.l		#2,16(a7)			// next
+	movem.l		(a7),d0/a0/a5		// register zurück
+	lea			12(a7),a7
+	rte
+// usp->a0
+pv_usp_a0:
+	move.l		a5,4(a7)
+	bra			pv_usp_ax
+pv_usp_a1:
+	move.l		a5,a1
+	bra			pv_usp_ax
+pv_usp_a2:
+	move.l		a5,a2
+	bra			pv_usp_ax
+pv_usp_a3:
+	move.l		a5,a3
+	bra			pv_usp_ax
+pv_usp_a4:
+	move.l		a5,a4
+	bra			pv_usp_ax
+pv_usp_a5:
+	move.l		a5,8(a7)
+	bra			pv_usp_ax
+pv_usp_a6:
+	move.l		a5,a6
+pv_usp_ax:
+	addq.l		#2,16(a7)		// next
+	movem.l		(a7),d0/a0/a5	// register zurück
+	lea			12(a7),a7
+	rte
+// rte
+pv_rte:
+	move.l		usp,a5
+#ifdef cf_stack
+	move.l		(a5)+,12(a7)	// sr verschieben
+	move.l		(a5)+,16(a7)	// pc verschieben
+#else
+	move.w		(a5)+,14(a7)	// sr verschieben
+	move.l		(a5)+,16(a7)	// pc verschieben
+	move.w		(a5)+,12(a7)	// vector
+#endif
+	bclr		#5,14(a7)		// war es von super?
+	bne			pv_rte_sup		// ja->
+	clr.l		(a0)			// rt_mod auf user
+	move.l		a5,4(a0)		// rt_ssp sichern
+	move.l		8(a0),a5		// rt_usp holen
+pv_rte_sup:
+	move.l		a5,usp			// usp setzen
+	movem.l		(a7),d0/a0/a5	// register zurück
+	lea			12(a7),a7
+	rte
+// stop
+pv_stop:
+	move.b		2(a5),d0		// sr wert
+	and.l		#0x0700,d0		// int mask
+	cmp.w		#0x700,d0
+	beq			stop7
+	cmp.w		#0x600,d0
+	beq			stop6
+	cmp.w		#0x500,d0
+	beq			stop5
+	cmp.w		#0x400,d0
+	beq			stop4
+	cmp.w		#0x300,d0
+	beq			stop3
+	cmp.w		#0x200,d0
+	beq			stop2
+	cmp.w		#0x100,d0
+	beq			stop1
+	stop		#0x2000
+	bra			stop_weiter
+stop1:
+	stop		#0x2100
+	bra			stop_weiter
+stop2:
+	stop		#0x2200
+	bra			stop_weiter
+stop3:
+	stop		#0x2300
+	bra			stop_weiter
+stop4:
+	stop		#0x2400
+	bra			stop_weiter
+stop5:
+	stop		#0x2500
+	bra			stop_weiter
+stop6:
+	stop		#0x2600
+	bra			stop_weiter
+stop7:
+	stop		#0x2700
+stop_weiter:
+	addq.l		#4,16(a7)		// next 
+	movem.l		(a7),d0/a0/a5	// register zurück
+	lea			12(a7),a7
+	rte
+// movec ???????
+pv_movec:
+	move.w		2(a5),d0			// 2.word holen
+	and.l		#0xf000,d0
+	btst		#15,d0				// addressregister?
+	bne			pv_movec_ax			// ja->
+	tst.w		d0					// d0?
+	bne			pvm_d1				// nein->
+	move.l		(a7),-(a7)			// d0 holen und sichern
+	bra			pvm_me
+pvm_d1:
+	cmp.w		#0x1000,d0			// d1?
+	bne			pvm_d2				// nein->
+	move.l		d1,-(a7)			// d1 holen und sichern
+	bra			pvm_me				// fertig machen
+pvm_d2:
+	cmp.w		#0x2000,d0			// d1?
+	bne			pvm_d3				// nein->
+	move.l		d2,-(a7)			// d2 holen und sichern
+	bra			pvm_me				// fertig machen
+pvm_d3:
+	cmp.w		#0x3000,d0			// d1?
+	bne			pvm_d4				// nein->
+	move.l		d3,-(a7)			// d3 holen und sichern
+	bra			pvm_me				// fertig machen
+pvm_d4:
+	cmp.w		#0x4000,d0			// d1?
+	bne			pvm_d5				// nein->
+	move.l		d4,-(a7)			// d4 holen und sichern
+	bra			pvm_me				// fertig machen
+pvm_d5:
+	cmp.w		#0x5000,d0			// d1?
+	bne			pvm_d6				// nein->
+	move.l		d5,-(a7)			// d5 holen und sichern
+	bra			pvm_me				// fertig machen
+pvm_d6:
+	cmp.w		#0x6000,d0			// d1?
+	bne			pvm_d7				// nein->
+	move.l		d6,-(a7)			// d6 holen und sichern
+	bra			pvm_me				// fertig machen
+pvm_d7:
+	move.l		d7,-(a7)			// d7 holen und sichern
+	bra			pvm_me				// fertig machen
+pv_movec_ax:
+	cmp.w		#0x8000,d0			// a0?
+	bne			pvm_a1				// nein->
+	move.l		4(a7),-(a7)			// a0 holen und sichern
+	bra			pvm_me				// fertig machen
+pvm_a1:
+	cmp.w		#0x9000,d0			// a0?
+	bne			pvm_a2				// nein->
+	move.l		a1,-(a7)			// a1 holen und sichern
+	bra			pvm_me				// fertig machen
+pvm_a2:
+	cmp.w		#0xa000,d0			// a0?
+	bne			pvm_a3				// nein->
+	move.l		a2,-(a7)			// a2 holen und sichern
+	bra			pvm_me				// fertig machen
+pvm_a3:
+	cmp.w		#0xb000,d0			// a0?
+	bne			pvm_a4				// nein->
+	move.l		a3,-(a7)			// a3 holen und sichern
+	bra			pvm_me				// fertig machen
+pvm_a4:
+	cmp.w		#0xc000,d0			// a0?
+	bne			pvm_a5				// nein->
+	move.l		a4,-(a7)			// a4 holen und sichern
+	bra			pvm_me				// fertig machen
+pvm_a5:
+	cmp.w		#0xd000,d0			// a0?
+	bne			pvm_a6				// nein->
+	move.l		8(a7),-(a7)			// a5 holen und sichern
+	bra			pvm_me				// fertig machen
+pvm_a6:
+	cmp.w		#0xe000,d0			// a0?
+	bne			pvm_a7				// nein->
+	move.l		a6,-(a7)			// a6 holen und sichern
+	bra			pvm_me				// fertig machen
+pvm_a7:
+	move.l		4(a7),-(a7)			// a7 holen und sichern
+pvm_me:
+	move.w		2(a5),d0			// 2.word holen
+	andi.l		#0xf,d0				// nur letzte 4 bits
+	move.l		(a7)+,8(a0,d0*4)	// start bei +8, *4 weil long
+	jsr			cpusha				// gesammten cache flushen
+	rte
+// code 0x46xx *****************************************
+pv_46:	
+	move.b		1(a5),d0	
+	cmp.b		#0xfc,d0		//#d16->sr
+	beq			im_sr			//ja->
+//move dx->sr (sr und rt_mod ist supervisor sonst wäre es privileg violation
+	cmp.b		#0xc0,d0		//d0->sr?
+	bne			d1_sr			//nein->
+	move.w		2(a7),d0		//hier ist d0 gesichert
+	bra			d0_sr
+d1_sr:
+	cmp.b		#0xc1,d0		//d1->sr?
+	bne			d2_sr			//nein->
+	move.w		d1,d0
+	bra			d0_sr
+d2_sr:
+	cmp.b		#0xc2,d0		//d2->sr?
+	bne			d3_sr
+	move.w		d2,d0
+	bra			d0_sr
+d3_sr:
+	cmp.b		#0xc3,d0		//d3->sr?
+	bne			d4_sr
+	move.w		d3,d0
+	bra			d0_sr
+d4_sr:
+	cmp.b		#0xc4,d0		//d4->sr?
+	bne			d5_sr
+	move.w		d4,d0
+	bra			d0_sr
+d5_sr:
+	cmp.b		#0xc5,d0		//d5->sr?
+	bne			d6_sr
+	move.w		d5,d0
+	bra			d0_sr
+d6_sr:
+	cmp.b		#0xc6,d0		//d6->sr?
+	bne			d7_sr
+	move.w		d6,d0
+	bra			d0_sr
+d7_sr:
+	move.w		d7,d0			// sonst d7->sr
+d0_sr:
+	addq.l		#2,16(a7)		// next 
+	bra			pv_set_sr_end	// fertig machen
+// move #xxxx,sr	
+im_sr:
+	addq.l		#4,16(a7)		// next 
+	move.w		2(a5),d0		// data
+pv_set_sr_end:
+	bclr		#13,d0			// war super?
+	bne			pv_sre2			// ja ->
+	clr.l		(a0)
+	move.l		usp,a5			// usp
+	move.l		a5,4(a0)		// rt_ssp speichern
+	move.l		8(a0),a5		// rt_usp holen
+	move.l		a5,usp			// setzen
+pv_sre2:
+	move.w		d0,14(a7)		// sr setzen
+	movem.l		(a7),d0/a0/a5	// register zurück
+	lea			12(a7),a7
+	rte
+// code 0x40xx  *****************************************
+pv_40:
+	move.b		1(a5),d0		// 2.byt
+	cmp.b		#0xe7,d0
+	beq			pv_strldsr
+// move sr->dx
+	move.l		12(a7),a5		// sr holen
+	tst.b		(a0)			// super?
+	beq			pv_40_user		// nein?
+	lea			0x2000(a5),a5	// super zuaddieren
+pv_40_user:
+	cmp.b		#0xc0,d0
+	bne			nsr_d1
+	move.w		a5,2(a7)
+	bra			sr_dx_end
+nsr_d1:
+	cmp.b		#0xc1,d0
+	bne			nsr_d2
+	move.w		a5,d1
+	bra			sr_dx_end
+nsr_d2:
+	cmp.b		#0xc2,d0
+	bne			nsr_d3
+	move.w		a5,d2
+	bra			sr_dx_end
+nsr_d3:
+	cmp.b		#0xc3,d0
+	bne			nsr_d4
+	move.w		a5,d3
+	bra			sr_dx_end
+nsr_d4:
+	cmp.b		#0xc4,d0
+	bne			nsr_d5
+	move.w		a5,d4
+	bra			sr_dx_end
+nsr_d5:
+	cmp.b		#0xc5,d0
+	bne			nsr_d6
+	move.w		a5,d5
+	bra			sr_dx_end
+nsr_d6:
+	cmp.b		#0xc6,d0
+	bne			nsr_d7
+	move.w		a5,d6
+	bra			sr_dx_end
+nsr_d7:
+	move.w		a5,d7
+	halt
+sr_dx_end:
+	addq.l		#2,16(a7)		// next 
+	movem.l		(a7),d0/a0/a5	// register zurück
+	lea			12(a7),a7
+	rte
+// strldsr
+pv_strldsr:
+	nop
+	halt
+	nop
+// code 0xf4xx  ***********************************
+pv_f4:
+	addq.l		#2,16(a7)			// next instr
+	move.b		1(a5),d0			// 2.byt
+	bsr			pv_ax_a0			// richtiges register
+	move.b		1(a5),d0			// 2.byt
+	cmp.b		#0x30,d0			// >0xf430
+	blo			pv_intouch
+// cpushl
+	cpushl		bc,(a0)
+	movem.l		(a7),d0/a0/a5
+	lea			12(a7),a7
+	rte
+pv_intouch:
+	intouch		(a0)
+	movem.l		(a7),d0/a0/a5
+	lea			12(a7),a7
+	rte
+// subroutine register ax->a0
+pv_ax_a0:
+	and.l		#0x7,d0				// nur register nummer
+	subq.l		#1,d0
+	bmi			pv_a0_a0
+	subq.l		#1,d0
+	bmi			pv_a1_a0
+	subq.l		#1,d0
+	bmi			pv_a2_a0
+	subq.l		#1,d0
+	bmi			pv_a3_a0
+	subq.l		#1,d0
+	bmi			pv_a4_a0
+	subq.l		#1,d0
+	bmi			pv_a5_a0
+	subq.l		#1,d0
+	bmi			pv_a6_a0
+	move.l		a7,a0
+	rts
+pv_a0_a0:
+	move.l		8(a7),a0
+	rts
+pv_a1_a0:
+	move.l		a1,a0
+	rts
+pv_a2_a0:
+	move.l		a2,a0
+	rts
+pv_a3_a0:
+	move.l		a3,a0
+	rts
+pv_a4_a0:
+	move.l		a4,a0
+	rts
+pv_a5_a0:
+	move.l		12(a7),a0
+	rts
+pv_a6_a0:
+	move.l		a6,a0
+	rts
+// code 0xf4xx  ***********************************
+pv_f3:
+	addq.l		#2,16(a7)			// next instr
+	move.b		1(a5),d0			// 2. byt
+	cmp.b		#0x40,d0
+	bgt			pv_frestore
+//fsave (ax) oder d16(ax)
+	jsr			pv_ax_a0			// richtiges register holen
+	move.b		1(a5),d0			
+	cmp.b		#0x20,d0
+// +d16
+	blt			pv_f3_ax
+	addq.l		#2,16(a7)			// next instr
+	clr.l		d0
+	move.w		2(a0),d0			// d16
+	add.l		d0,a0
+pv_f3_ax:
+	fsave		(a0)	
+	movem.l		(a7),d0/a0/a5
+	lea			12(a7),a7
+	rte
+pv_frestore:
+	cmp.b		#0x7a,d0
+	beq			pv_f_d16pc
+// frestore (ax) oder d16(ax)
+	jsr			pv_ax_a0			// richtiges register holen
+	move.b		1(a5),d0			
+	cmp.b		#0x60,d0
+	blt			pv_frestore_ax
+pv_fend:
+	addq.l		#2,16(a7)			// next instr
+	clr.l		d0
+	move.w		2(a0),d0			// d16
+	add.l		d0,a0
+pv_frestore_ax:
+	frestore	(a0)	
+	movem.l		(a7),d0/a0/a5
+	lea			12(a7),a7
+	rte
+// frestore d16(pc)
+pv_f_d16pc:
+	move.l		16(a7),a0			// pc holen
+	bra			pv_fend
+//*****************************************************
+cpusha:	 
+ 	lea			-16(a7),a7
+	movem.l		d0-d2/a0,(a7)		// register sichern
+	move		sr,d2
+	nop
+	move		#0x2700,sr			// no interrupts
+
+	clr.l		d0
+	clr.l		d1
+	move.l		d0,a0
+cfa_setloop:
+	cpushl		bc,(a0)				// flush
+	lea			0x10(a0),a0			// index+1
+	addq.l		#1,d1				// index+1
+	cmpi.w		#512,d1				// alle sets?
+	bne			cfa_setloop			// nein->
+	clr.l		d1
+	addq.l		#1,d0
+	move.l		d0,a0
+	cmpi.w		#4,d0				// all ways?
+	bne			cfa_setloop			// nein->
+	nop
+	move.l		_rt_cacr,d0			// holen
+	movec		d0,cacr				// setzen
+	move.w		d2,sr				// alte interrupt maske
+	movem.l		(a7),d0-d2/a0		// register zurück
+	lea			16(a7),a7
+
+	rts	
+//*******************************************************33
+
diff --git a/firebeeV1/sources/sysinit.c b/firebeeV1/sources/sysinit.c
new file mode 100644
index 0000000..9d75090
--- /dev/null
+++ b/firebeeV1/sources/sysinit.c
@@ -0,0 +1,833 @@
+/*
+ * File:		sysinit.c
+ * Purpose:		Power-on Reset configuration of the COLDARI board.
+ *
+ * Notes: 
+ *
+ */
+#include "MCF5475.h"
+#include "startcf.h"
+
+extern unsigned long far __VRAM;
+extern unsigned long far __Bas_base;
+extern unsigned long far BaS;
+extern unsigned long far __BOOT_FLASH[]; 
+extern int copy_end();
+extern int warte_10us();
+extern int warte_1ms();
+extern int warte_10ms();
+extern int warte_50us();
+
+extern unsigned long far rt_cacr;
+
+/********************************************************************/
+// init SLICE TIMER 0 
+// all  = 32.538 sec = 30.736mHz
+// BYT0 = 127.1ms/tick = 7.876Hz   offset 0
+// BYT1 = 496.5us/tick = 2.014kHz  offset 1
+// BYT2 = 1.939us/tick = 515.6kHz  offset 2
+// BYT3 = 7.576ns/tick = 132.00MHz offset 3
+// count down!!! 132MHz!!!
+/********************************************************************/
+
+void init_slt(void)
+{
+	asm
+	{
+		lea 		MCF_SLT0_STCNT,a0
+		move.l		#0xffffffff,(a0)
+		lea 		MCF_SLT0_SCR,a0
+		move.b		#0x05,(a0)
+			
+	}
+		MCF_PSC0_PSCTB_8BIT = 'SLT ';
+		MCF_PSC0_PSCTB_8BIT = 'OK! ';
+		MCF_PSC0_PSCTB_8BIT = 0x0a0d;
+}
+
+/********************************************************************/
+// init GPIO ETC.
+/********************************************************************/
+
+void init_gpio(void)
+{
+
+
+// PAD REGISTER P.S.:FBCTL UND FBCS WERDEN RICHTIG GESETZT BEIM RESET 
+	MCF_PAD_PAR_DMA 		= 0b11111111;			// NORMAL ALS DREQ DACK
+	MCF_PAD_PAR_FECI2CIRQ 	= 0b1111001111001111;	// FEC0 NORMAL, FEC1 ALS I/O, I2C, #INT5..6
+	MCF_PAD_PAR_PCIBG 		= 0b0000001000111111;	// #PCI_BG4=#TBST,#PIC_BG3=I/O,#PCI_BG2..0=NORMAL
+	MCF_PAD_PAR_PCIBR 		= 0b0000001000111111;	// #PCI_BR4=#INT4,#PIC_BR3=INPUT,#PCI_BR2..0=NORMAL
+	MCF_PAD_PAR_PSC3		= 0b00001100;			// PSC3=TX,RX CTS+RTS=I/O
+	MCF_PAD_PAR_PSC1		= 0b11111100;			// PSC1 NORMAL SERIELL
+	MCF_PAD_PAR_PSC0		= 0b11111100;			// PSC0 NORMAL SERIELL
+	MCF_PAD_PAR_DSPI		= 0b0001111111111111;	// DSPI NORMAL
+	MCF_PAD_PAR_TIMER		= 0b00101101;			// TIN3..2=#IRQ3..2;TOUT3..2=NORMAL
+// ALLE OUTPUTS NORMAL LOW
+
+// ALLE DIR NORMAL INPUT = 0
+	MCF_GPIO_PDDR_FEC1L		= 0b00011110;			// OUT: 4=LED,3=PRG_DQ0,2=#FPGA_CONFIG,1=PRG_CLK(FPGA)	
+
+}
+
+/********************************************************************/
+// init seriel
+/********************************************************************/
+
+void init_seriel(void)
+{
+		
+// PSC0: SER1 ----------
+ 		MCF_PSC0_PSCSICR = 0;		// UART
+		MCF_PSC0_PSCCSR = 0xDD;
+		MCF_PSC0_PSCCTUR = 0x00;	 
+		MCF_PSC0_PSCCTLR = 36;		// BAUD RATE = 115200
+		MCF_PSC0_PSCCR = 0x20;
+		MCF_PSC0_PSCCR = 0x30;
+		MCF_PSC0_PSCCR = 0x40;
+		MCF_PSC0_PSCCR = 0x50;
+		MCF_PSC0_PSCCR = 0x10;
+		MCF_PSC0_PSCIMR = 0x8700;
+		MCF_PSC0_PSCACR = 0x03;
+		MCF_PSC0_PSCMR1= 0xb3;
+		MCF_PSC0_PSCMR2= 0x07;
+		MCF_PSC0_PSCRFCR = 0x0F;
+		MCF_PSC0_PSCTFCR = 0x0F;
+		MCF_PSC0_PSCRFAR = 0x00F0;
+		MCF_PSC0_PSCTFAR = 0x00F0;
+		MCF_PSC0_PSCOPSET = 0x01;
+		MCF_PSC0_PSCCR = 0x05;
+// PSC3: PIC ----------
+ 		MCF_PSC3_PSCSICR = 0;		// UART
+		MCF_PSC3_PSCCSR = 0xDD;
+		MCF_PSC3_PSCCTUR = 0x00;	 
+		MCF_PSC3_PSCCTLR = 36;		// BAUD RATE = 115200
+		MCF_PSC3_PSCCR = 0x20;
+		MCF_PSC3_PSCCR = 0x30;
+		MCF_PSC3_PSCCR = 0x40;
+		MCF_PSC3_PSCCR = 0x50;
+		MCF_PSC3_PSCCR = 0x10;
+		MCF_PSC3_PSCIMR = 0x0200;	// receiver interrupt enable
+		MCF_PSC3_PSCACR = 0x03;
+		MCF_PSC3_PSCMR1= 0xb3;
+		MCF_PSC3_PSCMR2= 0x07;
+		MCF_PSC3_PSCRFCR = 0x0F;
+		MCF_PSC3_PSCTFCR = 0x0F;
+		MCF_PSC3_PSCRFAR = 0x00F0;
+		MCF_PSC3_PSCTFAR = 0x00F0;
+		MCF_PSC3_PSCOPSET = 0x01;
+		MCF_PSC3_PSCCR = 0x05;
+		MCF_INTC_ICR32 = 0x3F;		//MAXIMALE PRIORITY/**********/
+
+		MCF_PSC0_PSCTB_8BIT = 0x0a0d;
+		MCF_PSC0_PSCTB_8BIT = 'SERI';
+		MCF_PSC0_PSCTB_8BIT = 'AL O';
+		MCF_PSC0_PSCTB_8BIT = 'K!  ';
+		MCF_PSC0_PSCTB_8BIT = 0x0a0d;	
+}
+/********************************************************************/
+   /* Initialize DDR DIMMs on the EVB board */
+/********************************************************************/
+   /*
+    * Check to see if the SDRAM has already been initialized
+    * by a run control tool
+    */
+
+
+void init_ddram(void)
+{
+ 		MCF_PSC0_PSCTB_8BIT = 'DDRA';
+  if (!(MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF))
+   {
+
+	/* Basic configuration and initialization */
+	MCF_SDRAMC_SDRAMDS 	= 0x000002AA;	// SDRAMDS configuration
+	MCF_SDRAMC_CS0CFG 	= 0x0000001A;   // SDRAM CS0 configuration (128Mbytes 0000_0000 - 07FF_FFFF)
+	MCF_SDRAMC_CS1CFG 	= 0x0800001A;   // SDRAM CS1 configuration (128Mbytes 0800_0000 - 0FFF_FFFF)
+	MCF_SDRAMC_CS2CFG 	= 0x1000001A;   // SDRAM CS2 configuration (128Mbytes 1000_0000 - 07FF_FFFF)
+	MCF_SDRAMC_CS3CFG 	= 0x1800001A;   // SDRAM CS3 configuration (128Mbytes 1800_0000 - 1FFF_FFFF)
+//  	MCF_SDRAMC_SDCFG1 	= 0x53722938;   // SDCFG1
+	MCF_SDRAMC_SDCFG1 	= 0x73622830;   // SDCFG1
+//  	MCF_SDRAMC_SDCFG2 	= 0x24330000;   // SDCFG2
+	MCF_SDRAMC_SDCFG2 	= 0x46770000;   // SDCFG2
+//   	MCF_SDRAMC_SDCR 	= 0xE10F0002;   // SDCR + IPALL
+   	MCF_SDRAMC_SDCR 	= 0xE10D0002;   // SDCR + IPALL
+   	MCF_SDRAMC_SDMR 	= 0x40010000;   // SDMR (write to LEMR)
+//   	MCF_SDRAMC_SDMR 	= 0x05890000;   // SDRM (write to LMR)
+   	MCF_SDRAMC_SDMR 	= 0x048D0000;   // SDRM (write to LMR)
+//   	MCF_SDRAMC_SDCR 	= 0xE10F0002;   // SDCR + IPALL
+   	MCF_SDRAMC_SDCR 	= 0xE10D0002;   // SDCR + IPALL
+//   	MCF_SDRAMC_SDCR 	= 0xE10F0004;   // SDCR + IREF (first refresh)
+   	MCF_SDRAMC_SDCR 	= 0xE10D0004;   // SDCR + IREF (first refresh)
+//   	MCF_SDRAMC_SDCR 	= 0xE10F0004;   // SDCR + IREF (second refresh)
+  	MCF_SDRAMC_SDCR 	= 0xE10D0004;   // SDCR + IREF (second refresh)
+///   	MCF_SDRAMC_SDMR 	= 0x01890000;   // SDMR (write to LMR)
+   	MCF_SDRAMC_SDMR 	= 0x008D0000;   // SDMR (write to LMR)
+//   	MCF_SDRAMC_SDCR 	= 0x710F0F00;   // SDCR (lock SDMR and enable refresh)
+   	MCF_SDRAMC_SDCR 	= 0x710D0F00;   // SDCR (lock SDMR and enable refresh)
+   }
+		MCF_PSC0_PSCTB_8BIT = 'M OK';
+		MCF_PSC0_PSCTB_8BIT = '!   ';
+		MCF_PSC0_PSCTB_8BIT = 0x0a0d;
+}
+/********************************************************************/
+	/* init FB_CSx /*
+/********************************************************************/
+void init_fbcs()
+{
+		MCF_PSC0_PSCTB_8BIT = 'FBCS';
+		/* Flash */
+ 	MCF_FBCS0_CSAR 	= 0xE0000000;						// FLASH ADRESS
+ 	MCF_FBCS0_CSCR 	= 0x00001180 						// 16 bit 4ws aa
+  					| MCF_FBCS_CSCR_RDAH(1);			// READ HOLD TIME 1 CYCLUS 
+ 	MCF_FBCS0_CSMR 	= 0x007F0001;					 	// 8MB on
+		
+	MCF_FBCS1_CSAR	= 0xFFF00000;						// ATARI I/O ADRESS
+	MCF_FBCS1_CSCR 	= MCF_FBCS_CSCR_PS_16 				// 16BIT PORT 
+					| MCF_FBCS_CSCR_WS(8)				// DEFAULT 8WS
+ 					| MCF_FBCS_CSCR_RDAH(1)				// READ HOLD TIME 1 CYCLUS 
+ 					| MCF_FBCS_CSCR_AA;					// AA 
+	MCF_FBCS1_CSMR 	= (MCF_FBCS_CSMR_BAM_1M 
+					| MCF_FBCS_CSMR_V);
+
+	MCF_FBCS2_CSAR	= 0xF0000000;						// NEUER I/O ADRESS-BEREICH
+	MCF_FBCS2_CSCR 	= MCF_FBCS_CSCR_PS_32				// 32BIT PORT
+					| MCF_FBCS_CSCR_WS(8)				// DEFAULT 4WS
+  					| MCF_FBCS_CSCR_RDAH(1)				// READ HOLD TIME 1 CYCLUS 
+					| MCF_FBCS_CSCR_AA;					// AA 
+	MCF_FBCS2_CSMR 	= (MCF_FBCS_CSMR_BAM_128M 			// F000'0000-F7FF'FFFF
+					| MCF_FBCS_CSMR_V);
+ 	
+	MCF_FBCS3_CSAR	= 0xF8000000;						// NEUER I/O ADRESS-BEREICH
+	MCF_FBCS3_CSCR 	= MCF_FBCS_CSCR_PS_16				// 16BIT PORT
+					| MCF_FBCS_CSCR_WS(0)				// 0WS
+ 					| MCF_FBCS_CSCR_RDAH(1)				// READ HOLD TIME 1 CYCLUS 
+					| MCF_FBCS_CSCR_AA;					// AA 
+	MCF_FBCS3_CSMR 	= (MCF_FBCS_CSMR_BAM_64M 			// F800'0000-FBFF'FFFF
+					| MCF_FBCS_CSMR_V);
+ 
+	MCF_FBCS4_CSAR	= 0x40000000;						// VIDEO RAM BEREICH, #FB_CS3 WIRD NICHT BENÜTZT, DECODE DIREKT AUF DEM FPGA
+	MCF_FBCS4_CSCR 	= MCF_FBCS_CSCR_PS_32				// 32BIT PORT
+					| MCF_FBCS_CSCR_BSTR				// BURST READ ENABLE
+					| MCF_FBCS_CSCR_BSTW;				// BURST WRITE ENABLE
+	MCF_FBCS4_CSMR 	= (MCF_FBCS_CSMR_BAM_1G 			// 4000'0000-7FFF'FFFF
+					| MCF_FBCS_CSMR_V);
+
+		MCF_PSC0_PSCTB_8BIT = ' OK!';
+		MCF_PSC0_PSCTB_8BIT = 0x0a0d;
+}
+
+/********************************************************************/
+	/* FPGA LADEN /*
+/********************************************************************/
+
+
+void init_fpga(void)
+{
+
+		MCF_PSC0_PSCTB_8BIT = 'FPGA';
+asm
+	{
+  		lea			MCF_GPIO_PODR_FEC1L,a1				// register adresse:write
+  		lea			MCF_GPIO_PPDSDR_FEC1L,a2			// reads
+  		bclr		#1,(a1)								// clk auf low
+		bclr		#2,(a1)								// #config=low 
+test_nSTATUS:
+		btst		#0,(a2)								// nSTATUS==0
+		bne			test_nSTATUS						// nein->
+		btst		#5,(a2)								// conf done==0
+		bne			test_nSTATUS						// nein->
+		jsr			warte_10us							// warten
+		bset		#2,(a1)								// #config=high
+		jsr			warte_10us							// warten
+test_STATUS:
+		btst		#0,(a2)								// status high?
+		beq			test_STATUS							// nein->
+		jsr			warte_10us							// warten
+
+  		lea			0xE0700000,a0						// startadresse fpga daten
+word_send_loop:
+		cmp.l		#0xE0800000,a0
+		bgt			fpga_error
+		move.b		(a0)+,d0							// 32 bit holen
+		moveq		#8,d1								// 32 bit ausgeben
+bit_send_loop:
+		lsr.l		#1,d0								// bit rausschieben
+		bcs			bit_is_1							
+		bclr		#3,(a1)
+		bra			bit_send
+bit_is_1:
+		bset		#3,(a1)
+bit_send:
+		bset		#1,(a1)								// clock=high
+		bclr		#1,(a1)								// clock=low
+		subq.l		#1,d1
+		bne			bit_send_loop						// wiederholen bis fertig
+		btst		#5,(a2)								// fpga fertig, conf_done=high?
+		beq			word_send_loop						// nein, next word->
+		move.l		#4000,d1
+overclk:
+		bset		#1,(a1)								// clock=high
+		nop
+		bclr		#1,(a1)								// clock=low
+		subq.l		#1,d1
+		bne			overclk								// weiter bis fertig
+  		bra			init_fpga_end
+
+//---------------------------------------------------------
+wait_pll:
+  		lea			MCF_SLT0_SCNT,a3
+  		move.l		(a3),d0
+  		move.l		#100000,d6			// ca 1ms
+wait_pll_loop:
+		tst.w		(a1)
+		bpl			wait_pll_ok
+		move.l		(a3),d1
+		sub.l		d0,d1
+		add.l		d6,d1
+		bpl			wait_pll_loop
+wait_pll_ok:
+		rts
+// fertig
+fpga_error:
+ 	}
+		MCF_PSC0_PSCTB_8BIT = ' NOT';
+init_fpga_end:
+		MCF_PSC0_PSCTB_8BIT = ' OK!';
+		MCF_PSC0_PSCTB_8BIT = 0x0a0d;
+
+// init pll		
+		MCF_PSC0_PSCTB_8BIT = 'PLL ';
+asm
+{
+		lea		0xf0000600,a0
+		lea		0xf0000800,a1
+		bsr		wait_pll
+		move.w	#27,0x48(a0)		// loopfilter r
+		bsr		wait_pll
+		move.w	#1,0x08(a0)			// charge pump I
+		bsr		wait_pll
+		move.w	#12,0x0(a0)			// N counter high = 12
+		bsr		wait_pll
+		move.w	#12,0x40(a0)		// N counter low = 12
+		bsr		wait_pll
+		move.w	#1,0x114(a0)		// ck1 bypass
+		bsr		wait_pll
+		move.w	#1,0x118(a0)		// ck2 bypass
+		bsr		wait_pll
+		move.w	#1,0x11c(a0)		// ck3 bypass
+		bsr		wait_pll
+		move.w	#1,0x10(a0)			// ck0 high = 1
+		bsr		wait_pll
+		move.w	#1,0x50(a0)			// ck0 low	= 1
+		
+		bsr		wait_pll
+		move.w	#1,0x144(a0)		// M odd division
+		bsr		wait_pll
+		move.w	#1,0x44(a0)			// M low = 1
+
+		bsr		wait_pll
+		move.w	#165,0x04(a0)		// M high = 145 = 146MHz
+
+		bsr		wait_pll
+		clr.b	(a1)				// set
+}
+		MCF_PSC0_PSCTB_8BIT = 'SET!';
+		MCF_PSC0_PSCTB_8BIT = 0x0a0d;
+}		
+
+/********************************************************************/
+	/* INIT VIDEO DDR RAM /*
+/********************************************************************/
+
+void init_video_ddr(void)
+{
+	asm
+	{
+
+// init video ram
+		moveq.l	#0xB,d0
+		move.w	d0,0xF0000400				//set cke=1, cs=1 config=1
+		nop
+		lea		__VRAM,a0					//zeiger auf video ram
+		nop
+		move.l	#0x00050400,(a0)			//IPALL
+		nop
+		move.l	#0x00072000,(a0)			//load EMR pll on
+		nop
+		move.l	#0x00070122,(a0)			//load MR: reset pll, cl=2 BURST=4lw
+		nop
+		move.l	#0x00050400,(a0)			//IPALL
+		nop
+		move.l	#0x00060000,(a0)			//auto refresh
+		nop
+		move.l	#0x00060000,(a0)			//auto refresh
+		nop
+		move.l	#0000070022,(a0)			//load MR dll on
+		nop
+		move.l	#0x01070002,d0				// fifo on, refresh on, ddrcs und cke on, video dac on,
+		move.l	d0,0xf0000400
+	}
+}
+
+/********************************************************************/
+	/* video mit auflösung 1280x1000 137MHz /*
+/********************************************************************/
+
+void video_1280_1024(void)
+{
+extern int wait_pll;
+
+	asm
+	{
+
+
+// SPEICHER FÜLLEM
+
+//testmuster 1
+		lea		__VRAM,a2
+		lea		__VRAM+0x600000,a3
+		clr.l	d0
+		move.l	#0x1000102,d1
+loop5:	move.l  d0,(a2)+
+		move.l  d0,(a2)+
+		move.l  d0,(a2)+
+		move.l  d0,(a2)+
+		move.l  d0,(a2)+
+		move.l  d0,(a2)+
+		move.l  d0,(a2)+
+		move.l  d0,(a2)+
+		move.l  d0,(a2)+
+		move.l  d0,(a2)+
+		move.l  d0,(a2)+
+		move.l  d0,(a2)+
+		move.l  d0,(a2)+
+		move.l  d0,(a2)+
+		move.l  d0,(a2)+
+		move.l  d0,(a2)+
+		move.l  d0,(a2)+
+		move.l  d0,(a2)+
+		move.l  d0,(a2)+
+		move.l  d0,(a2)+
+		add.l	d1,d0
+flo6:	cmp.l	a2,a3
+		bgt		loop5
+
+// screen setzen
+//horizontal 1280
+		lea		0xffff8282,a0
+		move.w	#1800,(a0)+
+		move.w	#1380,(a0)+
+		move.w	#99,(a0)+
+		move.w	#100,(a0)+
+		move.w	#1379,(a0)+
+		move.w	#1500,(a0)
+//vertical 1024
+		lea		0xffff82a2,a0
+		move.w	#1150,(a0)+
+		move.w	#1074,(a0)+
+		move.w	#49,(a0)+
+		move.w	#50,(a0)+
+		move.w	#1073,(a0)+
+		move.w	#1100,(a0)+
+// acp video on		
+		move.l	#0x01070207,d0
+		move.l	d0,0xf0000400
+		
+		
+// clut setzen
+		lea		0xf0000000,a0
+		move.l	#0xffffffff,(a0)+
+		move.l	#0xff,(a0)+
+		move.l	#0xff00,(a0)+
+		move.l	#0xff0000,(a0) 
+		
+//		halt
+		
+	}
+
+}
+/********************************************************************/
+	/* INIT PCI /*
+/********************************************************************/
+
+#define	 PCI_MEMORY_OFFSET	(0x80000000)
+#define	 PCI_MEMORY_SIZE	(0x40000000)
+#define	 PCI_IO_OFFSET		(0xD0000000)
+#define	 PCI_IO_SIZE		(0x10000000)
+
+
+void init_PCI(void)
+{
+
+		MCF_PSC0_PSCTB_8BIT = 'PCI ';
+asm
+	{
+ 	// Setup the arbiter
+		move.l #MCF_PCIARB_PACR_INTMPRI \
+		 + MCF_PCIARB_PACR_EXTMPRI(0x1F) \
+		 + MCF_PCIARB_PACR_INTMINTEN \
+		 + MCF_PCIARB_PACR_EXTMINTEN(0x1F),D0
+		move.l D0,MCF_PCIARB_PACR
+	// Setup burst parameters
+		move.l #MCF_PCI_PCICR1_CACHELINESIZE(4) + MCF_PCI_PCICR1_LATTIMER(32),D0
+		move.l D0,MCF_PCI_PCICR1
+		move.l #MCF_PCI_PCICR2_MINGNT(16) + MCF_PCI_PCICR2_MAXLAT(16),D0
+		move.l D0,MCF_PCI_PCICR2
+	// Turn on error signaling
+		move.l #MCF_PCI_PCIICR_TAE + MCF_PCI_PCIICR_IAE + MCF_PCI_PCIICR_REE + 32,D0
+		move.l D0,MCF_PCI_PCIICR
+		move.l #MCF_PCI_PCIGSCR_SEE,D0
+		or.l D0,MCF_PCI_PCIGSCR
+	// Configure Initiator Windows */
+		move.l #PCI_MEMORY_OFFSET + ((PCI_MEMORY_SIZE - 1) >> 8),D0
+		clr.w D0
+		move.l D0,MCF_PCI_PCIIW0BTAR // Initiator Window 0 Base / Translation Address Register
+	
+		move.l #PCI_IO_OFFSET+((PCI_IO_SIZE-1)>>8),D0
+		clr.w D0
+		move.l D0,MCF_PCI_PCIIW1BTAR // Initiator Window 1 Base / Translation Address Register
+
+		clr.l MCF_PCI_PCIIW2BTAR     // not used
+		
+		move.l #MCF_PCI_PCIIWCR_WINCTRL0_MEMRDLINE + MCF_PCI_PCIIWCR_WINCTRL1_IO,D0
+		move.l D0,MCF_PCI_PCIIWCR	   // Initiator Window Configuration Register
+
+	/* Clear PCI Reset and wait for devices to reset */
+		move.l #~MCF_PCI_PCIGSCR_PR,D0
+		and.l D0,MCF_PCI_PCIGSCR
+	}
+
+		MCF_PSC0_PSCTB_8BIT = 'OK! ';
+		MCF_PSC0_PSCTB_8BIT = 0x0a0d;
+}
+/********************************************************************/
+	/* test UPC720101 (USB) /*
+/********************************************************************/
+
+void test_upd720101(void)
+{
+
+		MCF_PSC0_PSCTB_8BIT = 'NEC ';
+asm
+	{
+	// SELECT UPD720101 AD17
+		MOVE.L	#MCF_PCI_PCICAR_E+MCF_PCI_PCICAR_DEVNUM(17)+MCF_PCI_PCICAR_FUNCNUM(0)+MCF_PCI_PCICAR_DWORD(0),D0
+		MOVE.L	D0,MCF_PCI_PCICAR
+		LEA		PCI_IO_OFFSET,A0
+		MOVE.L	(A0),D1	
+		move.l	#0x33103500,d0
+		cmp.l	d0,d1
+		beq		nec_ok
+	}
+		MCF_PSC0_PSCTB_8BIT = 'NOT ';
+		goto	nec_not_ok;
+nec_ok:
+	asm 
+	{
+		MOVE.L	#MCF_PCI_PCICAR_E+MCF_PCI_PCICAR_DEVNUM(17)+MCF_PCI_PCICAR_FUNCNUM(0)+MCF_PCI_PCICAR_DWORD(57),D0
+		MOVE.L	D0,MCF_PCI_PCICAR
+		move.b	#0x20,(a0)
+	}
+nec_not_ok:
+	asm 
+	{
+		MOVE.L	#MCF_PCI_PCICAR_DEVNUM(17)+MCF_PCI_PCICAR_FUNCNUM(0)+MCF_PCI_PCICAR_DWORD(57),D0
+		MOVE.L	D0,MCF_PCI_PCICAR
+	}
+		MCF_PSC0_PSCTB_8BIT = 'OK! ';
+		MCF_PSC0_PSCTB_8BIT = 0x0a0d;
+}
+
+/********************************************************************/
+	/* TFP410 (vdi) einschalten /*
+/********************************************************************/
+
+void vdi_on(void)
+{
+ 		uint8  RBYT, DBYT;
+ 		int versuche, startzeit;
+
+ 		 
+		MCF_PSC0_PSCTB_8BIT = 'DVI ';
+		MCF_I2C_I2FDR = 0x34;			// 100kHz standard
+		versuche = 0;
+loop_i2c:
+		if (versuche++>10) goto next;
+		MCF_I2C_I2ICR = 0x0;
+		MCF_I2C_I2CR = 0x0;
+		MCF_I2C_I2CR = 0xA;
+		RBYT = MCF_I2C_I2DR;
+		MCF_I2C_I2SR = 0x0;
+		MCF_I2C_I2CR = 0x0;
+		MCF_I2C_I2ICR = 0x01;
+ 
+		MCF_I2C_I2CR = 0xb0;
+		MCF_I2C_I2DR = 0x7A;
+		warte_100us();
+		if (MCF_I2C_I2SR!=0xa2 | MCF_I2C_I2CR!=0xb0) goto loop_i2c;
+		MCF_I2C_I2SR &= 0xfd;
+	
+		MCF_I2C_I2DR = 0x00;					// SUB ADRESS 0
+		while(!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)) ;
+		MCF_I2C_I2SR &= 0xfd;
+
+		MCF_I2C_I2CR |= 0x4;					// repeat start
+	
+		MCF_I2C_I2DR = 0x7b;					// beginn read
+		warte_100us();
+		if (MCF_I2C_I2SR!=0xa6 | MCF_I2C_I2CR!=0xb0) goto loop_i2c;
+		MCF_I2C_I2SR &= 0xfd;
+
+		MCF_I2C_I2CR &= 0xef;					// switch to rx	
+		DBYT = MCF_I2C_I2DR;					// dummy read
+
+		while(!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)) ;
+		MCF_I2C_I2SR &= 0xfd;
+		
+		MCF_I2C_I2CR |= 0x08;					// txak=1
+
+		warte_100us();
+		RBYT = MCF_I2C_I2DR;
+
+		while(!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)) ;
+		MCF_I2C_I2SR &= 0xfd;
+
+		MCF_I2C_I2CR = 0x0;						// stop
+		DBYT = MCF_I2C_I2DR;					// dummy read
+
+		if (RBYT!=0x4c) goto loop_i2c;
+		
+
+i2c_ok:
+		MCF_I2C_I2CR = 0x0;						// stop
+		MCF_I2C_I2SR = 0x0;						// clear sr
+		while((MCF_I2C_I2SR & MCF_I2C_I2SR_IBB)) ; // wait auf bus free
+		
+		MCF_I2C_I2CR = 0xb0;					// on tx master	
+		MCF_I2C_I2DR = 0x7A;
+		warte_50us();
+		if (MCF_I2C_I2SR!=0xa2 | MCF_I2C_I2CR!=0xb0) goto loop_i2c;
+		MCF_I2C_I2SR &= 0xfd;
+	
+		MCF_I2C_I2DR = 0x08;					// SUB ADRESS 8
+		while(!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)) ;
+		MCF_I2C_I2SR &= 0xfd;
+
+		MCF_I2C_I2DR = 0xbf;					// ctl1: power on, T:M:D:S: enable
+		while(!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)) ;
+		MCF_I2C_I2SR &= 0xfd;
+
+		MCF_I2C_I2CR = 0x0;						// stop
+		MCF_I2C_I2SR = 0x0;						// clear sr
+
+		while((MCF_I2C_I2SR & MCF_I2C_I2SR_IBB)) ; // wait auf bus free
+
+		MCF_I2C_I2CR = 0xb0;
+		MCF_I2C_I2DR = 0x7A;
+		warte_50us();
+		if (MCF_I2C_I2SR!=0xa2 | MCF_I2C_I2CR!=0xb0) goto loop_i2c;
+		MCF_I2C_I2SR &= 0xfd;
+		
+		MCF_I2C_I2DR = 0x08;					// SUB ADRESS 8
+		while(!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)) ;
+		MCF_I2C_I2SR &= 0xfd;
+
+		MCF_I2C_I2CR |= 0x4;					// repeat start
+		MCF_I2C_I2DR = 0x7b;					// beginn read
+		warte_50us();
+		if (MCF_I2C_I2SR!=0xa6 | MCF_I2C_I2CR!=0xb0) goto loop_i2c;
+		MCF_I2C_I2SR &= 0xfd;
+
+		MCF_I2C_I2CR &= 0xef;					// switch to rx	
+
+		DBYT = MCF_I2C_I2DR;					// dummy read
+
+		while(!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)) ;
+		MCF_I2C_I2SR &= 0xfd;
+		
+		MCF_I2C_I2CR |= 0x08;					// txak=1
+
+		warte_50us();
+		RBYT = MCF_I2C_I2DR;
+
+		while(!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)) ;
+		MCF_I2C_I2SR &= 0xfd;
+
+		MCF_I2C_I2CR = 0x0;						// stop
+		DBYT = MCF_I2C_I2DR;					// dummy read
+
+		if (RBYT!=0xbf) goto loop_i2c;
+		
+		goto	dvi_ok;
+next:
+		MCF_I2C_I2CR = 0x0;						// stop
+		MCF_PSC0_PSCTB_8BIT = 'NOT ';
+dvi_ok:
+		MCF_PSC0_PSCTB_8BIT = 'OK! ';
+		MCF_PSC0_PSCTB_8BIT = 0x0a0d;
+}
+
+/********************************************************************/
+	/* AC97 /*
+/********************************************************************/
+void init_ac97(void)
+{
+// PSC2: AC97 ----------
+		int i,k,zm,x,va,vb,vc;
+
+		MCF_PSC0_PSCTB_8BIT = 'AC97';
+		MCF_PAD_PAR_PSC2 = MCF_PAD_PAR_PSC2_PAR_RTS2_RTS	// PSC2=TX,RX BCLK,CTS->AC'97
+						 | MCF_PAD_PAR_PSC2_PAR_CTS2_BCLK
+						 | MCF_PAD_PAR_PSC2_PAR_TXD2
+ 						 | MCF_PAD_PAR_PSC2_PAR_RXD2;  
+ 		MCF_PSC2_PSCMR1 = 0x0;		 	 
+		MCF_PSC2_PSCMR2 = 0x0;	
+		MCF_PSC2_PSCIMR = 0x0300;	 	 
+		MCF_PSC2_PSCSICR = 0x03;		//AC97		 
+		MCF_PSC2_PSCRFCR = 0x0f000000;
+		MCF_PSC2_PSCTFCR = 0x0f000000;
+		MCF_PSC2_PSCRFAR = 0x00F0;
+		MCF_PSC2_PSCTFAR = 0x00F0;
+
+	for ( zm = 0; zm<100000; zm++)		// wiederholen bis synchron
+	{
+		MCF_PSC2_PSCCR = 0x20;
+		MCF_PSC2_PSCCR = 0x30;
+		MCF_PSC2_PSCCR = 0x40;
+		MCF_PSC2_PSCCR = 0x05;
+// MASTER VOLUME -0dB
+		MCF_PSC2_PSCTB_AC97 = 0xE0000000; //START SLOT1 + SLOT2, FIRST FRAME
+		MCF_PSC2_PSCTB_AC97 = 0x02000000; //SLOT1:WR REG MASTER VOLUME adr 0x02
+		for ( i = 2; i<13; i++ )
+		{
+			MCF_PSC2_PSCTB_AC97 = 0x0; //SLOT2-12:WR REG ALLES 0
+		}
+ //	 read register
+ 		MCF_PSC2_PSCTB_AC97 = 0xc0000000; //START SLOT1 + SLOT2, FIRST FRAME
+ 		MCF_PSC2_PSCTB_AC97 = 0x82000000; //SLOT1:master volume
+		for ( i = 2; i<13; i++ )
+		{
+			MCF_PSC2_PSCTB_AC97 = 0x00000000; //SLOT2-12:RD REG ALLES 0
+		}
+		warte_50us();    
+		va = MCF_PSC2_PSCTB_AC97;
+		if ((va & 0x80000fff)==0x80000800)
+		{
+			vb = MCF_PSC2_PSCTB_AC97;
+ 			vc = MCF_PSC2_PSCTB_AC97;
+			if ((va & 0xE0000fff)==0xE0000800 & vb==0x02000000 & vc==0x00000000)
+			{
+				goto livo;
+			}
+		}
+	}
+	MCF_PSC0_PSCTB_8BIT = ' NOT';
+livo: 
+// AUX VOLUME ->-0dB 
+	MCF_PSC2_PSCTB_AC97 = 0xE0000000; //START SLOT1 + SLOT2, FIRST FRAME
+	MCF_PSC2_PSCTB_AC97 = 0x16000000; //SLOT1:WR REG AUX VOLUME adr 0x16
+	MCF_PSC2_PSCTB_AC97 = 0x06060000; //SLOT1:VOLUME 
+	for ( i = 3; i<13; i++ )
+	{
+		MCF_PSC2_PSCTB_AC97 = 0x0; //SLOT2-12:WR REG ALLES 0
+	}
+ 
+// line in VOLUME +12dB
+	MCF_PSC2_PSCTB_AC97 = 0xE0000000; //START SLOT1 + SLOT2, FIRST FRAME
+	MCF_PSC2_PSCTB_AC97 = 0x10000000; //SLOT1:WR REG MASTER VOLUME adr 0x02
+	for ( i = 2; i<13; i++ )
+	{
+		MCF_PSC2_PSCTB_AC97 = 0x0; //SLOT2-12:WR REG ALLES 0
+	}
+// cd in VOLUME 0dB
+	MCF_PSC2_PSCTB_AC97 = 0xE0000000; //START SLOT1 + SLOT2, FIRST FRAME
+	MCF_PSC2_PSCTB_AC97 = 0x12000000; //SLOT1:WR REG MASTER VOLUME adr 0x02
+	for ( i = 2; i<13; i++ )
+	{
+		MCF_PSC2_PSCTB_AC97 = 0x0; //SLOT2-12:WR REG ALLES 0
+	}
+// mono out VOLUME 0dB
+	MCF_PSC2_PSCTB_AC97 = 0xE0000000; //START SLOT1 + SLOT2, FIRST FRAME
+	MCF_PSC2_PSCTB_AC97 = 0x06000000; //SLOT1:WR REG MASTER VOLUME adr 0x02
+	MCF_PSC2_PSCTB_AC97 = 0x00000000; //SLOT1:WR REG MASTER VOLUME adr 0x02
+	for ( i = 3; i<13; i++ )
+	{
+		MCF_PSC2_PSCTB_AC97 = 0x0; //SLOT2-12:WR REG ALLES 0
+	}
+	MCF_PSC2_PSCTFCR |= MCF_PSC_PSCTFCR_WFR; //set EOF
+	MCF_PSC2_PSCTB_AC97 = 0x00000000; //last data
+
+ac97_end:
+	MCF_PSC0_PSCTB_8BIT = ' OK!';
+	MCF_PSC0_PSCTB_8BIT = 0x0a0d;
+
+}
+/********************************************************************/
+
+void __initialize_hardware(void)
+{
+_init_hardware:
+asm
+{
+	// instruction cache on
+	 	move.l		#0x000C8120,d0
+	 	move.l		d0,rt_cacr
+ 		movec		d0,cacr
+ 		nop
+}
+		init_gpio();
+   		init_seriel();
+		init_slt();
+		init_fbcs();
+		init_ddram();
+// Ports nicht initialisieren wenn DIP Switch 6 = on
+asm
+{
+		move.b	DIP_SWITCH,d0					// dip schalter adresse
+		btst.b	#6,d0
+		beq		not_init_ports
+}
+ 		init_PCI();		//pci braucht zeit
+ not_init_ports:
+		init_fpga();
+		init_video_ddr();
+ 		vdi_on();
+// Ports nicht initialisieren wenn DIP Switch 6 = on
+asm
+{
+		move.b	DIP_SWITCH,d0					// dip schalter adresse
+		btst.b	#6,d0
+		beq		not_init_ports2
+}
+//  		video_1280_1024();
+  		test_upd720101();
+not_init_ports2:
+  		init_ac97();
+
+asm
+{
+/*****************************************************/
+/* BaS kopieren 
+/*****************************************************/
+ 		lea		copy_start,a0
+ 		lea		BaS,a1
+ 		sub.l	a0,a1
+		move.l	#__Bas_base,a2
+ 		move.l	a2,a3
+ 		add.l	a1,a3
+		lea		copy_end,a4
+BaS_kopieren_loop:					// immer 16 bytes
+		move.l	(a0)+,(a2)+
+		move.l	(a0)+,(a2)+
+		move.l	(a0)+,(a2)+
+		move.l	(a0)+,(a2)+
+		cmp.l	a4,a0
+		blt		BaS_kopieren_loop
+/*****************************************************/
+		jmp		(a3)
+ copy_start:
+/********************************************************************/
+}
+}
+
diff --git a/firebeeV1/sources/sysinit.h b/firebeeV1/sources/sysinit.h
new file mode 100644
index 0000000..70bc6da
--- /dev/null
+++ b/firebeeV1/sources/sysinit.h
@@ -0,0 +1,87 @@
+/*
+ * File:		sysinit.h
+ * Purpose:		COLDARI Power-on Reset configuration
+ *
+ * Notes:
+ *
+ */
+
+#ifndef __SYSINIT_H__
+#define __SYSINIT_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+#if ENABLE_UART_SUPPORT==1 
+
+/*
+ * System Bus Clock Info
+ */
+// 5475EVB has 133Mhz system clock
+#define SYSTEM_CLOCK_KHZ    133000     /* system bus frequency in kHz */
+
+
+/*** 
+ * Serial Port Info
+ * The baud rate to be : 19200
+ * Data bits : 8
+ * Parity : None
+ * Stop Bits : 1
+ * Flow Control : None
+ */
+#define TERMINAL_PORT       (0)          /* PSC channel used as terminal */
+#define TERMINAL_BAUD       kBaud19200   /* 115200 */
+#undef  HARDWARE_FLOW_CONTROL       /* Flow control ON or OFF */
+#endif
+
+/*** 
+ * Board Memory map definitions from linker command files:
+ * __SDRAM,__SDRAM_SIZE, __FLASH, __FLASH_SIZE linker 
+ * symbols must be defined in the linker command file.
+ */
+extern __declspec(system) uint8 __BOOT_FLASH[];
+extern __declspec(system) uint8 __BOOT_FLASH_SIZE[];
+
+extern __declspec(system) uint8 __SDRAM[];
+extern __declspec(system) uint8 __SDRAM_SIZE[];
+
+
+#define BOOT_FLASH_ADDRESS		(uint32)__BOOT_FLASH
+#define BOOT_FLASH_SIZE			(uint32)__BOOT_FLASH_SIZE
+
+#define SDRAM_ADDRESS		    (uint32)__SDRAM
+#define SDRAM_SIZE			   	(uint32)__SDRAM_SIZE
+
+
+
+
+/********************************************************************/
+/* __initialize_hardware Startup code routine
+ * 
+ * __initialize_hardware is called by the startup code right after reset, 
+ * with interrupt disabled and SP pre-set to a valid memory area.
+ * Here you should initialize memory and some peripherics;
+ * at this point global variables are not initialized yet.
+ * The startup code will initialize SP on return of this function.
+ */
+void __initialize_hardware(void);
+
+/********************************************************************/
+/* __initialize_system Startup code routine
+ * 
+ * __initialize_system is called by the startup code when all languages 
+ * specific initialization are done to allow additional hardware setup.
+ */ 
+void __initialize_system(void);
+
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __SYSINIT_H__ */
+
+
diff --git a/workspace.cww b/workspace.cww
new file mode 100644
index 0000000..2d84375
--- /dev/null
+++ b/workspace.cww
@@ -0,0 +1,413 @@
+<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
+<?codewarrior exportversion="1.0" ideversion="5.9.0" success="y" ?>
+
+<!DOCTYPE MWIDEWORKSPACE [
+<!ELEMENT MWIDEWORKSPACE (WINDOW*, COMWINDOW*)>
+<!ELEMENT WINDOW (SESSION, EDOCTYPE, PATH, FRAMELOC, FRAMESIZE, DOCKINFO)>
+<!ELEMENT COMWINDOW (SESSION, CLSID, OWNERPROJECT, DATA, FRAMELOC, FRAMESIZE, DOCKINFO)>
+<!ELEMENT SESSION (#PCDATA)>
+<!ELEMENT EDOCTYPE (#PCDATA)>
+<!ELEMENT DEFAULT (#PCDATA)>
+<!ELEMENT MAXIMIZED (#PCDATA)>
+<!ELEMENT PATH (#PCDATA)>
+<!ATTLIST PATH USERELATIVEPATHS (true | false) "true">
+<!ELEMENT FRAMELOC (X, Y)>
+<!ELEMENT X (#PCDATA)>
+<!ELEMENT Y (#PCDATA)>
+<!ELEMENT FRAMESIZE (W, H)>
+<!ELEMENT W (#PCDATA)>
+<!ELEMENT H (#PCDATA)>
+<!ELEMENT DOCKINFO (STATUS, ROW, COLUMN, DOCKBARID, PCTWIDTH, HGT, GROUPID)>
+<!ELEMENT STATUS (#PCDATA)>
+<!ELEMENT ROW (#PCDATA)>
+<!ELEMENT COLUMN (#PCDATA)>
+<!ELEMENT DOCKBARID (#PCDATA)>
+<!ELEMENT PCTWIDTH (#PCDATA)>
+<!ELEMENT HGT (#PCDATA)>
+<!ELEMENT GROUPID (GIDHIGHPART, GIDLOWPART)>
+<!ELEMENT GIDHIGHPART (#PCDATA)>
+<!ELEMENT GIDLOWPART (#PCDATA)>
+<!ELEMENT CLSID (#PCDATA)>
+<!ELEMENT OWNERPROJECT (#PCDATA)>
+<!ATTLIST OWNERPROJECT USERELATIVEPATHS (true | false) "true">
+<!ELEMENT DATA (#PCDATA)>
+<!ATTLIST DATA BINARYFORMAT (true | false) "true">
+]>
+
+<MWIDEWORKSPACE>
+    <WINDOW>
+        <SESSION>-1</SESSION>
+        <EDOCTYPE>0</EDOCTYPE>
+        <DEFAULT>true</DEFAULT>
+        <PATH USERELATIVEPATHS = "true">firebeeV1\firebeeV1.mcp</PATH>
+        <FRAMELOC>
+            <X>938</X>
+            <Y>306</Y>
+        </FRAMELOC>
+        <FRAMESIZE>
+            <W>392</W>
+            <H>338</H>
+        </FRAMESIZE>
+        <DOCKINFO>
+            <STATUS>1</STATUS>
+            <ROW>0</ROW>
+            <COLUMN>0</COLUMN>
+            <DOCKBARID>59420</DOCKBARID>
+            <PCTWIDTH>1.000000</PCTWIDTH>
+            <HGT>378</HGT>
+            <GROUPID>
+                <GIDHIGHPART>0</GIDHIGHPART>
+                <GIDLOWPART>0</GIDLOWPART>
+            </GROUPID>
+        </DOCKINFO>
+    </WINDOW>
+    <WINDOW>
+        <SESSION>-1</SESSION>
+        <EDOCTYPE>1</EDOCTYPE>
+        <PATH USERELATIVEPATHS = "true">firebeeV1\sources\exceptions.s</PATH>
+        <FRAMELOC>
+            <X>8</X>
+            <Y>34</Y>
+        </FRAMELOC>
+        <FRAMESIZE>
+            <W>549</W>
+            <H>895</H>
+        </FRAMESIZE>
+        <DOCKINFO>
+            <STATUS>0</STATUS>
+            <ROW></ROW>
+            <COLUMN></COLUMN>
+            <DOCKBARID></DOCKBARID>
+            <PCTWIDTH></PCTWIDTH>
+            <HGT></HGT>
+            <GROUPID>
+                <GIDHIGHPART></GIDHIGHPART>
+                <GIDLOWPART></GIDLOWPART>
+            </GROUPID>
+        </DOCKINFO>
+    </WINDOW>
+    <WINDOW>
+        <SESSION>1073741824</SESSION>
+        <EDOCTYPE>35</EDOCTYPE>
+        <FRAMELOC>
+            <X>60</X>
+            <Y>205</Y>
+        </FRAMELOC>
+        <FRAMESIZE>
+            <W>582</W>
+            <H>392</H>
+        </FRAMESIZE>
+        <DOCKINFO>
+            <STATUS>0</STATUS>
+            <ROW></ROW>
+            <COLUMN></COLUMN>
+            <DOCKBARID></DOCKBARID>
+            <PCTWIDTH></PCTWIDTH>
+            <HGT></HGT>
+            <GROUPID>
+                <GIDHIGHPART></GIDHIGHPART>
+                <GIDLOWPART></GIDLOWPART>
+            </GROUPID>
+        </DOCKINFO>
+        <DEBUGCONTEXT>GlobalSession, cpu68K, osCWDS</DEBUGCONTEXT>
+        <DEBUGTARGETNAME>C:\FireBee\codewarrior\firebeeV1\bin\DDRAM.elf</DEBUGTARGETNAME>
+            <MEMORYWININDEX>2</MEMORYWININDEX>
+            <MEMORYWINSETTINGS EXPRSTRING = "0xf0000600" SPACEINDEX = "1" VIEWINDEX = "1" WORDSIZE = "1" SNAP16 = "0" SWAPENDIAN = "0" ASCIISHOWN = "1"/>
+    </WINDOW>
+    <WINDOW>
+        <SESSION>1073741824</SESSION>
+        <EDOCTYPE>35</EDOCTYPE>
+        <FRAMELOC>
+            <X>1586</X>
+            <Y>31</Y>
+        </FRAMELOC>
+        <FRAMESIZE>
+            <W>484</W>
+            <H>907</H>
+        </FRAMESIZE>
+        <DOCKINFO>
+            <STATUS>0</STATUS>
+            <ROW></ROW>
+            <COLUMN></COLUMN>
+            <DOCKBARID></DOCKBARID>
+            <PCTWIDTH></PCTWIDTH>
+            <HGT></HGT>
+            <GROUPID>
+                <GIDHIGHPART></GIDHIGHPART>
+                <GIDLOWPART></GIDLOWPART>
+            </GROUPID>
+        </DOCKINFO>
+        <DEBUGCONTEXT>GlobalSession, cpu68K, osCWDS</DEBUGCONTEXT>
+        <DEBUGTARGETNAME>C:\firebee\codewarrior\firebeeV1\bin\DDRAM.elf</DEBUGTARGETNAME>
+            <MEMORYWININDEX>4</MEMORYWININDEX>
+            <MEMORYWINSETTINGS EXPRSTRING = "0x1009626" SPACEINDEX = "1" VIEWINDEX = "4" WORDSIZE = "2" SNAP16 = "0" SWAPENDIAN = "0" ASCIISHOWN = "1"/>
+    </WINDOW>
+    <WINDOW>
+        <SESSION>1073741824</SESSION>
+        <EDOCTYPE>35</EDOCTYPE>
+        <FRAMELOC>
+            <X>1185</X>
+            <Y>39</Y>
+        </FRAMELOC>
+        <FRAMESIZE>
+            <W>481</W>
+            <H>225</H>
+        </FRAMESIZE>
+        <DOCKINFO>
+            <STATUS>0</STATUS>
+            <ROW></ROW>
+            <COLUMN></COLUMN>
+            <DOCKBARID></DOCKBARID>
+            <PCTWIDTH></PCTWIDTH>
+            <HGT></HGT>
+            <GROUPID>
+                <GIDHIGHPART></GIDHIGHPART>
+                <GIDLOWPART></GIDLOWPART>
+            </GROUPID>
+        </DOCKINFO>
+        <DEBUGCONTEXT>GlobalSession, cpu68K, osCWDS</DEBUGCONTEXT>
+        <DEBUGTARGETNAME>C:\firebee\codewarrior\firebeeV1\bin\DDRAM.elf</DEBUGTARGETNAME>
+            <MEMORYWININDEX>5</MEMORYWININDEX>
+            <MEMORYWINSETTINGS EXPRSTRING = "0xF" SPACEINDEX = "1" VIEWINDEX = "1" WORDSIZE = "3" SNAP16 = "0" SWAPENDIAN = "0" ASCIISHOWN = "1"/>
+    </WINDOW>
+    <WINDOW>
+        <SESSION>1073741824</SESSION>
+        <EDOCTYPE>35</EDOCTYPE>
+        <FRAMELOC>
+            <X>1100</X>
+            <Y>691</Y>
+        </FRAMELOC>
+        <FRAMESIZE>
+            <W>481</W>
+            <H>225</H>
+        </FRAMESIZE>
+        <DOCKINFO>
+            <STATUS>0</STATUS>
+            <ROW></ROW>
+            <COLUMN></COLUMN>
+            <DOCKBARID></DOCKBARID>
+            <PCTWIDTH></PCTWIDTH>
+            <HGT></HGT>
+            <GROUPID>
+                <GIDHIGHPART></GIDHIGHPART>
+                <GIDLOWPART></GIDLOWPART>
+            </GROUPID>
+        </DOCKINFO>
+        <DEBUGCONTEXT>GlobalSession, cpu68K, osCWDS</DEBUGCONTEXT>
+        <DEBUGTARGETNAME>C:\firebee\codewarrior\firebeeV1\bin\DDRAM.elf</DEBUGTARGETNAME>
+            <MEMORYWININDEX>3</MEMORYWININDEX>
+            <MEMORYWINSETTINGS EXPRSTRING = "0x010077e2" SPACEINDEX = "1" VIEWINDEX = "1" WORDSIZE = "3" SNAP16 = "0" SWAPENDIAN = "0" ASCIISHOWN = "1"/>
+    </WINDOW>
+    <WINDOW>
+        <SESSION>1073741824</SESSION>
+        <EDOCTYPE>35</EDOCTYPE>
+        <FRAMELOC>
+            <X>645</X>
+            <Y>600</Y>
+        </FRAMELOC>
+        <FRAMESIZE>
+            <W>481</W>
+            <H>225</H>
+        </FRAMESIZE>
+        <DOCKINFO>
+            <STATUS>0</STATUS>
+            <ROW></ROW>
+            <COLUMN></COLUMN>
+            <DOCKBARID></DOCKBARID>
+            <PCTWIDTH></PCTWIDTH>
+            <HGT></HGT>
+            <GROUPID>
+                <GIDHIGHPART></GIDHIGHPART>
+                <GIDLOWPART></GIDLOWPART>
+            </GROUPID>
+        </DOCKINFO>
+        <DEBUGCONTEXT>GlobalSession, cpu68K, osCWDS</DEBUGCONTEXT>
+        <DEBUGTARGETNAME>C:\FireBee\codewarrior\firebeeV1\bin\DDRAM.elf</DEBUGTARGETNAME>
+            <MEMORYWININDEX>1</MEMORYWININDEX>
+            <MEMORYWINSETTINGS EXPRSTRING = "0xfffffa" SPACEINDEX = "1" VIEWINDEX = "1" WORDSIZE = "1" SNAP16 = "0" SWAPENDIAN = "0" ASCIISHOWN = "1"/>
+    </WINDOW>
+    <WINDOW>
+        <SESSION>-2147483648</SESSION>
+        <EDOCTYPE>24</EDOCTYPE>
+        <FRAMELOC>
+            <X>13</X>
+            <Y>33</Y>
+        </FRAMELOC>
+        <FRAMESIZE>
+            <W>591</W>
+            <H>742</H>
+        </FRAMESIZE>
+        <DOCKINFO>
+            <STATUS>0</STATUS>
+            <ROW></ROW>
+            <COLUMN></COLUMN>
+            <DOCKBARID></DOCKBARID>
+            <PCTWIDTH></PCTWIDTH>
+            <HGT></HGT>
+            <GROUPID>
+                <GIDHIGHPART></GIDHIGHPART>
+                <GIDLOWPART></GIDLOWPART>
+            </GROUPID>
+        </DOCKINFO>
+    </WINDOW>
+    <WINDOW>
+        <SESSION>-2147483648</SESSION>
+        <EDOCTYPE>28</EDOCTYPE>
+        <FRAMELOC>
+            <X>652</X>
+            <Y>33</Y>
+        </FRAMELOC>
+        <FRAMESIZE>
+            <W>518</W>
+            <H>519</H>
+        </FRAMESIZE>
+        <DOCKINFO>
+            <STATUS>0</STATUS>
+            <ROW></ROW>
+            <COLUMN></COLUMN>
+            <DOCKBARID></DOCKBARID>
+            <PCTWIDTH></PCTWIDTH>
+            <HGT></HGT>
+            <GROUPID>
+                <GIDHIGHPART></GIDHIGHPART>
+                <GIDLOWPART></GIDLOWPART>
+            </GROUPID>
+        </DOCKINFO>
+        <DEBUGCONTEXT>GlobalSession, cpu68K, osCWDS</DEBUGCONTEXT>
+        <DEBUGTARGETNAME>C:\FireBee\codewarrior\firebeeV1\bin\DDRAM.elf</DEBUGTARGETNAME>
+            <REGISTERWINDOW><WINDOWINDEX>0</WINDOWINDEX>
+            <DIVIDERPOS>373</DIVIDERPOS>
+            <REGDISCLOSE NAME = "" TYPE = "334368068" DISCLOSED = "0">
+                <REGDISCLOSE NAME = "PEMICRO_USB" TYPE = "3" DISCLOSED = "1">
+                    <REGDISCLOSE NAME = "DDRAM.elf" TYPE = "4" DISCLOSED = "1">
+                        <REGDISCLOSE NAME = "Thread 0x0" TYPE = "5" DISCLOSED = "1">
+                            <REGDISCLOSE NAME = "General Purpose Registers" TYPE = "1" DISCLOSED = "1">
+                            </REGDISCLOSE>
+                            <REGDISCLOSE NAME = "FPU Registers" TYPE = "1" DISCLOSED = "0">
+                            </REGDISCLOSE>
+                            <REGDISCLOSE NAME = "EMAC Registers" TYPE = "1" DISCLOSED = "0">
+                            </REGDISCLOSE>
+                        </REGDISCLOSE>
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "Supervisor Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "Memory Management Unit Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "System Integration Unit Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "SDRAM Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "XL Bus Arbiter Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "Clock Module Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "Chip Select Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "Interrupt Controller Module Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "GPT Module Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "GPT Module Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "GPT Module Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "GPT Module Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "SLT0 Module Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "SLT1 Module Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "General Purpose I/O Port FBCTL Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "General Purpose I/O Port FBCS Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "General Purpose I/O Port DMA Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "General Purpose I/O Port FEC0H Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "General Purpose I/O Port FEC0L Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "General Purpose I/O Port FEC1H Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "General Purpose I/O Port FEC1L Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "General Purpose I/O Port FECI2C Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "General Purpose I/O Port PCIBG Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "General Purpose I/O Port PCIBR Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "General Purpose I/O Port PSC3PSC2 Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "General Purpose I/O Port PSC1PSC0 Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "General Purpose I/O Port DSPI Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "Common GPIO Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "PCI Bus Controller Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "PCI Bus Arbiter Module Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "Edge Port Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "Comm Timer Module Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "Multichannel DMA Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "Programmable Serial Controller 0 Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "Programmable Serial Controller 1 Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "Programmable Serial Controller 2 Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "Programmable Serial Controller 3 Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "DMA Serial Peripheral Interface Registers" TYPE = "1" DISCLOSED = "1">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "I2C Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "FEC0 Module Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "FEC1 Module Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "USB Interface Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                    <REGDISCLOSE NAME = "SRAM Module Registers" TYPE = "1" DISCLOSED = "0">
+                    </REGDISCLOSE>
+                </REGDISCLOSE>
+            </REGDISCLOSE>
+            </REGISTERWINDOW>
+    </WINDOW>
+    <WINDOW>
+        <SESSION>1073741824</SESSION>
+        <EDOCTYPE>28</EDOCTYPE>
+        <FRAMELOC>
+            <X>652</X>
+            <Y>33</Y>
+        </FRAMELOC>
+        <FRAMESIZE>
+            <W>518</W>
+            <H>519</H>
+        </FRAMESIZE>
+        <DOCKINFO>
+            <STATUS>0</STATUS>
+            <ROW></ROW>
+            <COLUMN></COLUMN>
+            <DOCKBARID></DOCKBARID>
+            <PCTWIDTH></PCTWIDTH>
+            <HGT></HGT>
+            <GROUPID>
+                <GIDHIGHPART></GIDHIGHPART>
+                <GIDLOWPART></GIDLOWPART>
+            </GROUPID>
+        </DOCKINFO>
+        <DEBUGCONTEXT>GlobalSession, cpu68K, osCWDS</DEBUGCONTEXT>
+        <DEBUGTARGETNAME>C:\FireBee\codewarrior\firebeeV1\bin\DDRAM.elf</DEBUGTARGETNAME>
+            <REGISTERWINDOW><WINDOWINDEX>0</WINDOWINDEX>
+            <DIVIDERPOS>373</DIVIDERPOS>
+            <REGDISCLOSE NAME = "" TYPE = "334367732" DISCLOSED = "0">
+            </REGDISCLOSE>
+            </REGISTERWINDOW>
+    </WINDOW>
+</MWIDEWORKSPACE>