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Sync from Fredi's source tree 13/05/2017

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This commit is contained in:
David Gálvez
2018-04-09 16:26:54 +02:00
parent c1e31dcdf0
commit 030afcd535
59 changed files with 13625 additions and 1139 deletions
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184
sources/BaS.c
View File

@@ -7,8 +7,12 @@
#include "MCF5475.h"
#include "startcf.h"
extern unsigned long far __SP_AFTER_RESET[];
extern unsigned long far __Bas_base[];
#include "MCD_dma.h"
#define MBAR_BASE_ADRS 0xff000000
#define MMAP_DMA 0x00008000
#define MMAP_SRAM 0x00010000
extern unsigned long far __SDRAM_SIZE;
/* imported routines */
extern int mmu_init();
@@ -27,11 +31,12 @@ void warte_10ms(void)
{
warte_10ms:
move.l d0,-(sp)
move.l MCF_SLT0_SCNT,d0
sub.l #1320000,d0
move.l #1330000,d0
move.l d0,MCF_SLT0_STCNT
warte_d6:
cmp.l MCF_SLT0_SCNT,d0
bcs warte_d6
move.b MCF_SLT0_SSR,d0
btst.b #0,d0
beq warte_d6
move.l (sp)+,d0
}
}
@@ -42,11 +47,12 @@ void warte_1ms(void)
{
warte_1ms:
move.l d0,-(sp)
move.l MCF_SLT0_SCNT,d0
sub.l #132000,d0
move.l #133000,d0
move.l d0,MCF_SLT0_STCNT
warte_d6:
cmp.l MCF_SLT0_SCNT,d0
bcs warte_d6
move.b MCF_SLT0_SSR,d0
btst.b #0,d0
beq warte_d6
move.l (sp)+,d0
}
}
@@ -57,11 +63,12 @@ void warte_100us(void)
{
warte_100us:
move.l d0,-(sp)
move.l MCF_SLT0_SCNT,d0
sub.l #13200,d0
move.l #13300,d0
move.l d0,MCF_SLT0_STCNT
warte_d6:
cmp.l MCF_SLT0_SCNT,d0
bcs warte_d6
move.b MCF_SLT0_SSR,d0
btst.b #0,d0
beq warte_d6
move.l (sp)+,d0
}
}
@@ -72,11 +79,12 @@ void warte_50us(void)
{
warte_50us:
move.l d0,-(sp)
move.l MCF_SLT0_SCNT,d0
sub.l #6600,d0
move.l #6650,d0
move.l d0,MCF_SLT0_STCNT
warte_d6:
cmp.l MCF_SLT0_SCNT,d0
bcs warte_d6
move.b MCF_SLT0_SSR,d0
btst.b #0,d0
beq warte_d6
move.l (sp)+,d0
}
}
@@ -86,11 +94,12 @@ void warte_10us(void)
{
warte_10us:
move.l d0,-(sp)
move.l MCF_SLT0_SCNT,d0
sub.l #1320,d0
move.l #1330,d0
move.l d0,MCF_SLT0_STCNT
warte_d6:
cmp.l MCF_SLT0_SCNT,d0
bcs warte_d6
move.b MCF_SLT0_SSR,d0
btst.b #0,d0
beq warte_d6
move.l (sp)+,d0
}
}
@@ -101,20 +110,27 @@ void warte_1us(void)
{
warte_1us:
move.l d0,-(sp)
move.l MCF_SLT0_SCNT,d0
sub.l #132,d0
move.l #133,d0
move.l d0,MCF_SLT0_STCNT
warte_d6:
cmp.l MCF_SLT0_SCNT,d0
bcs warte_d6
move.b MCF_SLT0_SSR,d0
btst.b #0,d0
beq warte_d6
move.l (sp)+,d0
}
}
/********************************************************************/
#define ide_dma_tnr 7
void BaS(void)
{
/*********************************************/
// SD-Card abfragen
int az_sectors;
int sd_status,i;
int dma_init_status,dma_run_status,dma_status;
az_sectors = sd_card_init();
@@ -122,12 +138,15 @@ void BaS(void)
{
sd_card_idle();
}
/*********************************************/
// FireTOS laden?
asm
{
move.b DIP_SWITCH,d0 // dip schalter adresse
{
move.b DIP_SWITCH,d0
btst.b #6,d0
beq firetos_kopieren
/**************************************/
// PIC initieren und daten anfordern
lea MCF_PSC0_PSCTB_8BIT,a6
lea MCF_PSC3_PSCTB_8BIT,a3
lea MCF_PSC3_PSCRB_8BIT,a4
@@ -141,8 +160,10 @@ void BaS(void)
move.b d1,(a6)
move.b (a4),d2
move.b d2,(a6)
move.l #0x0a0d,(a6)
move.b #0x01,(a3) // RTC DATEN ANFORDERN
move.l #'OK!',(a6)
move.l #0x0a0d,(a6)
/**************************************/
// TOS kopieren
lea 0x00e00000,a0
lea 0xe0600000,a1 // default tos
@@ -155,6 +176,13 @@ firetos_kopieren:
lea 0xe0400000,a1
lea 0xe0500000,a2 // 1MB
cptos_loop:
move.l (a1)+,(a0)+
move.l (a1)+,(a0)+
move.l (a1)+,(a0)+
move.l (a1)+,(a0)+
move.l (a1)+,(a0)+
move.l (a1)+,(a0)+
move.l (a1)+,(a0)+
move.l (a1)+,(a0)+
cmp.l a2,a1
blt cptos_loop
@@ -165,7 +193,7 @@ div_inits:
move.b DIP_SWITCH,d0 // dip schalter adresse
btst.b #6,d0
beq video_setup
// rtc daten, mmu set, etc nur wenn switch 6 = off
// rtc daten laden, mmu set, etc nur wenn switch 6 = off -> kein init wenn FireTOS
lea 0xffff8961,a0
clr.l d1
moveq #64,d2
@@ -179,13 +207,11 @@ loop_sr:
addq.l #1,d1
cmp.b d1,d2
bne loop_sr
/*
// Set the NVRAM checksum as invalid
move.b #63,(a0)
move.b 2(a0),d0
add #1,d0
move.b d0,2(a0)
*/
not_rtc:
bsr mmu_init
bsr vec_init
@@ -221,33 +247,9 @@ not_rtc:
nop
nop
/********************************************************************/
/* IDE reset
/********************************************************************/
lea 0xffff8802,a0
move.b #14,-2(a0)
move.b #0x80,(a0)
bsr warte_1ms
clr.b (a0)
/********************************************************************/
/* video setup
/********************************************************************/
video_setup:
lea 0xf0000410,a0
// 25MHz
move.l #0x032002ba,(a0)+ // horizontal 640x480
move.l #0x020c020a,(a0)+ // vertikal 640x480
move.l #0x0190015d,(a0)+ // horizontal 320x240
move.l #0x020C020A,(a0)+ // vertikal 320x240 */
/*
// 32MHz
move.l #0x037002ba,(a0)+ // horizontal 640x480
move.l #0x020d020a,(a0)+ // vertikal 640x480
move.l #0x02A001e0,(a0)+ // horizontal 320x240
move.l #0x05a00160,(a0)+ // vertikal 320x240
*/
lea -0x20(a0),a0
move.l #0x01070002,(a0) // fifo on, refresh on, ddrcs und cke on, video dac on,
/********************************************************************/
// nichts
/*******************************************************************/
/* memory setup
/********************************************************************/
lea 0x400,a0
@@ -272,7 +274,7 @@ mem_clr_loop:
move.l #0x5555aaaa,d0 // memval3
move.l d0,0x51a
// ttram
move.l #__Bas_base,d0 // ende ttram
move.l #__SDRAM_SIZE,d0 // ende ttram
move.l d0,0x5a4
move.l #0x1357bd13,d0 // ramvalid
move.l d0,0x5a8
@@ -292,13 +294,69 @@ mem_clr_loop:
move.b d0,0xfffffa11
nop
}
/*
// init_dma:
dma_init_status =
MCD_initDma(
(dmaRegs*) (MBAR_BASE_ADRS + MMAP_DMA),
(void*) (MBAR_BASE_ADRS + MMAP_SRAM),
(MCD_RELOC_TASKS)
);
for (i=0; i<64; i++)
{
dma_run_status =
MCD_startDma(ide_dma_tnr, //int channel, the channel on which to run the DMA
(char*) (0x60004000), //s8 *srcAddr, the address to move data from, or physical buffer-descriptor address
4, //s16 srcIncr, the amount to increment the source address per transfer
(char*) (0x60000000), //s8 *destAddr, the address to move data to
4, //s16 destIncr, the amount to increment the destination address per transfer
4*389120, //u32 dmaSize, the number of bytes to transfer independent of the transfer size
4, //u32 xferSize, the number bytes in of each data movement (1, 2, or 4)
0, //u32 initiator, what device initiates the DMA
5, //int priority, priority of the DMA
MCD_SINGLE_DMA+
MCD_TT_FLAGS_CW+ //u32 flags, flags describing the DMA
MCD_TT_FLAGS_RL+
MCD_TT_FLAGS_SP,
MCD_NO_BYTE_SWAP+
MCD_NO_BIT_REV //u32 funcDesc a description of byte swapping, bit swapping, and CRC actions
);
while (MCD_dmaStatus(ide_dma_tnr)!=6);
}
dma_status =
MCD_dmaStatus(ide_dma_tnr);
MCD_killDma(ide_dma_tnr);
*/
asm
{
// test auf protect mode ---------------------
move.b DIP_SWITCH,d0
btst #7,d0
beq no_protect // nein->
move.w #0x0700,sr
no_protect:
}
MCF_PSC0_PSCTB_8BIT = 0x0a0d;
MCF_PSC0_PSCTB_8BIT = 'BaS ';
MCF_PSC0_PSCTB_8BIT = 'comp';
MCF_PSC0_PSCTB_8BIT = 'lete';
MCF_PSC0_PSCTB_8BIT = 'd';
MCF_PSC0_PSCTB_8BIT = 0x0a0d;
MCF_PSC0_PSCTB_8BIT = '----';
MCF_PSC0_PSCTB_8BIT = '----';
MCF_PSC0_PSCTB_8BIT = '----';
MCF_PSC0_PSCTB_8BIT = '-';
MCF_PSC0_PSCTB_8BIT = 0x0a0d;
MCF_PSC0_PSCTB_8BIT = 0x0a0d;
asm
{
nop
bsr warte_10ms
jmp 0xe00030
}
}
}

933
sources/MCD_dmaApi.c Normal file
View File

@@ -0,0 +1,933 @@
/*
* File: MCD_dmaApi.c
* Purpose: Main C file for multi-channel DMA API.
*
* Notes:
*/
#include "MCD_dma.h"
#include "MCD_tasksInit.h"
#include "MCD_progCheck.h"
/********************************************************************/
/*
* This is an API-internal pointer to the DMA's registers
*/
dmaRegs *MCD_dmaBar;
/*
* These are the real and model task tables as generated by the
* build process
*/
extern TaskTableEntry MCD_realTaskTableSrc[NCHANNELS];
extern TaskTableEntry MCD_modelTaskTableSrc[NUMOFVARIANTS];
/*
* However, this (usually) gets relocated to on-chip SRAM, at which
* point we access them as these tables
*/
volatile TaskTableEntry *MCD_taskTable;
TaskTableEntry *MCD_modelTaskTable;
/*
* MCD_chStatus[] is an array of status indicators for remembering
* whether a DMA has ever been attempted on each channel, pausing
* status, etc.
*/
static int MCD_chStatus[NCHANNELS] =
{
MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA,
MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA,
MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA,
MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA, MCD_NO_DMA
};
/*
* Prototypes for local functions
*/
static void MCD_memcpy (int *dest, int *src, u32 size);
static void MCD_resmActions (int channel);
/*
* Buffer descriptors used for storage of progress info for single Dmas
* Also used as storage for the DMA for CRCs for single DMAs
* Otherwise, the DMA does not parse these buffer descriptors
*/
#ifdef MCD_INCLUDE_EU
extern MCD_bufDesc MCD_singleBufDescs[NCHANNELS];
#else
MCD_bufDesc MCD_singleBufDescs[NCHANNELS];
#endif
MCD_bufDesc *MCD_relocBuffDesc;
/*
* Defines for the debug control register's functions
*/
#define DBG_CTL_COMP1_TASK (0x00002000) /* have comparator 1 look for a task # */
#define DBG_CTL_ENABLE (DBG_CTL_AUTO_ARM | \
DBG_CTL_BREAK | \
DBG_CTL_INT_BREAK | \
DBG_CTL_COMP1_TASK)
#define DBG_CTL_DISABLE (DBG_CTL_AUTO_ARM | \
DBG_CTL_INT_BREAK | \
DBG_CTL_COMP1_TASK)
#define DBG_KILL_ALL_STAT (0xFFFFFFFF)
/*
* Offset to context save area where progress info is stored
*/
#define CSAVE_OFFSET 10
/*
* Defines for Byte Swapping
*/
#define MCD_BYTE_SWAP_KILLER 0xFFF8888F
#define MCD_NO_BYTE_SWAP_ATALL 0x00040000
/*
* Execution Unit Identifiers
*/
#define MAC 0 /* legacy - not used */
#define LUAC 1 /* legacy - not used */
#define CRC 2 /* legacy - not used */
#define LURC 3 /* Logic Unit with CRC */
/*
* Task Identifiers
*/
#define TASK_CHAINNOEU 0
#define TASK_SINGLENOEU 1
#ifdef MCD_INCLUDE_EU
#define TASK_CHAINEU 2
#define TASK_SINGLEEU 3
#define TASK_FECRX 4
#define TASK_FECTX 5
#else
#define TASK_CHAINEU 0
#define TASK_SINGLEEU 1
#define TASK_FECRX 2
#define TASK_FECTX 3
#endif
/*
* Structure to remember which variant is on which channel
* TBD- need this?
*/
typedef struct MCD_remVariants_struct MCD_remVariant;
struct MCD_remVariants_struct
{
int remDestRsdIncr[NCHANNELS]; /* -1,0,1 */
int remSrcRsdIncr[NCHANNELS]; /* -1,0,1 */
s16 remDestIncr[NCHANNELS]; /* DestIncr */
s16 remSrcIncr[NCHANNELS]; /* srcIncr */
u32 remXferSize[NCHANNELS]; /* xferSize */
};
/*
* Structure to remember the startDma parameters for each channel
*/
MCD_remVariant MCD_remVariants;
/********************************************************************/
/*
* Function: MCD_initDma
* Purpose: Initializes the DMA API by setting up a pointer to the DMA
* registers, relocating and creating the appropriate task
* structures, and setting up some global settings
* Arguments:
* dmaBarAddr - pointer to the multichannel DMA registers
* taskTableDest - location to move DMA task code and structs to
* flags - operational parameters
* Return Value:
* MCD_TABLE_UNALIGNED if taskTableDest is not 512-byte aligned
* MCD_OK otherwise
*/
extern u32 MCD_funcDescTab0[];
int MCD_initDma (dmaRegs *dmaBarAddr, void *taskTableDest, u32 flags)
{
int i;
TaskTableEntry *entryPtr;
/* setup the local pointer to register set */
MCD_dmaBar = dmaBarAddr;
/* do we need to move/create a task table */
if ((flags & MCD_RELOC_TASKS) != 0)
{
int fixedSize;
u32 *fixedPtr;
/*int *tablePtr = taskTableDest;TBD*/
int varTabsOffset, funcDescTabsOffset, contextSavesOffset;
int taskDescTabsOffset;
int taskTableSize, varTabsSize, funcDescTabsSize, contextSavesSize;
int taskDescTabSize;
int i;
/* check if physical address is aligned on 512 byte boundary */
if (((u32)taskTableDest & 0x000001ff) != 0)
return(MCD_TABLE_UNALIGNED);
MCD_taskTable = taskTableDest; /* set up local pointer to task Table */
/*
* Create a task table:
* - compute aligned base offsets for variable tables and
* function descriptor tables, then
* - loop through the task table and setup the pointers
* - copy over model task table with the the actual task descriptor
* tables
*/
taskTableSize = NCHANNELS * sizeof(TaskTableEntry);
/* align variable tables to size */
varTabsOffset = taskTableSize + (u32)taskTableDest;
if ((varTabsOffset & (VAR_TAB_SIZE - 1)) != 0)
varTabsOffset = (varTabsOffset + VAR_TAB_SIZE) & (~VAR_TAB_SIZE);
/* align function descriptor tables */
varTabsSize = NCHANNELS * VAR_TAB_SIZE;
funcDescTabsOffset = varTabsOffset + varTabsSize;
if ((funcDescTabsOffset & (FUNCDESC_TAB_SIZE - 1)) != 0)
funcDescTabsOffset = (funcDescTabsOffset + FUNCDESC_TAB_SIZE) &
(~FUNCDESC_TAB_SIZE);
funcDescTabsSize = FUNCDESC_TAB_NUM * FUNCDESC_TAB_SIZE;
contextSavesOffset = funcDescTabsOffset + funcDescTabsSize;
contextSavesSize = (NCHANNELS * CONTEXT_SAVE_SIZE);
fixedSize = taskTableSize + varTabsSize + funcDescTabsSize +
contextSavesSize;
/* zero the thing out */
fixedPtr = (u32 *)taskTableDest;
for (i = 0;i<(fixedSize/4);i++)
fixedPtr[i] = 0;
entryPtr = (TaskTableEntry*)MCD_taskTable;
/* set up fixed pointers */
for (i = 0; i < NCHANNELS; i++)
{
entryPtr[i].varTab = (u32)varTabsOffset; /* update ptr to local value */
entryPtr[i].FDTandFlags = (u32)funcDescTabsOffset | MCD_TT_FLAGS_DEF;
entryPtr[i].contextSaveSpace = (u32)contextSavesOffset;
varTabsOffset += VAR_TAB_SIZE;
#ifdef MCD_INCLUDE_EU /* if not there is only one, just point to the same one */
funcDescTabsOffset += FUNCDESC_TAB_SIZE;
#endif
contextSavesOffset += CONTEXT_SAVE_SIZE;
}
/* copy over the function descriptor table */
for ( i = 0; i < FUNCDESC_TAB_NUM; i++)
{
MCD_memcpy((void*)(entryPtr[i].FDTandFlags & ~MCD_TT_FLAGS_MASK),
(void*)MCD_funcDescTab0, FUNCDESC_TAB_SIZE);
}
/* copy model task table to where the context saves stuff leaves off*/
MCD_modelTaskTable = (TaskTableEntry*)contextSavesOffset;
MCD_memcpy ((void*)MCD_modelTaskTable, (void*)MCD_modelTaskTableSrc,
NUMOFVARIANTS * sizeof(TaskTableEntry));
entryPtr = MCD_modelTaskTable; /* point to local version of
model task table */
taskDescTabsOffset = (u32)MCD_modelTaskTable +
(NUMOFVARIANTS * sizeof(TaskTableEntry));
/* copy actual task code and update TDT ptrs in local model task table */
for (i = 0; i < NUMOFVARIANTS; i++)
{
taskDescTabSize = entryPtr[i].TDTend - entryPtr[i].TDTstart + 4;
MCD_memcpy ((void*)taskDescTabsOffset, (void*)entryPtr[i].TDTstart, taskDescTabSize);
entryPtr[i].TDTstart = (u32)taskDescTabsOffset;
taskDescTabsOffset += taskDescTabSize;
entryPtr[i].TDTend = (u32)taskDescTabsOffset - 4;
}
#ifdef MCD_INCLUDE_EU /* Tack single DMA BDs onto end of code so API controls
where they are since DMA might write to them */
MCD_relocBuffDesc = (MCD_bufDesc*)(entryPtr[NUMOFVARIANTS - 1].TDTend + 4);
#else /* DMA does not touch them so they can be wherever and we don't need to
waste SRAM on them */
MCD_relocBuffDesc = MCD_singleBufDescs;
#endif
}
else
{
/* point the would-be relocated task tables and the
buffer descriptors to the ones the linker generated */
if (((u32)MCD_realTaskTableSrc & 0x000001ff) != 0)
return(MCD_TABLE_UNALIGNED);
/* need to add code to make sure that every thing else is aligned properly TBD*/
/* this is problematic if we init more than once or after running tasks,
need to add variable to see if we have aleady init'd */
entryPtr = MCD_realTaskTableSrc;
for (i = 0; i < NCHANNELS; i++)
{
if (((entryPtr[i].varTab & (VAR_TAB_SIZE - 1)) != 0) ||
((entryPtr[i].FDTandFlags & (FUNCDESC_TAB_SIZE - 1)) != 0))
return(MCD_TABLE_UNALIGNED);
}
MCD_taskTable = MCD_realTaskTableSrc;
MCD_modelTaskTable = MCD_modelTaskTableSrc;
MCD_relocBuffDesc = MCD_singleBufDescs;
}
/* Make all channels as totally inactive, and remember them as such: */
MCD_dmaBar->taskbar = (u32) MCD_taskTable;
for (i = 0; i < NCHANNELS; i++)
{
MCD_dmaBar->taskControl[i] = 0x0;
MCD_chStatus[i] = MCD_NO_DMA;
}
/* Set up pausing mechanism to inactive state: */
MCD_dmaBar->debugComp1 = 0; /* no particular values yet for either comparator registers */
MCD_dmaBar->debugComp2 = 0;
MCD_dmaBar->debugControl = DBG_CTL_DISABLE;
MCD_dmaBar->debugStatus = DBG_KILL_ALL_STAT;
/* enable or disable commbus prefetch, really need an ifdef or
something to keep from trying to set this in the 8220 */
if ((flags & MCD_COMM_PREFETCH_EN) != 0)
MCD_dmaBar->ptdControl &= ~PTD_CTL_COMM_PREFETCH;
else
MCD_dmaBar->ptdControl |= PTD_CTL_COMM_PREFETCH;
return(MCD_OK);
}
/*********************** End of MCD_initDma() ***********************/
/********************************************************************/
/* Function: MCD_dmaStatus
* Purpose: Returns the status of the DMA on the requested channel
* Arguments: channel - channel number
* Returns: Predefined status indicators
*/
int MCD_dmaStatus (int channel)
{
u16 tcrValue;
if((channel < 0) || (channel >= NCHANNELS))
return(MCD_CHANNEL_INVALID);
tcrValue = MCD_dmaBar->taskControl[channel];
if ((tcrValue & TASK_CTL_EN) == 0)
{ /* nothing running */
/* if last reported with task enabled */
if ( MCD_chStatus[channel] == MCD_RUNNING
|| MCD_chStatus[channel] == MCD_IDLE)
MCD_chStatus[channel] = MCD_DONE;
}
else /* something is running */
{
/* There are three possibilities: paused, running or idle. */
if ( MCD_chStatus[channel] == MCD_RUNNING
|| MCD_chStatus[channel] == MCD_IDLE)
{
MCD_dmaBar->ptdDebug = PTD_DBG_TSK_VLD_INIT;
/* This register is selected to know which initiator is
actually asserted. */
if ((MCD_dmaBar->ptdDebug >> channel ) & 0x1 )
MCD_chStatus[channel] = MCD_RUNNING;
else
MCD_chStatus[channel] = MCD_IDLE;
/* do not change the status if it is already paused. */
}
}
return MCD_chStatus[channel];
}
/******************** End of MCD_dmaStatus() ************************/
/********************************************************************/
/* Function: MCD_startDma
* Ppurpose: Starts a particular kind of DMA
* Arguments: see below
* Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
*/
int MCD_startDma (
int channel, /* the channel on which to run the DMA */
s8 *srcAddr, /* the address to move data from, or physical buffer-descriptor address */
s16 srcIncr, /* the amount to increment the source address per transfer */
s8 *destAddr, /* the address to move data to */
s16 destIncr, /* the amount to increment the destination address per transfer */
u32 dmaSize, /* the number of bytes to transfer independent of the transfer size */
u32 xferSize, /* the number bytes in of each data movement (1, 2, or 4) */
u32 initiator, /* what device initiates the DMA */
int priority, /* priority of the DMA */
u32 flags, /* flags describing the DMA */
u32 funcDesc /* a description of byte swapping, bit swapping, and CRC actions */
#ifdef MCD_NEED_ADDR_TRANS
s8 *srcAddrVirt /* virtual buffer descriptor address TBD*/
#endif
)
{
int srcRsdIncr, destRsdIncr;
int *cSave;
short xferSizeIncr;
int tcrCount = 0;
#ifdef MCD_INCLUDE_EU
u32 *realFuncArray;
#endif
if((channel < 0) || (channel >= NCHANNELS))
return(MCD_CHANNEL_INVALID);
/* tbd - need to determine the proper response to a bad funcDesc when not
including EU functions, for now, assign a benign funcDesc, but maybe
should return an error */
#ifndef MCD_INCLUDE_EU
funcDesc = MCD_FUNC_NOEU1;
#endif
#ifdef MCD_DEBUG
printf("startDma:Setting up params\n");
#endif
/* Set us up for task-wise priority. We don't technically need to do this on every start, but
since the register involved is in the same longword as other registers that users are in control
of, setting it more than once is probably preferable. That since the documentation doesn't seem
to be completely consistent about the nature of the PTD control register. */
MCD_dmaBar->ptdControl |= (u16) 0x8000;
#if 1 /* Not sure what we need to keep here rtm TBD */
/* Calculate additional parameters to the regular DMA calls. */
srcRsdIncr = srcIncr < 0 ? -1 : (srcIncr > 0 ? 1 : 0);
destRsdIncr = destIncr < 0 ? -1 : (destIncr > 0 ? 1 : 0);
xferSizeIncr = (xferSize & 0xffff) | 0x20000000;
/* Remember for each channel which variant is running. */
MCD_remVariants.remSrcRsdIncr[channel] = srcRsdIncr;
MCD_remVariants.remDestRsdIncr[channel] = destRsdIncr;
MCD_remVariants.remDestIncr[channel] = destIncr;
MCD_remVariants.remSrcIncr[channel] = srcIncr;
MCD_remVariants.remXferSize[channel] = xferSize;
#endif
cSave = (int*)(MCD_taskTable[channel].contextSaveSpace) + CSAVE_OFFSET + CURRBD;
#ifdef MCD_INCLUDE_EU /* may move this to EU specific calls */
realFuncArray = (u32 *) (MCD_taskTable[channel].FDTandFlags & 0xffffff00);
/* Modify the LURC's normal and byte-residue-loop functions according to parameter. */
realFuncArray[(LURC*16)] = xferSize == 4 ?
funcDesc : xferSize == 2 ?
funcDesc & 0xfffff00f : funcDesc & 0xffff000f;
realFuncArray[(LURC*16+1)] = (funcDesc & MCD_BYTE_SWAP_KILLER) | MCD_NO_BYTE_SWAP_ATALL;
#endif
/* Write the initiator field in the TCR, and also set the initiator-hold
bit. Note that,due to a hardware quirk, this could collide with an
MDE access to the initiator-register file, so we have to verify that the write
reads back correctly. */
MCD_dmaBar->taskControl[channel] =
(initiator << 8) | TASK_CTL_HIPRITSKEN | TASK_CTL_HLDINITNUM;
while(((MCD_dmaBar->taskControl[channel] & 0x1fff) !=
((initiator << 8) | TASK_CTL_HIPRITSKEN | TASK_CTL_HLDINITNUM)) &&
(tcrCount < 1000))
{
tcrCount++;
/*MCD_dmaBar->ptd_tcr[channel] = (initiator << 8) | 0x0020;*/
MCD_dmaBar->taskControl[channel] =
(initiator << 8) | TASK_CTL_HIPRITSKEN | TASK_CTL_HLDINITNUM;
}
MCD_dmaBar->priority[channel] = (u8)priority & PRIORITY_PRI_MASK;
/* should be albe to handle this stuff with only one write to ts reg - tbd */
if (channel < 8 && channel >= 0)
{
MCD_dmaBar->taskSize0 &= ~(0xf << (7-channel)*4);
MCD_dmaBar->taskSize0 |= (xferSize & 3) << (((7 - channel)*4) + 2);
MCD_dmaBar->taskSize0 |= (xferSize & 3) << ((7 - channel)*4);
}
else
{
MCD_dmaBar->taskSize1 &= ~(0xf << (15-channel)*4);
MCD_dmaBar->taskSize1 |= (xferSize & 3) << (((15 - channel)*4) + 2);
MCD_dmaBar->taskSize1 |= (xferSize & 3) << ((15 - channel)*4);
}
/* setup task table flags/options which mostly control the line buffers */
MCD_taskTable[channel].FDTandFlags &= ~MCD_TT_FLAGS_MASK;
MCD_taskTable[channel].FDTandFlags |= (MCD_TT_FLAGS_MASK & flags);
if (flags & MCD_FECTX_DMA)
{
/* TDTStart and TDTEnd */
MCD_taskTable[channel].TDTstart = MCD_modelTaskTable[TASK_FECTX].TDTstart;
MCD_taskTable[channel].TDTend = MCD_modelTaskTable[TASK_FECTX].TDTend;
MCD_startDmaENetXmit(srcAddr, srcAddr, destAddr, MCD_taskTable, channel);
}
else if (flags & MCD_FECRX_DMA)
{
/* TDTStart and TDTEnd */
MCD_taskTable[channel].TDTstart = MCD_modelTaskTable[TASK_FECRX].TDTstart;
MCD_taskTable[channel].TDTend = MCD_modelTaskTable[TASK_FECRX].TDTend;
MCD_startDmaENetRcv(srcAddr, srcAddr, destAddr, MCD_taskTable, channel);
}
else if(flags & MCD_SINGLE_DMA)
{
/* this buffer descriptor is used for storing off initial parameters for later
progress query calculation and for the DMA to write the resulting checksum
The DMA does not use this to determine how to operate, that info is passed
with the init routine*/
MCD_relocBuffDesc[channel].srcAddr = srcAddr;
MCD_relocBuffDesc[channel].destAddr = destAddr;
MCD_relocBuffDesc[channel].lastDestAddr = destAddr; /* definitely not its final value */
MCD_relocBuffDesc[channel].dmaSize = dmaSize;
MCD_relocBuffDesc[channel].flags = 0; /* not used */
MCD_relocBuffDesc[channel].csumResult = 0; /* not used */
MCD_relocBuffDesc[channel].next = 0; /* not used */
/* Initialize the progress-querying stuff to show no progress:*/
((volatile int *)MCD_taskTable[channel].contextSaveSpace)[SRCPTR + CSAVE_OFFSET] = (int)srcAddr;
((volatile int *)MCD_taskTable[channel].contextSaveSpace)[DESTPTR + CSAVE_OFFSET] = (int)destAddr;
((volatile int *)MCD_taskTable[channel].contextSaveSpace)[DCOUNT + CSAVE_OFFSET] = 0;
((volatile int *)MCD_taskTable[channel].contextSaveSpace)[CURRBD + CSAVE_OFFSET] =
(u32) &(MCD_relocBuffDesc[channel]);
/* tbd - need to keep the user from trying to call the EU routine
when MCD_INCLUDE_EU is not defined */
if( funcDesc == MCD_FUNC_NOEU1 || funcDesc == MCD_FUNC_NOEU2)
{
/* TDTStart and TDTEnd */
MCD_taskTable[channel].TDTstart = MCD_modelTaskTable[TASK_SINGLENOEU].TDTstart;
MCD_taskTable[channel].TDTend = MCD_modelTaskTable[TASK_SINGLENOEU].TDTend;
MCD_startDmaSingleNoEu(srcAddr, srcIncr, destAddr, destIncr, dmaSize,
xferSizeIncr, flags, (int *)&(MCD_relocBuffDesc[channel]), cSave,
MCD_taskTable, channel);
}
else
{
/* TDTStart and TDTEnd */
MCD_taskTable[channel].TDTstart = MCD_modelTaskTable[TASK_SINGLEEU].TDTstart;
MCD_taskTable[channel].TDTend = MCD_modelTaskTable[TASK_SINGLEEU].TDTend;
MCD_startDmaSingleEu(srcAddr, srcIncr, destAddr, destIncr, dmaSize,
xferSizeIncr, flags, (int *)&(MCD_relocBuffDesc[channel]), cSave,
MCD_taskTable, channel);
}
}
else
{ /* chained DMAS */
/* Initialize the progress-querying stuff to show no progress:*/
#if 1 /* (!defined(MCD_NEED_ADDR_TRANS)) */
((volatile int *)MCD_taskTable[channel].contextSaveSpace)[SRCPTR + CSAVE_OFFSET]
= (int)((MCD_bufDesc*) srcAddr)->srcAddr;
((volatile int *)MCD_taskTable[channel].contextSaveSpace)[DESTPTR + CSAVE_OFFSET]
= (int)((MCD_bufDesc*) srcAddr)->destAddr;
#else /* if using address translation, need the virtual addr of the first buffdesc */
((volatile int *)MCD_taskTable[channel].contextSaveSpace)[SRCPTR + CSAVE_OFFSET]
= (int)((MCD_bufDesc*) srcAddrVirt)->srcAddr;
((volatile int *)MCD_taskTable[channel].contextSaveSpace)[DESTPTR + CSAVE_OFFSET]
= (int)((MCD_bufDesc*) srcAddrVirt)->destAddr;
#endif
((volatile int *)MCD_taskTable[channel].contextSaveSpace)[DCOUNT + CSAVE_OFFSET] = 0;
((volatile int *)MCD_taskTable[channel].contextSaveSpace)[CURRBD + CSAVE_OFFSET] = (u32) srcAddr;
if( funcDesc == MCD_FUNC_NOEU1 || funcDesc == MCD_FUNC_NOEU2)
{
/*TDTStart and TDTEnd*/
MCD_taskTable[channel].TDTstart = MCD_modelTaskTable[TASK_CHAINNOEU].TDTstart;
MCD_taskTable[channel].TDTend = MCD_modelTaskTable[TASK_CHAINNOEU].TDTend;
MCD_startDmaChainNoEu((int *)srcAddr, srcIncr, destIncr, xferSize,
xferSizeIncr, cSave, MCD_taskTable, channel);
}
else
{
/*TDTStart and TDTEnd*/
MCD_taskTable[channel].TDTstart = MCD_modelTaskTable[TASK_CHAINEU].TDTstart;
MCD_taskTable[channel].TDTend = MCD_modelTaskTable[TASK_CHAINEU].TDTend;
MCD_startDmaChainEu((int *)srcAddr, srcIncr, destIncr, xferSize,
xferSizeIncr, cSave, MCD_taskTable, channel);
}
}
MCD_chStatus[channel] = MCD_IDLE;
return(MCD_OK);
}
/************************ End of MCD_startDma() *********************/
/********************************************************************/
/* Function: MCD_XferProgrQuery
* Purpose: Returns progress of DMA on requested channel
* Arguments: channel - channel to retrieve progress for
* progRep - pointer to user supplied MCD_XferProg struct
* Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
*
* Notes:
* MCD_XferProgrQuery() upon completing or after aborting a DMA, or
* while the DMA is in progress, this function returns the first
* DMA-destination address not (or not yet) used in the DMA. When
* encountering a non-ready buffer descriptor, the information for
* the last completed descriptor is returned.
*
* MCD_XferProgQuery() has to avoid the possibility of getting
* partially-updated information in the event that we should happen
* to query DMA progress just as the DMA is updating it. It does that
* by taking advantage of the fact context is not saved frequently for
* the most part. We therefore read it at least twice until we get the
* same information twice in a row.
*
* Because a small, but not insignificant, amount of time is required
* to write out the progress-query information, especially upon
* completion of the DMA, it would be wise to guarantee some time lag
* between successive readings of the progress-query information.
*/
/*
* How many iterations of the loop below to execute to stabilize values
*/
#define STABTIME 0
int MCD_XferProgrQuery (int channel, MCD_XferProg *progRep)
{
MCD_XferProg prevRep;
int again; /* true if we are to try again to get consistent results */
int i; /* used as a time-waste counter */
int destDiffBytes; /* Total number of bytes that we think actually got xfered. */
int numIterations; /* number of iterations */
int bytesNotXfered; /* bytes that did not get xfered. */
s8 *LWAlignedInitDestAddr, *LWAlignedCurrDestAddr;
int subModVal, addModVal; /* Mode values to added and subtracted from the
final destAddr */
if((channel < 0) || (channel >= NCHANNELS))
return(MCD_CHANNEL_INVALID);
/* Read a trial value for the progress-reporting values*/
prevRep.lastSrcAddr =
(s8 *) ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[SRCPTR + CSAVE_OFFSET];
prevRep.lastDestAddr =
(s8 *) ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[DESTPTR + CSAVE_OFFSET];
prevRep.dmaSize = ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[DCOUNT + CSAVE_OFFSET];
prevRep.currBufDesc =
(MCD_bufDesc*) ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[CURRBD + CSAVE_OFFSET];
/* Repeatedly reread those values until they match previous values: */
do {
/* Waste a little bit of time to ensure stability: */
for (i = 0; i < STABTIME; i++)
i += i >> 2; /* make sure this loop does something so that it doesn't get optimized out */
/* Check them again: */
progRep->lastSrcAddr =
(s8 *) ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[SRCPTR + CSAVE_OFFSET];
progRep->lastDestAddr =
(s8 *) ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[DESTPTR + CSAVE_OFFSET];
progRep->dmaSize = ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[DCOUNT + CSAVE_OFFSET];
progRep->currBufDesc =
(MCD_bufDesc*) ((volatile int*) MCD_taskTable[channel].contextSaveSpace)[CURRBD + CSAVE_OFFSET];
/* See if they match: */
if ( prevRep.lastSrcAddr != progRep->lastSrcAddr
|| prevRep.lastDestAddr != progRep->lastDestAddr
|| prevRep.dmaSize != progRep->dmaSize
|| prevRep.currBufDesc != progRep->currBufDesc)
{
/* If they don't match, remember previous values and try again:*/
prevRep.lastSrcAddr = progRep->lastSrcAddr;
prevRep.lastDestAddr = progRep->lastDestAddr;
prevRep.dmaSize = progRep->dmaSize;
prevRep.currBufDesc = progRep->currBufDesc;
again = MCD_TRUE;
}
else
again = MCD_FALSE;
} while (again == MCD_TRUE);
/* Update the dCount, srcAddr and destAddr */
/* To calculate dmaCount, we consider destination address. C
overs M1,P1,Z for destination */
switch(MCD_remVariants.remDestRsdIncr[channel]) {
case MINUS1:
subModVal = ((int)progRep->lastDestAddr) & ((MCD_remVariants.remXferSize[channel]) - 1);
addModVal = ((int)progRep->currBufDesc->destAddr) & ((MCD_remVariants.remXferSize[channel]) - 1);
LWAlignedInitDestAddr = (progRep->currBufDesc->destAddr) - addModVal;
LWAlignedCurrDestAddr = (progRep->lastDestAddr) - subModVal;
destDiffBytes = LWAlignedInitDestAddr - LWAlignedCurrDestAddr;
bytesNotXfered = (destDiffBytes/MCD_remVariants.remDestIncr[channel]) *
( MCD_remVariants.remDestIncr[channel]
+ MCD_remVariants.remXferSize[channel]);
progRep->dmaSize = destDiffBytes - bytesNotXfered + addModVal - subModVal;
break;
case ZERO:
progRep->lastDestAddr = progRep->currBufDesc->destAddr;
break;
case PLUS1:
/* This value has to be subtracted from the final calculated dCount. */
subModVal = ((int)progRep->currBufDesc->destAddr) & ((MCD_remVariants.remXferSize[channel]) - 1);
/* These bytes are already in lastDestAddr. */
addModVal = ((int)progRep->lastDestAddr) & ((MCD_remVariants.remXferSize[channel]) - 1);
LWAlignedInitDestAddr = (progRep->currBufDesc->destAddr) - subModVal;
LWAlignedCurrDestAddr = (progRep->lastDestAddr) - addModVal;
destDiffBytes = (progRep->lastDestAddr - LWAlignedInitDestAddr);
numIterations = ( LWAlignedCurrDestAddr - LWAlignedInitDestAddr)/MCD_remVariants.remDestIncr[channel];
bytesNotXfered = numIterations *
( MCD_remVariants.remDestIncr[channel]
- MCD_remVariants.remXferSize[channel]);
progRep->dmaSize = destDiffBytes - bytesNotXfered - subModVal;
break;
default:
break;
}
/* This covers M1,P1,Z for source */
switch(MCD_remVariants.remSrcRsdIncr[channel]) {
case MINUS1:
progRep->lastSrcAddr =
progRep->currBufDesc->srcAddr +
( MCD_remVariants.remSrcIncr[channel] *
(progRep->dmaSize/MCD_remVariants.remXferSize[channel]));
break;
case ZERO:
progRep->lastSrcAddr = progRep->currBufDesc->srcAddr;
break;
case PLUS1:
progRep->lastSrcAddr =
progRep->currBufDesc->srcAddr +
( MCD_remVariants.remSrcIncr[channel] *
(progRep->dmaSize/MCD_remVariants.remXferSize[channel]));
break;
default: break;
}
return(MCD_OK);
}
/******************* End of MCD_XferProgrQuery() ********************/
/********************************************************************/
/* MCD_resmActions() does the majority of the actions of a DMA resume.
* It is called from MCD_killDma() and MCD_resumeDma(). It has to be
* a separate function because the kill function has to negate the task
* enable before resuming it, but the resume function has to do nothing
* if there is no DMA on that channel (i.e., if the enable bit is 0).
*/
static void MCD_resmActions (int channel)
{
MCD_dmaBar->debugControl = DBG_CTL_DISABLE;
MCD_dmaBar->debugStatus = MCD_dmaBar->debugStatus;
MCD_dmaBar->ptdDebug = PTD_DBG_TSK_VLD_INIT; /* This register is selected to know
which initiator is actually asserted. */
if((MCD_dmaBar->ptdDebug >> channel ) & 0x1)
MCD_chStatus[channel] = MCD_RUNNING;
else
MCD_chStatus[channel] = MCD_IDLE;
}
/********************* End of MCD_resmActions() *********************/
/********************************************************************/
/* Function: MCD_killDma
* Purpose: Halt the DMA on the requested channel, without any
* intention of resuming the DMA.
* Arguments: channel - requested channel
* Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
*
* Notes:
* A DMA may be killed from any state, including paused state, and it
* always goes to the MCD_HALTED state even if it is killed while in
* the MCD_NO_DMA or MCD_IDLE states.
*/
int MCD_killDma (int channel)
{
/* MCD_XferProg progRep; */
if((channel < 0) || (channel >= NCHANNELS))
return(MCD_CHANNEL_INVALID);
MCD_dmaBar->taskControl[channel] = 0x0;
MCD_resumeDma (channel);
/*
* This must be after the write to the TCR so that the task doesn't
* start up again momentarily, and before the status assignment so
* as to override whatever MCD_resumeDma() may do to the channel
* status.
*/
MCD_chStatus[channel] = MCD_HALTED;
/*
* Update the current buffer descriptor's lastDestAddr field
*
* MCD_XferProgrQuery (channel, &progRep);
* progRep.currBufDesc->lastDestAddr = progRep.lastDestAddr;
*/
return(MCD_OK);
}
/************************ End of MCD_killDma() **********************/
/********************************************************************/
/* Function: MCD_continDma
* Purpose: Continue a DMA which as stopped due to encountering an
* unready buffer descriptor.
* Arguments: channel - channel to continue the DMA on
* Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
*
* Notes:
* This routine does not check to see if there is a task which can
* be continued. Also this routine should not be used with single DMAs.
*/
int MCD_continDma (int channel)
{
if((channel < 0) || (channel >= NCHANNELS))
return(MCD_CHANNEL_INVALID);
MCD_dmaBar->taskControl[channel] |= TASK_CTL_EN;
MCD_chStatus[channel] = MCD_RUNNING;
return(MCD_OK);
}
/********************** End of MCD_continDma() **********************/
/*********************************************************************
* MCD_pauseDma() and MCD_resumeDma() below use the DMA's debug unit
* to freeze a task and resume it. We freeze a task by breakpointing
* on the stated task. That is, not any specific place in the task,
* but any time that task executes. In particular, when that task
* executes, we want to freeze that task and only that task.
*
* The bits of the debug control register influence interrupts vs.
* breakpoints as follows:
* - Bits 14 and 0 enable or disable debug functions. If enabled, you
* will get the interrupt but you may or may not get a breakpoint.
* - Bits 2 and 1 decide whether you also get a breakpoint in addition
* to an interrupt.
*
* The debug unit can do these actions in response to either internally
* detected breakpoint conditions from the comparators, or in response
* to the external breakpoint pin, or both.
* - Bits 14 and 1 perform the above-described functions for
* internally-generated conditions, i.e., the debug comparators.
* - Bits 0 and 2 perform the above-described functions for external
* conditions, i.e., the breakpoint external pin.
*
* Note that, although you "always" get the interrupt when you turn
* the debug functions, the interrupt can nevertheless, if desired, be
* masked by the corresponding bit in the PTD's IMR. Note also that
* this means that bits 14 and 0 must enable debug functions before
* bits 1 and 2, respectively, have any effect.
*
* NOTE: It's extremely important to not pause more than one DMA channel
* at a time.
********************************************************************/
/********************************************************************/
/* Function: MCD_pauseDma
* Purpose: Pauses the DMA on a given channel (if any DMA is running
* on that channel).
* Arguments: channel
* Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
*/
int MCD_pauseDma (int channel)
{
/* MCD_XferProg progRep; */
if((channel < 0) || (channel >= NCHANNELS))
return(MCD_CHANNEL_INVALID);
if (MCD_dmaBar->taskControl[channel] & TASK_CTL_EN)
{
MCD_dmaBar->debugComp1 = channel;
MCD_dmaBar->debugControl = DBG_CTL_ENABLE | (1 << (channel + 16));
MCD_chStatus[channel] = MCD_PAUSED;
/*
* Update the current buffer descriptor's lastDestAddr field
*
* MCD_XferProgrQuery (channel, &progRep);
* progRep.currBufDesc->lastDestAddr = progRep.lastDestAddr;
*/
}
return(MCD_OK);
}
/************************* End of MCD_pauseDma() ********************/
/********************************************************************/
/* Function: MCD_resumeDma
* Purpose: Resumes the DMA on a given channel (if any DMA is
* running on that channel).
* Arguments: channel - channel on which to resume DMA
* Returns: MCD_CHANNEL_INVALID if channel is invalid, else MCD_OK
*/
int MCD_resumeDma (int channel)
{
if((channel < 0) || (channel >= NCHANNELS))
return(MCD_CHANNEL_INVALID);
if (MCD_dmaBar->taskControl[channel] & TASK_CTL_EN)
MCD_resmActions (channel);
return(MCD_OK);
}
/************************ End of MCD_resumeDma() ********************/
/********************************************************************/
/* Function: MCD_csumQuery
* Purpose: Provide the checksum after performing a non-chained DMA
* Arguments: channel - channel to report on
* csum - pointer to where to write the checksum/CRC
* Returns: MCD_ERROR if the channel is invalid, else MCD_OK
*
* Notes:
*
*/
int MCD_csumQuery (int channel, u32 *csum)
{
#ifdef MCD_INCLUDE_EU
if((channel < 0) || (channel >= NCHANNELS))
return(MCD_CHANNEL_INVALID);
*csum = MCD_relocBuffDesc[channel].csumResult;
return(MCD_OK);
#else
return(MCD_ERROR);
#endif
}
/*********************** End of MCD_resumeDma() *********************/
/********************************************************************/
/* Function: MCD_getCodeSize
* Purpose: Provide the size requirements of the microcoded tasks
* Returns: Size in bytes
*/
int MCD_getCodeSize(void)
{
#ifdef MCD_INCLUDE_EU
return(0x2b5c);
#else
return(0x173c);
#endif
}
/********************** End of MCD_getCodeSize() ********************/
/********************************************************************/
/* Function: MCD_getVersion
* Purpose: Provide the version string and number
* Arguments: longVersion - user supplied pointer to a pointer to a char
* which points to the version string
* Returns: Version number and version string (by reference)
*/
char MCD_versionString[] = "Multi-channel DMA API Alpha v0.3 (2004-04-26)";
#define MCD_REV_MAJOR 0x00
#define MCD_REV_MINOR 0x03
int MCD_getVersion(char **longVersion)
{
*longVersion = MCD_versionString;
return((MCD_REV_MAJOR << 8) | MCD_REV_MINOR);
}
/********************** End of MCD_getVersion() *********************/
/********************************************************************/
/* Private version of memcpy()
* Note that everything this is used for is longword-aligned.
*/
static void MCD_memcpy (int *dest, int *src, u32 size)
{
u32 i;
for (i = 0; i < size; i += sizeof(int), dest++, src++)
*dest = *src;
}
/********************************************************************/

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sources/MCD_tasks.c Normal file
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sources/MCD_tasksInit.c Normal file
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/*
* File: MCD_tasksInit.c
* Purpose: Functions for initializing variable tables of different
* types of tasks.
*
* Notes:
*/
/*
* Do not edit!
*/
#include "MCD_dma.h"
extern dmaRegs *MCD_dmaBar;
/*
* Task 0
*/
void MCD_startDmaChainNoEu(int *currBD, short srcIncr, short destIncr, int xferSize, short xferSizeIncr, int *cSave, volatile TaskTableEntry *taskTable, int channel)
{
MCD_SET_VAR(taskTable+channel, 2, (u32)currBD); /* var[2] */
MCD_SET_VAR(taskTable+channel, 25, (u32)(0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */
MCD_SET_VAR(taskTable+channel, 24, (u32)(0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */
MCD_SET_VAR(taskTable+channel, 11, (u32)xferSize); /* var[11] */
MCD_SET_VAR(taskTable+channel, 26, (u32)(0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */
MCD_SET_VAR(taskTable+channel, 0, (u32)cSave); /* var[0] */
MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */
MCD_SET_VAR(taskTable+channel, 3, (u32)0x00000000); /* var[3] */
MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */
MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */
MCD_SET_VAR(taskTable+channel, 6, (u32)0x00000000); /* var[6] */
MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */
MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */
MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000000); /* var[9] */
MCD_SET_VAR(taskTable+channel, 10, (u32)0x00000000); /* var[10] */
MCD_SET_VAR(taskTable+channel, 12, (u32)0x00000000); /* var[12] */
MCD_SET_VAR(taskTable+channel, 13, (u32)0x80000000); /* var[13] */
MCD_SET_VAR(taskTable+channel, 14, (u32)0x00000010); /* var[14] */
MCD_SET_VAR(taskTable+channel, 15, (u32)0x00000004); /* var[15] */
MCD_SET_VAR(taskTable+channel, 16, (u32)0x08000000); /* var[16] */
MCD_SET_VAR(taskTable+channel, 27, (u32)0x00000000); /* inc[3] */
MCD_SET_VAR(taskTable+channel, 28, (u32)0x80000000); /* inc[4] */
MCD_SET_VAR(taskTable+channel, 29, (u32)0x80000001); /* inc[5] */
MCD_SET_VAR(taskTable+channel, 30, (u32)0x40000000); /* inc[6] */
/* Set the task's Enable bit in its Task Control Register */
MCD_dmaBar->taskControl[channel] |= (u16)0x8000;
}
/*
* Task 1
*/
void MCD_startDmaSingleNoEu(char *srcAddr, short srcIncr, char *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel)
{
MCD_SET_VAR(taskTable+channel, 7, (u32)srcAddr); /* var[7] */
MCD_SET_VAR(taskTable+channel, 25, (u32)(0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */
MCD_SET_VAR(taskTable+channel, 2, (u32)destAddr); /* var[2] */
MCD_SET_VAR(taskTable+channel, 24, (u32)(0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */
MCD_SET_VAR(taskTable+channel, 3, (u32)dmaSize); /* var[3] */
MCD_SET_VAR(taskTable+channel, 26, (u32)(0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */
MCD_SET_VAR(taskTable+channel, 5, (u32)flags); /* var[5] */
MCD_SET_VAR(taskTable+channel, 1, (u32)currBD); /* var[1] */
MCD_SET_VAR(taskTable+channel, 0, (u32)cSave); /* var[0] */
MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */
MCD_SET_VAR(taskTable+channel, 6, (u32)0x00000000); /* var[6] */
MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */
MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000004); /* var[9] */
MCD_SET_VAR(taskTable+channel, 10, (u32)0x08000000); /* var[10] */
MCD_SET_VAR(taskTable+channel, 27, (u32)0x00000000); /* inc[3] */
MCD_SET_VAR(taskTable+channel, 28, (u32)0x80000001); /* inc[4] */
MCD_SET_VAR(taskTable+channel, 29, (u32)0x40000000); /* inc[5] */
/* Set the task's Enable bit in its Task Control Register */
MCD_dmaBar->taskControl[channel] |= (u16)0x8000;
}
/*
* Task 2
*/
void MCD_startDmaChainEu(int *currBD, short srcIncr, short destIncr, int xferSize, short xferSizeIncr, int *cSave, volatile TaskTableEntry *taskTable, int channel)
{
MCD_SET_VAR(taskTable+channel, 3, (u32)currBD); /* var[3] */
MCD_SET_VAR(taskTable+channel, 25, (u32)(0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */
MCD_SET_VAR(taskTable+channel, 24, (u32)(0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */
MCD_SET_VAR(taskTable+channel, 12, (u32)xferSize); /* var[12] */
MCD_SET_VAR(taskTable+channel, 26, (u32)(0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */
MCD_SET_VAR(taskTable+channel, 0, (u32)cSave); /* var[0] */
MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */
MCD_SET_VAR(taskTable+channel, 2, (u32)0x00000000); /* var[2] */
MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */
MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */
MCD_SET_VAR(taskTable+channel, 6, (u32)0x00000000); /* var[6] */
MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */
MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */
MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000000); /* var[9] */
MCD_SET_VAR(taskTable+channel, 10, (u32)0x00000000); /* var[10] */
MCD_SET_VAR(taskTable+channel, 11, (u32)0x00000000); /* var[11] */
MCD_SET_VAR(taskTable+channel, 13, (u32)0x00000000); /* var[13] */
MCD_SET_VAR(taskTable+channel, 14, (u32)0x80000000); /* var[14] */
MCD_SET_VAR(taskTable+channel, 15, (u32)0x00000010); /* var[15] */
MCD_SET_VAR(taskTable+channel, 16, (u32)0x00000001); /* var[16] */
MCD_SET_VAR(taskTable+channel, 17, (u32)0x00000004); /* var[17] */
MCD_SET_VAR(taskTable+channel, 18, (u32)0x08000000); /* var[18] */
MCD_SET_VAR(taskTable+channel, 27, (u32)0x00000000); /* inc[3] */
MCD_SET_VAR(taskTable+channel, 28, (u32)0x80000000); /* inc[4] */
MCD_SET_VAR(taskTable+channel, 29, (u32)0xc0000000); /* inc[5] */
MCD_SET_VAR(taskTable+channel, 30, (u32)0x80000001); /* inc[6] */
MCD_SET_VAR(taskTable+channel, 31, (u32)0x40000000); /* inc[7] */
/* Set the task's Enable bit in its Task Control Register */
MCD_dmaBar->taskControl[channel] |= (u16)0x8000;
}
/*
* Task 3
*/
void MCD_startDmaSingleEu(char *srcAddr, short srcIncr, char *destAddr, short destIncr, int dmaSize, short xferSizeIncr, int flags, int *currBD, int *cSave, volatile TaskTableEntry *taskTable, int channel)
{
MCD_SET_VAR(taskTable+channel, 8, (u32)srcAddr); /* var[8] */
MCD_SET_VAR(taskTable+channel, 25, (u32)(0xe000 << 16) | (0xffff & srcIncr)); /* inc[1] */
MCD_SET_VAR(taskTable+channel, 3, (u32)destAddr); /* var[3] */
MCD_SET_VAR(taskTable+channel, 24, (u32)(0xe000 << 16) | (0xffff & destIncr)); /* inc[0] */
MCD_SET_VAR(taskTable+channel, 4, (u32)dmaSize); /* var[4] */
MCD_SET_VAR(taskTable+channel, 26, (u32)(0x2000 << 16) | (0xffff & xferSizeIncr)); /* inc[2] */
MCD_SET_VAR(taskTable+channel, 6, (u32)flags); /* var[6] */
MCD_SET_VAR(taskTable+channel, 2, (u32)currBD); /* var[2] */
MCD_SET_VAR(taskTable+channel, 0, (u32)cSave); /* var[0] */
MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */
MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */
MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */
MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000000); /* var[9] */
MCD_SET_VAR(taskTable+channel, 10, (u32)0x00000001); /* var[10] */
MCD_SET_VAR(taskTable+channel, 11, (u32)0x00000004); /* var[11] */
MCD_SET_VAR(taskTable+channel, 12, (u32)0x08000000); /* var[12] */
MCD_SET_VAR(taskTable+channel, 27, (u32)0x00000000); /* inc[3] */
MCD_SET_VAR(taskTable+channel, 28, (u32)0xc0000000); /* inc[4] */
MCD_SET_VAR(taskTable+channel, 29, (u32)0x80000000); /* inc[5] */
MCD_SET_VAR(taskTable+channel, 30, (u32)0x80000001); /* inc[6] */
MCD_SET_VAR(taskTable+channel, 31, (u32)0x40000000); /* inc[7] */
/* Set the task's Enable bit in its Task Control Register */
MCD_dmaBar->taskControl[channel] |= (u16)0x8000;
}
/*
* Task 4
*/
void MCD_startDmaENetRcv(char *bDBase, char *currBD, char *rcvFifoPtr, volatile TaskTableEntry *taskTable, int channel)
{
MCD_SET_VAR(taskTable+channel, 0, (u32)bDBase); /* var[0] */
MCD_SET_VAR(taskTable+channel, 3, (u32)currBD); /* var[3] */
MCD_SET_VAR(taskTable+channel, 6, (u32)rcvFifoPtr); /* var[6] */
MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */
MCD_SET_VAR(taskTable+channel, 2, (u32)0x00000000); /* var[2] */
MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */
MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */
MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */
MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */
MCD_SET_VAR(taskTable+channel, 9, (u32)0x0000ffff); /* var[9] */
MCD_SET_VAR(taskTable+channel, 10, (u32)0x30000000); /* var[10] */
MCD_SET_VAR(taskTable+channel, 11, (u32)0x0fffffff); /* var[11] */
MCD_SET_VAR(taskTable+channel, 12, (u32)0x00000008); /* var[12] */
MCD_SET_VAR(taskTable+channel, 24, (u32)0x00000000); /* inc[0] */
MCD_SET_VAR(taskTable+channel, 25, (u32)0x60000000); /* inc[1] */
MCD_SET_VAR(taskTable+channel, 26, (u32)0x20000004); /* inc[2] */
MCD_SET_VAR(taskTable+channel, 27, (u32)0x40000000); /* inc[3] */
/* Set the task's Enable bit in its Task Control Register */
MCD_dmaBar->taskControl[channel] |= (u16)0x8000;
}
/*
* Task 5
*/
void MCD_startDmaENetXmit(char *bDBase, char *currBD, char *xmitFifoPtr, volatile TaskTableEntry *taskTable, int channel)
{
MCD_SET_VAR(taskTable+channel, 0, (u32)bDBase); /* var[0] */
MCD_SET_VAR(taskTable+channel, 3, (u32)currBD); /* var[3] */
MCD_SET_VAR(taskTable+channel, 11, (u32)xmitFifoPtr); /* var[11] */
MCD_SET_VAR(taskTable+channel, 1, (u32)0x00000000); /* var[1] */
MCD_SET_VAR(taskTable+channel, 2, (u32)0x00000000); /* var[2] */
MCD_SET_VAR(taskTable+channel, 4, (u32)0x00000000); /* var[4] */
MCD_SET_VAR(taskTable+channel, 5, (u32)0x00000000); /* var[5] */
MCD_SET_VAR(taskTable+channel, 6, (u32)0x00000000); /* var[6] */
MCD_SET_VAR(taskTable+channel, 7, (u32)0x00000000); /* var[7] */
MCD_SET_VAR(taskTable+channel, 8, (u32)0x00000000); /* var[8] */
MCD_SET_VAR(taskTable+channel, 9, (u32)0x00000000); /* var[9] */
MCD_SET_VAR(taskTable+channel, 10, (u32)0x00000000); /* var[10] */
MCD_SET_VAR(taskTable+channel, 12, (u32)0x00000000); /* var[12] */
MCD_SET_VAR(taskTable+channel, 13, (u32)0x0000ffff); /* var[13] */
MCD_SET_VAR(taskTable+channel, 14, (u32)0xffffffff); /* var[14] */
MCD_SET_VAR(taskTable+channel, 15, (u32)0x00000004); /* var[15] */
MCD_SET_VAR(taskTable+channel, 16, (u32)0x00000008); /* var[16] */
MCD_SET_VAR(taskTable+channel, 24, (u32)0x00000000); /* inc[0] */
MCD_SET_VAR(taskTable+channel, 25, (u32)0x60000000); /* inc[1] */
MCD_SET_VAR(taskTable+channel, 26, (u32)0x40000000); /* inc[2] */
MCD_SET_VAR(taskTable+channel, 27, (u32)0xc000fffc); /* inc[3] */
MCD_SET_VAR(taskTable+channel, 28, (u32)0xe0000004); /* inc[4] */
MCD_SET_VAR(taskTable+channel, 29, (u32)0x80000000); /* inc[5] */
MCD_SET_VAR(taskTable+channel, 30, (u32)0x4000ffff); /* inc[6] */
MCD_SET_VAR(taskTable+channel, 31, (u32)0xe0000001); /* inc[7] */
/* Set the task's Enable bit in its Task Control Register */
MCD_dmaBar->taskControl[channel] |= (u16)0x8000;
}

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/*
* BaS
*
*/
#include "MCF5475.h"
#include "startcf.h"
#include "MCD_dma.h"
#define MBAR_BASE_ADRS 0xff000000
#define MMAP_DMA 0x00008000
#define MMAP_SRAM 0x00010000
extern unsigned long far __SP_AFTER_RESET[];
extern unsigned long far __Bas_base[];
/* imported routines */
extern int mmu_init();
extern int mmutr_miss();
extern int vec_init();
extern int illegal_table_make();
extern int cf68k_initialize();
/********************************************************************/
/* warte_routinen /*
********************************************************************/
void warte_10ms(void)
{
asm
{
warte_10ms:
move.l d0,-(sp)
move.l MCF_SLT0_SCNT,d0
sub.l #1320000,d0
warte_d6:
cmp.l MCF_SLT0_SCNT,d0
bcs warte_d6
move.l (sp)+,d0
}
}
void warte_1ms(void)
{
asm
{
warte_1ms:
move.l d0,-(sp)
move.l MCF_SLT0_SCNT,d0
sub.l #132000,d0
warte_d6:
cmp.l MCF_SLT0_SCNT,d0
bcs warte_d6
move.l (sp)+,d0
}
}
void warte_100us(void)
{
asm
{
warte_100us:
move.l d0,-(sp)
move.l MCF_SLT0_SCNT,d0
sub.l #13200,d0
warte_d6:
cmp.l MCF_SLT0_SCNT,d0
bcs warte_d6
move.l (sp)+,d0
}
}
void warte_50us(void)
{
asm
{
warte_50us:
move.l d0,-(sp)
move.l MCF_SLT0_SCNT,d0
sub.l #6600,d0
warte_d6:
cmp.l MCF_SLT0_SCNT,d0
bcs warte_d6
move.l (sp)+,d0
}
}
void warte_10us(void)
{
asm
{
warte_10us:
move.l d0,-(sp)
move.l MCF_SLT0_SCNT,d0
sub.l #1320,d0
warte_d6:
cmp.l MCF_SLT0_SCNT,d0
bcs warte_d6
move.l (sp)+,d0
}
}
void warte_1us(void)
{
asm
{
warte_1us:
move.l d0,-(sp)
move.l MCF_SLT0_SCNT,d0
sub.l #132,d0
warte_d6:
cmp.l MCF_SLT0_SCNT,d0
bcs warte_d6
move.l (sp)+,d0
}
}
/********************************************************************/
void BaS(void)
{
int az_sectors;
int sd_status,i;
int status;
int dma_task_nr = 0;
az_sectors = sd_card_init();
if(az_sectors>0)
{
sd_card_idle();
}
/* variablenbereich setzen*/
asm
{
lea 0x1fc00000,a5
lea 0x1fd00000,a6
}
init_dma:
status =
MCD_initDma(
(dmaRegs*) (MBAR_BASE_ADRS + MMAP_DMA),
(void*) (MBAR_BASE_ADRS + MMAP_SRAM),
(MCD_RELOC_TASKS)
);
status = MCD_startDma(0, /*int channel, /* the channel on which to run the DMA */
(char*) (0xfff00000), /*s8 *srcAddr, /* the address to move data from, or physical buffer-descriptor address */
0, /*s16 srcIncr, /* the amount to increment the source address per transfer */
(char*) (0x12345678), /*s8 *destAddr, /* the address to move data to */
2, /*s16 destIncr, /* the amount to increment the destination address per transfer */
512, /*u32 dmaSize, /* the number of bytes to transfer independent of the transfer size */
2, /*u32 xferSize, /* the number bytes in of each data movement (1, 2, or 4) */
3, /*u32 initiator, /* what device initiates the DMA */
4, /*int priority, /* priority of the DMA */
MCD_SINGLE_DMA+
MCD_TT_FLAGS_CW+
MCD_TT_FLAGS_RL+
MCD_TT_FLAGS_SP, /*u32 flags, /* flags describing the DMA */
MCD_NO_BYTE_SWAP+
MCD_NO_BIT_REV /*u32 funcDesc /* a description of byte swapping, bit swapping, and CRC actions */
);
status =
MCD_dmaStatus(0);
MCD_killDma(0);
asm
{
move.b DIP_SWITCH,d0 // dip schalter adresse
btst.b #6,d0
beq firetos_kopieren
lea MCF_PSC0_PSCTB_8BIT,a6
lea MCF_PSC3_PSCTB_8BIT,a3
lea MCF_PSC3_PSCRB_8BIT,a4
lea MCF_PSC3_PSCRFCNT,a5
move.l #'ACPF',(a3) // SEND SYNC MARKE, MCF BEREIT
bsr warte_10ms
move.l #'PIC ',(a6)
move.b (a4),d0
move.b d0,(a6)
move.b (a4),d1
move.b d1,(a6)
move.b (a4),d2
move.b d2,(a6)
move.l #0x0a0d,(a6)
move.b #0x01,(a3) // RTC DATEN ANFORDERN
// TOS kopieren
lea 0x00e00000,a0
lea 0xe0600000,a1 // default tos
lea 0xe0700000,a2 // 1MB
move.b DIP_SWITCH,d0 // dip schalter adresse
btst.b #6,d0
bne cptos_loop
firetos_kopieren:
lea 0x00e00000,a0
lea 0xe0400000,a1
lea 0xe0500000,a2 // 1MB
cptos_loop:
move.l (a1)+,(a0)+
cmp.l a2,a1
blt cptos_loop
/***************************************************************/
/* div inits
/***************************************************************/
div_inits:
move.b DIP_SWITCH,d0 // dip schalter adresse
btst.b #6,d0
beq video_setup
// rtc daten, mmu set, etc nur wenn switch 6 = off
lea 0xffff8961,a0
clr.l d1
moveq #64,d2
move.b (a4),d0
cmp.b #0x81,d0
bne not_rtc
loop_sr:
move.b (a4),d0
move.b d1,(a0)
move.b d0,2(a0)
addq.l #1,d1
cmp.b d1,d2
bne loop_sr
move.b #63,(a0)
move.b 2(a0),d0
add #1,d0
move.b d0,2(a0)
not_rtc:
bsr mmu_init
bsr vec_init
bsr illegal_table_make
// interrupts
clr.l 0xf0010004 // disable all interrupts
lea MCF_EPORT_EPPAR,a0
move.w #0xaaa8,(a0) // falling edge all,
// timer 0 on mit int -> video change -------------------------------------------
move.l #MCF_GPT_GMS_ICT(1)|MCF_GPT_GMS_IEN|MCF_GPT_GMS_TMS(1),d0 //caputre mit int on rising edge
move.l d0,MCF_GPT0_GMS
moveq.l #0x3f,d0 // max prority interrutp
move.b d0,MCF_INTC_ICR62 // setzen
// -------------------------------------------------
move.b #0xfe,d0
move.b d0,0xf0010004 // enable int 1-7
nop
lea MCF_EPORT_EPIER,a0
move.b #0xfe,(a0) // int 1-7 on
nop
lea MCF_EPORT_EPFR,a0
move.b #0xff,(a0) // alle pending interrupts l<>schen
nop
lea MCF_INTC_IMRL,a0
move.l #0xFFFFFF00,(a0) // int 1-7 on
lea MCF_INTC_IMRH,a0
move.l #0xBFFFFFFE,(a0) // psc3 and timer 0 int on
move.l #MCF_MMU_MMUCR_EN,d0
move.l d0,MCF_MMU_MMUCR // mmu on
nop
nop
/********************************************************************/
/* IDE reset
/********************************************************************/
lea 0xffff8802,a0
move.b #14,-2(a0)
move.b #0x80,(a0)
bsr warte_1ms
clr.b (a0)
/********************************************************************/
/* video setup
/********************************************************************/
video_setup:
lea 0xf0000410,a0
// 25MHz
move.l #0x032002ba,(a0)+ // horizontal 640x480
move.l #0x020c020a,(a0)+ // vertikal 640x480
move.l #0x0190015d,(a0)+ // horizontal 320x240
move.l #0x020C020A,(a0)+ // vertikal 320x240 */
/*
// 32MHz
move.l #0x037002ba,(a0)+ // horizontal 640x480
move.l #0x020d020a,(a0)+ // vertikal 640x480
move.l #0x02A001e0,(a0)+ // horizontal 320x240
move.l #0x05a00160,(a0)+ // vertikal 320x240
*/
lea -0x20(a0),a0
move.l #0x01070002,(a0) // fifo on, refresh on, ddrcs und cke on, video dac on,
/********************************************************************/
/* memory setup
/********************************************************************/
lea 0x400,a0
lea 0x800,a1
mem_clr_loop:
clr.l (a0)+
clr.l (a0)+
clr.l (a0)+
clr.l (a0)+
cmp.l a0,a1
bgt mem_clr_loop
moveq #0x48,d0
move.b d0,0xffff8007
// stram
move.l #0xe00000,d0 // ende stram
move.l d0,0x42e
move.l #0x752019f3,d0 // memvalid
move.l d0,0x420
move.l #0x237698aa,d0 // memval2
move.l d0,0x43a
move.l #0x5555aaaa,d0 // memval3
move.l d0,0x51a
// ttram
move.l #__Bas_base,d0 // ende ttram
move.l d0,0x5a4
move.l #0x1357bd13,d0 // ramvalid
move.l d0,0x5a8
// init acia
moveq #3,d0
move.b d0,0xfffffc00
nop
move.b d0,0xfffffc04
nop
moveq #0x96,d0
move.b d0,0xfffffc00
moveq #-1,d0
nop
move.b d0,0xfffffa0f
nop
move.b d0,0xfffffa11
nop
// test auf protect mode ---------------------
move.b DIP_SWITCH,d0
btst #7,d0
beq no_protect // nein->
move.w #0x0700,sr
no_protect:
jmp 0xe00030
}
}

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/*
* BaS
*
*/
#include "MCF5475.h"
#include "startcf.h"
#include "MCD_dma.h"
#define MBAR_BASE_ADRS 0xff000000
#define MMAP_DMA 0x00008000
#define MMAP_SRAM 0x00010000
extern unsigned long far __SP_AFTER_RESET[];
extern unsigned long far __Bas_base[];
/* imported routines */
extern int mmu_init();
extern int mmutr_miss();
extern int vec_init();
extern int illegal_table_make();
extern int cf68k_initialize();
/********************************************************************/
/* warte_routinen /*
********************************************************************/
void warte_10ms(void)
{
asm
{
warte_10ms:
move.l d0,-(sp)
move.l MCF_SLT0_SCNT,d0
sub.l #1320000,d0
warte_d6:
cmp.l MCF_SLT0_SCNT,d0
bcs warte_d6
move.l (sp)+,d0
}
}
void warte_1ms(void)
{
asm
{
warte_1ms:
move.l d0,-(sp)
move.l MCF_SLT0_SCNT,d0
sub.l #132000,d0
warte_d6:
cmp.l MCF_SLT0_SCNT,d0
bcs warte_d6
move.l (sp)+,d0
}
}
void warte_100us(void)
{
asm
{
warte_100us:
move.l d0,-(sp)
move.l MCF_SLT0_SCNT,d0
sub.l #13200,d0
warte_d6:
cmp.l MCF_SLT0_SCNT,d0
bcs warte_d6
move.l (sp)+,d0
}
}
void warte_50us(void)
{
asm
{
warte_50us:
move.l d0,-(sp)
move.l MCF_SLT0_SCNT,d0
sub.l #6600,d0
warte_d6:
cmp.l MCF_SLT0_SCNT,d0
bcs warte_d6
move.l (sp)+,d0
}
}
void warte_10us(void)
{
asm
{
warte_10us:
move.l d0,-(sp)
move.l MCF_SLT0_SCNT,d0
sub.l #1320,d0
warte_d6:
cmp.l MCF_SLT0_SCNT,d0
bcs warte_d6
move.l (sp)+,d0
}
}
void warte_1us(void)
{
asm
{
warte_1us:
move.l d0,-(sp)
move.l MCF_SLT0_SCNT,d0
sub.l #132,d0
warte_d6:
cmp.l MCF_SLT0_SCNT,d0
bcs warte_d6
move.l (sp)+,d0
}
}
/********************************************************************/
void BaS(void)
{
int az_sectors;
int sd_status,i;
int status;
int dma_task_nr = 0;
az_sectors = sd_card_init();
if(az_sectors>0)
{
sd_card_idle();
}
asm
{
move.b DIP_SWITCH,d0 // dip schalter adresse
btst.b #6,d0
beq firetos_kopieren
lea MCF_PSC0_PSCTB_8BIT,a6
lea MCF_PSC3_PSCTB_8BIT,a3
lea MCF_PSC3_PSCRB_8BIT,a4
lea MCF_PSC3_PSCRFCNT,a5
move.l #'ACPF',(a3) // SEND SYNC MARKE, MCF BEREIT
bsr warte_10ms
move.l #'PIC ',(a6)
move.b (a4),d0
move.b d0,(a6)
move.b (a4),d1
move.b d1,(a6)
move.b (a4),d2
move.b d2,(a6)
move.l #0x0a0d,(a6)
move.b #0x01,(a3) // RTC DATEN ANFORDERN
// TOS kopieren
lea 0x00e00000,a0
lea 0xe0600000,a1 // default tos
lea 0xe0700000,a2 // 1MB
move.b DIP_SWITCH,d0 // dip schalter adresse
btst.b #6,d0
bne cptos_loop
firetos_kopieren:
lea 0x00e00000,a0
lea 0xe0400000,a1
lea 0xe0500000,a2 // 1MB
cptos_loop:
move.l (a1)+,(a0)+
cmp.l a2,a1
blt cptos_loop
/***************************************************************/
/* div inits
/***************************************************************/
div_inits:
move.b DIP_SWITCH,d0 // dip schalter adresse
btst.b #6,d0
beq video_setup
// rtc daten, mmu set, etc nur wenn switch 6 = off
lea 0xffff8961,a0
clr.l d1
moveq #64,d2
move.b (a4),d0
cmp.b #0x81,d0
bne not_rtc
loop_sr:
move.b (a4),d0
move.b d1,(a0)
move.b d0,2(a0)
addq.l #1,d1
cmp.b d1,d2
bne loop_sr
move.b #63,(a0)
move.b 2(a0),d0
add #1,d0
move.b d0,2(a0)
not_rtc:
bsr mmu_init
bsr vec_init
bsr illegal_table_make
// interrupts
clr.l 0xf0010004 // disable all interrupts
lea MCF_EPORT_EPPAR,a0
move.w #0xaaa8,(a0) // falling edge all,
// timer 0 on mit int -> video change -------------------------------------------
move.l #MCF_GPT_GMS_ICT(1)|MCF_GPT_GMS_IEN|MCF_GPT_GMS_TMS(1),d0 //caputre mit int on rising edge
move.l d0,MCF_GPT0_GMS
moveq.l #0x3f,d0 // max prority interrutp
move.b d0,MCF_INTC_ICR62 // setzen
// -------------------------------------------------
move.b #0xfe,d0
move.b d0,0xf0010004 // enable int 1-7
nop
lea MCF_EPORT_EPIER,a0
move.b #0xfe,(a0) // int 1-7 on
nop
lea MCF_EPORT_EPFR,a0
move.b #0xff,(a0) // alle pending interrupts l<>schen
nop
lea MCF_INTC_IMRL,a0
move.l #0xFFFFFF00,(a0) // int 1-7 on
lea MCF_INTC_IMRH,a0
move.l #0xBFFFFFFE,(a0) // psc3 and timer 0 int on
move.l #MCF_MMU_MMUCR_EN,d0
move.l d0,MCF_MMU_MMUCR // mmu on
nop
nop
/********************************************************************/
/* IDE reset
/********************************************************************/
lea 0xffff8802,a0
move.b #14,-2(a0)
move.b #0x80,(a0)
bsr warte_1ms
clr.b (a0)
/********************************************************************/
/* video setup
/********************************************************************/
video_setup:
lea 0xf0000410,a0
// 25MHz
move.l #0x032002ba,(a0)+ // horizontal 640x480
move.l #0x020c020a,(a0)+ // vertikal 640x480
move.l #0x0190015d,(a0)+ // horizontal 320x240
move.l #0x020C020A,(a0)+ // vertikal 320x240 */
/*
// 32MHz
move.l #0x037002ba,(a0)+ // horizontal 640x480
move.l #0x020d020a,(a0)+ // vertikal 640x480
move.l #0x02A001e0,(a0)+ // horizontal 320x240
move.l #0x05a00160,(a0)+ // vertikal 320x240
*/
lea -0x20(a0),a0
move.l #0x01070002,(a0) // fifo on, refresh on, ddrcs und cke on, video dac on,
/********************************************************************/
/* memory setup
/********************************************************************/
lea 0x400,a0
lea 0x800,a1
mem_clr_loop:
clr.l (a0)+
clr.l (a0)+
clr.l (a0)+
clr.l (a0)+
cmp.l a0,a1
bgt mem_clr_loop
moveq #0x48,d0
move.b d0,0xffff8007
// stram
move.l #0xe00000,d0 // ende stram
move.l d0,0x42e
move.l #0x752019f3,d0 // memvalid
move.l d0,0x420
move.l #0x237698aa,d0 // memval2
move.l d0,0x43a
move.l #0x5555aaaa,d0 // memval3
move.l d0,0x51a
// ttram
move.l #__Bas_base,d0 // ende ttram
move.l d0,0x5a4
move.l #0x1357bd13,d0 // ramvalid
move.l d0,0x5a8
// init acia
moveq #3,d0
move.b d0,0xfffffc00
nop
move.b d0,0xfffffc04
nop
moveq #0x96,d0
move.b d0,0xfffffc00
moveq #-1,d0
nop
move.b d0,0xfffffa0f
nop
move.b d0,0xfffffa11
nop
// test auf protect mode ---------------------
move.b DIP_SWITCH,d0
btst #7,d0
beq no_protect // nein->
move.w #0x0700,sr
no_protect:
jmp 0xe00030
}
}

0
sources/div.s → sources/alt und div/div.s
View File

0
sources/sd_ide.c → sources/alt und div/sd_ide.c
View File

5
sources/ewf.s
View File

@@ -1,6 +1,7 @@
/*************************************************************************************************/
// extension word format: a0 zeigt auf code, in a1 ist ay, d0/d1 wird zerst<EFBFBD>rt
//------------------------------------------------------------------------------
#ifdef ii_on
.include "ii_macro.h"
@@ -1561,5 +1562,5 @@ ewff_lln:
add.l d0,a1
add.l d0,a1
rts
/****************************************************************************************************************
/************************************************************************/
#endif

8
sources/exceptions.s
View File

@@ -4,7 +4,7 @@
.include "startcf.h"
.extern ___Bas_base
.extern ___SDRAM_SIZE
.extern ___SUP_SP
.extern ___BOOT_FLASH
.extern ___RAMBAR0
@@ -362,7 +362,7 @@ access_mmu:
btst #1,d0
bne bus_error
move.l MCF_MMU_MMUAR,d0
cmp.l #___Bas_base,d0 // max User RAM Bereich
cmp.l #___SDRAM_SIZE,d0 // max User RAM Bereich
bge bus_error // gr<EFBFBD>sser -> bus error
bra _mmutr_miss
bus_error:
@@ -421,13 +421,13 @@ flpoow:
nop
irq1:
irq 0x64,1,0x02
irq2: // hbl
irq2: //vsync
// move.b #3,2(a7)
// rte
irq 0x68,2,0x04
irq3:
irq 0x6c,3,0x08
irq4: // vbl
irq4: // vsync
irq 0x70,4,0x10
irq5: // acp
irq 0x74,5,0x20

581
sources/ii_add.h
View File

@@ -1,581 +0,0 @@
//--------------------------------------------------------------------
// add
//--------------------------------------------------------------------
/*****************************************************************************************/
//--------------------------------------------------------------------
// byt
//--------------------------------------------------------------------
//--------------------------------------------------------------------
// add.b #im,dx
//--------------------------------------------------------------------
addbir_macro:.macro
move.w (a0)+,d0
extb.l d0
mvs.b \2,d1
add.l d0,d1
set_cc0
move.b d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // add ea,dx
//--------------------------------------------------------------------
adddd:.macro
#ifdef halten_add
halt
#endif
mvs.\3 \1,d0
mvs.\3 \2,d1
add.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // add ea,dx (first ea->a1 z.B. f<>r a0,a1,USP)
//--------------------------------------------------------------------
addddd:.macro
#ifdef halten_add
halt
#endif
move.l \1,a1
mvs.\3 a1,d0
mvs.\3 \2,d1
add.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // add (ea),dx (first ea->a1 z.B. f<>r a0,a1,USP)
//--------------------------------------------------------------------
adddda:.macro
#ifdef halten_add
halt
#endif
move.l \1,a1
mvs.\3 (a1),d0
mvs.\3 \2,d1
add.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // add (ay)+,dx (first ea->a1 z.B. f<>r a0,a1,USP)
//--------------------------------------------------------------------
addddai:.macro
#ifdef halten_add
halt
#endif
move.l \1,a1
mvs.\3 (a1)+,d0
move.l a1,\1
mvs.\3 \2,d1
add.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // add -(ay),dx (first ea->a1 z.B. f<>r a0,a1,USP)
//--------------------------------------------------------------------
addddad:.macro
#ifdef halten_add
halt
#endif
move.l \1,a1
mvs.\3 -(a1),d0
move.l a1,\1
mvs.\3 \2,d1
add.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // add d16(ay),dx
//--------------------------------------------------------------------
addd16ad:.macro
#ifdef halten_add
halt
#endif
move.l \1,a1
mvs.w (a0)+,d0
add.l d0,a1
mvs.\3 (a1),d0
mvs.\3 \2,d1
add.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // add d8(ay,dy),dx
//--------------------------------------------------------------------
addd8ad:.macro
#ifdef halten_add
halt
#endif
move.l \1,a1
jsr ewf
.ifc \3,l
move.l (a1),d0
move.l \2,d1
.else
mvs.\3 (a1),d0
mvs.\3 \2,d1
.endif
add.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // add xxx.w,dx
//--------------------------------------------------------------------
addxwd:.macro
#ifdef halten_add
halt
#endif
move.w (a0)+,a1
mvs.\3 (a1),d0
mvs.\3 \2,d1
add.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // add xxx.l,dx
//--------------------------------------------------------------------
addxld:.macro
#ifdef halten_add
halt
#endif
move.l (a0)+,a1
mvs.\3 (a1),d0
mvs.\3 \2,d1
add.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // add d16(pc),dx
//--------------------------------------------------------------------
addd16pcd:.macro
#ifdef halten_add
halt
#endif
move.l a0,a1
mvs.w (a0)+,d0
add.l d0,a1
mvs.\3 (a1),d0
mvs.\3 \2,d1
add.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // add d8(pc,dy),dx
//--------------------------------------------------------------------
addd8pcd:.macro
#ifdef halten_add
halt
#endif
move.l a0,a1
jsr ewf
.ifc \3,l
move.l (a1),d0
move.l \2,d1
.else
mvs.\3 (a1),d0
mvs.\3 \2,d1
.endif
add.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// add dy,ea
//--------------------------------------------------------------------
//--------------------------------------------------------------------
// // add dx,(ay) (first ea->a1 z.B. f<>r a0,a1,USP)
//--------------------------------------------------------------------
addeda:.macro
#ifdef halten_add
halt
#endif
mvs.\3 \1,d0
move.l \2,a1
mvs.\3 (a1),d1
add.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------
// // add dx,(ay)+ (first ea->a1 z.B. f<>r a0,a1,USP)
//--------------------------------------------------------------------
addedai:.macro
#ifdef halten_add
halt
#endif
mvs.\3 \1,d0
move.l \2,a1
mvs.\3 (a1),d1
add.l d0,d1
set_cc0
move.\3 d1,(a1)+
move.l a1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // add dx,(ay)+
//--------------------------------------------------------------------
addedaid:.macro
#ifdef halten_add
halt
#endif
mvs.\3 \1,d0
mvs.\3 \2,d1
add.l d0,d1
set_cc0
move.\3 d1,\2+
ii_end
.endm;
//--------------------------------------------------------------------
// // add dx,-(ay)
//--------------------------------------------------------------------
addedad:.macro
#ifdef halten_add
halt
#endif
mvs.\3 \1,d0
move.l \2,a1
mvs.\3 -(a1),d1
move.l a1,\2
add.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------
// // add dx,-(ay)
//--------------------------------------------------------------------
addedadd:.macro
#ifdef halten_add
halt
#endif
mvs.\3 \1,d0
mvs.\3 -\2,d1
add.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // add dx,d16(ay)
//--------------------------------------------------------------------
adde16ad:.macro
#ifdef halten_add
halt
#endif
mvs.\3 \1,d0
move.l \2,a1
mvs.w (a0)+,d1
add.l d1,a1
mvs.\3 (a1),d1
add.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------
// // add.w d8(ay,dy),dx
//--------------------------------------------------------------------
adde8ad:.macro
#ifdef halten_add
halt
#endif
move.l \2,a1
jsr ewf
.ifc \3,l
move.l (a1),d1
move.l \1,d0
.else
mvs.\3 (a1),d1
mvs.\3 \1,d0
.endif
add.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------
// // add dx,xxx.w
//--------------------------------------------------------------------
addxwe:.macro
#ifdef halten_add
halt
#endif
mvs.\3 \1,d0
move.w (a0)+,a1
mvs.\3 (a1),d1
add.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------
// // add dx,xxx.l
//--------------------------------------------------------------------
addxle:.macro
#ifdef halten_add
halt
#endif
mvs.\3 \1,d0
move.l (a0)+,a1
mvs.\3 (a1),d1
add.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
/******************************************************/
// adress register
/******************************************************/
//--------------------------------------------------------------------
// // adda.w ea,ax (ea = dx;ax;(ax);(ax)+,-(ax)
//--------------------------------------------------------------------
addaw:.macro
#ifdef halten_add
halt
#endif
move.l a0,pc_off(a7) // pc auf next
movem.l (a7),d0/d1/a0/a1 // register zurp<72>ck
mvs.w \1,d0
adda.l d0,\2
move.l d0_off(a7),d0
lea ii_ss(a7),a7 // stack erh<72>hen
rte
.endm;
//--------------------------------------------------------------------
// add.w ea,usp
//--------------------------------------------------------------------
addawa7:.macro
#ifdef halten_add
halt
#endif
mvs.w \1,d0
move.l usp,a1
add.l d0,a1
move.l a1,usp
ii_end
.endm;
//--------------------------------------------------------------------
// // adda.w ea,usp (ea = dx;ax;(ax);(ax)+,-(ax)
//--------------------------------------------------------------------
addawu:.macro
#ifdef halten_add
halt
#endif
move.l a0,pc_off(a7) // pc auf next
movem.l (a7),d0/d1/a0/a1 // register zurp<72>ck
move.l a7,_a7_save
move.l usp,a7
move.l \1,d0
adda.l d0,\2
move.l a7,usp
move.l _a7_save,a7
move.l d0_off(a7),d0
lea ii_ss(a7),a7 // stack erh<72>hen
rte
.endm;
//--------------------------------------------------------------------
// // adda.w ea,usp (ea = a7 => dx;ax;(ax);(ax)+,-(ax)
//--------------------------------------------------------------------
addawua7:.macro
addawu \1,\2
.endm;
//--------------------------------------------------------------------
// // adda.w d16(ay),ax
//--------------------------------------------------------------------
addawd16a:.macro
#ifdef halten_add
halt
#endif
move.l \1,a1
mvs.w (a0)+,d0
adda.l d0,a1
mvs.w (a1),d0
move.l \2,a1
add.l d0,a1
move.l a1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // adda.w d8(ay,dy),ax
//--------------------------------------------------------------------
addawd8a:.macro
#ifdef halten_add
halt
#endif
move.l \1,a1
jsr ewf
mvs.w (a1),d0
move.l \2,a1
add.l d0,a1
move.l a1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // adda.w xxx.w,ax
//--------------------------------------------------------------------
addawxwax:.macro
#ifdef halten_add
halt
#endif
move.w \1,a1
mvs.w (a1),d0
move.l \2,a1
adda.l d0,a1
move.l a1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // adda.w xxx.l,ax
//--------------------------------------------------------------------
addawxlax:.macro
#ifdef halten_add
halt
#endif
move.l \1,a1
mvs.w (a1),d0
move.l \2,a1
adda.l d0,a1
move.l a1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // adda.w d16(pc),ax
//--------------------------------------------------------------------
addawd16pcax:.macro
#ifdef halten_add
halt
#endif
move.w \1,a1
adda.l a0,a1
mvs.w (a1),d0
move.l \2,a1
adda.l d0,a1
move.l a1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // adda.w d8(pc,dy),ax
//--------------------------------------------------------------------
addawd8pcax:.macro
#ifdef halten_add
halt
#endif
move.l a0,a1
jsr ewf
mvs.w (a1),d0
move.l \2,a1
adda.l d0,a1
move.l a1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // adda.w #im,ax
//--------------------------------------------------------------------
addawim:.macro
#ifdef halten_add
halt
#endif
mvs.w \1,d0
move.l \2,a1
adda.l d0,a1
move.l a1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // adda.l d8(ay,dy),ax
//--------------------------------------------------------------------
addald8a:.macro
#ifdef halten_add
halt
#endif
move.l \1,a1
jsr ewf
move.l (a1),d0
move.l \2,a1
adda.l d0,a1
move.l a1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // adda.l d8(pc,dy),ax
//--------------------------------------------------------------------
addakd8pcax:.macro
#ifdef halten_add
halt
#endif
move.l a0,a1
jsr ewf
move.l (a1),d0
move.l \2,a1
adda.l d0,a1
move.l a1,\2
ii_end
.endm;
//*****************************************************************************************
// addx
//*****************************************************************************************
//--------------------------------------------------------------------
// // addx dy,dx
//--------------------------------------------------------------------
adddx:.macro
#ifdef halten_add
halt
#endif
move.b sr_off+1(a7),d0 //ccr holen
move d0,ccr //setzen
mvs.\3 \2,d0
mvs.\3 \1,d1
addx.l d0,d1
set_cc0
move.\3 d1,\1
ii_end
.endm;
//--------------------------------------------------------------------
// // addx -(ay),-(ax)
//--------------------------------------------------------------------
adddax:.macro
#ifdef halten_add
halt
#endif
move.b sr_off+1(a7),d0 //ccr holen
move d0,ccr //setzen
move.l \1,a1
.ifc \3,l
move.l -(a1),d0
.else
mvs.\3 -(a1),d0
.endif
move.l \2,a1
.ifc \3,l
move.l -(a1),d0
.else
mvs.\3 -(a1),d1
.endif
addx.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------

441
sources/ii_and.h
View File

@@ -1,441 +0,0 @@
//--------------------------------------------------------------------
// and
//--------------------------------------------------------------------
/*****************************************************************************************/
//--------------------------------------------------------------------
// byt
//--------------------------------------------------------------------
//--------------------------------------------------------------------
// and.b #im,dx
//--------------------------------------------------------------------
andbir_macro:.macro
move.w (a0)+,d0
extb.l d0
mvs.b \2,d1
and.l d0,d1
set_cc0
move.b d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // and ea,dx
//--------------------------------------------------------------------
anddd:.macro
#ifdef halten_and
halt
#endif
mvs.\3 \1,d0
mvs.\3 \2,d1
and.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // and ea(l)->dy(w),dx z.B. f<>r USP
//--------------------------------------------------------------------
andddd:.macro
#ifdef halten_and
halt
#endif
move.l \1,a1
mvs.\3 a1,d0
mvs.\3 \2,d1
and.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // and (ea)->dy,dx
//--------------------------------------------------------------------
anddda:.macro
#ifdef halten_and
halt
#endif
move.l \1,a1
mvs.\3 (a1),d0
mvs.\3 \2,d1
and.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // and ea->ay,(ay)+,dx
//--------------------------------------------------------------------
andddai:.macro
#ifdef halten_and
halt
#endif
move.l \1,a1
mvs.\3 (a1)+,d0
move.l a1,\1
mvs.\3 \2,d1
and.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // and ea->ay,-(ay),dx
//--------------------------------------------------------------------
andddad:.macro
#ifdef halten_and
halt
#endif
move.l \1,a1
mvs.\3 -(a1),d0
move.l a1,\1
mvs.\3 \2,d1
and.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // and d16(ay),dx
//--------------------------------------------------------------------
andd16ad:.macro
#ifdef halten_and
halt
#endif
move.l \1,a1
mvs.w (a0)+,d0
add.l d0,a1
mvs.\3 (a1),d0
mvs.\3 \2,d1
and.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // and d8(ay,dy),dx
//--------------------------------------------------------------------
andd8ad:.macro
#ifdef halten_and
halt
#endif
move.l \1,a1
jsr ewf
.ifc \3,l
move.l (a1),d0
move.l \2,d1
.else
mvs.\3 (a1),d0
mvs.\3 \2,d1
.endif
and.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // and xxx.w,dx
//--------------------------------------------------------------------
andxwd:.macro
#ifdef halten_and
halt
#endif
move.w (a0)+,a1
mvs.\3 (a1),d0
mvs.\3 \2,d1
and.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // and xxx.l,dx
//--------------------------------------------------------------------
andxld:.macro
#ifdef halten_and
halt
#endif
move.l (a0)+,a1
mvs.\3 (a1),d0
mvs.\3 \2,d1
and.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // and d16(pc),dx
//--------------------------------------------------------------------
andd16pcd:.macro
#ifdef halten_and
halt
#endif
move.l a0,a1
mvs.w (a0)+,d0
add.l d0,a1
mvs.\3 (a1),d0
mvs.\3 \2,d1
and.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // and d8(pc,dy),dx
//--------------------------------------------------------------------
andd8pcd:.macro
#ifdef halten_and
halt
#endif
move.l a0,a1
jsr ewf
.ifc \3,l
move.l (a1),d0
move.l \2,d1
.else
mvs.\3 (a1),d0
mvs.\3 \2,d1
.endif
and.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// and dx,ea
//--------------------------------------------------------------------
//--------------------------------------------------------------------
// // and dx,(ea)->dy
//--------------------------------------------------------------------
andeda:.macro
#ifdef halten_and
halt
#endif
mvs.\3 \1,d0
move.l \2,a1
mvs.\3 (a1),d1
and.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------
// // and dx,ea->ay,(ay)+
//--------------------------------------------------------------------
andedai:.macro
#ifdef halten_and
halt
#endif
mvs.\3 \1,d0
move.l \2,a1
mvs.\3 (a1),d1
and.l d0,d1
set_cc0
move.\3 d1,(a1)+
move.l a1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // and dx,ea->ay,(ay)+
//--------------------------------------------------------------------
andedaid:.macro
#ifdef halten_and
halt
#endif
mvs.\3 \1,d0
mvs.\3 \2,d1
and.l d0,d1
set_cc0
move.\3 d1,\2+
ii_end
.endm;
//--------------------------------------------------------------------
// // and dx,ea->ay,-(ay)
//--------------------------------------------------------------------
andedad:.macro
#ifdef halten_and
halt
#endif
mvs.\3 \1,d0
move.l \2,a1
mvs.\3 -(a1),d1
move.l a1,\2
and.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------
// // and dx,ea->ay,-(ay)
//--------------------------------------------------------------------
andedadd:.macro
#ifdef halten_and
halt
#endif
mvs.\3 \1,d0
mvs.\3 -\2,d1
and.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // and dx,d16(ay)
//--------------------------------------------------------------------
ande16ad:.macro
#ifdef halten_and
halt
#endif
mvs.\3 \1,d0
move.l \2,a1
mvs.w (a0)+,d1
add.l d1,a1
mvs.\3 (a1),d1
and.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------
// // and.w dx,d8(ay,dy)
//--------------------------------------------------------------------
ande8ad:.macro
#ifdef halten_and
halt
#endif
move.l \2,a1
jsr ewf
.ifc \3,l
move.l (a1),d1
move.l \1,d0
.else
mvs.\3 (a1),d1
mvs.\3 \1,d0
.endif
and.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------
// // and dx,xxx.w
//--------------------------------------------------------------------
andxwe:.macro
#ifdef halten_and
halt
#endif
mvs.\3 \1,d0
move.w (a0)+,a1
mvs.\3 (a1),d1
and.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------
// // and dx,xxx.l
//--------------------------------------------------------------------
andxle:.macro
#ifdef halten_and
halt
#endif
mvs.\3 \1,d0
move.l (a0)+,a1
mvs.\3 (a1),d1
and.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------
// // anda.w ea,ax
//--------------------------------------------------------------------
andaw:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// and.w ea,usp
//--------------------------------------------------------------------
andawa7:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// // anda.w usp?,ax
//--------------------------------------------------------------------
andawu:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// // anda.w usp?,usp
//--------------------------------------------------------------------
andawua7:.macro
andawu \1,\2
.endm;
//--------------------------------------------------------------------
// // anda.w d16(ay),ax
//--------------------------------------------------------------------
andawd16a:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// // anda.w d8(ay,dy),ax
//--------------------------------------------------------------------
andawd8a:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// // anda.w xxx.w,ax
//--------------------------------------------------------------------
andawxwax:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// // anda.w xxx.l,ax
//--------------------------------------------------------------------
andawxlax:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// // anda.w d16(pc),ax
//--------------------------------------------------------------------
andawd16pcax:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// // anda.w d8(pc,dy),ax
//--------------------------------------------------------------------
andawd8pcax:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// // anda.w #im,ax
//--------------------------------------------------------------------
andawim:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// // anda.l d8(ay,dy),ax
//--------------------------------------------------------------------
andald8a:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// // anda.l d8(pc,dy),ax
//--------------------------------------------------------------------
andald8pcax:.macro
jmp ii_error
.endm;
//*****************************************************************************************
// spezial addx subx etc.
//--------------------------------------------------------------------
//--------------------------------------------------------------------
// // addx dy,dx
//--------------------------------------------------------------------
anddx:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// // addx -(ay),-(ax)
//--------------------------------------------------------------------
anddax:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------

117
sources/ii_dbcc.h
View File

@@ -1,117 +0,0 @@
//--------------------------------------------------------------------
// dbcc,trapcc
//--------------------------------------------------------------------
.text
ii_lset_dbcc:.macro
// dbra
ii_lset_opeau 51,c
ii_lset_opeau 52,c
ii_lset_opeau 53,c
ii_lset_opeau 54,c
ii_lset_opeau 55,c
ii_lset_opeau 56,c
ii_lset_opeau 57,c
ii_lset_opeau 58,c
ii_lset_opeau 59,c
ii_lset_opeau 5a,c
ii_lset_opeau 5b,c
ii_lset_opeau 5c,c
ii_lset_opeau 5d,c
ii_lset_opeau 5e,c
ii_lset_opeau 5f,c
.endm
ii_dbcc_func:.macro
ii_0x51c8:
dbra_macro d0_off+2(a7)
ii_0x51c9:
dbra_macro d1_off+2(a7)
ii_0x51ca:
dbra_macro d2
ii_0x51cb:
dbra_macro d3
ii_0x51cc:
dbra_macro d4
ii_0x51cd:
dbra_macro d5
ii_0x51ce:
dbra_macro d6
ii_0x51cf:
dbra_macro d7
//---------------------------------------------------------------------------------------------
// dbcc dx
//---------------------------------------------------------------------------------------------
ii_dbcc 2,hi
ii_dbcc 3,ls
ii_dbcc 4,cc
ii_dbcc 5,cs
ii_dbcc 6,ne
ii_dbcc 7,eq
ii_dbcc 8,vc
ii_dbcc 9,vs
ii_dbcc a,pl
ii_dbcc b,mi
ii_dbcc c,ge
ii_dbcc d,lt
ii_dbcc e,gt
ii_dbcc f,le
.endm
//---------------------------------------------------------------------------------------------
// dbra dx
//---------------------------------------------------------------------------------------------
dbra_macro:.macro
#ifdef halten_dbcc
halt
#endif
mvz.w \1,d1 // dx holen
subq.l #1,d1 // dx-1
bcc dbra\@ // bra if plus?
addq.l #2,a0 // offset <20>berspringen
move.w d1,\1 // dx sichern
ii_end
dbra\@:
move.w (a0),a1 // offset (wird auf long erweitert)
add.l a1,a0 // dazuadieren
move.w d1,\1 // dx sichern
ii_end
.endm
//---------------------------------------------------------------------------------------------
// dbcc dx
//---------------------------------------------------------------------------------------------
dbcc_macro:.macro
#ifdef halten_dbcc
halt
#endif
b\2 dbncc\@
mvz.w \1,d1 // dx holen
subq.l #1,d1 // dx-1
bcc dbcc\@ // bra if plus?
dbncc\@:
addq.l #2,a0 // offset <20>berspringen
move.w d1,\1 // dx sichern
ii_end
dbcc\@:
move.w (a0),a1 // offset (wird auf long erweitert)
add.l a1,a0 // dazuadieren
move.w d1,\1 // dx sichern
ii_end
.endm
//db
ii_dbcc:.macro
ii_0x5\1c8:
dbcc_macro d0_off+2(a7),\2
ii_0x5\1c9:
dbcc_macro d1_off+2(a7),\2
ii_0x5\1ca:
dbcc_macro d2,\2
ii_0x5\1cb:
dbcc_macro d3,\2
ii_0x5\1cc:
dbcc_macro d4,\2
ii_0x5\1cd:
dbcc_macro d5,\2
ii_0x5\1ce:
dbcc_macro d6,\2
ii_0x5\1cf:
dbcc_macro d7,\2
.endm

181
sources/ii_ewf.h
View File

@@ -1,181 +0,0 @@
//--------------------------------------------------------------------
// extension word format missing
//--------------------------------------------------------------------
.text
ii_ewf_lset:.macro
// pea
ii_lset_opeag 48,7
ii_lset 0x487b
// jmp
ii_lset_opeag 4e,f
ii_lset 0x4efb
// jsr
ii_lset_opeag 4e,b
ii_lset 0x4ebb
// tas
ii_lset_opeag 4a,f
ii_lset 0x4ebb
// tst.b
ii_lset_opeag 4a,3
ii_lset 0x4ebb
// tst.w
ii_lset_opeag 4a,7
ii_lset 0x4ebb
// tst.l
ii_lset_opeag 4a,b
ii_lset 0x4ebb
// clr.b
ii_lset_opeag 42,3
ii_lset 0x423b
// clr.w
ii_lset_opeag 42,7
ii_lset 0x423b
// clr.l
ii_lset_opeag 42,b
ii_lset 0x423b
.endm
//---------------------------------------------------------------------------------------------
ii_ewf_func:.macro
ewf_func_macro pea,487
ewf_func_macro jmp,4ef
ewf_func_macro jsr,4eb
ewf_func_macro tas,4af
ewf_func_macro tstb,4a3
ewf_func_macro tstw,4a7
ewf_func_macro tstl,4ab
ewf_func_macro clrb,423
ewf_func_macro clrw,427
ewf_func_macro clrl,42b
.endm
//---------------------------------------------------------------------------------------------
pea_macro:.macro
jsr ewf
move.l (a1),d0
move.l usp,a1
move.l d0,-(a1)
move.l a1,usp
ii_end
.endm
jmp_macro:.macro
jsr ewf
move.l a1,a0
ii_end
.endm
jsr_macro:.macro
jsr ewf
move.l a1,d0
move.l usp,a1
move.l a0,-(a1)
move.l a1,usp
move.l d0,a0
ii_end
.endm
tas_macro:.macro
jsr ewf
tas (a1)
set_cc0
ii_end
.endm
tstb_macro:.macro
jsr ewf
tst.b (a1)
set_cc0
ii_end
.endm
tstw_macro:.macro
jsr ewf
tst.w (a1)
set_cc0
ii_end
.endm
tstl_macro:.macro
jsr ewf
tst.l (a1)
set_cc0
ii_end
.endm
clrb_macro:.macro
jsr ewf
clr.b (a1)
set_cc0
ii_end
.endm
clrw_macro:.macro
jsr ewf
clr.w (a1)
set_cc0
ii_end
.endm
clrl_macro:.macro
jsr ewf
clr.l (a1)
set_cc0
ii_end
.endm
//--------------------------------------------------------------------
ewf_func_macro:.macro //1=art 2=code
ii_0x\20:
#ifdef halten_ewf
halt
#endif
move.l a0_off(a7),a1
\1_macro
ii_0x\21:
#ifdef halten_ewf
halt
#endif
move.l a1_off(a7),a1
\1_macro
ii_0x\22:
#ifdef halten_ewf
halt
#endif
move.l a2,a1
\1_macro
ii_0x\23:
#ifdef halten_ewf
halt
#endif
move.l a3,a1
\1_macro
ii_0x\24:
#ifdef halten_ewf
halt
#endif
move.l a4,a1
\1_macro
ii_0x\25:
#ifdef halten_ewf
halt
#endif
move.l a5,a1
\1_macro
ii_0x\26:
#ifdef halten_ewf
halt
#endif
move.l a6,a1
\1_macro
ii_0x\27:
#ifdef halten_ewf
halt
#endif
move.l usp,a1
\1_macro
ii_0x\2b:
#ifdef halten_ewf
halt
#endif
move.l a0,a1
\1_macro
.endm

120
sources/ii_exg.h
View File

@@ -1,120 +0,0 @@
//--------------------------------------------------------------------
// exg
//--------------------------------------------------------------------
.text
ii_exg_lset:.macro
/* ii_lset_dxu c,40 //dx,d0
ii_lset_dxu c,41 //dx,d1
ii_lset_dxu c,42 //dx,d2
ii_lset_dxu c,43 //dx,d3
ii_lset_dxu c,44 //dx,d4
ii_lset_dxu c,45 //dx,d5
ii_lset_dxu c,46 //dx,d6
ii_lset_dxu c,47 //dx,d7
ii_lset_dxu c,48 //ax,a0
ii_lset_dxu c,49 //ax,a1
ii_lset_dxu c,4a //ax,a2
ii_lset_dxu c,4b //ax,a3
ii_lset_dxu c,4c //ax,a4
ii_lset_dxu c,4d //ax,a5
ii_lset_dxu c,4e //ax,a6
ii_lset_dxu c,4f //ax,a7 */ -->setting by "and"
ii_lset_dxu c,88 //dx,a0
ii_lset_dxu c,89 //dx,a1
ii_lset_dxu c,8a //dx,a2
ii_lset_dxu c,8b //dx,a3
ii_lset_dxu c,8c //dx,a4
ii_lset_dxu c,8d //dx,a5
ii_lset_dxu c,8e //dx,a6
ii_lset_dxu c,8f //dx,a7
.endm
//---------------------------------------------------------------------------------------------
ii_exg_func:.macro
// exg dx,dy
ii_exg_dx_dx 14,d0_off(a7)
ii_exg_dx_dx 34,d1_off(a7)
ii_exg_dx_dx 54,d2
ii_exg_dx_dx 74,d3
ii_exg_dx_dx 94,d4
ii_exg_dx_dx b4,d5
ii_exg_dx_dx d4,d6
ii_exg_dx_dx f4,d7
// exg ax,ay
ii_exg_to_ax 14,a0_off(a7)
ii_exg_to_ax 34,a1_off(a7)
ii_exg_to_ax 54,a2
ii_exg_to_ax 74,a3
ii_exg_to_ax 94,a4
ii_exg_to_ax b4,a5
ii_exg_to_ax d4,a6
ii_exg_to_ax f4,usp
// exg dx,ay
ii_exg_to_ax 18,d0_off(a7)
ii_exg_to_ax 38,d1_off(a7)
ii_exg_to_ax 58,d2
ii_exg_to_ax 78,d3
ii_exg_to_ax 98,d4
ii_exg_to_ax b8,d5
ii_exg_to_ax d8,d6
ii_exg_to_ax f8,d7
.endm
//---------------------------------------------------------------------------------------------
exg_macro:.macro
#ifdef halten_exg
halt
#endif
move.l \1,a1
.ifc \2,usp
move.l a1,d0
move.l \2,a1
move.l a1,\1
move.l d0,a1
.else
.ifc \1,usp
move.l a1,d0
move.l \2,a1
move.l a1,\1
move.l d0,a1
.else
move.l \2,\1
.endif
.endif
move.l a1,\2
ii_end
.endm
ii_exg_dx_dx:.macro
ii_0xc\10:
exg_macro \2,d0_off(a7)
ii_0xc\11:
exg_macro \2,d1_off(a7)
ii_0xc\12:
exg_macro \2,d2
ii_0xc\13:
exg_macro \2,d3
ii_0xc\14:
exg_macro \2,d4
ii_0xc\15:
exg_macro \2,d5
ii_0xc\16:
exg_macro \2,d6
ii_0xc\17:
exg_macro \2,d7
.endm
ii_exg_to_ax:.macro
ii_0xc\18:
exg_macro \2,a0_off(a7)
ii_0xc\19:
exg_macro \2,a1_off(a7)
ii_0xc\1a:
exg_macro \2,a2
ii_0xc\1b:
exg_macro \2,a3
ii_0xc\1c:
exg_macro \2,a4
ii_0xc\1d:
exg_macro \2,a5
ii_0xc\1e:
exg_macro \2,a6
ii_0xc\1f:
exg_macro \2,usp
.endm

945
sources/ii_func.h
View File

@@ -1,945 +0,0 @@
//--------------------------------------------------------------------
// functionen macros
//--------------------------------------------------------------------
ii_lset_func:.macro
/******************************************************/
// byt
/******************************************************/
// func.b dy,dx
ii_lset_dx \1,00 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c
ii_lset_dx \1,01
ii_lset_dx \1,02
ii_lset_dx \1,03
ii_lset_dx \1,04
ii_lset_dx \1,05
ii_lset_dx \1,06
ii_lset_dx \1,07
// func.b ax,dx
ii_lset_dxu \1,08
ii_lset_dxu \1,09
ii_lset_dxu \1,0a
ii_lset_dxu \1,0b
ii_lset_dxu \1,0c
ii_lset_dxu \1,0d
ii_lset_dxu \1,0e
ii_lset_dxu \1,0f
// func.b (ax),dx
ii_lset_dx \1,10
ii_lset_dx \1,11
ii_lset_dx \1,12
ii_lset_dx \1,13
ii_lset_dx \1,14
ii_lset_dx \1,15
ii_lset_dx \1,16
ii_lset_dx \1,17
// func.b (ax)+,dx
ii_lset_dx \1,18
ii_lset_dx \1,19
ii_lset_dx \1,1a
ii_lset_dx \1,1b
ii_lset_dx \1,1c
ii_lset_dx \1,1d
ii_lset_dx \1,1e
ii_lset_dx \1,1f
// func.b -(ax),dx
ii_lset_dx \1,20
ii_lset_dx \1,21
ii_lset_dx \1,22
ii_lset_dx \1,23
ii_lset_dx \1,24
ii_lset_dx \1,25
ii_lset_dx \1,26
ii_lset_dx \1,27
// func.b d16(ax),dx
ii_lset_dx \1,28
ii_lset_dx \1,29
ii_lset_dx \1,2a
ii_lset_dx \1,2b
ii_lset_dx \1,2c
ii_lset_dx \1,2d
ii_lset_dx \1,2e
ii_lset_dx \1,2f
// func.b dd8(ax,dy),dx
ii_lset_dx \1,30
ii_lset_dx \1,31
ii_lset_dx \1,32
ii_lset_dx \1,33
ii_lset_dx \1,34
ii_lset_dx \1,35
ii_lset_dx \1,36
ii_lset_dx \1,37
// func.b xxx.w,dx
ii_lset_dx \1,38 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c
// func.b xxx.l,dx
ii_lset_dx \1,39 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c
// func.b d16(pc),dx
ii_lset_dxg \1,7a // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c
// func.b d8(pc,dy),dx
ii_lset_dxg \1,3b // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c
// func.b #im,dx
ii_lset_dxg \1,3c // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c
/******************************************************/
// word
/******************************************************/
// func.w dy,dx
ii_lset_dx \1,40 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c
ii_lset_dx \1,41
ii_lset_dx \1,42
ii_lset_dx \1,43
ii_lset_dx \1,44
ii_lset_dx \1,45
ii_lset_dx \1,46
ii_lset_dx \1,47
// func.w ax,dx
ii_lset_dx \1,48
ii_lset_dx \1,49
ii_lset_dx \1,4a
ii_lset_dx \1,4b
ii_lset_dx \1,4c
ii_lset_dx \1,4d
ii_lset_dx \1,4e
ii_lset_dx \1,4f
// func.w (ax),dx
ii_lset_dx \1,50
ii_lset_dx \1,51
ii_lset_dx \1,52
ii_lset_dx \1,53
ii_lset_dx \1,54
ii_lset_dx \1,55
ii_lset_dx \1,56
ii_lset_dx \1,57
// func.w (ax)+,dx
ii_lset_dx \1,58
ii_lset_dx \1,59
ii_lset_dx \1,5a
ii_lset_dx \1,5b
ii_lset_dx \1,5c
ii_lset_dx \1,5d
ii_lset_dx \1,5e
ii_lset_dx \1,5f
// func.w -(ax),dx
ii_lset_dx \1,60
ii_lset_dx \1,61
ii_lset_dx \1,62
ii_lset_dx \1,63
ii_lset_dx \1,64
ii_lset_dx \1,65
ii_lset_dx \1,66
ii_lset_dx \1,67
// func.w d16(ax),dx
ii_lset_dx \1,68
ii_lset_dx \1,69
ii_lset_dx \1,6a
ii_lset_dx \1,6b
ii_lset_dx \1,6c
ii_lset_dx \1,6d
ii_lset_dx \1,6e
ii_lset_dx \1,6f
// func.w d8(ax,dy),dx
ii_lset_dx \1,70
ii_lset_dx \1,71
ii_lset_dx \1,72
ii_lset_dx \1,73
ii_lset_dx \1,74
ii_lset_dx \1,75
ii_lset_dx \1,76
ii_lset_dx \1,77
// func.w xxx.w,dx
ii_lset_dx \1,78 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c
// func.w xxx.l,dx
ii_lset_dx \1,79 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c
// func.w d16(pc),dx
ii_lset_dxg \1,7a // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c
// func.w d8(pc,dy),dx
ii_lset_dxg \1,7b // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c
// func.w #im,dx
ii_lset_dxg \1,7c // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c
/******************************************************/
// long
/******************************************************/
// func.l ax,dx -> -(ay),-(ax)
ii_lset_dxu \1,c8
ii_lset_dxu \1,c9
ii_lset_dxu \1,ca
ii_lset_dxu \1,cb
ii_lset_dxu \1,cc
ii_lset_dxu \1,cd
ii_lset_dxu \1,ce
ii_lset_dxu \1,cf
// func.w d8(ax,dy),dx
ii_lset_dx \1,b0
ii_lset_dx \1,b1
ii_lset_dx \1,b2
ii_lset_dx \1,b3
ii_lset_dx \1,b4
ii_lset_dx \1,b5
ii_lset_dx \1,b6
ii_lset_dx \1,b7
// func.l d8(pc,dy),dx
ii_lset_dxg \1,bb // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c
/******************************************************/
// adress register
/******************************************************/
//func.w dy,ax
ii_lset_dxg \1,c0
ii_lset_dxg \1,c1
ii_lset_dxg \1,c2
ii_lset_dxg \1,c3
ii_lset_dxg \1,c4
ii_lset_dxg \1,c5
ii_lset_dxg \1,c6
ii_lset_dxg \1,c7
//func.w ay,ax
ii_lset_dxg \1,c8
ii_lset_dxg \1,c9
ii_lset_dxg \1,ca
ii_lset_dxg \1,cb
ii_lset_dxg \1,cc
ii_lset_dxg \1,cd
ii_lset_dxg \1,ce
ii_lset_dxg \1,cf
//func.w (ay),ax
ii_lset_dxg \1,d0
ii_lset_dxg \1,d1
ii_lset_dxg \1,d2
ii_lset_dxg \1,d3
ii_lset_dxg \1,d4
ii_lset_dxg \1,d5
ii_lset_dxg \1,d6
ii_lset_dxg \1,d7
//func.w (ay)+,ax
ii_lset_dxg \1,d8
ii_lset_dxg \1,d9
ii_lset_dxg \1,da
ii_lset_dxg \1,db
ii_lset_dxg \1,dc
ii_lset_dxg \1,dd
ii_lset_dxg \1,de
ii_lset_dxg \1,df
//func.w -(ay),ax
ii_lset_dxg \1,e0
ii_lset_dxg \1,e1
ii_lset_dxg \1,e2
ii_lset_dxg \1,e3
ii_lset_dxg \1,e4
ii_lset_dxg \1,e5
ii_lset_dxg \1,e6
ii_lset_dxg \1,e7
//func.w d16(ay),ax
ii_lset_dxg \1,e8
ii_lset_dxg \1,e9
ii_lset_dxg \1,ea
ii_lset_dxg \1,eb
ii_lset_dxg \1,ec
ii_lset_dxg \1,ed
ii_lset_dxg \1,ee
ii_lset_dxg \1,ef
//func.w d8(ay,dy),ax
ii_lset_dxg \1,f0
ii_lset_dxg \1,f1
ii_lset_dxg \1,f2
ii_lset_dxg \1,f3
ii_lset_dxg \1,f4
ii_lset_dxg \1,f5
ii_lset_dxg \1,f6
ii_lset_dxg \1,f7
// func.w xxx.w,ax
ii_lset_dxg \1,f8
// func.w xxx.l,ax
ii_lset_dxg \1,f9
// func.w d16(pc),ax
ii_lset_dxg \1,fa
// func.w d8(pc,dy),ax
ii_lset_dxg \1,fb
// func.w #im,ax
ii_lset_dxg \1,fc
//--------------------------------------------------------------------
// ende
.endm;
/*****************************************************************************************/
ii_func:.macro
//--------------------------------------------------------------------
// byt
//--------------------------------------------------------------------
///--------------------------------------------------------------------
// func.b ds,dx
//--------------------------------------------------------------------
funcbeadx \1,00,\2dd,d0_off+3(a7)
funcbeadx \1,01,\2dd,d1_off+3(a7)
funcbeadx \1,02,\2dd,d2
funcbeadx \1,03,\2dd,d3
funcbeadx \1,04,\2dd,d4
funcbeadx \1,05,\2dd,d5
funcbeadx \1,06,\2dd,d6
funcbeadx \1,07,\2dd,d7
//--------------------------------------------------------------------
// func.b (ax),dx
//--------------------------------------------------------------------
funcbeadx \1,10,\2dda,a0_off(a7)
funcbeadx \1,11,\2dda,a1_off(a7)
funcbeadx \1,12,\2dd,(a2)
funcbeadx \1,13,\2dd,(a3)
funcbeadx \1,14,\2dd,(a4)
funcbeadx \1,15,\2dd,(a5)
funcbeadx \1,16,\2dd,(a6)
funcbeadx \1,17,\2dda,usp
//--------------------------------------------------------------------
// func.b (ax)+,dx
//--------------------------------------------------------------------
funcbeadx \1,18,\2ddai,a0_off(a7)
funcbeadx \1,19,\2ddai,a1_off(a7)
funcbeadx \1,1a,\2dd,(a2)+
funcbeadx \1,1b,\2dd,(a3)+
funcbeadx \1,1c,\2dd,(a4)+
funcbeadx \1,1d,\2dd,(a5)+
funcbeadx \1,1e,\2dd,(a6)+
funcbeadx \1,1f,\2ddai,usp
//--------------------------------------------------------------------
// func.b -(ax),dx
//--------------------------------------------------------------------
funcbeadx \1,20,\2ddad,a0_off(a7)
funcbeadx \1,21,\2ddad,a1_off(a7)
funcbeadx \1,22,\2dd,-(a2)
funcbeadx \1,23,\2dd,-(a3)
funcbeadx \1,24,\2dd,-(a4)
funcbeadx \1,25,\2dd,-(a5)
funcbeadx \1,26,\2dd,-(a6)
funcbeadx \1,27,\2ddad,usp
//--------------------------------------------------------------------
// func.b d16(ax),dx
//--------------------------------------------------------------------
funcbeadx \1,28,\2d16ad,a0_off(a7)
funcbeadx \1,29,\2d16ad,a1_off(a7)
funcbeadx \1,2a,\2d16ad,a2
funcbeadx \1,2b,\2d16ad,a3
funcbeadx \1,2c,\2d16ad,a4
funcbeadx \1,2d,\2d16ad,a5
funcbeadx \1,2e,\2d16ad,a6
funcbeadx \1,2f,\2d16ad,usp
//--------------------------------------------------------------------
// func.b d8(ax,dy),dx
//--------------------------------------------------------------------
funcbeadx \1,30,\2d8ad,a0_off(a7)
funcbeadx \1,31,\2d8ad,a1_off(a7)
funcbeadx \1,32,\2d8ad,a2
funcbeadx \1,33,\2d8ad,a3
funcbeadx \1,34,\2d8ad,a4
funcbeadx \1,35,\2d8ad,a5
funcbeadx \1,36,\2d8ad,a6
funcbeadx \1,37,\2d8ad,usp
//--------------------------------------------------------------------
// func.b xxx.w,dx
//--------------------------------------------------------------------
funcbeadx \1,38,\2xwd,(a0)+
//--------------------------------------------------------------------
// func.b xxx.w,dx
//--------------------------------------------------------------------
funcbeadx \1,39,\2xld,(a0)+
//--------------------------------------------------------------------
// func.b d16(pc),dx
//--------------------------------------------------------------------
funcbeadx \1,3a,\2d16pcd,(a0)+
//--------------------------------------------------------------------
// func.b d8(pc,dy),dx
//--------------------------------------------------------------------
funcbeadx \1,3b,\2d8pcd,(a0)+ (a0 wird nicht verwendet)
//--------------------------------------------------------------------
// func.b #im,dx
//--------------------------------------------------------------------
funcbeadx \1,3c,\2bir_macro,(a0)+
//--------------------------------------------------------------------
// func.b dy,ea
//--------------------------------------------------------------------
///--------------------------------------------------------------------
// func.b dx,dd -> addx subx etc. src und dest vertauscht!
//--------------------------------------------------------------------
funcbdxea \1,00,\2dx,d0_off+3(a7)
funcbdxea \1,01,\2dx,d1_off+3(a7)
funcbdxea \1,02,\2dx,d2
funcbdxea \1,03,\2dx,d3
funcbdxea \1,04,\2dx,d4
funcbdxea \1,05,\2dx,d5
funcbdxea \1,06,\2dx,d6
funcbdxea \1,07,\2dx,d7
//--------------------------------------------------------------------
// func.b -(ax),-(ay) addx subx etc. src und dest vertauscht!
//--------------------------------------------------------------------
funcaxay \1,08,\2dax,a0_off(a7),b
funcaxay \1,09,\2dax,a1_off(a7).b
funcaxay \1,0a,\2dax,a2,b
funcaxay \1,0b,\2dax,a3,b
funcaxay \1,0c,\2dax,a4,b
funcaxay \1,0d,\2dax,a5,b
funcaxay \1,0e,\2dax,a6,b
funcaxay \1,0f,\2dax,usp,b
//--------------------------------------------------------------------
// func.b dy,(ax)
//--------------------------------------------------------------------
funcbdxea \1,10,\2eda,a0_off(a7)
funcbdxea \1,11,\2eda,a1_off(a7)
funcbdxea \1,12,\2dd,(a2)
funcbdxea \1,13,\2dd,(a3)
funcbdxea \1,14,\2dd,(a4)
funcbdxea \1,15,\2dd,(a5)
funcbdxea \1,16,\2dd,(a6)
funcbdxea \1,17,\2eda,usp
//--------------------------------------------------------------------
// func.b dy,(ax)+
//--------------------------------------------------------------------
funcbdxea \1,18,\2edai,a0_off(a7)
funcbdxea \1,19,\2edai,a1_off(a7)
funcbdxea \1,1a,\2edaid,(a2)
funcbdxea \1,1b,\2edaid,(a3)
funcbdxea \1,1c,\2edaid,(a4)
funcbdxea \1,1d,\2edaid,(a5)
funcbdxea \1,1e,\2edaid,(a6)
funcbdxea \1,1f,\2edai,usp
//--------------------------------------------------------------------
// func.b dy,-(ax)
//--------------------------------------------------------------------
funcbdxea \1,20,\2edad,a0_off(a7)
funcbdxea \1,21,\2edad,a1_off(a7)
funcbdxea \1,22,\2edadd,(a2)
funcbdxea \1,23,\2edadd,(a3)
funcbdxea \1,24,\2edadd,(a4)
funcbdxea \1,25,\2edadd,(a5)
funcbdxea \1,26,\2edadd,(a6)
funcbdxea \1,27,\2edad,usp
//--------------------------------------------------------------------
// func.b dy,d16(ax)
//--------------------------------------------------------------------
funcbdxea \1,28,\2e16ad,a0_off(a7)
funcbdxea \1,29,\2e16ad,a1_off(a7)
funcbdxea \1,2a,\2e16ad,a2
funcbdxea \1,2b,\2e16ad,a3
funcbdxea \1,2c,\2e16ad,a4
funcbdxea \1,2d,\2e16ad,a5
funcbdxea \1,2e,\2e16ad,a6
funcbdxea \1,2f,\2e16ad,usp
//--------------------------------------------------------------------
// func.b dy,d8(ax,dy)
//--------------------------------------------------------------------
funcbdxea \1,30,\2e8ad,a0_off(a7)
funcbdxea \1,31,\2e8ad,a1_off(a7)
funcbdxea \1,32,\2e8ad,a2
funcbdxea \1,33,\2e8ad,a3
funcbdxea \1,34,\2e8ad,a4
funcbdxea \1,35,\2e8ad,a5
funcbdxea \1,36,\2e8ad,a6
funcbdxea \1,37,\2e8ad,usp
//--------------------------------------------------------------------
// func.w dy,xxx.w
//--------------------------------------------------------------------
funcwdxea \1,38,\2xwe,(a0)+
//--------------------------------------------------------------------
// func.w dy,xxx.w
//--------------------------------------------------------------------
funcwdxea \1,39,\2xld,(a0)+
/*****************************************************************************************/
// word
/*****************************************************************************************/
// func.w ds,dx
//--------------------------------------------------------------------
funcweadx \1,40,\2dd,d0_off+2(a7)
funcweadx \1,41,\2dd,d1_off+2(a7)
funcweadx \1,42,\2dd,d2
funcweadx \1,43,\2dd,d3
funcweadx \1,44,\2dd,d4
funcweadx \1,45,\2dd,d5
funcweadx \1,46,\2dd,d6
funcweadx \1,47,\2dd,d7
//--------------------------------------------------------------------
// func.w ax,dx
//--------------------------------------------------------------------
funcweadx \1,48,\2dd,a0_off+2(a7)
funcweadx \1,49,\2dd,a1_off+2(a7)
funcweadx \1,4a,\2dd,a2
funcweadx \1,4b,\2dd,a3
funcweadx \1,4c,\2dd,a4
funcweadx \1,4d,\2dd,a5
funcweadx \1,4e,\2dd,a6
funcweadx \1,4f,\2ddd,usp
//--------------------------------------------------------------------
// func.w (ax),dx
//--------------------------------------------------------------------
funcweadx \1,50,\2dda,a0_off(a7)
funcweadx \1,51,\2dda,a1_off(a7)
funcweadx \1,52,\2dd,(a2)
funcweadx \1,53,\2dd,(a3)
funcweadx \1,54,\2dd,(a4)
funcweadx \1,55,\2dd,(a5)
funcweadx \1,56,\2dd,(a6)
funcweadx \1,57,\2dda,usp
//--------------------------------------------------------------------
// func.w (ax)+,dx
//--------------------------------------------------------------------
funcweadx \1,58,\2ddai,a0_off(a7)
funcweadx \1,59,\2ddai,a1_off(a7)
funcweadx \1,5a,\2dd,(a2)+
funcweadx \1,5b,\2dd,(a3)+
funcweadx \1,5c,\2dd,(a4)+
funcweadx \1,5d,\2dd,(a5)+
funcweadx \1,5e,\2dd,(a6)+
funcweadx \1,5f,\2ddai,usp
//--------------------------------------------------------------------
// func.w -(ax),dx
//--------------------------------------------------------------------
funcweadx \1,60,\2ddad,a0_off(a7)
funcweadx \1,61,\2ddad,a1_off(a7)
funcweadx \1,62,\2dd,-(a2)
funcweadx \1,63,\2dd,-(a3)
funcweadx \1,64,\2dd,-(a4)
funcweadx \1,65,\2dd,-(a5)
funcweadx \1,66,\2dd,-(a6)
funcweadx \1,67,\2ddad,usp
//--------------------------------------------------------------------
// func.w d16(ax),dx
//--------------------------------------------------------------------
funcweadx \1,68,\2d16ad,a0_off(a7)
funcweadx \1,69,\2d16ad,a1_off(a7)
funcweadx \1,6a,\2d16ad,a2
funcweadx \1,6b,\2d16ad,a3
funcweadx \1,6c,\2d16ad,a4
funcweadx \1,6d,\2d16ad,a5
funcweadx \1,6e,\2d16ad,a6
funcweadx \1,6f,\2d16ad,usp
//--------------------------------------------------------------------
// func.w d8(ax,dy),dx
//--------------------------------------------------------------------
funcweadx \1,70,\2d8ad,a0_off(a7)
funcweadx \1,71,\2d8ad,a1_off(a7)
funcweadx \1,72,\2d8ad,a2
funcweadx \1,73,\2d8ad,a3
funcweadx \1,74,\2d8ad,a4
funcweadx \1,75,\2d8ad,a5
funcweadx \1,76,\2d8ad,a6
funcweadx \1,77,\2d8ad,usp
//--------------------------------------------------------------------
// func.w xxx.w,dx
//--------------------------------------------------------------------
funcweadx \1,78,\2xwd,(a0)+
//--------------------------------------------------------------------
// func.w xxx.w,dx
//--------------------------------------------------------------------
funcweadx \1,79,\2xld,(a0)+
//--------------------------------------------------------------------
// func.w d16(pc),dx
//--------------------------------------------------------------------
funcweadx \1,7a,\2d16pcd,(a0)+
//--------------------------------------------------------------------
// func.w d8(pc,dy),dx
//--------------------------------------------------------------------
funcweadx \1,7b,\2d8pcd,(a0)+ (a0 wird nicht verwendet)
//--------------------------------------------------------------------
// func.w #im,dx
//--------------------------------------------------------------------
funcweadx \1,7c,\2dd,(a0)+
//--------------------------------------------------------------------
// func.w dy,ea
//--------------------------------------------------------------------
///--------------------------------------------------------------------
// func.w dx,dd -> addx subx etc.
//--------------------------------------------------------------------
.ifnc \2,and //platz f<>r exg
funcwdxea \1,40,\2dx,d0_off+2(a7)
funcwdxea \1,41,\2dx,d1_off+2(a7)
funcwdxea \1,42,\2dx,d2
funcwdxea \1,43,\2dx,d3
funcwdxea \1,44,\2dx,d4
funcwdxea \1,45,\2dx,d5
funcwdxea \1,46,\2dx,d6
funcwdxea \1,47,\2dx,d7
//--------------------------------------------------------------------
// func.w -(ax),-(ay) -> addx,subx
//--------------------------------------------------------------------
funcaxay \1,48,\2dax,a0_off(a7),w
funcaxay \1,49,\2dax,a1_off(a7).w
funcaxay \1,4a,\2dax,a2,w
funcaxay \1,4b,\2dax,a3,w
funcaxay \1,4c,\2dax,a4,w
funcaxay \1,4d,\2dax,a5,w
funcaxay \1,4e,\2dax,a6,w
funcaxay \1,4f,\2dax,usp,w
.endif
//--------------------------------------------------------------------
// func.w dy,(ax)
//--------------------------------------------------------------------
funcwdxea \1,50,\2eda,a0_off(a7)
funcwdxea \1,51,\2eda,a1_off(a7)
funcwdxea \1,52,\2dd,(a2)
funcwdxea \1,53,\2dd,(a3)
funcwdxea \1,54,\2dd,(a4)
funcwdxea \1,55,\2dd,(a5)
funcwdxea \1,56,\2dd,(a6)
funcwdxea \1,57,\2eda,usp
//--------------------------------------------------------------------
// func.w dy,(ax)+
//--------------------------------------------------------------------
funcwdxea \1,58,\2edai,a0_off(a7)
funcwdxea \1,59,\2edai,a1_off(a7)
funcwdxea \1,5a,\2edaid,(a2)
funcwdxea \1,5b,\2edaid,(a3)
funcwdxea \1,5c,\2edaid,(a4)
funcwdxea \1,5d,\2edaid,(a5)
funcwdxea \1,5e,\2edaid,(a6)
funcwdxea \1,5f,\2edai,usp
//--------------------------------------------------------------------
// func.w dy,-(ax)
//--------------------------------------------------------------------
funcwdxea \1,60,\2edad,a0_off(a7)
funcwdxea \1,61,\2edad,a1_off(a7)
funcwdxea \1,62,\2edadd,(a2)
funcwdxea \1,63,\2edadd,(a3)
funcwdxea \1,64,\2edadd,(a4)
funcwdxea \1,65,\2edadd,(a5)
funcwdxea \1,66,\2edadd,(a6)
funcwdxea \1,67,\2edad,usp
//--------------------------------------------------------------------
// func.w dy,d16(ax)
//--------------------------------------------------------------------
funcwdxea \1,68,\2e16ad,a0_off(a7)
funcwdxea \1,69,\2e16ad,a1_off(a7)
funcwdxea \1,6a,\2e16ad,a2
funcwdxea \1,6b,\2e16ad,a3
funcwdxea \1,6c,\2e16ad,a4
funcwdxea \1,6d,\2e16ad,a5
funcwdxea \1,6e,\2e16ad,a6
funcwdxea \1,6f,\2e16ad,usp
//--------------------------------------------------------------------
// func.w dy,d8(ax,dy)
//--------------------------------------------------------------------
funcwdxea \1,70,\2e8ad,a0_off(a7)
funcwdxea \1,71,\2e8ad,a1_off(a7)
funcwdxea \1,72,\2e8ad,a2
funcwdxea \1,73,\2e8ad,a3
funcwdxea \1,74,\2e8ad,a4
funcwdxea \1,75,\2e8ad,a5
funcwdxea \1,76,\2e8ad,a6
funcwdxea \1,77,\2e8ad,usp
//--------------------------------------------------------------------
// func.w dy,xxx.w
//--------------------------------------------------------------------
funcwdxea \1,78,\2xwe,(a0)+
//--------------------------------------------------------------------
// func.w dy,xxx.w
//--------------------------------------------------------------------
funcwdxea \1,79,\2xld,(a0)+
/*****************************************************************************************/
// long
/*****************************************************************************************/
//--------------------------------------------------------------------
// func.l -(ax),-(ay)
//--------------------------------------------------------------------
funcaxay \1,c8,\2dax,a0_off(a7),l
funcaxay \1,c9,\2dax,a1_off(a7).l
funcaxay \1,ca,\2dax,a2,l
funcaxay \1,cb,\2dax,a3,l
funcaxay \1,cc,\2dax,a4,l
funcaxay \1,cd,\2dax,a5,l
funcaxay \1,ce,\2dax,a6,l
funcaxay \1,cf,\2dax,usp,l
//--------------------------------------------------------------------
// func.l d8(ax,dy),dx
//--------------------------------------------------------------------
funcleadx \1,b0,\2d8ad,a0_off(a7)
funcleadx \1,b1,\2d8ad,a1_off(a7)
funcleadx \1,b2,\2d8ad,a2
funcleadx \1,b3,\2d8ad,a3
funcleadx \1,b4,\2d8ad,a4
funcleadx \1,b5,\2d8ad,a5
funcleadx \1,b6,\2d8ad,a6
funcleadx \1,b7,\2d8ad,usp
//--------------------------------------------------------------------
// func.l d8(pc,dy),dx
//--------------------------------------------------------------------
funcleadx \1,bb,\2d8pcd,(a0)+ (a0 wird nicht verwendet)
//--------------------------------------------------------------------
// func.l dy,d8(ax,dy)
//--------------------------------------------------------------------
funcldxea \1,b0,\2e8ad,a0_off(a7)
funcldxea \1,b1,\2e8ad,a1_off(a7)
funcldxea \1,b2,\2e8ad,a2
funcldxea \1,b3,\2e8ad,a3
funcldxea \1,b4,\2e8ad,a4
funcldxea \1,b5,\2e8ad,a5
funcldxea \1,b6,\2e8ad,a6
funcldxea \1,b7,\2e8ad,usp
/******************************************************/
// adress register
/******************************************************/
//--------------------------------------------------------------------
// func.w ea,ax
//--------------------------------------------------------------------
//--------------------------------------------------------------------
// func.w dx,ax
//--------------------------------------------------------------------
funcweaax \1,c0,\2aw,d0
funcweaax \1,c1,\2aw,d1
funcweaax \1,c2,\2aw,d2
funcweaax \1,c3,\2aw,d3
funcweaax \1,c4,\2aw,d4
funcweaax \1,c5,\2aw,d5
funcweaax \1,c6,\2aw,d6
funcweaax \1,c7,\2aw,d7
//--------------------------------------------------------------------
// func.w ay,ax
//--------------------------------------------------------------------
funcweaax \1,c8,\2aw,a0
funcweaax \1,c9,\2aw,a1
funcweaax \1,ca,\2aw,a2
funcweaax \1,cb,\2aw,a3
funcweaax \1,cc,\2aw,a4
funcweaax \1,cd,\2aw,a5
funcweaax \1,ce,\2aw,a6
funcweaax \1,cf,\2awu,a7
//--------------------------------------------------------------------
// func.w (ay),ax
//--------------------------------------------------------------------
funcweaax \1,d0,\2aw,(a0)
funcweaax \1,d1,\2aw,(a1)
funcweaax \1,d2,\2aw,(a2)
funcweaax \1,d3,\2aw,(a3)
funcweaax \1,d4,\2aw,(a4)
funcweaax \1,d5,\2aw,(a5)
funcweaax \1,d6,\2aw,(a6)
funcweaax \1,d7,\2awu,(a7)
//--------------------------------------------------------------------
// func.w (ay)+,ax
//--------------------------------------------------------------------
funcweaax \1,d8,\2aw,(a0)+
funcweaax \1,d9,\2aw,(a1)+
funcweaax \1,da,\2aw,(a2)+
funcweaax \1,db,\2aw,(a3)+
funcweaax \1,dc,\2aw,(a4)+
funcweaax \1,dd,\2aw,(a5)+
funcweaax \1,de,\2aw,(a6)+
funcweaax \1,df,\2awu,(a7)+
//--------------------------------------------------------------------
// func.w -(ay),ax
//--------------------------------------------------------------------
funcweaax \1,e0,\2aw,-(a0)
funcweaax \1,e1,\2aw,-(a1)
funcweaax \1,e2,\2aw,-(a2)
funcweaax \1,e3,\2aw,-(a3)
funcweaax \1,e4,\2aw,-(a4)
funcweaax \1,e5,\2aw,-(a5)
funcweaax \1,e6,\2aw,-(a6)
funcweaax \1,e7,\2awu,-(a7)
//--------------------------------------------------------------------
// func.w d16(ay),ax
//--------------------------------------------------------------------
funcweaaxn \1,e8,\2awd16a,a0_off(a7)
funcweaaxn \1,e9,\2awd16a,a1_off(a7)
funcweaaxn \1,ea,\2awd16a,a2
funcweaaxn \1,eb,\2awd16a,a3
funcweaaxn \1,ec,\2awd16a,a4
funcweaaxn \1,ed,\2awd16a,a5
funcweaaxn \1,ee,\2awd16a,a6
funcweaaxn \1,ef,\2awd16a,usp
//--------------------------------------------------------------------
// func.w d8(ay,dy),ax
//--------------------------------------------------------------------
funcweaaxn \1,f0,\2awd8a,a0_off(a7)
funcweaaxn \1,f1,\2awd8a,a1_off(a7)
funcweaaxn \1,f2,\2awd8a,a2
funcweaaxn \1,f3,\2awd8a,a3
funcweaaxn \1,f4,\2awd8a,a4
funcweaaxn \1,f5,\2awd8a,a5
funcweaaxn \1,f6,\2awd8a,a6
funcweaaxn \1,f7,\2awd8a,usp
//--------------------------------------------------------------------
// func.w xxx.w,ax
//--------------------------------------------------------------------
funcweaaxn \1,f8,\2awxwax,(a0)+
//--------------------------------------------------------------------
// func.w xxxlw,ax
//--------------------------------------------------------------------
funcweaaxn \1,f9,\2awxlax,(a0)+
//--------------------------------------------------------------------
// func.w d16(pc),ax
//--------------------------------------------------------------------
funcweaaxn \1,fa,\2awd16pcax,(a0)+
//--------------------------------------------------------------------
// func.w d8(pc,dy),ax
//--------------------------------------------------------------------
funcweaaxn \1,fb,\2awd8pcax,(a0)+ //(a0 wird nicht verwendet)
//--------------------------------------------------------------------
// func.w #im,ax
//--------------------------------------------------------------------
funcweaaxn \1,fc,\2awim,(a0)+
//--------------------------------------------------------------------
// ende
.endm;
//--------------------------------------------------------------------
// byt
funcbeadx:.macro // function byt: im,dx
ii_0x\10\2:
\3 \4,d0_off+3(a7),b
ii_0x\12\2:
\3 \4,d1_off+3(a7),b
ii_0x\14\2:
\3 \4,d2,b
ii_0x\16\2:
\3 \4,d3,b
ii_0x\18\2:
\3 \4,d4,b
ii_0x\1a\2:
\3 \4,d5,b
ii_0x\1c\2:
\3 \4,d6,b
ii_0x\1e\2:
\3 \4,d7,b
.endm;
funcbdxea:.macro // ea(\4) function(\3) dx -> ea
ii_0x\11\2:
\3 d0_off+3(a7),\4,b
ii_0x\13\2:
\3 d1_off+3(a7),\4,b
ii_0x\15\2:
\3 d2,\4,b
ii_0x\17\2:
\3 d3,\4,b
ii_0x\19\2:
\3 d4,\4,b
ii_0x\1b\2:
\3 d5,\4,b
ii_0x\1d\2:
\3 d6,\4,b
ii_0x\1f\2:
\3 d7,\4,b
.endm;
//--------------------------------------------------------------------
// word
funcweadx:.macro // dx function(\3) ea(\4) -> dx
ii_0x\10\2:
\3 \4,d0_off+2(a7),w
ii_0x\12\2:
\3 \4,d1_off+2(a7),w
ii_0x\14\2:
\3 \4,d2,w
ii_0x\16\2:
\3 \4,d3,w
ii_0x\18\2:
\3 \4,d4,w
ii_0x\1a\2:
\3 \4,d5,w
ii_0x\1c\2:
\3 \4,d6,w
ii_0x\1e\2:
\3 \4,d7,w
.endm;
funcwdxea:.macro // ea(\4) function(\3) dx -> ea
ii_0x\11\2:
\3 d0_off+2(a7),\4,w
ii_0x\13\2:
\3 d1_off+2(a7),\4,w
ii_0x\15\2:
\3 d2,\4,w
ii_0x\17\2:
\3 d3,\4,w
ii_0x\19\2:
\3 d4,\4,w
ii_0x\1b\2:
\3 d5,\4,w
ii_0x\1d\2:
\3 d6,\4,w
ii_0x\1f\2:
\3 d7,\4,w
.endm;
//--------------------------------------------------------------------
// long
funcleadx:.macro // dx function(\3) ea(\4) -> dx
ii_0x\10\2:
\3 \4,d0_off(a7),w
ii_0x\12\2:
\3 \4,d1_off(a7),w
ii_0x\14\2:
\3 \4,d2,w
ii_0x\16\2:
\3 \4,d3,w
ii_0x\18\2:
\3 \4,d4,w
ii_0x\1a\2:
\3 \4,d5,w
ii_0x\1c\2:
\3 \4,d6,w
ii_0x\1e\2:
\3 \4,d7,w
.endm;
funcldxea:.macro // ea(\4) function(\3) dx -> ea
ii_0x\11\2:
\3 d0_off(a7),\4,w
ii_0x\13\2:
\3 d1_off(a7),\4,w
ii_0x\15\2:
\3 d2,\4,w
ii_0x\17\2:
\3 d3,\4,w
ii_0x\19\2:
\3 d4,\4,w
ii_0x\1b\2:
\3 d5,\4,w
ii_0x\1d\2:
\3 d6,\4,w
ii_0x\1f\2:
\3 d7,\4,w
.endm;
//--------------------------------------------------------------
// address
funcweaax:.macro // ax function(\3) ea(\4)(ext long!) -> ax
ii_0x\10\2:
\3 \4,a0
ii_0x\12\2:
\3 \4,a1
ii_0x\14\2:
\3 \4,a2
ii_0x\16\2:
\3 \4,a3
ii_0x\18\2:
\3 \4,a4
ii_0x\1a\2:
\3 \4,a5
ii_0x\1c\2:
\3 \4,a6
ii_0x\1e\2:
\3a7 \4,a7 // "a7" beachten wegen usp
.endm;
funcweaaxn:.macro // ax function(\3) ea(\4)(ext long!) -> ax
ii_0x\10\2:
\3 \4,a0_off(a7)
ii_0x\12\2:
\3 \4,a1_off(a7)
ii_0x\14\2:
\3 \4,a2
ii_0x\16\2:
\3 \4,a3
ii_0x\18\2:
\3 \4,a4
ii_0x\1a\2:
\3 \4,a5
ii_0x\1c\2:
\3 \4,a6
ii_0x\1e\2:
\3 \4,usp
.endm;
//--------------------------------------------------------------
// byt, word, long
//--------------------------------------------------------------
funcaxay:.macro // ea(\4) function(\3) dx -> ea,\5 = size
ii_0x\11\2:
\3 a0_off(a7),\4,\5
ii_0x\13\2:
\3 a1_off(a7),\4,\5
ii_0x\15\2:
\3 a2,\4,\5
ii_0x\17\2:
\3 a3,\4,\5
ii_0x\19\2:
\3 a4,\4,\5
ii_0x\1b\2:
\3 a5,\4,\5
ii_0x\1d\2:
\3 a6,\4,\5
ii_0x\1f\2:
\3 usp,\4,\5
.endm;

59
sources/ii_jmp.h
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@@ -1,59 +0,0 @@
//--------------------------------------------------------------------
// extension word format missing
//--------------------------------------------------------------------
ii_\1_func:.macro
ii_0x\20:
#ifdef halten_\1
halt
#endif
move.l a0_off(a7),a1
\1_macro
ii_0x\21:
#ifdef halten_\1
halt
#endif
move.l a1_off(a7),a1
\1_macro
ii_0x\22:
#ifdef halten_\1
halt
#endif
move.l a2,a1
\1_macro
ii_0x\23:
#ifdef halten_\1
halt
#endif
move.l a3,a1
\1_macro
ii_0x\24:
#ifdef halten_\1
halt
#endif
move.l a4,a1
\1_macro
ii_0x\25:
#ifdef halten_\1
halt
#endif
move.l a5,a1
\1_macro
ii_0x\26:
#ifdef halten_\1
halt
#endif
move.l a6,a1
\1_macro
ii_0x\27:
#ifdef halten_\1
halt
#endif
move.l usp,a1
\1_macro
ii_0x\2b:
#ifdef halten_\1
halt
#endif
move.l a0,a1
\1_macro
.endm

105
sources/ii_lea.h
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@@ -1,105 +0,0 @@
//-------------------------------------------------------------------
// lea
//-------------------------------------------------------------------
.text
ii_lea_lset:.macro
ii_lset_dxu 4,f0 // lea d8(a0,dy.w),a0-a7
ii_lset_dxu 4,f1 // lea d8(a1,dy.w),a0-a7
ii_lset_dxu 4,f2 // lea d8(a2,dy.w),a0-a7
ii_lset_dxu 4,f3 // lea d8(a3,dy.w),a0-a7
ii_lset_dxu 4,f4 // lea d8(a4,dy.w),a0-a7
ii_lset_dxu 4,f5 // lea d8(a5,dy.w),a0-a7
ii_lset_dxu 4,f6 // lea d8(a6,dy.w),a0-a7
ii_lset_dxu 4,f7 // lea d8(a7,dy.w),a0-a7
ii_lset_dxu 4,fb // lea d8(pc,dy.w),a0-a7
.endm
//---------------------------------------------------------------------------------------------
// function
//---------------------------------------------------------------------------------------------
ii_lea_sub:.macro
ii_0x4\1\2:
#ifdef halten_lea
halt
#endif
move.l \4,a1
jsr ewf
move.l a1,\3
ii_end
.endm
ii_lea_func:.macro
//lea d8(ax,dy.w),a0-a7
ii_lea_sub 1,f0,a0_off(a7),a0_off(a7)
ii_lea_sub 1,f1,a0_off(a7),a1_off(a7)
ii_lea_sub 1,f2,a0_off(a7),a2
ii_lea_sub 1,f3,a0_off(a7),a3
ii_lea_sub 1,f4,a0_off(a7),a4
ii_lea_sub 1,f5,a0_off(a7),a5
ii_lea_sub 1,f6,a0_off(a7),a6
ii_lea_sub 1,f7,a0_off(a7),usp
ii_lea_sub 3,f0,a1_off(a7),a0_off(a7)
ii_lea_sub 3,f1,a1_off(a7),a1_off(a7)
ii_lea_sub 3,f2,a1_off(a7),a2
ii_lea_sub 3,f3,a1_off(a7),a3
ii_lea_sub 3,f4,a1_off(a7),a4
ii_lea_sub 3,f5,a1_off(a7),a5
ii_lea_sub 3,f6,a1_off(a7),a6
ii_lea_sub 3,f7,a1_off(a7),usp
ii_lea_sub 5,f0,a2,a0_off(a7)
ii_lea_sub 5,f1,a2,a1_off(a7)
ii_lea_sub 5,f2,a2,a2
ii_lea_sub 5,f3,a2,a3
ii_lea_sub 5,f4,a2,a4
ii_lea_sub 5,f5,a2,a5
ii_lea_sub 5,f6,a2,a6
ii_lea_sub 5,f7,a2,usp
ii_lea_sub 7,f0,a3,a0_off(a7)
ii_lea_sub 7,f1,a3,a1_off(a7)
ii_lea_sub 7,f2,a3,a2
ii_lea_sub 7,f3,a3,a3
ii_lea_sub 7,f4,a3,a4
ii_lea_sub 7,f5,a3,a5
ii_lea_sub 7,f6,a3,a6
ii_lea_sub 7,f7,a3,usp
ii_lea_sub 9,f0,a4,a0_off(a7)
ii_lea_sub 9,f1,a4,a1_off(a7)
ii_lea_sub 9,f2,a4,a2
ii_lea_sub 9,f3,a4,a3
ii_lea_sub 9,f4,a4,a4
ii_lea_sub 9,f5,a4,a5
ii_lea_sub 9,f6,a4,a6
ii_lea_sub 9,f7,a4,usp
ii_lea_sub b,f0,a5,a0_off(a7)
ii_lea_sub b,f1,a5,a1_off(a7)
ii_lea_sub b,f2,a5,a2
ii_lea_sub b,f3,a5,a3
ii_lea_sub b,f4,a5,a4
ii_lea_sub b,f5,a5,a5
ii_lea_sub b,f6,a5,a6
ii_lea_sub b,f7,a6,usp
ii_lea_sub d,f0,a6,a0_off(a7)
ii_lea_sub d,f1,a6,a1_off(a7)
ii_lea_sub d,f2,a6,a2
ii_lea_sub d,f3,a6,a3
ii_lea_sub d,f4,a6,a4
ii_lea_sub d,f5,a6,a5
ii_lea_sub d,f6,a6,a6
ii_lea_sub d,f7,a6,usp
ii_lea_sub f,f0,usp,a0_off(a7)
ii_lea_sub f,f1,usp,a1_off(a7)
ii_lea_sub f,f2,usp,a2
ii_lea_sub f,f3,usp,a3
ii_lea_sub f,f4,usp,a4
ii_lea_sub f,f5,usp,a5
ii_lea_sub f,f6,usp,a6
ii_lea_sub f,f7,usp,usp
// lea d8(pc,dy.w),az
ii_lea_sub 1,fb,a0_off(a7),a0
ii_lea_sub 3,fb,a1_off(a7),a0
ii_lea_sub 5,fb,a2,a0
ii_lea_sub 7,fb,a3,a0
ii_lea_sub 9,fb,a4,a0
ii_lea_sub b,fb,a5,a0
ii_lea_sub d,fb,a6,a0
ii_lea_sub f,fb,usp,a0
.endm

144
sources/ii_macro.h
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@@ -1,144 +0,0 @@
/*******************************************************/
// constanten
/*******************************************************/
.extern ___RAMBAR1
.extern _rt_cacr
.extern _rt_mod
.extern _rt_ssp
.extern _rt_usp
.extern _rt_vbr
.extern _d0_save
.extern _a7_save
ii_ss = 16
d0_off = 0
d1_off = 4
a0_off = 8
a1_off = 12
format_off = 16
sr_off = 18
ccr_off = 19
pc_off = 20
#define table 0x20000000-0x8000-0xF000*4 // Adresse Sprungtabelle -> 8000=Sprungbereich mod cod, 61k(ohne 0xFxxx!)x4= tabelle
/*******************************************************/
// allgemeine macros
/*******************************************************/
ii_end: .macro
move.l a0,pc_off(a7)
movem.l (a7),d0/d1/a0/a1
lea ii_ss(a7),a7
rte
.endm;
set_cc0:.macro
move.w ccr,d0
move.b d0,ccr_off(a7)
.endm;
ii_esr: .macro // geht nicht!!??
movem.l (a7),d0/d1/a0/a1
lea ii_ss+8(a7),a7 // stack erh<72>hen
move.w d0,_d0_save // d0.w sicheren
move.w -6(a7),d0 // sr holen
move.w d0,sr // sr setzen
nop
move.w _d0_save,d0 // d0.w zur<75>ck
.endm;
ii_end_mvm:.macro
move.l a0_off(a7),a0
lea 16(a7),a7
rte
.endm;
ii_endj:.macro
movem.l (a7),d0/d1/a0/a1 // register zur<75>ck
lea ii_ss(a7),a7 // korr
rte // ende
.endm;
set_nzvc:.macro // set ccr bits nzvc
move.w ccr,d1
bclr #4,d1
btst #4,ccr_off(a7)
beq snzvc2\@
bset #4,d1
snzvc2\@:
move.b d1,ccr_off(a7)
.endm;
set_cc1:.macro
move.w ccr,d1
move.b d1,ccr_off(a7)
.endm;
set_cc_b:.macro
move.w ccr,d1
btst #7,d0 // byt negativ?
beq set_cc_b2\@
bset #3,d1 // make negativ
set_cc_b2\@:
move.b d1,ccr_off(a7)
.endm;
set_cc_w:.macro
move.w ccr,d1
btst #15,d0 // byt negativ?
beq set_cc_w2\@
bset #3,d1 // make negativ
set_cc_w2\@:
move.b d1,ccr_off(a7)
.endm;
get_pc: .macro
lea.l (a0),a1
.endm;
//--------------------------------------------------------------------
ii_lset:.macro
lea table+\1*4,a0
move.l #ii_\1,(a0)
.endm;
ii_lset_dx:.macro // 0x1.22 -> z.B. 1=d,2=4 ->0xd040 -> 0xde40
ii_lset_dxg \1,\2
ii_lset_dxu \1,\2
.endm;
ii_lset_dxg:.macro // gerade: 0x1.22 -> z.B. 1=d,2=4 ->0xd040 -> 0xde40
lea table+0x\10\2*4,a0
move.l #ii_0x\10\2,(a0)
lea 0x800(a0),a0 // 4 * 0x200
move.l #ii_0x\12\2,(a0)
lea 0x800(a0),a0
move.l #ii_0x\14\2,(a0)
lea 0x800(a0),a0
move.l #ii_0x\16\2,(a0)
lea 0x800(a0),a0
move.l #ii_0x\18\2,(a0)
lea 0x800(a0),a0
move.l #ii_0x\1a\2,(a0)
lea 0x800(a0),a0
move.l #ii_0x\1c\2,(a0)
lea 0x800(a0),a0
move.l #ii_0x\1e\2,(a0)
.endm;
ii_lset_dxu:.macro // ungerade: 0x1.22 -> z.B. 1=d,2=4 ->0xd140 -> 0xdf40
lea table+0x\11\2*4,a0
move.l #ii_0x\11\2,(a0)
lea 0x800(a0),a0
move.l #ii_0x\13\2,(a0)
lea 0x800(a0),a0
move.l #ii_0x\15\2,(a0)
lea 0x800(a0),a0
move.l #ii_0x\17\2,(a0)
lea 0x800(a0),a0
move.l #ii_0x\19\2,(a0)
lea 0x800(a0),a0
move.l #ii_0x\1b\2,(a0)
lea 0x800(a0),a0
move.l #ii_0x\1d\2,(a0)
lea 0x800(a0),a0
move.l #ii_0x\1f\2,(a0)
.endm;

1271
sources/ii_move.h
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374
sources/ii_movem.h
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@@ -1,374 +0,0 @@
//***********************************************************************************/
// movem
//***********************************************************************************/
ii_movem_lset: .macro
// movem.l rx,xxx.L
ii_lset 0x48f9
// movem.l xxx.L,rx
ii_lset 0x4cf9
// movem.w rx,xxx.L
ii_lset 0x48b9
// movem.w xxx.L,rx
ii_lset 0x4cb9
// movem.l rx,-(ax)
ii_lset 0x48e0
ii_lset 0x48e1
ii_lset 0x48e2
ii_lset 0x48e3
ii_lset 0x48e4
ii_lset 0x48e5
ii_lset 0x48e6
ii_lset 0x48e7
// movem.l (ax)+,rx
ii_lset 0x4cd8
ii_lset 0x4cd9
ii_lset 0x4cda
ii_lset 0x4cdb
ii_lset 0x4cdc
ii_lset 0x4cdd
ii_lset 0x4cde
ii_lset 0x4cdf
.endm
//***********************************************************************************/
ii_movem_func: .macro
//-------------------------------------------------------------------
// movem.l
//--------------------------------------------------------------------
// movem.l (ax)+,reg
//--------------------------------------------------------------------
.long 0
az_reg_table:
.byte 0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4 // 0-f
.byte 1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5 // 10-1f
.byte 1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5 // 20-2f
.byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // 30-3f
.byte 1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5 // 40-4f
.byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // 50
.byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // 60
.byte 3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7 // 70
.byte 1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5 // 80-8f
.byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // 90
.byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // a0
.byte 3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7 // b0
.byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // c0
.byte 3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7 // d0
.byte 3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7 // e0
.byte 4,5,5,6,5,6,6,7,5,6,6,7,6,7,7,8 // f0
//-------------------------------------------------------------------------------
ii_0x48e0: // movem.l reglist,-(a0)
mvm_mem_macro 0x48d0,a0_off(a7),2
ii_0x48e1: // movem.l reglist,-(a1)
mvm_mem_macro 0x48d1,a1_off(a7),2
ii_0x48e2: // movem.l reglist,-(a2)
mvm_mem_macro 0x48d2,a2,2
ii_0x48e3: // movem.l reglist,-(a3)
mvm_mem_macro 0x48d3,a3,2
ii_0x48e4: // movem.l reglist,-(a4)
mvm_mem_macro 0x48d4,a4,2
ii_0x48e5: // movem.l reglist,-(a5)
mvm_mem_macro 0x48d5,a5,2
ii_0x48e6: // movem.l reglist,-(a6)
mvm_mem_macro 0x48d6,a6,2
ii_0x48e7: // movem.l reglist,-(a7)
mvm_mem_macro 0x48d7,usp,2
//-------------------------------------------------------------------------------
ii_0x4cd8: // movem.l (a0)+,reglist
mvm_reg_macro 0x4cd0,0x41e8,2
ii_0x4cd9: // movem.l (a1)+,reglist
mvm_reg_macro 0x4cd1,0x43e9,2
ii_0x4cda: // movem.l (a2)+,reglist
mvm_reg_macro 0x4cd2,0x45ea,2
ii_0x4cdb: // movem.l (a3)+,reglist
mvm_reg_macro 0x4cd3,0x47eb,2
ii_0x4cdc: // movem.l (a4)+,reglist
mvm_reg_macro 0x4cd4,0x49ec,2
ii_0x4cdd: // movem.l (a5)+,reglist
mvm_reg_macro 0x4cd5,0x4bed,2
ii_0x4cde: // movem.l (a6)+,reglist
mvm_reg_macro 0x4cd6,0x4dee,2
ii_0x4cdf: // movem.l (a7)+,reglist
mvm_reg_macro 0x4cd7,0x4fef,2
//----------------------------------------------------------------------------
ii_0x48f9: // movem.l reg,xxx.L
#ifdef halten_movem
halt
#endif
move.w (a0)+,d0
move.l (a0)+,a1
movemrm_macro l
//---------------------------------------------------------------------------------------------
ii_0x4cf9: // movem.l xxx.L,reg
#ifdef halten_movem
halt
#endif
move.w (a0)+,d0
move.l (a0)+,a1
movemmr_macro l
//----------------------------------------------------------------------------
ii_0x48b9: // movem.w reg,xxx.L
#ifdef halten_movem
halt
#endif
move.w (a0)+,d0
move.l (a0)+,a1
movemrm_macro w
//---------------------------------------------------------------------------------------------
ii_0x4cb9: // movem.w xxx.L,reg
#ifdef halten_movem
halt
#endif
move.w (a0)+,d0
move.l (a0)+,a1
movemmr_macro w
.endm
//==============================================================
mvm_mem_macro:.macro
#ifdef halten_movem
halt
#endif
lea az_reg_table,a1
mvz.b (a0),d1
mvz.b 0(a1,d1)+,d0
mvz.b 1(a0),d1
mvz.b 0(a1,d1)+,d1
add.l d0,d1
lsl.l #\3,d1 // * anzahl byts pro wert
move.l \2,a1
sub.l d1,a1 // ax-anzahl byts
move.l a1,\2
lea ___RAMBAR1,a1
move.l a1,pc_off(a7)
move.l a1,d0
addq.l #1,d0
movec d0,RAMBAR1
move.w #\1,(a1)+ // movem.x reg_list,-(a7)
move.w (a0)+,(a1)+ // register list
move.w #0x4ef9,(a1)+ // jmp.l
move.l a0,(a1) // r<>cksprungadresse
move.l #___RAMBAR1 + 0x81,d0 // instruction
movec d0,RAMBAR1
movem.l (a7),d0/d1/a0/a1
lea ii_ss(a7),a7 // stack erh<72>hen
rte
.endm
//---------------------------------------------------------------------------------
mvm_reg_macro:.macro
#ifdef halten_movem
halt
#endif
lea az_reg_table,a1
mvz.b (a0),d1
mvz.b 0(a1,d1)+,d0
mvz.b 1(a0),d1
mvz.b 0(a1,d1)+,d1
add.l d0,d1
lea ___RAMBAR1,a1
move.l a1,pc_off(a7)
move.l a1,d0
addq.l #1,d0
movec d0,RAMBAR1
move.w #\1,(a1)+ // movem.x (ax),reg_list
move.w (a0)+,(a1)+ // register list
move.w #\2,(a1)+ // lea 0(ax),ax
lsl.l #\3,d1 // * anzahl byts pro wert
move.w d1,(a1)+ // offset von lea
move.w #0x4ef9,(a1)+ // jmp.l
move.l a0,(a1) // r<>cksprungadresse
move.l #___RAMBAR1 + 0x81,d0 // instruction
movec d0,RAMBAR1
movem.l (a7),d0/d1/a0/a1
lea ii_ss(a7),a7 // stack erh<72>hen
rte
.endm
//---------------------------------------------------------------------------------
movemrm_macro:.macro // in d0 register liste, in a1 zieladresse
#ifdef halten_movem
halt
#endif
tst.b d0 // datenregister zu verschieben?
bne mrm_dx\@ // ja->
lsr.l #8,d0 // sonst zu addressregister
jmp mmrm_nd7\@ // ->
mrm_dx\@:
lsr.l #1,d0
bcc mmrm_nd0\@
.ifc 1,l
move.l d0_off(a7),(a1)+
.else
move.w d0_off+2(a7),(a1)+
.endif
mmrm_nd0\@:
lsr.l #1,d0
bcc mmrm_nd1\@
.ifc 1,l
move.l d1_off(a7),(a1)+
.else
move.w d1_off+2(a7),(a1)+
.endif
mmrm_nd1\@:
lsr.l #1,d0
bcc mmrm_nd2\@
move.\1 d2,(a1)+
mmrm_nd2\@:
lsr.l #1,d0
bcc mmrm_nd3\@
move.\1 d3,(a1)+
mmrm_nd3\@:
lsr.l #1,d0
bcc mmrm_nd4\@
move.\1 d4,(a1)+
mmrm_nd4\@:
lsr.l #1,d0
bcc mmrm_nd5\@
move.\1 d5,(a1)+
mmrm_nd5\@:
lsr.l #1,d0
bcc mmrm_nd6\@
move.l d6,(a1)+
mmrm_nd6\@:
lsr.l #1,d0
bcc mmrm_nd7\@
move.\1 d7,(a1)+
mmrm_nd7\@:
tst.b d0 // addressregister zu verschieben?
beq mmrm_na7\@
lsr.l #1,d0
bcc mmrm_na0\@
.ifc 1,l
move.l a0_off(a7),(a1)+
.else
move.w a0_off+2(a7),(a1)+
.endif
mmrm_na0\@:
lsr.l #1,d0
bcc mmrm_na1\@
.ifc 1,l
move.l a1_off(a7),(a1)+
.else
move.w a1_off+2(a7),(a1)+
.endif
mmrm_na1\@:
lsr.l #1,d0
bcc mmrm_na2\@
move.\1 a2,(a1)+
mmrm_na2\@:
lsr.l #1,d0
bcc mmrm_na3\@
move.\1 a3,(a1)+
mmrm_na3\@:
lsr.l #1,d0
bcc mmrm_na4\@
move.\1 a4,(a1)+
mmrm_na4\@:
lsr.l #1,d0
bcc mmrm_na5\@
move.\1 a5,(a1)+
mmrm_na5\@:
lsr.l #1,d0
bcc mmrm_na6\@
move.\1 a6,(a1)+
mmrm_na6\@:
lsr.l #1,d0
bcc mmrm_na7\@
move.l a0,d1 // sichern
move.l usp,a0 // ist ja usp
move.\1 a0,(a1)+ // nach a0
move.l d1,a0 // pc zur<75>ck
mmrm_na7\@:
ii_end
.endm
//---------------------------------------------------------------------------------------------
movemmr_macro:.macro // in d0 register liste, in a1 source adr
#ifdef halten_movem
halt
#endif
tst.b d0 // datenregister zu verschieben?
bne mmr_dx\@ // ja->
lsr.l #8,d0 // sonst zu addressregister
bra mmmr_nd7\@ // ->
mmr_dx\@:
lsr.l #1,d0
bcc mmmr_nd0\@
.ifc 1,l
move.l (a1)+,d0_off(a7)
.else
move.w (a1)+,d0_off+2(a7)
.endif
mmmr_nd0\@:
lsr.l #1,d0
bcc mmmr_nd1\@
.ifc 1,l
move.l (a1)+,d1_off(a7)
.else
move.w (a1)+,d1_off+2(a7)
.endif
mmmr_nd1\@:
lsr.l #1,d0
bcc mmmr_nd2\@
move.\1 (a1)+,d2
mmmr_nd2\@:
lsr.l #1,d0
bcc mmmr_nd3\@
move.\1 (a1)+,d3
mmmr_nd3\@:
lsr.l #1,d0
bcc mmmr_nd4\@
move.\1 (a1)+,d4
mmmr_nd4\@:
lsr.l #1,d0
bcc mmmr_nd5\@
move.\1 (a1)+,d5
mmmr_nd5\@:
lsr.l #1,d0
bcc mmmr_nd6\@
move.\1 (a1)+,d6
mmmr_nd6\@:
lsr.l #1,d0
bcc mmmr_nd7\@
move.\1 (a1)+,d7
mmmr_nd7\@:
tst.b d0 // addressregister zu verschieben?
beq mmmr_na7\@ // nein->
lsr.l #1,d0
bcc mmmr_na0\@
.ifc 1,l
move.l (a1)+,a0_off(a7)
.else
move.w (a1)+,a0_off+2(a7)
.endif
mmmr_na0\@:
lsr.l #1,d0
bcc mmmr_na1\@
.ifc 1,l
move.l (a1)+,a1_off(a7)
.else
move.w (a1)+,a1_off+2(a7)
.endif
mmmr_na1\@:
lsr.l #1,d0
bcc mmmr_na2\@
move.\1 (a1)+,a2
mmmr_na2\@:
lsr.l #1,d0
bcc mmmr_na3\@
move.\1 (a1)+,a3
mmmr_na3\@:
lsr.l #1,d0
bcc mmmr_na4\@
move.\1 (a1)+,a4
mmmr_na4\@:
lsr.l #1,d0
bcc mmmr_na5\@
move.\1 (a1)+,a5
mmmr_na5\@:
lsr.l #1,d0
bcc mmmr_na6\@
move.\1 (a1)+,a6
mmmr_na6\@:
lsr.l #1,d0
bcc mmmr_na7\@
move.\1 (a1)+,a1 // nach a0
move.l a1,usp // war ja usp
mmmr_na7\@:
ii_end
.endm

179
sources/ii_movep.h
View File

@@ -1,179 +0,0 @@
//--------------------------------------------------------------------
// movep
//--------------------------------------------------------------------
.text
ii_movep_lset:.macro
ii_lset_opeau 01,0 //movep.w d(a0-7),d0
ii_lset_opeau 03,0 //movep.w d(a0-7),d1
ii_lset_opeau 05,0 //movep.w d(a0-7),d2
ii_lset_opeau 07,0 //movep.w d(a0-7),d3
ii_lset_opeau 09,0 //movep.w d(a0-7),d4
ii_lset_opeau 0b,0 //movep.w d(a0-7),d5
ii_lset_opeau 0d,0 //movep.w d(a0-7),d6
ii_lset_opeau 0f,0 //movep.w d(a0-7),d7
ii_lset_opeau 01,4 //movep.w d0,d(a0-7)
ii_lset_opeau 03,4 //movep.w d1,d(a0-7)
ii_lset_opeau 05,4 //movep.w d2,d(a0-7)
ii_lset_opeau 07,4 //movep.w d3,d(a0-7)
ii_lset_opeau 09,4 //movep.w d4,d(a0-7)
ii_lset_opeau 0b,4 //movep.w d5,d(a0-7)
ii_lset_opeau 0d,4 //movep.w d6,d(a0-7)
ii_lset_opeau 0f,4 //movep.w d7,d(a0-7)
ii_lset_opeau 01,8 //movep.l d(a0-7),d0
ii_lset_opeau 03,8 //movep.l d(a0-7),d1
ii_lset_opeau 05,8 //movep.l d(a0-7),d2
ii_lset_opeau 07,8 //movep.l d(a0-7),d3
ii_lset_opeau 09,8 //movep.l d(a0-7),d4
ii_lset_opeau 0b,8 //movep.l d(a0-7),d5
ii_lset_opeau 0d,8 //movep.l d(a0-7),d6
ii_lset_opeau 0f,8 //movep.l d(a0-7),d7
ii_lset_opeau 01,c //movep.l d0,d(a0-7)
ii_lset_opeau 03,c //movep.l d1,d(a0-7)
ii_lset_opeau 05,c //movep.l d2,d(a0-7)
ii_lset_opeau 07,c //movep.l d3,d(a0-7)
ii_lset_opeau 09,c //movep.l d4,d(a0-7)
ii_lset_opeau 0b,c //movep.l d5,d(a0-7)
ii_lset_opeau 0d,c //movep.l d6,d(a0-7)
ii_lset_opeau 0f,c //movep.l d7,d(a0-7)
.endm
//---------------------------------------------------------------------------------------------
ii_movep_func:.macro
//movep.w d(a0-7),d0-7
ii_movep 010,d0_off(a7),wad
ii_movep 030,d1_off(a7),wad
ii_movep 050,d2,wad
ii_movep 070,d3,wad
ii_movep 090,d4,wad
ii_movep 0b0,d5,wad
ii_movep 0d0,d6,wad
ii_movep 0f0,d7,wad
//movep.w d0-7,d(a0-7)
ii_movep 014,d0_off(a7),wda
ii_movep 034,d1_off(a7),wda
ii_movep 054,d2,wda
ii_movep 074,d3,wda
ii_movep 094,d4,wda
ii_movep 0b4,d5,wda
ii_movep 0d4,d6,wda
ii_movep 0f4,d7,wda
//movep.l d(a0-7),d0-7
ii_movep 018,d0_off(a7),lad
ii_movep 038,d1_off(a7),lad
ii_movep 058,d2,lad
ii_movep 078,d3,lad
ii_movep 098,d4,lad
ii_movep 0b8,d5,lad
ii_movep 0d8,d6,lad
ii_movep 0f8,d7,lad
//movep.l d0-7,d(a0-7)
ii_movep 01c,d0_off(a7),lda
ii_movep 03c,d1_off(a7),lda
ii_movep 05c,d2,lda
ii_movep 07c,d3,lda
ii_movep 09c,d4,lda
ii_movep 0bc,d5,lda
ii_movep 0dc,d6,lda
ii_movep 0fc,d7,lda
.endm
//---------------------------------------------------------------------------------------------
ii_movep:.macro //1=code ziffer 1-3 2=register 3=art
ii_0x\18:
#ifdef halten_movep
halt
#endif
move.l a0_off(a7),a1
ii_movep\3_up1 \2
ii_0x\19:
#ifdef halten_movep
halt
#endif
move.l a1_off(a7),a1
ii_movep\3_up1 \2
ii_0x\1a:
#ifdef halten_movep
halt
#endif
move.l a2,a1
ii_movep\3_up1 \2
ii_0x\1b:
#ifdef halten_movep
halt
#endif
move.l a3,a1
ii_movep\3_up1 \2
ii_0x\1c:
#ifdef halten_movep
halt
#endif
move.l a4,a1
ii_movep\3_up1 \2
ii_0x\1d:
#ifdef halten_movep
halt
#endif
move.l a5,a1
ii_movep\3_up1 \2
ii_0x\1e:
#ifdef halten_movep
halt
#endif
move.l a6,a1
ii_movep\3_up1 \2
ii_0x\1f:
#ifdef halten_movep
halt
#endif
move.l usp,a1
ii_movep\3_up1 \2
.endm
ii_movepwad_up1:.macro
mvs.w (a0)+,d1
add.l d1,a1
move.b (a1),d0
lsl.l #8,d0
move.b 2(a1,d1.l),d0
move.w d0,\1
ii_end
.endm
ii_movepwda_up1:.macro
mvs.w (a0)+,d1
add.l d1,a1
move.w \1,d0
move.b d0,2(a1)
lsr.l #8,d0
move.b d0,(a1)
ii_end
.endm
ii_moveplad_up1:.macro
mvs.w (a0)+,d1
add.l d1,a1
move.b (a1),d0
lsl.l #8,d0
move.b 2(a1),d0
lsl.l #8,d0
move.b 4(a1),d0
lsl.l #8,d0
move.b 6(a1),d0
move.l d0,\1
ii_end
.endm
ii_moveplda_up1:.macro
mvs.w (a0)+,d1
add.l d1,a1
move.l \1,d0
move.b d0,6(a1)
lsr.l #8,d0
move.b d0,4(a1)
lsr.l #8,d0
move.b d0,2(a1)
lsr.l #8,d0
move.b d0,(a1)
ii_end
.endm

661
sources/ii_op.h
View File

@@ -1,661 +0,0 @@
/*****************************************************************************************/
// opertionen
/*****************************************************************************************/
ii_lset_op:.macro
//byt
ii_lset_opea \1,0 // dx,ax
ii_lset_opea \1,1 // (ax), (ax)+
ii_lset_opea \1,2 // -(ax),d16(ax)
ii_lset_opeag \1,3 // d8(ax,dy)
lea table+0x\1\238*4,a0
move.l #ii_0x\138,(a0)+ // xxx.w
move.l #ii_0x\139,(a0)+ // xxx.l
//word
ii_lset_opea \1,4 // dx,ax
ii_lset_opea \1,5 // (ax), (ax)+
ii_lset_opea \1,6 // -(ax),d16(ax)
ii_lset_opeag \1,7 // d8(ax,dy)
lea table+0x\178*4,a0
move.l #ii_0x\178,(a0)+ // xxx.w
move.l #ii_0x\179,(a0)+ // xxx.l
//long
ii_lset_opea \1,8 // dx,ax
ii_lset_opea \1,9 // (ax), (ax)+
ii_lset_opea \1,a // -(ax),d16(ax)
ii_lset_opeag \1,b // d8(ax,dy)
lea table+0x\1b8*4,a0
move.l #ii_0x\1b8,(a0)+ // xxx.w
move.l #ii_0x\1b9,(a0)+ // xxx.l
.endm
ii_lset_opeag:.macro // 0x1120-0x1127
lea table+0x\1\20*4,a0
move.l #ii_0x\1\20,(a0)+
move.l #ii_0x\1\21,(a0)+
move.l #ii_0x\1\22,(a0)+
move.l #ii_0x\1\23,(a0)+
move.l #ii_0x\1\24,(a0)+
move.l #ii_0x\1\25,(a0)+
move.l #ii_0x\1\26,(a0)+
move.l #ii_0x\1\27,(a0)+
.endm;
ii_lset_opeau:.macro // 0x1128-0x112f
lea table+0x\1\28*4,a0
move.l #ii_0x\1\28,(a0)+
move.l #ii_0x\1\29,(a0)+
move.l #ii_0x\1\2a,(a0)+
move.l #ii_0x\1\2b,(a0)+
move.l #ii_0x\1\2c,(a0)+
move.l #ii_0x\1\2d,(a0)+
move.l #ii_0x\1\2e,(a0)+
move.l #ii_0x\1\2f,(a0)+
.endm;
ii_lset_opea:.macro
ii_lset_opeag \1,\2
ii_lset_opeau \1,\2
.endm
/******************************************************/
ii_op:.macro // 1=code 2=operation 3 = normal oder immediat/quick
// byt
opdx \1,\2,b,0,\3 // dx,ax
opia \1,\2,b,1,\3 // (ax),(ax)+
opdia \1,\2,b,2,\3 // -(ax),d16(ax)
opd8a \1,\2,b,3,\3 // d8(ax),xxx
// word
opdx \1,\2,w,4,\3 // dx,ax
opia \1,\2,w,5,\3 // (ax),(ax)+
opdia \1,\2,w,6,\3 // -(ax),d16(ax)
opd8a \1,\2,w,7,\3 // d8(ax),xxx
// long
opdx \1,\2,l,8,\3 // dx,ax
opia \1,\2,l,9,\3 // (ax),(ax)+
opdia \1,\2,l,a,\3 // -(ax),d16(ax)
opd8a \1,\2,l,b,\3 // d8(ax),xxx
.endm
/******************************************************/
// byt word long
/******************************************************/
opdx: .macro //register: \1=code \2 = operation \3 = size \4=size and adressierungsart 5 = immediate oder normal
ii_0x\1\40:
.ifc \3,b
op\5smd \2,d0_off+3(a7),d0_off+3(a7),\3
.else
.ifc \3,w
op\5smd \2,d0_off+2(a7),d0_off+2(a7),\3
.else
op\5smd \2,d0_off(a7),d0_off(a7),\3
.endif
.endif
ii_0x\1\41:
.ifc \3,b
op\5smd \2,d1_off+3(a7),d1_off+3(a7),\3
.else
.ifc \3,w
op\5smd \2,d1_off+2(a7),d1_off+2(a7),\3
.else
op\5smd \2,d1_off(a7),d1_off(a7),\3
.endif
.endif
ii_0x\1\42:
op\5smd \2,d2,d2,\3
ii_0x\1\43:
op\5smd \2,d3,d3,\3
ii_0x\1\44:
op\5smd \2,d4,d4,\3
ii_0x\1\45:
op\5smd \2,d5,d5,\3
ii_0x\1\46:
op\5smd \2,d6,d6,\3
ii_0x\1\47:
op\5smd \2,d7,d7,\3
//ax
ii_0x\1\48:
opa\5smd \2,a0_off(a7),a0_off(a7),\3
ii_0x\1\49:
opa\5smd \2,a1_off(a7),a1_off(a7),\3
ii_0x\1\4a:
opa\5smd \2,a2,a2,\3
ii_0x\1\4b:
opa\5smd \2,a3,a3,\3
ii_0x\1\4c:
opa\5smd \2,a4,a4,\3
ii_0x\1\4d:
opa\5smd \2,a5,a5,\3
ii_0x\1\4e:
opa\5smd \2,a6,a6,\3
ii_0x\1\4f:
opa\5smd \2,usp,usp,\3
.endm;
//-----------------------------------------------
opia: .macro // (ax) \1=code \2 = operation \3 = size \4=size and adressierungsart 5 = immediate oder normal
//(ax)
ii_0x\1\40:
op\5sia \2,a0_off(a7),(a1),(a1),\3
ii_0x\1\41:
op\5sia \2,a1_off(a7),(a1),(a1),\3
ii_0x\1\42:
op\5smd \2,(a2),(a2),\3
ii_0x\1\43:
op\5smd \2,(a3),(a3),\3
ii_0x\1\44:
op\5smd \2,(a4),(a4),\3
ii_0x\1\45:
op\5smd \2,(a5),(a5),\3
ii_0x\1\46:
op\5smd \2,(a6),(a6),\3
ii_0x\1\47:
op\5sia \2,usp,(a1),(a1),\3
//(ax)+
ii_0x\1\48:
op\5sia \2,a0_off(a7),(a1),(a1)+,\3
ii_0x\1\49:
op\5sia \2,a1_off(a7),(a1),(a1)+,\3
ii_0x\1\4a:
op\5smd \2,(a2),(a2)+,\3
ii_0x\1\4b:
op\5smd \2,(a3),(a3)+,\3
ii_0x\1\4c:
op\5smd \2,(a4),(a4)+,\3
ii_0x\1\4d:
op\5smd \2,(a5),(a5)+,\3
ii_0x\1\4e:
op\5smd \2,(a6),(a6)+,\3
ii_0x\1\4f:
op\5sia \2,usp,(a1),(a1)+,\3
.endm;
//-----------------------------------------------
opdia: .macro // -(ax) \1=code \2 = operation \3 = size \4 size and adressierungsart 5 = immediate oder normal
ii_0x\1\40:
op\5sia \2,a0_off(a7),-(a1),(a1),\3
ii_0x\1\41:
op\5sia \2,a1_off(a7),-(a1),(a1),\3
ii_0x\1\42:
op\5smd \2,-(a2),(a2),\3
ii_0x\1\43:
op\5smd \2,-(a3),(a3),\3
ii_0x\1\44:
op\5smd \2,-(a4),(a4),\3
ii_0x\1\45:
op\5smd \2,-(a5),(a5),\3
ii_0x\1\46:
op\5smd \2,-(a6),(a6),\3
ii_0x\1\47:
op\5sia \2,usp,-(a1),(a1),\3
ii_0x\1\48:
op\5sd16a \2,a0_off(a7),\3
ii_0x\1\49:
op\5sd16a \2,a1_off(a7),\3
ii_0x\1\4a:
op\5sd16a \2,a2,\3
ii_0x\1\4b:
op\5sd16a \2,a3,\3
ii_0x\1\4c:
op\5sd16a \2,a4,\3
ii_0x\1\4d:
op\5sd16a \2,a5,\3
ii_0x\1\4e:
op\5sd16a \2,a6,\3
ii_0x\1\4f:
op\5sd16a \2,usp,\3
.endm;
//-----------------------------------------------
opd8a: .macro // d8(ax,dy) \1=code \2 = operation \3 = size \4=size and adressierungsart 5 = immediate oder normal
ii_0x\1\40:
op\5sd8a \2,a0_off(a7),\3
ii_0x\1\41:
op\5sd8a \2,a1_off(a7),\3
ii_0x\1\42:
op\5sd8a \2,a2,\3
ii_0x\1\43:
op\5sd8a \2,a3,\3
ii_0x\1\44:
op\5sd8a \2,a4,\3
ii_0x\1\45:
op\5sd8a \2,a5,\3
ii_0x\1\46:
op\5sd8a \2,a6,\3
ii_0x\1\47:
op\5sd8a \2,usp,\3
ii_0x\1\48:
op\5sxx \2,\3,w
ii_0x\1\49:
op\5sxx \2,\3,l
.endm;
//-----------------------------------------------
opnsmd:.macro // direct dx: 1=operation 2=ea src 3=ea dest 4=size
#ifdef halten_op
halt
#endif
.ifc \4,l
move.l \2,d1
.else
mvs.\4 \2,d1
.endif
.ifc \1,negx
move.b sr_off+1(a7),d1 //ccr holen
move d1,ccr //setzen
.endif
\1 d1
set_cc0
move.\4 d1,\3
ii_end
.endm;
opansmd:.macro // direct ax: 1=operation 2=ea src 3=ea dest 4=size
#ifdef halten_op
halt
#endif
.ifc \2,usp
move.l usp,a1
move.l a1,d1
.else
move.l \2,d1
.endif
\1 d1
.ifc \3,usp
move.l d1,a1
move.l a1,usp
.else
move.l d1,\3
.endif
ii_end
.endm;
opnsia:.macro // indirect: 1=operation 2=adress register 3= src 4=dest 5=size
#ifdef halten_op
halt
#endif
move.l \2,a1
.ifc \5,l
move.l \3,d1
.else
mvs.\5 \3,d1
.endif
.ifc \1,negx
move.b sr_off+1(a7),d1 //ccr holen
move d1,ccr //setzen
.endif
\1 d1
set_cc0
move.\5 d1,\4
ii_end
.endm;
opnsd16a:.macro // indirect: 1=operation 2=adress register 3=size
#ifdef halten_op
halt
#endif
move.l \2,a1
mvs.w (a0)+,d1
add.l d1,a1
.ifc \3,l
move.l (a1),d1
.else
mvs.\3 (a1),d1
.endif
.ifc \1,negx
move.b sr_off+1(a7),d1 //ccr holen
move d1,ccr //setzen
.endif
\1 d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
opnsd8a:.macro // indirect: 1=operation 2=adress register 3=size
#ifdef halten_op
halt
#endif
move.l \2,a1
jsr ewf
.ifc \3,l
move.l (a1),d1
.else
mvs.\3 (a1),d1
.endif
.ifc \1,negx
move.b sr_off+1(a7),d1 //ccr holen
move d1,ccr //setzen
.endif
\1 d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
opnsxx:.macro // indirect: 1=operation 2=size 3=size adresse
#ifdef halten_op
halt
#endif
.ifc \2,l
move.l (a1),d1
.else
mvs.\2 (a1),d1
.endif
move.\3 (a0)+,a1
.ifc \1,negx
move.b sr_off+1(a7),d1 //ccr holen
move d1,ccr //setzen
.endif
\1 d1
set_cc0
move.\2 d1,(a1)
ii_end
.endm;
//*******************************************************************************3
opismd:.macro // immediate dx: 1=opieration 2=ea src 3=ea dest 4=size
#ifdef halten_op
halt
#endif
.ifc \4,l
move.l (a0)+,d0
.else
.ifc \4,w
mvs.w (a0)+,d0
.else
move.w (a0)+,d0
extb.l d0
.endif
.endif
.ifc \4,l
move.l \2,d1
.else
mvs.\4 \2,d1
.endif
\1 d0,d1
set_cc0
.ifnc \1,cmp.l
move.\4 d1,\3
.endif
ii_end
.endm;
opaismd:.macro // immediate ax: 1=opieration 2=ea src 3=ea dest 4=size
#ifdef halten_op
halt
#endif
.ifc \4,l
move.l (a0)+,d0
.else
.ifc \4,w
mvs.w (a0)+,d0
.else
move.w (a0)+,d0
extb.l d0
.endif
.endif
.ifc \2,usp
move.l usp,a1
move.l a1,d1
.else
move.l \2,d1
.endif
\1 d0,d1
.ifnc \1,cmp.l
.ifc \3,usp
move.l d1,a1
move.l a1,usp
.else
move.l d1,\3
.endif
.endif
ii_end
.endm;
opisia:.macro // indirect: 1=opieration 2=adress register 3= src 4=dest 5=size
#ifdef halten_op
halt
#endif
.ifc \5,l
move.l (a0)+,d0
.else
.ifc \5,w
mvs.w (a0)+,d0
.else
move.w (a0)+,d0
extb.l d0
.endif
.endif
move.l \2,a1
.ifc \5,l
move.l \3,d1
.else
mvs.\5 \3,d1
.endif
\1 d0,d1
set_cc0
.ifnc \1,cmp.l
move.\5 d1,\4
.endif
ii_end
.endm;
opisd16a:.macro // indirect: 1=opieration 2=adress register 3=size
#ifdef halten_op
halt
#endif
.ifc \3,l
move.l (a0)+,d0
.else
.ifc \3,w
mvs.w (a0)+,d0
.else
move.w (a0)+,d0
extb.l d0
.endif
.endif
move.l \2,a1
mvs.w (a0)+,d1
add.l d1,a1
.ifc \3,l
move.l (a1),d1
.else
mvs.\3 (a1),d1
.endif
\1 d0,d1
set_cc0
.ifnc \1,cmp.l
move.\3 d1,(a1)
.endif
ii_end
.endm;
opisd8a:.macro // indirect: 1=opieration 2=adress register 3=size
#ifdef halten_op
halt
#endif
.ifc \3,l
move.l (a0)+,d0
.else
.ifc \3,w
mvs.w (a0)+,d0
.else
move.w (a0)+,d0
extb.l d0
.endif
.endif
move.l d0,_d0_save
move.l \2,a1
jsr ewf
move.l _d0_save,d0
.ifc \3,l
move.l (a1),d1
.else
mvs.\3 (a1),d1
.endif
\1 d0,d1
set_cc0
.ifnc \1,cmp.l
move.\3 d1,(a1)
.endif
ii_end
.endm;
opisxx:.macro // immediate: 1=opieration 2=size 3=size adresse
.ifc \2,l
move.l (a0)+,d0
.else
.ifc \2,w
mvs.w (a0)+,d0
.else
move.w (a0)+,d0
extb.l d0
.endif
.endif
move.\3 (a0)+,a1
.ifc \2,l
move.l (a1),d1
.else
mvs.\2 (a1),d1
.endif
\1 d0,d1
set_cc0
.ifnc \1,cmp.l
move.\2 d1,(a1)
.endif
ii_end
.endm;
//*******************************************************************************3
opqsmd:.macro // quick: 1=opieration 2=ea src 3=ea dest 4=size
.ifc \4,l
move.l \2,d1
.else
mvs.\4 \2,d1
.endif
.ifc \1,eor.l d0
move.l d0_off(a7),d0
.endif
.ifc \1,eor.l d1
move.l d1_off(a7),d1
.endif
\1 ,d1
set_cc0
move.\4 d1,\3
ii_end
.endm;
opaqsmd:.macro // quick: 1=opieration 2=ea src 3=ea dest 4=size
.ifc \2,usp
move.l usp,a1
move.l a1,d1
.else
move.l \2,d1
.endif
\1 ,d1
.ifc \3,usp
move.l d1,a1
move.l a1,usp
.else
move.l d1,\3
.endif
ii_end
.endm;
opqsia:.macro // indirect: 1=opieration 2=adress register 3= src 4=dest 5=size
#ifdef halten_op
halt
#endif
move.l \2,a1
.ifc \5,l
move.l \3,d1
.else
mvs.\5 \3,d1
.endif
.ifc \1,eor.l d0
move.l d0_off(a7),d0
.endif
.ifc \1,eor.l d1
move.l d1_off(a7),d1
.endif
\1 ,d1
set_cc0
move.\5 d1,\4
ii_end
.endm;
opqsd16a:.macro // indirect: 1=opieration 2=adress register 3=size
#ifdef halten_op
halt
#endif
move.l \2,a1
mvs.w (a0)+,d1
add.l d1,a1
.ifc \3,l
move.l (a1),d1
.else
mvs.\3 (a1),d1
.endif
.ifc \1,eor.l d0
move.l d0_off(a7),d0
.endif
.ifc \1,eor.l d1
move.l d1_off(a7),d1
.endif
\1 ,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
opqsd8a:.macro // indirect: 1=opieration 2=adress register 3=size
#ifdef halten_op
halt
#endif
move.l d0,_d0_save
move.l \2,a1
jsr ewf
move.l _d0_save,d0
.ifc \3,l
move.l (a1),d1
.else
mvs.\3 (a1),d1
.endif
.ifc \1,eor.l d0
move.l d0_off(a7),d0
.endif
.ifc \1,eor.l d1
move.l d1_off(a7),d1
.endif
\1 ,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
opqsxx:.macro // quick: 1=opieration 2=size 3=size adresse
#ifdef halten_op
halt
#endif
move.\3 (a0)+,a1
.ifc \2,l
move.l (a1),d1
.else
mvs.\2 (a1),d1
.endif
.ifc \1,eor.l d0
move.l d0_off(a7),d0
.endif
.ifc \1,eor.l d1
move.l d1_off(a7),d1
.endif
\1 ,d1
set_cc0
move.\2 d1,(a1)
ii_end
.endm;

263
sources/ii_opc.h
View File

@@ -1,263 +0,0 @@
/*****************************************************************************************/
// functionen macros: fehlende adressierungsarte (MCF nur Dx support) ohne ax
// zusammen mit op.h
/*****************************************************************************************/
ii_lset_opc:.macro
ii_lset_opeag \1,c // dx,ax
ii_lset_opea \1,d // (ax), (ax)+
ii_lset_opea \1,e // -(ax),d16(ax)
ii_lset_opeag \1,f // d8(ax,dy)
lea table+0x\1b8*4,a0
move.l #ii_0x\1b8,(a0)+ // xxx.w
move.l #ii_0x\1b9,(a0)+ // xxx.l
.endm
/******************************************************/
ii_opc:.macro // 1=code 2=operation 3 = normal oder immediat
opcdx \1,\2,l,c,\3 // dx,ax
opia \1,\2,l,d,\3 // (ax),(ax)+
opdia \1,\2,l,e,\3 // -(ax),d16(ax)
opd8a \1,\2,l,f,\3 // d8(ax),xxx
.endm
//*******************************************************************************3
/******************************************************/
// byt word long
/******************************************************/
opcdx: .macro //register: \1=code \2 = operation \3 = size \4=size and adressierungsart 5 = immediate oder normal
ii_0x\1\40:
#ifdef halten_opc
halt
#endif
.ifc \3,b
op\5smd \2,d0_off+3(a7),d0_off+3(a7),\3
.else
.ifc \3,w
op\5smd \2,d0_off+2(a7),d0_off+2(a7),\3
.else
op\5smd \2,d0_off(a7),d0_off(a7),\3
.endif
.endif
ii_0x\1\41:
.ifc \3,b
op\5smd \2,d1_off+3(a7),d1_off+3(a7),\3
.else
.ifc \3,w
op\5smd \2,d1_off+2(a7),d1_off+2(a7),\3
.else
op\5smd \2,d1_off(a7),d1_off(a7),\3
.endif
.endif
ii_0x\1\42:
op\5smd \2,d2,d2,\3
ii_0x\1\43:
op\5smd \2,d3,d3,\3
ii_0x\1\44:
op\5smd \2,d4,d4,\3
ii_0x\1\45:
op\5smd \2,d5,d5,\3
ii_0x\1\46:
op\5smd \2,d6,d6,\3
ii_0x\1\47:
op\5smd \2,d7,d7,\3
.endm
//-----------------------------------------------------
opcsmd:.macro // dx: 1=opieration 2=ea src 3=ea dest 4=size
#ifdef halten_opc
halt
#endif
.ifc \4,l
move.l (a0)+,d0
.else
.ifc \4,w
mvs.w (a0)+,d0
.else
move.w (a0)+,d0
extb.l d0
.endif
.endif
.ifc \4,l
move.l \2,d1
.else
mvs.\4 \2,d1
.endif
.ifc \1,eor.l d0
move.l d0_off(a7),d1
.endif
.ifc \1,eor.l d1
move.l d1_off(a7),d1
.endif
\1 d1
set_cc0
move.\4 d1,\3
ii_end
.endm;
opacsmd:.macro // ax: 1=opieration 2=ea src 3=ea dest 4=size
#ifdef halten_opc
halt
#endif
.ifc \4,l
move.l (a0)+,d0
.else
.ifc \4,w
mvs.w (a0)+,d0
.else
move.w (a0)+,d0
extb.l d0
.endif
.endif
.ifc \2,usp
move.l usp,a1
move.l a1,d1
.else
move.l \2,d1
.endif
\1 d1
set_cc0
.ifc \3,usp
move.l d1,a1
move.l a1,usp
.else
move.l d1,\3
.endif
ii_end
.endm;
opcsia:.macro // (ax) (ax)+ -(ax): 1=opieration 2=adress register 3= src 4=dest 5=size
#ifdef halten_opc
halt
#endif
.ifc \4,l
move.l (a0)+,d0
.else
.ifc \4,w
mvs.w (a0)+,d0
.else
move.w (a0)+,d0
extb.l d0
.endif
.endif
move.l \2,a1
.ifc \5,l
move.l \3,d1
.else
mvs.\5 \3,d1
.endif
.ifc \1,eor.l d0
move.l d0_off(a7),d1
.endif
.ifc \1,eor.l d1
move.l d1_off(a7),d1
.endif
\1 d1
set_cc0
move.\5 d1,\4
ii_end
.endm;
opcsd16a:.macro // d16(ax): 1=opieration 2=adress register 3=size
#ifdef halten_opc
halt
#endif
.ifc \4,l
move.l (a0)+,d0
.else
.ifc \4,w
mvs.w (a0)+,d0
.else
move.w (a0)+,d0
extb.l d0
.endif
.endif
move.l \2,a1
mvs.w (a0)+,d1
add.l d1,a1
.ifc \3,l
move.l (a1),d1
.else
mvs.\3 (a1),d1
.endif
.ifc \1,eor.l d0
move.l d0_off(a7),d1
.endif
.ifc \1,eor.l d1
move.l d1_off(a7),d1
.endif
\1 d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
opcsd8a:.macro // indirect: 1=opieration 2=adress register 3=size
#ifdef halten_opc
halt
#endif
.ifc \4,l
move.l (a0)+,d0
.else
.ifc \4,w
mvs.w (a0)+,d0
.else
move.w (a0)+,d0
extb.l d0
.endif
.endif
move.l d0,_d0_save
move.l \2,a1
jsr ewf
move.l _d0_save,d0
.ifc \3,l
move.l (a1),d1
.else
mvs.\3 (a1),d1
.endif
.ifc \1,eor.l d0
move.l d0_off(a7),d1
.endif
.ifc \1,eor.l d1
move.l d1_off(a7),d1
.endif
\1 d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
opcsxx:.macro // indirect: 1=opieration 2=size 3=size adresse
#ifdef halten_opc
halt
#endif
.ifc \2,l
move.l (a0)+,d0
.else
.ifc \2,w
mvs.w (a0)+,d0
.else
move.w (a0)+,d0
extb.l d0
.endif
.endif
move.\3 (a0)+,a1
.ifc \2,l
move.l (a1),d1
.else
mvs.\2 (a1),d1
.endif
.ifc \1,eor.l d0
move.l d0_off(a7),d1
.endif
.ifc \1,eor.l d1
move.l d1_off(a7),d1
.endif
\1 d1
set_cc0
move.\2 d1,(a1)
ii_end
.endm;

442
sources/ii_or.h
View File

@@ -1,442 +0,0 @@
//--------------------------------------------------------------------
// or
//--------------------------------------------------------------------
/*****************************************************************************************/
//--------------------------------------------------------------------
// byt
//--------------------------------------------------------------------
//--------------------------------------------------------------------
// or.b #im,dx
//--------------------------------------------------------------------
orbir_macro:.macro
#ifdef halten_or
halt
#endif
move.w (a0)+,d0
extb.l d0
mvs.b \2,d1
or.l d0,d1
set_cc0
move.b d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // or ea,dx
//--------------------------------------------------------------------
ordd:.macro
#ifdef halten_or
halt
#endif
mvs.\3 \1,d0
mvs.\3 \2,d1
or.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // or ea(l)->dy(w),dx z.B. f<>r USP
//--------------------------------------------------------------------
orddd:.macro
#ifdef halten_or
halt
#endif
move.l \1,a1
mvs.\3 a1,d0
mvs.\3 \2,d1
or.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // or (ea)->dy,dx
//--------------------------------------------------------------------
ordda:.macro
#ifdef halten_or
halt
#endif
move.l \1,a1
mvs.\3 (a1),d0
mvs.\3 \2,d1
or.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // or ea->ay,(ay)+,dx
//--------------------------------------------------------------------
orddai:.macro
#ifdef halten_or
halt
#endif
move.l \1,a1
mvs.\3 (a1)+,d0
move.l a1,\1
mvs.\3 \2,d1
or.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // or ea->ay,-(ay),dx
//--------------------------------------------------------------------
orddad:.macro
#ifdef halten_or
halt
#endif
move.l \1,a1
mvs.\3 -(a1),d0
move.l a1,\1
mvs.\3 \2,d1
or.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // or d16(ay),dx
//--------------------------------------------------------------------
ord16ad:.macro
#ifdef halten_or
halt
#endif
move.l \1,a1
mvs.w (a0)+,d0
add.l d0,a1
mvs.\3 (a1),d0
mvs.\3 \2,d1
or.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // or d8(ay,dy),dx
//--------------------------------------------------------------------
ord8ad:.macro
#ifdef halten_or
halt
#endif
move.l \1,a1
jsr ewf
.ifc \3,l
move.l (a1),d0
move.l \2,d1
.else
mvs.\3 (a1),d0
mvs.\3 \2,d1
.endif
or.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // or xxx.w,dx
//--------------------------------------------------------------------
orxwd:.macro
#ifdef halten_or
halt
#endif
move.w (a0)+,a1
mvs.\3 (a1),d0
mvs.\3 \2,d1
or.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // or xxx.l,dx
//--------------------------------------------------------------------
orxld:.macro
#ifdef halten_or
halt
#endif
move.l (a0)+,a1
mvs.\3 (a1),d0
mvs.\3 \2,d1
or.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // or d16(pc),dx
//--------------------------------------------------------------------
ord16pcd:.macro
halt
move.l a0,a1
mvs.w (a0)+,d0
add.l d0,a1
mvs.\3 (a1),d0
mvs.\3 \2,d1
or.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // or d8(pc,dy),dx
//--------------------------------------------------------------------
ord8pcd:.macro
#ifdef halten_or
halt
#endif
move.l a0,a1
jsr ewf
.ifc \3,l
move.l (a1),d0
move.l \2,d1
.else
mvs.\3 (a1),d0
mvs.\3 \2,d1
.endif
or.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// or dy,ea
//--------------------------------------------------------------------
//--------------------------------------------------------------------
// // or (ea)->dy,dx
//--------------------------------------------------------------------
oreda:.macro
#ifdef halten_or
halt
#endif
mvs.\3 \1,d0
move.l \2,a1
mvs.\3 (a1),d1
or.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------
// // or dx,ea->ay,(ay)+
//--------------------------------------------------------------------
oredai:.macro
#ifdef halten_or
halt
#endif
mvs.\3 \1,d0
move.l \2,a1
mvs.\3 (a1),d1
or.l d0,d1
set_cc0
move.\3 d1,(a1)+
move.l a1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // or dx,ea->ay,(ay)+
//--------------------------------------------------------------------
oredaid:.macro
#ifdef halten_or
halt
#endif
mvs.\3 \1,d0
mvs.\3 \2,d1
or.l d0,d1
set_cc0
move.\3 d1,\2+
ii_end
.endm;
//--------------------------------------------------------------------
// // or dx,ea->ay,-(ay)
//--------------------------------------------------------------------
oredad:.macro
#ifdef halten_or
halt
#endif
mvs.\3 \1,d0
move.l \2,a1
mvs.\3 -(a1),d1
move.l a1,\2
or.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------
// // or dx,ea->ay,-(ay)
//--------------------------------------------------------------------
oredadd:.macro
#ifdef halten_or
halt
#endif
mvs.\3 \1,d0
mvs.\3 -\2,d1
or.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // or dx,d16(ay)
//--------------------------------------------------------------------
ore16ad:.macro
#ifdef halten_or
halt
#endif
mvs.\3 \1,d0
move.l \2,a1
mvs.w (a0)+,d1
add.l d1,a1
mvs.\3 (a1),d1
or.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------
// // or.w dx,d8(ay,dy)
//--------------------------------------------------------------------
ore8ad:.macro
#ifdef halten_or
halt
#endif
move.l \2,a1
jsr ewf
.ifc \3,l
move.l (a1),d1
move.l \1,d0
.else
mvs.\3 (a1),d1
mvs.\3 \1,d0
.endif
or.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------
// // or dx,xxx.w
//--------------------------------------------------------------------
orxwe:.macro
#ifdef halten_or
halt
#endif
mvs.\3 \1,d0
move.w (a0)+,a1
mvs.\3 (a1),d1
or.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------
// // or dx,xxx.l
//--------------------------------------------------------------------
orxle:.macro
#ifdef halten_or
halt
#endif
mvs.\3 \1,d0
move.l (a0)+,a1
mvs.\3 (a1),d1
or.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------
// // ora.w ea,ax
//--------------------------------------------------------------------
oraw:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// or.w ea,usp
//--------------------------------------------------------------------
orawa7:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// // ora.w usp?,ax
//--------------------------------------------------------------------
orawu:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// // ora.w usp?,usp
//--------------------------------------------------------------------
orawua7:.macro
orawu \1,\2
.endm;
//--------------------------------------------------------------------
// // ora.w d16(ay),ax
//--------------------------------------------------------------------
orawd16a:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// // ora.w d8(ay,dy),ax
//--------------------------------------------------------------------
orawd8a:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// // ora.w xxx.w,ax
//--------------------------------------------------------------------
orawxwax:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// // ora.w xxx.l,ax
//--------------------------------------------------------------------
orawxlax:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// // ora.w d16(pc),ax
//--------------------------------------------------------------------
orawd16pcax:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// // ora.w d8(pc,dy),ax
//--------------------------------------------------------------------
orawd8pcax:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// // ora.w #im,ax
//--------------------------------------------------------------------
orawim:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// // ora.l d8(ay,dy),ax
//--------------------------------------------------------------------
orald8a:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// // ora.l d8(pc,dy),ax
//--------------------------------------------------------------------
orald8pcax:.macro
jmp ii_error
.endm;
//*****************************************************************************************
// spezial addx subx etc.
//--------------------------------------------------------------------
//--------------------------------------------------------------------
// // addx dy,dx
//--------------------------------------------------------------------
ordx:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------
// // addx -(ay),-(ax)
//--------------------------------------------------------------------
ordax:.macro
jmp ii_error
.endm;
//--------------------------------------------------------------------

74
sources/ii_pea.h
View File

@@ -1,74 +0,0 @@
//--------------------------------------------------------------------
// pea
//--------------------------------------------------------------------
.text
ii_pea_lset:.macro
ii_lset_opeag 48,7
ii_lset 0x487b
.endm
//---------------------------------------------------------------------------------------------
ii_pea_func:.macro
ii_0x4870:
#ifdef halten_pea
halt
#endif
move.l a0_off(a7),a1
pea_macro
ii_0x4871:
#ifdef halten_pea
halt
#endif
move.l a1_off(a7),a1
pea_macro
ii_0x4872:
#ifdef halten_pea
halt
#endif
move.l a2,a1
pea_macro
ii_0x4873:
#ifdef halten_pea
halt
#endif
move.l a3,a1
pea_macro
ii_0x4874:
#ifdef halten_pea
halt
#endif
move.l a4,a1
pea_macro
ii_0x4875:
#ifdef halten_pea
halt
#endif
move.l a5,a1
pea_macro
ii_0x4876:
#ifdef halten_pea
halt
#endif
move.l a6,a1
pea_macro
ii_0x4877:
#ifdef halten_pea
halt
#endif
move.l usp,a1
pea_macro
ii_0x487b:
#ifdef halten_pea
halt
#endif
move.l a0,a1
pea_macro
.endm
//---------------------------------------------------------------------------------------------
pea_macro:.macro
jsr ewf
move.l (a1),d0
move.l usp,a1
move.l d0,-(a1)
move.l a1,usp
ii_end
.endm

247
sources/ii_shd.h
View File

@@ -1,247 +0,0 @@
/*****************************************************************************************/
// opertionen
/*****************************************************************************************/
ii_lset_shd:.macro
ii_lset_shdx e0 //r d0
ii_lset_shdx e2 //r d1
ii_lset_shdx e4 //r d2
ii_lset_shdx e6 //r d3
ii_lset_shdx e8 //r d4
ii_lset_shdx ea //r d5
ii_lset_shdx ec //r d6
ii_lset_shdx ee //r d7
ii_lset_shdx e1 //l d0
ii_lset_shdx e3 //l d1
ii_lset_shdx e4 //l d2
ii_lset_shdx e5 //l d3
ii_lset_shdx e9 //l d4
ii_lset_shdx eb //l d5
ii_lset_shdx ed //l d6
ii_lset_shdx ef //l d7
.endm
ii_lset_shdx:.macro
//byt
ii_lset_opea \1,0 // as,ls #im,dx
ii_lset_opea \1,1 // rox,ro #im,dx
ii_lset_opea \1,2 // as,ls dy,dx
ii_lset_opea \1,3 // rox,ro dy,dx
//word
ii_lset_opea \1,4 // as,ls #im,dx
ii_lset_opea \1,5 // rox,ro #im,dx
ii_lset_opea \1,6 // as,ls dy,dx
ii_lset_opea \1,7 // rox,ro dy,dx
//long
// ii_lset_opea \1,8 // as,ls #im,dx -> vorhanden
ii_lset_opea \1,9 // rox,ro #im,dx
// ii_lset_opea \1,a // as,ls dy,dx -> vorhanden
ii_lset_opea \1,b // rox,ro dy,dx
.endm
/******************************************************/
ii_shd:.macro // 1=code 2=operation 3 = normal, direct oder immediat
// byt
opdx \1,\2,b,0,\3 // dx
// word
opdx \1,\2,w,4,\3 // dx
// long
opdx \1,\2,l,8,\3 // dx
.endm
/******************************************************/
// byt word long routinen
/******************************************************/
sh_asr: .macro // asr -> 1=operation 2 = dx 3 = dy/im 4 = size b/w
mvs.\4 \2,d1
sh_shal \1,\2,\3,\4
.endm
sh_lsr: .macro // asl -> 1=operation 2 = dx 3 = dy/im 4 = size b/w
mvz.\4 \2,d1
sh_shal \1,\2,\3,\4
.endm
sh_shal:.macro
move.w \3,d0
\1.l d0,d1
set_cc0
move.\4 d1,\2
.endm
sh_all: .macro // asl/lsl -> 1=operation 2 = dx 3 = dy/im 4 = size b/w
mvz.\4 \2,d1
.ifc \4,b
byterev.l d1
.else
swap.w d1
.endif
sh_asr \1,\2,\3,\4
.endm
sh_ror: .macro // ror -> 1=operation 2 = dx 3 = dy/im 4 = size b/w/l
move.\4 \2,d1 /
move.w \3,d0
.ifc \4,b
lsl.l #8,d1
move.b \2,d1
and.l #0x7,d0
lsr.l d0,d1
.else
.ifc \4,w
swap.w d1
move.w \2,d1
and.l #0xf,d0
lsr.l d0,d1
.else
and.l #0x1f,d0
lsr.l d0,d1
move.l d1,a1
move.l \2,d1
sub.l #32,d0
neg.l d0
lsl.l d0,d1
add.l a1,d1
.endif
.endif
move.\4 d1,\2
move.w ccr,d0
and.l #1,d1 // ist auch carry bit
or.l d1,d0
move.b d0,ccr_off(a7)
.endm
sh_rol: .macro // rol -> 1=operation 2 = dx 3 = dy/im 4 = size b/w/l
move.\4 \2,d1
move.w \3,d0
.ifc \4,b
lsl.l #8,d1
move.b \2,d1
and.l #0x7,d0
lsl.l d0,d1
lsr.l #8,d1
moveq #7,d0
.else
.ifc \4,w
swap.w d1
move.w \2,d1
and.l #0xf,d0
lsr.l d0,d1
swap.w d1
moveq #15,d0
.else
and.l #0x1f,d0
lsl.l d0,d1
move.l d1,a1
move.l \2,d1
sub.l #32,d0
neg.l d0
lsr.l d0,d1
add.l a1,d1
moveq #31,d0
.endif
.endif
move.\4 d1,\2
lsr.l d0,d1 // carry bit schieben
move.w ccr,d0
and.l #1,d1
or.l d1,d0
move.b d0,ccr_off(a7)
.endm
sh_roxr: .macro // roxr -> 1=operation 2 = dx 3 = dy/im 4 = size b/w/l
clr.l d0
addx.l d0,d0
ifc \4,b
mvz.b \2,d1
lsl.l #1,d1
add.l d0,d1
lsl.l #8,d1
move.b \2,d1
move.w \3,d0
and.l #0x7,d0
lsr.l d0,d1
set_cc0
else
.ifc \4,w
mvz.b \2,d1
lsl.l #1,d1
add.l d0,d1
lsl.l #8,d1
lsl.l #8,d1
move.w \2,d1
move.w \3,d0
and.l #0xf,d0
lsr.l d0,d1
set_cc0
.else
bitrev.l d0
move.l \2,d1
lsr.l #1,d1
add.l d0,d1
move.w \3,d0
subq.l #1,d0
and.l #0x1f,d0
lsr.l d0,d1
move.l d1,a1
set_cc1
move.l \2,d1
sub.l #32,d0
neg.l d0
lsl.l d0,d1
add.l a1,d1
.endif
.endif
move.\4 d1,\2
.endm
sh_roxl: .macro // roxl -> 1=operation 2 = dx 3 = dy/im 4 = size b/w/l
clr.l d0
addx.l d0,d0
ifc \4,b
mvz.b \2,d1
lsl.l #1,d1
add.l d0,d1
lsl.l #8,d1
move.b \2,d1
lsl.l #8,d1
lsl.l #7,d1
move.w \3,d0
and.l #0x7,d0
lsl.l d0,d1
set_cc0
byterev.l d1
else
.ifc \4,w
mvz.b \2,d1
lsl.l #1,d1
add.l d0,d1
lsl.l #8,d1
lsl.l #7,d1
mvz.w \2,d0
lsr.l #1,d0
add.l d0,d1
move.w \3,d0
and.l #0xf,d0
lsl.l d0,d1
set_cc0
swap.w d1
.else
move.l \2,d1
lsl.l #1,d1
add.l d0,d1
move.w \3,d0
subq.l #1,d0
and.l #0x1f,d0
lsl.l d0,d1
move.l d1,a1
set_cc1
move.l \2,d1
sub.l #32,d0
neg.l d0
lsr.l d0,d1
add.l a1,d1
.endif
.endif
move.\4 d1,\2
.endm

687
sources/ii_shift.h
View File

@@ -1,687 +0,0 @@
/*****************************************************************************************/
// opertionen
/*****************************************************************************************/
ii_shift_lset:.macro
/******************************************************/
// byt
/******************************************************/
// asx.b #,dx
ii_lset_dx \1,00 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c
ii_lset_dx \1,01
ii_lset_dx \1,02
ii_lset_dx \1,03
ii_lset_dx \1,04
ii_lset_dx \1,05
ii_lset_dx \1,06
ii_lset_dx \1,07
// lsx.b #,dx
ii_lset_dxu \1,08
ii_lset_dxu \1,09
ii_lset_dxu \1,0a
ii_lset_dxu \1,0b
ii_lset_dxu \1,0c
ii_lset_dxu \1,0d
ii_lset_dxu \1,0e
ii_lset_dxu \1,0f
// roxx.b #,dx
ii_lset_dx \1,10
ii_lset_dx \1,11
ii_lset_dx \1,12
ii_lset_dx \1,13
ii_lset_dx \1,14
ii_lset_dx \1,15
ii_lset_dx \1,16
ii_lset_dx \1,17
// rox.b #,dx
ii_lset_dx \1,18
ii_lset_dx \1,19
ii_lset_dx \1,1a
ii_lset_dx \1,1b
ii_lset_dx \1,1c
ii_lset_dx \1,1d
ii_lset_dx \1,1e
ii_lset_dx \1,1f
// asx.b dy,dx
ii_lset_dx \1,20
ii_lset_dx \1,21
ii_lset_dx \1,22
ii_lset_dx \1,23
ii_lset_dx \1,24
ii_lset_dx \1,25
ii_lset_dx \1,26
ii_lset_dx \1,27
// lsx.b dy,dx
ii_lset_dx \1,28
ii_lset_dx \1,29
ii_lset_dx \1,2a
ii_lset_dx \1,2b
ii_lset_dx \1,2c
ii_lset_dx \1,2d
ii_lset_dx \1,2e
ii_lset_dx \1,2f
// roxx.dy,dx
ii_lset_dx \1,30
ii_lset_dx \1,31
ii_lset_dx \1,32
ii_lset_dx \1,33
ii_lset_dx \1,34
ii_lset_dx \1,35
ii_lset_dx \1,36
ii_lset_dx \1,37
// rox.b dy,dx
ii_lset_dx \1,38
ii_lset_dx \1,39
ii_lset_dx \1,3a
ii_lset_dx \1,3b
ii_lset_dx \1,3c
ii_lset_dx \1,3d
ii_lset_dx \1,3e
ii_lset_dx \1,3f
/******************************************************/
// word
/******************************************************/
// asx.w #x,dx
ii_lset_dx \1,40 // 0x1.22 -> z.B. 1=d2=4 ->0xd07c -> 0xde7c
ii_lset_dx \1,41
ii_lset_dx \1,42
ii_lset_dx \1,43
ii_lset_dx \1,44
ii_lset_dx \1,45
ii_lset_dx \1,46
ii_lset_dx \1,47
// lsx.w #,dx
ii_lset_dx \1,48
ii_lset_dx \1,49
ii_lset_dx \1,4a
ii_lset_dx \1,4b
ii_lset_dx \1,4c
ii_lset_dx \1,4d
ii_lset_dx \1,4e
ii_lset_dx \1,4f
// roxx.w #,dx
ii_lset_dx \1,50
ii_lset_dx \1,51
ii_lset_dx \1,52
ii_lset_dx \1,53
ii_lset_dx \1,54
ii_lset_dx \1,55
ii_lset_dx \1,56
ii_lset_dx \1,57
// rox.w #xdx
ii_lset_dx \1,58
ii_lset_dx \1,59
ii_lset_dx \1,5a
ii_lset_dx \1,5b
ii_lset_dx \1,5c
ii_lset_dx \1,5d
ii_lset_dx \1,5e
ii_lset_dx \1,5f
// asx.w dy,dx
ii_lset_dx \1,60
ii_lset_dx \1,61
ii_lset_dx \1,62
ii_lset_dx \1,63
ii_lset_dx \1,64
ii_lset_dx \1,65
ii_lset_dx \1,66
ii_lset_dx \1,67
// lsx.w dy,dx
ii_lset_dx \1,68
ii_lset_dx \1,69
ii_lset_dx \1,6a
ii_lset_dx \1,6b
ii_lset_dx \1,6c
ii_lset_dx \1,6d
ii_lset_dx \1,6e
ii_lset_dx \1,6f
// roxx.w dy,dx
ii_lset_dx \1,70
ii_lset_dx \1,71
ii_lset_dx \1,72
ii_lset_dx \1,73
ii_lset_dx \1,74
ii_lset_dx \1,75
ii_lset_dx \1,76
ii_lset_dx \1,77
// rox.w dy,dx
ii_lset_dx \1,78
ii_lset_dx \1,79
ii_lset_dx \1,7a
ii_lset_dx \1,7b
ii_lset_dx \1,7c
ii_lset_dx \1,7d
ii_lset_dx \1,7e
ii_lset_dx \1,7f
/******************************************************/
// long
/******************************************************/
// roxx.l #,dx
ii_lset_dx \1,90
ii_lset_dx \1,91
ii_lset_dx \1,92
ii_lset_dx \1,93
ii_lset_dx \1,94
ii_lset_dx \1,95
ii_lset_dx \1,96
ii_lset_dx \1,97
// rox.l #xdx
ii_lset_dx \1,98
ii_lset_dx \1,99
ii_lset_dx \1,9a
ii_lset_dx \1,9b
ii_lset_dx \1,9c
ii_lset_dx \1,9d
ii_lset_dx \1,9e
ii_lset_dx \1,9f
// roxx.l dy,dx
ii_lset_dx \1,b0
ii_lset_dx \1,b1
ii_lset_dx \1,b2
ii_lset_dx \1,b3
ii_lset_dx \1,b4
ii_lset_dx \1,b5
ii_lset_dx \1,b6
ii_lset_dx \1,b7
// rox.l dy,dx
ii_lset_dx \1,b8
ii_lset_dx \1,b9
ii_lset_dx \1,ba
ii_lset_dx \1,bb
ii_lset_dx \1,bc
ii_lset_dx \1,bd
ii_lset_dx \1,be
ii_lset_dx \1,bf
//--------------------------------------------------------------------
// asr.w ea
ii_lset_opea \10,d // (ax), (ax)+
ii_lset_opea \10,e // -(ax),d16(ax)
ii_lset_opeag \10,f // d8(ax,dy)
lea table+0x\10\2f8*4,a0
move.l #ii_0x\10f8,(a0)+ // xxx.w
move.l #ii_0x\10f9,(a0)+ // xxx.l
// asl.w ea
ii_lset_opea \11,d // (ax), (ax)+
ii_lset_opea \11,e // -(ax),d16(ax)
ii_lset_opeag \11,f // d8(ax,dy)
lea table+0x\11\2f8*4,a0
move.l #ii_0x\11f8,(a0)+ // xxx.w
move.l #ii_0x\11f9,(a0)+ // xxx.l
// lsr.w ea
ii_lset_opea \12,d // (ax), (ax)+
ii_lset_opea \12,e // -(ax),d16(ax)
ii_lset_opeag \12,f // d8(ax,dy)
lea table+0x\12\2f8*4,a0
move.l #ii_0x\12f8,(a0)+ // xxx.w
move.l #ii_0x\12f9,(a0)+ // xxx.l
// lsr.w ea
ii_lset_opea \13,d // (ax), (ax)+
ii_lset_opea \13,e // -(ax),d16(ax)
ii_lset_opeag \13,f // d8(ax,dy)
lea table+0x\13\2f8*4,a0
move.l #ii_0x\13f8,(a0)+ // xxx.w
move.l #ii_0x\13f9,(a0)+ // xxx.l
// roxr.w ea
ii_lset_opea \14,d // (ax), (ax)+
ii_lset_opea \14,e // -(ax),d16(ax)
ii_lset_opeag \14,f // d8(ax,dy)
lea table+0x\14\2f8*4,a0
move.l #ii_0x\14f8,(a0)+ // xxx.w
move.l #ii_0x\14f9,(a0)+ // xxx.l
// roxl.w ea
ii_lset_opea \15,e // (ax), (ax)+
ii_lset_opea \15,e // -(ax),d16(ax)
ii_lset_opeag \15,f // d8(ax,dy)
lea table+0x\15\2f8*4,a0
move.l #ii_0x\15f8,(a0)+ // xxx.w
move.l #ii_0x\15f9,(a0)+ // xxx.l
// ror.w ea
ii_lset_opea \16,d // (ax), (ax)+
ii_lset_opea \16,e // -(ax),d16(ax)
ii_lset_opeag \16,f // d8(ax,dy)
lea table+0x\16\2f8*4,a0
move.l #ii_0x\16f8,(a0)+ // xxx.w
move.l #ii_0x\16f9,(a0)+ // xxx.l
// rol.w ea
ii_lset_opea \17,d // (ax), (ax)+
ii_lset_opea \17,e // -(ax),d16(ax)
ii_lset_opeag \17,f // d8(ax,dy)
lea table+0x\17\2f8*4,a0
move.l #ii_0x\17f8,(a0)+ // xxx.w
move.l #ii_0x\17f9,(a0)+ // xxx.l
// ende
.endm;
/******************************************************/
ii_shift_op:.macro // 1=code
//byt-------------------------------
//asx.b #x,dx
ii_shift_op2agb 0,as,a
//lsx.b #x,dx
ii_shift_op2aub 0,ls,a
//roxx.b #x,dx
ii_shift_op2agb 1,rox,a
//rox.b #x,dx
ii_shift_op2aub 1,ro,a
//asx.b dy,dx
ii_shift_op2agb 2,as,b
//lsx.b dy,dx
ii_shift_op2aub 2,ls,b
//roxx.b dy,dx
ii_shift_op2agb 3,rox,b
//rox.b dy,dx
ii_shift_op2aub 3,ro,b
// word ---------------------------------------
//asx.w #x,dx
ii_shift_op2agw 4,as,a
//lsx.w #x,dx
ii_shift_op2auw 4,ls,a
//roxx.w #x,dx
ii_shift_op2agw 5,rox,a
//rox.w #x,dx
ii_shift_op2auw 5,ro,a
//asx.w dy,dx
ii_shift_op2agw 6,as,b
//lsx.w dy,dx
ii_shift_op2auw 6,ls,b
//roxx.w dy,dx
ii_shift_op2agw 7,rox,b
//rox.w dy,dx
ii_shift_op2auw 7,ro,b
// long ---------------------------------------
//roxx.l #x,dx
ii_shift_op2agw 9,rox,a
//rox.l #x,dx
ii_shift_op2auw 9,ro,a
//roxx.l dy,dx
ii_shift_op2agw b,rox,b
//rox.l dy,dx
ii_shift_op2auw b,ro,b
// ea ---------------------------------------
//asr.w #1,ea
ii_shift_op2ea 0,asr
//asl.w #1,ea
ii_shift_op2ea 1,asl
//lsr.w #1,ea
ii_shift_op2ea 2,lsr,
//lsl.w #1,ea
ii_shift_op2ea 3,lsl
//roxr.w #1,ea
ii_shift_op2ea 4,roxr
//roxl.w #1,ea
ii_shift_op2ea 5,roxl
//ror.w #1,ea
ii_shift_op2ea 6,ror
//rol.w #1,ea
ii_shift_op2ea 7,rol
.endm
//byt ============================================
ii_shift_op2agb:.macro //byt: 1=code 2=operation 3=quick(a) oder register(b)
ii_shift_op1\3b \1,0,\2,d0_off+3(a7)
ii_shift_op1\3b \1,1,\2,d1_off+3(a7)
ii_shift_op1\3b \1,2,\2,d2
ii_shift_op1\3b \1,3,\2,d3
ii_shift_op1\3b \1,4,\2,d4
ii_shift_op1\3b \1,5,\2,d5
ii_shift_op1\3b \1,6,\2,d6
ii_shift_op1\3b \1,7,\2,d7
.endm
ii_shift_op2aub:.macro //byt: 1=code 2=operation
ii_shift_op1\3b \1,8,\2,d0_off+3(a7)
ii_shift_op1\3b \1,9,\2,d1_off+3(a7)
ii_shift_op1\3b \1,a,\2,d2
ii_shift_op1\3b \1,b,\2,d3
ii_shift_op1\3b \1,c,\2,d4
ii_shift_op1\3b \1,d,\2,d5
ii_shift_op1\3b \1,e,\2,d6
ii_shift_op1\3b \1,f,\2,d7
.endm
ii_shift_op1ab:.macro // z.B. asr.w. #x,dx 1=code 3.ziffer 2=code 4.ziffer 3=shift art 4=dx
ii_shift_op0 0\1\2,b,\3r,#8,\4
ii_shift_op0 2\1\2,b,\3r,#1,\4
ii_shift_op0 4\1\2,b,\3r,#2,\4
ii_shift_op0 6\1\2,b,\3r,#3,\4
ii_shift_op0 8\1\2,b,\3r,#4,\4
ii_shift_op0 a\1\2,b,\3r,#5,\4
ii_shift_op0 c\1\2,b,\3r,#6,\4
ii_shift_op0 e\1\2,b,\3r,#7,\4
ii_shift_op0 1\1\2,b,\3l,#8,\4
ii_shift_op0 3\1\2,b,\3l,#1,\4
ii_shift_op0 5\1\2,b,\3l,#2,\4
ii_shift_op0 7\1\2,b,\3l,#3,\4
ii_shift_op0 9\1\2,b,\3l,#4,\4
ii_shift_op0 b\1\2,b,\3l,#5,\4
ii_shift_op0 d\1\2,b,\3l,#6,\4
ii_shift_op0 f\1\2,b,\3l,#7,\4
.endm
ii_shift_op1bb:.macro // z.B. asr.w. #x,dx 1=code 3.ziffer 2=code 4.ziffer 3=shift art 4=dx
ii_shift_op0b 0\1\2,b,\3r,d0_off(a7),\4
ii_shift_op0b 2\1\2,b,\3r,d1_off(a7),\4
ii_shift_op0 4\1\2,b,\3r,d2,\4
ii_shift_op0 6\1\2,b,\3r,d3,\4
ii_shift_op0 8\1\2,b,\3r,d4,\4
ii_shift_op0 a\1\2,b,\3r,d5,\4
ii_shift_op0 c\1\2,b,\3r,d6,\4
ii_shift_op0 e\1\2,b,\3r,d7,\4
ii_shift_op0b 1\1\2,b,\3l,d0_off(a7),\4
ii_shift_op0b 3\1\2,b,\3l,d1_off(a7),\4
ii_shift_op0 5\1\2,b,\3l,d2,\4
ii_shift_op0 7\1\2,b,\3l,d3,\4
ii_shift_op0 9\1\2,b,\3l,d4,\4
ii_shift_op0 b\1\2,b,\3l,d5,\4
ii_shift_op0 d\1\2,b,\3l,d6,\4
ii_shift_op0 f\1\2,b,\3l,d7,\4
.endm
// word ---------------------------------------
ii_shift_op2agw:.macro //byt: 1=code 2=operation 3=quick(a) oder register(b)
ii_shift_op1\3w \1,0,\2,d0_off+2(a7)
ii_shift_op1\3w \1,1,\2,d1_off+2(a7)
ii_shift_op1\3w \1,2,\2,d2
ii_shift_op1\3w \1,3,\2,d3
ii_shift_op1\3w \1,4,\2,d4
ii_shift_op1\3w \1,5,\2,d5
ii_shift_op1\3w \1,6,\2,d6
ii_shift_op1\3w \1,7,\2,d7
.endm
ii_shift_op2auw:.macro //byt: 1=code 2=operation
ii_shift_op1\3w \1,8,\2,d0_off+2(a7)
ii_shift_op1\3w \1,9,\2,d1_off+2(a7)
ii_shift_op1\3w \1,a,\2,d2
ii_shift_op1\3w \1,b,\2,d3
ii_shift_op1\3w \1,c,\2,d4
ii_shift_op1\3w \1,d,\2,d5
ii_shift_op1\3w \1,e,\2,d6
ii_shift_op1\3w \1,f,\2,d7
.endm
ii_shift_op1aw:.macro // z.B. asr.w. #x,dx 1=code 3.ziffer 2=code 4.ziffer 3=shift art 4=dx
ii_shift_op0 0\1\2,w,\3r,#8,\4
ii_shift_op0 2\1\2,w,\3r,#1,\4
ii_shift_op0 4\1\2,w,\3r,#2,\4
ii_shift_op0 6\1\2,w,\3r,#3,\4
ii_shift_op0 8\1\2,w,\3r,#4,\4
ii_shift_op0 a\1\2,w,\3r,#5,\4
ii_shift_op0 c\1\2,w,\3r,#6,\4
ii_shift_op0 e\1\2,w,\3r,#7,\4
ii_shift_op0 1\1\2,w,\3l,#8,\4
ii_shift_op0 3\1\2,w,\3l,#1,\4
ii_shift_op0 5\1\2,w,\3l,#2,\4
ii_shift_op0 7\1\2,w,\3l,#3,\4
ii_shift_op0 9\1\2,w,\3l,#4,\4
ii_shift_op0 b\1\2,w,\3l,#5,\4
ii_shift_op0 d\1\2,w,\3l,#6,\4
ii_shift_op0 f\1\2,w,\3l,#7,\4
.endm
ii_shift_op1bw:.macro // z.B. asr.w. #x,dx 1=code 3.ziffer 2=code 4.ziffer 3=shift art 4=dx
ii_shift_op0b 0\1\2,w,\3r,d0_off(a7),\4
ii_shift_op0b 2\1\2,w,\3r,d1_off(a7),\4
ii_shift_op0 4\1\2,w,\3r,d2,\4
ii_shift_op0 6\1\2,w,\3r,d3,\4
ii_shift_op0 8\1\2,w,\3r,d4,\4
ii_shift_op0 a\1\2,w,\3r,d5,\4
ii_shift_op0 c\1\2,w,\3r,d6,\4
ii_shift_op0 e\1\2,w,\3r,d7,\4
ii_shift_op0b 1\1\2,w,\3l,d0_off(a7),\4
ii_shift_op0b 3\1\2,w,\3l,d1_off(a7),\4
ii_shift_op0 5\1\2,w,\3l,d2,\4
ii_shift_op0 7\1\2,w,\3l,d3,\4
ii_shift_op0 9\1\2,w,\3l,d4,\4
ii_shift_op0 b\1\2,w,\3l,d5,\4
ii_shift_op0 d\1\2,w,\3l,d6,\4
ii_shift_op0 f\1\2,w,\3l,d7,\4
.endm
// long ---------------------------------------
ii_shift_op2agl:.macro //byt: 1=code 2=operation 3=quick(a) oder register(b)
ii_shift_op1\3l \1,0,\2,d0_off(a7)
ii_shift_op1\3l \1,1,\2,d1_off(a7)
ii_shift_op1\3l \1,2,\2,d2
ii_shift_op1\3l \1,3,\2,d3
ii_shift_op1\3l \1,4,\2,d4
ii_shift_op1\3l \1,5,\2,d5
ii_shift_op1\3l \1,6,\2,d6
ii_shift_op1\3l \1,7,\2,d7
.endm
ii_shift_op2aul:.macro //byt: 1=code 2=operation
ii_shift_op1\3l \1,8,\2,d0_off(a7)
ii_shift_op1\3l \1,9,\2,d1_off(a7)
ii_shift_op1\3l \1,a,\2,d2
ii_shift_op1\3l \1,b,\2,d3
ii_shift_op1\3l \1,c,\2,d4
ii_shift_op1\3l \1,d,\2,d5
ii_shift_op1\3l \1,e,\2,d6
ii_shift_op1\3l \1,f,\2,d7
.endm
ii_shift_op1al:.macro // z.B. asr.w. #x,dx 1=code 3.ziffer 2=code 4.ziffer 3=shift art 4=dx
ii_shift_op0 0\1\2,l,\3r,#8,\4
ii_shift_op0 2\1\2,l,\3r,#1,\4
ii_shift_op0 4\1\2,l,\3r,#2,\4
ii_shift_op0 6\1\2,l,\3r,#3,\4
ii_shift_op0 8\1\2,l,\3r,#4,\4
ii_shift_op0 a\1\2,l,\3r,#5,\4
ii_shift_op0 c\1\2,l,\3r,#6,\4
ii_shift_op0 e\1\2,l,\3r,#7,\4
ii_shift_op0 1\1\2,l,\3l,#8,\4
ii_shift_op0 3\1\2,l,\3l,#1,\4
ii_shift_op0 5\1\2,l,\3l,#2,\4
ii_shift_op0 7\1\2,l,\3l,#3,\4
ii_shift_op0 9\1\2,l,\3l,#4,\4
ii_shift_op0 b\1\2,l,\3l,#5,\4
ii_shift_op0 d\1\2,l,\3l,#6,\4
ii_shift_op0 f\1\2,l,\3l,#7,\4
.endm
ii_shift_op1bl:.macro // z.B. asr.w. #x,dx 1=code 3.ziffer 2=code 4.ziffer 3=shift art 4=dx
ii_shift_op0b 0\1\2,l,\3r,d0_off(a7),\4
ii_shift_op0b 2\1\2,l,\3r,d1_off(a7),\4
ii_shift_op0 4\1\2,l,\3r,d2,\4
ii_shift_op0 6\1\2,l,\3r,d3,\4
ii_shift_op0 8\1\2,l,\3r,d4,\4
ii_shift_op0 a\1\2,l,\3r,d5,\4
ii_shift_op0 c\1\2,l,\3r,d6,\4
ii_shift_op0 e\1\2,l,\3r,d7,\4
ii_shift_op0b 1\1\2,l,\3l,d0_off(a7),\4
ii_shift_op0b 3\1\2,l,\3l,d1_off(a7),\4
ii_shift_op0 5\1\2,l,\3l,d2,\4
ii_shift_op0 7\1\2,l,\3l,d3,\4
ii_shift_op0 9\1\2,l,\3l,d4,\4
ii_shift_op0 b\1\2,l,\3l,d5,\4
ii_shift_op0 d\1\2,l,\3l,d6,\4
ii_shift_op0 f\1\2,l,\3l,d7,\4
.endm
// .word ea ============================================
ii_shift_op2ea:.macro //1=code 2.ziffer 2=shiftart
// (a0) bis (a7) ----------------------------
ii_0xe\1d0:
move.l a0_off(a7),a1
ii_shift_typ w,\2,#1,(a1),(a1).
ii_0xe\1d1:
move.l a1_off(a7),a1
ii_shift_typ w,\2,#1,(a1),(a1).
ii_0xe\1d2:
ii_shift_typ w,\2,#1,(a2),(a2).
ii_0xe\1d3:
ii_shift_typ w,\2,#1,(a3),(a3).
ii_0xe\1d4:
ii_shift_typ w,\2,#1,(a4),(a4).
ii_0xe\1d5:
ii_shift_typ w,\2,#1,(a5),(a5).
ii_0xe\1d6:
ii_shift_typ w,\2,#1,(a6),(a6).
ii_0xe\1d7:
move.l usp,a1
ii_shift_typ w,\2,#1,(a1),(a1).
// (a0)+ bis (a7)+ -----------------------------
ii_0xe\1d8:
move.l a0_off(a7),a1
addq.l #2,a0_off(a7)
ii_shift_typ w,\2,#1,(a1),(a1).
ii_0xe\1d9:
move.l a1_off(a7),a1
addq.l #2,a0_off(a7)
ii_shift_typ w,\2,#1,(a1),(a1).
ii_0xe\1da:
ii_shift_typ w,\2,#1,(a2),(a2)+.
ii_0xe\1db:
ii_shift_typ w,\2,#1,(a3),(a3)+
ii_0xe\1dc:
ii_shift_typ w,\2,#1,(a4),(a4)+
ii_0xe\1dd:
ii_shift_typ w,\2,#1,(a5),(a5)+
ii_0xe\1de:
ii_shift_typ w,\2,#1,(a6),(a6)+
ii_0xe\1df:
move.l usp,a1
addq.l #2,a1
move.l a1,usp
subq.l #2,a1
ii_shift_typ w,\2,#1,(a1),(a1).
// -(a0) bis -(a7) -----------------------------
ii_0xe\1e0:
move.l a0_off(a7),a1
subq.l #2,a1
move.l a1,a0_off(a7)
ii_shift_typ w,\2,#1,(a1),(a1).
ii_0xe\1e1:
move.l a1_off(a7),a1
subq.l #2,a1
move.l a1,a1_off(a7)
ii_shift_typ w,\2,#1,(a1),(a1).
ii_0xe\1e2:
ii_shift_typ w,\2,#1,-(a2),(a2).
ii_0xe\1e3:
ii_shift_typ w,\2,#1,-(a3),(a3)
ii_0xe\1e4:
ii_shift_typ w,\2,#1,-(a4),(a4)
ii_0xe\1e5:
ii_shift_typ w,\2,#1,-(a5),(a5)
ii_0xe\1e6:
ii_shift_typ w,\2,#1,-(a6),(a6)
ii_0xe\1e7:
move.l usp,a1
subq.l #2,a1
move.l a1,usp
ii_shift_typ w,\2,#1,(a1),(a1).
// d16(a0) bis d16(a7) -----------------------------
ii_0xe\1e8:
move.w (a0)+,a1
add.l a0_off(a7),a1
ii_shift_typ w,\2,#1,(a1),(a1).
ii_0xe\1e9:
move.w (a0)+,a1
add.l a1_off(a7),a1
ii_shift_typ w,\2,#1,(a1),(a1).
ii_0xe\1ea:
move.w (a0)+,a1
add.l a2,a1
ii_shift_typ w,\2,#1,(a1),(a1).
ii_0xe\1eb:
move.w (a0)+,a1
add.l a3,a1
ii_shift_typ w,\2,#1,(a1),(a1)
ii_0xe\1ec:
move.w (a0)+,a1
add.l a4,a1
ii_shift_typ w,\2,#1,(a1),(a1)
ii_0xe\1ed:
move.w (a0)+,a1
add.l a5,a1
ii_shift_typ w,\2,#1,(a1),(a1)
ii_0xe\1ee:
move.w (a0)+,a1
add.l a6,a1
ii_shift_typ w,\2,#1,(a1),(a1)
ii_0xe\1ef:
mvs.w (a0)+,d0
move.l usp,a1
add.l d0,a1
ii_shift_typ w,\2,#1,(a1),(a1).
// d8(a0,dy) bis d8(a7,dy) -----------------------------
ii_0xe\1f0:
move.l a0_off(a0),a1
jsr ewf
ii_shift_typ w,\2,#1,(a1),(a1).
ii_0xe\1f1:
move.l a1_off(a0),a1
jsr ewf
ii_shift_typ w,\2,#1,(a1),(a1).
ii_0xe\1f2:
move.l a2,a1
jsr ewf
ii_shift_typ w,\2,#1,(a1),(a1).
ii_0xe\1f3:
move.l a3,a1
jsr ewf
ii_shift_typ w,\2,#1,(a1),(a1).
ii_0xe\1f4:
move.l a4,a1
jsr ewf
ii_shift_typ w,\2,#1,(a1),(a1).
ii_0xe\1f5:
move.l a5,a1
jsr ewf
ii_shift_typ w,\2,#1,(a1),(a1).
ii_0xe\1f6:
move.l a6,a1
jsr ewf
ii_shift_typ w,\2,#1,(a1),(a1).
ii_0xe\1f7:
move.l usp,a1
jsr ewf
ii_shift_typ w,\2,#1,(a1),(a1).
// xxx.w xxx.l
ii_0xe\1f8:
move.w (a0)+,a1
ii_shift_typ w,\2,#1,(a1),(a1).
ii_0xe\1f9:
move.l (a0)+,a1
ii_shift_typ w,\2,#1,(a1),(a1).
.endm
//============================================================================
//subroutine
//------------------------------
ii_shift_op0:.macro // shift: 1=code 2=size 3=shift art 4=shift wert 5=ea
ii_0xe\1:
ii_shift_typ \2,\3,\4,\5,\5
.endm
ii_shift_op0b:.macro // shift wert nach d0 holen: 1=code 2=size 3=shift art 4=shift wert 5=ea
ii_0xe\1:
move.l \4,d0
ii_shift_typ \2,\3,d0,\5,\5
.endm
ii_shift_typ:.macro //1=size 2=shift art 3=shift wert 4=source 5=dest
#ifdef halten
halt
#endif
.ifc asr,\2
mvs.\1 \4,d1
.else
mvz.\1 \4,d1
.endif
.ifc roxr,\2
nop
.else
.ifc roxl,\2
nop
.else
.ifc ror,\2
nop
.else
.ifc rol,\2
nop
.else
\2.l \3,d1
.endif
.endif
.endif
.endif
set_cc0
move.\1 d1,\5
ii_end
.endm

584
sources/ii_sub.h
View File

@@ -1,584 +0,0 @@
//--------------------------------------------------------------------
// sub
//--------------------------------------------------------------------
/*****************************************************************************************/
//--------------------------------------------------------------------
// byt
//--------------------------------------------------------------------
//--------------------------------------------------------------------
// sub.b #im,dx
//--------------------------------------------------------------------
subbir_macro:.macro
#ifdef halten_sub
halt
#endif
move.w (a0)+,d0
extb.l d0
mvs.b \2,d1
sub.l d0,d1
set_cc0
move.b d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // sub ea,dx
//--------------------------------------------------------------------
subdd:.macro
#ifdef halten_sub
halt
#endif
mvs.\3 \1,d0
mvs.\3 \2,d1
sub.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // sub ea(l)->dy(w),dx z.B. f<>r USP
//--------------------------------------------------------------------
subddd:.macro
#ifdef halten_sub
halt
#endif
move.l \1,a1
mvs.\3 a1,d0
mvs.\3 \2,d1
sub.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // sub (ea)->dy,dx
//--------------------------------------------------------------------
subdda:.macro
#ifdef halten_sub
halt
#endif
move.l \1,a1
mvs.\3 (a1),d0
mvs.\3 \2,d1
sub.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // sub ea->ay,(ay)+,dx
//--------------------------------------------------------------------
subddai:.macro
#ifdef halten_sub
halt
#endif
move.l \1,a1
mvs.\3 (a1)+,d0
move.l a1,\1
mvs.\3 \2,d1
sub.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // sub ea->ay,-(ay),dx
//--------------------------------------------------------------------
subddad:.macro
#ifdef halten_sub
halt
#endif
move.l \1,a1
mvs.\3 -(a1),d0
move.l a1,\1
mvs.\3 \2,d1
sub.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // sub d16(ay),dx
//--------------------------------------------------------------------
subd16ad:.macro
#ifdef halten_sub
halt
#endif
move.l \1,a1
mvs.w (a0)+,d0
add.l d0,a1
mvs.\3 (a1),d0
mvs.\3 \2,d1
sub.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // sub d8(ay,dy),dx
//--------------------------------------------------------------------
subd8ad:.macro
#ifdef halten_sub
halt
#endif
move.l \1,a1
jsr ewf
.ifc \3,l
move.l (a1),d0
move.l \2,d1
.else
mvs.\3 (a1),d0
mvs.\3 \2,d1
.endif
sub.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // sub xxx.w,dx
//--------------------------------------------------------------------
subxwd:.macro
#ifdef halten_sub
halt
#endif
move.w (a0)+,a1
mvs.\3 (a1),d0
mvs.\3 \2,d1
sub.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // sub xxx.l,dx
//--------------------------------------------------------------------
subxld:.macro
#ifdef halten_sub
halt
#endif
move.l (a0)+,a1
mvs.\3 (a1),d0
mvs.\3 \2,d1
sub.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // sub d16(pc),dx
//--------------------------------------------------------------------
subd16pcd:.macro
#ifdef halten_sub
halt
#endif
move.l a0,a1
mvs.w (a0)+,d0
add.l d0,a1
mvs.\3 (a1),d0
mvs.\3 \2,d1
sub.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // sub d8(pc,dy),dx
//--------------------------------------------------------------------
subd8pcd:.macro
#ifdef halten_sub
halt
#endif
move.l a0,a1
jsr ewf
.ifc \3,l
move.l (a1),d0
move.l \2,d1
.else
mvs.\3 (a1),d0
mvs.\3 \2,d1
.endif
sub.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// sub dy,ea
//--------------------------------------------------------------------
//--------------------------------------------------------------------
// // sub (ea)->dy,dx
//--------------------------------------------------------------------
subeda:.macro
#ifdef halten_sub
halt
#endif
mvs.\3 \1,d0
move.l \2,a1
mvs.\3 (a1),d1
sub.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------
// // sub dx,ea->ay,(ay)+
//--------------------------------------------------------------------
subedai:.macro
#ifdef halten_sub
halt
#endif
mvs.\3 \1,d0
move.l \2,a1
mvs.\3 (a1),d1
sub.l d0,d1
set_cc0
move.\3 d1,(a1)+
move.l a1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // sub dx,ea->ay,(ay)+
//--------------------------------------------------------------------
subedaid:.macro
#ifdef halten_sub
halt
#endif
mvs.\3 \1,d0
mvs.\3 \2,d1
sub.l d0,d1
set_cc0
move.\3 d1,\2+
ii_end
.endm;
//--------------------------------------------------------------------
// // sub dx,ea->ay,-(ay)
//--------------------------------------------------------------------
subedad:.macro
#ifdef halten_sub
halt
#endif
mvs.\3 \1,d0
move.l \2,a1
mvs.\3 -(a1),d1
move.l a1,\2
sub.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------
// // sub dx,ea->ay,-(ay)
//--------------------------------------------------------------------
subedadd:.macro
#ifdef halten_sub
halt
#endif
mvs.\3 \1,d0
mvs.\3 -\2,d1
sub.l d0,d1
set_cc0
move.\3 d1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // sub dx,d16(ay)
//--------------------------------------------------------------------
sube16ad:.macro
#ifdef halten_sub
halt
#endif
mvs.\3 \1,d0
move.l \2,a1
mvs.w (a0)+,d1
add.l d1,a1
mvs.\3 (a1),d1
sub.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------
// // sub dx,d8(ay,dy)
//--------------------------------------------------------------------
sube8ad:.macro
#ifdef halten_sub
halt
#endif
move.l \2,a1
jsr ewf
.ifc \3,l
move.l (a1),d1
move.l \1,d0
.else
mvs.\3 (a1),d1
mvs.\3 \1,d0
.endif
sub.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------
// // sub dx,xxx.w
//--------------------------------------------------------------------
subxwe:.macro
#ifdef halten_sub
halt
#endif
mvs.\3 \1,d0
move.w (a0)+,a1
mvs.\3 (a1),d1
sub.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------
// // sub dx,xxx.l
//--------------------------------------------------------------------
subxle:.macro
#ifdef halten_sub
halt
#endif
mvs.\3 \1,d0
move.l (a0)+,a1
mvs.\3 (a1),d1
sub.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
/******************************************************/
// adress register
/******************************************************/
//--------------------------------------------------------------------
// // suba.w ea,ax
//--------------------------------------------------------------------
subaw:.macro
#ifdef halten_sub
halt
#endif
move.l a0,pc_off(a7) // pc auf next
movem.l (a7),d0/d1/a0/a1 // register zurp<72>ck
mvs.w \1,d0
suba.l d0,\2
move.l d0_off(a7),d0
lea ii_ss(a7),a7 // stack erh<72>hen
rte
.endm;
//--------------------------------------------------------------------
// sub.w ea,usp
//--------------------------------------------------------------------
subawa7:.macro
#ifdef halten_sub
halt
#endif
mvs.w \1,d0
move.l usp,a1
sub.l d0,a1
move.l a1,usp
ii_end
.endm;
//--------------------------------------------------------------------
// // suba.w usp?,ax
//--------------------------------------------------------------------
subawu:.macro
#ifdef halten_sub
halt
#endif
move.l a0,pc_off(a7) // pc auf next
movem.l (a7),d0/d1/a0/a1 // register zurp<72>ck
move.l a7,_a7_save
move.l usp,a7
move.l \1,d0
suba.l d0,\2
move.l a7,usp
move.l _a7_save,a7
move.l d0_off(a7),d0
lea ii_ss(a7),a7 // stack erh<72>hen
rte
.endm;
//--------------------------------------------------------------------
// // suba.w usp?,usp
//--------------------------------------------------------------------
subawua7:.macro
subawu \1,\2
.endm;
//--------------------------------------------------------------------
// // suba.w d16(ay),ax
//--------------------------------------------------------------------
subawd16a:.macro
#ifdef halten_sub
halt
#endif
move.l \1,a1
mvs.w (a0)+,d0
adda.l d0,a1
mvs.w (a1),d0
move.l \2,a1
sub.l d0,a1
move.l a1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // suba.w d8(ay,dy),ax
//--------------------------------------------------------------------
subawd8a:.macro
#ifdef halten_sub
halt
#endif
move.l \1,a1
jsr ewf
mvs.w (a1),d0
move.l \2,a1
sub.l d0,a1
move.l a1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // suba.w xxx.w,ax
//--------------------------------------------------------------------
subawxwax:.macro
#ifdef halten_sub
halt
#endif
move.w (a0)+,a1
mvs.w (a1),d0
move.l \2,a1
suba.l d0,a1
move.l a1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // suba.w xxx.l,ax
//--------------------------------------------------------------------
subawxlax:.macro
#ifdef halten_sub
halt
#endif
move.l (a0)+,a1
mvs.w (a1),d0
move.l \2,a1
suba.l d0,a1
move.l a1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // suba.w d16(pc),ax
//--------------------------------------------------------------------
subawd16pcax:.macro
#ifdef halten_sub
halt
#endif
move.w (a0)+,a1
adda.l a0,a1
mvs.w (a1),d0
move.l \2,a1
suba.l d0,a1
move.l a1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // suba.w d8(pc,dy),ax
//--------------------------------------------------------------------
subawd8pcax:.macro
#ifdef halten_sub
halt
#endif
move.l a0,a1
jsr ewf
mvs.w (a1),d0
move.l \2,a1
sub.l d0,a1
move.l a1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // suba.w #im,ax
//--------------------------------------------------------------------
subawim:.macro
#ifdef halten_sub
halt
#endif
mvs.w \1,d0
move.l \2,a1
sub.l d0,a1
move.l a1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // suba.l d8(ay,dy),ax
//--------------------------------------------------------------------
subald8a:.macro
#ifdef halten_sub
halt
#endif
move.l \1,a1
jsr ewf
move.l (a1),d0
move.l \2,a1
sub.l d0,a1
move.l a1,\2
ii_end
.endm;
//--------------------------------------------------------------------
// // suba.l d8(pc,dy),ax
//--------------------------------------------------------------------
subakd8pcax:.macro
#ifdef halten_sub
halt
#endif
move.l a0,a1
jsr ewf
move.l (a1),d0
move.l \2,a1
sub.l d0,a1
move.l a1,\2
ii_end
.endm;
//*****************************************************************************************
// subx
//*****************************************************************************************
//--------------------------------------------------------------------
// // subx dy,dx
//--------------------------------------------------------------------
subdx:.macro
#ifdef halten_sub
halt
#endif
move.b sr_off+1(a7),d0 //ccr holen
move d0,ccr //setzen
mvs.\3 \2,d0
mvs.\3 \1,d1
subx.l d0,d1
set_cc0
move.\3 d1,\1
ii_end
.endm;
//--------------------------------------------------------------------
// // subx -(ay),-(ax)
//--------------------------------------------------------------------
subdax:.macro
#ifdef halten_sub
halt
#endif
move.b sr_off+1(a7),d0 //ccr holen
move d0,ccr //setzen
move.l \1,a1
.ifc \3,l
move.l -(a1),d0
.else
mvs.\3 -(a1),d0
.endif
move.l \2,a1
.ifc \3,l
move.l -(a1),d0
.else
mvs.\3 -(a1),d1
.endif
subx.l d0,d1
set_cc0
move.\3 d1,(a1)
ii_end
.endm;
//--------------------------------------------------------------------

3
sources/illegal_instruction.s
View File

@@ -1,7 +1,9 @@
.public _illegal_instruction
.public _illegal_table_make
.include "startcf.h"
#ifdef ii_on
.include "ii_macro.h"
.include "ii_func.h"
.include "ii_op.h"
@@ -19,6 +21,7 @@
.include "ii_movep.h"
.include "ii_ewf.h"
.include "ii_move.h"
#endif
.extern _ii_shift_vec
.extern ewf

11
sources/last.c
View File

@@ -1,11 +0,0 @@
// letztes file der liste
// wichtig als endpunkt des kopierens
void copy_end(void)
{
asm
{
copy_end:
nop
}
}

10
sources/last.s
View File

@@ -1,10 +0,0 @@
// letztes file der liste
// wichtig als endpunkt des kopierens
.global copy_end
.text
nop
copy_end:
nop
.asciz 'ende copy';

10
sources/macro.h
View File

@@ -1,10 +0,0 @@
/*******************************************************/
// allgemeine macros
/*******************************************************/
.text
wait_pll: .macro
wait1_pll\@:
tst.w (a1)
bmi wait1_pll\@
rts
.endm

256
sources/movem.h
View File

@@ -1,256 +0,0 @@
// movem
_ii_movem_lset: .macro
// movem rx,xxx.L
ii_lset 0x48f9
// movem rx,-(ax)
// movem (ax)+,rx
ii_lset 0x4cd8
ii_lset 0x4cd9
ii_lset 0x4cda
ii_lset 0x4cdb
ii_lset 0x4cdc
ii_lset 0x4cdd
ii_lset 0x4cde
ii_lset 0x4cdf
// movem xxx.L,rx
ii_lset 0x4cf9
.endm
//***********************************************************************************/
_ii_movem_func: .macro
//-------------------------------------------------------------------
// movem.l
//--------------------------------------------------------------------
// movem.l (ax)+,reg
//--------------------------------------------------------------------
//-------------------------------------------------------------------------------
ii_0x4cd8: // movem.l (a0)+,reglist
mvm_macro 0x4cd0,0x41e8,2
ii_0x4cd9: // movem.l (a1)+,reglist
mvm_macro 0x4cd1,0x43e9,2
ii_0x4cda: // movem.l (a2)+,reglist
mvm_macro 0x4cd2,0x45ea,2
ii_0x4cdb: // movem.l (a3)+,reglist
mvm_macro 0x4cd3,0x47eb,2
ii_0x4cdc: // movem.l (a4)+,reglist
mvm_macro 0x4cd4,0x49ec,2
ii_0x4cdd: // movem.l (a5)+,reglist
mvm_macro 0x4cd5,0x4bed,2
ii_0x4cde: // movem.l (a6)+,reglist
mvm_macro 0x4cd6,0x4dee,2
ii_0x4cdf: // movem.l (a7)+,reglist
mvm_macro 0x4cd7,0x4fef,2
//----------------------------------------------------------------------------
ii_0x48f9: // movem.l reg,xxx.L
move.w (a0)+,d0
move.l (a0)+,a1
movemrm_macro
ii_end
//---------------------------------------------------------------------------------------------
ii_0x4cf9: // movem.l xxx.L,reg
move.w (a0)+,d0
move.l (a0)+,a1
movemmr_macro
ii_end
.endm
//==============================================================
mvm_macro:.macro
halt
lea az_reg_table,a1
mvz.b (a0),d1
mvz.b 0(a1,d1)+,d0
mvz.b 1(a0),d1
mvz.b 0(a1,d1)+,d1
add.l d0,d1
lea ___RAMBAR1,a1
move.l a1,pc_off(a7)
move.l a1,d0
addq.l #1,d0
movec d0,RAMBAR1
move.w #\1,(a1)+ // movem.x (ax),reg_list
move.w (a0)+,(a1)+ // register list
move.w #\2,(a1)+ // lea 0(ax),ax
lsl.l #\3,d1 // * anzahl byts pro wert
move.w d1,(a1)+ // offset von lea
move.w #0x4ef9,(a1)+ // jmp.l
move.l a0,(a1) // r<>cksprungadresse
move.l #___RAMBAR1 + 0x81,d0 // instruction
movec d0,RAMBAR1
movem.l (a7),d0/d1/a0/a1
lea ii_ss(a7),a7 // stack erh<72>hen
rte
.endm
.long 0
az_reg_table:
.byte 0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4 // 0-f
.byte 1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5 // 10-1f
.byte 1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5 // 20-2f
.byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // 30-3f
.byte 1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5 // 40-4f
.byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // 50
.byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // 60
.byte 3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7 // 70
.byte 1,2,2,3,2,3,3,4,2,3,3,4,3,4,4,5 // 80-8f
.byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // 90
.byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // a0
.byte 3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7 // b0
.byte 2,3,3,4,3,4,4,5,3,4,4,5,4,5,5,6 // c0
.byte 3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7 // d0
.byte 3,4,4,5,4,5,5,6,4,5,5,6,5,6,6,7 // e0
.byte 4,5,5,6,5,6,6,7,5,6,6,7,6,7,7,8 // f0
//---------------------------------------------------------------------------------
movemrm_macro:.macro // in d0 register liste, in a1 zieladresse
halt
tst.b d0 // datenregister zu verschieben?
bne mrm_dx // ja->
lsr.l #8,d0 // sonst zu addressregister
jmp mmrm_nd7 // ->
mrm_dx:
lsr.l #1,d0
bcc mmrm_nd0
move.l d0_off(a7),(a1)+
mmrm_nd0:
lsr.l #1,d0
bcc mmrm_nd1
move.l d1_off(a7),(a1)+
mmrm_nd1:
lsr.l #1,d0
bcc mmrm_nd2
move.l d2,(a1)+
mmrm_nd2:
lsr.l #1,d0
bcc mmrm_nd3
move.l d3,(a1)+
mmrm_nd3:
lsr.l #1,d0
bcc mmrm_nd4
move.l d4,(a1)+
mmrm_nd4:
lsr.l #1,d0
bcc mmrm_nd5
move.l d5,(a1)+
mmrm_nd5:
lsr.l #1,d0
bcc mmrm_nd6
move.l d6,(a1)+
mmrm_nd6:
lsr.l #1,d0
bcc mmrm_nd7
move.l d7,(a1)+
mmrm_nd7:
tst.b d0 // addressregister zu verschieben?
beq mmrm_na7
lsr.l #1,d0
bcc mmrm_na0
move.l a0_off(a7),(a1)+
mmrm_na0:
lsr.l #1,d0
bcc mmrm_na1
move.l a1_off(a7),(a1)+
mmrm_na1:
lsr.l #1,d0
bcc mmrm_na2
move.l a2,(a1)+
mmrm_na2:
lsr.l #1,d0
bcc mmrm_na3
move.l a3,(a1)+
mmrm_na3:
lsr.l #1,d0
bcc mmrm_na4
move.l a4,(a1)+
mmrm_na4:
lsr.l #1,d0
bcc mmrm_na5
move.l a5,(a1)+
mmrm_na5:
lsr.l #1,d0
bcc mmrm_na6
move.l a6,(a1)+
mmrm_na6:
lsr.l #1,d0
bcc mmrm_na7
move.l a0,d1 // sichern
move.l usp,a0 // ist ja usp
move.l a0,(a1)+ // nach a0
move.l d1,a0 // pc zur<75>ck
mmrm_na7:
.endm
//---------------------------------------------------------------------------------------------
movemmr_macro:.macro // in d0 register liste, in a1 source adr
halt
tst.b d0 // datenregister zu verschieben?
bne mmr_dx // ja->
lsr.l #8,d0 // sonst zu addressregister
bra mmmr_nd7 // ->
mmr_dx:
lsr.l #1,d0
bcc mmmr_nd0
move.l (a1)+,d0_off(a7)
mmmr_nd0:
lsr.l #1,d0
bcc mmmr_nd1
move.l (a1)+,d1_off(a7)
mmmr_nd1:
lsr.l #1,d0
bcc mmmr_nd2
move.l (a1)+,d2
mmmr_nd2:
lsr.l #1,d0
bcc mmmr_nd3
move.l (a1)+,d3
mmmr_nd3:
lsr.l #1,d0
bcc mmmr_nd4
move.l (a1)+,d4
mmmr_nd4:
lsr.l #1,d0
bcc mmmr_nd5
move.l (a1)+,d5
mmmr_nd5:
lsr.l #1,d0
bcc mmmr_nd6
move.l (a1)+,d6
mmmr_nd6:
lsr.l #1,d0
bcc mmmr_nd7
move.l (a1)+,d7
mmmr_nd7:
tst.b d0 // addressregister zu verschieben?
beq mmmr_na7 // nein->
lsr.l #1,d0
bcc mmmr_na0
move.l (a1)+,a0_off(a7)
mmmr_na0:
lsr.l #1,d0
bcc mmmr_na1
move.l (a1)+,a1_off(a7)
mmmr_na1:
lsr.l #1,d0
bcc mmmr_na2
move.l (a1)+,a2
mmmr_na2:
lsr.l #1,d0
bcc mmmr_na3
move.l (a1)+,a3
mmmr_na3:
lsr.l #1,d0
bcc mmmr_na4
move.l (a1)+,a4
mmmr_na4:
lsr.l #1,d0
bcc mmmr_na5
move.l (a1)+,a5
mmmr_na5:
lsr.l #1,d0
bcc mmmr_na6
move.l (a1)+,a6
mmmr_na6:
lsr.l #1,d0
bcc mmmr_na7
move.l a0,d1 // sichern
move.l (a1)+,a0 // nach a0
move.l a0,usp // war ja usp
move.l d1,a0 // pc zur<75>ck
mmmr_na7:
.endm

22
sources/sd_card.c
View File

@@ -5,7 +5,7 @@
#define __MBAR 0xff000000
#define MCF_SLT0_SCNT __MBAR + 0x908
#define MCF_PSC0_PSCTB_8BIT __MBAR + 0x860C
#define MCF_PAD_PAR_DSPI __MBAR + 0xA50
#define MCF_PAD_PAR_DSPI __MBAR + 0xa30
#define MCF_DSPI_DMCR __MBAR + 0x8A00 //dspi control
#define dspi_dtar0 0x0c
@@ -115,7 +115,7 @@ int sd_card_init(void)
move.l #'SD-C',(a1)
move.l #'ard ',(a1)
move.l buffer,a5 // basis addresse (diesen bereich brauchen wir nicht mehr!)
move.l buffer,a3 // basis addresse (diesen bereich brauchen wir nicht mehr!)
move.l #0x1fffffff,d0 // normal dspi
move.l d0,MCF_PAD_PAR_DSPI
lea MCF_DSPI_DMCR,a0
@@ -301,11 +301,11 @@ read_cid:
move.b #0x95,d4
bsr sd_com
move.l a5,a2 // adresse setzen
move.l a3,a2 // adresse setzen
bsr sd_rcv_info
// name ausgeben
lea 1(a5),a2
lea 1(a3),a2
moveq #7,d7
sd_nam_loop:
move.b (a2)+,(a1)
@@ -330,19 +330,19 @@ read_csd:
move.b #0x01,d4
bsr sd_com
move.l a5,a2 // adresse setzen
move.l a3,a2 // adresse setzen
bsr sd_rcv_info
mvz.b (a5),d0
mvz.b (a3),d0
lsr.l #6,d0
bne sd_csd2 // format v2
move.l 6(a5),d1
move.l 6(a3),d1
moveq #14,d0 // bit 73..62 c_size
lsr.l d0,d1 // bits extrahieren
and.l #0xfff,d1 // 12 bits
addq.l #1,d1
mvz.w 9(a5),d0
mvz.w 9(a3),d0
lsr.l #7,d0 // bits 49..47
and.l #0x7,d0 // 3 bits
moveq.l #8,d2 // x256 (dif v1 v2)
@@ -350,7 +350,7 @@ read_csd:
lsr.l d2,d1
bra sd_print_size
sd_csd2:
mvz.w 8(a5),d1
mvz.w 8(a3),d1
addq.l #1,d1
sd_print_size:
swap d1
@@ -468,7 +468,7 @@ sd_rs_end:
int sd_card_sector_read(long sec_nr,long buf_adr)
{
int status ;
int status=0 ;
asm
{
lea MCF_DSPI_DMCR,a0
@@ -554,7 +554,7 @@ sd_send_end:
int sd_card_sector_write(long sec_nr,long buf_adr)
{
int status;
int status=0;
asm
{
lea MCF_DSPI_DMCR,a0

406
sources/sd_card.s
View File

@@ -1,406 +0,0 @@
/********************************************************************/
// sd card
/********************************************************************/
#define dspi_dtar0 0x0c
#define dspi_dsr 0x2c
#define dspi_dtfr 0x34
#define dspi_drfr 0x38
.text
sd_test:
lea MCF_PSC0_PSCTB_8BIT,a6
move.l #'SD-C',(a6)
move.l #'ard ',(a6)
move.l #__Bas_base,a5 // basis addresse (diesen bereich brauchen wir nicht mehr!)
move.l #0x1fffffff,d0 // normal dspi
move.l d0,MCF_PAD_PAR_DSPI
lea MCF_DSPI_DMCR,a0
move.l #0x800d3c00,(a0) // 8 bit cs5 on
move.l #0x38558897,d0
move.l d0,dspi_dtar0(a0) // 400kHz
move.l #0x082000ff,d4 // tx vorbesetzen
mov3q.l #-1,dspi_dsr(a0)
bsr warte_1ms
move.l #0xc00d3c00,(a0) // 8 bit 4MHz clocken cs off
bsr warte_10ms
move.l #0x800d3c00,(a0) // 8 bit 4MHz normal cs on
bsr sd_com
bsr sd_com
bsr sd_com
bsr sd_com
bsr sd_com
bsr sd_com
bsr sd_com
bsr sd_com
bsr sd_com
bsr sd_com
move.l #0x802d3c00,(a0) // 8 bit 4MHz normal cs off
clr.b d4
bsr sd_com
bsr sd_com
move.l #0x800d3c00,(a0) // 8 bit 4MHz normal cs on
move.b #0xff,d4
bsr sd_com
bsr sd_com
move.l #0x802d3c00,(a0) // 8 bit 4MHz normal cs off
bsr warte_10ms
// sd idle
move.l #100,d6 // 100 versuche
move.l #10,d3 // 10 versuche
sd_idle:
move.b #0xff,d4 // receive byt
bsr sd_com
move.b #0x40,d4
bsr sd_com
move.b #00,d4
bsr sd_com
move.b #00,d4
bsr sd_com
move.b #00,d4
bsr sd_com
move.b #00,d4
bsr sd_com
move.b #0x95,d4
bsr sd_com
move.b #0xff,d4 // receive byt
bsr sd_com
cmp.b #0x01,d5
beq idle_end
bsr sd_com
cmp.b #0x01,d5
beq idle_end
bsr sd_com
cmp.b #0x01,d5
beq idle_end
bsr sd_com
cmp.b #0x01,d5
beq idle_end
bsr sd_com
cmp.b #0x01,d5
beq idle_end
bsr sd_com
cmp.b #0x01,d5
beq idle_end
subq.l #1,d6
beq sd_not
bra sd_idle
idle_end:
// cdm 8
read_ic:
move.b #0xff,d4 // receive byt
bsr sd_com
move.b #0x48,d4
bsr sd_com
move.b #00,d4
bsr sd_com
move.b #00,d4
bsr sd_com
move.b #0x01,d4
bsr sd_com
move.b #0xaa,d4
bsr sd_com
move.b #0x87,d4
bsr sd_com
bsr sd_get_status
cmp.b #5,d5
beq sd_v1
cmp.b #1,d5
bne read_ic
move.b #0xff,d4
bsr sd_com
move.b d5,d0
bsr sd_com
move.b d5,d1
bsr sd_com
move.b d5,d2
bsr sd_com
cmp.b #0xaa,d5
bne sd_testd3
move.l #'SDHC',(a6)
move.b #' ',(a6)
sd_v1:
// cdm 58
read_ocr:
move.b #0xff,d4 // receive byt
bsr sd_com
move.b #0x7a,d4
bsr sd_com
move.b #00,d4
bsr sd_com
move.b #00,d4
bsr sd_com
move.b #0x00,d4
bsr sd_com
move.b #0x00,d4
bsr sd_com
move.b #0x01,d4
bsr sd_com
bsr sd_get_status
move.l #'Ver1',d6
cmp.b #5,d5
beq read_ocr
cmp.b #1,d5
bne read_ocr
move.b #0xff,d4
bsr sd_com
move.b d5,d0
bsr sd_com
move.b d5,d1
bsr sd_com
move.b d5,d2
bsr sd_com
// acdm 41
move.l #20000,d6 // 20000 versuche ready can bis 1 sec gehen
wait_of_aktiv:
move.b #0xff,d4 // receive byt
bsr sd_com
move.b #0x77,d4
bsr sd_com
move.b #00,d4
bsr sd_com
move.b #00,d4
bsr sd_com
move.b #00,d4
bsr sd_com
move.b #00,d4
bsr sd_com
move.b #0x95,d4
bsr sd_com
bsr sd_get_status
cmp.b #0x05,d5
beq wait_of_aktiv
wait_of_aktiv2:
move.b #0xff,d4 // receive byt
bsr sd_com
move.b #0x69,d4
bsr sd_com
move.b #0x40,d4
bsr sd_com
move.b #0x00,d4
bsr sd_com
move.b #0x00,d4
bsr sd_com
move.b #0x00,d4
bsr sd_com
move.b #0x95,d4
bsr sd_com
bsr sd_get_status
tst.b d5
beq sd_init_ok
cmp.b #0x05,d5
beq wait_of_aktiv2
subq.l #1,d6
bne wait_of_aktiv
sd_testd3:
subq.l #1,d3
bne sd_idle
bra sd_error
sd_init_ok:
// cdm 10
read_cid:
move.b #0xff,d4 // receive byt
bsr sd_com
move.b #0x4a,d4
bsr sd_com
move.b #00,d4
bsr sd_com
move.b #00,d4
bsr sd_com
move.b #0x00,d4
bsr sd_com
move.b #0x00,d4
bsr sd_com
move.b #0x95,d4
bsr sd_com
move.l a5,a4 // adresse setzen
bsr sd_rcv_info
// name ausgeben
lea 1(a5),a4
moveq #7,d7
sd_nam_loop:
move.b (a4)+,(a6)
subq.l #1,d7
bne sd_nam_loop
move.b #' ',(a6)
// cdm 9
read_csd:
move.b #0xff,d4 // receive byt
bsr sd_com
move.b #0x49,d4
bsr sd_com
move.b #00,d4
bsr sd_com
move.b #00,d4
bsr sd_com
move.b #0x00,d4
bsr sd_com
move.b #0x00,d4
bsr sd_com
move.b #0x01,d4
bsr sd_com
move.l a5,a4 // adresse setzen
bsr sd_rcv_info
mvz.b (a5),d0
lsr.l #6,d0
bne sd_csd2 // format v2
move.l 6(a5),d1
moveq #14,d0 // bit 73..62 c_size
lsr.l d0,d1 // bits extrahieren
and.l #0xfff,d1 // 12 bits
addq.l #1,d1
mvz.w 9(a5),d0
lsr.l #7,d0 // bits 49..47
and.l #0x7,d0 // 3 bits
moveq.l #8,d2 // x256 (dif v1 v2)
sub.l d0,d2
lsr.l d2,d1
bra sd_print_size
sd_csd2:
mvz.w 8(a5),d1
addq.l #1,d1
sd_print_size:
swap d1
lsl.l #1,d1
bcc sd_16G
move.l #'32GB',(a6)
bra sd_ok
sd_16G:
lsl.l #1,d1
bcc sd_8G
move.l #'16GB',(a6)
bra sd_ok
sd_8G:
lsl.l #1,d1
bcc sd_4G
move.l #' 8GB',(a6)
bra sd_ok
sd_4G:
lsl.l #1,d1
bcc sd_2G
move.l #' 4GB',(a6)
bra sd_ok
sd_2G:
lsl.l #1,d1
bcc sd_1G
move.l #' 2GB',(a6)
bra sd_ok
sd_1G:
lsl.l #1,d1
bcc sd_512M
move.l #' 1GB',(a6)
bra sd_ok
sd_512M:
lsl.l #1,d1
bcc sd_256M
move.b #'5',(a6)
move.l #'12MB',(a6)
bra sd_ok
sd_256M:
lsl.l #1,d1
bcc sd_128M
move.b #'2',(a6)
move.l #'56MB',(a6)
bra sd_ok
sd_128M:
lsl.l #1,d1
bcc sd_64M
move.b #'1',(a6)
move.l #'28MB',(a6)
bra sd_ok
sd_64M:
lsl.l #1,d1
bcc sd_32M
move.l #'64MB',(a6)
bra sd_ok
sd_32M:
lsl.l #1,d1
bcc sd_16M
move.l #'32MB',(a6)
bra sd_ok
sd_16M:
lsl.l #1,d1
bcc sd_8M
move.l #'16MB',(a6)
bra sd_ok
sd_8M:
move.l #'<9MB',(a6)
sd_ok:
move.l #' OK!',(a6)
move.l #0x0a0d,(a6)
halt
halt
rts
// subs ende -------------------------------
sd_V1:
move.l #'non!',(a6)
move.l #0x0a0d,(a6)
halt
halt
rts
sd_error:
move.l #'Erro',(a6)
move.l #'r!',(a6)
move.l #0x0a0d,(a6)
halt
halt
rts
sd_not:
move.l #'non!',(a6)
move.l #0x0a0d,(a6)
halt
halt
rts
// status holen -------------------------------
sd_get_status:
move.b #0xff,d4
bsr sd_com
cmp.b #0xff,d5
beq sd_get_status
rts
// byt senden und holen ---------------------
sd_com:
move.l d4,dspi_dtfr(a0)
wait_auf_complett:
btst.b #7,dspi_dsr(a0)
beq wait_auf_complett
move.l dspi_drfr(a0),d5
mov3q.l #-1,dspi_dsr(a0) // clr status register
rts
// daten holen ----------------------------
sd_rcv_info:
moveq #18,d3 // 16 byts + 2 byts crc
move.b #0xff,d4
sd_rcv_rb_w:
bsr sd_get_status
cmp.b #0xfe,d5 // daten bereit?
bne sd_rcv_rb_w // nein->
sd_rcv_rd_rb:
bsr sd_com
move.b d5,(a4)+
subq.l #1,d3
bne sd_rcv_rd_rb
rts
/******************************************/

458
sources/sd_ide.s
View File

@@ -1,458 +0,0 @@
//.include "startcf.h"
//.extern ___MBAR
//#define MCF_SLT0_SCNT ___MBAR+0x908
//.global ide_test
.text
/*
sd_test:
clr.w MCF_PAD_PAR_DSPI
lea MCF_GPIO_PPDSDR_DSPI,a2 // data in
lea MCF_GPIO_PODR_DSPI,a1 // data out
move.b #0x00,(a1) // alle auf 0
lea MCF_GPIO_PDDR_DSPI,a0
move.b #0x7d,(a0) // din = input rest output
bsr warten_20ms
move.b #0x7f,(a1) // alle auf 1
bsr sd_16clk
bsr sd_16clk
bsr sd_16clk
bsr sd_16clk
bsr sd_16clk
bsr sd_16clk
bsr sd_16clk
bsr sd_16clk
// sd idle
sd_idle:
bsr sd_16clk
moveq #0x40,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #0x95,d4
bsr sd_com
bsr sd_receive
cmp.b #0x05,d5
beq sd_test
cmp.b #0x01,d5
beq wait_of_aktiv
cmp.b #0x04,d5
beq sd_init_ok
cmp.b #0x00,d5
beq sd_init_ok
bra sd_idle
// acdm 41
wait_of_aktiv:
bsr sd_16clk
moveq #0x77,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #0x01,d4
bsr sd_com
bsr sd_receive
bsr sd_16clk
move.l #0xff,d6
moveq #0x69,d4
bsr sd_com
and d5,d6
moveq #00,d4
bsr sd_com
and d5,d6
moveq #00,d4
bsr sd_com
and d5,d6
moveq #0x02,d4
bsr sd_com
and d5,d6
moveq #00,d4
bsr sd_com
and d5,d6
moveq #0x01,d4
bsr sd_com
and d5,d6
bsr sd_receive
cmp.b #0x00,d5
beq sd_init_ok
cmp.b #0x05,d5
beq sd_test
bra wait_of_aktiv
sd_init_ok:
// blockgr<EFBFBD>sse 512byt
sd_bg:
bsr sd_16clk
moveq #0x50,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #02,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #0x01,d4
bsr sd_com
bsr sd_receive
cmp.b #0x00,d5
bne sd_bg
// read block
sd_rb:
bsr sd_16clk
moveq #0x51,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #0x08,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #0x01,d4
bsr sd_com
bsr sd_receive
cmp.b #0x00,d5
bne sd_rb
lea 0xc00000,a4
move.l #513,d7
rd_rb:
bsr sd_receive
move.b d5,(a4)+
subq.l #1,d7
bne rd_rb
// write block
sd_wb:
bsr sd_16clk
moveq #0x58,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #0x08,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #0x01,d4
bsr sd_com
bsr sd_receive
cmp.b #0x00,d5
bne sd_wb
lea 0xc00000,a4
move.l #513,d7
moveq.l #0x66,d4
wr_wb:
bsr sd_com
// subq.l #1,d4
moveq #0x66,d4
subq.l #1,d7
bne wr_wb
bsr sd_receive
wr_wb_el:
moveq #0xff,d4
bsr sd_com
cmp.b #0xff,d5
bne wr_wb_el
// read block 2
sd_rb2:
bsr sd_16clk
moveq #0x51,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #0x08,d4
bsr sd_com
moveq #00,d4
bsr sd_com
moveq #0x01,d4
bsr sd_com
bsr sd_receive
cmp.b #0x00,d5
bne sd_rb2
lea 0xc00400,a4
move.l #513,d7
rd_rb2:
bsr sd_receive
move.b d5,(a4)+
subq.l #1,d7
bne rd_rb2
nop
nop
rts
sd_receive:
moveq #0xff,d4
bsr sd_com
cmp.b #0xff,d5
beq sd_receive
rts
sd_com:
bclr.b #6,(a1)
sd_comb:
bsr warten_10us
moveq #7,d2
clr.l d5
sd_com_loop:
btst d2,d4
beq sd_com2
bset.b #0,(a1)
bra sd_com2_1
sd_com2:
bclr.b #0,(a1)
sd_com2_1:
bsr sd_clk
and.l #0x02,d3
beq sd_com3
bset.b d2,d5
sd_com3:
subq.l #1,d2
bge sd_com_loop
bsr warten_10us
bset.b #6,(a1)
bset.b #0,(a1)
bsr warten_200us
rts
sd_clk:
tst.b 0xfffff700
tst.b 0xfffff700
bset.b #2,(a1)
tst.b 0xfffff700
tst.b 0xfffff700
move.b (a2),d3
tst.b 0xfffff700
bclr.b #2,(a1)
rts
sd_15clk:
move #15,d0
bra sd_16clk
sd_16clk:
moveq #16,d0
sd_16clk1:
bsr sd_clk
subq.l #1,d0
bne sd_16clk1
bsr warten_10us
rts
// warteschleife ca. 20ms
warten_20ms:
move.l a0,-(sp)
move.l d6,-(sp)
move.l d1,-(sp)
move.l d0,-(sp)
lea MCF_SLT0_SCNT,a0
move.l (a0),d0
move.l #700000,d6
bra warten_loop
// warteschleife ca. 200us
warten_200us:
move.l a0,-(sp)
move.l d6,-(sp)
move.l d1,-(sp)
move.l d0,-(sp)
lea MCF_SLT0_SCNT,a0
move.l (a0),d0
move.l #7000,d6
bra warten_loop
// warteschleife ca. 10us
warten_10us:
move.l a0,-(sp)
move.l d6,-(sp)
move.l d1,-(sp)
move.l d0,-(sp)
lea MCF_SLT0_SCNT,a0
move.l (a0),d0
move.l #333,d6
warten_loop:
move.l (a0),d1
sub.l d0,d1
add.l d6,d1
bpl warten_loop
move.l (sp)+,d0
move.l (sp)+,d1
move.l (sp)+,d6
move.l (sp)+,a0
rts;
/********************************************************************/
#define cmd_reg (0x1d)
#define status_reg (0x1d)
#define seccnt (0x09)
ide_test:
lea 0xfff00040,a0
lea 0xc00000,a1
move.b #0xec,cmd_reg(a0) //identify devcie cmd
bsr wait_int
bsr ds_rx
// read sector normal
move.b #1,seccnt(a0) // 1 sector
move.b #0x20,cmd_reg(a0) // read cmd
bsr wait_int
bsr ds_rx
// write testpattern sector
move.b #1,seccnt(a0) // 1 sector
move.b #0x30,cmd_reg(a0) // write cmd
bsr drq_wait
// write pattern
move.l #256,d0
ide_test_loop3:
move.w #0xa55a,(a0)
subq.l #1,d0
bne ide_test_loop3
bsr wait_int
// read testpattern sector
move.b #1,seccnt(a0) // 1 sector
move.b #0x20,cmd_reg(a0) // read
bsr wait_int
bsr ds_rx
// sector restauriern
move.b #1,seccnt(a0) // 1 sector
move.b #0x30,cmd_reg(a0) // write
lea -0x400(a1),a1 // vorletzer
bsr drq_wait
bsr ds_tx
bsr wait_int
// fertig und zur<EFBFBD>ck
nop
rts
// wait auf int
wait_int:
move.b 0xfffffa01,d0
btst #5,d0
bne wait_int
move.b status_reg(a0),d0
rts
// wait auf drq
drq_wait:
move.b status_reg(a0),d0
btst #3,d0
beq drq_wait
rts
// 1 sector lesen word
ds_rx:
move.l #256,d0
ds_rx_loop:
move.w (a0),(a1)+
subq.l #1,d0
bne ds_rx_loop
rts
// 1 sector lesen long
ds_rxl:
move.l #128,d0
ds_rxl_loop:
move.l (a0),(a1)+
subq.l #1,d0
bne ds_rxl_loop
rts
// 1 sector schreiben word
ds_tx:
move.l #256,d0
ds_tx_loop:
move.w (a1)+,(a0)
subq.l #1,d0
bne ds_tx_loop
rts
// 1 sector schreiben word
ds_txl:
move.l #128,d0
ds_txl_loop:
move.l (a1)+,(a0)
subq.l #1,d0
bne ds_txl_loop
rts
// warteschleife ca. 20ms
warten_20ms:
move.l a0,-(sp)
move.l d6,-(sp)
move.l d1,-(sp)
move.l d0,-(sp)
lea MCF_SLT0_SCNT,a0
move.l (a0),d0
move.l #700000,d6
bra warten_loop
// warteschleife ca. 200us
warten_200us:
move.l a0,-(sp)
move.l d6,-(sp)
move.l d1,-(sp)
move.l d0,-(sp)
lea MCF_SLT0_SCNT,a0
move.l (a0),d0
move.l #7000,d6
bra warten_loop
// warteschleife ca. 10us
warten_10us:
move.l a0,-(sp)
move.l d6,-(sp)
move.l d1,-(sp)
move.l d0,-(sp)
lea MCF_SLT0_SCNT,a0
move.l (a0),d0
move.l #333,d6
warten_loop:
move.l (a0),d1
sub.l d0,d1
add.l d6,d1
bpl warten_loop
move.l (sp)+,d0
move.l (sp)+,d1
move.l (sp)+,d6
move.l (sp)+,a0
rts;
/********************************************************************/

134
sources/set_ide_access_mode.c Normal file
View File

@@ -0,0 +1,134 @@
/******************************************
// setze zugriffsgeschwindigkeit cf card
/********************************************************************/
#include "MCF5475.h"
#define error_reg (0x05)
#define seccnt (0x09)
#define stasec (0x0d)
#define cmd_reg (0x1d)
#define status_reg (0x1d)
#define wati (200)
extern void warte_10ms();
extern void warte_10us();
void ds_rx(void)
{
asm
{
// 1 sector lesen word
ds_rx:
move.l #128,d0
move.l a1,a0
ds_rx_loop:
move.l (a2),(a0)+
subq.l #1,d0
bne ds_rx_loop
}
};
void test_drive(void)
{
asm
{
moveq.l #11,d1 // default access (3) mode not wait (+8)
// reset
ide_reset:
clr.b 0x19(a2)
move.b #0x8,cmd_reg(a2) // device reset
move.l #wati,d0 // max. 2s warten
wait_ready:
tst.b status_reg(a2) // comando fertig?
bpl ide_ready // nein
subq.l #1,d0
bmi dam_nok // nicht da -> default werwenden
bsr warte_10ms
bra wait_ready
ide_ready:
clr.b 0x19(a2)
move.b #0xec,cmd_reg(a2) // identify devcie
move.l #wati,d0 // max. 2s warten
wait_busy:
tst.b status_reg(a2) // laufwerk bereit?
bpl ide_busy
subq.l #1,d0
bmi dam_nok // nicht da -> default werwenden
bsr warte_10ms
bra wait_busy
ide_busy:
clr.l (a1)
btst #3,status_reg(a2)
beq non_data
bsr ds_rx
tst.l (a1)
bne dam_ok
non_data:
subq.l #1,d3
bmi dam_nok
bra ide_ready
dam_ok:
tst.b status_reg(a2) // interrupt r<>ckstellen
lea MCF_PSC0_PSCTB_8BIT,a2 // name ausgeben
lea 54(a1),a0
moveq.l #40,d0
name_loop:
move.b (a0)+,(a2)
subq.l #1,d0
bne name_loop
move.l #' OK!',(a2)
move.l #0x0a0d,(a2)
moveq.l #3,d1
clr.l d0
move.w 2*68(a1),d0 // pio cycle time
lsr.l #5,d0 // :32(ns)
subq.l #1,d0
bmi siam_fertig
move.w d0,d1
siam_fertig:
cmp.w #3,d1 // gr<67>sser als max?
ble dam_nok
moveq.l #3,d1 // sonst default
dam_nok:
}
};
void set_ide_access_mode(void)
{
asm
{
lea 0xf0040000,a3
bset.b #1,(a3) // ide reset
bsr warte_10ms
move.w #0x1033,(a3) // 1.cf 2.ide, ide int activ, scsi int disable, speed = min
bsr warte_10ms
lea 0xfff00000,a2
lea 0xc00000,a1
}
test_drive();
asm
{
move.b d1,d2
}
asm
{
lea 0xfff00040,a2
lea 0xc00000,a1
}
test_drive();
asm
{
lsl.l #4,d1
or.l d1,d2
move.b d2,1(a3)
}
/********************************************************************/
};

117
sources/startcf.c
View File

@@ -19,11 +19,12 @@
#ifdef __cplusplus
#pragma cplusplus off
#endif
#pragma PID off
#pragma PID off
#pragma PIC off
#include "MCF5475.h"
#include "startcf.h"
#include "RuntimeConfig.h"
/* imported data */
@@ -31,53 +32,99 @@ extern unsigned long far _SP_INIT, _SDA_BASE;
extern unsigned long far _START_BSS, _END_BSS;
extern unsigned long far _START_SBSS, _END_SBSS;
extern unsigned long far __DATA_RAM, __DATA_ROM, __DATA_END;
extern unsigned long far __Bas_base;
extern unsigned long far __SUP_SP,__BOOT_FLASH;
extern unsigned long far rt_mbar;
extern unsigned long far _S_romp;
/* imported routines */
extern int BaS(int, char **);
/* exported routines */
extern void __initialize_hardware(void);
extern void init_slt(void);
extern void BaS(void);
void _startup(void)
{
asm
{
bra warmstart
jmp __BOOT_FLASH + 8 // ist zugleich reset vector
/* disable interrupts */
warmstart:
// disable interrupts
move.w #0x2700,sr
// Initialize MBAR
MOVE.L #__MBAR,D0
MOVEC D0,MBAR
move.l d0,rt_mbar
// mmu off
move.l #__MMUBAR+1,d0
movec d0,MMUBAR //mmubar setzen
clr.l d0
move.l d0,MCF_MMU_MMUCR // mmu off
/* Initialize RAMBARs: locate SRAM and validate it */ \
move.l #__RAMBAR0 + 0x7,d0 // supervisor only
movec d0,RAMBAR0
move.l #__RAMBAR1 + 0x1,d0 // on for all
movec d0,RAMBAR1
{
bra warmstart
jmp __BOOT_FLASH + 8 // ist zugleich reset vector
/* disable interrupts */
warmstart:
// disable interrupts
move.w #0x2700,sr
// Initialize MBAR
MOVE.L #__MBAR,D0
MOVEC D0,MBAR
move.l d0,rt_mbar
// mmu off
move.l #__MMUBAR+1,d0
movec d0,MMUBAR //mmubar setzen
clr.l d0
move.l d0,MCF_MMU_MMUCR // mmu off
/* Initialize RAMBARs: locate SRAM and validate it */ \
move.l #__RAMBAR0 + 0x7,d0 // supervisor only
movec d0,RAMBAR0
move.l #__RAMBAR1 + 0x1,d0 // on for all
movec d0,RAMBAR1
// STACKPOINTER AUF ENDE SRAM1
lea __SUP_SP,a7
// STACKPOINTER AUF ENDE SRAM1
lea __SUP_SP,a7
// hardware initieren
jsr __initialize_hardware
// STACKPOINTER AUF ENDE SRAM1
lea __SUP_SP,a7
/* setup A6 dummy stackframe */
movea.l #0,a6
link a6,#0
/* setup A5 */
lea _SDA_BASE,a5
/* copy all ROM sections to their RAM locations ... */
/*
* _S_romp is a null terminated array of
* typedef struct RomInfo {
* unsigned long Source;
* unsigned long Target;
* unsigned long Size;
* } RomInfo;
*
* Watch out if you're rebasing using _PICPID_DELTA
*/
lea _S_romp, a0
move.l (a0),a1
move.l 4(a0),a2
move.l 8(a0),d0
lsr.l #2,d0
crr_loop:
move.l (a1)+,(a2)+
subq.l #1,d0
bne crr_loop
/* call main(int, char **) */
pea __argv
clr.l -(sp) /* clearing a long is ok since it's caller cleanup */
jsr BaS
addq.l #8, sp
// instruction cache on
move.l #0x000C8100,d0
movec d0,cacr
nop
// initialize any hardware specific issues
bra __initialize_hardware
unlk a6
/* should never reach here but just in case */
jsr warmstart
illegal
rts
/* exit will never return */
__argv:
dc.l 0
};
}
}

47
sources/startcf.h
View File

@@ -1,47 +0,0 @@
/******************************************************************************
FILE : startcf.h
PURPOSE : startup code for ColdFire
LANGUAGE: C
Notes:
1) Default entry point is _startup.
. disable interrupts
. the SP is set to __SP_AFTER_RESET
. SP must be initialized to valid memory
in case the memory it points to is not valid using MEMORY_INIT macro
2) __initialize_hardware is called. Here you can initialize memory and some peripherics
at this point global variables are not initialized yet
3) After __initialize_hardware memory is setup; initialize SP to _SP_INIT and perform
needed initialisations for the language (clear memory, data rom copy).
4) void __initialize_system(void); is called
to allow additional hardware initialization (UART, GPIOs, etc...)
5) Jump to main
*/
/********************************************************************************/
#define cf_stack
//#define ii_on
#define halten
#define halten_dbcc
#define halten_and
#define halten_add
#define halten_sub
#define halten_or
#define halten_op
#define halten_opc
#define halten_movem
#define halten_lea
#define halten_shift
#define halten_move
#define halten_exg
#define halten_movep
#define halten_ewf
#define DIP_SWITCH (*(vuint8 *)(&__MBAR[0xA2C]))
#define DIP_SWITCHa ___MBAR + 0xA2C
#define sca_page_ID 6

336
sources/sysinit.c
View File

@@ -7,18 +7,20 @@
*/
#include "MCF5475.h"
#include "startcf.h"
#include "RuntimeConfig.h"
extern unsigned long far __VRAM;
extern unsigned long far __Bas_base;
extern unsigned long far BaS;
extern unsigned long far __BOOT_FLASH[];
extern int copy_end();
extern int warte_10us();
extern int warte_1ms();
extern int warte_10ms();
extern int warte_50us();
extern void warte_10us();
extern void warte_1ms();
extern void set_ide_access_mode();
extern unsigned long far rt_cacr;
extern unsigned long far rt_acr0;
extern unsigned long far rt_acr1;
extern unsigned long far rt_acr2;
extern unsigned long far rt_acr3;
extern unsigned long far rt_mmubar;
/********************************************************************/
// init SLICE TIMER 0
@@ -119,7 +121,17 @@ void init_seriel(void)
MCF_PSC3_PSCCR = 0x05;
MCF_INTC_ICR32 = 0x3F; //MAXIMALE PRIORITY/**********/
MCF_PSC0_PSCTB_8BIT = 0x0a0d;
MCF_PSC0_PSCTB_8BIT = 0x0a0a0a0d;
MCF_PSC0_PSCTB_8BIT = 'BaS ';
MCF_PSC0_PSCTB_8BIT = '13.0';
MCF_PSC0_PSCTB_8BIT = '5.20';
MCF_PSC0_PSCTB_8BIT = '17';
MCF_PSC0_PSCTB_8BIT = 0x0a0d;
MCF_PSC0_PSCTB_8BIT = '====';
MCF_PSC0_PSCTB_8BIT = '====';
MCF_PSC0_PSCTB_8BIT = '====';
MCF_PSC0_PSCTB_8BIT = '==';
MCF_PSC0_PSCTB_8BIT = 0x0a0d;
MCF_PSC0_PSCTB_8BIT = 'SERI';
MCF_PSC0_PSCTB_8BIT = 'AL O';
MCF_PSC0_PSCTB_8BIT = 'K! ';
@@ -175,39 +187,43 @@ void init_ddram(void)
/********************************************************************/
void init_fbcs()
{
MCF_PSC0_PSCTB_8BIT = 'FBCS';
/* Flash */
MCF_FBCS0_CSAR = 0xE0000000; // FLASH ADRESS
MCF_FBCS0_CSCR = 0x00001180; // 16 bit 4ws aa
MCF_FBCS0_CSMR = 0x007F0001; // 8MB on
MCF_PSC0_PSCTB_8BIT = 'FBCS';
MCF_FBCS1_CSAR = 0xFFF00000; // ATARI I/O ADRESS
MCF_FBCS1_CSAR = 0xFFF80000; // FFF8'0000-FFFF'FFFF: ATARI I/O ADRESS
MCF_FBCS1_CSCR = MCF_FBCS_CSCR_PS_16 // 16BIT PORT
| MCF_FBCS_CSCR_WS(8) // DEFAULT 8WS
| MCF_FBCS_CSCR_AA; // AA
MCF_FBCS1_CSMR = (MCF_FBCS_CSMR_BAM_1M
| MCF_FBCS_CSCR_WS(63) // DEFAULT 63WS
| MCF_FBCS_CSCR_AA; // AA
MCF_FBCS1_CSMR = (MCF_FBCS_CSMR_BAM_512K
| MCF_FBCS_CSMR_V);
MCF_FBCS2_CSAR = 0xF0000000; // NEUER I/O ADRESS-BEREICH
MCF_FBCS2_CSCR = MCF_FBCS_CSCR_PS_32 // 32BIT PORT
| MCF_FBCS_CSCR_WS(8) // DEFAULT 4WS
| MCF_FBCS_CSCR_WS(8) // DEFAULT 8WS
| MCF_FBCS_CSCR_AA; // AA
MCF_FBCS2_CSMR = (MCF_FBCS_CSMR_BAM_128M // F000'0000-F7FF'FFFF
| MCF_FBCS_CSMR_V);
MCF_FBCS3_CSAR = 0xF8000000; // NEUER I/O ADRESS-BEREICH
MCF_FBCS3_CSAR = 0xFFF00000; // IDE I/O ADRESS-BEREICH BURST!
MCF_FBCS3_CSCR = MCF_FBCS_CSCR_PS_16 // 16BIT PORT
| MCF_FBCS_CSCR_WS(16) // DEFAULT 16WS
| MCF_FBCS_CSCR_BSTR // Burst read enable
| MCF_FBCS_CSCR_BSTW // Burst write enable
| MCF_FBCS_CSCR_AA; // AA
MCF_FBCS3_CSMR = (MCF_FBCS_CSMR_BAM_64M // F800'0000-FBFF'FFFF
MCF_FBCS3_CSMR = (MCF_FBCS_CSMR_BAM_512K // FFF0'0000-FFF7'FFFF
| MCF_FBCS_CSMR_V);
MCF_FBCS4_CSAR = 0x40000000; // VIDEO RAM BEREICH, #FB_CS3 WIRD NICHT BEN<45>TZT, DECODE DIREKT AUF DEM FPGA
MCF_FBCS4_CSAR = 0x40000000; // VIDEO RAM BEREICH,
MCF_FBCS4_CSCR = MCF_FBCS_CSCR_PS_32 // 32BIT PORT
| MCF_FBCS_CSCR_BSTR // BURST READ ENABLE
| MCF_FBCS_CSCR_BSTW; // BURST WRITE ENABLE
MCF_FBCS4_CSMR = (MCF_FBCS_CSMR_BAM_1G // 4000'0000-7FFF'FFFF
| MCF_FBCS_CSMR_V);
/* Flash */
MCF_FBCS0_CSAR = 0xE0000000; // FLASH ADRESS
MCF_FBCS0_CSCR = 0x00001180; // 16 bit 4ws aa
MCF_FBCS0_CSMR = 0x007F0001; // 8MB on
MCF_PSC0_PSCTB_8BIT = ' OK!';
MCF_PSC0_PSCTB_8BIT = 0x0a0d;
}
@@ -241,23 +257,87 @@ test_STATUS:
jsr warte_10us // warten
lea 0xE0700000,a0 // startadresse fpga daten
moveq #0x4,d2
moveq #0x6,d3
moveq #0xc,d4
moveq #0xe,d5
word_send_loop:
cmp.l #0xE0800000,a0
bgt fpga_error
move.b (a0)+,d0 // 32 bit holen
moveq #8,d1 // 32 bit ausgeben
bit_send_loop:
lsr.l #1,d0 // bit rausschieben
bcs bit_is_1
bclr #3,(a1)
bra bit_send
bit_is_1:
bset #3,(a1)
bit_send:
bset #1,(a1) // clock=high
bclr #1,(a1) // clock=low
subq.l #1,d1
bne bit_send_loop // wiederholen bis fertig
bcs bit_is_10 // data bit3, #config bit2, clock bit1
move.b d2,(a1) // data low, config high, clk low
move.b d3,(a1) // data low, config high, clk high
bra bit_send0
bit_is_10:
move.b d4,(a1) // clk low, config high, data high
move.b d5,(a1) // clk high, config high, data high
bit_send0:
lsr.l #1,d0 // bit rausschieben
bcs bit_is_11 // data bit3, #config bit2, clock bit1
move.b d2,(a1) // data low, config high, clk low
move.b d3,(a1) // data low, config high, clk high
bra bit_send1
bit_is_11:
move.b d4,(a1) // clk low, config high, data high
move.b d5,(a1) // clk high, config high, data high
bit_send1:
lsr.l #1,d0 // bit rausschieben
bcs bit_is_12 // data bit3, #config bit2, clock bit1
move.b d2,(a1) // data low, config high, clk low
move.b d3,(a1) // data low, config high, clk high
bra bit_send2
bit_is_12:
move.b d4,(a1) // clk low, config high, data high
move.b d5,(a1) // clk high, config high, data high
bit_send2:
lsr.l #1,d0 // bit rausschieben
bcs bit_is_13 // data bit3, #config bit2, clock bit1
move.b d2,(a1) // data low, config high, clk low
move.b d3,(a1) // data low, config high, clk high
bra bit_send3
bit_is_13:
move.b d4,(a1) // clk low, config high, data high
move.b d5,(a1) // clk high, config high, data high
bit_send3:
lsr.l #1,d0 // bit rausschieben
bcs bit_is_14 // data bit3, #config bit2, clock bit1
move.b d2,(a1) // data low, config high, clk low
move.b d3,(a1) // data low, config high, clk high
bra bit_send4
bit_is_14:
move.b d4,(a1) // clk low, config high, data high
move.b d5,(a1) // clk high, config high, data high
bit_send4:
lsr.l #1,d0 // bit rausschieben
bcs bit_is_15 // data bit3, #config bit2, clock bit1
move.b d2,(a1) // data low, config high, clk low
move.b d3,(a1) // data low, config high, clk high
bra bit_send5
bit_is_15:
move.b d4,(a1) // clk low, config high, data high
move.b d5,(a1) // clk high, config high, data high
bit_send5:
lsr.l #1,d0 // bit rausschieben
bcs bit_is_16 // data bit3, #config bit2, clock bit1
move.b d2,(a1) // data low, config high, clk low
move.b d3,(a1) // data low, config high, clk high
bra bit_send6
bit_is_16:
move.b d4,(a1) // clk low, config high, data high
move.b d5,(a1) // clk high, config high, data high
bit_send6:
lsr.l #1,d0 // bit rausschieben
bcs bit_is_17 // data bit3, #config bit2, clock bit1
move.b d2,(a1) // data low, config high, clk low
move.b d3,(a1) // data low, config high, clk high
bra bit_send7
bit_is_17:
move.b d4,(a1) // clk low, config high, data high
move.b d5,(a1) // clk high, config high, data high
bit_send7:
// test auf fertig
btst #5,(a2) // fpga fertig, conf_done=high?
beq word_send_loop // nein, next word->
move.l #4000,d1
@@ -267,8 +347,31 @@ overclk:
bclr #1,(a1) // clock=low
subq.l #1,d1
bne overclk // weiter bis fertig
// datum des FPGA files ausgeben
jsr warte_10us // warten
lea MCF_PSC0_PSCTB_8BIT,a3
move.l #': Da',(a3)
move.l #'te: ',(a3)
move.l 0xf0040100,d1
moveq #8,d0
date_loop:
btst #0,d0
bne kein_punkt
btst #2,d0
beq kein_punkt
move.b #'.',(a3)
kein_punkt:
move.l d0,d3 // index
subq.l #1,d3 // -1
lsl.l #2,d3 // *2
move.l d1,d2
lsr.l d3,d2 // und schieben
and.l #0x0f,d2
add.l #'0',d2
move.b d2,(a3)
subq.l #1,d0
bgt date_loop
bra init_fpga_end
//---------------------------------------------------------
wait_pll:
lea MCF_SLT0_SCNT,a3
@@ -322,7 +425,7 @@ asm
move.w #1,0x44(a0) // M low = 1
bsr wait_pll
move.w #145,0x04(a0) // M high = 145 = 146MHz
move.w #65,0x04(a0) // M high = 65 = 65MHz
bsr wait_pll
clr.b (a1) // set
@@ -368,7 +471,7 @@ void init_video_ddr(void)
/********************************************************************/
/* video mit aufl<66>sung 1280x1000 137MHz /*
/********************************************************************/
/*
void video_1280_1024(void)
{
extern int wait_pll;
@@ -381,7 +484,7 @@ extern int wait_pll;
//testmuster 1
lea __VRAM,a2
lea __VRAM+0x600000,a3
lea __VRAM+0x120000,a3
clr.l d0
move.l #0x1000102,d1
loop5: move.l d0,(a2)+
@@ -409,35 +512,48 @@ flo6: cmp.l a2,a3
bgt loop5
// screen setzen
//horizontal 1280
//horizontal 1024
lea 0xffff8282,a0
move.w #1800,(a0)+
move.w #1380,(a0)+
move.w #99,(a0)+
move.w #100,(a0)+
move.w #1379,(a0)+
move.w #1500,(a0)
//vertical 1024
move.w #1344,(a0)+
move.w #1184,(a0)+
move.w #159,(a0)+
move.w #160,(a0)+
move.w #1183,(a0)+
move.w #1208,(a0)
//vertical 768
lea 0xffff82a2,a0
move.w #1150,(a0)+
move.w #1074,(a0)+
move.w #49,(a0)+
move.w #50,(a0)+
move.w #1073,(a0)+
move.w #1100,(a0)+
move.w #806,(a0)+
move.w #797,(a0)+
move.w #28,(a0)+
move.w #29,(a0)+
move.w #796,(a0)+
move.w #800,(a0)+
// acp video on
move.l #0x01070207,d0
move.l #0x0107820b,d0 // acp video, color1, pll pixelclk, dac on
move.l d0,0xf0000400
lea 0xffff8200,a0
clr.w (a0)
clr.b 3(a0)
clr.b 0xd(a0)
move.w #0x400,10(a0)
move.w #0x182,0xc0(a0)
clr.w 0xc2(a0)
// clut setzen
lea 0xf0000000,a0
move.l #0xffffffff,(a0)+
move.l #0xff,(a0)+
move.l #0xff00,(a0)+
move.l #0xff0000,(a0)
// halt
/*
lea 0xffff8200,a0
move.w #6,0xc0(a0)
move.w #7,0x40(a0)
move.w #7,0x42(a0)
move.w #7,0x44(a0)
move.w #7,0x46(a0)
move.b #1,0x60(a0)
halt
}
@@ -767,70 +883,64 @@ ac97_end:
}
/********************************************************************/
void __initialize_hardware(void)
{
_init_hardware:
asm
{
// instruction cache on
move.l #0x000C8120,d0
init_ddram();
asm
{
// instruction cache on
move.l #0x007fe000,d0
movec d0,acr0
move.l d0,rt_acr0
movec d0,acr2
move.l d0,rt_acr2
clr.l d0
movec d0,acr1
move.l d0,rt_acr1
movec d0,acr3
move.l d0,rt_acr3
move.l d0,MCF_MMU_MMUCR
move.l #0x050c8120,d0
move.l d0,rt_cacr
movec d0,cacr
nop
}
init_gpio();
init_seriel();
init_slt();
init_fbcs();
init_ddram();
// Ports nicht initialisieren wenn DIP Switch 5 = on
asm
{
move.b DIP_SWITCH,d0 // dip schalter adresse
btst.b #6,d0
beq not_init_ports
}
}
init_gpio();
init_seriel();
init_slt();
init_fbcs();
init_fpga();
init_video_ddr();
vdi_on();
// Ports nicht initialisieren wenn DIP Switch 6 = on
asm
{
// IDE reset
lea 0xffff8802,a0 // IDE reset
move.b #14,-2(a0)
move.b #0x80,(a0)
bsr warte_1ms
clr.b (a0)
// dip switch
move.b DIP_SWITCH,d0 // dip schalter adresse
move.b d0,0xF0040002 // acp conf +2
// ACP_CONF setzen und Ports nicht initialisieren wenn DIP Switch 6 = on
btst.b #6,d0
beq not_init_ports
}
init_PCI(); //pci braucht zeit
not_init_ports:
init_fpga();
init_video_ddr();
vdi_on();
// Ports nicht initialisieren wenn DIP Switch 5 = on
asm
{
move.b DIP_SWITCH,d0 // dip schalter adresse
btst.b #6,d0
beq not_init_ports2
}
test_upd720101();
// video_1280_1024();
init_ac97();
not_init_ports2:
test_upd720101();
// video_1280_1024();
asm
{
not_init_ports:
}
set_ide_access_mode();
asm
{
/*****************************************************/
/* BaS kopieren
/*****************************************************/
lea copy_start,a0
lea BaS,a1
sub.l a0,a1
move.l #__Bas_base,a2
move.l a2,a3
add.l a1,a3
lea copy_end,a4
BaS_kopieren_loop: // immer 16 bytes
move.l (a0)+,(a2)+
move.l (a0)+,(a2)+
move.l (a0)+,(a2)+
move.l (a0)+,(a2)+
cmp.l a4,a0
blt BaS_kopieren_loop
/*****************************************************/
jmp (a3)
copy_start:
/********************************************************************/
}
}

874
sources/sysinit.c.alt Normal file
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/*
* File: sysinit.c
* Purpose: Power-on Reset configuration of the COLDARI board.
*
* Notes:
*
*/
#include "MCF5475.h"
#include "startcf.h"
#include "RuntimeConfig.h"
extern unsigned long far __VRAM;
extern unsigned long far __BOOT_FLASH[];
extern void warte_10us();
extern void set_ide_access_mode();
extern unsigned long far rt_cacr;
extern unsigned long far rt_acr0;
extern unsigned long far rt_acr1;
extern unsigned long far rt_acr2;
extern unsigned long far rt_acr3;
extern unsigned long far rt_mmubar;
/********************************************************************/
// init SLICE TIMER 0
// all = 32.538 sec = 30.736mHz
// BYT0 = 127.1ms/tick = 7.876Hz offset 0
// BYT1 = 496.5us/tick = 2.014kHz offset 1
// BYT2 = 1.939us/tick = 515.6kHz offset 2
// BYT3 = 7.576ns/tick = 132.00MHz offset 3
// count down!!! 132MHz!!!
/********************************************************************/
void init_slt(void)
{
asm
{
lea MCF_SLT0_STCNT,a0
move.l #0xffffffff,(a0)
lea MCF_SLT0_SCR,a0
move.b #0x05,(a0)
}
MCF_PSC0_PSCTB_8BIT = 'SLT ';
MCF_PSC0_PSCTB_8BIT = 'OK! ';
MCF_PSC0_PSCTB_8BIT = 0x0a0d;
}
/********************************************************************/
// init GPIO ETC.
/********************************************************************/
void init_gpio(void)
{
// PAD REGISTER P.S.:FBCTL UND FBCS WERDEN RICHTIG GESETZT BEIM RESET
MCF_PAD_PAR_DMA = 0b11111111; // NORMAL ALS DREQ DACK
MCF_PAD_PAR_FECI2CIRQ = 0b1111001111001111; // FEC0 NORMAL, FEC1 ALS I/O, I2C, #INT5..6
MCF_PAD_PAR_PCIBG = 0b0000001000111111; // #PCI_BG4=#TBST,#PIC_BG3=I/O,#PCI_BG2..0=NORMAL
MCF_PAD_PAR_PCIBR = 0b0000001000111111; // #PCI_BR4=#INT4,#PIC_BR3=INPUT,#PCI_BR2..0=NORMAL
MCF_PAD_PAR_PSC3 = 0b00001100; // PSC3=TX,RX CTS+RTS=I/O
MCF_PAD_PAR_PSC1 = 0b11111100; // PSC1 NORMAL SERIELL
MCF_PAD_PAR_PSC0 = 0b11111100; // PSC0 NORMAL SERIELL
MCF_PAD_PAR_DSPI = 0b0001111111111111; // DSPI NORMAL
MCF_PAD_PAR_TIMER = 0b00101101; // TIN3..2=#IRQ3..2;TOUT3..2=NORMAL
// ALLE OUTPUTS NORMAL LOW
// ALLE DIR NORMAL INPUT = 0
MCF_GPIO_PDDR_FEC1L = 0b00011110; // OUT: 4=LED,3=PRG_DQ0,2=#FPGA_CONFIG,1=PRG_CLK(FPGA)
}
/********************************************************************/
// init seriel
/********************************************************************/
void init_seriel(void)
{
// PSC0: SER1 ----------
MCF_PSC0_PSCSICR = 0; // UART
MCF_PSC0_PSCCSR = 0xDD;
MCF_PSC0_PSCCTUR = 0x00;
MCF_PSC0_PSCCTLR = 36; // BAUD RATE = 115200
MCF_PSC0_PSCCR = 0x20;
MCF_PSC0_PSCCR = 0x30;
MCF_PSC0_PSCCR = 0x40;
MCF_PSC0_PSCCR = 0x50;
MCF_PSC0_PSCCR = 0x10;
MCF_PSC0_PSCIMR = 0x8700;
MCF_PSC0_PSCACR = 0x03;
MCF_PSC0_PSCMR1= 0xb3;
MCF_PSC0_PSCMR2= 0x07;
MCF_PSC0_PSCRFCR = 0x0F;
MCF_PSC0_PSCTFCR = 0x0F;
MCF_PSC0_PSCRFAR = 0x00F0;
MCF_PSC0_PSCTFAR = 0x00F0;
MCF_PSC0_PSCOPSET = 0x01;
MCF_PSC0_PSCCR = 0x05;
// PSC3: PIC ----------
MCF_PSC3_PSCSICR = 0; // UART
MCF_PSC3_PSCCSR = 0xDD;
MCF_PSC3_PSCCTUR = 0x00;
MCF_PSC3_PSCCTLR = 36; // BAUD RATE = 115200
MCF_PSC3_PSCCR = 0x20;
MCF_PSC3_PSCCR = 0x30;
MCF_PSC3_PSCCR = 0x40;
MCF_PSC3_PSCCR = 0x50;
MCF_PSC3_PSCCR = 0x10;
MCF_PSC3_PSCIMR = 0x0200; // receiver interrupt enable
MCF_PSC3_PSCACR = 0x03;
MCF_PSC3_PSCMR1= 0xb3;
MCF_PSC3_PSCMR2= 0x07;
MCF_PSC3_PSCRFCR = 0x0F;
MCF_PSC3_PSCTFCR = 0x0F;
MCF_PSC3_PSCRFAR = 0x00F0;
MCF_PSC3_PSCTFAR = 0x00F0;
MCF_PSC3_PSCOPSET = 0x01;
MCF_PSC3_PSCCR = 0x05;
MCF_INTC_ICR32 = 0x3F; //MAXIMALE PRIORITY/**********/
MCF_PSC0_PSCTB_8BIT = 0x0a0d;
MCF_PSC0_PSCTB_8BIT = 'SERI';
MCF_PSC0_PSCTB_8BIT = 'AL O';
MCF_PSC0_PSCTB_8BIT = 'K! ';
MCF_PSC0_PSCTB_8BIT = 0x0a0d;
}
/********************************************************************/
/* Initialize DDR DIMMs on the EVB board */
/********************************************************************/
/*
* Check to see if the SDRAM has already been initialized
* by a run control tool
*/
void init_ddram(void)
{
MCF_PSC0_PSCTB_8BIT = 'DDRA';
if (!(MCF_SDRAMC_SDCR & MCF_SDRAMC_SDCR_REF))
{
/* Basic configuration and initialization */
MCF_SDRAMC_SDRAMDS = 0x000002AA; // SDRAMDS configuration
MCF_SDRAMC_CS0CFG = 0x0000001A; // SDRAM CS0 configuration (128Mbytes 0000_0000 - 07FF_FFFF)
MCF_SDRAMC_CS1CFG = 0x0800001A; // SDRAM CS1 configuration (128Mbytes 0800_0000 - 0FFF_FFFF)
MCF_SDRAMC_CS2CFG = 0x1000001A; // SDRAM CS2 configuration (128Mbytes 1000_0000 - 07FF_FFFF)
MCF_SDRAMC_CS3CFG = 0x1800001A; // SDRAM CS3 configuration (128Mbytes 1800_0000 - 1FFF_FFFF)
// MCF_SDRAMC_SDCFG1 = 0x53722938; // SDCFG1
MCF_SDRAMC_SDCFG1 = 0x73622830; // SDCFG1
// MCF_SDRAMC_SDCFG2 = 0x24330000; // SDCFG2
MCF_SDRAMC_SDCFG2 = 0x46770000; // SDCFG2
// MCF_SDRAMC_SDCR = 0xE10F0002; // SDCR + IPALL
MCF_SDRAMC_SDCR = 0xE10D0002; // SDCR + IPALL
MCF_SDRAMC_SDMR = 0x40010000; // SDMR (write to LEMR)
// MCF_SDRAMC_SDMR = 0x05890000; // SDRM (write to LMR)
MCF_SDRAMC_SDMR = 0x048D0000; // SDRM (write to LMR)
// MCF_SDRAMC_SDCR = 0xE10F0002; // SDCR + IPALL
MCF_SDRAMC_SDCR = 0xE10D0002; // SDCR + IPALL
// MCF_SDRAMC_SDCR = 0xE10F0004; // SDCR + IREF (first refresh)
MCF_SDRAMC_SDCR = 0xE10D0004; // SDCR + IREF (first refresh)
// MCF_SDRAMC_SDCR = 0xE10F0004; // SDCR + IREF (second refresh)
MCF_SDRAMC_SDCR = 0xE10D0004; // SDCR + IREF (second refresh)
/// MCF_SDRAMC_SDMR = 0x01890000; // SDMR (write to LMR)
MCF_SDRAMC_SDMR = 0x008D0000; // SDMR (write to LMR)
// MCF_SDRAMC_SDCR = 0x710F0F00; // SDCR (lock SDMR and enable refresh)
MCF_SDRAMC_SDCR = 0x710D0F00; // SDCR (lock SDMR and enable refresh)
}
MCF_PSC0_PSCTB_8BIT = 'M OK';
MCF_PSC0_PSCTB_8BIT = '! ';
MCF_PSC0_PSCTB_8BIT = 0x0a0d;
}
/********************************************************************/
/* init FB_CSx /*
/********************************************************************/
void init_fbcs()
{
MCF_PSC0_PSCTB_8BIT = 'FBCS';
MCF_FBCS1_CSAR = 0xFFF00000; // ATARI I/O ADRESS
MCF_FBCS1_CSCR = MCF_FBCS_CSCR_PS_16 // 16BIT PORT
| MCF_FBCS_CSCR_WS(32) // DEFAULT 32WS
| MCF_FBCS_CSCR_BSTR // Burst read enable
| MCF_FBCS_CSCR_BSTW // Burst write enable
| MCF_FBCS_CSCR_AA; // AA
MCF_FBCS1_CSMR = (MCF_FBCS_CSMR_BAM_1M
| MCF_FBCS_CSMR_V);
MCF_FBCS2_CSAR = 0xF0000000; // NEUER I/O ADRESS-BEREICH
MCF_FBCS2_CSCR = MCF_FBCS_CSCR_PS_32 // 32BIT PORT
| MCF_FBCS_CSCR_WS(8) // DEFAULT 8WS
| MCF_FBCS_CSCR_AA; // AA
MCF_FBCS2_CSMR = (MCF_FBCS_CSMR_BAM_128M // F000'0000-F7FF'FFFF
| MCF_FBCS_CSMR_V);
MCF_FBCS3_CSAR = 0xF8000000; // NEUER I/O ADRESS-BEREICH
MCF_FBCS3_CSCR = MCF_FBCS_CSCR_PS_16 // 16BIT PORT
| MCF_FBCS_CSCR_WS(32) // DEFAULT 32WS
| MCF_FBCS_CSCR_BSTR // Burst read enable
| MCF_FBCS_CSCR_BSTW // Burst write enable
| MCF_FBCS_CSCR_AA; // AA
MCF_FBCS3_CSMR = (MCF_FBCS_CSMR_BAM_64M // F800'0000-FBFF'FFFF
| MCF_FBCS_CSMR_V);
MCF_FBCS4_CSAR = 0x40000000; // VIDEO RAM BEREICH,
MCF_FBCS4_CSCR = MCF_FBCS_CSCR_PS_32 // 32BIT PORT
| MCF_FBCS_CSCR_BSTR // BURST READ ENABLE
| MCF_FBCS_CSCR_BSTW; // BURST WRITE ENABLE
MCF_FBCS4_CSMR = (MCF_FBCS_CSMR_BAM_1G // 4000'0000-7FFF'FFFF
| MCF_FBCS_CSMR_V);
/* Flash */
MCF_FBCS0_CSAR = 0xE0000000; // FLASH ADRESS
MCF_FBCS0_CSCR = 0x00001180; // 16 bit 4ws aa
MCF_FBCS0_CSMR = 0x007F0001; // 8MB on
MCF_PSC0_PSCTB_8BIT = ' OK!';
MCF_PSC0_PSCTB_8BIT = 0x0a0d;
}
/********************************************************************/
/* FPGA LADEN /*
/********************************************************************/
void init_fpga(void)
{
MCF_PSC0_PSCTB_8BIT = 'FPGA';
asm
{
lea MCF_GPIO_PODR_FEC1L,a1 // register adresse:write
lea MCF_GPIO_PPDSDR_FEC1L,a2 // reads
bclr #1,(a1) // clk auf low
bclr #2,(a1) // #config=low
test_nSTATUS:
btst #0,(a2) // nSTATUS==0
bne test_nSTATUS // nein->
btst #5,(a2) // conf done==0
bne test_nSTATUS // nein->
jsr warte_10us // warten
bset #2,(a1) // #config=high
jsr warte_10us // warten
test_STATUS:
btst #0,(a2) // status high?
beq test_STATUS // nein->
jsr warte_10us // warten
lea 0xE0700000,a0 // startadresse fpga daten
word_send_loop:
cmp.l #0xE0800000,a0
bgt fpga_error
move.b (a0)+,d0 // 32 bit holen
moveq #8,d1 // 32 bit ausgeben
bit_send_loop:
lsr.l #1,d0 // bit rausschieben
bcs bit_is_1
bclr #3,(a1)
bra bit_send
bit_is_1:
bset #3,(a1)
bit_send:
bset #1,(a1) // clock=high
bclr #1,(a1) // clock=low
subq.l #1,d1
bne bit_send_loop // wiederholen bis fertig
btst #5,(a2) // fpga fertig, conf_done=high?
beq word_send_loop // nein, next word->
move.l #4000,d1
overclk:
bset #1,(a1) // clock=high
nop
bclr #1,(a1) // clock=low
subq.l #1,d1
bne overclk // weiter bis fertig
// datum des FPGA files ausgeben
jsr warte_10us // warten
lea MCF_PSC0_PSCTB_8BIT,a3
move.l #': Da',(a3)
move.l #'te: ',(a3)
move.l 0xf0040100,d1
moveq #8,d0
date_loop:
btst #0,d0
bne kein_punkt
btst #2,d0
beq kein_punkt
move.b #'.',(a3)
kein_punkt:
move.l d0,d3 // index
subq.l #1,d3 // -1
lsl.l #2,d3 // *2
move.l d1,d2
lsr.l d3,d2 // und schieben
and.l #0x0f,d2
add.l #'0',d2
move.b d2,(a3)
subq.l #1,d0
bgt date_loop
bra init_fpga_end
//---------------------------------------------------------
wait_pll:
lea MCF_SLT0_SCNT,a3
move.l (a3),d0
move.l #100000,d6 // ca 1ms
wait_pll_loop:
tst.w (a1)
bpl wait_pll_ok
move.l (a3),d1
sub.l d0,d1
add.l d6,d1
bpl wait_pll_loop
wait_pll_ok:
rts
// fertig
fpga_error:
}
MCF_PSC0_PSCTB_8BIT = ' NOT';
init_fpga_end:
MCF_PSC0_PSCTB_8BIT = ' OK!';
MCF_PSC0_PSCTB_8BIT = 0x0a0d;
// init pll
MCF_PSC0_PSCTB_8BIT = 'PLL ';
asm
{
lea 0xf0000600,a0
lea 0xf0000800,a1
bsr wait_pll
move.w #27,0x48(a0) // loopfilter r
bsr wait_pll
move.w #1,0x08(a0) // charge pump I
bsr wait_pll
move.w #12,0x0(a0) // N counter high = 12
bsr wait_pll
move.w #12,0x40(a0) // N counter low = 12
bsr wait_pll
move.w #1,0x114(a0) // ck1 bypass
bsr wait_pll
move.w #1,0x118(a0) // ck2 bypass
bsr wait_pll
move.w #1,0x11c(a0) // ck3 bypass
bsr wait_pll
move.w #1,0x10(a0) // ck0 high = 1
bsr wait_pll
move.w #1,0x50(a0) // ck0 low = 1
bsr wait_pll
move.w #1,0x144(a0) // M odd division
bsr wait_pll
move.w #1,0x44(a0) // M low = 1
bsr wait_pll
move.w #65,0x04(a0) // M high = 65 = 65MHz
bsr wait_pll
clr.b (a1) // set
}
MCF_PSC0_PSCTB_8BIT = 'SET!';
MCF_PSC0_PSCTB_8BIT = 0x0a0d;
}
/********************************************************************/
/* INIT VIDEO DDR RAM /*
/********************************************************************/
void init_video_ddr(void)
{
asm
{
// init video ram
moveq.l #0xB,d0
move.w d0,0xF0000400 //set cke=1, cs=1 config=1
nop
lea __VRAM,a0 //zeiger auf video ram
nop
move.l #0x00050400,(a0) //IPALL
nop
move.l #0x00072000,(a0) //load EMR pll on
nop
move.l #0x00070122,(a0) //load MR: reset pll, cl=2 BURST=4lw
nop
move.l #0x00050400,(a0) //IPALL
nop
move.l #0x00060000,(a0) //auto refresh
nop
move.l #0x00060000,(a0) //auto refresh
nop
move.l #0000070022,(a0) //load MR dll on
nop
move.l #0x01070002,d0 // fifo on, refresh on, ddrcs und cke on, video dac on,
move.l d0,0xf0000400
}
}
/********************************************************************/
/* video mit aufl<66>sung 1280x1000 137MHz /*
/********************************************************************/
void video_1280_1024(void)
{
extern int wait_pll;
asm
{
// SPEICHER F<>LLEM
//testmuster 1
lea __VRAM,a2
lea __VRAM+0x120000,a3
clr.l d0
move.l #0x1000102,d1
loop5: move.l d0,(a2)+
move.l d0,(a2)+
move.l d0,(a2)+
move.l d0,(a2)+
move.l d0,(a2)+
move.l d0,(a2)+
move.l d0,(a2)+
move.l d0,(a2)+
move.l d0,(a2)+
move.l d0,(a2)+
move.l d0,(a2)+
move.l d0,(a2)+
move.l d0,(a2)+
move.l d0,(a2)+
move.l d0,(a2)+
move.l d0,(a2)+
move.l d0,(a2)+
move.l d0,(a2)+
move.l d0,(a2)+
move.l d0,(a2)+
add.l d1,d0
flo6: cmp.l a2,a3
bgt loop5
// screen setzen
//horizontal 1024
lea 0xffff8282,a0
move.w #1344,(a0)+
move.w #1184,(a0)+
move.w #159,(a0)+
move.w #160,(a0)+
move.w #1183,(a0)+
move.w #1208,(a0)
//vertical 768
lea 0xffff82a2,a0
move.w #806,(a0)+
move.w #797,(a0)+
move.w #28,(a0)+
move.w #29,(a0)+
move.w #796,(a0)+
move.w #800,(a0)+
// acp video on
move.l #0x0107820b,d0 // acp video, color1, pll pixelclk, dac on
move.l d0,0xf0000400
lea 0xffff8200,a0
clr.w (a0)
clr.b 3(a0)
clr.b 0xd(a0)
move.w #0x400,10(a0)
move.w #0x182,0xc0(a0)
clr.w 0xc2(a0)
// clut setzen
lea 0xf0000000,a0
move.l #0xffffffff,(a0)+
move.l #0xff,(a0)+
move.l #0xff00,(a0)+
move.l #0xff0000,(a0)
/*
lea 0xffff8200,a0
move.w #6,0xc0(a0)
move.w #7,0x40(a0)
move.w #7,0x42(a0)
move.w #7,0x44(a0)
move.w #7,0x46(a0)
move.b #1,0x60(a0)
*/
// halt
}
}
/********************************************************************/
/* INIT PCI /*
/********************************************************************/
#define PCI_MEMORY_OFFSET (0x80000000)
#define PCI_MEMORY_SIZE (0x40000000)
#define PCI_IO_OFFSET (0xD0000000)
#define PCI_IO_SIZE (0x10000000)
void init_PCI(void)
{
MCF_PSC0_PSCTB_8BIT = 'PCI ';
asm
{
// Setup the arbiter
move.l #MCF_PCIARB_PACR_INTMPRI \
+ MCF_PCIARB_PACR_EXTMPRI(0x1F) \
+ MCF_PCIARB_PACR_INTMINTEN \
+ MCF_PCIARB_PACR_EXTMINTEN(0x1F),D0
move.l D0,MCF_PCIARB_PACR
// Setup burst parameters
move.l #MCF_PCI_PCICR1_CACHELINESIZE(4) + MCF_PCI_PCICR1_LATTIMER(32),D0
move.l D0,MCF_PCI_PCICR1
move.l #MCF_PCI_PCICR2_MINGNT(16) + MCF_PCI_PCICR2_MAXLAT(16),D0
move.l D0,MCF_PCI_PCICR2
// Turn on error signaling
move.l #MCF_PCI_PCIICR_TAE + MCF_PCI_PCIICR_IAE + MCF_PCI_PCIICR_REE + 32,D0
move.l D0,MCF_PCI_PCIICR
move.l #MCF_PCI_PCIGSCR_SEE,D0
or.l D0,MCF_PCI_PCIGSCR
// Configure Initiator Windows */
move.l #PCI_MEMORY_OFFSET + ((PCI_MEMORY_SIZE - 1) >> 8),D0
clr.w D0
move.l D0,MCF_PCI_PCIIW0BTAR // Initiator Window 0 Base / Translation Address Register
move.l #PCI_IO_OFFSET+((PCI_IO_SIZE-1)>>8),D0
clr.w D0
move.l D0,MCF_PCI_PCIIW1BTAR // Initiator Window 1 Base / Translation Address Register
clr.l MCF_PCI_PCIIW2BTAR // not used
move.l #MCF_PCI_PCIIWCR_WINCTRL0_MEMRDLINE + MCF_PCI_PCIIWCR_WINCTRL1_IO,D0
move.l D0,MCF_PCI_PCIIWCR // Initiator Window Configuration Register
/* Clear PCI Reset and wait for devices to reset */
move.l #~MCF_PCI_PCIGSCR_PR,D0
and.l D0,MCF_PCI_PCIGSCR
}
MCF_PSC0_PSCTB_8BIT = 'OK! ';
MCF_PSC0_PSCTB_8BIT = 0x0a0d;
}
/********************************************************************/
/* test UPC720101 (USB) /*
/********************************************************************/
void test_upd720101(void)
{
MCF_PSC0_PSCTB_8BIT = 'NEC ';
asm
{
// SELECT UPD720101 AD17
MOVE.L #MCF_PCI_PCICAR_E+MCF_PCI_PCICAR_DEVNUM(17)+MCF_PCI_PCICAR_FUNCNUM(0)+MCF_PCI_PCICAR_DWORD(0),D0
MOVE.L D0,MCF_PCI_PCICAR
LEA PCI_IO_OFFSET,A0
MOVE.L (A0),D1
move.l #0x33103500,d0
cmp.l d0,d1
beq nec_ok
}
MCF_PSC0_PSCTB_8BIT = 'NOT ';
goto nec_not_ok;
nec_ok:
asm
{
MOVE.L #MCF_PCI_PCICAR_E+MCF_PCI_PCICAR_DEVNUM(17)+MCF_PCI_PCICAR_FUNCNUM(0)+MCF_PCI_PCICAR_DWORD(57),D0
MOVE.L D0,MCF_PCI_PCICAR
move.b #0x20,(a0)
}
nec_not_ok:
asm
{
MOVE.L #MCF_PCI_PCICAR_DEVNUM(17)+MCF_PCI_PCICAR_FUNCNUM(0)+MCF_PCI_PCICAR_DWORD(57),D0
MOVE.L D0,MCF_PCI_PCICAR
}
MCF_PSC0_PSCTB_8BIT = 'OK! ';
MCF_PSC0_PSCTB_8BIT = 0x0a0d;
}
/********************************************************************/
/* TFP410 (vdi) einschalten /*
/********************************************************************/
void vdi_on(void)
{
uint8 RBYT, DBYT;
int versuche, startzeit;
MCF_PSC0_PSCTB_8BIT = 'DVI ';
MCF_I2C_I2FDR = 0x3c; // 100kHz standard
versuche = 0;
loop_i2c:
if (versuche++>10) goto next;
MCF_I2C_I2ICR = 0x0;
MCF_I2C_I2CR = 0x0;
MCF_I2C_I2CR = 0xA;
RBYT = MCF_I2C_I2DR;
MCF_I2C_I2SR = 0x0;
MCF_I2C_I2CR = 0x0;
MCF_I2C_I2ICR = 0x01;
MCF_I2C_I2CR = 0xb0;
MCF_I2C_I2DR = 0x7a; // ADRESSE TFP410
while(!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)) ; // warten auf fertig
MCF_I2C_I2SR &= 0xfd; // clear bit
if (MCF_I2C_I2SR & MCF_I2C_I2SR_RXAK) goto loop_i2c; // ack erhalten? -> nein
tpf_410_ACK_OK:
MCF_I2C_I2DR = 0x00; // SUB ADRESS 0
while(!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)) ;
MCF_I2C_I2SR &= 0xfd;
MCF_I2C_I2CR |= 0x4; // repeat start
MCF_I2C_I2DR = 0x7b; // beginn read
while(!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)) ; // warten auf fertig
MCF_I2C_I2SR &= 0xfd; // clear bit
if (MCF_I2C_I2SR & MCF_I2C_I2SR_RXAK) goto loop_i2c; // ack erhalten? -> nein
MCF_I2C_I2CR &= 0xef; // switch to rx
DBYT = MCF_I2C_I2DR; // dummy read
while(!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)) ;
MCF_I2C_I2SR &= 0xfd;
MCF_I2C_I2CR |= 0x08; // txak=1
RBYT = MCF_I2C_I2DR;
while(!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)) ;
MCF_I2C_I2SR &= 0xfd;
MCF_I2C_I2CR = 0x80; // stop
DBYT = MCF_I2C_I2DR; // dummy read
if (RBYT!=0x4c) goto loop_i2c;
i2c_ok:
MCF_I2C_I2CR = 0x0; // stop
MCF_I2C_I2SR = 0x0; // clear sr
while((MCF_I2C_I2SR & MCF_I2C_I2SR_IBB)) ; // wait auf bus free
MCF_I2C_I2CR = 0xb0; // on tx master
MCF_I2C_I2DR = 0x7A;
while(!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)) ; // warten auf fertig
MCF_I2C_I2SR &= 0xfd; // clear bit
if (MCF_I2C_I2SR & MCF_I2C_I2SR_RXAK) goto loop_i2c; // ack erhalten? -> nein
MCF_I2C_I2DR = 0x08; // SUB ADRESS 8
while(!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)) ;
MCF_I2C_I2SR &= 0xfd;
MCF_I2C_I2DR = 0xbf; // ctl1: power on, T:M:D:S: enable
while(!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)) ; // warten auf fertig
MCF_I2C_I2SR &= 0xfd; // clear bit
MCF_I2C_I2CR = 0x80; // stop
DBYT = MCF_I2C_I2DR; // dummy read
MCF_I2C_I2SR = 0x0; // clear sr
while((MCF_I2C_I2SR & MCF_I2C_I2SR_IBB)) ; // wait auf bus free
MCF_I2C_I2CR = 0xb0;
MCF_I2C_I2DR = 0x7A;
while(!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)) ; // warten auf fertig
MCF_I2C_I2SR &= 0xfd; // clear bit
if (MCF_I2C_I2SR & MCF_I2C_I2SR_RXAK) goto loop_i2c; // ack erhalten? -> nein
MCF_I2C_I2DR = 0x08; // SUB ADRESS 8
while(!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)) ;
MCF_I2C_I2SR &= 0xfd;
MCF_I2C_I2CR |= 0x4; // repeat start
MCF_I2C_I2DR = 0x7b; // beginn read
while(!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)) ; // warten auf fertig
MCF_I2C_I2SR &= 0xfd; // clear bit
if (MCF_I2C_I2SR & MCF_I2C_I2SR_RXAK) goto loop_i2c; // ack erhalten? -> nein
MCF_I2C_I2CR &= 0xef; // switch to rx
DBYT = MCF_I2C_I2DR; // dummy read
while(!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)) ;
MCF_I2C_I2SR &= 0xfd;
MCF_I2C_I2CR |= 0x08; // txak=1
warte_50us();
RBYT = MCF_I2C_I2DR;
while(!(MCF_I2C_I2SR & MCF_I2C_I2SR_IIF)) ;
MCF_I2C_I2SR &= 0xfd;
MCF_I2C_I2CR = 0x80; // stop
DBYT = MCF_I2C_I2DR; // dummy read
if (RBYT!=0xbf) goto loop_i2c;
goto dvi_ok;
next:
MCF_PSC0_PSCTB_8BIT = 'NOT ';
dvi_ok:
MCF_PSC0_PSCTB_8BIT = 'OK! ';
MCF_PSC0_PSCTB_8BIT = 0x0a0d;
MCF_I2C_I2CR = 0x0; // i2c off
}
/********************************************************************/
/* AC97 /*
/********************************************************************/
void init_ac97(void)
{
// PSC2: AC97 ----------
int i,k,zm,x,va,vb,vc;
MCF_PSC0_PSCTB_8BIT = 'AC97';
MCF_PAD_PAR_PSC2 = MCF_PAD_PAR_PSC2_PAR_RTS2_RTS // PSC2=TX,RX BCLK,CTS->AC'97
| MCF_PAD_PAR_PSC2_PAR_CTS2_BCLK
| MCF_PAD_PAR_PSC2_PAR_TXD2
| MCF_PAD_PAR_PSC2_PAR_RXD2;
MCF_PSC2_PSCMR1 = 0x0;
MCF_PSC2_PSCMR2 = 0x0;
MCF_PSC2_PSCIMR = 0x0300;
MCF_PSC2_PSCSICR = 0x03; //AC97
MCF_PSC2_PSCRFCR = 0x0f000000;
MCF_PSC2_PSCTFCR = 0x0f000000;
MCF_PSC2_PSCRFAR = 0x00F0;
MCF_PSC2_PSCTFAR = 0x00F0;
for ( zm = 0; zm<100000; zm++) // wiederholen bis synchron
{
MCF_PSC2_PSCCR = 0x20;
MCF_PSC2_PSCCR = 0x30;
MCF_PSC2_PSCCR = 0x40;
MCF_PSC2_PSCCR = 0x05;
// MASTER VOLUME -0dB
MCF_PSC2_PSCTB_AC97 = 0xE0000000; //START SLOT1 + SLOT2, FIRST FRAME
MCF_PSC2_PSCTB_AC97 = 0x02000000; //SLOT1:WR REG MASTER VOLUME adr 0x02
for ( i = 2; i<13; i++ )
{
MCF_PSC2_PSCTB_AC97 = 0x0; //SLOT2-12:WR REG ALLES 0
}
// read register
MCF_PSC2_PSCTB_AC97 = 0xc0000000; //START SLOT1 + SLOT2, FIRST FRAME
MCF_PSC2_PSCTB_AC97 = 0x82000000; //SLOT1:master volume
for ( i = 2; i<13; i++ )
{
MCF_PSC2_PSCTB_AC97 = 0x00000000; //SLOT2-12:RD REG ALLES 0
}
warte_50us();
va = MCF_PSC2_PSCTB_AC97;
if ((va & 0x80000fff)==0x80000800)
{
vb = MCF_PSC2_PSCTB_AC97;
vc = MCF_PSC2_PSCTB_AC97;
if ((va & 0xE0000fff)==0xE0000800 & vb==0x02000000 & vc==0x00000000)
{
goto livo;
}
}
}
MCF_PSC0_PSCTB_8BIT = ' NOT';
livo:
// AUX VOLUME ->-0dB
MCF_PSC2_PSCTB_AC97 = 0xE0000000; //START SLOT1 + SLOT2, FIRST FRAME
MCF_PSC2_PSCTB_AC97 = 0x16000000; //SLOT1:WR REG AUX VOLUME adr 0x16
MCF_PSC2_PSCTB_AC97 = 0x06060000; //SLOT1:VOLUME
for ( i = 3; i<13; i++ )
{
MCF_PSC2_PSCTB_AC97 = 0x0; //SLOT2-12:WR REG ALLES 0
}
// line in VOLUME +12dB
MCF_PSC2_PSCTB_AC97 = 0xE0000000; //START SLOT1 + SLOT2, FIRST FRAME
MCF_PSC2_PSCTB_AC97 = 0x10000000; //SLOT1:WR REG MASTER VOLUME adr 0x02
for ( i = 2; i<13; i++ )
{
MCF_PSC2_PSCTB_AC97 = 0x0; //SLOT2-12:WR REG ALLES 0
}
// cd in VOLUME 0dB
MCF_PSC2_PSCTB_AC97 = 0xE0000000; //START SLOT1 + SLOT2, FIRST FRAME
MCF_PSC2_PSCTB_AC97 = 0x12000000; //SLOT1:WR REG MASTER VOLUME adr 0x02
for ( i = 2; i<13; i++ )
{
MCF_PSC2_PSCTB_AC97 = 0x0; //SLOT2-12:WR REG ALLES 0
}
// mono out VOLUME 0dB
MCF_PSC2_PSCTB_AC97 = 0xE0000000; //START SLOT1 + SLOT2, FIRST FRAME
MCF_PSC2_PSCTB_AC97 = 0x06000000; //SLOT1:WR REG MASTER VOLUME adr 0x02
MCF_PSC2_PSCTB_AC97 = 0x00000000; //SLOT1:WR REG MASTER VOLUME adr 0x02
for ( i = 3; i<13; i++ )
{
MCF_PSC2_PSCTB_AC97 = 0x0; //SLOT2-12:WR REG ALLES 0
}
MCF_PSC2_PSCTFCR |= MCF_PSC_PSCTFCR_WFR; //set EOF
MCF_PSC2_PSCTB_AC97 = 0x00000000; //last data
ac97_end:
MCF_PSC0_PSCTB_8BIT = ' OK!';
MCF_PSC0_PSCTB_8BIT = 0x0a0d;
}
/********************************************************************/
void __initialize_hardware(void)
{
_init_hardware:
init_ddram();
asm
{
// instruction cache on
move.l #0x007fe000,d0
movec d0,acr0
move.l d0,rt_acr0
movec d0,acr2
move.l d0,rt_acr2
clr.l d0
movec d0,acr1
move.l d0,rt_acr1
movec d0,acr3
move.l d0,rt_acr3
move.l d0,MCF_MMU_MMUCR
move.l #0x050c8120,d0
move.l d0,rt_cacr
movec d0,cacr
nop
}
init_gpio();
init_seriel();
init_slt();
init_fbcs();
// ACP_CONF setzen und Ports nicht initialisieren wenn DIP Switch 6 = on
asm
{
move.b DIP_SWITCH,d0 // dip schalter adresse
btst.b #6,d0
beq not_init_ports
}
init_PCI(); //pci braucht zeit
not_init_ports:
init_fpga();
init_video_ddr();
vdi_on();
// Ports nicht initialisieren wenn DIP Switch 6 = on
asm
{
move.b DIP_SWITCH,d0 // dip schalter adresse
move.b d0,0xF0040002 // acp conf +2
btst.b #6,d0
beq not_init_ports2
}
test_upd720101();
init_ac97();
asm
{
not_init_ports2:
}
// video_1280_1024();
set_ide_access_mode();
}

87
sources/sysinit.h
View File

@@ -1,87 +0,0 @@
/*
* File: sysinit.h
* Purpose: COLDARI Power-on Reset configuration
*
* Notes:
*
*/
#ifndef __SYSINIT_H__
#define __SYSINIT_H__
#ifdef __cplusplus
extern "C" {
#endif
#if ENABLE_UART_SUPPORT==1
/*
* System Bus Clock Info
*/
// 5475EVB has 133Mhz system clock
#define SYSTEM_CLOCK_KHZ 133000 /* system bus frequency in kHz */
/***
* Serial Port Info
* The baud rate to be : 19200
* Data bits : 8
* Parity : None
* Stop Bits : 1
* Flow Control : None
*/
#define TERMINAL_PORT (0) /* PSC channel used as terminal */
#define TERMINAL_BAUD kBaud19200 /* 115200 */
#undef HARDWARE_FLOW_CONTROL /* Flow control ON or OFF */
#endif
/***
* Board Memory map definitions from linker command files:
* __SDRAM,__SDRAM_SIZE, __FLASH, __FLASH_SIZE linker
* symbols must be defined in the linker command file.
*/
extern __declspec(system) uint8 __BOOT_FLASH[];
extern __declspec(system) uint8 __BOOT_FLASH_SIZE[];
extern __declspec(system) uint8 __SDRAM[];
extern __declspec(system) uint8 __SDRAM_SIZE[];
#define BOOT_FLASH_ADDRESS (uint32)__BOOT_FLASH
#define BOOT_FLASH_SIZE (uint32)__BOOT_FLASH_SIZE
#define SDRAM_ADDRESS (uint32)__SDRAM
#define SDRAM_SIZE (uint32)__SDRAM_SIZE
/********************************************************************/
/* __initialize_hardware Startup code routine
*
* __initialize_hardware is called by the startup code right after reset,
* with interrupt disabled and SP pre-set to a valid memory area.
* Here you should initialize memory and some peripherics;
* at this point global variables are not initialized yet.
* The startup code will initialize SP on return of this function.
*/
void __initialize_hardware(void);
/********************************************************************/
/* __initialize_system Startup code routine
*
* __initialize_system is called by the startup code when all languages
* specific initialization are done to allow additional hardware setup.
*/
void __initialize_system(void);
#ifdef __cplusplus
}
#endif
#endif /* __SYSINIT_H__ */