forked from Firebee/FPGA_Config
90 lines
2.4 KiB
VHDL
90 lines
2.4 KiB
VHDL
-- Copyright (C) 1991-2009 Altera Corporation
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-- Your use of Altera Corporation's design tools, logic functions
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-- and other software and tools, and its AMPP partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Altera Program License
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-- Subscription Agreement, Altera MegaCore Function License
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-- Agreement, or other applicable license agreement, including,
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-- without limitation, that your use is for the sole purpose of
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-- programming logic devices manufactured by Altera and sold by
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-- Altera or its authorized distributors. Please refer to the
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-- applicable agreement for further details.
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-- PROGRAM "Quartus II 64-Bit"
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-- VERSION "Version 9.1 Build 222 10/21/2009 SJ Full Version"
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-- CREATED "Sat Mar 01 09:16:22 2014"
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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LIBRARY work;
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ENTITY mux41 IS
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PORT
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(
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S0 : IN STD_LOGIC;
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D2 : IN STD_LOGIC;
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INH : IN STD_LOGIC;
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D0 : IN STD_LOGIC;
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D1 : IN STD_LOGIC;
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D3 : IN STD_LOGIC;
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S1 : IN STD_LOGIC;
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Q : OUT STD_LOGIC
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);
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END mux41;
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ARCHITECTURE bdf_type OF mux41 IS
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SIGNAL SYNTHESIZED_WIRE_18 : STD_LOGIC;
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SIGNAL SYNTHESIZED_WIRE_19 : STD_LOGIC;
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SIGNAL SYNTHESIZED_WIRE_20 : STD_LOGIC;
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SIGNAL SYNTHESIZED_WIRE_21 : STD_LOGIC;
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SIGNAL SYNTHESIZED_WIRE_22 : STD_LOGIC;
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SIGNAL SYNTHESIZED_WIRE_13 : STD_LOGIC;
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SIGNAL SYNTHESIZED_WIRE_14 : STD_LOGIC;
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SIGNAL SYNTHESIZED_WIRE_15 : STD_LOGIC;
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SIGNAL SYNTHESIZED_WIRE_16 : STD_LOGIC;
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BEGIN
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SYNTHESIZED_WIRE_18 <= NOT(S0);
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SYNTHESIZED_WIRE_21 <= NOT(SYNTHESIZED_WIRE_18);
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SYNTHESIZED_WIRE_13 <= SYNTHESIZED_WIRE_19 AND SYNTHESIZED_WIRE_20 AND SYNTHESIZED_WIRE_18 AND D0;
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SYNTHESIZED_WIRE_14 <= SYNTHESIZED_WIRE_19 AND SYNTHESIZED_WIRE_20 AND SYNTHESIZED_WIRE_21 AND D1;
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SYNTHESIZED_WIRE_15 <= SYNTHESIZED_WIRE_19 AND SYNTHESIZED_WIRE_22 AND SYNTHESIZED_WIRE_18 AND D2;
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SYNTHESIZED_WIRE_16 <= SYNTHESIZED_WIRE_19 AND SYNTHESIZED_WIRE_22 AND SYNTHESIZED_WIRE_21 AND D3;
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Q <= SYNTHESIZED_WIRE_13 OR SYNTHESIZED_WIRE_14 OR SYNTHESIZED_WIRE_15 OR SYNTHESIZED_WIRE_16;
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SYNTHESIZED_WIRE_19 <= NOT(INH);
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SYNTHESIZED_WIRE_20 <= NOT(S1);
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SYNTHESIZED_WIRE_22 <= NOT(SYNTHESIZED_WIRE_20);
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END bdf_type; |