forked from Firebee/FPGA_Config
43 lines
1.7 KiB
Plaintext
43 lines
1.7 KiB
Plaintext
/*
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WARNING: Do NOT edit the input and output ports in this file in a text
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editor if you plan to continue editing the block that represents it in
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the Block Editor! File corruption is VERY likely to occur.
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*/
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/*
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Copyright (C) 1991-2008 Altera Corporation
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Your use of Altera Corporation's design tools, logic functions
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and other software and tools, and its AMPP partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Altera Program License
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Subscription Agreement, Altera MegaCore Function License
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Agreement, or other applicable license agreement, including,
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without limitation, that your use is for the sole purpose of
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programming logic devices manufactured by Altera and sold by
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Altera or its authorized distributors. Please refer to the
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applicable agreement for further details.
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*/
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(header "symbol" (version "1.1"))
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(symbol
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(rect 0 0 96 48)
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(text "lpm_constant4" (rect 6 1 106 17)(font "Arial" (font_size 10)))
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(text "inst" (rect 8 32 25 44)(font "Arial" ))
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(port
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(pt 96 24)
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(output)
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(text "result[10..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
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(text "result[10..0]" (rect 93 -31 106 24)(font "Arial" (font_size 8))(invisible))
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(line (pt 96 24)(pt 80 24)(line_width 3))
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)
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(drawing
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(text "2040" (rect 60 18 80 30)(font "Arial" ))
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(text "11" (rect 85 25 95 37)(font "Arial" ))
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(line (pt 16 16)(pt 80 16)(line_width 1))
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(line (pt 80 16)(pt 80 32)(line_width 1))
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(line (pt 80 32)(pt 16 32)(line_width 1))
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(line (pt 16 32)(pt 16 16)(line_width 1))
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(line (pt 80 28)(pt 88 20)(line_width 1))
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)
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)
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