forked from Firebee/FPGA_Config
101 lines
4.1 KiB
Plaintext
101 lines
4.1 KiB
Plaintext
/*
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WARNING: Do NOT edit the input and output ports in this file in a text
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editor if you plan to continue editing the block that represents it in
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the Block Editor! File corruption is VERY likely to occur.
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*/
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/*
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Copyright (C) 1991-2010 Altera Corporation
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Your use of Altera Corporation's design tools, logic functions
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and other software and tools, and its AMPP partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Altera Program License
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Subscription Agreement, Altera MegaCore Function License
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Agreement, or other applicable license agreement, including,
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without limitation, that your use is for the sole purpose of
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programming logic devices manufactured by Altera and sold by
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Altera or its authorized distributors. Please refer to the
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applicable agreement for further details.
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*/
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(header "symbol" (version "1.1"))
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(symbol
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(rect 0 0 328 216)
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(text "altpll1" (rect 144 1 191 20)(font "Arial" (font_size 10)))
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(text "inst" (rect 8 197 31 212)(font "Arial" ))
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(port
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(pt 0 72)
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(input)
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(text "inclk0" (rect 0 0 40 16)(font "Arial" (font_size 8)))
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(text "inclk0" (rect 4 56 38 72)(font "Arial" (font_size 8)))
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)
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(drawing
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(text "inclk0 frequency: 33.000 MHz" (rect 58 67 201 81)(font "Arial" ))
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(text "Operation Mode: Src Sync Comp" (rect 58 84 215 98)(font "Arial" ))
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(text "Clk " (rect 59 111 76 125)(font "Arial" ))
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