forked from Firebee/FPGA_Config
150 lines
6.5 KiB
Tcl
150 lines
6.5 KiB
Tcl
###########################################################################
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#
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# Generated by : Version 9.1 Build 222 10/21/2009 SJ Full Version
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#
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# Project : firebee1
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# Revision : firebee1
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#
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# Date : Sat Mar 01 15:22:38 CET 2014
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#
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###########################################################################
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# WARNING: Ignored QSF Variable: Global TSU_REQUIREMENT = 1 ns
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# WARNING: Ignored QSF Variable: Global TH_REQUIREMENT = 1 ns
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# WARNING: Ignored QSF Variable: Global TPD_REQUIREMENT = 1 ns
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# WARNING: Ignored QSF Variable: Global TCO_REQUIREMENT = 1 ns
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# WARNING: Expected ENABLE_CLOCK_LATENCY to be set to 'ON', but it is set to 'OFF'
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# In SDC, create_generated_clock auto-generates clock latency
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#
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# ------------------------------------------
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#
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# Create generated clocks based on PLLs
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derive_pll_clocks -use_tan_name
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#
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# ------------------------------------------
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# WARNING: Global Fmax translated to derive_clocks. Behavior is not identical
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if {![info exist ::qsta_message_posted]} {
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post_message -type warning "Original Global Fmax translated from QSF using derive_clocks"
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set ::qsta_message_posted 1
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}
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derive_clocks -period "30.303 ns"
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#
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# Original Clock Setting Name: CLK33M
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create_clock -period "30.303 ns" \
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-name {CLK33M} {CLK33M}
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# ---------------------------------------------
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# ** Clock Latency
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# -------------
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# ** Clock Uncertainty
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# -----------------
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derive_clock_uncertainty
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# ** Multicycles
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# -----------
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# ** Cuts
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# ----
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# ** Input/Output Delays
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# -------------------
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# QSF: -name INPUT_MAX_DELAY 4 ns -from * -to FB_ALE
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# Command requires a unique clock. Expand clock
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#foreach_in_collection clk [get_clocks * ] {
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# set_input_delay -add_delay -max 4 -clock [get_object_info -name $clk] [get_ports {FB_ALE}]
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#}
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#set_input_delay -add_delay -max 4 -clock {altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[4]} [get_ports {FB_ALE}]
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# ** Tpd requirements
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# ----------------
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# ** Setup/Hold Relationships
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# ------------------------
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# ** Tsu/Th requirements
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# -------------------
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# ** Tco/MinTco requirements
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# -----------------------
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#
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# Entity Specific Timing Assignments found in
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# the Timing Analyzer Settings report panel
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#
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set_false_path -from [get_registers {*dcfifo*delayed_wrptr_g[*]}] -to [get_registers {*dcfifo*rs_dgwp*}]
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set_false_path -from [get_registers {*dcfifo*rdptr_g[*]}] -to [get_registers {*dcfifo*ws_dgrp*}]
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set_clock_groups -asynchronous -group { \
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altpll4:b2v_inst22|altpll:altpll_component|altpll_qfk2:auto_generated|clk[0] \
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} \
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-group { \
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altpll3:b2v_inst13|altpll:altpll_component|altpll_jvs2:auto_generated|clk[3] \
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} \
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-group { \
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altpll3:b2v_inst13|altpll:altpll_component|altpll_jvs2:auto_generated|clk[2] \
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} \
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-group { \
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altpll3:b2v_inst13|altpll:altpll_component|altpll_jvs2:auto_generated|clk[1] \
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} \
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-group { \
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altpll3:b2v_inst13|altpll:altpll_component|altpll_jvs2:auto_generated|clk[0] \
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} \
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-group { \
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altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[4] \
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altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[3] \
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altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[2] \
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altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[1] \
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altpll2:b2v_inst12|altpll:altpll_component|altpll_1r33:auto_generated|clk[0] \
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CLK33M \
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} \
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-group { \
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altpll1:b2v_inst|altpll:altpll_component|altpll_8tp2:auto_generated|clk[2] \
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altpll1:b2v_inst|altpll:altpll_component|altpll_8tp2:auto_generated|clk[1] \
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} \
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-group { \
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altpll1:b2v_inst|altpll:altpll_component|altpll_8tp2:auto_generated|clk[0] \
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} \
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set_multicycle_path -from [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_*:auto_generated|clk[4]}] -to [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_*:auto_generated|clk[0]}] -setup -end 2
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set_multicycle_path -from [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_*:auto_generated|clk[4]}] -to [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_*:auto_generated|clk[0]}] -hold -end 1
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set_multicycle_path -from [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_*:auto_generated|clk[4]}] -to [get_clocks {CLK33M}] -setup -end 2
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set_multicycle_path -from [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_*:auto_generated|clk[4]}] -to [get_clocks {CLK33M}] -hold -end 1
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set_multicycle_path -from [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_*:auto_generated|clk[0]}] -to [get_clocks {CLK33M}] -setup -end 2
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set_multicycle_path -from [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_*:auto_generated|clk[0]}] -to [get_clocks {CLK33M}] -hold -end 1
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set_multicycle_path -from [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_*:auto_generated|clk[3]}] -to [get_clocks {CLK33M}] -setup -end 2
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set_multicycle_path -from [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_*:auto_generated|clk[3]}] -to [get_clocks {CLK33M}] -hold -end 1
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set_multicycle_path -from [get_clocks {CLK33M}] -to [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_*:auto_generated|clk[4]}] -setup -end 2
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set_multicycle_path -from [get_clocks {CLK33M}] -to [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_*:auto_generated|clk[4]}] -hold -end 1
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set_multicycle_path -from [get_clocks {CLK33M}] -to [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_*:auto_generated|clk[1]}] -setup -end 2
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set_multicycle_path -from [get_clocks {CLK33M}] -to [get_clocks {altpll2:b2v_inst12|altpll:altpll_component|altpll_*:auto_generated|clk[1]}] -hold -end 1
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# ---------------------------------------------
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# WARNING: Ignored QSF Variable: -name MAX_DELAY 5 ns -from VD -to FB_AD
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# WARNING: Ignored QSF Variable: -name MAX_DELAY 5 ns -from FB_AD -to VA
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# WARNING: Ignored QSF Variable: -name MAX_DELAY 5 ns -from FB_AD -to nVRAS
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# WARNING: Ignored QSF Variable: -name MAX_DELAY 5 ns -from FB_AD -to BA
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#set_max_delay -from [get_ports {VD[*]}] -to [get_ports {FB_AD[*]}] 5.000
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#set_max_delay -from [get_ports {FB_AD[*]}] -to [get_ports {VA[*]}] 5.000
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#set_max_delay -from [get_ports {FB_AD[*]}] -to [get_ports {nVRAS}] 5.000
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#set_max_delay -from [get_ports {FB_AD[*]}] -to [get_ports {BA[*]}] 5.000
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# Constrain the input I/O path
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set_input_delay -clock CLK33M -max 5 [all_inputs]
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#set_input_delay -clock CLK33M -min 4 [all_inputs]
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# Constrain the output I/O path
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set_output_delay -clock CLK33M -max 5 [all_outputs]
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