forked from Firebee/FPGA_Config
15 lines
302 B
VHDL
15 lines
302 B
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use work.datetime.all;
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entity compile_date is
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port
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(
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datetime : out std_ulogic_vector(31 downto 0)
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);
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end entity compile_date;
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architecture rtl of compile_date is
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begin
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datetime <= work.datetime.DATE_HEX_DMY;
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end architecture rtl; |