forked from Firebee/FPGA_Config
56 lines
1.4 KiB
VHDL
56 lines
1.4 KiB
VHDL
-- Copyright (C) 1991-2014 Altera Corporation
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-- Your use of Altera Corporation's design tools, logic functions
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-- and other software and tools, and its AMPP partner logic
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-- functions, and any output files from any of the foregoing
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-- (including device programming or simulation files), and any
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-- associated documentation or information are expressly subject
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-- to the terms and conditions of the Altera Program License
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-- Subscription Agreement, Altera MegaCore Function License
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-- Agreement, or other applicable license agreement, including,
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-- without limitation, that your use is for the sole purpose of
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-- programming logic devices manufactured by Altera and sold by
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-- Altera or its authorized distributors. Please refer to the
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-- applicable agreement for further details.
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-- PROGRAM "Quartus II 64-Bit"
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-- VERSION "Version 13.1.4 Build 182 03/12/2014 SJ Web Edition"
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-- CREATED "Mon Jan 11 09:20:56 2016"
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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LIBRARY altera;
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USE altera.maxplus2.all;
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LIBRARY work;
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ENTITY mux41_5 IS
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PORT
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(
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S0 : IN STD_LOGIC;
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D2 : IN STD_LOGIC;
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S1 : IN STD_LOGIC;
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D0 : IN STD_LOGIC;
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INH : IN STD_LOGIC;
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D1 : IN STD_LOGIC;
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Q : OUT STD_LOGIC
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);
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END mux41_5;
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ARCHITECTURE bdf_type OF mux41_5 IS
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BEGIN
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-- instantiate macrofunction
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b2v_inst45 : work.mux41
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PORT MAP(S0 => S0,
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D2 => D2,
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S1 => S1,
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D0 => D0,
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D3 => '0',
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INH => INH,
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D1 => D1,
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Q => Q);
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END bdf_type; |