forked from Firebee/FPGA_Config
17 lines
840 B
XML
17 lines
840 B
XML
<?xml version="1.0" encoding="UTF-8" ?>
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<!DOCTYPE pinplan>
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<pinplan intended_family="Cyclone III" variation_name="altddio_bidir0" megafunction_name="ALTDDIO_BIDIR" specifies="all_ports">
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<global>
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<pin name="datain_h[31..0]" direction="input" scope="external" />
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<pin name="datain_l[31..0]" direction="input" scope="external" />
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<pin name="inclock" direction="input" scope="external" source="clock" />
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<pin name="oe" direction="input" scope="external" />
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<pin name="outclock" direction="input" scope="external" source="clock" />
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<pin name="combout[31..0]" direction="output" scope="external" />
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<pin name="dataout_h[31..0]" direction="output" scope="external" />
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<pin name="dataout_l[31..0]" direction="output" scope="external" />
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<pin name="padio[31..0]" direction="bidir" scope="external" />
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</global>
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</pinplan>
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