forked from Firebee/FPGA_Config
80 lines
2.7 KiB
VHDL
80 lines
2.7 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.firebee_utils_pkg.all;
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entity flexbus_register is
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generic
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(
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reg_width : integer := 11;
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match_address : std_logic_vector(31 downto 0) := (others => '0');
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num_ignore : integer range 0 to 31;
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match_fbcs : integer := 0
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);
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port
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(
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clk : in std_logic;
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-- FlexBus signals
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fb_addr : in std_logic_vector(31 downto 0);
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fb_ad_in : in std_logic_vector(31 downto 0);
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fb_ad_out : out std_logic_vector(31 downto 0);
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fb_cs_n : in std_logic_vector(5 downto 1);
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fb_wr_n : in std_logic;
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fb_oe_n : in std_logic;
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fb_size : in std_logic_vector(1 downto 0);
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register_ta : out std_logic
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);
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end entity flexbus_register;
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architecture rtl of flexbus_register is
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signal fbcs_match : std_logic;
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signal address_match : std_logic;
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signal fb_b : std_logic_vector(3 downto 0); -- byte selects
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signal cs : std_logic;
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signal reg_value : std_logic_vector(reg_width - 1 downto 0);
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begin
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-- byte selects
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-- HWORD
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-- HHBYT
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-- LONG UND LINE
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fb_b(0) <= (fb_size(1) and (not fb_size(0)) and (not fb_addr(1))) or
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((not fb_size(1)) and fb_size(0) and (not fb_addr(1)) and (not fb_addr(0))) or
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((not fb_size(1)) and (not fb_size(0))) or
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(fb_size(1) and fb_size(0));
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-- HWORD
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-- HLBYT
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-- LONG UND LINE
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fb_b(1) <= (fb_size(1) and (not fb_size(0) and (not fb_addr(1)))) or
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((not fb_size(1)) and fb_size(0) and (not fb_addr(1)) and fb_addr(0)) or
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((not fb_size(1)) and (not fb_size(0))) or
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(fb_size(1) and fb_size(0));
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-- LWORD
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-- LHBYT
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-- LONG UND LINE
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fb_b(2) <= (fb_size(1) and (not fb_size(0)) and fb_addr(1)) or
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((not fb_size(1)) and fb_size(0) and fb_addr(1) and (not fb_addr(0))) or
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((not fb_size(1)) and (not fb_size(0))) or (fb_size(1) and fb_size(0));
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-- LWORD
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-- LLBYT
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-- LONG UND LINE
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fb_b(3) <= (fb_size(1) and (not fb_size(0)) and fb_addr(1)) or
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((not fb_size(1)) and fb_size(0) and fb_addr(1) and fb_addr(0)) or
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((not fb_size(1)) and (not fb_size(0))) or
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(fb_size(1) and fb_size(0));
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fbcs_match <= '1' when not(fb_cs_n(match_fbcs)) = '1' else '0';
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address_match <= f_addr_cmp_mask(fb_addr, match_address, num_ignore);
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p_register_access : process(all)
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begin
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if rising_edge(clk) then
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end if;
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end process p_register_access;
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end architecture rtl; |