forked from Firebee/FPGA_Config
63 lines
2.9 KiB
VHDL
63 lines
2.9 KiB
VHDL
library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library work;
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use work.parameter_pkg.all;
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use work.types_pkg.all;
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package constants_pkg is
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-------------------------
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-- Flags in CCR register
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-------------------------
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constant C_FLAG : natural := 0;
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constant V_FLAG : natural := 1;
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constant Z_FLAG : natural := 2;
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constant N_FLAG : natural := 3;
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constant U_FLAG : natural := 4;
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constant E_FLAG : natural := 5;
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constant L_FLAG : natural := 6;
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constant S_FLAG : natural := 7;
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-------------------
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-- Pipeline stages
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-------------------
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constant ST_FETCH : natural := 0;
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constant ST_FETCH2 : natural := 1;
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constant ST_DECODE : natural := 2;
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constant ST_ADGEN : natural := 3;
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constant ST_EXEC : natural := 4;
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----------------------
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-- Activation signals
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----------------------
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constant ACT_ADGEN : natural := 0; -- Run the address generator
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constant ACT_ALU : natural := 1; -- Activation of ALU results in modification of the status register
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constant ACT_EXEC_BRA : natural := 2; -- Branch (in execute stage)
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constant ACT_EXEC_CR_MOD : natural := 3; -- Control Register Modification (in execute stage)
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constant ACT_EXEC_LOOP : natural := 4; -- Loop instruction (REP, DO)
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constant ACT_X_MEM_RD : natural := 5; -- Init read from X memory
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constant ACT_Y_MEM_RD : natural := 6; -- Init read from Y memory
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constant ACT_P_MEM_RD : natural := 7; -- Init read from P memory
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constant ACT_X_MEM_WR : natural := 8; -- Init write to X memory
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constant ACT_Y_MEM_WR : natural := 9; -- Init write to Y memory
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constant ACT_P_MEM_WR : natural := 10; -- Init write to P memory
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constant ACT_REG_RD : natural := 11; -- Read from register (6 bit addressing)
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constant ACT_REG_WR : natural := 12; -- Write to register (6 bit addressing)
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constant ACT_IMM_8BIT : natural := 13; -- 8 bit immediate operand (in instruction word)
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constant ACT_IMM_12BIT : natural := 14; -- 12 bit immediate operand (in instruction word)
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constant ACT_IMM_LONG : natural := 15; -- 24 bit immediate operant (in optional instruction word)
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constant ACT_X_BUS_RD : natural := 16; -- Read data via X-bus (from x0,x1,a,b)
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constant ACT_X_BUS_WR : natural := 17; -- Write data via X-bus (to x0,x1,a,b)
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constant ACT_Y_BUS_RD : natural := 18; -- Read data via Y-bus (from y0,y1,a,b)
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constant ACT_Y_BUS_WR : natural := 19; -- Write data via Y-bus (to y0,y1,a,b)
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constant ACT_L_BUS_RD : natural := 20; -- Read data via L-bus (from a10, b10,x,y,a,b,ab,ba)
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constant ACT_L_BUS_WR : natural := 21; -- Write data via L-bus (to a10, b10,x,y,a,b,ab,ba)
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constant ACT_BIT_MOD_WR : natural := 22; -- Bit modify write (to set for BSET, BCLR, BCHG)
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constant ACT_REG_WR_CC : natural := 23; -- Write to register file conditionally (Tcc)
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constant ACT_ALU_WR_CC : natural := 24; -- Write ALU result conditionally (Tcc)
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constant ACT_NORM : natural := 25; -- NORM instruction needs special handling
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end package constants_pkg;
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