forked from Firebee/FPGA_Config
239 lines
13 KiB
Tcl
239 lines
13 KiB
Tcl
#--------------------------------------------------------------#
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# #
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# Synopsis design constraints for the Firebee project #
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# #
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# This file is part of the Firebee ACP project. #
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# http://www.firebee.org #
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# #
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# Description: #
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# timing constraints for the Firebee VHDL config #
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# #
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# #
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# #
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# To Do: #
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# - #
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# #
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# Author(s): #
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# Markus Fröschle, mfro@mubf.de #
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# #
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#--------------------------------------------------------------#
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# #
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# Copyright (C) 2015 Markus Fröschle & the ACP project #
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# #
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# This source file may be used and distributed without #
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# restriction provided that this copyright statement is not #
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# removed from the file and that any derivative work contains #
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# the original copyright notice and the associated disclaimer. #
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# #
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# This source file is free software; you can redistribute it #
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# and/or modify it under the terms of the GNU Lesser General #
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# Public License as published by the Free Software Foundation; #
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# either version 2.1 of the License, or (at your option) any #
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# later version. #
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# #
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# This source is distributed in the hope that it will be #
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# useful, but WITHOUT ANY WARRANTY; without even the implied #
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# warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR #
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# PURPOSE. See the GNU Lesser General Public License for more #
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# details. #
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# #
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# You should have received a copy of the GNU Lesser General #
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# Public License along with this source; if not, download it #
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# from http://www.gnu.org/licenses/lgpl.html #
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# #
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################################################################
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#**************************************************************
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# Time Information
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#**************************************************************
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set_time_format -unit ns -decimal_places 3
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#**************************************************************
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# Create Clock
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#**************************************************************
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create_clock -name {MAIN_CLK} -period 30.303 -waveform { 0.000 15.151 } [get_ports {MAIN_CLK}]
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# Clocks used:
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# MAIN_CLK 33MHz
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#
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# PLL1: i_mfp_acia_clk_pll
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# input: MAIN_CLK
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# c0: 500 kHz
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# c1: 2.4576 MHz
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# c2: 24.576 MHz
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#
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# PLL2: i_ddr_clock_pll
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# input: MAIN_CLK
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# c0: 132 MHz 190°
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# c1: 132 MHz 0°
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# c2: 132 MHz 180°
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# c3: 132 MHz 105°
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# c4: 66 MHz 270°
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#
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# PLL3: i_atari_clk_pll
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# input: MAIN_CLK
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# c0: 2 MHz
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# c1: 16 MHz
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# c2: 25 MHz
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# c3: 48 MHz
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#
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# PLL4_ i_video_clk_pll
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# input: USB_CLK (48 MHz, PLL3 c3)
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# c0: 96 MHz, programmable in 1MHz steps
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#
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#**************************************************************
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# Create Generated Clock
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#**************************************************************
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derive_pll_clocks
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# PIXEL_CLK is either
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# CLK13M, CLK17M, CLK25M, CLK33M or CLK_VIDEO
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# where CLK13M is half of CLK25M,
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# CLK17M is half of CLK33M and CLK_VIDEO is the freely programmable
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# clock of i_video_clk_pll
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#
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#**************************************************************
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# Set Clock Latency
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#**************************************************************
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#**************************************************************
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# Set Clock Uncertainty
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#**************************************************************
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set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {MAIN_CLK}] 2.00
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set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {MAIN_CLK}] 2.00
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derive_clock_uncertainty
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#**************************************************************
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# Set Input Delay
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#**************************************************************
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set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 2.500 [all_inputs]
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set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 2.500 [all_inputs]
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#set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 1.500 [get_ports {FB*}]
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#set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 1.500 {nFB_CS1 nFB_CS2 nFB_CS3 nFB_OE}
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#set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 [get_ports {FB*}]
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#set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 {nFB_CS1 nFB_CS2 nFB_CS3 nFB_OE}
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#**************************************************************
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# Set Output Delay
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#**************************************************************
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set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 2.500 [all_outputs]
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set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 2.500 [all_outputs]
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#set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 1.500 [get_ports {FB*}]
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#set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 1.500 {nFB_TA}
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#set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 [get_ports {FB*}]
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#set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 {nFB_TA}
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# video RAM access
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#set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 0.500 [get_ports {VA[*]}]
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#set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 0.500 [get_ports {VA[*]}]
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#set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 0.500 [get_ports {VD[*]}]
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#set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 0.500 [get_ports {VD[*]}]
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#set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 0.500 [get_ports {VDQS[*]}]
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#set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 0.500 [get_ports {VDQS[*]}]
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#set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 0.500 [get_ports {VDM[*]}]
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#set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 0.500 [get_ports {VDM[*]}]
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#set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 0.500 {nVCAS nVRAS nVWE nVCS VCKE DDR_CLK nDDR_CLK BA[*]}
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#set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 0.500 {nVCAS nVRAS nVWE nVCS VCKE DDR_CLK nDDR_CLK BA[*]}
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#**************************************************************
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# Set Clock Groups
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#**************************************************************
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#**************************************************************
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# Set False Path
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#**************************************************************
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#
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# i_video_clk is freely programmable
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#
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set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]
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# MAIN_CLK to 16 MHz clk -> false_path
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set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[1]}]
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set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}]
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# MAIN_CLK to DDR clk and v.v.
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set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]
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set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_mfp_acia_clk_pll|altpll_component|auto_generated|pll1|clk[1]}]
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set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {MAIN_CLK}]
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set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[3]}] -to [get_clocks {MAIN_CLK}]
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set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {MAIN_CLK}]
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set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]
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set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[1]}]
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set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {i_mfp_acia_clk_pll|altpll_component|auto_generated|pll1|clk[1]}]
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set_false_path -from [get_clocks {i_mfp_acia_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {MAIN_CLK}]
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set_false_path -from [get_clocks {i_mfp_acia_clk_pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {MAIN_CLK}]
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set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]
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# 2 MHz to 33 MHz
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set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {MAIN_CLK}]
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set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]
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set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[3]}] -to [get_clocks {MAIN_CLK}]
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# 16 MHz to 33 MHz
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set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[1]}] -to [get_clocks {MAIN_CLK}]
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set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[1]}]
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# 25 MHz to 33 MHz
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set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] -to [get_clocks {MAIN_CLK}]
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set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}]
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set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]
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set_false_path -from [get_clocks {i_mfp_acia_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] -to [get_clocks {MAIN_CLK}]
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set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] -to [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]
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set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]
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set_false_path -from [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}]
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set_false_path -from [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {MAIN_CLK}]
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set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]
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set_false_path -from [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]
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set_false_path -from [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]
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set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_id9:dffpipe17|dffe18a*}]
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set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_hd9:dffpipe12|dffe13a*}]
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set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_kd9:dffpipe15|dffe16a*}]
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set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a*}]
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set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_re9:dffpipe19|dffe20a*}]
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#**************************************************************
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# Set Multicycle Path
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#**************************************************************
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#**************************************************************
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# Set Maximum Delay
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#**************************************************************
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#**************************************************************
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# Set Minimum Delay
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#**************************************************************
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#**************************************************************
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# Set Input Transition
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#**************************************************************
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