forked from Firebee/FPGA_Config
272 lines
10 KiB
VHDL
272 lines
10 KiB
VHDL
-- megafunction wizard: %LPM_MUX%
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-- GENERATION: STANDARD
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-- VERSION: WM1.0
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-- MODULE: lpm_mux
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-- ============================================================
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-- File Name: lpm_mux1.vhd
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-- Megafunction Name(s):
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-- lpm_mux
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--
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-- Simulation Library Files(s):
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-- lpm
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-- ============================================================
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-- ************************************************************
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-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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--
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-- 8.1 Build 163 10/28/2008 SJ Web Edition
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-- ************************************************************
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--Copyright (C) 1991-2008 Altera Corporation
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--Your use of Altera Corporation's design tools, logic functions
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--and other software and tools, and its AMPP partner logic
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--functions, and any output files from any of the foregoing
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--(including device programming or simulation files), and any
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--associated documentation or information are expressly subject
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--to the terms and conditions of the Altera Program License
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--Subscription Agreement, Altera MegaCore Function License
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--Agreement, or other applicable license agreement, including,
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--without limitation, that your use is for the sole purpose of
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--programming logic devices manufactured by Altera and sold by
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--Altera or its authorized distributors. Please refer to the
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--applicable agreement for further details.
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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LIBRARY lpm;
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USE lpm.lpm_components.all;
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ENTITY lpm_mux1 IS
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PORT
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(
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clock : IN STD_LOGIC ;
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data0x : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
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data1x : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
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data2x : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
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data3x : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
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data4x : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
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data5x : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
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data6x : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
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data7x : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
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sel : IN STD_LOGIC_VECTOR (2 DOWNTO 0);
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result : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
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);
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END lpm_mux1;
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ARCHITECTURE SYN OF lpm_mux1 IS
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-- type STD_LOGIC_2D is array (NATURAL RANGE <>, NATURAL RANGE <>) of STD_LOGIC;
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SIGNAL sub_wire0 : STD_LOGIC_VECTOR (15 DOWNTO 0);
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SIGNAL sub_wire1 : STD_LOGIC_VECTOR (15 DOWNTO 0);
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SIGNAL sub_wire2 : STD_LOGIC_2D (7 DOWNTO 0, 15 DOWNTO 0);
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SIGNAL sub_wire3 : STD_LOGIC_VECTOR (15 DOWNTO 0);
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SIGNAL sub_wire4 : STD_LOGIC_VECTOR (15 DOWNTO 0);
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SIGNAL sub_wire5 : STD_LOGIC_VECTOR (15 DOWNTO 0);
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SIGNAL sub_wire6 : STD_LOGIC_VECTOR (15 DOWNTO 0);
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SIGNAL sub_wire7 : STD_LOGIC_VECTOR (15 DOWNTO 0);
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SIGNAL sub_wire8 : STD_LOGIC_VECTOR (15 DOWNTO 0);
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SIGNAL sub_wire9 : STD_LOGIC_VECTOR (15 DOWNTO 0);
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BEGIN
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sub_wire9 <= data0x(15 DOWNTO 0);
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sub_wire8 <= data1x(15 DOWNTO 0);
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sub_wire7 <= data2x(15 DOWNTO 0);
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sub_wire6 <= data3x(15 DOWNTO 0);
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sub_wire5 <= data4x(15 DOWNTO 0);
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sub_wire4 <= data5x(15 DOWNTO 0);
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sub_wire3 <= data6x(15 DOWNTO 0);
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result <= sub_wire0(15 DOWNTO 0);
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sub_wire1 <= data7x(15 DOWNTO 0);
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sub_wire2(7, 0) <= sub_wire1(0);
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sub_wire2(7, 1) <= sub_wire1(1);
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sub_wire2(7, 2) <= sub_wire1(2);
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sub_wire2(7, 3) <= sub_wire1(3);
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sub_wire2(7, 4) <= sub_wire1(4);
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sub_wire2(7, 5) <= sub_wire1(5);
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sub_wire2(7, 6) <= sub_wire1(6);
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sub_wire2(7, 7) <= sub_wire1(7);
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sub_wire2(7, 8) <= sub_wire1(8);
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sub_wire2(7, 9) <= sub_wire1(9);
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sub_wire2(7, 10) <= sub_wire1(10);
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sub_wire2(7, 11) <= sub_wire1(11);
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sub_wire2(7, 12) <= sub_wire1(12);
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sub_wire2(7, 13) <= sub_wire1(13);
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sub_wire2(7, 14) <= sub_wire1(14);
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sub_wire2(7, 15) <= sub_wire1(15);
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sub_wire2(6, 0) <= sub_wire3(0);
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sub_wire2(6, 1) <= sub_wire3(1);
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sub_wire2(6, 2) <= sub_wire3(2);
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sub_wire2(6, 3) <= sub_wire3(3);
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sub_wire2(6, 4) <= sub_wire3(4);
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sub_wire2(6, 5) <= sub_wire3(5);
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sub_wire2(6, 6) <= sub_wire3(6);
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sub_wire2(6, 7) <= sub_wire3(7);
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sub_wire2(6, 8) <= sub_wire3(8);
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sub_wire2(6, 9) <= sub_wire3(9);
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sub_wire2(6, 10) <= sub_wire3(10);
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sub_wire2(6, 11) <= sub_wire3(11);
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sub_wire2(6, 12) <= sub_wire3(12);
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sub_wire2(6, 13) <= sub_wire3(13);
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sub_wire2(6, 14) <= sub_wire3(14);
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sub_wire2(6, 15) <= sub_wire3(15);
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sub_wire2(5, 0) <= sub_wire4(0);
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sub_wire2(5, 1) <= sub_wire4(1);
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sub_wire2(5, 2) <= sub_wire4(2);
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sub_wire2(5, 3) <= sub_wire4(3);
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sub_wire2(5, 4) <= sub_wire4(4);
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sub_wire2(5, 5) <= sub_wire4(5);
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sub_wire2(5, 6) <= sub_wire4(6);
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sub_wire2(5, 7) <= sub_wire4(7);
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sub_wire2(5, 8) <= sub_wire4(8);
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sub_wire2(5, 9) <= sub_wire4(9);
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sub_wire2(5, 10) <= sub_wire4(10);
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sub_wire2(5, 11) <= sub_wire4(11);
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sub_wire2(5, 12) <= sub_wire4(12);
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sub_wire2(5, 13) <= sub_wire4(13);
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sub_wire2(5, 14) <= sub_wire4(14);
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sub_wire2(5, 15) <= sub_wire4(15);
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sub_wire2(4, 0) <= sub_wire5(0);
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sub_wire2(4, 1) <= sub_wire5(1);
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sub_wire2(4, 2) <= sub_wire5(2);
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sub_wire2(4, 3) <= sub_wire5(3);
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sub_wire2(4, 4) <= sub_wire5(4);
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sub_wire2(4, 5) <= sub_wire5(5);
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sub_wire2(4, 6) <= sub_wire5(6);
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sub_wire2(4, 7) <= sub_wire5(7);
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sub_wire2(4, 8) <= sub_wire5(8);
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sub_wire2(4, 9) <= sub_wire5(9);
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sub_wire2(4, 10) <= sub_wire5(10);
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sub_wire2(4, 11) <= sub_wire5(11);
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sub_wire2(4, 12) <= sub_wire5(12);
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sub_wire2(4, 13) <= sub_wire5(13);
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sub_wire2(4, 14) <= sub_wire5(14);
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sub_wire2(4, 15) <= sub_wire5(15);
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sub_wire2(3, 0) <= sub_wire6(0);
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sub_wire2(3, 1) <= sub_wire6(1);
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sub_wire2(3, 2) <= sub_wire6(2);
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sub_wire2(3, 3) <= sub_wire6(3);
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sub_wire2(3, 4) <= sub_wire6(4);
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sub_wire2(3, 5) <= sub_wire6(5);
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sub_wire2(3, 6) <= sub_wire6(6);
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sub_wire2(3, 7) <= sub_wire6(7);
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sub_wire2(3, 8) <= sub_wire6(8);
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sub_wire2(3, 9) <= sub_wire6(9);
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sub_wire2(3, 10) <= sub_wire6(10);
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sub_wire2(3, 11) <= sub_wire6(11);
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sub_wire2(3, 12) <= sub_wire6(12);
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sub_wire2(3, 13) <= sub_wire6(13);
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sub_wire2(3, 14) <= sub_wire6(14);
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sub_wire2(3, 15) <= sub_wire6(15);
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sub_wire2(2, 0) <= sub_wire7(0);
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sub_wire2(2, 1) <= sub_wire7(1);
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sub_wire2(2, 2) <= sub_wire7(2);
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sub_wire2(2, 3) <= sub_wire7(3);
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sub_wire2(2, 4) <= sub_wire7(4);
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sub_wire2(2, 5) <= sub_wire7(5);
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sub_wire2(2, 6) <= sub_wire7(6);
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sub_wire2(2, 7) <= sub_wire7(7);
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sub_wire2(2, 8) <= sub_wire7(8);
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sub_wire2(2, 9) <= sub_wire7(9);
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sub_wire2(2, 10) <= sub_wire7(10);
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sub_wire2(2, 11) <= sub_wire7(11);
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sub_wire2(2, 12) <= sub_wire7(12);
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sub_wire2(2, 13) <= sub_wire7(13);
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sub_wire2(2, 14) <= sub_wire7(14);
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sub_wire2(2, 15) <= sub_wire7(15);
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sub_wire2(1, 0) <= sub_wire8(0);
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sub_wire2(1, 1) <= sub_wire8(1);
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sub_wire2(1, 2) <= sub_wire8(2);
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sub_wire2(1, 3) <= sub_wire8(3);
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sub_wire2(1, 4) <= sub_wire8(4);
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sub_wire2(1, 5) <= sub_wire8(5);
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sub_wire2(1, 6) <= sub_wire8(6);
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sub_wire2(1, 7) <= sub_wire8(7);
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sub_wire2(1, 8) <= sub_wire8(8);
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sub_wire2(1, 9) <= sub_wire8(9);
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sub_wire2(1, 10) <= sub_wire8(10);
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sub_wire2(1, 11) <= sub_wire8(11);
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sub_wire2(1, 12) <= sub_wire8(12);
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sub_wire2(1, 13) <= sub_wire8(13);
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sub_wire2(1, 14) <= sub_wire8(14);
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sub_wire2(1, 15) <= sub_wire8(15);
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sub_wire2(0, 0) <= sub_wire9(0);
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sub_wire2(0, 1) <= sub_wire9(1);
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sub_wire2(0, 2) <= sub_wire9(2);
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sub_wire2(0, 3) <= sub_wire9(3);
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sub_wire2(0, 4) <= sub_wire9(4);
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sub_wire2(0, 5) <= sub_wire9(5);
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sub_wire2(0, 6) <= sub_wire9(6);
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sub_wire2(0, 7) <= sub_wire9(7);
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sub_wire2(0, 8) <= sub_wire9(8);
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sub_wire2(0, 9) <= sub_wire9(9);
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sub_wire2(0, 10) <= sub_wire9(10);
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sub_wire2(0, 11) <= sub_wire9(11);
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sub_wire2(0, 12) <= sub_wire9(12);
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sub_wire2(0, 13) <= sub_wire9(13);
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sub_wire2(0, 14) <= sub_wire9(14);
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sub_wire2(0, 15) <= sub_wire9(15);
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lpm_mux_component : lpm_mux
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GENERIC MAP (
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lpm_pipeline => 4,
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lpm_size => 8,
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lpm_type => "LPM_MUX",
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lpm_width => 16,
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lpm_widths => 3
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)
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PORT MAP (
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sel => sel,
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clock => clock,
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data => sub_wire2,
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result => sub_wire0
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);
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END SYN;
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-- ============================================================
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-- CNX file retrieval info
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-- ============================================================
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-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
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-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
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-- Retrieval info: CONSTANT: LPM_PIPELINE NUMERIC "4"
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-- Retrieval info: CONSTANT: LPM_SIZE NUMERIC "8"
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-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_MUX"
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-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
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-- Retrieval info: CONSTANT: LPM_WIDTHS NUMERIC "3"
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-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
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-- Retrieval info: USED_PORT: data0x 0 0 16 0 INPUT NODEFVAL data0x[15..0]
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-- Retrieval info: USED_PORT: data1x 0 0 16 0 INPUT NODEFVAL data1x[15..0]
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-- Retrieval info: USED_PORT: data2x 0 0 16 0 INPUT NODEFVAL data2x[15..0]
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-- Retrieval info: USED_PORT: data3x 0 0 16 0 INPUT NODEFVAL data3x[15..0]
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-- Retrieval info: USED_PORT: data4x 0 0 16 0 INPUT NODEFVAL data4x[15..0]
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-- Retrieval info: USED_PORT: data5x 0 0 16 0 INPUT NODEFVAL data5x[15..0]
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-- Retrieval info: USED_PORT: data6x 0 0 16 0 INPUT NODEFVAL data6x[15..0]
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-- Retrieval info: USED_PORT: data7x 0 0 16 0 INPUT NODEFVAL data7x[15..0]
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-- Retrieval info: USED_PORT: result 0 0 16 0 OUTPUT NODEFVAL result[15..0]
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-- Retrieval info: USED_PORT: sel 0 0 3 0 INPUT NODEFVAL sel[2..0]
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-- Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
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-- Retrieval info: CONNECT: result 0 0 16 0 @result 0 0 16 0
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-- Retrieval info: CONNECT: @data 1 7 16 0 data7x 0 0 16 0
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-- Retrieval info: CONNECT: @data 1 6 16 0 data6x 0 0 16 0
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-- Retrieval info: CONNECT: @data 1 5 16 0 data5x 0 0 16 0
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-- Retrieval info: CONNECT: @data 1 4 16 0 data4x 0 0 16 0
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-- Retrieval info: CONNECT: @data 1 3 16 0 data3x 0 0 16 0
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-- Retrieval info: CONNECT: @data 1 2 16 0 data2x 0 0 16 0
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-- Retrieval info: CONNECT: @data 1 1 16 0 data1x 0 0 16 0
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-- Retrieval info: CONNECT: @data 1 0 16 0 data0x 0 0 16 0
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-- Retrieval info: CONNECT: @sel 0 0 3 0 sel 0 0 3 0
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-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
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-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.vhd TRUE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.inc TRUE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.cmp TRUE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1.bsf TRUE FALSE
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-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_mux1_inst.vhd FALSE
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-- Retrieval info: LIB_FILE: lpm
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