-- megafunction wizard: %ALTSYNCRAM% -- GENERATION: STANDARD -- VERSION: WM1.0 -- MODULE: altsyncram -- ============================================================ -- File Name: altsyncram0.tdf -- Megafunction Name(s): -- altsyncram -- -- Simulation Library Files(s): -- altera_mf -- ============================================================ -- ************************************************************ -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE! -- -- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition -- ************************************************************ --Copyright (C) 1991-2010 Altera Corporation --Your use of Altera Corporation's design tools, logic functions --and other software and tools, and its AMPP partner logic --functions, and any output files from any of the foregoing --(including device programming or simulation files), and any --associated documentation or information are expressly subject --to the terms and conditions of the Altera Program License --Subscription Agreement, Altera MegaCore Function License --Agreement, or other applicable license agreement, including, --without limitation, that your use is for the sole purpose of --programming logic devices manufactured by Altera and sold by --Altera or its authorized distributors. Please refer to the --applicable agreement for further details. INCLUDE "altsyncram.inc"; SUBDESIGN altsyncram0 ( address_a[3..0] : INPUT; address_b[3..0] : INPUT; byteena_a[1..0] : INPUT = VCC; clock_a : INPUT = VCC; clock_b : INPUT; data_a[15..0] : INPUT; data_b[15..0] : INPUT; wren_a : INPUT = GND; wren_b : INPUT = GND; q_a[15..0] : OUTPUT; q_b[15..0] : OUTPUT; ) VARIABLE altsyncram_component : altsyncram WITH ( ADDRESS_REG_B = "CLOCK1", BYTE_SIZE = 8, CLOCK_ENABLE_INPUT_A = "BYPASS", CLOCK_ENABLE_INPUT_B = "BYPASS", CLOCK_ENABLE_OUTPUT_A = "BYPASS", CLOCK_ENABLE_OUTPUT_B = "BYPASS", INDATA_REG_B = "CLOCK1", INTENDED_DEVICE_FAMILY = "Cyclone III", LPM_TYPE = "altsyncram", NUMWORDS_A = 16, NUMWORDS_B = 16, OPERATION_MODE = "BIDIR_DUAL_PORT", OUTDATA_ACLR_A = "NONE", OUTDATA_ACLR_B = "NONE", OUTDATA_REG_A = "UNREGISTERED", OUTDATA_REG_B = "UNREGISTERED", POWER_UP_UNINITIALIZED = "FALSE", READ_DURING_WRITE_MODE_PORT_A = "NEW_DATA_WITH_NBE_READ", READ_DURING_WRITE_MODE_PORT_B = "NEW_DATA_WITH_NBE_READ", WIDTHAD_A = 4, WIDTHAD_B = 4, WIDTH_A = 16, WIDTH_B = 16, WIDTH_BYTEENA_A = 2, WIDTH_BYTEENA_B = 1, WRCONTROL_WRADDRESS_REG_B = "CLOCK1" ); BEGIN q_a[15..0] = altsyncram_component.q_a[15..0]; q_b[15..0] = altsyncram_component.q_b[15..0]; altsyncram_component.wren_a = wren_a; altsyncram_component.clock0 = clock_a; altsyncram_component.wren_b = wren_b; altsyncram_component.clock1 = clock_b; altsyncram_component.byteena_a[1..0] = byteena_a[1..0]; altsyncram_component.address_a[3..0] = address_a[3..0]; altsyncram_component.address_b[3..0] = address_b[3..0]; altsyncram_component.data_a[15..0] = data_a[15..0]; altsyncram_component.data_b[15..0] = data_b[15..0]; END; -- ============================================================ -- CNX file retrieval info -- ============================================================ -- Retrieval info: PRIVATE: ADDRESSSTALL_A NUMERIC "0" -- Retrieval info: PRIVATE: ADDRESSSTALL_B NUMERIC "0" -- Retrieval info: PRIVATE: BYTEENA_ACLR_A NUMERIC "0" -- Retrieval info: PRIVATE: BYTEENA_ACLR_B NUMERIC "0" -- Retrieval info: PRIVATE: BYTE_ENABLE_A NUMERIC "1" -- Retrieval info: PRIVATE: BYTE_ENABLE_B NUMERIC "0" -- Retrieval info: PRIVATE: BYTE_SIZE NUMERIC "8" -- Retrieval info: PRIVATE: BlankMemory NUMERIC "1" -- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_A NUMERIC "0" -- Retrieval info: PRIVATE: CLOCK_ENABLE_INPUT_B NUMERIC "0" -- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_A NUMERIC "0" -- Retrieval info: PRIVATE: CLOCK_ENABLE_OUTPUT_B NUMERIC "0" -- Retrieval info: PRIVATE: CLRdata NUMERIC "0" -- Retrieval info: PRIVATE: CLRq NUMERIC "0" -- Retrieval info: PRIVATE: CLRrdaddress NUMERIC "0" -- Retrieval info: PRIVATE: CLRrren NUMERIC "0" -- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0" -- Retrieval info: PRIVATE: CLRwren NUMERIC "0" -- Retrieval info: PRIVATE: Clock NUMERIC "5" -- Retrieval info: PRIVATE: Clock_A NUMERIC "0" -- Retrieval info: PRIVATE: Clock_B NUMERIC "0" -- Retrieval info: PRIVATE: ECC NUMERIC "0" -- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0" -- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0" -- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1" -- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A" -- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0" -- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0" -- Retrieval info: PRIVATE: JTAG_ID STRING "NONE" -- Retrieval info: PRIVATE: MAXIMUM_DEPTH NUMERIC "0" -- Retrieval info: PRIVATE: MEMSIZE NUMERIC "256" -- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0" -- Retrieval info: PRIVATE: MIFfilename STRING "" -- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3" -- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0" -- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0" -- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0" -- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2" -- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "4" -- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "4" -- Retrieval info: PRIVATE: REGdata NUMERIC "1" -- Retrieval info: PRIVATE: REGq NUMERIC "0" -- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0" -- Retrieval info: PRIVATE: REGrren NUMERIC "0" -- Retrieval info: PRIVATE: REGwraddress NUMERIC "1" -- Retrieval info: PRIVATE: REGwren NUMERIC "1" -- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0" -- Retrieval info: PRIVATE: USE_DIFF_CLKEN NUMERIC "0" -- Retrieval info: PRIVATE: UseDPRAM NUMERIC "1" -- Retrieval info: PRIVATE: VarWidth NUMERIC "0" -- Retrieval info: PRIVATE: WIDTH_READ_A NUMERIC "16" -- Retrieval info: PRIVATE: WIDTH_READ_B NUMERIC "16" -- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16" -- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16" -- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0" -- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1" -- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0" -- Retrieval info: PRIVATE: enable NUMERIC "0" -- Retrieval info: PRIVATE: rden NUMERIC "0" -- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1" -- Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8" -- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS" -- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS" -- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS" -- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS" -- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1" -- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III" -- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram" -- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16" -- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16" -- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT" -- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE" -- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE" -- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED" -- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED" -- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE" -- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_WITH_NBE_READ" -- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_WITH_NBE_READ" -- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "4" -- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "4" -- Retrieval info: CONSTANT: WIDTH_A NUMERIC "16" -- Retrieval info: CONSTANT: WIDTH_B NUMERIC "16" -- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "2" -- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1" -- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1" -- Retrieval info: USED_PORT: address_a 0 0 4 0 INPUT NODEFVAL address_a[3..0] -- Retrieval info: USED_PORT: address_b 0 0 4 0 INPUT NODEFVAL address_b[3..0] -- Retrieval info: USED_PORT: byteena_a 0 0 2 0 INPUT VCC byteena_a[1..0] -- Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC clock_a -- Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL clock_b -- Retrieval info: USED_PORT: data_a 0 0 16 0 INPUT NODEFVAL data_a[15..0] -- Retrieval info: USED_PORT: data_b 0 0 16 0 INPUT NODEFVAL data_b[15..0] -- Retrieval info: USED_PORT: q_a 0 0 16 0 OUTPUT NODEFVAL q_a[15..0] -- Retrieval info: USED_PORT: q_b 0 0 16 0 OUTPUT NODEFVAL q_b[15..0] -- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND wren_a -- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND wren_b -- Retrieval info: CONNECT: @data_a 0 0 16 0 data_a 0 0 16 0 -- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0 -- Retrieval info: CONNECT: q_a 0 0 16 0 @q_a 0 0 16 0 -- Retrieval info: CONNECT: q_b 0 0 16 0 @q_b 0 0 16 0 -- Retrieval info: CONNECT: @address_a 0 0 4 0 address_a 0 0 4 0 -- Retrieval info: CONNECT: @data_b 0 0 16 0 data_b 0 0 16 0 -- Retrieval info: CONNECT: @address_b 0 0 4 0 address_b 0 0 4 0 -- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0 -- Retrieval info: CONNECT: @byteena_a 0 0 2 0 byteena_a 0 0 2 0 -- Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0 -- Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0 -- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all -- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0.tdf TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0.inc TRUE -- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0.cmp FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0.bsf FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0_inst.tdf FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0_waveforms.html FALSE -- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0_wave*.jpg FALSE -- Retrieval info: LIB_FILE: altera_mf