create datestamp on the fly during compilation

FPGA_by_Fredi/.gitignore

@@ -1,6 +1,8 @@
-
+datetime.vhd
 db
 incremental_db
+greybox_tmp
+*.bak
 *.rpt
 *.summary
 *.sof
@@ -8,5 +10,6 @@ incremental_db
 *.pin
 *.smsg
 *.jdi
+*.cdf
 PLLJ_PLLSPE_INFO.txt
 

FPGA_by_Fredi/FPGA_DATE.inc

@@ -1,23 +0,0 @@
---Copyright (C) 1991-2010 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
-
-
-FUNCTION FPGA_DATE 
-(
-
-)
-
-RETURNS (
-	result[31..0]
-);

FPGA_by_Fredi/FPGA_DATE.qip

@@ -1,5 +0,0 @@
-set_global_assignment -name IP_TOOL_NAME "LPM_CONSTANT"
-set_global_assignment -name IP_TOOL_VERSION "9.1"
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "FPGA_DATE.tdf"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "FPGA_DATE.bsf"]
-set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "FPGA_DATE.inc"]

FPGA_by_Fredi/FPGA_DATE.tdf

@@ -1,79 +0,0 @@
--- megafunction wizard: %LPM_CONSTANT%
--- GENERATION: STANDARD
--- VERSION: WM1.0
--- MODULE: lpm_constant 
-
--- ============================================================
--- File Name: FPGA_DATE.tdf
--- Megafunction Name(s):
--- 			lpm_constant
---
--- Simulation Library Files(s):
--- 			
--- ============================================================
--- ************************************************************
--- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
---
--- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
--- ************************************************************
-
-
---Copyright (C) 1991-2010 Altera Corporation
---Your use of Altera Corporation's design tools, logic functions 
---and other software and tools, and its AMPP partner logic 
---functions, and any output files from any of the foregoing 
---(including device programming or simulation files), and any 
---associated documentation or information are expressly subject 
---to the terms and conditions of the Altera Program License 
---Subscription Agreement, Altera MegaCore Function License 
---Agreement, or other applicable license agreement, including, 
---without limitation, that your use is for the sole purpose of 
---programming logic devices manufactured by Altera and sold by 
---Altera or its authorized distributors.  Please refer to the 
---applicable agreement for further details.
-
--- Clearbox generated function header
-FUNCTION FPGA_DATE_lpm_constant_f19 ()
-RETURNS ( result[31..0]);
-
-
-
-
-SUBDESIGN FPGA_DATE
-(
-	result[31..0]	 : OUTPUT;
-)
-
-VARIABLE
-
-	FPGA_DATE_lpm_constant_f19_component : FPGA_DATE_lpm_constant_f19;
-
-BEGIN
-
-	result[31..0] = FPGA_DATE_lpm_constant_f19_component.result[31..0];
-END;
-
-
-
--- ============================================================
--- CNX file retrieval info
--- ============================================================
--- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
--- Retrieval info: PRIVATE: JTAG_ENABLED NUMERIC "0"
--- Retrieval info: PRIVATE: JTAG_ID STRING "NONE"
--- Retrieval info: PRIVATE: Radix NUMERIC "16"
--- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
--- Retrieval info: PRIVATE: Value NUMERIC "570826775"
--- Retrieval info: PRIVATE: nBit NUMERIC "32"
--- Retrieval info: CONSTANT: LPM_CVALUE NUMERIC "570826775"
--- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
--- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CONSTANT"
--- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
--- Retrieval info: USED_PORT: result 0 0 32 0 OUTPUT NODEFVAL result[31..0]
--- Retrieval info: CONNECT: result 0 0 32 0 @result 0 0 32 0
--- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
--- Retrieval info: GEN_FILE: TYPE_NORMAL FPGA_DATE.tdf TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL FPGA_DATE.inc TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL FPGA_DATE.cmp FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL FPGA_DATE.bsf TRUE FALSE
--- Retrieval info: GEN_FILE: TYPE_NORMAL FPGA_DATE_inst.tdf FALSE

FPGA_by_Fredi/FPGA_DATE_lpm_constant_e19.tdf

@@ -1,30 +0,0 @@
---lpm_constant CBX_AUTO_BLACKBOX="ALL" ENABLE_RUNTIME_MOD="NO" LPM_CVALUE=21062017 LPM_WIDTH=32 result
---VERSION_BEGIN 9.1SP2 cbx_lpm_constant 2010:03:24:20:43:43:SJ cbx_mgl 2010:03:24:21:01:05:SJ  VERSION_END
-
-
--- Copyright (C) 1991-2010 Altera Corporation
---  Your use of Altera Corporation's design tools, logic functions 
---  and other software and tools, and its AMPP partner logic 
---  functions, and any output files from any of the foregoing 
---  (including device programming or simulation files), and any 
---  associated documentation or information are expressly subject 
---  to the terms and conditions of the Altera Program License 
---  Subscription Agreement, Altera MegaCore Function License 
---  Agreement, or other applicable license agreement, including, 
---  without limitation, that your use is for the sole purpose of 
---  programming logic devices manufactured by Altera and sold by 
---  Altera or its authorized distributors.  Please refer to the 
---  applicable agreement for further details.
-
-
-
---synthesis_resources = 
-SUBDESIGN FPGA_DATE_lpm_constant_e19
-( 
-	result[31..0]	:	output;
-) 
-
-BEGIN 
-	result[] = B"00100001000001100010000000010111";
-END;
---VALID FILE

FPGA_by_Fredi/FPGA_DATE_lpm_constant_f19.tdf

@@ -1,30 +0,0 @@
---lpm_constant CBX_AUTO_BLACKBOX="ALL" ENABLE_RUNTIME_MOD="NO" LPM_CVALUE=22062017 LPM_WIDTH=32 result
---VERSION_BEGIN 9.1SP2 cbx_lpm_constant 2010:03:24:20:43:43:SJ cbx_mgl 2010:03:24:21:01:05:SJ  VERSION_END
-
-
--- Copyright (C) 1991-2010 Altera Corporation
---  Your use of Altera Corporation's design tools, logic functions 
---  and other software and tools, and its AMPP partner logic 
---  functions, and any output files from any of the foregoing 
---  (including device programming or simulation files), and any 
---  associated documentation or information are expressly subject 
---  to the terms and conditions of the Altera Program License 
---  Subscription Agreement, Altera MegaCore Function License 
---  Agreement, or other applicable license agreement, including, 
---  without limitation, that your use is for the sole purpose of 
---  programming logic devices manufactured by Altera and sold by 
---  Altera or its authorized distributors.  Please refer to the 
---  applicable agreement for further details.
-
-
-
---synthesis_resources = 
-SUBDESIGN FPGA_DATE_lpm_constant_f19
-( 
-	result[31..0]	:	output;
-) 
-
-BEGIN 
-	result[] = B"00100010000001100010000000010111";
-END;
---VALID FILE

FPGA_by_Fredi/FPGA_DATE_lpm_constant_g19.tdf

@@ -1,30 +0,0 @@
---lpm_constant CBX_AUTO_BLACKBOX="ALL" ENABLE_RUNTIME_MOD="NO" LPM_CVALUE=05062017 LPM_WIDTH=32 result
---VERSION_BEGIN 9.1SP2 cbx_lpm_constant 2010:03:24:20:43:43:SJ cbx_mgl 2010:03:24:21:01:05:SJ  VERSION_END
-
-
--- Copyright (C) 1991-2010 Altera Corporation
---  Your use of Altera Corporation's design tools, logic functions 
---  and other software and tools, and its AMPP partner logic 
---  functions, and any output files from any of the foregoing 
---  (including device programming or simulation files), and any 
---  associated documentation or information are expressly subject 
---  to the terms and conditions of the Altera Program License 
---  Subscription Agreement, Altera MegaCore Function License 
---  Agreement, or other applicable license agreement, including, 
---  without limitation, that your use is for the sole purpose of 
---  programming logic devices manufactured by Altera and sold by 
---  Altera or its authorized distributors.  Please refer to the 
---  applicable agreement for further details.
-
-
-
---synthesis_resources = 
-SUBDESIGN FPGA_DATE_lpm_constant_g19
-( 
-	result[31..0]	:	output;
-) 
-
-BEGIN 
-	result[] = B"00000101000001100010000000010111";
-END;
---VALID FILE

FPGA_by_Fredi/altpll1.bsf

@@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in
 the Block Editor! File corruption is VERY likely to occur.
 */
 /*
-Copyright (C) 1991-2010 Altera Corporation
+Copyright (C) 1991-2014 Altera Corporation
 Your use of Altera Corporation's design tools, logic functions 
 and other software and tools, and its AMPP partner logic 
 functions, and any output files from any of the foregoing 
@@ -18,83 +18,83 @@ programming logic devices manufactured by Altera and sold by
 Altera or its authorized distributors.  Please refer to the 
 applicable agreement for further details.
 */
-(header "symbol" (version "1.1"))
+(header "symbol" (version "1.2"))
 (symbol
-	(rect 0 0 272 184)
+	(rect 0 0 272 176)
-	(text "altpll1" (rect 119 0 159 16)(font "Arial" (font_size 10)))
+	(text "altpll1" (rect 119 0 160 16)(font "Arial" (font_size 10)))
-	(text "inst" (rect 8 168 25 180)(font "Arial" ))
+	(text "inst" (rect 8 161 26 172)(font "Arial" ))
 	(port
 		(pt 0 64)
 		(input)
-		(text "inclk0" (rect 0 0 31 14)(font "Arial" (font_size 8)))
+		(text "inclk0" (rect 0 0 34 13)(font "Arial" (font_size 8)))
-		(text "inclk0" (rect 4 51 31 64)(font "Arial" (font_size 8)))
+		(text "inclk0" (rect 4 51 31 63)(font "Arial" (font_size 8)))
-		(line (pt 0 64)(pt 40 64)(line_width 1))
+		(line (pt 0 64)(pt 40 64))
 	)
 	(port
 		(pt 272 64)
 		(output)
-		(text "c0" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+		(text "c0" (rect 0 0 15 13)(font "Arial" (font_size 8)))
-		(text "c0" (rect 257 51 268 64)(font "Arial" (font_size 8)))
+		(text "c0" (rect 257 51 269 63)(font "Arial" (font_size 8)))
-		(line (pt 272 64)(pt 224 64)(line_width 1))
 	)
 	(port
 		(pt 272 80)
 		(output)
-		(text "c1" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+		(text "c1" (rect 0 0 14 13)(font "Arial" (font_size 8)))
-		(text "c1" (rect 257 67 268 80)(font "Arial" (font_size 8)))
+		(text "c1" (rect 257 67 267 79)(font "Arial" (font_size 8)))
-		(line (pt 272 80)(pt 224 80)(line_width 1))
 	)
 	(port
 		(pt 272 96)
 		(output)
-		(text "c2" (rect 0 0 14 14)(font "Arial" (font_size 8)))
+		(text "c2" (rect 0 0 15 13)(font "Arial" (font_size 8)))
-		(text "c2" (rect 257 83 268 96)(font "Arial" (font_size 8)))
+		(text "c2" (rect 257 83 269 95)(font "Arial" (font_size 8)))
-		(line (pt 272 96)(pt 224 96)(line_width 1))
 	)
 	(port
 		(pt 272 112)
 		(output)
-		(text "locked" (rect 0 0 36 14)(font "Arial" (font_size 8)))
+		(text "locked" (rect 0 0 37 13)(font "Arial" (font_size 8)))
-		(text "locked" (rect 238 99 268 112)(font "Arial" (font_size 8)))
+		(text "locked" (rect 237 99 268 111)(font "Arial" (font_size 8)))
-		(line (pt 272 112)(pt 224 112)(line_width 1))
 	)
 	(drawing
-		(text "Cyclone III" (rect 211 169 258 181)(font "Arial" ))
+		(text "Cyclone III" (rect 214 162 474 334)(font "Arial" ))
-		(text "inclk0 frequency: 33.000 MHz" (rect 50 59 175 71)(font "Arial" ))
+		(text "inclk0 frequency: 33.000 MHz" (rect 50 60 226 130)(font "Arial" ))
-		(text "Operation Mode: Src Sync Comp" (rect 50 73 188 85)(font "Arial" ))
+		(text "Operation Mode: Src Sync Comp" (rect 50 72 239 154)(font "Arial" ))
-		(text "Clk " (rect 51 96 68 108)(font "Arial" ))
+		(text "Clk " (rect 51 91 117 192)(font "Arial" ))
-		(text "Ratio" (rect 83 96 105 108)(font "Arial" ))
+		(text "Ratio" (rect 71 91 165 192)(font "Arial" ))
-		(text "Ph (dg)" (rect 121 96 151 108)(font "Arial" ))
+		(text "Ph (dg)" (rect 98 91 227 192)(font "Arial" ))
-		(text "DC (%)" (rect 156 96 187 108)(font "Arial" ))
+		(text "DC (%)" (rect 133 91 298 192)(font "Arial" ))
-		(text "c0" (rect 54 111 64 123)(font "Arial" ))
+		(text "c0" (rect 54 104 119 218)(font "Arial" ))
-		(text "16/11" (rect 83 111 106 123)(font "Arial" ))
+		(text "16/11" (rect 71 104 164 218)(font "Arial" ))
-		(text "0.00" (rect 127 111 145 123)(font "Arial" ))
+		(text "0.00" (rect 104 104 227 218)(font "Arial" ))
-		(text "50.00" (rect 160 111 183 123)(font "Arial" ))
+		(text "50.00" (rect 137 104 298 218)(font "Arial" ))
-		(text "c1" (rect 54 126 64 138)(font "Arial" ))
+		(text "c1" (rect 54 117 118 244)(font "Arial" ))
-		(text "16/33" (rect 83 126 106 138)(font "Arial" ))
+		(text "16/33" (rect 71 117 165 244)(font "Arial" ))
-		(text "0.00" (rect 127 126 145 138)(font "Arial" ))
+		(text "0.00" (rect 104 117 227 244)(font "Arial" ))
-		(text "50.00" (rect 160 126 183 138)(font "Arial" ))
+		(text "50.00" (rect 137 117 298 244)(font "Arial" ))
-		(text "c2" (rect 54 141 64 153)(font "Arial" ))
+		(text "c2" (rect 54 130 119 270)(font "Arial" ))
-		(text "1024/1375" (rect 73 141 116 153)(font "Arial" ))
+		(text "32/43" (rect 71 130 166 270)(font "Arial" ))
-		(text "0.00" (rect 127 141 145 153)(font "Arial" ))
+		(text "0.00" (rect 104 130 227 270)(font "Arial" ))
-		(text "50.00" (rect 160 141 183 153)(font "Arial" ))
+		(text "50.00" (rect 137 130 298 270)(font "Arial" ))
-		(line (pt 0 0)(pt 273 0)(line_width 1))
+		(line (pt 0 0)(pt 273 0))
-		(line (pt 273 0)(pt 273 185)(line_width 1))
+		(line (pt 273 0)(pt 273 177))
-		(line (pt 0 185)(pt 273 185)(line_width 1))
+		(line (pt 0 177)(pt 273 177))
-		(line (pt 0 0)(pt 0 185)(line_width 1))
+		(line (pt 0 0)(pt 0 177))
-		(line (pt 48 94)(pt 189 94)(line_width 1))
+		(line (pt 48 89)(pt 165 89))
-		(line (pt 48 108)(pt 189 108)(line_width 1))
+		(line (pt 48 101)(pt 165 101))
-		(line (pt 48 123)(pt 189 123)(line_width 1))
+		(line (pt 48 114)(pt 165 114))
-		(line (pt 48 138)(pt 189 138)(line_width 1))
+		(line (pt 48 127)(pt 165 127))
-		(line (pt 48 153)(pt 189 153)(line_width 1))
+		(line (pt 48 140)(pt 165 140))
-		(line (pt 48 94)(pt 48 153)(line_width 1))
+		(line (pt 48 89)(pt 48 140))
-		(line (pt 70 94)(pt 70 153)(line_width 3))
+		(line (pt 68 89)(pt 68 140)(line_width 3))
-		(line (pt 118 94)(pt 118 153)(line_width 3))
+		(line (pt 95 89)(pt 95 140)(line_width 3))
-		(line (pt 153 94)(pt 153 153)(line_width 3))
+		(line (pt 130 89)(pt 130 140)(line_width 3))
-		(line (pt 188 94)(pt 188 153)(line_width 1))
+		(line (pt 164 89)(pt 164 140))
-		(line (pt 40 48)(pt 224 48)(line_width 1))
+		(line (pt 40 48)(pt 223 48))
-		(line (pt 224 48)(pt 224 168)(line_width 1))
+		(line (pt 223 48)(pt 223 159))
-		(line (pt 40 168)(pt 224 168)(line_width 1))
+		(line (pt 40 159)(pt 223 159))
-		(line (pt 40 48)(pt 40 168)(line_width 1))
+		(line (pt 40 48)(pt 40 159))
+		(line (pt 271 64)(pt 223 64))
+		(line (pt 271 80)(pt 223 80))
+		(line (pt 271 96)(pt 223 96))
+		(line (pt 271 112)(pt 223 112))
 	)
 )

FPGA_by_Fredi/altpll1.cmp

@@ -1,4 +1,4 @@
---Copyright (C) 1991-2010 Altera Corporation
+--Copyright (C) 1991-2014 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 

FPGA_by_Fredi/altpll1.inc

@@ -1,4 +1,4 @@
---Copyright (C) 1991-2010 Altera Corporation
+--Copyright (C) 1991-2014 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 

FPGA_by_Fredi/altpll1.qip

@@ -1,5 +1,5 @@
 set_global_assignment -name IP_TOOL_NAME "ALTPLL"
-set_global_assignment -name IP_TOOL_VERSION "9.1"
+set_global_assignment -name IP_TOOL_VERSION "13.1"
 set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll1.vhd"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.bsf"]
 set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll1.inc"]

FPGA_by_Fredi/altpll1.vhd

@@ -14,11 +14,11 @@
 -- ************************************************************
 -- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
 --
--- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
+-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
 -- ************************************************************
 
 
---Copyright (C) 1991-2010 Altera Corporation
+--Copyright (C) 1991-2014 Altera Corporation
 --Your use of Altera Corporation's design tools, logic functions 
 --and other software and tools, and its AMPP partner logic 
 --functions, and any output files from any of the foregoing 
@@ -131,22 +131,22 @@ ARCHITECTURE SYN OF altpll1 IS
 		width_clock		: NATURAL
 	);
 	PORT (
+			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
 			inclk	: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
-			locked	: OUT STD_LOGIC ;
+			locked	: OUT STD_LOGIC 
-			clk	: OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
 	);
 	END COMPONENT;
 
 BEGIN
 	sub_wire7_bv(0 DOWNTO 0) <= "0";
 	sub_wire7    <= To_stdlogicvector(sub_wire7_bv);
-	sub_wire3    <= sub_wire0(2);
+	sub_wire4    <= sub_wire0(2);
-	sub_wire2    <= sub_wire0(1);
+	sub_wire3    <= sub_wire0(0);
-	sub_wire1    <= sub_wire0(0);
+	sub_wire1    <= sub_wire0(1);
-	c0    <= sub_wire1;
+	c1    <= sub_wire1;
-	c1    <= sub_wire2;
+	locked    <= sub_wire2;
-	c2    <= sub_wire3;
+	c0    <= sub_wire3;
-	locked    <= sub_wire4;
+	c2    <= sub_wire4;
 	sub_wire5    <= inclk0;
 	sub_wire6    <= sub_wire7(0 DOWNTO 0) & sub_wire5;
 
@@ -161,9 +161,9 @@ BEGIN
 		clk1_duty_cycle => 50,
 		clk1_multiply_by => 16,
 		clk1_phase_shift => "0",
-		clk2_divide_by => 1375,
+		clk2_divide_by => 43,
 		clk2_duty_cycle => 50,
-		clk2_multiply_by => 1024,
+		clk2_multiply_by => 32,
 		clk2_phase_shift => "0",
 		compensate_clock => "CLK0",
 		inclk0_input_frequency => 30303,
@@ -218,7 +218,7 @@ BEGIN
 	PORT MAP (
 		inclk => sub_wire6,
 		clk => sub_wire0,
-		locked => sub_wire4
+		locked => sub_wire2
 	);
 
 
@@ -246,13 +246,13 @@ END SYN;
 -- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
 -- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "1"
 -- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "900"
--- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "90"
+-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "43"
 -- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
 -- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
 -- Retrieval info: PRIVATE: DUTY_CYCLE2 STRING "50.00000000"
 -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "48.000000"
 -- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "16.000000"
--- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "24.576000"
+-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "24.558140"
 -- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
 -- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
 -- Retrieval info: PRIVATE: GLOCKED_COUNTER_EDIT_CHANGED STRING "1"
@@ -270,7 +270,7 @@ END SYN;
 -- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
 -- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "1"
 -- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
--- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "330.000"
+-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
 -- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
 -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "ps"
 -- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
@@ -281,14 +281,14 @@ END SYN;
 -- Retrieval info: PRIVATE: MIRROR_CLK2 STRING "0"
 -- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "1"
 -- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "67"
--- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "67"
+-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "32"
 -- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "48.00000000"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ1 STRING "16.00000000"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ2 STRING "24.57600000"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE0 STRING "1"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE1 STRING "1"
--- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "1"
+-- Retrieval info: PRIVATE: OUTPUT_FREQ_MODE2 STRING "0"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT0 STRING "MHz"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT1 STRING "MHz"
 -- Retrieval info: PRIVATE: OUTPUT_FREQ_UNIT2 STRING "MHz"
@@ -346,9 +346,9 @@ END SYN;
 -- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
 -- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "16"
 -- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
--- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "1375"
+-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "43"
 -- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
--- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "1024"
+-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "32"
 -- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
 -- Retrieval info: CONSTANT: COMPENSATE_CLOCK STRING "CLK0"
 -- Retrieval info: CONSTANT: INCLK0_INPUT_FREQUENCY NUMERIC "30303"
@@ -406,17 +406,17 @@ END SYN;
 -- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
 -- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
 -- Retrieval info: USED_PORT: locked 0 0 0 0 OUTPUT GND "locked"
--- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
+-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
 -- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
 -- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
 -- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
 -- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
--- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
+-- Retrieval info: CONNECT: locked 0 0 0 0 @locked 0 0 0 0
 -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.vhd TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.ppf TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.inc TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.cmp TRUE
--- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.bsf TRUE FALSE
+-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1.bsf TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_inst.vhd FALSE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_waveforms.html TRUE
 -- Retrieval info: GEN_FILE: TYPE_NORMAL altpll1_wave*.jpg FALSE

FPGA_by_Fredi/compile_date.bsf

@@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in
 the Block Editor! File corruption is VERY likely to occur.
 */
 /*
-Copyright (C) 1991-2010 Altera Corporation
+Copyright (C) 1991-2014 Altera Corporation
 Your use of Altera Corporation's design tools, logic functions 
 and other software and tools, and its AMPP partner logic 
 functions, and any output files from any of the foregoing 
@@ -20,23 +20,10 @@ applicable agreement for further details.
 */
 (header "symbol" (version "1.1"))
 (symbol
-	(rect 0 0 88 48)
+	(rect 16 16 64 64)
-	(text "FPGA_DATE" (rect 6 1 96 17)(font "Arial" (font_size 10)))
+	(text "compile_date" (rect 5 0 56 12)(font "Arial" ))
-	(text "inst" (rect 8 32 25 44)(font "Arial" ))
+	(text "inst" (rect 8 32 20 44)(font "Arial" ))
-	(port
-		(pt 88 24)
-		(output)
-		(text "result[31..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
-		(text "result[31..0]" (rect 85 -31 98 24)(font "Arial" (font_size 8))(invisible))
-		(line (pt 88 24)(pt 72 24)(line_width 3))
-	)
 	(drawing
-		(text "570826775" (rect 27 18 72 30)(font "Arial" ))
+		(rectangle (rect 16 16 32 32)(line_width 1))
-		(text "32" (rect 77 25 87 37)(font "Arial" ))
-		(line (pt 16 16)(pt 72 16)(line_width 1))
-		(line (pt 72 16)(pt 72 32)(line_width 1))
-		(line (pt 72 32)(pt 16 32)(line_width 1))
-		(line (pt 16 32)(pt 16 16)(line_width 1))
-		(line (pt 72 28)(pt 80 20)(line_width 1))
 	)
 )

FPGA_by_Fredi/compile_date.vhd

@@ -0,0 +1,15 @@
+library ieee;
+use ieee.std_logic_1164.all;
+use work.datetime.all;
+
+entity compile_date is
+    port
+    (
+        datetime    : out std_ulogic_vector(31 downto 0)
+    );
+end entity compile_date;
+
+architecture rtl of compile_date is
+begin
+    datetime <= work.datetime.DATE_HEX_DMY;
+end architecture rtl;

FPGA_by_Fredi/firebee1.done

@@ -1 +1 @@
-Wed Aug 28 16:04:24 2019
+Sun Jul 11 19:34:46 2021

FPGA_by_Fredi/firebee1.qsf

@@ -35,13 +35,14 @@
 #
 # -------------------------------------------------------------------------- #
 
+set_global_assignment -name PRE_FLOW_SCRIPT_FILE "quartus_sh:precmd.tcl"
 
 
 # Project-Wide Assignments
 # ========================
 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 8.1
 set_global_assignment -name PROJECT_CREATION_TIME_DATE "10:07:29  SEPTEMBER 03, 2009"
-set_global_assignment -name LAST_QUARTUS_VERSION 8.1
+set_global_assignment -name LAST_QUARTUS_VERSION 13.1
 set_global_assignment -name MISC_FILE "C:/firebee/FPGA/firebee1.dpf"
 
 # Pin & Location Assignments
@@ -348,7 +349,6 @@ set_global_assignment -name TSU_REQUIREMENT "1 ns"
 set_global_assignment -name TCO_REQUIREMENT "1 ns"
 set_global_assignment -name TH_REQUIREMENT "1 ns"
 set_global_assignment -name FMAX_REQUIREMENT "33 MHz"
-set_global_assignment -name USE_TIMEQUEST_TIMING_ANALYZER OFF
 
 # Analysis & Synthesis Assignments
 # ================================
@@ -635,6 +635,29 @@ set_instance_assignment -name IO_STANDARD "3.0-V LVCMOS" -to IO[8]
 set_instance_assignment -name SLEW_RATE 0 -to LP_D
 set_instance_assignment -name SLEW_RATE 0 -to LP_STR
 set_instance_assignment -name SLEW_RATE 0 -to LPDIR
+set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS ON
+set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS ON
+set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK ON
+set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS ON
+set_global_assignment -name FMAX_REQUIREMENT "33 MHz" -section_id Main
+set_instance_assignment -name CLOCK_SETTINGS Main -to MAIN_CLK
+set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "Design Compiler"
+set_global_assignment -name EDA_INPUT_VCC_NAME VDD -section_id eda_design_synthesis
+set_global_assignment -name EDA_LMF_FILE altsyn.lmf -section_id eda_design_synthesis
+set_global_assignment -name EDA_INPUT_DATA_FORMAT EDIF -section_id eda_design_synthesis
+set_global_assignment -name TIMEQUEST_DO_REPORT_TIMING ON
+set_global_assignment -name SYNCHRONIZER_IDENTIFICATION OFF
+set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
+set_instance_assignment -name AUTO_GLOBAL_CLOCK ON -to MAIN_CLK
+set_location_assignment PLL_1 -to "altpll3:inst13|altpll:altpll_component|altpll_9j03:auto_generated|pll1"
+set_location_assignment PLL_3 -to "altpll2:inst12|altpll:altpll_component|altpll_1r33:auto_generated|pll1"
+set_location_assignment PLL_2 -to "altpll4:inst22|altpll:altpll_component|altpll_r4n2:auto_generated|pll1"
+
+set_location_assignment PLL_4 -to "altpll1:inst|altpll:altpll_component|altpll_hsp2:auto_generated|pll1"
+
+set_global_assignment -name SDC_FILE firebee1.sdc
+set_global_assignment -name VHDL_FILE compile_date.vhd
+set_global_assignment -name VHDL_FILE datetime.vhd
 set_global_assignment -name SOURCE_FILE Video/BLITTER/lpm_ror128.cmp
 set_global_assignment -name AHDL_FILE Video/BLITTER/lpm_ror128.tdf
 set_global_assignment -name AHDL_FILE Video/BLITTER/lpm_clshift144.tdf
@@ -753,8 +776,8 @@ set_global_assignment -name SOURCE_FILE altpll1.cmp
 set_global_assignment -name BDF_FILE firebee1.bdf
 set_global_assignment -name QIP_FILE altpll0.qip
 set_global_assignment -name QIP_FILE lpm_counter0.qip
-set_global_assignment -name VHDL_FILE "FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd"
+set_global_assignment -name VHDL_FILE FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd
-set_global_assignment -name VHDL_FILE "DSP/DSP.vhd"
+set_global_assignment -name VHDL_FILE DSP/DSP.vhd
 set_global_assignment -name QIP_FILE Video/lpm_shiftreg0.qip
 set_global_assignment -name QIP_FILE Video/altdpram0.qip
 set_global_assignment -name QIP_FILE Video/lpm_bustri1.qip
@@ -777,7 +800,7 @@ set_global_assignment -name QIP_FILE Video/lpm_latch1.qip
 set_global_assignment -name QIP_FILE Video/lpm_constant4.qip
 set_global_assignment -name QIP_FILE Video/lpm_shiftreg2.qip
 set_global_assignment -name QIP_FILE Video/lpm_compare1.qip
-set_global_assignment -name AHDL_FILE "Interrupt_Handler/interrupt_handler.tdf"
+set_global_assignment -name AHDL_FILE Interrupt_Handler/interrupt_handler.tdf
 set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip
 set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip
 set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip
@@ -801,7 +824,6 @@ set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo0.qip
 set_global_assignment -name QIP_FILE FalconIO_SDCard_IDE_CF/dcfifo1.qip
 set_global_assignment -name QIP_FILE Video/lpm_muxDZ.qip
 set_global_assignment -name QIP_FILE Video/lpm_muxVDM.qip
-set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt
 set_global_assignment -name QIP_FILE altpll_reconfig1.qip
 set_global_assignment -name QIP_FILE altpll4.qip
 set_global_assignment -name QIP_FILE lpm_mux0.qip
@@ -819,10 +841,4 @@ set_global_assignment -name QIP_FILE FPGA_DATE.qip
 set_global_assignment -name QIP_FILE Video/Doppelzeilen_Fifo.qip
 set_global_assignment -name QIP_FILE Video/shiftreg_dpz.qip
 set_global_assignment -name QIP_FILE Video/BLITTER/lpm_ror128.qip
-set_global_assignment -name CUT_OFF_PATHS_BETWEEN_CLOCK_DOMAINS ON
-set_global_assignment -name CUT_OFF_READ_DURING_WRITE_PATHS ON
-set_global_assignment -name CUT_OFF_IO_PIN_FEEDBACK ON
-set_global_assignment -name ANALYZE_LATCHES_AS_SYNCHRONOUS_ELEMENTS ON
-set_global_assignment -name FMAX_REQUIREMENT "33 MHz" -section_id Main
-set_instance_assignment -name CLOCK_SETTINGS Main -to MAIN_CLK
 set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

FPGA_by_Fredi/firebee1.sdc

@@ -0,0 +1,155 @@
+## Generated SDC file "D:/Download/firebee1.out.sdc"
+
+## Copyright (C) 1991-2010 Altera Corporation
+## Your use of Altera Corporation's design tools, logic functions 
+## and other software and tools, and its AMPP partner logic 
+## functions, and any output files from any of the foregoing 
+## (including device programming or simulation files), and any 
+## associated documentation or information are expressly subject 
+## to the terms and conditions of the Altera Program License 
+## Subscription Agreement, Altera MegaCore Function License 
+## Agreement, or other applicable license agreement, including, 
+## without limitation, that your use is for the sole purpose of 
+## programming logic devices manufactured by Altera and sold by 
+## Altera or its authorized distributors.  Please refer to the 
+## applicable agreement for further details.
+
+
+## VENDOR  "Altera"
+## PROGRAM "Quartus II"
+## VERSION "Version 9.1 Build 350 03/24/2010 Service Pack 2 SJ Web Edition"
+
+## DATE    "Tue Jun 02 13:09:12 2020"
+
+##
+## DEVICE  "EP3C40F484C6"
+##
+
+
+#**************************************************************
+# Time Information
+#**************************************************************
+
+set_time_format -unit ns -decimal_places 3
+
+
+
+#**************************************************************
+# Create Clock
+#**************************************************************
+
+
+create_clock -name {MAIN_CLK} -period 30.303 -waveform { 0.000 15.151 } [get_ports {MAIN_CLK}]
+
+#create_generated_clock  -multiply_by 4                    -name {CLK_DDR[0]} -phase 240  -source [get_ports {MAIN_CLK}] [get_pins inst12|altpll_component|auto_generated|pll1|clk[0]]
+#create_generated_clock  -multiply_by 4                    -name {CLK_DDR[1]} -phase 0    -source [get_ports {MAIN_CLK}] [get_pins inst12|altpll_component|auto_generated|pll1|clk[1]]
+#create_generated_clock  -multiply_by 4                    -name {CLK_DDR[2]} -phase 180  -source [get_ports {MAIN_CLK}] [get_pins inst12|altpll_component|auto_generated|pll1|clk[2]]
+#create_generated_clock  -multiply_by 4                    -name {CLK_DDR[3]} -phase 105  -source [get_ports {MAIN_CLK}] [get_pins inst12|altpll_component|auto_generated|pll1|clk[3]]
+#create_generated_clock  -multiply_by 2                    -name {CLK_DDR[4]} -phase 270  -source [get_ports {MAIN_CLK}] [get_pins inst12|altpll_component|auto_generated|pll1|clk[4]]
+
+#create_generated_clock  -multiply_by 16   -divide_by 11   -name {CLK_48M}              -source [get_ports {MAIN_CLK}] [get_pins inst|altpll_component|auto_generated|pll1|clk[0]]
+#create_generated_clock  -multiply_by 16   -divide_by 33   -name {CLK_FDC}              -source [get_ports {MAIN_CLK}] [get_pins inst|altpll_component|auto_generated|pll1|clk[1]]
+#create_generated_clock  -multiply_by 32   -divide_by 43   -name {CLK_24M}              -source [get_ports {MAIN_CLK}] [get_pins inst|altpll_component|auto_generated|pll1|clk[2]]
+
+#create_generated_clock  -multiply_by 25   -divide_by 33   -name {CLK_25M}              -source [get_ports {MAIN_CLK}] [get_pins inst13|altpll_component|auto_generated|pll1|clk[0]]
+#create_generated_clock  -multiply_by 2    -divide_by 33   -name {CLK_2M}               -source [get_ports {MAIN_CLK}] [get_pins inst13|altpll_component|auto_generated|pll1|clk[1]]
+#create_generated_clock  -multiply_by 1    -divide_by 66   -name {CLK_500k}             -source [get_ports {MAIN_CLK}] [get_pins inst13|altpll_component|auto_generated|pll1|clk[2]]
+#create_generated_clock  -multiply_by 25   -divide_by 336  -name {CLK_2M4}              -source [get_ports {MAIN_CLK}] [get_pins inst13|altpll_component|auto_generated|pll1|clk[3]]
+
+#create_generated_clock  -multiply_by 2                    -name {CLK_PIXEL}            -source [get_pins inst|altpll_component|auto_generated|pll1|clk[0]] [get_pins inst22|altpll_component|auto_generated|pll1|clk[0]]
+
+# see if Quartus finds even more clocks
+
+derive_pll_clocks -use_net_name
+derive_clocks -period 30.303
+
+#**************************************************************
+# Create Generated Clock
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Latency
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Uncertainty
+#**************************************************************
+
+derive_clock_uncertainty
+
+
+#**************************************************************
+# Set Input Delay
+#**************************************************************
+
+set_input_delay -clock {MAIN_CLK} -max 4 [remove_from_collection [all_inputs] [get_ports {MAIN_CLK}]]
+
+
+#**************************************************************
+# Set Output Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Clock Groups
+#**************************************************************
+
+
+
+#**************************************************************
+# Set False Path
+#**************************************************************
+
+set_false_path -from [get_keepers *0hh1*d_wrptr*] -to [get_keepers *0hh1*dffe13a*]
+set_false_path -from [get_keepers *0hh1*rdptr_g\[*] -to [get_keepers *0hh1*dffe18*]
+set_false_path -from [get_keepers *3fh1*d_wrptr*] -to [get_keepers *3fh1*dffe13a*]
+set_false_path -from [get_keepers *3fh1*rdptr_g\[*] -to [get_keepers *3fh1*15\|dffe16a\[*]
+
+set_false_path -from MAIN_CLK -to altpll4:inst22|altpll:altpll_component|altpll_r4n2:auto_generated|clk[0]
+
+#set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_id9:dffpipe17|dffe18a*}]
+#set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_hd9:dffpipe12|dffe13a*}]
+#set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_kd9:dffpipe15|dffe16a*}]
+#set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a*}]
+#set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_te9:dffpipe20|dffe21a*}]
+
+
+#**************************************************************
+# Set Multicycle Path
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Maximum Delay
+#**************************************************************
+
+# TPD
+set_max_delay -from [all_inputs] -to [all_outputs] 1 
+
+# TSU
+set_max_delay -from [all_inputs] -to [all_registers] 1
+
+# TCO
+set_max_delay -from [all_registers] -to [all_outputs] 1 
+
+set_max_delay -from [get_keepers FB_AD*] -to [get_keepers BA*] 5
+set_max_delay -from [get_keepers FB_AD*] -to [get_keepers VA*] 5
+set_max_delay -from [get_keepers FB_AD*] -to [get_keepers nVRA*] 5
+
+
+#**************************************************************
+# Set Minimum Delay
+#**************************************************************
+
+
+
+#**************************************************************
+# Set Input Transition
+#**************************************************************
+

FPGA_by_Fredi/make_datetime.tcl

@@ -0,0 +1,36 @@
+puts make_datetime.tcl
+
+# Make datetime.vhd package from Tcl script
+
+# Current date, time, and seconds since epoch
+# Array index                                            0  1  2  3  4  5  6
+set datetime_arr [clock format [clock seconds] -format {%Y %m %d %H %M %S %s}]
+
+# Write VHDL package
+set filename datetime.vhd
+set file [open $filename w]
+puts $file "library ieee;"
+puts $file "use ieee.std_logic_1164.all;"
+puts $file ""
+puts $file "package datetime is"
+puts $file "    -- Date information"
+puts $file "    constant YEAR_INT       : integer                        := [lindex $datetime_arr 0];"
+puts $file "    constant YEAR_HEX       : std_ulogic_vector(15 downto 0) := X\"[lindex $datetime_arr 0]\";"
+puts $file "    constant MONTH_INT      : integer                        := [lindex $datetime_arr 1];"
+puts $file "    constant MONTH_HEX      : std_ulogic_vector(7 downto 0)  := X\"[lindex $datetime_arr 1]\";"
+puts $file "    constant DAY_INT        : integer                        := [lindex $datetime_arr 2];"
+puts $file "    constant DAY_HEX        : std_ulogic_vector(7 downto 0)  := X\"[lindex $datetime_arr 2]\";"
+puts $file "    constant DATE_HEX_DMY   : std_ulogic_vector(31 downto 0) := DAY_HEX & MONTH_HEX & YEAR_HEX;"
+puts $file "    constant DATE_HEX_YMD   : std_ulogic_vector(31 downto 0) := YEAR_HEX & MONTH_HEX & DAY_HEX;"
+puts $file "    -- Time information"
+puts $file "    constant HOUR_INT       : integer                       := [lindex $datetime_arr 3];"
+puts $file "    constant HOUR_HEX       : std_ulogic_vector(7 downto 0) := X\"[lindex $datetime_arr 3]\";"
+puts $file "    constant MINUTE_INT     : integer                       := [lindex $datetime_arr 4];"
+puts $file "    constant MINUTE_HEX     : std_ulogic_vector(7 downto 0) := X\"[lindex $datetime_arr 4]\";"
+puts $file "    constant SECOND_INT     : integer                       := [lindex $datetime_arr 5];"
+puts $file "    constant SECOND_HEX     : std_ulogic_vector(7 downto 0) := X\"[lindex $datetime_arr 5]\";"
+puts $file "    constant TIME_HEX       : std_ulogic_vector(31 downto 0):= X\"00\" & HOUR_HEX & MINUTE_HEX & SECOND_HEX;"
+puts $file "    -- Miscellaneous information"
+puts $file "    constant EPOCH_INT      : integer := [lindex $datetime_arr 6];  -- Seconds since 1970-01-01_00:00:00"
+puts $file "end package;"
+close $file

FPGA_by_Fredi/precmd.tcl

@@ -0,0 +1,13 @@
+#
+# execute each of a list of tcl scripts
+#
+# meant to be used with the PRE_FLOW_SCRIPT_FILE quartus assignment
+# that allows to evaluate a tcl script before analysis starts
+
+set precmd_list { "make_datetime.tcl" }
+
+set script [info script]
+foreach item $precmd_list {
+    post_message "$script: execute $item"
+    exec quartus_sh -t $item
+}