ragnar/FPGA_Config
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Code Pull Requests Activity
84 Commits 5 Branches 0 Tags
8114dcadf3672ef370c4061a852db970b4578f6c
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15 Commits

Author SHA1 Message Date
Markus Fröschle
8114dcadf3 fix hsync len calculation for Firebee mode 2016-04-14 05:56:39 +00:00
Markus Fröschle
accc7e85f0 make it compile again 2016-02-10 17:06:57 +00:00
Markus Fröschle
5f55a6738a cast to std_logic_vector 2016-01-19 17:36:29 +00:00
Markus Fröschle
752b4cd0ad modify to use WHEN statements instead of binary logic 2016-01-19 15:50:36 +00:00
Markus Fröschle
1846f7eff2 remove specialised clocks 2016-01-19 07:27:27 +00:00
Markus Fröschle
2724be31d1 removed more "indirect" clocks 2016-01-19 07:07:31 +00:00
Markus Fröschle
e2ab4af020 get rid of BUFFER parameters 2016-01-18 18:32:50 +00:00
Markus Fröschle
652dd1c124 hold time fix test 2016-01-18 18:15:02 +00:00
Markus Fröschle
21a4a80fb7 start of flexbus_register implementation to simplify that 2016-01-17 20:28:18 +00:00
Markus Fröschle
ddad975d6f fix 13MHz clock sdc 2016-01-17 08:43:20 +00:00
Markus Fröschle
7bf4d912a0 fix timing 2016-01-16 21:38:17 +00:00
Markus Fröschle
c4d56bb652 reformat 2016-01-14 16:49:11 +00:00
Markus Fröschle
97a48bf636 reactivated delay chain 2016-01-13 15:04:24 +00:00
Markus Fröschle
fd5abf8b4a reformat 2016-01-13 13:23:46 +00:00
Markus Fröschle
5183d08d60 finish conversion to vhdl 2016-01-13 12:53:03 +00:00