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add false paths to design constraints

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This commit is contained in:
Markus Fröschle
2015-09-20 16:23:52 +00:00
parent f72db5f2b5
commit fb3fcdf996
12 changed files with 1883 additions and 1864 deletions
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219
FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd
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@@ -228,7 +228,9 @@ END falconio_sdcard_ide_cf;
SIGNAL WRF_RDE : std_logic;
SIGNAL WRF_WRE : std_logic;
SIGNAL nFDC_WR : std_logic;
type FCF_STATES is( FCF_IDLE, FCF_T0, FCF_T1, FCF_T2, FCF_T3, FCF_T6, FCF_T7);
TYPE FCF_STATES IS (FCF_IDLE, FCF_T0, FCF_T1, FCF_T2, FCF_T3, FCF_T6, FCF_T7);
SIGNAL FCF_STATE : FCF_STATES;
SIGNAL NEXT_FCF_STATE : FCF_STATES;
SIGNAL DMA_REQ : std_logic;
@@ -239,6 +241,7 @@ END falconio_sdcard_ide_cf;
SIGNAL DMA_ACTIV : std_logic;
SIGNAL DMA_ACTIV_NEW : std_logic;
SIGNAL FDC_OUT : std_logic_vector(7 DOWNTO 0);
-- SCSI
SIGNAL SCSI_CS : std_logic;
SIGNAL SCSI_CSn : std_logic;
@@ -256,6 +259,7 @@ END falconio_sdcard_ide_cf;
SIGNAL BSY_EN : std_logic;
SIGNAL SEL_OUTn : std_logic;
SIGNAL SEL_EN : std_logic;
-- IDE
SIGNAL nnIDE_RES : std_logic;
SIGNAL IDE_CF_CS : std_logic;
@@ -268,25 +272,28 @@ END falconio_sdcard_ide_cf;
BEGIN
LONG <= '1' WHEN FB_SIZE1 = '0' and FB_SIZE0 = '0' ELSE '0';
BYT <= '1' WHEN FB_SIZE1 = '0' and FB_SIZE0 = '1' ELSE '0';
FB_B0 <= '1' WHEN FB_ADR(0) = '0' or BYT = '0' ELSE '0';
FB_B1 <= '1' WHEN FB_ADR(0) = '1' or BYT = '0' ELSE '0';
LONG <= '1' WHEN FB_SIZE1 = '0' AND FB_SIZE0 = '0' ELSE '0';
BYT <= '1' WHEN FB_SIZE1 = '0' AND FB_SIZE0 = '1' ELSE '0';
FB_B0 <= '1' WHEN FB_ADR(0) = '0' OR BYT = '0' ELSE '0';
FB_B1 <= '1' WHEN FB_ADR(0) = '1' OR BYT = '0' ELSE '0';
FALCON_IO_TA <= '1' WHEN SNDCS = '1' or DTACK_OUT_MFPn = '0' or ACIA_CS_I = '1' or DMA_MODUS_CS ='1'
or DMA_ADR_CS = '1' or DMA_DIRM_CS = '1' or DMA_BYT_CNT_CS = '1' or FCF_CS = '1' or IDE_CF_TA = '1' ELSE '0';
SUB_BUS <= '1' WHEN nFB_WR = '1' and ROM_CS = '1' ELSE
'1' WHEN nFB_WR = '1' and IDE_CF_CS = '1' ELSE
'1' WHEN nFB_WR = '0' and nIDE_WR = '0' ELSE '0';
nRP_UDS <= '0' WHEN SUB_BUS = '1' and FB_B0 = '1' ELSE '1';
nRP_LDS <= '0' WHEN SUB_BUS = '1' and FB_B1 = '1' ELSE '1';
FALCON_IO_TA <= '1' WHEN SNDCS = '1' OR DTACK_OUT_MFPn = '0' OR ACIA_CS_I = '1' OR DMA_MODUS_CS ='1'
OR DMA_ADR_CS = '1' OR DMA_DIRM_CS = '1' OR DMA_BYT_CNT_CS = '1' OR FCF_CS = '1' OR IDE_CF_TA = '1' ELSE '0';
SUB_BUS <= '1' WHEN nFB_WR = '1' AND ROM_CS = '1' ELSE
'1' WHEN nFB_WR = '1' AND IDE_CF_CS = '1' ELSE
'1' WHEN nFB_WR = '0' AND nIDE_WR = '0' ELSE '0';
nRP_UDS <= '0' WHEN SUB_BUS = '1' AND FB_B0 = '1' ELSE '1';
nRP_LDS <= '0' WHEN SUB_BUS = '1' AND FB_B1 = '1' ELSE '1';
nDREQ0 <= '0';
----------------------------------------------------------------------------
-- SD
----------------------------------------------------------------------------
SD_CLK <= 'Z';
SD_CD_DATA3 <= 'Z';
SD_CDM_D1 <= 'Z';
----------------------------------------------------------------------------
-- IDE
----------------------------------------------------------------------------
@@ -344,16 +351,21 @@ BEGIN
END CASE;
END PROCESS CMD_DECODER;
IDE_RES <= not nnIDE_RES and nRSTO;
IDE_CF_CS <= '1' WHEN nFB_CS1 = '0' and FB_ADR(19 DOWNTO 7) = x"0" ELSE '0'; -- FFF0'0000/80
nCF_CS0 <= '0' WHEN ACP_CONF(31) = '0' and FB_ADR(19 DOWNTO 5) = x"0" ELSE -- FFFO'0000-FFF0'001F
'0' WHEN ACP_CONF(31) = '1' and FB_ADR(19 DOWNTO 5) = x"2" ELSE '1'; -- FFFO'0040-FFF0'005F
nCF_CS1 <= '0' WHEN ACP_CONF(31) = '0' and FB_ADR(19 DOWNTO 5) = x"1" ELSE -- FFF0'0020-FFF0'003F
'0' WHEN ACP_CONF(31) = '1' and FB_ADR(19 DOWNTO 5) = x"3" ELSE '1'; -- FFFO'0060-FFF0'007F
nIDE_CS0 <= '0' WHEN ACP_CONF(30) = '0' and FB_ADR(19 DOWNTO 5) = x"2" ELSE -- FFF0'0040-FFF0'005F
'0' WHEN ACP_CONF(30) = '1' and FB_ADR(19 DOWNTO 5) = x"0" ELSE '1'; -- FFFO'0000-FFF0'001F
nIDE_CS1 <= '0' WHEN ACP_CONF(30) = '0' and FB_ADR(19 DOWNTO 5) = x"3" ELSE -- FFF0'0060-FFF0'007F
'0' WHEN ACP_CONF(30) = '1' and FB_ADR(19 DOWNTO 5) = x"1" ELSE '1'; -- FFFO'0020-FFF0'003F
IDE_RES <= NOT nnIDE_RES AND nRSTO;
IDE_CF_CS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 7) = x"0" ELSE '0'; -- FFF0'0000/80
nCF_CS0 <= '0' WHEN ACP_CONF(31) = '0' AND FB_ADR(19 DOWNTO 5) = x"0" ELSE -- FFFO'0000-FFF0'001F
'0' WHEN ACP_CONF(31) = '1' AND FB_ADR(19 DOWNTO 5) = x"2" ELSE '1'; -- FFFO'0040-FFF0'005F
nCF_CS1 <= '0' WHEN ACP_CONF(31) = '0' AND FB_ADR(19 DOWNTO 5) = x"1" ELSE -- FFF0'0020-FFF0'003F
'0' WHEN ACP_CONF(31) = '1' AND FB_ADR(19 DOWNTO 5) = x"3" ELSE '1'; -- FFFO'0060-FFF0'007F
nIDE_CS0 <= '0' WHEN ACP_CONF(30) = '0' AND FB_ADR(19 DOWNTO 5) = x"2" ELSE -- FFF0'0040-FFF0'005F
'0' WHEN ACP_CONF(30) = '1' AND FB_ADR(19 DOWNTO 5) = x"0" ELSE '1'; -- FFFO'0000-FFF0'001F
nIDE_CS1 <= '0' WHEN ACP_CONF(30) = '0' AND FB_ADR(19 DOWNTO 5) = x"3" ELSE -- FFF0'0060-FFF0'007F
'0' WHEN ACP_CONF(30) = '1' AND FB_ADR(19 DOWNTO 5) = x"1" ELSE '1'; -- FFFO'0020-FFF0'003F
-----------------------------------------------------------------------------------------------------------------------------------------
-- ACSI, SCSI UND FLOPPY WD1772
-------------------------------------------------------------------------------------------------------------------------------------------
@@ -369,11 +381,14 @@ BEGIN
q => RDF_DOUT,
wrusedw => RDF_AZ
);
FCF_CS <= '1' WHEN nFB_CS2 = '0' and FB_ADR(26 DOWNTO 0) = x"0020110" and LONG = '1' ELSE '0'; -- F002'0110 LONG ONLY
FCF_APH <= '1' WHEN FB_ALE = '1' and FB_AD(31 DOWNTO 0) = x"F0020110" and LONG = '1' ELSE '0'; -- ADRESSPHASE F0020110 LONG ONLY
RDF_RDE <= '1' WHEN FCF_APH = '1' and nFB_WR = '1' ELSE '0'; -- AKTIVIEREN IN ADRESSPHASE
FB_AD <= RDF_DOUT(7 DOWNTO 0) & RDF_DOUT(15 DOWNTO 8) & RDF_DOUT(23 DOWNTO 16) & RDF_DOUT(31 DOWNTO 24) WHEN FCF_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
FCF_CS <= '1' WHEN nFB_CS2 = '0' AND FB_ADR(26 DOWNTO 0) = x"0020110" AND LONG = '1' ELSE '0'; -- F002'0110 LONG ONLY
FCF_APH <= '1' WHEN FB_ALE = '1' AND FB_AD(31 DOWNTO 0) = x"F0020110" AND LONG = '1' ELSE '0'; -- ADRESSPHASE F0020110 LONG ONLY
RDF_RDE <= '1' WHEN FCF_APH = '1' AND nFB_WR = '1' ELSE '0'; -- AKTIVIEREN IN ADRESSPHASE
FB_AD <= RDF_DOUT(7 DOWNTO 0) & RDF_DOUT(15 DOWNTO 8) & RDF_DOUT(23 DOWNTO 16) & RDF_DOUT(31 DOWNTO 24) WHEN FCF_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z');
RDF_DIN <= CD_OUT_FDC WHEN DMA_MODUS(7) = '1' ELSE SCSI_DOUT;
-- daten write fifo
WRF: dcfifo1
PORT MAP(
@@ -387,9 +402,9 @@ BEGIN
rdusedw => WRF_AZ
);
CD_IN_FDC <= WRF_DOUT WHEN DMA_ACTIV = '1' and DMA_MODUS(8) = '1' ELSE FB_AD(23 DOWNTO 16); -- BEI DMA WRITE <-FIFO SONST <-FB
DMA_AZ_CS <= '1' WHEN nFB_CS2 = '0' and FB_ADR(26 DOWNTO 0) = x"002010C" ELSE '0'; -- F002'010C LONG
FB_AD <= DMA_DRQ_Q & DMA_DRQ_REG & IDE_INT & FDINT & SCSI_INT & RDF_AZ & "0" & DMA_STATUS & "00" & WRF_AZ WHEN DMA_AZ_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
CD_IN_FDC <= WRF_DOUT WHEN DMA_ACTIV = '1' AND DMA_MODUS(8) = '1' ELSE FB_AD(23 DOWNTO 16); -- BEI DMA WRITE <-FIFO SONST <-FB
DMA_AZ_CS <= '1' WHEN nFB_CS2 = '0' AND FB_ADR(26 DOWNTO 0) = x"002010C" ELSE '0'; -- F002'010C LONG
FB_AD <= DMA_DRQ_Q & DMA_DRQ_REG & IDE_INT & FDINT & SCSI_INT & RDF_AZ & "0" & DMA_STATUS & "00" & WRF_AZ WHEN DMA_AZ_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z');
DMA_DRQ_Q <= '1' WHEN DMA_DRQ_REG = "11" and DMA_MODUS(6) = '0' ELSE '0';
-- FIFO WRITE: GENAU 1 MAIN_CLK -------------------------------------------------------------------------
@@ -398,7 +413,7 @@ BEGIN
IF nRSTO = '0' THEN
WRF_WRE <= '0';
ELSIF rising_edge(MAIN_CLK) THEN
IF FCF_APH = '1' and nFB_WR = '0' THEN
IF FCF_APH = '1' AND nFB_WR = '0' THEN
WRF_WRE <= '1';
ELSE
WRF_WRE <= '0';
@@ -426,27 +441,27 @@ BEGIN
BEGIN
IF nRSTO = '0' THEN
FDC_OUT <= x"00";
ELSIF rising_edge(FDC_CLK) and FDCS_In = '0' THEN
ELSIF rising_edge(FDC_CLK) AND FDCS_In = '0' THEN
FDC_OUT <= CD_OUT_FDC; -- set
ELSE
FDC_OUT <= FDC_OUT; -- halten
END IF;
END PROCESS FDC_REG;
DMA_REQ <= '1' WHEN ((DMA_DRQ_I = '1' and DMA_MODUS(7) = '1') or (SCSI_DRQ = '1' and DMA_MODUS(7) = '0')) and DMA_STATUS(1) = '1' and DMA_MODUS(6) = '0' and CLR_FIFO = '0' ELSE '0';
FDC_CS <= '1' WHEN DMA_DATEN_CS = '1' and DMA_MODUS(4 DOWNTO 3) = "00" and FB_B1 = '1' ELSE '0';
SCSI_CS <= '1' WHEN DMA_DATEN_CS = '1' and DMA_MODUS(4 DOWNTO 3) = "01" and FB_B1 = '1' ELSE '0';
DMA_REQ <= '1' WHEN ((DMA_DRQ_I = '1' AND DMA_MODUS(7) = '1') OR (SCSI_DRQ = '1' AND DMA_MODUS(7) = '0')) AND DMA_STATUS(1) = '1' AND DMA_MODUS(6) = '0' AND CLR_FIFO = '0' ELSE '0';
FDC_CS <= '1' WHEN DMA_DATEN_CS = '1' AND DMA_MODUS(4 DOWNTO 3) = "00" AND FB_B1 = '1' ELSE '0';
SCSI_CS <= '1' WHEN DMA_DATEN_CS = '1' AND DMA_MODUS(4 DOWNTO 3) = "01" AND FB_B1 = '1' ELSE '0';
FCF_DECODER: PROCESS(FCF_STATE, NEXT_FCF_STATE, DMA_REQ,FDC_CS, RDF_WRE, WRF_RDE, SCSI_DRQ, nSCSI_DACK, DMA_MODUS, DMA_ACTIV, FDCS_In,SCSI_CS, SCSI_CSn)
BEGIN
case FCF_STATE is
CASE FCF_STATE IS
WHEN FCF_IDLE =>
SCSI_CSn <= '1';
FDCS_In <= '1';
RDF_WRE <= '0';
WRF_RDE <= '0';
nSCSI_DACK <= '1';
IF DMA_REQ = '1' or FDC_CS = '1' or SCSI_CS = '1' THEN
IF DMA_REQ = '1' OR FDC_CS = '1' OR SCSI_CS = '1' THEN
DMA_ACTIV_NEW <= DMA_REQ;
NEXT_FCF_STATE <= FCF_T0;
ELSE
@@ -459,8 +474,8 @@ BEGIN
RDF_WRE <= '0';
nSCSI_DACK <= '1';
DMA_ACTIV_NEW <= DMA_REQ;
WRF_RDE <= DMA_MODUS(8) and DMA_REQ; -- WRITE -> READ FROM FIFO
IF DMA_REQ = '0' and DMA_ACTIV = '1' THEN -- spike?
WRF_RDE <= DMA_MODUS(8) AND DMA_REQ; -- WRITE -> READ FROM FIFO
IF DMA_REQ = '0' AND DMA_ACTIV = '1' THEN -- spike?
NEXT_FCF_STATE <= FCF_IDLE; -- ja -> zum start
ELSE
NEXT_FCF_STATE <= FCF_T1;
@@ -469,33 +484,33 @@ BEGIN
RDF_WRE <= '0';
WRF_RDE <= '0';
DMA_ACTIV_NEW <= DMA_ACTIV;
SCSI_CSn <= not SCSI_CS;
FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3);
nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV;
SCSI_CSn <= NOT SCSI_CS;
FDCS_In <= DMA_MODUS(4) OR DMA_MODUS(3);
nSCSI_DACK <= DMA_MODUS(7) AND DMA_ACTIV;
NEXT_FCF_STATE <= FCF_T2;
WHEN FCF_T2 =>
RDF_WRE <= '0';
WRF_RDE <= '0';
DMA_ACTIV_NEW <= DMA_ACTIV;
SCSI_CSn <= not SCSI_CS;
FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3);
nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV;
SCSI_CSn <= NOT SCSI_CS;
FDCS_In <= DMA_MODUS(4) OR DMA_MODUS(3);
nSCSI_DACK <= DMA_MODUS(7) AND DMA_ACTIV;
NEXT_FCF_STATE <= FCF_T3;
WHEN FCF_T3 =>
RDF_WRE <= '0';
WRF_RDE <= '0';
DMA_ACTIV_NEW <= DMA_ACTIV;
SCSI_CSn <= not SCSI_CS;
FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3);
nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV;
SCSI_CSn <= NOT SCSI_CS;
FDCS_In <= DMA_MODUS(4) OR DMA_MODUS(3);
nSCSI_DACK <= DMA_MODUS(7) AND DMA_ACTIV;
NEXT_FCF_STATE <= FCF_T6;
WHEN FCF_T6 =>
WRF_RDE <= '0';
DMA_ACTIV_NEW <= DMA_ACTIV;
SCSI_CSn <= not SCSI_CS;
FDCS_In <= DMA_MODUS(4) or DMA_MODUS(3);
nSCSI_DACK <= DMA_MODUS(7) and DMA_ACTIV;
RDF_WRE <= not DMA_MODUS(8) and DMA_ACTIV; -- READ -> WRITE IN FIFO
SCSI_CSn <= NOT SCSI_CS;
FDCS_In <= DMA_MODUS(4) OR DMA_MODUS(3);
nSCSI_DACK <= DMA_MODUS(7) AND DMA_ACTIV;
RDF_WRE <= NOT DMA_MODUS(8) AND DMA_ACTIV; -- READ -> WRITE IN FIFO
NEXT_FCF_STATE <= FCF_T7;
WHEN FCF_T7 =>
SCSI_CSn <= '1';
@@ -504,7 +519,7 @@ BEGIN
WRF_RDE <= '0';
nSCSI_DACK <= '1';
DMA_ACTIV_NEW <= '0';
IF FDC_CS = '1' and DMA_REQ = '0' THEN
IF FDC_CS = '1' AND DMA_REQ = '0' THEN
NEXT_FCF_STATE <= FCF_T7;
ELSE
NEXT_FCF_STATE <= FCF_IDLE;
@@ -538,22 +553,22 @@ BEGIN
INTRQ => FDINT
);
DMA_DATEN_CS <= '1' WHEN nFB_CS1 = '0' and FB_ADR(19 DOWNTO 1) = x"7C302" ELSE '0'; -- F8604/2
DMA_MODUS_CS <= '1' WHEN nFB_CS1 = '0' and FB_ADR(19 DOWNTO 1) = x"7C303" ELSE '0'; -- F8606/2
WDC_BSL_CS <= '1' WHEN nFB_CS1 = '0' and FB_ADR(19 DOWNTO 1) = x"7C307" ELSE '0'; -- F860E/2
DMA_DATEN_CS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 1) = x"7C302" ELSE '0'; -- F8604/2
DMA_MODUS_CS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 1) = x"7C303" ELSE '0'; -- F8606/2
WDC_BSL_CS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 1) = x"7C307" ELSE '0'; -- F860E/2
HD_DD_OUT <= HD_DD WHEN ACP_CONF(29) = '0' ELSE WDC_BSL(0);
nFDC_WR <= (not DMA_MODUS(8)) WHEN DMA_ACTIV = '1' ELSE nFB_WR;
nFDC_WR <= NOT DMA_MODUS(8) WHEN DMA_ACTIV = '1' ELSE nFB_WR;
CA0 <= '1' WHEN DMA_ACTIV = '1' ELSE DMA_MODUS(0);
CA1 <= '1' WHEN DMA_ACTIV = '1' ELSE DMA_MODUS(1);
CA2 <= '1' WHEN DMA_ACTIV = '1' ELSE DMA_MODUS(2);
FB_AD(23 DOWNTO 16) <= "0000" & (not DMA_STATUS(1)) & "0" & WDC_BSL(1) & HD_DD WHEN WDC_BSL_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ";
FB_AD(31 DOWNTO 24) <= "00000000" WHEN DMA_DATEN_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ";
FB_AD(23 DOWNTO 16) <= FDC_OUT WHEN DMA_DATEN_CS = '1' and DMA_MODUS(4 DOWNTO 3) = "00" and nFB_OE = '0' ELSE
SCSI_DOUT WHEN DMA_DATEN_CS = '1' and DMA_MODUS(4 DOWNTO 3) = "01" and nFB_OE = '0' ELSE
DMA_BYT_CNT(16 DOWNTO 9) WHEN DMA_DATEN_CS = '1' and DMA_MODUS(4) = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ";
FB_AD(23 DOWNTO 16) <= "0000" & (NOT DMA_STATUS(1)) & "0" & WDC_BSL(1) & HD_DD WHEN WDC_BSL_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z');
FB_AD(31 DOWNTO 24) <= "00000000" WHEN DMA_DATEN_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z');
FB_AD(23 DOWNTO 16) <= FDC_OUT WHEN DMA_DATEN_CS = '1' AND DMA_MODUS(4 DOWNTO 3) = "00" AND nFB_OE = '0' ELSE
SCSI_DOUT WHEN DMA_DATEN_CS = '1' AND DMA_MODUS(4 DOWNTO 3) = "01" AND nFB_OE = '0' ELSE
DMA_BYT_CNT(16 DOWNTO 9) WHEN DMA_DATEN_CS = '1' AND DMA_MODUS(4) = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z');
--- WDC BSL REGISTER -------------------------------------------------------
@@ -561,7 +576,7 @@ BEGIN
BEGIN
IF nRSTO = '0' THEN
WDC_BSL <= "00";
ELSIF rising_edge(MAIN_CLK) and WDC_BSL_CS = '1' and nFB_WR = '0' THEN
ELSIF rising_edge(MAIN_CLK) AND WDC_BSL_CS = '1' AND nFB_WR = '0' THEN
IF FB_B0 = '1' THEN
WDC_BSL(1 DOWNTO 0) <= FB_AD(25 DOWNTO 24);
ELSE
@@ -575,7 +590,7 @@ BEGIN
BEGIN
IF nRSTO = '0' THEN
DMA_MODUS <= x"0000";
ELSIF rising_edge(MAIN_CLK) and DMA_MODUS_CS = '1' and nFB_WR = '0' THEN
ELSIF rising_edge(MAIN_CLK) AND DMA_MODUS_CS = '1' AND nFB_WR = '0' THEN
IF FB_B0 = '1' THEN
DMA_MODUS(15 DOWNTO 8) <= FB_AD(31 DOWNTO 24);
ELSE
@@ -594,13 +609,13 @@ BEGIN
-- BYT COUNTER, SECTOR COUNTER ----------------------------------------------------
PROCESS(MAIN_CLK, nRSTO, DMA_DATEN_CS, DMA_BYT_CNT_CS, DMA_BYT_CNT, nFB_WR, FB_B0, FB_B1, DMA_MODUS, CLR_FIFO)
BEGIN
IF nRSTO = '0' or CLR_FIFO = '1' THEN
IF nRSTO = '0' OR CLR_FIFO = '1' THEN
DMA_BYT_CNT <= x"00000000";
ELSIF rising_edge(MAIN_CLK) and nFB_WR = '0' and DMA_DATEN_CS = '1' and nFB_WR = '0' and DMA_MODUS(4) = '1' and FB_B1 = '1' THEN
ELSIF rising_edge(MAIN_CLK) AND nFB_WR = '0' AND DMA_DATEN_CS = '1' AND nFB_WR = '0' AND DMA_MODUS(4) = '1' AND FB_B1 = '1' THEN
DMA_BYT_CNT(31 DOWNTO 17) <= (OTHERS => 'Z');
DMA_BYT_CNT(16 DOWNTO 9) <= FB_AD(23 DOWNTO 16);
DMA_BYT_CNT(8 DOWNTO 0) <= (OTHERS => 'Z');
ELSIF rising_edge(MAIN_CLK) and nFB_WR = '0' and DMA_BYT_CNT_CS = '1' THEN
ELSIF rising_edge(MAIN_CLK) AND nFB_WR = '0' AND DMA_BYT_CNT_CS = '1' THEN
DMA_BYT_CNT <= FB_AD;
ELSE
DMA_BYT_CNT <= DMA_BYT_CNT;
@@ -610,11 +625,11 @@ BEGIN
FB_AD(31 DOWNTO 16) <= "0000000000000" & DMA_STATUS WHEN DMA_MODUS_CS = '1' and nFB_OE = '0' ELSE (OTHERS => 'Z');
DMA_STATUS(0) <= '1'; -- DMA OK
DMA_STATUS(1) <= '1' WHEN DMA_BYT_CNT /= 0 and DMA_BYT_CNT(31) = '0' ELSE '0'; -- WENN byts UND NICHT MINUS
DMA_STATUS(2) <= '0' WHEN DMA_DRQ_I = '1' or SCSI_DRQ = '1' ELSE '0';
DMA_DRQQ <= '1' WHEN DMA_STATUS(1) = '1' and DMA_MODUS(8) = '0' and RDF_AZ > 15 and DMA_MODUS(6) = '0' ELSE
'1' WHEN DMA_STATUS(1) = '1' and DMA_MODUS(8) = '1' and WRF_AZ < 512 and DMA_MODUS(6) = '0' ELSE '0';
DMA_DRQ <= '1' WHEN DMA_DRQ_REG = "11" and DMA_MODUS(6) = '0' ELSE '0';
DMA_STATUS(1) <= '1' WHEN DMA_BYT_CNT /= 0 AND DMA_BYT_CNT(31) = '0' ELSE '0'; -- WENN byts UND NICHT MINUS
DMA_STATUS(2) <= '0' WHEN DMA_DRQ_I = '1' OR SCSI_DRQ = '1' ELSE '0';
DMA_DRQQ <= '1' WHEN DMA_STATUS(1) = '1' AND DMA_MODUS(8) = '0' AND RDF_AZ > 15 AND DMA_MODUS(6) = '0' ELSE
'1' WHEN DMA_STATUS(1) = '1' AND DMA_MODUS(8) = '1' AND WRF_AZ < 512 AND DMA_MODUS(6) = '0' ELSE '0';
DMA_DRQ <= '1' WHEN DMA_DRQ_REG = "11" AND DMA_MODUS(6) = '0' ELSE '0';
-- DMA REQUEST: SPIKES AUSFILTERN ------------------------------------------
PROCESS(FDC_CLK, nRSTO, DMA_DRQ_REG)
@@ -634,7 +649,7 @@ BEGIN
BEGIN
IF nRSTO = '0' THEN
DMA_TOP <= x"00";
ELSIF rising_edge(MAIN_CLK) and nFB_WR = '0' and (DMA_TOP_CS = '1' or DMA_ADR_CS = '1') THEN
ELSIF rising_edge(MAIN_CLK) AND nFB_WR = '0' AND (DMA_TOP_CS = '1' OR DMA_ADR_CS = '1') THEN
DMA_TOP <= FB_AD(31 DOWNTO 24);
ELSE
DMA_TOP <= DMA_TOP;
@@ -645,7 +660,7 @@ BEGIN
BEGIN
IF nRSTO = '0' THEN
DMA_HIGH <= x"00";
ELSIF rising_edge(MAIN_CLK) and nFB_WR = '0' and (DMA_HIGH_CS = '1' or DMA_ADR_CS = '1') THEN
ELSIF rising_edge(MAIN_CLK) AND nFB_WR = '0' AND (DMA_HIGH_CS = '1' OR DMA_ADR_CS = '1') THEN
DMA_HIGH <= FB_AD(23 DOWNTO 16);
ELSE
DMA_HIGH <= DMA_HIGH;
@@ -657,7 +672,7 @@ BEGIN
DMA_MID <= DMA_MID;
IF nRSTO = '0' THEN
DMA_MID <= x"00";
ELSIF rising_edge(MAIN_CLK) and nFB_WR = '0' THEN
ELSIF rising_edge(MAIN_CLK) AND nFB_WR = '0' THEN
IF DMA_MID_CS = '1' THEN
DMA_MID <= FB_AD(23 DOWNTO 16);
ELSIF DMA_ADR_CS = '1' THEN
@@ -671,7 +686,7 @@ BEGIN
DMA_LOW <= DMA_LOW;
IF nRSTO = '0' THEN
DMA_LOW <= x"00";
ELSIF rising_edge(MAIN_CLK) and nFB_WR = '0' THEN
ELSIF rising_edge(MAIN_CLK) AND nFB_WR = '0' THEN
IF DMA_LOW_CS = '1'THEN
DMA_LOW <= FB_AD(23 DOWNTO 16);
ELSIF DMA_ADR_CS = '1' THEN
@@ -681,23 +696,23 @@ BEGIN
END PROCESS;
--------------------------------------------------------------------------------------------
DMA_TOP_CS <= '1' WHEN nFB_CS1 = '0' and FB_ADR(19 DOWNTO 1) = x"7C304" and FB_B0 = '1' ELSE '0'; -- F8608/2
DMA_HIGH_CS <= '1' WHEN nFB_CS1 = '0' and FB_ADR(19 DOWNTO 1) = x"7C304" and FB_B1 = '1' ELSE '0'; -- F8609/2
DMA_MID_CS <= '1' WHEN nFB_CS1 = '0' and FB_ADR(19 DOWNTO 1) = x"7C305" and FB_B1 = '1' ELSE '0'; -- F860B/2
DMA_LOW_CS <= '1' WHEN nFB_CS1 = '0' and FB_ADR(19 DOWNTO 1) = x"7C306" and FB_B1 = '1' ELSE '0'; -- F860D/2
DMA_TOP_CS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 1) = x"7C304" AND FB_B0 = '1' ELSE '0'; -- F8608/2
DMA_HIGH_CS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 1) = x"7C304" AND FB_B1 = '1' ELSE '0'; -- F8609/2
DMA_MID_CS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 1) = x"7C305" AND FB_B1 = '1' ELSE '0'; -- F860B/2
DMA_LOW_CS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 1) = x"7C306" AND FB_B1 = '1' ELSE '0'; -- F860D/2
FB_AD(31 DOWNTO 24) <= DMA_TOP WHEN DMA_TOP_CS = '1' and nFB_OE = '0' ELSE (OTHERS => 'Z');
FB_AD(23 DOWNTO 16) <= DMA_HIGH WHEN DMA_HIGH_CS = '1' and nFB_OE = '0' ELSE (OTHERS => 'Z');
FB_AD(23 DOWNTO 16) <= DMA_MID WHEN DMA_MID_CS = '1' and nFB_OE = '0' ELSE (OTHERS => 'Z');
FB_AD(23 DOWNTO 16) <= DMA_LOW WHEN DMA_LOW_CS = '1' and nFB_OE = '0' ELSE (OTHERS => 'Z');
FB_AD(31 DOWNTO 24) <= DMA_TOP WHEN DMA_TOP_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z');
FB_AD(23 DOWNTO 16) <= DMA_HIGH WHEN DMA_HIGH_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z');
FB_AD(23 DOWNTO 16) <= DMA_MID WHEN DMA_MID_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z');
FB_AD(23 DOWNTO 16) <= DMA_LOW WHEN DMA_LOW_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z');
-- DIRECTZUGRIFF
DMA_DIRM_CS <= '1' WHEN nFB_CS2 = '0' and FB_ADR(26 DOWNTO 0) = x"20100" ELSE '0'; -- F002'0100 WORD
DMA_ADR_CS <= '1' WHEN nFB_CS2 = '0' and FB_ADR(26 DOWNTO 0) = x"20104" ELSE '0'; -- F002'0104 LONG
DMA_BYT_CNT_CS <= '1' WHEN nFB_CS2 = '0' and FB_ADR(26 DOWNTO 0) = x"20108" ELSE '0'; -- F002'0108 LONG
DMA_DIRM_CS <= '1' WHEN nFB_CS2 = '0' AND FB_ADR(26 DOWNTO 0) = x"20100" ELSE '0'; -- F002'0100 WORD
DMA_ADR_CS <= '1' WHEN nFB_CS2 = '0' AND FB_ADR(26 DOWNTO 0) = x"20104" ELSE '0'; -- F002'0104 LONG
DMA_BYT_CNT_CS <= '1' WHEN nFB_CS2 = '0' AND FB_ADR(26 DOWNTO 0) = x"20108" ELSE '0'; -- F002'0108 LONG
FB_AD <= DMA_TOP & DMA_HIGH & DMA_MID & DMA_LOW WHEN DMA_ADR_CS = '1' and nFB_OE = '0' ELSE (OTHERS => 'Z');
FB_AD(31 DOWNTO 16) <= DMA_MODUS WHEN DMA_DIRM_CS = '1' and nFB_OE = '0' ELSE (OTHERS => 'Z');
FB_AD <= DMA_BYT_CNT WHEN DMA_BYT_CNT_CS = '1' and nFB_OE = '0' ELSE (OTHERS => 'Z');
FB_AD <= DMA_TOP & DMA_HIGH & DMA_MID & DMA_LOW WHEN DMA_ADR_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z');
FB_AD(31 DOWNTO 16) <= DMA_MODUS WHEN DMA_DIRM_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z');
FB_AD <= DMA_BYT_CNT WHEN DMA_BYT_CNT_CS = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z');
-- DMA RW TOGGLE ------------------------------------------
@@ -706,14 +721,14 @@ BEGIN
BEGIN
IF nRSTO = '0' THEN
DMA_DIR_OLD <= '0';
ELSIF rising_edge(MAIN_CLK) and DMA_MODUS_CS = '0' THEN
ELSIF rising_edge(MAIN_CLK) AND DMA_MODUS_CS = '0' THEN
DMA_DIR_OLD <= DMA_MODUS(8);
ELSE
DMA_DIR_OLD <= DMA_DIR_OLD;
END IF;
END PROCESS;
CLR_FIFO <= DMA_MODUS(8) xor DMA_DIR_OLD;
CLR_FIFO <= DMA_MODUS(8) XOR DMA_DIR_OLD;
-- SCSI ----------------------------------------------------------------------------------
I_SCSI: WF5380_TOP_SOC
@@ -892,8 +907,8 @@ BEGIN
CLK => MAIN_CLK,
RESETn => nRSTO,
-- Asynchronous bus control:
DSn => not LDS,
CSn => not MFP_CS,
DSn => NOT LDS,
CSn => NOT MFP_CS,
RWn => nFB_WR,
DTACKn => DTACK_OUT_MFPn,
-- Data and Adresses:
@@ -901,18 +916,18 @@ BEGIN
DATA_IN => FB_AD(23 DOWNTO 16),
DATA_OUT => DATA_OUT_MFP,
-- DATA_EN => DATA_EN_MFP,
GPIP_IN(7) => not DMA_DRQ_Q,
GPIP_IN(6) => not RI,
GPIP_IN(7) => NOT DMA_DRQ_Q,
GPIP_IN(6) => NOT RI,
GPIP_IN(5) => DINTn,
GPIP_IN(4) => IRQ_ACIAn,
GPIP_IN(3) => DSP_INT,
GPIP_IN(2) => not CTS,
GPIP_IN(1) => not DCD,
GPIP_IN(2) => NOT CTS,
GPIP_IN(1) => NOT DCD,
GPIP_IN(0) => LP_BUSY,
-- GPIP_OUT =>, -- Not used; all GPIPs are direction input.
-- GPIP_EN =>, -- Not used; all GPIPs are direction input.
-- Interrupt control:
IACKn => not MFP_INTACK,
IACKn => NOT MFP_INTACK,
IEIn => '0',
-- IEOn =>, -- Not used.
IRQn => nMFP_INT,
@@ -999,10 +1014,10 @@ BEGIN
OUT_C => YM_QC
);
SNDCS <= '1' WHEN nFB_CS1 = '0' and FB_ADR(19 DOWNTO 2) = x"3E200" ELSE '0'; -- 8800-8803 F8800/4
SNDCS_I <= '1' WHEN SNDCS = '1' and FB_ADR (1 DOWNTO 1) = "0" ELSE '0';
SNDIR_I <= '1' WHEN SNDCS = '1' and nFB_WR = '0' ELSE '0';
FB_AD(31 DOWNTO 24) <= DA_OUT_X WHEN SNDCS_I = '1' and nFB_OE = '0' ELSE (OTHERS => 'Z');
SNDCS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 2) = x"3E200" ELSE '0'; -- 8800-8803 F8800/4
SNDCS_I <= '1' WHEN SNDCS = '1' AND FB_ADR (1 DOWNTO 1) = "0" ELSE '0';
SNDIR_I <= '1' WHEN SNDCS = '1' AND nFB_WR = '0' ELSE '0';
FB_AD(31 DOWNTO 24) <= DA_OUT_X WHEN SNDCS_I = '1' AND nFB_OE = '0' ELSE (OTHERS => 'Z');
LP_D <= LP_D_X WHEN LP_DIR_X = '0' ELSE (OTHERS => 'Z');
LP_DIR <= LP_DIR_X;

1044
FPGA_Quartus_13.1/Video/Video.bdf
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File diff suppressed because it is too large Load Diff

134
FPGA_Quartus_13.1/altpll3.bsf
View File

@@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2010 Altera Corporation
Copyright (C) 1991-2014 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
@@ -18,88 +18,88 @@ programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(header "symbol" (version "1.2"))
(symbol
(rect 0 0 304 232)
(text "altpll3" (rect 132 1 179 20)(font "Arial" (font_size 10)))
(text "inst" (rect 8 213 31 228)(font "Arial" ))
(rect 0 0 256 184)
(text "altpll3" (rect 111 0 153 16)(font "Arial" (font_size 10)))
(text "inst" (rect 8 169 26 180)(font "Arial" ))
(port
(pt 0 72)
(pt 0 64)
(input)
(text "inclk0" (rect 0 0 40 16)(font "Arial" (font_size 8)))
(text "inclk0" (rect 4 56 38 72)(font "Arial" (font_size 8)))
(line (pt 0 72)(pt 48 72)(line_width 1))
(text "inclk0" (rect 0 0 34 13)(font "Arial" (font_size 8)))
(text "inclk0" (rect 4 51 31 63)(font "Arial" (font_size 8)))
(line (pt 0 64)(pt 40 64))
)
(port
(pt 304 72)
(pt 256 64)
(output)
(text "c0" (rect 0 0 16 16)(font "Arial" (font_size 8)))
(text "c0" (rect 287 56 301 72)(font "Arial" (font_size 8)))
(line (pt 304 72)(pt 272 72)(line_width 1))
(text "c0" (rect 0 0 15 13)(font "Arial" (font_size 8)))
(text "c0" (rect 241 51 253 63)(font "Arial" (font_size 8)))
)
(port
(pt 304 96)
(pt 256 80)
(output)
(text "c1" (rect 0 0 16 16)(font "Arial" (font_size 8)))
(text "c1" (rect 287 80 301 96)(font "Arial" (font_size 8)))
(line (pt 304 96)(pt 272 96)(line_width 1))
(text "c1" (rect 0 0 14 13)(font "Arial" (font_size 8)))
(text "c1" (rect 241 67 251 79)(font "Arial" (font_size 8)))
)
(port
(pt 304 120)
(pt 256 96)
(output)
(text "c2" (rect 0 0 16 16)(font "Arial" (font_size 8)))
(text "c2" (rect 287 104 301 120)(font "Arial" (font_size 8)))
(line (pt 304 120)(pt 272 120)(line_width 1))
(text "c2" (rect 0 0 15 13)(font "Arial" (font_size 8)))
(text "c2" (rect 241 83 253 95)(font "Arial" (font_size 8)))
)
(port
(pt 304 144)
(pt 256 112)
(output)
(text "c3" (rect 0 0 16 16)(font "Arial" (font_size 8)))
(text "c3" (rect 287 128 301 144)(font "Arial" (font_size 8)))
(line (pt 304 144)(pt 272 144)(line_width 1))
(text "c3" (rect 0 0 15 13)(font "Arial" (font_size 8)))
(text "c3" (rect 241 99 253 111)(font "Arial" (font_size 8)))
)
(drawing
(text "Cyclone III" (rect 229 214 277 228)(font "Arial" ))
(text "inclk0 frequency: 33.000 MHz" (rect 58 67 201 81)(font "Arial" ))
(text "Operation Mode: Src Sync Comp" (rect 58 84 215 98)(font "Arial" ))
(text "Clk " (rect 59 111 76 125)(font "Arial" ))
(text "Ratio" (rect 86 111 110 125)(font "Arial" ))
(text "Ph (dg)" (rect 121 111 156 125)(font "Arial" ))
(text "DC (%)" (rect 166 111 201 125)(font "Arial" ))
(text "c0" (rect 63 129 75 143)(font "Arial" ))
(text "2/33" (rect 88 129 109 143)(font "Arial" ))
(text "0.00" (rect 129 129 150 143)(font "Arial" ))
(text "50.00" (rect 171 129 198 143)(font "Arial" ))
(text "c1" (rect 63 147 75 161)(font "Arial" ))
(text "16/33" (rect 85 147 112 161)(font "Arial" ))
(text "0.00" (rect 129 147 150 161)(font "Arial" ))
(text "50.00" (rect 171 147 198 161)(font "Arial" ))
(text "c2" (rect 63 165 75 179)(font "Arial" ))
(text "25/33" (rect 85 165 112 179)(font "Arial" ))
(text "0.00" (rect 129 165 150 179)(font "Arial" ))
(text "50.00" (rect 171 165 198 179)(font "Arial" ))
(text "c3" (rect 63 183 75 197)(font "Arial" ))
(text "16/11" (rect 85 183 112 197)(font "Arial" ))
(text "0.00" (rect 129 183 150 197)(font "Arial" ))
(text "50.00" (rect 171 183 198 197)(font "Arial" ))
(line (pt 0 0)(pt 305 0)(line_width 1))
(line (pt 305 0)(pt 305 233)(line_width 1))
(line (pt 0 233)(pt 305 233)(line_width 1))
(line (pt 0 0)(pt 0 233)(line_width 1))
(line (pt 56 108)(pt 208 108)(line_width 1))
(line (pt 56 125)(pt 208 125)(line_width 1))
(line (pt 56 143)(pt 208 143)(line_width 1))
(line (pt 56 161)(pt 208 161)(line_width 1))
(line (pt 56 179)(pt 208 179)(line_width 1))
(line (pt 56 197)(pt 208 197)(line_width 1))
(line (pt 56 108)(pt 56 197)(line_width 1))
(line (pt 82 108)(pt 82 197)(line_width 3))
(line (pt 118 108)(pt 118 197)(line_width 3))
(line (pt 163 108)(pt 163 197)(line_width 3))
(line (pt 207 108)(pt 207 197)(line_width 1))
(line (pt 48 56)(pt 272 56)(line_width 1))
(line (pt 272 56)(pt 272 216)(line_width 1))
(line (pt 48 216)(pt 272 216)(line_width 1))
(line (pt 48 56)(pt 48 216)(line_width 1))
(text "Cyclone III" (rect 198 170 442 350)(font "Arial" ))
(text "inclk0 frequency: 33.000 MHz" (rect 50 60 226 130)(font "Arial" ))
(text "Operation Mode: Src Sync Comp" (rect 50 72 239 154)(font "Arial" ))
(text "Clk " (rect 51 91 117 192)(font "Arial" ))
(text "Ratio" (rect 77 91 177 192)(font "Arial" ))
(text "Ph (dg)" (rect 109 91 249 192)(font "Arial" ))
(text "DC (%)" (rect 144 91 320 192)(font "Arial" ))
(text "c0" (rect 54 104 119 218)(font "Arial" ))
(text "2/33" (rect 79 104 177 218)(font "Arial" ))
(text "0.00" (rect 115 104 249 218)(font "Arial" ))
(text "50.00" (rect 148 104 320 218)(font "Arial" ))
(text "c1" (rect 54 117 118 244)(font "Arial" ))
(text "16/33" (rect 77 117 177 244)(font "Arial" ))
(text "0.00" (rect 115 117 249 244)(font "Arial" ))
(text "50.00" (rect 148 117 320 244)(font "Arial" ))
(text "c2" (rect 54 130 119 270)(font "Arial" ))
(text "109/144" (rect 71 130 175 270)(font "Arial" ))
(text "0.00" (rect 115 130 249 270)(font "Arial" ))
(text "50.00" (rect 148 130 320 270)(font "Arial" ))
(text "c3" (rect 54 143 119 296)(font "Arial" ))
(text "16/11" (rect 77 143 176 296)(font "Arial" ))
(text "0.00" (rect 115 143 249 296)(font "Arial" ))
(text "50.00" (rect 148 143 320 296)(font "Arial" ))
(line (pt 0 0)(pt 257 0))
(line (pt 257 0)(pt 257 185))
(line (pt 0 185)(pt 257 185))
(line (pt 0 0)(pt 0 185))
(line (pt 48 89)(pt 176 89))
(line (pt 48 101)(pt 176 101))
(line (pt 48 114)(pt 176 114))
(line (pt 48 127)(pt 176 127))
(line (pt 48 140)(pt 176 140))
(line (pt 48 153)(pt 176 153))
(line (pt 48 89)(pt 48 153))
(line (pt 68 89)(pt 68 153)(line_width 3))
(line (pt 106 89)(pt 106 153)(line_width 3))
(line (pt 141 89)(pt 141 153)(line_width 3))
(line (pt 175 89)(pt 175 153))
(line (pt 40 48)(pt 223 48))
(line (pt 223 48)(pt 223 167))
(line (pt 40 167)(pt 223 167))
(line (pt 40 48)(pt 40 167))
(line (pt 255 64)(pt 223 64))
(line (pt 255 80)(pt 223 80))
(line (pt 255 96)(pt 223 96))
(line (pt 255 112)(pt 223 112))
)
)

2
FPGA_Quartus_13.1/altpll3.cmp
View File

@@ -1,4 +1,4 @@
--Copyright (C) 1991-2010 Altera Corporation
--Copyright (C) 1991-2014 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing

2
FPGA_Quartus_13.1/altpll3.inc
View File

@@ -1,4 +1,4 @@
--Copyright (C) 1991-2010 Altera Corporation
--Copyright (C) 1991-2014 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing

2
FPGA_Quartus_13.1/altpll3.qip
View File

@@ -1,5 +1,5 @@
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
set_global_assignment -name IP_TOOL_VERSION "9.1"
set_global_assignment -name IP_TOOL_VERSION "13.1"
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll3.vhd"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll3.bsf"]
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll3.inc"]

46
FPGA_Quartus_13.1/altpll3.vhd
View File

@@ -14,11 +14,11 @@
-- ************************************************************
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
--
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
-- ************************************************************
--Copyright (C) 1991-2010 Altera Corporation
--Copyright (C) 1991-2014 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
@@ -134,22 +134,22 @@ ARCHITECTURE SYN OF altpll3 IS
width_clock : NATURAL
);
PORT (
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0)
);
END COMPONENT;
BEGIN
sub_wire7_bv(0 DOWNTO 0) <= "0";
sub_wire7 <= To_stdlogicvector(sub_wire7_bv);
sub_wire4 <= sub_wire0(3);
sub_wire3 <= sub_wire0(2);
sub_wire2 <= sub_wire0(1);
sub_wire1 <= sub_wire0(0);
c0 <= sub_wire1;
c1 <= sub_wire2;
c2 <= sub_wire3;
c3 <= sub_wire4;
sub_wire4 <= sub_wire0(2);
sub_wire3 <= sub_wire0(0);
sub_wire2 <= sub_wire0(3);
sub_wire1 <= sub_wire0(1);
c1 <= sub_wire1;
c3 <= sub_wire2;
c0 <= sub_wire3;
c2 <= sub_wire4;
sub_wire5 <= inclk0;
sub_wire6 <= sub_wire7(0 DOWNTO 0) & sub_wire5;
@@ -164,9 +164,9 @@ BEGIN
clk1_duty_cycle => 50,
clk1_multiply_by => 16,
clk1_phase_shift => "0",
clk2_divide_by => 33,
clk2_divide_by => 144,
clk2_duty_cycle => 50,
clk2_multiply_by => 25,
clk2_multiply_by => 109,
clk2_phase_shift => "0",
clk3_divide_by => 11,
clk3_duty_cycle => 50,
@@ -251,7 +251,7 @@ END SYN;
-- Retrieval info: PRIVATE: DEVICE_SPEED_GRADE STRING "8"
-- Retrieval info: PRIVATE: DIV_FACTOR0 NUMERIC "33"
-- Retrieval info: PRIVATE: DIV_FACTOR1 NUMERIC "33"
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "33"
-- Retrieval info: PRIVATE: DIV_FACTOR2 NUMERIC "144"
-- Retrieval info: PRIVATE: DIV_FACTOR3 NUMERIC "33"
-- Retrieval info: PRIVATE: DUTY_CYCLE0 STRING "50.00000000"
-- Retrieval info: PRIVATE: DUTY_CYCLE1 STRING "50.00000000"
@@ -259,7 +259,7 @@ END SYN;
-- Retrieval info: PRIVATE: DUTY_CYCLE3 STRING "50.00000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE0 STRING "2.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE1 STRING "16.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "25.000000"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE2 STRING "24.979166"
-- Retrieval info: PRIVATE: EFF_OUTPUT_FREQ_VALUE3 STRING "48.000000"
-- Retrieval info: PRIVATE: EXPLICIT_SWITCHOVER_COUNTER STRING "0"
-- Retrieval info: PRIVATE: EXT_FEEDBACK_RADIO STRING "0"
@@ -278,7 +278,7 @@ END SYN;
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "330.000"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
@@ -291,7 +291,7 @@ END SYN;
-- Retrieval info: PRIVATE: MIRROR_CLK3 STRING "0"
-- Retrieval info: PRIVATE: MULT_FACTOR0 NUMERIC "2"
-- Retrieval info: PRIVATE: MULT_FACTOR1 NUMERIC "16"
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "25"
-- Retrieval info: PRIVATE: MULT_FACTOR2 NUMERIC "109"
-- Retrieval info: PRIVATE: MULT_FACTOR3 NUMERIC "48"
-- Retrieval info: PRIVATE: NORMAL_MODE_RADIO STRING "0"
-- Retrieval info: PRIVATE: OUTPUT_FREQ0 STRING "2.00000000"
@@ -365,9 +365,9 @@ END SYN;
-- Retrieval info: CONSTANT: CLK1_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK1_MULTIPLY_BY NUMERIC "16"
-- Retrieval info: CONSTANT: CLK1_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "33"
-- Retrieval info: CONSTANT: CLK2_DIVIDE_BY NUMERIC "144"
-- Retrieval info: CONSTANT: CLK2_DUTY_CYCLE NUMERIC "50"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "25"
-- Retrieval info: CONSTANT: CLK2_MULTIPLY_BY NUMERIC "109"
-- Retrieval info: CONSTANT: CLK2_PHASE_SHIFT STRING "0"
-- Retrieval info: CONSTANT: CLK3_DIVIDE_BY NUMERIC "11"
-- Retrieval info: CONSTANT: CLK3_DUTY_CYCLE NUMERIC "50"
@@ -428,17 +428,17 @@ END SYN;
-- Retrieval info: USED_PORT: c2 0 0 0 0 OUTPUT_CLK_EXT VCC "c2"
-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.vhd TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.ppf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.inc TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.cmp TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.bsf TRUE FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3.bsf TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3_inst.vhd FALSE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3_waveforms.html TRUE
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll3_wave*.jpg FALSE

1
FPGA_Quartus_13.1/firebee1.qsf
View File

@@ -742,4 +742,5 @@ set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip
set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip
set_global_assignment -name QIP_FILE altddio_out3.qip
set_global_assignment -name SOURCE_FILE firebee1.fit.summary_alt
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top

5
FPGA_Quartus_13.1/firebee1.sdc
View File

@@ -19,7 +19,7 @@
## PROGRAM "Quartus II"
## VERSION "Version 13.1.4 Build 182 03/12/2014 SJ Web Edition"
## DATE "Sun Sep 20 14:58:25 2015"
## DATE "Sun Sep 20 18:14:49 2015"
##
## DEVICE "EP3C40F484C6"
@@ -88,11 +88,14 @@ set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_video_clock_
set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] -to [get_clocks {i_video_clock_pll|altpll_component|auto_generated|pll1|clk[0]}]
set_false_path -from [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]
set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {MAIN_CLK}]
set_false_path -from [get_clocks {i_video_clock_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[2]}]
set_false_path -from [get_clocks {i_video_clock_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {MAIN_CLK}]
set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_id9:dffpipe17|dffe18a*}]
set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_hd9:dffpipe12|dffe13a*}]
set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_kd9:dffpipe15|dffe16a*}]
set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_jd9:dffpipe12|dffe13a*}]
set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_re9:dffpipe19|dffe20a*}]
set_false_path -from [get_keepers {Video:i_video|video_mod_mux_clutctr:i_video_mod_mux_clutctr|nBLANK}] -to [get_keepers {falconio_sdcard_ide_cf:i_falcon_io_sdcard_ide_cf|WF68901IP_TOP_SOC:I_MFP|WF68901IP_INTERRUPTS:I_INTERRUPTS|\EDGE_ENA:LOCK[3]}]
#**************************************************************