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renamed components to lower case

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This commit is contained in:
Markus Fröschle
2015-09-20 15:07:18 +00:00
parent 6288a1e16b
commit f72db5f2b5
2 changed files with 631 additions and 491 deletions
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10
FPGA_Quartus_13.1/DSP/DSP.vhd
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@@ -21,12 +21,12 @@
-- Created on Tue Sep 08 16:24:57 2009 -- Created on Tue Sep 08 16:24:57 2009
LIBRARY ieee; LIBRARY ieee;
USE ieee.std_logic_1164.all; USE ieee.std_logic_1164.all;
-- Entity Declaration -- Entity Declaration
ENTITY DSP IS ENTITY dsp IS
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
PORT PORT
( (
@@ -55,12 +55,12 @@ ENTITY DSP IS
); );
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
END DSP; END dsp;
-- Architecture Body -- Architecture Body
ARCHITECTURE DSP_architecture OF DSP IS ARCHITECTURE rtl OF DSP IS
BEGIN BEGIN
@@ -76,4 +76,4 @@ BEGIN
FB_AD(31 downto 16) <= SRD(15 downto 0) when nFB_OE = '0' and nSRCS = '0' else "ZZZZZZZZZZZZZZZZ"; FB_AD(31 downto 16) <= SRD(15 downto 0) when nFB_OE = '0' and nSRCS = '0' else "ZZZZZZZZZZZZZZZZ";
END DSP_architecture; END rtl;

1112
FPGA_Quartus_13.1/firebee1.bdf
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