ragnar/FPGA_Config
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get rid of CLK33M

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This commit is contained in:
Markus Fröschle
2015-09-20 12:32:02 +00:00
parent 489fb04b16
commit f416539480
5 changed files with 57 additions and 470 deletions
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4
FPGA_Quartus_13.1/Video/BLITTER/BLITTER.vhd
View File

@@ -26,7 +26,7 @@ USE ieee.std_logic_1164.all;
-- Entity Declaration
ENTITY BLITTER IS
ENTITY blitter IS
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
PORT
(
@@ -61,7 +61,7 @@ END BLITTER;
-- Architecture Body
ARCHITECTURE BLITTER_architecture OF BLITTER IS
ARCHITECTURE BLITTER_architecture OF blitter IS
BEGIN

23
FPGA_Quartus_13.1/Video/DDR_CTR.tdf
View File

@@ -225,15 +225,16 @@ BEGIN
DDR_CS.CLK = MAIN_CLK;
DDR_CS.ENA = FB_ALE;
DDR_CS = DDR_SEL;
-- WENN READ ODER WRITE B,W,L DDR SOFORT ANFORDERN, BEI WRITE LINE SP<53>TER
-- WENN READ ODER WRITE B,W,L DDR SOFORT ANFORDERN, BEI WRITE LINE SP<53>TER
CPU_SIG = DDR_SEL & (nFB_WR # !LINE) & !DDR_CONFIG -- NICHT LINE ODER READ SOFORT LOS WENN NICHT CONFIG
# DDR_SEL & DDR_CONFIG -- CONFIG SOFORT LOS
# FB_REGDDR==FR_S1 & !nFB_WR; -- LINE WRITE SP<53>TER
# FB_REGDDR==FR_S1 & !nFB_WR; -- LINE WRITE SP<53>TER
CPU_REQ.CLK = DDR_SYNC_66M;
CPU_REQ = CPU_SIG
# CPU_REQ & FB_REGDDR!=FR_S1 & FB_REGDDR!=FR_S3 & !BUS_CYC_END & !BUS_CYC; -- HALTEN BUS CYC BEGONNEN ODER FERTIG
BUS_CYC.CLK = DDRCLK0;
BUS_CYC = BUS_CYC & !BUS_CYC_END;
-- STATE MACHINE SYNCHRONISIEREN -----------------
MCS[].CLK = DDRCLK0;
MCS0 = MAIN_CLK;
@@ -341,7 +342,7 @@ BEGIN
CPU_AC = CPU_AC;
BLITTER_AC = BLITTER_AC;
VCAS = VCC;
SR_DDR_FB = CPU_AC; -- READ DATEN F<>R CPU
SR_DDR_FB = CPU_AC; -- READ DATEN F<>R CPU
SR_BLITTER_DACK = BLITTER_AC; -- BLITTER DACK AND BLITTER LATCH DATEN
DDR_SM = DS_T5R;
@@ -383,7 +384,7 @@ BEGIN
VCAS = VCC;
VWE = VCC;
SR_DDR_WR = VCC; -- WRITE COMMAND CPU UND BLITTER IF WRITER
SR_DDRWR_D_SEL = VCC; -- 2. H<>LFTE WRITE DATEN SELEKTIEREN
SR_DDRWR_D_SEL = VCC; -- 2. H<>LFTE WRITE DATEN SELEKTIEREN
SR_VDMP[] = LINE & B"11111111"; -- WENN LINE DANN ACTIV
DDR_SM = DS_T7W;
@@ -391,7 +392,7 @@ BEGIN
CPU_AC = CPU_AC;
BLITTER_AC = BLITTER_AC;
SR_DDR_WR = VCC; -- WRITE COMMAND CPU UND BLITTER IF WRITE
SR_DDRWR_D_SEL = VCC; -- 2. H<>LFTE WRITE DATEN SELEKTIEREN
SR_DDRWR_D_SEL = VCC; -- 2. H<>LFTE WRITE DATEN SELEKTIEREN
DDR_SM = DS_T8W;
WHEN DS_T8W =>
@@ -523,12 +524,12 @@ BEGIN
-- CLOSE FIFO BANK
WHEN DS_CB6 =>
FIFO_BANK_NOT_OK = VCC; -- AUF NOT OK
VRAS = VCC; -- B<>NKE SCHLIESSEN
VRAS = VCC; -- B<>NKE SCHLIESSEN
VWE = VCC;
DDR_SM = DS_N7;
WHEN DS_CB8 =>
FIFO_BANK_NOT_OK = VCC; -- AUF NOT OK
VRAS = VCC; -- B<>NKE SCHLIESSEN
VRAS = VCC; -- B<>NKE SCHLIESSEN
VWE = VCC;
DDR_SM = DS_T1;
-- REFRESH 70NS = 10 ZYCLEN
@@ -584,14 +585,14 @@ BEGIN
FIFO_COL_ADR[] = (VIDEO_ADR_CNT[7..0],B"00");
FIFO_BANK_OK.CLK = DDRCLK0;
FIFO_BANK_OK = FIFO_BANK_OK & !FIFO_BANK_NOT_OK;
-- Z<>HLER R<>CKSETZEN WENN CLR FIFO ----------------
-- Z<>HLER R<>CKSETZEN WENN CLR FIFO ----------------
CLR_FIFO_SYNC.CLK =DDRCLK0;
CLR_FIFO_SYNC = CLR_FIFO; -- SYNCHRONISIEREN
CLEAR_FIFO_CNT.CLK = DDRCLK0;
CLEAR_FIFO_CNT = CLR_FIFO_SYNC # !FIFO_ACTIVE;
STOP.CLK = DDRCLK0;
STOP = CLR_FIFO_SYNC # CLEAR_FIFO_CNT;
-- Z<>HLEN -----------------------------------------------
-- Z<>HLEN -----------------------------------------------
VIDEO_ADR_CNT[].CLK = DDRCLK0;
VIDEO_ADR_CNT[].ENA = SR_FIFO_WRE # CLEAR_FIFO_CNT;
VIDEO_ADR_CNT[] = CLEAR_FIFO_CNT & VIDEO_BASE_ADR[]
@@ -608,12 +609,12 @@ BEGIN
-- REFRESH: IMMER 8 AUFS MAL, ANFORDERUNG ALLE 7.8us X 8 STCK. = 62.4us = 2059->2048 33MHz CLOCKS
-----------------------------------------------------------------------------------------
DDR_REFRESH_CNT[].CLK = CLK33M;
DDR_REFRESH_CNT[] = DDR_REFRESH_CNT[]+1; -- Z<>HLEN 0-2047
DDR_REFRESH_CNT[] = DDR_REFRESH_CNT[]+1; -- Z<>HLEN 0-2047
REFRESH_TIME.CLK = DDRCLK0;
REFRESH_TIME = DDR_REFRESH_CNT[]==0 & !MAIN_CLK; -- SYNC
DDR_REFRESH_SIG[].CLK = DDRCLK0;
DDR_REFRESH_SIG[].ENA = REFRESH_TIME # DDR_SM==DS_R6;
DDR_REFRESH_SIG[] = REFRESH_TIME & 9 & DDR_REFRESH_ON & !DDR_CONFIG -- 9 ST<53>CK (8 REFRESH UND 1 ALS VORLAUF)
DDR_REFRESH_SIG[] = REFRESH_TIME & 9 & DDR_REFRESH_ON & !DDR_CONFIG -- 9 ST<53>CK (8 REFRESH UND 1 ALS VORLAUF)
# !REFRESH_TIME & (DDR_REFRESH_SIG[]-1) & DDR_REFRESH_ON & !DDR_CONFIG; -- MINUS 1 WENN GEMACHT
DDR_REFRESH_REQ.CLK = DDRCLK0;
DDR_REFRESH_REQ = DDR_REFRESH_SIG[]!=0 & DDR_REFRESH_ON & !REFRESH_TIME & !DDR_CONFIG;

2
FPGA_Quartus_13.1/Video/VIDEO_MOD_MUX_CLUTCTR.tdf
View File

@@ -8,7 +8,7 @@ INCLUDE "lpm_bustri_BYT.inc";
-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
SUBDESIGN VIDEO_MOD_MUX_CLUTCTR
SUBDESIGN video_mod_mux_clutctr
(
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
nRSTO : INPUT;

91
FPGA_Quartus_13.1/firebee1.bdf
View File

@@ -57,23 +57,6 @@ applicable agreement for further details.
(text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6)))
(annotation_block (location)(rect 944 952 1000 968))
)
(pin
(input)
(rect 168 296 336 312)
(text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6)))
(text "CLK33M" (rect 9 0 53 11)(font "Arial" ))
(pt 168 8)
(drawing
(line (pt 92 12)(pt 117 12))
(line (pt 92 4)(pt 117 4))
(line (pt 121 8)(pt 168 8))
(line (pt 92 12)(pt 92 4))
(line (pt 117 4)(pt 121 8))
(line (pt 117 12)(pt 121 8))
)
(text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6)))
(annotation_block (location)(rect 104 312 176 328))
)
(pin
(input)
(rect 992 960 1160 976)
@@ -856,23 +839,6 @@ applicable agreement for further details.
(text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6)))
(annotation_block (location)(rect 808 1632 872 1648))
)
(pin
(input)
(rect 96 -288 264 -272)
(text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6)))
(text "MAIN_CLK" (rect 9 0 66 11)(font "Arial" ))
(pt 168 8)
(drawing
(line (pt 92 12)(pt 117 12))
(line (pt 92 4)(pt 117 4))
(line (pt 121 8)(pt 168 8))
(line (pt 92 12)(pt 92 4))
(line (pt 117 4)(pt 121 8))
(line (pt 117 12)(pt 121 8))
)
(text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6)))
(annotation_block (location)(rect 56 -304 120 -288))
)
(pin
(input)
(rect 664 440 840 456)
@@ -890,6 +856,23 @@ applicable agreement for further details.
(text "VCC" (rect 144 7 165 17)(font "Arial" (font_size 6)))
(annotation_block (location)(rect 600 448 664 464))
)
(pin
(input)
(rect 168 296 336 312)
(text "INPUT" (rect 133 0 162 10)(font "Arial" (font_size 6)))
(text "MAIN_CLK" (rect 5 0 63 11)(font "Arial" ))
(pt 168 8)
(drawing
(line (pt 92 12)(pt 117 12))
(line (pt 92 4)(pt 117 4))
(line (pt 121 8)(pt 168 8))
(line (pt 92 12)(pt 92 4))
(line (pt 117 4)(pt 121 8))
(line (pt 117 12)(pt 121 8))
)
(text "VCC" (rect 136 7 157 17)(font "Arial" (font_size 6)))
(annotation_block (location)(rect 104 312 176 328))
)
(pin
(output)
(rect 864 288 1040 304)
@@ -4379,11 +4362,6 @@ applicable agreement for further details.
(pt 1152 800)
(pt 1264 800)
)
(connector
(text "CLK33M" (rect 1210 760 1254 771)(font "Arial" ))
(pt 1200 776)
(pt 1264 776)
)
(connector
(text "CLK2M" (rect 1202 808 1240 819)(font "Arial" ))
(pt 1192 824)
@@ -5042,11 +5020,6 @@ applicable agreement for further details.
(pt 776 1496)
(pt 1264 1496)
)
(connector
(text "CLK33M" (rect 346 288 390 299)(font "Arial" ))
(pt 336 304)
(pt 400 304)
)
(connector
(text "CLK25M" (rect 1202 608 1246 619)(font "Arial" ))
(pt 1192 624)
@@ -5662,11 +5635,6 @@ applicable agreement for further details.
(pt 984 568)
(pt 1264 568)
)
(connector
(text "CLK33M" (rect 1202 584 1246 595)(font "Arial" ))
(pt 1264 600)
(pt 1192 600)
)
(connector
(text "CLK500k" (rect 802 232 849 243)(font "Arial" ))
(pt 768 248)
@@ -5734,11 +5702,6 @@ applicable agreement for further details.
(pt 1152 3024)
(pt 1264 3024)
)
(connector
(text "CLK33M" (rect 1210 2984 1254 2995)(font "Arial" ))
(pt 1200 3000)
(pt 1264 3000)
)
(connector
(text "nFB_WR" (rect 1170 3056 1216 3067)(font "Arial" ))
(pt 1264 3072)
@@ -5831,6 +5794,26 @@ applicable agreement for further details.
(pt 1264 3144)
(pt 1160 3144)
)
(connector
(text "MAIN_CLK" (rect 346 288 403 299)(font "Arial" ))
(pt 336 304)
(pt 400 304)
)
(connector
(text "MAIN_CLK" (rect 1202 584 1259 595)(font "Arial" ))
(pt 1264 600)
(pt 1192 600)
)
(connector
(text "MAIN_CLK" (rect 1210 760 1267 771)(font "Arial" ))
(pt 1200 776)
(pt 1264 776)
)
(connector
(text "MAIN_CLK" (rect 1210 2984 1267 2995)(font "Arial" ))
(pt 1200 3000)
(pt 1264 3000)
)
(junction (pt 2504 760))
(junction (pt 400 248))
(junction (pt 1856 -64))

407
FPGA_Quartus_13.1/firebee1.sdc
View File

@@ -19,7 +19,7 @@
## PROGRAM "Quartus II"
## VERSION "Version 13.1.4 Build 182 03/12/2014 SJ Web Edition"
## DATE "Sun Sep 20 08:38:08 2015"
## DATE "Sun Sep 20 10:41:57 2015"
##
## DEVICE "EP3C40F484C6"
@@ -38,37 +38,14 @@ set_time_format -unit ns -decimal_places 3
# Create Clock
#**************************************************************
create_clock -name {CLK33M} -period 30.303 -waveform { 0.000 15.151 } [get_ports {CLK33M}]
create_clock -name {MAIN_CLK} -period 30.303 -waveform { 0.000 15.151 } [get_ports {MAIN_CLK}]
create_clock -name {E0_INT} -period 1.000 -waveform { 0.000 0.500 } [get_ports {E0_INT}]
create_clock -name {nPCI_INTB} -period 1.000 -waveform { 0.000 0.500 } [get_ports {nPCI_INTB}]
create_clock -name {nPCI_INTA} -period 1.000 -waveform { 0.000 0.500 } [get_ports {nPCI_INTA}]
create_clock -name {DVI_INT} -period 1.000 -waveform { 0.000 0.500 } [get_ports {DVI_INT}]
create_clock -name {nPCI_INTC} -period 1.000 -waveform { 0.000 0.500 } [get_ports {nPCI_INTC}]
create_clock -name {nPCI_INTD} -period 1.000 -waveform { 0.000 0.500 } [get_ports {nPCI_INTD}]
create_clock -name {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC} -period 1.000 -waveform { 0.000 0.500 } [get_registers {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}]
create_clock -name {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC} -period 1.000 -waveform { 0.000 0.500 } [get_registers {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}]
create_clock -name {PIC_INT} -period 1.000 -waveform { 0.000 0.500 } [get_ports {PIC_INT}]
#**************************************************************
# Create Generated Clock
#**************************************************************
create_generated_clock -name {inst|altpll_component|auto_generated|pll1|clk[0]} -source [get_pins {inst|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 1 -divide_by 66 -master_clock {CLK33M} [get_pins {inst|altpll_component|auto_generated|pll1|clk[0]}]
create_generated_clock -name {inst|altpll_component|auto_generated|pll1|clk[1]} -source [get_pins {inst|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 67 -divide_by 900 -master_clock {CLK33M} [get_pins {inst|altpll_component|auto_generated|pll1|clk[1]}]
create_generated_clock -name {inst|altpll_component|auto_generated|pll1|clk[2]} -source [get_pins {inst|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 67 -divide_by 90 -master_clock {CLK33M} [get_pins {inst|altpll_component|auto_generated|pll1|clk[2]}]
create_generated_clock -name {inst13|altpll_component|auto_generated|pll1|clk[0]} -source [get_pins {inst13|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 109 -divide_by 1800 -master_clock {CLK33M} [get_pins {inst13|altpll_component|auto_generated|pll1|clk[0]}]
create_generated_clock -name {inst13|altpll_component|auto_generated|pll1|clk[1]} -source [get_pins {inst13|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 109 -divide_by 225 -master_clock {CLK33M} [get_pins {inst13|altpll_component|auto_generated|pll1|clk[1]}]
create_generated_clock -name {inst13|altpll_component|auto_generated|pll1|clk[2]} -source [get_pins {inst13|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 109 -divide_by 144 -master_clock {CLK33M} [get_pins {inst13|altpll_component|auto_generated|pll1|clk[2]}]
create_generated_clock -name {inst13|altpll_component|auto_generated|pll1|clk[3]} -source [get_pins {inst13|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 109 -divide_by 75 -master_clock {CLK33M} [get_pins {inst13|altpll_component|auto_generated|pll1|clk[3]}]
create_generated_clock -name {inst12|altpll_component|auto_generated|pll1|clk[0]} -source [get_pins {inst12|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 4 -phase 240.000 -master_clock {MAIN_CLK} [get_pins {inst12|altpll_component|auto_generated|pll1|clk[0]}]
create_generated_clock -name {inst12|altpll_component|auto_generated|pll1|clk[1]} -source [get_pins {inst12|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 4 -master_clock {MAIN_CLK} [get_pins {inst12|altpll_component|auto_generated|pll1|clk[1]}]
create_generated_clock -name {inst12|altpll_component|auto_generated|pll1|clk[2]} -source [get_pins {inst12|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 4 -phase 180.000 -master_clock {MAIN_CLK} [get_pins {inst12|altpll_component|auto_generated|pll1|clk[2]}]
create_generated_clock -name {inst12|altpll_component|auto_generated|pll1|clk[3]} -source [get_pins {inst12|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 4 -phase 105.000 -master_clock {MAIN_CLK} [get_pins {inst12|altpll_component|auto_generated|pll1|clk[3]}]
create_generated_clock -name {inst12|altpll_component|auto_generated|pll1|clk[4]} -source [get_pins {inst12|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 2 -phase 270.000 -master_clock {MAIN_CLK} [get_pins {inst12|altpll_component|auto_generated|pll1|clk[4]}]
create_generated_clock -name {inst22|altpll_component|auto_generated|pll1|clk[0]} -source [get_pins {inst22|altpll_component|auto_generated|pll1|inclk[0]}] -duty_cycle 50.000 -multiply_by 2 -master_clock {inst13|altpll_component|auto_generated|pll1|clk[3]} [get_pins {inst22|altpll_component|auto_generated|pll1|clk[0]}]
derive_pll_clocks
#**************************************************************
# Set Clock Latency
@@ -80,382 +57,8 @@ create_generated_clock -name {inst22|altpll_component|auto_generated|pll1|clk[0]
# Set Clock Uncertainty
#**************************************************************
set_clock_uncertainty -rise_from [get_clocks {inst|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst|altpll_component|auto_generated|pll1|clk[0]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {inst|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst|altpll_component|auto_generated|pll1|clk[0]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {inst|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {MAIN_CLK}] -setup 0.110
set_clock_uncertainty -rise_from [get_clocks {inst|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {MAIN_CLK}] -hold 0.080
set_clock_uncertainty -rise_from [get_clocks {inst|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {MAIN_CLK}] -setup 0.110
set_clock_uncertainty -rise_from [get_clocks {inst|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {MAIN_CLK}] -hold 0.080
set_clock_uncertainty -fall_from [get_clocks {inst|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst|altpll_component|auto_generated|pll1|clk[0]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {inst|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst|altpll_component|auto_generated|pll1|clk[0]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {inst|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {MAIN_CLK}] -setup 0.110
set_clock_uncertainty -fall_from [get_clocks {inst|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {MAIN_CLK}] -hold 0.080
set_clock_uncertainty -fall_from [get_clocks {inst|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {MAIN_CLK}] -setup 0.110
set_clock_uncertainty -fall_from [get_clocks {inst|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {MAIN_CLK}] -hold 0.080
set_clock_uncertainty -rise_from [get_clocks {PIC_INT}] -rise_to [get_clocks {MAIN_CLK}] 0.030
set_clock_uncertainty -rise_from [get_clocks {PIC_INT}] -fall_to [get_clocks {MAIN_CLK}] 0.030
set_clock_uncertainty -fall_from [get_clocks {PIC_INT}] -rise_to [get_clocks {MAIN_CLK}] 0.030
set_clock_uncertainty -fall_from [get_clocks {PIC_INT}] -fall_to [get_clocks {MAIN_CLK}] 0.030
set_clock_uncertainty -rise_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -rise_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.080
set_clock_uncertainty -rise_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -rise_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.130
set_clock_uncertainty -rise_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -fall_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.080
set_clock_uncertainty -rise_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -fall_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.130
set_clock_uncertainty -rise_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -setup 0.060
set_clock_uncertainty -rise_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -hold 0.090
set_clock_uncertainty -rise_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -setup 0.060
set_clock_uncertainty -rise_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -hold 0.090
set_clock_uncertainty -rise_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -rise_to [get_clocks {CLK33M}] 0.020
set_clock_uncertainty -rise_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -fall_to [get_clocks {CLK33M}] 0.020
set_clock_uncertainty -fall_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -rise_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.080
set_clock_uncertainty -fall_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -rise_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.130
set_clock_uncertainty -fall_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -fall_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.080
set_clock_uncertainty -fall_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -fall_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.130
set_clock_uncertainty -fall_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -setup 0.060
set_clock_uncertainty -fall_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -hold 0.090
set_clock_uncertainty -fall_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -setup 0.060
set_clock_uncertainty -fall_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -hold 0.090
set_clock_uncertainty -fall_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -rise_to [get_clocks {CLK33M}] 0.020
set_clock_uncertainty -fall_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -fall_to [get_clocks {CLK33M}] 0.020
set_clock_uncertainty -rise_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -rise_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.080
set_clock_uncertainty -rise_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -rise_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.130
set_clock_uncertainty -rise_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -fall_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.080
set_clock_uncertainty -rise_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -fall_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.130
set_clock_uncertainty -rise_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -setup 0.060
set_clock_uncertainty -rise_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -hold 0.090
set_clock_uncertainty -rise_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -setup 0.060
set_clock_uncertainty -rise_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -hold 0.090
set_clock_uncertainty -rise_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -rise_to [get_clocks {CLK33M}] 0.020
set_clock_uncertainty -rise_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -fall_to [get_clocks {CLK33M}] 0.020
set_clock_uncertainty -fall_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -rise_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.080
set_clock_uncertainty -fall_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -rise_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.130
set_clock_uncertainty -fall_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -fall_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.080
set_clock_uncertainty -fall_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -fall_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.130
set_clock_uncertainty -fall_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -setup 0.060
set_clock_uncertainty -fall_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -hold 0.090
set_clock_uncertainty -fall_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -setup 0.060
set_clock_uncertainty -fall_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -hold 0.090
set_clock_uncertainty -fall_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -rise_to [get_clocks {CLK33M}] 0.020
set_clock_uncertainty -fall_from [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -fall_to [get_clocks {CLK33M}] 0.020
set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -setup 0.130
set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -hold 0.080
set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -setup 0.130
set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -hold 0.080
set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -setup 0.130
set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -hold 0.080
set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -setup 0.130
set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -hold 0.080
set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] 0.030
set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] 0.030
set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {MAIN_CLK}] -setup 0.140
set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {MAIN_CLK}] -hold 0.100
set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {MAIN_CLK}] -setup 0.140
set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {MAIN_CLK}] -hold 0.100
set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.190
set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.180
set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.190
set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.180
set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -setup 0.100
set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -hold 0.080
set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -setup 0.100
set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -hold 0.080
set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {CLK33M}] -setup 0.130
set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {CLK33M}] -hold 0.090
set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {CLK33M}] -setup 0.130
set_clock_uncertainty -rise_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {CLK33M}] -hold 0.090
set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -setup 0.130
set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -hold 0.080
set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -setup 0.130
set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -hold 0.080
set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -setup 0.130
set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -hold 0.080
set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -setup 0.130
set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -hold 0.080
set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] 0.030
set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] 0.030
set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {MAIN_CLK}] -setup 0.140
set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {MAIN_CLK}] -hold 0.100
set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {MAIN_CLK}] -setup 0.140
set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {MAIN_CLK}] -hold 0.100
set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.190
set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.180
set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.190
set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.180
set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -setup 0.100
set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -hold 0.080
set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -setup 0.100
set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -hold 0.080
set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {CLK33M}] -setup 0.130
set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {CLK33M}] -hold 0.090
set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {CLK33M}] -setup 0.130
set_clock_uncertainty -fall_from [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {CLK33M}] -hold 0.090
set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[3]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[3]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {MAIN_CLK}] -setup 0.090
set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {MAIN_CLK}] -hold 0.070
set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {MAIN_CLK}] -setup 0.090
set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {MAIN_CLK}] -hold 0.070
set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -setup 0.150
set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -hold 0.160
set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -setup 0.150
set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -hold 0.160
set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[3]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[3]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {MAIN_CLK}] -setup 0.090
set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {MAIN_CLK}] -hold 0.070
set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {MAIN_CLK}] -setup 0.090
set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {MAIN_CLK}] -hold 0.070
set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -setup 0.150
set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -hold 0.160
set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -setup 0.150
set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -hold 0.160
set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[3]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[3]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[3]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[3]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[3]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[3]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[3]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[3]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[3]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[3]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[1]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[1]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[1]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[1]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {PIC_INT}] 0.030
set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {PIC_INT}] 0.030
set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] 0.020
set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] 0.020
set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] 0.020
set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] 0.020
set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {nPCI_INTD}] 0.030
set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {nPCI_INTD}] 0.030
set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {nPCI_INTC}] 0.030
set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {nPCI_INTC}] 0.030
set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {DVI_INT}] 0.030
set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {DVI_INT}] 0.030
set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {nPCI_INTA}] 0.030
set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {nPCI_INTA}] 0.030
set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {nPCI_INTB}] 0.030
set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {nPCI_INTB}] 0.030
set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {E0_INT}] 0.030
set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {E0_INT}] 0.030
set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.100
set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.140
set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.100
set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.140
set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -setup 0.070
set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -hold 0.090
set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -setup 0.070
set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -hold 0.090
set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.070
set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.090
set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.070
set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.090
set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -setup 0.070
set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -hold 0.100
set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -setup 0.070
set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -hold 0.100
set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -setup 0.070
set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -hold 0.100
set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -setup 0.070
set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -hold 0.100
set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {CLK33M}] 0.030
set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {CLK33M}] 0.030
set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {PIC_INT}] 0.030
set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {PIC_INT}] 0.030
set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] 0.020
set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] 0.020
set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] 0.020
set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] 0.020
set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {nPCI_INTD}] 0.030
set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {nPCI_INTD}] 0.030
set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {nPCI_INTC}] 0.030
set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {nPCI_INTC}] 0.030
set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {DVI_INT}] 0.030
set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {DVI_INT}] 0.030
set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {nPCI_INTA}] 0.030
set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {nPCI_INTA}] 0.030
set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {nPCI_INTB}] 0.030
set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {nPCI_INTB}] 0.030
set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {E0_INT}] 0.030
set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {E0_INT}] 0.030
set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.100
set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.140
set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.100
set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.140
set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -setup 0.070
set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -hold 0.090
set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -setup 0.070
set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] -hold 0.090
set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.070
set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.090
set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.070
set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.090
set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -setup 0.070
set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -hold 0.100
set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -setup 0.070
set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -hold 0.100
set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -setup 0.070
set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -hold 0.100
set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -setup 0.070
set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -hold 0.100
set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {CLK33M}] 0.030
set_clock_uncertainty -fall_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {CLK33M}] 0.030
set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[3]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[3]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[2]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[2]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {MAIN_CLK}] -setup 0.090
set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {MAIN_CLK}] -hold 0.070
set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {MAIN_CLK}] -setup 0.090
set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {MAIN_CLK}] -hold 0.070
set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[4]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[3]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[3]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[2]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[2]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {MAIN_CLK}] -setup 0.090
set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {MAIN_CLK}] -hold 0.070
set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {MAIN_CLK}] -setup 0.090
set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {MAIN_CLK}] -hold 0.070
set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -setup 0.090
set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -hold 0.060
set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -setup 0.090
set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -hold 0.060
set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -setup 0.090
set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -hold 0.060
set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -setup 0.090
set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -hold 0.060
set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.080
set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.100
set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.080
set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.100
set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {MAIN_CLK}] -setup 0.100
set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {MAIN_CLK}] -hold 0.070
set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {MAIN_CLK}] -setup 0.100
set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {MAIN_CLK}] -hold 0.070
set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.160
set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.150
set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.160
set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.150
set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] 0.030
set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] 0.030
set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {CLK33M}] -setup 0.090
set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {CLK33M}] -hold 0.060
set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {CLK33M}] -setup 0.090
set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {CLK33M}] -hold 0.060
set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -setup 0.090
set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -hold 0.060
set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -setup 0.090
set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] -hold 0.060
set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -setup 0.090
set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -hold 0.060
set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -setup 0.090
set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] -hold 0.060
set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.080
set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.100
set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.080
set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.100
set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {MAIN_CLK}] -setup 0.100
set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {MAIN_CLK}] -hold 0.070
set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {MAIN_CLK}] -setup 0.100
set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {MAIN_CLK}] -hold 0.070
set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.160
set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.150
set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.160
set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.150
set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] 0.030
set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] 0.030
set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {CLK33M}] -setup 0.090
set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -rise_to [get_clocks {CLK33M}] -hold 0.060
set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {CLK33M}] -setup 0.090
set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -fall_to [get_clocks {CLK33M}] -hold 0.060
set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {MAIN_CLK}] -setup 0.100
set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {MAIN_CLK}] -hold 0.070
set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {MAIN_CLK}] -setup 0.100
set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {MAIN_CLK}] -hold 0.070
set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {MAIN_CLK}] -setup 0.100
set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {MAIN_CLK}] -hold 0.070
set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {MAIN_CLK}] -setup 0.100
set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {MAIN_CLK}] -hold 0.070
set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[1]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {MAIN_CLK}] -setup 0.100
set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {MAIN_CLK}] -hold 0.070
set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {MAIN_CLK}] -setup 0.100
set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {MAIN_CLK}] -hold 0.070
set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[0]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[0]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {MAIN_CLK}] -setup 0.100
set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {MAIN_CLK}] -hold 0.070
set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {MAIN_CLK}] -setup 0.100
set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {MAIN_CLK}] -hold 0.070
set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[0]}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[0]}] 0.020
set_clock_uncertainty -fall_from [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[0]}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[0]}] 0.020
set_clock_uncertainty -rise_from [get_clocks {inst|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {MAIN_CLK}] 0.030
set_clock_uncertainty -rise_from [get_clocks {inst|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {MAIN_CLK}] 0.030
set_clock_uncertainty -fall_from [get_clocks {inst|altpll_component|auto_generated|pll1|clk[1]}] -rise_to [get_clocks {MAIN_CLK}] 0.030
set_clock_uncertainty -fall_from [get_clocks {inst|altpll_component|auto_generated|pll1|clk[1]}] -fall_to [get_clocks {MAIN_CLK}] 0.030
set_clock_uncertainty -rise_from [get_clocks {CLK33M}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] 0.020
set_clock_uncertainty -rise_from [get_clocks {CLK33M}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] 0.020
set_clock_uncertainty -rise_from [get_clocks {CLK33M}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] 0.020
set_clock_uncertainty -rise_from [get_clocks {CLK33M}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] 0.020
set_clock_uncertainty -rise_from [get_clocks {CLK33M}] -rise_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.090
set_clock_uncertainty -rise_from [get_clocks {CLK33M}] -rise_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.130
set_clock_uncertainty -rise_from [get_clocks {CLK33M}] -fall_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.090
set_clock_uncertainty -rise_from [get_clocks {CLK33M}] -fall_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.130
set_clock_uncertainty -rise_from [get_clocks {CLK33M}] -rise_to [get_clocks {MAIN_CLK}] 0.030
set_clock_uncertainty -rise_from [get_clocks {CLK33M}] -fall_to [get_clocks {MAIN_CLK}] 0.030
set_clock_uncertainty -rise_from [get_clocks {CLK33M}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.090
set_clock_uncertainty -rise_from [get_clocks {CLK33M}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.110
set_clock_uncertainty -rise_from [get_clocks {CLK33M}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.090
set_clock_uncertainty -rise_from [get_clocks {CLK33M}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.110
set_clock_uncertainty -rise_from [get_clocks {CLK33M}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -setup 0.060
set_clock_uncertainty -rise_from [get_clocks {CLK33M}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -hold 0.090
set_clock_uncertainty -rise_from [get_clocks {CLK33M}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -setup 0.060
set_clock_uncertainty -rise_from [get_clocks {CLK33M}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -hold 0.090
set_clock_uncertainty -rise_from [get_clocks {CLK33M}] -rise_to [get_clocks {CLK33M}] 0.020
set_clock_uncertainty -rise_from [get_clocks {CLK33M}] -fall_to [get_clocks {CLK33M}] 0.020
set_clock_uncertainty -fall_from [get_clocks {CLK33M}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] 0.020
set_clock_uncertainty -fall_from [get_clocks {CLK33M}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|HSYNC}] 0.020
set_clock_uncertainty -fall_from [get_clocks {CLK33M}] -rise_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] 0.020
set_clock_uncertainty -fall_from [get_clocks {CLK33M}] -fall_to [get_clocks {Video:Fredi_Aschwanden|VIDEO_MOD_MUX_CLUTCTR:VIDEO_MOD_MUX_CLUTCTR|VSYNC}] 0.020
set_clock_uncertainty -fall_from [get_clocks {CLK33M}] -rise_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.090
set_clock_uncertainty -fall_from [get_clocks {CLK33M}] -rise_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.130
set_clock_uncertainty -fall_from [get_clocks {CLK33M}] -fall_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.090
set_clock_uncertainty -fall_from [get_clocks {CLK33M}] -fall_to [get_clocks {inst22|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.130
set_clock_uncertainty -fall_from [get_clocks {CLK33M}] -rise_to [get_clocks {MAIN_CLK}] 0.030
set_clock_uncertainty -fall_from [get_clocks {CLK33M}] -fall_to [get_clocks {MAIN_CLK}] 0.030
set_clock_uncertainty -fall_from [get_clocks {CLK33M}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.090
set_clock_uncertainty -fall_from [get_clocks {CLK33M}] -rise_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.110
set_clock_uncertainty -fall_from [get_clocks {CLK33M}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -setup 0.090
set_clock_uncertainty -fall_from [get_clocks {CLK33M}] -fall_to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}] -hold 0.110
set_clock_uncertainty -fall_from [get_clocks {CLK33M}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -setup 0.060
set_clock_uncertainty -fall_from [get_clocks {CLK33M}] -rise_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -hold 0.090
set_clock_uncertainty -fall_from [get_clocks {CLK33M}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -setup 0.060
set_clock_uncertainty -fall_from [get_clocks {CLK33M}] -fall_to [get_clocks {inst13|altpll_component|auto_generated|pll1|clk[2]}] -hold 0.090
set_clock_uncertainty -fall_from [get_clocks {CLK33M}] -rise_to [get_clocks {CLK33M}] 0.020
set_clock_uncertainty -fall_from [get_clocks {CLK33M}] -fall_to [get_clocks {CLK33M}] 0.020
set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -rise_to [get_clocks {MAIN_CLK}] 0.050
set_clock_uncertainty -rise_from [get_clocks {MAIN_CLK}] -fall_to [get_clocks {MAIN_CLK}] 0.050
#**************************************************************
@@ -480,7 +83,6 @@ set_clock_uncertainty -fall_from [get_clocks {CLK33M}] -fall_to [get_clocks {CLK
# Set False Path
#**************************************************************
set_false_path -from [get_clocks {CLK33M}] -to [get_clocks {inst12|altpll_component|auto_generated|pll1|clk[0]}]
set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_id9:dffpipe17|dffe18a*}]
set_false_path -from [get_keepers {*delayed_wrptr_g*}] -to [get_keepers {*rs_dgwp|dffpipe_hd9:dffpipe12|dffe13a*}]
set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpipe_kd9:dffpipe15|dffe16a*}]
@@ -492,6 +94,7 @@ set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpip
# Set Multicycle Path
#**************************************************************
set_multicycle_path -hold -end -from [get_clocks {MAIN_CLK}] -to [get_keepers {Video:i_video|DDR_CTR:i_ddr_ctr|MCS[0]}] 2
#**************************************************************