From f1a038e3a5171f0a17416180047d824111d7ac1d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Markus=20Fr=C3=B6schle?= Date: Thu, 28 Jul 2016 11:48:10 +0000 Subject: [PATCH] finally fixed multiple drivers problem --- FPGA_Quartus_13.1/DSP/DSP.vhd | 8 +- .../FalconIO_SDCard_IDE_CF.vhd | 137 +-- .../Interrupt_Handler/interrupt_handler.vhd | 155 +-- FPGA_Quartus_13.1/Video/BLITTER/BLITTER.vhd | 100 +- FPGA_Quartus_13.1/Video/DDR_CTR.vhd | 30 +- FPGA_Quartus_13.1/Video/video.vhd | 926 +++++++++--------- .../Video/video_mod_mux_clutctr.vhd | 94 +- FPGA_Quartus_13.1/firebee1.vhd | 46 +- FPGA_Quartus_13.1/firebee_utils_pkg.vhd | 171 ---- 9 files changed, 760 insertions(+), 907 deletions(-) delete mode 100644 FPGA_Quartus_13.1/firebee_utils_pkg.vhd diff --git a/FPGA_Quartus_13.1/DSP/DSP.vhd b/FPGA_Quartus_13.1/DSP/DSP.vhd index 22ae2ee..2873ce7 100644 --- a/FPGA_Quartus_13.1/DSP/DSP.vhd +++ b/FPGA_Quartus_13.1/DSP/DSP.vhd @@ -49,7 +49,8 @@ ENTITY dsp IS nSROE : OUT std_logic; DSP_INT : OUT std_logic; DSP_TA : OUT std_logic; - FB_AD : INOUT std_logic_vector(31 DOWNTO 0); + fb_ad_in : in std_logic_vector(31 downto 0); + fb_ad_out : out std_logic_vector(31 downto 0); IO : INOUT std_logic_vector(17 DOWNTO 0); SRD : INOUT std_logic_vector(15 DOWNTO 0) ); @@ -72,6 +73,7 @@ BEGIN DSP_INT <= '0'; DSP_TA <= '0'; IO(17 DOWNTO 0) <= FB_ADR(18 DOWNTO 1); - SRD(15 DOWNTO 0) <= FB_AD(31 DOWNTO 16) WHEN nFB_WR = '0' AND nSRCS = '0' ELSE "ZZZZZZZZZZZZZZZZ"; - FB_AD(31 DOWNTO 16) <= SRD(15 DOWNTO 0) WHEN nFB_OE = '0' AND nSRCS = '0' ELSE "ZZZZZZZZZZZZZZZZ"; + SRD(15 DOWNTO 0) <= fb_ad_in(31 DOWNTO 16) WHEN nFB_WR = '0' AND nSRCS = '0' ELSE (others => 'Z'); + -- fb_ad_out(31 DOWNTO 16) <= SRD(15 DOWNTO 0) WHEN nFB_OE = '0' AND nSRCS = '0' ELSE (others => 'Z'); + fb_ad_out(31 downto 0) <= (others => 'Z'); -- otherwise we get a constant driver error END rtl; diff --git a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd index 2529551..78e8ae2 100644 --- a/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd +++ b/FPGA_Quartus_13.1/FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd @@ -130,7 +130,8 @@ ENTITY falconio_sdcard_ide_cf IS WR_DATA : OUT std_logic; WR_GATE : OUT std_logic; DMA_DRQ : OUT std_logic; - FB_AD : INOUT std_logic_vector(31 DOWNTO 0); + fb_ad_in : in std_logic_vector(31 downto 0); + fb_ad_out : out std_logic_vector(31 downto 0); LP_D : INOUT std_logic_vector(7 DOWNTO 0); SND_A : INOUT std_logic_vector(7 downto 0); ACSI_D : INOUT std_logic_vector(7 DOWNTO 0); @@ -302,11 +303,11 @@ BEGIN nDREQ0 <= '0'; -- input daten halten - p_hold_input_data : PROCESS(MAIN_CLK, nFB_WR, FB_AD(31 DOWNTO 16), FB_ADI(15 DOWNTO 0)) + p_hold_input_data : PROCESS(MAIN_CLK, nFB_WR, fb_ad_in(31 DOWNTO 16), FB_ADI(15 DOWNTO 0)) BEGIN IF rising_edge(MAIN_CLK) THEN IF nFB_WR = '0' THEN - FB_ADI <= FB_AD(31 downto 16); + FB_ADI <= fb_ad_in(31 downto 16); ELSE FB_ADI <= FB_ADI; END IF; @@ -403,9 +404,9 @@ BEGIN wrusedw => RDF_AZ ); FCF_CS <= '1' WHEN nFB_CS2 = '0' AND FB_ADR(26 DOWNTO 0) = x"0020110" AND LONG = '1' ELSE '0'; -- F002'0110 LONG ONLY - FCF_APH <= '1' WHEN FB_ALE = '1' AND FB_AD(31 DOWNTO 0) = x"F0020110" AND LONG = '1' ELSE '0'; -- ADRESSPHASE F0020110 LONG ONLY + FCF_APH <= '1' WHEN FB_ALE = '1' AND fb_ad_in(31 DOWNTO 0) = x"F0020110" AND LONG = '1' ELSE '0'; -- ADRESSPHASE F0020110 LONG ONLY RDF_RDE <= '1' WHEN FCF_APH = '1' AND nFB_WR = '1' ELSE '0'; -- AKTIVIEREN IN ADRESSPHASE - FB_AD <= RDF_DOUT(7 DOWNTO 0) & RDF_DOUT(15 DOWNTO 8) & RDF_DOUT(23 DOWNTO 16) & RDF_DOUT(31 DOWNTO 24) WHEN FCF_CS = '1' and nFB_OE = '0' + fb_ad_out <= RDF_DOUT(7 DOWNTO 0) & RDF_DOUT(15 DOWNTO 8) & RDF_DOUT(23 DOWNTO 16) & RDF_DOUT(31 DOWNTO 24) WHEN FCF_CS = '1' and nFB_OE = '0' ELSE (OTHERS => 'Z'); RDF_DIN <= CD_OUT_FDC WHEN DMA_MODUS(7) = '1' ELSE SCSI_DOUT; @@ -413,7 +414,7 @@ BEGIN WRF: dcfifo1 PORT MAP( aclr => CLR_FIFO, - data => FB_AD(7 DOWNTO 0) & FB_AD(15 DOWNTO 8) & FB_AD(23 DOWNTO 16) & FB_AD(31 DOWNTO 24), + data => fb_ad_in(7 DOWNTO 0) & fb_ad_in(15 DOWNTO 8) & fb_ad_in(23 DOWNTO 16) & fb_ad_in(31 DOWNTO 24), rdclk => FDC_CLK, rdreq => WRF_RDE, wrclk => MAIN_CLK, @@ -423,7 +424,7 @@ BEGIN ); CD_IN_FDC <= WRF_DOUT WHEN DMA_ACTIV = '1' and DMA_MODUS(8) = '1' ELSE FB_ADI(7 DOWNTO 0); -- BEI DMA WRITE <-FIFO SONST <-FB DMA_AZ_CS <= '1' WHEN nFB_CS2 = '0' AND FB_ADR(26 DOWNTO 0) = x"002010C" ELSE '0'; -- F002'010C LONG - FB_AD <= DMA_DRQ_Q & DMA_DRQ_REG & IDE_INT & FDINT & SCSI_INT & RDF_AZ & "0" & DMA_STATUS & "00" & WRF_AZ WHEN DMA_AZ_CS = '1' and nFB_OE = '0' + fb_ad_out <= DMA_DRQ_Q & DMA_DRQ_REG & IDE_INT & FDINT & SCSI_INT & RDF_AZ & "0" & DMA_STATUS & "00" & WRF_AZ WHEN DMA_AZ_CS = '1' and nFB_OE = '0' ELSE (OTHERS => 'Z'); DMA_DRQ_Q <= '1' WHEN DMA_DRQ_REG = "11" and DMA_MODUS(6) = '0' ELSE '0'; @@ -581,9 +582,9 @@ BEGIN CA1 <= '1' WHEN DMA_ACTIV = '1' ELSE DMA_MODUS(1); CA2 <= '1' WHEN DMA_ACTIV = '1' ELSE DMA_MODUS(2); - FB_AD(23 downto 16) <= "0000" & (not DMA_STATUS(1)) & "0" & WDC_BSL(1) & HD_DD when WDC_BSL_CS = '1' and nFB_OE = '0' else (OTHERS => 'Z'); - FB_AD(31 downto 24) <= "00000000" when DMA_DATEN_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ"; - FB_AD(23 DOWNTO 16) <= FDC_OUT WHEN DMA_DATEN_CS = '1' AND DMA_MODUS(4 DOWNTO 3) = "00" AND nFB_OE = '0' ELSE + fb_ad_out(23 downto 16) <= "0000" & (not DMA_STATUS(1)) & "0" & WDC_BSL(1) & HD_DD when WDC_BSL_CS = '1' and nFB_OE = '0' else (OTHERS => 'Z'); + fb_ad_out(31 downto 24) <= "00000000" when DMA_DATEN_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ"; + fb_ad_out(23 DOWNTO 16) <= FDC_OUT WHEN DMA_DATEN_CS = '1' AND DMA_MODUS(4 DOWNTO 3) = "00" AND nFB_OE = '0' ELSE SCSI_DOUT WHEN DMA_DATEN_CS = '1' AND DMA_MODUS(4 DOWNTO 3) = "01" AND nFB_OE = '0' ELSE DMA_BYT_CNT(16 downto 9) when DMA_DATEN_CS = '1' and DMA_MODUS(4) = '1' and nFB_OE = '0' else "ZZZZZZZZ"; --- WDC BSL REGISTER ------------------------------------------------------- @@ -593,7 +594,7 @@ BEGIN WDC_BSL <= "00"; ELSIF rising_edge(MAIN_CLK) AND WDC_BSL_CS = '1' AND nFB_WR = '0' THEN IF FB_B0 = '1' THEN - WDC_BSL(1 DOWNTO 0) <= FB_AD(25 DOWNTO 24); + WDC_BSL(1 DOWNTO 0) <= fb_ad_in(25 DOWNTO 24); ELSE WDC_BSL(1 DOWNTO 0) <= WDC_BSL(1 DOWNTO 0); END IF; @@ -606,12 +607,12 @@ BEGIN DMA_MODUS <= x"0000"; ELSIF rising_edge(MAIN_CLK) AND DMA_MODUS_CS = '1' AND nFB_WR = '0' THEN IF FB_B0 = '1' THEN - DMA_MODUS(15 DOWNTO 8) <= FB_AD(31 DOWNTO 24); + DMA_MODUS(15 DOWNTO 8) <= fb_ad_in(31 DOWNTO 24); ELSE DMA_MODUS(15 DOWNTO 8) <= DMA_MODUS(15 DOWNTO 8); END IF; IF FB_B1 = '1' THEN - DMA_MODUS(7 DOWNTO 0) <= FB_AD(23 DOWNTO 16); + DMA_MODUS(7 DOWNTO 0) <= fb_ad_in(23 DOWNTO 16); ELSE DMA_MODUS(7 DOWNTO 0) <= DMA_MODUS(7 DOWNTO 0); END IF; @@ -626,16 +627,16 @@ BEGIN DMA_BYT_CNT <= x"00000000"; ELSIF rising_edge(MAIN_CLK) AND nFB_WR = '0' AND DMA_DATEN_CS = '1' AND nFB_WR = '0' AND DMA_MODUS(4) = '1' AND FB_B1 = '1' THEN DMA_BYT_CNT(31 downto 17) <= "000000000000000"; - DMA_BYT_CNT(16 DOWNTO 9) <= FB_AD(23 DOWNTO 16); + DMA_BYT_CNT(16 DOWNTO 9) <= fb_ad_in(23 DOWNTO 16); DMA_BYT_CNT(8 downto 0) <= "000000000"; ELSIF rising_edge(MAIN_CLK) AND nFB_WR = '0' AND DMA_BYT_CNT_CS = '1' THEN - DMA_BYT_CNT <= FB_AD; + DMA_BYT_CNT <= fb_ad_in; ELSE DMA_BYT_CNT <= DMA_BYT_CNT; END IF; END PROCESS; -------------------------------------------------------------------- - FB_AD(31 downto 16) <= "0000000000000" & DMA_STATUS when DMA_MODUS_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ"; + fb_ad_out(31 downto 16) <= "0000000000000" & DMA_STATUS when DMA_MODUS_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZ"; DMA_STATUS(0) <= '1'; -- DMA OK DMA_STATUS(1) <= '1' WHEN DMA_BYT_CNT /= 0 AND DMA_BYT_CNT(31) = '0' ELSE '0'; -- WENN byts UND NICHT MINUS DMA_STATUS(2) <= '0' WHEN DMA_DRQ_I = '1' OR SCSI_DRQ = '1' ELSE '0'; @@ -660,7 +661,7 @@ BEGIN IF nRSTO = '0' THEN DMA_TOP <= x"00"; ELSIF rising_edge(MAIN_CLK) AND nFB_WR = '0' AND (DMA_TOP_CS = '1' OR DMA_ADR_CS = '1') THEN - DMA_TOP <= FB_AD(31 DOWNTO 24); + DMA_TOP <= fb_ad_in(31 DOWNTO 24); ELSE DMA_TOP <= DMA_TOP; END IF; @@ -670,7 +671,7 @@ BEGIN IF nRSTO = '0' THEN DMA_HIGH <= x"00"; ELSIF rising_edge(MAIN_CLK) AND nFB_WR = '0' AND (DMA_HIGH_CS = '1' OR DMA_ADR_CS = '1') THEN - DMA_HIGH <= FB_AD(23 DOWNTO 16); + DMA_HIGH <= fb_ad_in(23 DOWNTO 16); ELSE DMA_HIGH <= DMA_HIGH; END IF; @@ -682,9 +683,9 @@ BEGIN DMA_MID <= x"00"; ELSIF rising_edge(MAIN_CLK) AND nFB_WR = '0' THEN IF DMA_MID_CS = '1' THEN - DMA_MID <= FB_AD(23 DOWNTO 16); + DMA_MID <= fb_ad_in(23 DOWNTO 16); ELSIF DMA_ADR_CS = '1' THEN - DMA_MID <= FB_AD(15 DOWNTO 8); + DMA_MID <= fb_ad_in(15 DOWNTO 8); END IF; END IF; END PROCESS; @@ -695,9 +696,9 @@ BEGIN DMA_LOW <= x"00"; ELSIF rising_edge(MAIN_CLK) AND nFB_WR = '0' THEN IF DMA_LOW_CS = '1'THEN - DMA_LOW <= FB_AD(23 DOWNTO 16); + DMA_LOW <= fb_ad_in(23 DOWNTO 16); ELSIF DMA_ADR_CS = '1' THEN - DMA_LOW <= FB_AD(7 DOWNTO 0); + DMA_LOW <= fb_ad_in(7 DOWNTO 0); END IF; END IF; END PROCESS; @@ -707,18 +708,18 @@ BEGIN DMA_MID_CS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 1) = x"7C305" AND FB_B1 = '1' ELSE '0'; -- F860B/2 DMA_LOW_CS <= '1' WHEN nFB_CS1 = '0' AND FB_ADR(19 DOWNTO 1) = x"7C306" AND FB_B1 = '1' ELSE '0'; -- F860D/2 - FB_AD(31 DOWNTO 24) <= DMA_TOP WHEN DMA_TOP_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ"; - FB_AD(23 DOWNTO 16) <= DMA_HIGH WHEN DMA_HIGH_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ"; - FB_AD(23 DOWNTO 16) <= DMA_MID WHEN DMA_MID_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ"; - FB_AD(23 DOWNTO 16) <= DMA_LOW WHEN DMA_LOW_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ"; + fb_ad_out(31 DOWNTO 24) <= DMA_TOP WHEN DMA_TOP_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ"; + fb_ad_out(23 DOWNTO 16) <= DMA_HIGH WHEN DMA_HIGH_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ"; + fb_ad_out(23 DOWNTO 16) <= DMA_MID WHEN DMA_MID_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ"; + fb_ad_out(23 DOWNTO 16) <= DMA_LOW WHEN DMA_LOW_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ"; -- DIRECTZUGRIFF DMA_DIRM_CS <= '1' WHEN nFB_CS2 = '0' AND FB_ADR(26 DOWNTO 0) = x"20100" ELSE '0'; -- F002'0100 WORD DMA_ADR_CS <= '1' WHEN nFB_CS2 = '0' AND FB_ADR(26 DOWNTO 0) = x"20104" ELSE '0'; -- F002'0104 LONG DMA_BYT_CNT_CS <= '1' WHEN nFB_CS2 = '0' AND FB_ADR(26 DOWNTO 0) = x"20108" ELSE '0'; -- F002'0108 LONG - FB_AD <= DMA_TOP & DMA_HIGH & DMA_MID & DMA_LOW when DMA_ADR_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; - FB_AD(31 DOWNTO 16) <= DMA_MODUS WHEN DMA_DIRM_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZ"; - FB_AD <= DMA_BYT_CNT WHEN DMA_BYT_CNT_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; + fb_ad_out <= DMA_TOP & DMA_HIGH & DMA_MID & DMA_LOW when DMA_ADR_CS = '1' and nFB_OE = '0' else "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; + fb_ad_out(31 DOWNTO 16) <= DMA_MODUS WHEN DMA_DIRM_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZ"; + fb_ad_out <= DMA_BYT_CNT WHEN DMA_BYT_CNT_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ"; -- DMA RW TOGGLE ------------------------------------------ PROCESS(MAIN_CLK, nRSTO, DMA_MODUS_CS, DMA_MODUS, DMA_DIR_OLD) @@ -840,8 +841,8 @@ BEGIN ); ACIA_CS_I <= '1' WHEN nFB_CS1 = '0'AND FB_ADR(19 DOWNTO 3) = x"1FF80" ELSE '0'; -- FFC00-FFC07 FFC00/8 KEYB_RxD <= '0' WHEN AMKB_REG(3) = '0' or PIC_AMKB_RX = '0' ELSE '1'; -- TASTATUR DATEN VOM PIC(PS2) OR NORMAL // - FB_AD(31 DOWNTO 24) <= DATA_OUT_ACIA_I WHEN ACIA_CS_I = '1' and FB_ADR(2) = '0' and nFB_OE = '0' ELSE - DATA_OUT_ACIA_II WHEN ACIA_CS_I = '1' and FB_ADR(2) = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ"; + fb_ad_out(31 DOWNTO 24) <= DATA_OUT_ACIA_I WHEN ACIA_CS_I = '1' and FB_ADR(2) = '0' and nFB_OE = '0' ELSE + DATA_OUT_ACIA_II WHEN ACIA_CS_I = '1' and FB_ADR(2) = '1' and nFB_OE = '0' ELSE (others => 'Z'); -- AMKB_TX: SPIKES AUSFILTERN und sychronisieren ------------------------------------------ PROCESS(CLK2M, AMKB_RX, AMKB_REG) @@ -916,7 +917,7 @@ BEGIN DTACKn => DTACK_OUT_MFPn, -- Data and Adresses: RS => FB_ADR(5 DOWNTO 1), - DATA_IN => FB_AD(23 DOWNTO 16), + DATA_IN => fb_ad_in(23 DOWNTO 16), DATA_OUT => DATA_OUT_MFP, -- DATA_EN => DATA_EN_MFP, GPIP_IN(7) => NOT DMA_DRQ_Q, @@ -957,10 +958,10 @@ BEGIN MFP_INTACK <= '1' WHEN nFB_CS2 = '0' AND FB_ADR(26 DOWNTO 0) = x"20000" ELSE '0'; --F002'0000 LDS <= '1' WHEN MFP_CS = '1' OR MFP_INTACK = '1' ELSE '0'; - FB_AD(23 DOWNTO 16) <= DATA_OUT_MFP WHEN MFP_CS = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ"; - FB_AD(31 DOWNTO 10) <= "0000000000000000000000" WHEN MFP_INTACK = '1' and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZZZZZZZ"; - FB_AD(9 DOWNTO 2) <= DATA_OUT_MFP when MFP_INTACK = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ"; - FB_AD(1 DOWNTO 0) <= "00" WHEN MFP_INTACK = '1' AND nFB_OE = '0' ELSE "ZZ"; + fb_ad_out(23 DOWNTO 16) <= DATA_OUT_MFP WHEN MFP_CS = '1' and nFB_OE = '0' ELSE (others => 'Z'); + fb_ad_out(31 DOWNTO 10) <= "0000000000000000000000" WHEN MFP_INTACK = '1' and nFB_OE = '0' ELSE (others => 'Z'); + fb_ad_out(9 DOWNTO 2) <= DATA_OUT_MFP when MFP_INTACK = '1' and nFB_OE = '0' ELSE (others => 'Z'); + fb_ad_out(1 DOWNTO 0) <= "00" WHEN MFP_INTACK = '1' AND nFB_OE = '0' ELSE (others => 'Z'); DINTn <= '0' WHEN IDE_INT = '1' AND ACP_CONF(28) = '1' ELSE '0' WHEN FDINT = '1' ELSE '0' WHEN SCSI_INT = '1' AND ACP_CONF(28) = '1' ELSE '1'; @@ -1000,7 +1001,7 @@ BEGIN SNDCS_I <= '1' WHEN SNDCS = '1' AND FB_ADR (1 DOWNTO 1) = "0" ELSE '0'; SNDIR_I <= '1' WHEN SNDCS = '1' AND nFB_WR = '0' ELSE '0'; - FB_AD(31 DOWNTO 24) <= DA_OUT_X WHEN SNDCS_I = '1' and nFB_OE = '0' ELSE "ZZZZZZZZ"; + fb_ad_out(31 DOWNTO 24) <= DA_OUT_X WHEN SNDCS_I = '1' and nFB_OE = '0' ELSE (others => 'Z'); nnIDE_RES <= SND_A_X(7); LP_DIR_X <= SND_A_X(6); @@ -1012,7 +1013,7 @@ BEGIN DSA_D <= SND_A_X(1); nSDSEL <= SND_A_X(0); SND_A <= SND_A_X; - LP_D <= LP_D_X WHEN LP_DIR_X = '0' ELSE "ZZZZZZZZ"; + LP_D <= LP_D_X WHEN LP_DIR_X = '0' ELSE (others => 'Z'); LP_DIR <= LP_DIR_X; @@ -1027,143 +1028,143 @@ BEGIN IF nRSTO = '0' THEN sndmactl <= x"00"; ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"0" and nFB_WR = '0' and FB_B1 ='1' THEN - sndmactl <= FB_AD(23 DOWNTO 16); + sndmactl <= fb_ad_in(23 DOWNTO 16); ELSE sndmactl <= sndmactl; END IF; END PROCESS; - FB_AD(23 DOWNTO 16) <= sndmactl WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"0" and nFB_OE = '0' ELSE "ZZZZZZZZ"; + fb_ad_out(23 DOWNTO 16) <= sndmactl WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"0" and nFB_OE = '0' ELSE (others => 'Z'); PROCESS(nRSTO, MAIN_CLK, FB_ADR(5 DOWNTO 1), dma_snd_cs) begin IF nRSTO = '0' THEN sndbashi <= x"00"; ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"1" and nFB_WR = '0' and FB_B1 ='1' THEN - sndbashi <= FB_AD(23 DOWNTO 16); + sndbashi <= fb_ad_in(23 DOWNTO 16); ELSE sndbashi <= sndbashi; END IF; END PROCESS; - FB_AD(23 DOWNTO 16) <= sndbashi WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"1" and nFB_OE = '0' ELSE "ZZZZZZZZ"; + fb_ad_out(23 DOWNTO 16) <= sndbashi WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"1" and nFB_OE = '0' ELSE (others => 'Z'); PROCESS(nRSTO,MAIN_CLK,FB_ADR(5 DOWNTO 1), dma_snd_cs) BEGIN IF nRSTO = '0' THEN sndbasmi <= x"00"; ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"2" and nFB_WR = '0' and FB_B1 ='1' THEN - sndbasmi <= FB_AD(23 DOWNTO 16); + sndbasmi <= fb_ad_in(23 DOWNTO 16); ELSE sndbasmi <= sndbasmi; END IF; END PROCESS; - FB_AD(23 DOWNTO 16) <= sndbasmi WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"2" and nFB_OE = '0' ELSE "ZZZZZZZZ"; + fb_ad_out(23 DOWNTO 16) <= sndbasmi WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"2" and nFB_OE = '0' ELSE (others => 'Z'); PROCESS(nRSTO, MAIN_CLK, FB_ADR(5 DOWNTO 1), dma_snd_cs) BEGIN IF nRSTO = '0' THEN sndbaslo <= x"00"; ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"3" and nFB_WR = '0' and FB_B1 ='1' THEN - sndbaslo <= FB_AD(23 DOWNTO 16); + sndbaslo <= fb_ad_in(23 DOWNTO 16); ELSE sndbaslo <= sndbaslo; END IF; END PROCESS; - FB_AD(23 DOWNTO 16) <= sndbaslo WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"3" and nFB_OE = '0' ELSE "ZZZZZZZZ"; + fb_ad_out(23 DOWNTO 16) <= sndbaslo WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"3" and nFB_OE = '0' ELSE (others => 'Z'); PROCESS(nRSTO,MAIN_CLK,FB_ADR(5 DOWNTO 1), dma_snd_cs) BEGIN IF nRSTO = '0' THEN sndadrhi <= x"00"; ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"4" and nFB_WR = '0' and FB_B1 ='1' THEN - sndadrhi <= FB_AD(23 DOWNTO 16); + sndadrhi <= fb_ad_in(23 DOWNTO 16); ELSE sndadrhi <= sndadrhi; END IF; END PROCESS; - FB_AD(23 DOWNTO 16) <= sndadrhi WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"4" and nFB_OE = '0' ELSE "ZZZZZZZZ"; + fb_ad_out(23 DOWNTO 16) <= sndadrhi WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"4" and nFB_OE = '0' ELSE (others => 'Z'); PROCESS(nRSTO, MAIN_CLK, FB_ADR(5 DOWNTO 1), dma_snd_cs) BEGIN IF nRSTO = '0' THEN sndadrmi <= x"00"; ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"5" and nFB_WR = '0' and FB_B1 ='1' THEN - sndadrmi <= FB_AD(23 DOWNTO 16); + sndadrmi <= fb_ad_in(23 DOWNTO 16); ELSE sndadrmi <= sndadrmi; END IF; END PROCESS; - FB_AD(23 DOWNTO 16) <= sndadrmi WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"5" and nFB_OE = '0' else "ZZZZZZZZ"; + fb_ad_out(23 DOWNTO 16) <= sndadrmi WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"5" and nFB_OE = '0' else (others => 'Z'); PROCESS(nRSTO, MAIN_CLK, FB_ADR(5 DOWNTO 1), dma_snd_cs) BEGIN IF nRSTO = '0' THEN sndadrlo <= x"00"; ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"6" and nFB_WR = '0' and FB_B1 ='1' THEN - sndadrlo <= FB_AD(23 DOWNTO 16); + sndadrlo <= fb_ad_in(23 DOWNTO 16); ELSE sndadrlo <= sndadrlo; END IF; END PROCESS; - FB_AD(23 DOWNTO 16) <= sndadrlo WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"6" and nFB_OE = '0' ELSE "ZZZZZZZZ"; + fb_ad_out(23 DOWNTO 16) <= sndadrlo WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"6" and nFB_OE = '0' ELSE (others => 'Z'); PROCESS(nRSTO, MAIN_CLK, FB_ADR(5 DOWNTO 1), dma_snd_cs) BEGIN IF nRSTO = '0' THEN sndendhi <= x"00"; ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"7" and nFB_WR = '0' and FB_B1 ='1' THEN - sndendhi <= FB_AD(23 DOWNTO 16); + sndendhi <= fb_ad_in(23 DOWNTO 16); ELSE sndendhi <= sndendhi; END IF; END PROCESS; - FB_AD(23 DOWNTO 16) <= sndendhi WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"7" and nFB_OE = '0' ELSE "ZZZZZZZZ"; + fb_ad_out(23 DOWNTO 16) <= sndendhi WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"7" and nFB_OE = '0' ELSE (others => 'Z'); PROCESS(nRSTO, MAIN_CLK, FB_ADR(5 DOWNTO 1), dma_snd_cs) BEGIN IF nRSTO = '0' THEN sndendmi <= x"00"; ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"8" and nFB_WR = '0' and FB_B1 ='1' THEN - sndendmi <= FB_AD(23 DOWNTO 16); + sndendmi <= fb_ad_in(23 DOWNTO 16); ELSE sndendmi <= sndendmi; END IF; END PROCESS; - FB_AD(23 DOWNTO 16) <= sndendmi WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"8" and nFB_OE = '0' ELSE "ZZZZZZZZ"; + fb_ad_out(23 DOWNTO 16) <= sndendmi WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"8" and nFB_OE = '0' ELSE (others => 'Z'); PROCESS(nRSTO, MAIN_CLK, FB_ADR(5 DOWNTO 1), dma_snd_cs) BEGIN IF nRSTO = '0' THEN sndendlo <= x"00"; ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"9" and nFB_WR = '0' and FB_B1 ='1' THEN - sndendlo <= FB_AD(23 DOWNTO 16); + sndendlo <= fb_ad_in(23 DOWNTO 16); ELSE sndendlo <= sndendlo; END IF; END PROCESS; - FB_AD(23 DOWNTO 16) <= sndendlo WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"9" and nFB_OE = '0' ELSE "ZZZZZZZZ"; + fb_ad_out(23 DOWNTO 16) <= sndendlo WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"9" and nFB_OE = '0' ELSE (others => 'Z'); PROCESS(nRSTO, MAIN_CLK, FB_ADR(5 DOWNTO 1), dma_snd_cs) BEGIN IF nRSTO = '0' THEN sndmode <= x"00"; ELSIF rising_edge(MAIN_CLK) and dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"10" and nFB_WR = '0' and FB_B1 ='1' THEN - sndmode <= FB_AD(23 DOWNTO 16); + sndmode <= fb_ad_in(23 DOWNTO 16); ELSE sndmode <= sndmode; END IF; END PROCESS; - FB_AD(23 DOWNTO 16) <= sndmode WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"10" and nFB_OE = '0' ELSE "ZZZZZZZZ"; + fb_ad_out(23 DOWNTO 16) <= sndmode WHEN dma_snd_cs = '1' and FB_ADR(5 DOWNTO 1) = x"10" and nFB_OE = '0' ELSE (others => 'Z'); ---------------------------------------------------------------------------- -- Paddle @@ -1171,13 +1172,13 @@ BEGIN paddle_cs <= '1' WHEN nFB_CS1 = '0' and FB_ADR(19 DOWNTO 6) = x"3E48" ELSE '0'; -- F9200-F923F - FB_AD(31 DOWNTO 16) <= x"bfff" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"0" and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZ"; - FB_AD(31 DOWNTO 16) <= x"ffff" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"1" and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZ"; - FB_AD(31 DOWNTO 16) <= x"ffff" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"8" and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZ"; - FB_AD(31 DOWNTO 16) <= x"ffff" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"9" and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZ"; - FB_AD(31 DOWNTO 16) <= x"ffff" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"A" and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZ"; - FB_AD(31 DOWNTO 16) <= x"ffff" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"B" and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZ"; - FB_AD(31 DOWNTO 16) <= x"0000" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"10" and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZ"; - FB_AD(31 DOWNTO 16) <= x"0000" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"11" and nFB_OE = '0' ELSE "ZZZZZZZZZZZZZZZZ"; + fb_ad_out(31 DOWNTO 16) <= x"bfff" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"0" and nFB_OE = '0' ELSE (others => 'Z'); + fb_ad_out(31 DOWNTO 16) <= x"ffff" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"1" and nFB_OE = '0' ELSE (others => 'Z'); + fb_ad_out(31 DOWNTO 16) <= x"ffff" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"8" and nFB_OE = '0' ELSE (others => 'Z'); + fb_ad_out(31 DOWNTO 16) <= x"ffff" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"9" and nFB_OE = '0' ELSE (others => 'Z'); + fb_ad_out(31 DOWNTO 16) <= x"ffff" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"A" and nFB_OE = '0' ELSE (others => 'Z'); + fb_ad_out(31 DOWNTO 16) <= x"ffff" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"B" and nFB_OE = '0' ELSE (others => 'Z'); + fb_ad_out(31 DOWNTO 16) <= x"0000" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"10" and nFB_OE = '0' ELSE (others => 'Z'); + fb_ad_out(31 DOWNTO 16) <= x"0000" WHEN paddle_cs = '1' and FB_ADR(5 DOWNTO 1) = x"11" and nFB_OE = '0' ELSE (others => 'Z'); END rtl; diff --git a/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.vhd b/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.vhd index 52c8703..1fce052 100755 --- a/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.vhd +++ b/FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.vhd @@ -174,7 +174,8 @@ ENTITY interrupt_handler IS INT_HANDLER_TA : BUFFER std_logic; ACP_CONF : BUFFER std_logic_vector(31 DOWNTO 0); TIN0 : BUFFER std_logic; - FB_AD : INOUT std_logic_vector(31 DOWNTO 0) + fb_ad_in : in std_logic_vector(31 downto 0); + fb_ad_out : out std_logic_vector(31 downto 0) ); END interrupt_handler; @@ -5100,7 +5101,7 @@ BEGIN -- $10000/4 INT_CTR_CS <= '1' when nFB_CS2 = '0' and FB_ADR(27 downto 2) = 26x"4000" else '0'; - INT_CTR_d <= FB_AD; + INT_CTR_d <= fb_ad_in; INT_CTR24_ena_ctrl <= INT_CTR_CS and FB_B(0) and (not nFB_WR); INT_CTR16_ena_ctrl <= INT_CTR_CS and FB_B(1) and (not nFB_WR); INT_CTR8_ena_ctrl <= INT_CTR_CS and FB_B(2) and (not nFB_WR); @@ -5115,7 +5116,7 @@ BEGIN -- INT_ENA_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) = -- "00000000000100000000000001"); - INT_ENA_d <= FB_AD; + INT_ENA_d <= fb_ad_in; INT_ENA24_ena_ctrl <= INT_ENA_CS and FB_B(0) and (not nFB_WR); INT_ENA16_ena_ctrl <= INT_ENA_CS and FB_B(1) and (not nFB_WR); INT_ENA8_ena_ctrl <= INT_ENA_CS and FB_B(2) and (not nFB_WR); @@ -5127,13 +5128,13 @@ BEGIN -- $10008/4 int_clear_cs <= '1' when nFB_CS2 = '0' and FB_ADR(27 downto 2) = 26x"4002" else '0'; -- INT_CLEAR_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) = "00000000000100000000000010"); - INT_CLEAR_d(31 DOWNTO 24) <= FB_AD(31 DOWNTO 24) and sizeIt(INT_CLEAR_CS,8) + INT_CLEAR_d(31 DOWNTO 24) <= fb_ad_in(31 DOWNTO 24) and sizeIt(INT_CLEAR_CS,8) and sizeIt(FB_B(0),8) and sizeIt(not nFB_WR,8); - INT_CLEAR_d(23 DOWNTO 16) <= FB_AD(23 DOWNTO 16) and sizeIt(INT_CLEAR_CS,8) + INT_CLEAR_d(23 DOWNTO 16) <= fb_ad_in(23 DOWNTO 16) and sizeIt(INT_CLEAR_CS,8) and sizeIt(FB_B(1),8) and sizeIt(not nFB_WR,8); - INT_CLEAR_d(15 DOWNTO 8) <= FB_AD(15 DOWNTO 8) and sizeIt(INT_CLEAR_CS,8) + INT_CLEAR_d(15 DOWNTO 8) <= fb_ad_in(15 DOWNTO 8) and sizeIt(INT_CLEAR_CS,8) and sizeIt(FB_B(2),8) and sizeIt(not nFB_WR,8); - INT_CLEAR_d(7 DOWNTO 0) <= FB_AD(7 DOWNTO 0) and sizeIt(INT_CLEAR_CS,8) and + INT_CLEAR_d(7 DOWNTO 0) <= fb_ad_in(7 DOWNTO 0) and sizeIt(INT_CLEAR_CS,8) and sizeIt(FB_B(3),8) and sizeIt(not nFB_WR,8); -- INTERRUPT LATCH REGISTER READ ONLY @@ -5341,7 +5342,7 @@ BEGIN -- $4'0000/4 ACP_CONF_CS <= to_std_logic(((not nFB_CS2)='1') and FB_ADR(27 DOWNTO 2) = "00000000010000000000000000"); - ACP_CONF_d <= FB_AD; + ACP_CONF_d <= fb_ad_in; ACP_CONF24_ena_ctrl <= ACP_CONF_CS and FB_B(0) and (not nFB_WR); ACP_CONF16_ena_ctrl <= ACP_CONF_CS and FB_B(1) and (not nFB_WR); ACP_CONF8_ena_ctrl <= ACP_CONF_CS and FB_B(2) and (not nFB_WR); @@ -5352,7 +5353,7 @@ BEGIN -- C1287 0=SEK 2=MIN 4=STD 6=WOCHENTAG 7=TAG 8=MONAT 9=JAHR -- -------------------------------------------------------- RTC_ADR0_clk_ctrl <= MAIN_CLK; - RTC_ADR_d <= FB_AD(21 DOWNTO 16); + RTC_ADR_d <= fb_ad_in(21 DOWNTO 16); -- FFFF8961 UHR_AS <= to_std_logic(((not nFB_CS1)='1') and FB_ADR(19 DOWNTO 1) = "1111100010010110000") and FB_B(1); @@ -5370,210 +5371,210 @@ BEGIN WERTE0_0_clk_ctrl <= MAIN_CLK; (WERTE7_0_d_1, WERTE6_0_d_1, WERTE5_0_d_1, WERTE4_0_d_1, WERTE3_0_d_1, - WERTE2_0_d_1, WERTE1_0_d_1, WERTE0_0_d_1) <= FB_AD(23 DOWNTO 16) and + WERTE2_0_d_1, WERTE1_0_d_1, WERTE0_0_d_1) <= fb_ad_in(23 DOWNTO 16) and sizeIt(to_std_logic(RTC_ADR_q = "000000"),8) and sizeIt(UHR_DS,8) and sizeIt(not nFB_WR,8); (WERTE7_d(1), WERTE6_d(1), WERTE5_d(1), WERTE4_d(1), WERTE3_d(1), - WERTE2_d(1), WERTE1_d(1), WERTE0_d(1)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(1), WERTE1_d(1), WERTE0_d(1)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_2_d_1, WERTE6_2_d_1, WERTE5_2_d_1, WERTE4_2_d_1, WERTE3_2_d_1, - WERTE2_2_d_1, WERTE1_2_d_1, WERTE0_2_d_1) <= FB_AD(23 DOWNTO 16) and + WERTE2_2_d_1, WERTE1_2_d_1, WERTE0_2_d_1) <= fb_ad_in(23 DOWNTO 16) and sizeIt(to_std_logic(RTC_ADR_q = "000010"),8) and sizeIt(UHR_DS,8) and sizeIt(not nFB_WR,8); (WERTE7_d(3), WERTE6_d(3), WERTE5_d(3), WERTE4_d(3), WERTE3_d(3), - WERTE2_d(3), WERTE1_d(3), WERTE0_d(3)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(3), WERTE1_d(3), WERTE0_d(3)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_4_d_1, WERTE6_4_d_1, WERTE5_4_d_1, WERTE4_4_d_1, WERTE3_4_d_1, - WERTE2_4_d_1, WERTE1_4_d_1, WERTE0_4_d_1) <= FB_AD(23 DOWNTO 16) and + WERTE2_4_d_1, WERTE1_4_d_1, WERTE0_4_d_1) <= fb_ad_in(23 DOWNTO 16) and sizeIt(to_std_logic(RTC_ADR_q = "000100"),8) and sizeIt(UHR_DS,8) and sizeIt(not nFB_WR,8); (WERTE7_d(5), WERTE6_d(5), WERTE5_d(5), WERTE4_d(5), WERTE3_d(5), - WERTE2_d(5), WERTE1_d(5), WERTE0_d(5)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(5), WERTE1_d(5), WERTE0_d(5)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_6_d_1, WERTE6_6_d_1, WERTE5_6_d_1, WERTE4_6_d_1, WERTE3_6_d_1, - WERTE2_6_d_1, WERTE1_6_d_1, WERTE0_6_d_1) <= FB_AD(23 DOWNTO 16) and + WERTE2_6_d_1, WERTE1_6_d_1, WERTE0_6_d_1) <= fb_ad_in(23 DOWNTO 16) and sizeIt(to_std_logic(RTC_ADR_q = "000110"),8) and sizeIt(UHR_DS,8) and sizeIt(not nFB_WR,8); (WERTE7_7_d_1, WERTE6_7_d_1, WERTE5_7_d_1, WERTE4_7_d_1, WERTE3_7_d_1, - WERTE2_7_d_1, WERTE1_7_d_1, WERTE0_7_d_1) <= FB_AD(23 DOWNTO 16) and + WERTE2_7_d_1, WERTE1_7_d_1, WERTE0_7_d_1) <= fb_ad_in(23 DOWNTO 16) and sizeIt(to_std_logic(RTC_ADR_q = "000111"),8) and sizeIt(UHR_DS,8) and sizeIt(not nFB_WR,8); (WERTE7_8_d_1, WERTE6_8_d_1, WERTE5_8_d_1, WERTE4_8_d_1, WERTE3_8_d_1, - WERTE2_8_d_1, WERTE1_8_d_1, WERTE0_8_d_1) <= FB_AD(23 DOWNTO 16) and + WERTE2_8_d_1, WERTE1_8_d_1, WERTE0_8_d_1) <= fb_ad_in(23 DOWNTO 16) and sizeIt(to_std_logic(RTC_ADR_q = "001000"),8) and sizeIt(UHR_DS,8) and sizeIt(not nFB_WR,8); (WERTE7_9_d_1, WERTE6_9_d_1, WERTE5_9_d_1, WERTE4_9_d_1, WERTE3_9_d_1, - WERTE2_9_d_1, WERTE1_9_d_1, WERTE0_9_d_1) <= FB_AD(23 DOWNTO 16) and + WERTE2_9_d_1, WERTE1_9_d_1, WERTE0_9_d_1) <= fb_ad_in(23 DOWNTO 16) and sizeIt(to_std_logic(RTC_ADR_q = "001001"),8) and sizeIt(UHR_DS,8) and sizeIt(not nFB_WR,8); (WERTE7_d(10), WERTE6_d(10), WERTE5_d(10), WERTE4_d(10), WERTE3_d(10), - WERTE2_d(10), WERTE1_d(10), WERTE0_d(10)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(10), WERTE1_d(10), WERTE0_d(10)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(11), WERTE6_d(11), WERTE5_d(11), WERTE4_d(11), WERTE3_d(11), - WERTE2_11_d_1, WERTE1_11_d_1, WERTE0_11_d_1) <= FB_AD(23 DOWNTO 16); + WERTE2_11_d_1, WERTE1_11_d_1, WERTE0_11_d_1) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(12), WERTE6_d(12), WERTE5_d(12), WERTE4_d(12), WERTE3_d(12), - WERTE2_d(12), WERTE1_d(12), WERTE0_d(12)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(12), WERTE1_d(12), WERTE0_d(12)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_13_d_1, WERTE6_d(13), WERTE5_d(13), WERTE4_d(13), WERTE3_d(13), - WERTE2_d(13), WERTE1_d(13), WERTE0_13_d_1) <= FB_AD(23 DOWNTO 16); + WERTE2_d(13), WERTE1_d(13), WERTE0_13_d_1) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(14), WERTE6_d(14), WERTE5_d(14), WERTE4_d(14), WERTE3_d(14), - WERTE2_d(14), WERTE1_d(14), WERTE0_d(14)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(14), WERTE1_d(14), WERTE0_d(14)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(15), WERTE6_d(15), WERTE5_d(15), WERTE4_d(15), WERTE3_d(15), - WERTE2_d(15), WERTE1_d(15), WERTE0_d(15)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(15), WERTE1_d(15), WERTE0_d(15)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(16), WERTE6_d(16), WERTE5_d(16), WERTE4_d(16), WERTE3_d(16), - WERTE2_d(16), WERTE1_d(16), WERTE0_d(16)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(16), WERTE1_d(16), WERTE0_d(16)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(17), WERTE6_d(17), WERTE5_d(17), WERTE4_d(17), WERTE3_d(17), - WERTE2_d(17), WERTE1_d(17), WERTE0_d(17)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(17), WERTE1_d(17), WERTE0_d(17)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(18), WERTE6_d(18), WERTE5_d(18), WERTE4_d(18), WERTE3_d(18), - WERTE2_d(18), WERTE1_d(18), WERTE0_d(18)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(18), WERTE1_d(18), WERTE0_d(18)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(19), WERTE6_d(19), WERTE5_d(19), WERTE4_d(19), WERTE3_d(19), - WERTE2_d(19), WERTE1_d(19), WERTE0_d(19)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(19), WERTE1_d(19), WERTE0_d(19)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(20), WERTE6_d(20), WERTE5_d(20), WERTE4_d(20), WERTE3_d(20), - WERTE2_d(20), WERTE1_d(20), WERTE0_d(20)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(20), WERTE1_d(20), WERTE0_d(20)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(21), WERTE6_d(21), WERTE5_d(21), WERTE4_d(21), WERTE3_d(21), - WERTE2_d(21), WERTE1_d(21), WERTE0_d(21)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(21), WERTE1_d(21), WERTE0_d(21)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(22), WERTE6_d(22), WERTE5_d(22), WERTE4_d(22), WERTE3_d(22), - WERTE2_d(22), WERTE1_d(22), WERTE0_d(22)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(22), WERTE1_d(22), WERTE0_d(22)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(23), WERTE6_d(23), WERTE5_d(23), WERTE4_d(23), WERTE3_d(23), - WERTE2_d(23), WERTE1_d(23), WERTE0_d(23)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(23), WERTE1_d(23), WERTE0_d(23)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(24), WERTE6_d(24), WERTE5_d(24), WERTE4_d(24), WERTE3_d(24), - WERTE2_d(24), WERTE1_d(24), WERTE0_d(24)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(24), WERTE1_d(24), WERTE0_d(24)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(25), WERTE6_d(25), WERTE5_d(25), WERTE4_d(25), WERTE3_d(25), - WERTE2_d(25), WERTE1_d(25), WERTE0_d(25)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(25), WERTE1_d(25), WERTE0_d(25)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(26), WERTE6_d(26), WERTE5_d(26), WERTE4_d(26), WERTE3_d(26), - WERTE2_d(26), WERTE1_d(26), WERTE0_d(26)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(26), WERTE1_d(26), WERTE0_d(26)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(27), WERTE6_d(27), WERTE5_d(27), WERTE4_d(27), WERTE3_d(27), - WERTE2_d(27), WERTE1_d(27), WERTE0_d(27)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(27), WERTE1_d(27), WERTE0_d(27)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(28), WERTE6_d(28), WERTE5_d(28), WERTE4_d(28), WERTE3_d(28), - WERTE2_d(28), WERTE1_d(28), WERTE0_d(28)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(28), WERTE1_d(28), WERTE0_d(28)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(29), WERTE6_d(29), WERTE5_d(29), WERTE4_d(29), WERTE3_d(29), - WERTE2_d(29), WERTE1_d(29), WERTE0_d(29)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(29), WERTE1_d(29), WERTE0_d(29)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(30), WERTE6_d(30), WERTE5_d(30), WERTE4_d(30), WERTE3_d(30), - WERTE2_d(30), WERTE1_d(30), WERTE0_d(30)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(30), WERTE1_d(30), WERTE0_d(30)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(31), WERTE6_d(31), WERTE5_d(31), WERTE4_d(31), WERTE3_d(31), - WERTE2_d(31), WERTE1_d(31), WERTE0_d(31)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(31), WERTE1_d(31), WERTE0_d(31)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(32), WERTE6_d(32), WERTE5_d(32), WERTE4_d(32), WERTE3_d(32), - WERTE2_d(32), WERTE1_d(32), WERTE0_d(32)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(32), WERTE1_d(32), WERTE0_d(32)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(33), WERTE6_d(33), WERTE5_d(33), WERTE4_d(33), WERTE3_d(33), - WERTE2_d(33), WERTE1_d(33), WERTE0_d(33)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(33), WERTE1_d(33), WERTE0_d(33)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(34), WERTE6_d(34), WERTE5_d(34), WERTE4_d(34), WERTE3_d(34), - WERTE2_d(34), WERTE1_d(34), WERTE0_d(34)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(34), WERTE1_d(34), WERTE0_d(34)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(35), WERTE6_d(35), WERTE5_d(35), WERTE4_d(35), WERTE3_d(35), - WERTE2_d(35), WERTE1_d(35), WERTE0_d(35)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(35), WERTE1_d(35), WERTE0_d(35)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(36), WERTE6_d(36), WERTE5_d(36), WERTE4_d(36), WERTE3_d(36), - WERTE2_d(36), WERTE1_d(36), WERTE0_d(36)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(36), WERTE1_d(36), WERTE0_d(36)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(37), WERTE6_d(37), WERTE5_d(37), WERTE4_d(37), WERTE3_d(37), - WERTE2_d(37), WERTE1_d(37), WERTE0_d(37)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(37), WERTE1_d(37), WERTE0_d(37)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(38), WERTE6_d(38), WERTE5_d(38), WERTE4_d(38), WERTE3_d(38), - WERTE2_d(38), WERTE1_d(38), WERTE0_d(38)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(38), WERTE1_d(38), WERTE0_d(38)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(39), WERTE6_d(39), WERTE5_d(39), WERTE4_d(39), WERTE3_d(39), - WERTE2_d(39), WERTE1_d(39), WERTE0_d(39)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(39), WERTE1_d(39), WERTE0_d(39)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(40), WERTE6_d(40), WERTE5_d(40), WERTE4_d(40), WERTE3_d(40), - WERTE2_d(40), WERTE1_d(40), WERTE0_d(40)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(40), WERTE1_d(40), WERTE0_d(40)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(41), WERTE6_d(41), WERTE5_d(41), WERTE4_d(41), WERTE3_d(41), - WERTE2_d(41), WERTE1_d(41), WERTE0_d(41)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(41), WERTE1_d(41), WERTE0_d(41)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(42), WERTE6_d(42), WERTE5_d(42), WERTE4_d(42), WERTE3_d(42), - WERTE2_d(42), WERTE1_d(42), WERTE0_d(42)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(42), WERTE1_d(42), WERTE0_d(42)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(43), WERTE6_d(43), WERTE5_d(43), WERTE4_d(43), WERTE3_d(43), - WERTE2_d(43), WERTE1_d(43), WERTE0_d(43)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(43), WERTE1_d(43), WERTE0_d(43)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(44), WERTE6_d(44), WERTE5_d(44), WERTE4_d(44), WERTE3_d(44), - WERTE2_d(44), WERTE1_d(44), WERTE0_d(44)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(44), WERTE1_d(44), WERTE0_d(44)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(45), WERTE6_d(45), WERTE5_d(45), WERTE4_d(45), WERTE3_d(45), - WERTE2_d(45), WERTE1_d(45), WERTE0_d(45)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(45), WERTE1_d(45), WERTE0_d(45)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(46), WERTE6_d(46), WERTE5_d(46), WERTE4_d(46), WERTE3_d(46), - WERTE2_d(46), WERTE1_d(46), WERTE0_d(46)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(46), WERTE1_d(46), WERTE0_d(46)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(47), WERTE6_d(47), WERTE5_d(47), WERTE4_d(47), WERTE3_d(47), - WERTE2_d(47), WERTE1_d(47), WERTE0_d(47)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(47), WERTE1_d(47), WERTE0_d(47)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(48), WERTE6_d(48), WERTE5_d(48), WERTE4_d(48), WERTE3_d(48), - WERTE2_d(48), WERTE1_d(48), WERTE0_d(48)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(48), WERTE1_d(48), WERTE0_d(48)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(49), WERTE6_d(49), WERTE5_d(49), WERTE4_d(49), WERTE3_d(49), - WERTE2_d(49), WERTE1_d(49), WERTE0_d(49)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(49), WERTE1_d(49), WERTE0_d(49)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(50), WERTE6_d(50), WERTE5_d(50), WERTE4_d(50), WERTE3_d(50), - WERTE2_d(50), WERTE1_d(50), WERTE0_d(50)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(50), WERTE1_d(50), WERTE0_d(50)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(51), WERTE6_d(51), WERTE5_d(51), WERTE4_d(51), WERTE3_d(51), - WERTE2_d(51), WERTE1_d(51), WERTE0_d(51)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(51), WERTE1_d(51), WERTE0_d(51)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(52), WERTE6_d(52), WERTE5_d(52), WERTE4_d(52), WERTE3_d(52), - WERTE2_d(52), WERTE1_d(52), WERTE0_d(52)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(52), WERTE1_d(52), WERTE0_d(52)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(53), WERTE6_d(53), WERTE5_d(53), WERTE4_d(53), WERTE3_d(53), - WERTE2_d(53), WERTE1_d(53), WERTE0_d(53)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(53), WERTE1_d(53), WERTE0_d(53)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(54), WERTE6_d(54), WERTE5_d(54), WERTE4_d(54), WERTE3_d(54), - WERTE2_d(54), WERTE1_d(54), WERTE0_d(54)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(54), WERTE1_d(54), WERTE0_d(54)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(55), WERTE6_d(55), WERTE5_d(55), WERTE4_d(55), WERTE3_d(55), - WERTE2_d(55), WERTE1_d(55), WERTE0_d(55)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(55), WERTE1_d(55), WERTE0_d(55)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(56), WERTE6_d(56), WERTE5_d(56), WERTE4_d(56), WERTE3_d(56), - WERTE2_d(56), WERTE1_d(56), WERTE0_d(56)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(56), WERTE1_d(56), WERTE0_d(56)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(57), WERTE6_d(57), WERTE5_d(57), WERTE4_d(57), WERTE3_d(57), - WERTE2_d(57), WERTE1_d(57), WERTE0_d(57)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(57), WERTE1_d(57), WERTE0_d(57)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(58), WERTE6_d(58), WERTE5_d(58), WERTE4_d(58), WERTE3_d(58), - WERTE2_d(58), WERTE1_d(58), WERTE0_d(58)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(58), WERTE1_d(58), WERTE0_d(58)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(59), WERTE6_d(59), WERTE5_d(59), WERTE4_d(59), WERTE3_d(59), - WERTE2_d(59), WERTE1_d(59), WERTE0_d(59)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(59), WERTE1_d(59), WERTE0_d(59)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(60), WERTE6_d(60), WERTE5_d(60), WERTE4_d(60), WERTE3_d(60), - WERTE2_d(60), WERTE1_d(60), WERTE0_d(60)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(60), WERTE1_d(60), WERTE0_d(60)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(61), WERTE6_d(61), WERTE5_d(61), WERTE4_d(61), WERTE3_d(61), - WERTE2_d(61), WERTE1_d(61), WERTE0_d(61)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(61), WERTE1_d(61), WERTE0_d(61)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(62), WERTE6_d(62), WERTE5_d(62), WERTE4_d(62), WERTE3_d(62), - WERTE2_d(62), WERTE1_d(62), WERTE0_d(62)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(62), WERTE1_d(62), WERTE0_d(62)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_d(63), WERTE6_d(63), WERTE5_d(63), WERTE4_d(63), WERTE3_d(63), - WERTE2_d(63), WERTE1_d(63), WERTE0_d(63)) <= FB_AD(23 DOWNTO 16); + WERTE2_d(63), WERTE1_d(63), WERTE0_d(63)) <= fb_ad_in(23 DOWNTO 16); (WERTE7_0_ena_1, WERTE6_0_ena_1, WERTE5_0_ena_1, WERTE4_0_ena_1, WERTE3_0_ena_1, WERTE2_0_ena_1, WERTE1_0_ena_1, WERTE0_0_ena_1) <= @@ -6008,7 +6009,7 @@ BEGIN (sizeIt(ACP_CONF_CS,8) and ACP_CONF_q(31 DOWNTO 24)); u0_enabledt <= (INT_CTR_CS or INT_ENA_CS or INT_LATCH_CS or INT_CLEAR_CS or ACP_CONF_CS) and (not nFB_OE); - FB_AD(31 DOWNTO 24) <= u0_tridata; + fb_ad_out(31 DOWNTO 24) <= u0_tridata; u1_data <= (std_logic_vector'(WERTE7_q(0) & WERTE6_q(0) & WERTE5_q(0) & WERTE4_q(0) & WERTE3_q(0) & WERTE2_q(0) & WERTE1_q(0) & WERTE0_q(0)) and sizeIt(to_std_logic(RTC_ADR_q = "000000"),8) and sizeIt(UHR_DS,8)) @@ -6227,7 +6228,7 @@ BEGIN (sizeIt(ACP_CONF_CS,8) and ACP_CONF_q(23 DOWNTO 16)); u1_enabledt <= (UHR_DS or UHR_AS or INT_CTR_CS or INT_ENA_CS or INT_LATCH_CS or INT_CLEAR_CS or ACP_CONF_CS) and (not nFB_OE); - FB_AD(23 DOWNTO 16) <= u1_tridata; + fb_ad_out(23 DOWNTO 16) <= u1_tridata; u2_data <= (sizeIt(INT_CTR_CS,8) and INT_CTR_q(15 DOWNTO 8)) or (sizeIt(INT_ENA_CS,8) and INT_ENA_q(15 DOWNTO 8)) or (sizeIt(INT_LATCH_CS,8) and INT_LATCH_q(15 DOWNTO 8)) or @@ -6235,7 +6236,7 @@ BEGIN (sizeIt(ACP_CONF_CS,8) and ACP_CONF_q(15 DOWNTO 8)); u2_enabledt <= (INT_CTR_CS or INT_ENA_CS or INT_LATCH_CS or INT_CLEAR_CS or ACP_CONF_CS) and (not nFB_OE); - FB_AD(15 DOWNTO 8) <= u2_tridata; + fb_ad_out(15 DOWNTO 8) <= u2_tridata; u3_data <= (sizeIt(INT_CTR_CS,8) and INT_CTR_q(7 DOWNTO 0)) or (sizeIt(INT_ENA_CS,8) and INT_ENA_q(7 DOWNTO 0)) or (sizeIt(INT_LATCH_CS,8) and INT_LATCH_q(7 DOWNTO 0)) or @@ -6243,7 +6244,7 @@ BEGIN (sizeIt(ACP_CONF_CS,8) and ACP_CONF_q(7 DOWNTO 0)); u3_enabledt <= (INT_CTR_CS or INT_ENA_CS or INT_LATCH_CS or INT_CLEAR_CS or ACP_CONF_CS) and (not nFB_OE); - FB_AD(7 DOWNTO 0) <= u3_tridata; + fb_ad_out(7 DOWNTO 0) <= u3_tridata; INT_HANDLER_TA <= int_ctr_cs or int_ena_cs or int_latch_cs or int_clear_cs; diff --git a/FPGA_Quartus_13.1/Video/BLITTER/BLITTER.vhd b/FPGA_Quartus_13.1/Video/BLITTER/BLITTER.vhd index f42df9b..eedb5e0 100644 --- a/FPGA_Quartus_13.1/Video/BLITTER/BLITTER.vhd +++ b/FPGA_Quartus_13.1/Video/BLITTER/BLITTER.vhd @@ -1,73 +1,47 @@ --- WARNING: Do NOT edit the input and output ports in this file in a text --- editor if you plan to continue editing the block that represents it in --- the Block Editor! File corruption is VERY likely to occur. - --- Copyright (C) 1991-2008 Altera Corporation --- Your use of Altera Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Altera Program License --- Subscription Agreement, Altera MegaCore Function License --- Agreement, or other applicable license agreement, including, --- without limitation, that your use is for the sole purpose of --- programming logic devices manufactured by Altera and sold by --- Altera or its authorized distributors. Please refer to the --- applicable agreement for further details. - - --- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008) --- Created on Fri Oct 16 15:40:59 2009 - library ieee; - use ieee.std_logic_1164.all; - use ieee.numeric_std.all; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; entity blitter is - -- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE! - PORT + port ( - nRSTO : IN std_logic; - MAIN_CLK : IN std_logic; - FB_ALE : IN std_logic; - nFB_WR : IN std_logic; - nFB_OE : IN std_logic; - FB_SIZE0 : IN std_logic; - FB_SIZE1 : IN std_logic; - VIDEO_RAM_CTR : IN std_logic_vector(15 DOWNTO 0); - BLITTER_ON : IN std_logic; - FB_ADR : IN std_logic_vector(31 DOWNTO 0); - nFB_CS1 : IN std_logic; - nFB_CS2 : IN std_logic; - nFB_CS3 : IN std_logic; - DDRCLK0 : IN std_logic; - BLITTER_DIN : IN std_logic_vector(127 DOWNTO 0); - BLITTER_DACK : IN std_logic_vector(4 DOWNTO 0); - SR_BLITTER_DACK : IN std_logic; - BLITTER_RUN : OUT std_logic; - BLITTER_DOUT : OUT std_logic_vector(127 DOWNTO 0); - BLITTER_ADR : OUT std_logic_vector(31 DOWNTO 0); - BLITTER_SIG : OUT std_logic; - BLITTER_WR : OUT std_logic; - blitter_ta : OUT std_logic; - fb_ad_in : in std_logic_vector(31 DOWNTO 0); + nRSTO : in std_logic; + MAIN_CLK : in std_logic; + FB_ALE : in std_logic; + nFB_WR : in std_logic; + nFB_OE : in std_logic; + FB_SIZE0 : in std_logic; + FB_SIZE1 : in std_logic; + VIDEO_RAM_CTR : in std_logic_vector(15 downto 0); + BLITTER_ON : in std_logic; + FB_ADR : in std_logic_vector(31 downto 0); + nFB_CS1 : in std_logic; + nFB_CS2 : in std_logic; + nFB_CS3 : in std_logic; + DDRCLK0 : in std_logic; + BLITTER_DIN : in std_logic_vector(127 downto 0); + BLITTER_DACK : in std_logic_vector(4 downto 0); + SR_BLITTER_DACK : in std_logic; + blitter_run : out std_logic; + blitter_dout : out std_logic_vector(127 downto 0); + blitter_adr : out std_logic_vector(31 downto 0); + blitter_sig : out std_logic; + blitter_wr : out std_logic; + blitter_ta : out std_logic; + fb_ad_in : in std_logic_vector(31 downto 0); fb_ad_out : out std_logic_vector(31 downto 0) ); - -- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE! - -END BLITTER; +end BLITTER; -ARCHITECTURE rtl OF blitter IS +architecture rtl of blitter is - -BEGIN - BLITTER_RUN <= '0'; - BLITTER_DOUT <= x"FEDCBA9876543210F0F0F0F0F0F0F0F0"; - BLITTER_ADR <= x"76543210"; - BLITTER_SIG <= '0'; - BLITTER_WR <= '0'; +begin + blitter_run <= '0'; + blitter_dout <= x"FEDCBA9876543210F0F0F0F0F0F0F0F0"; + blitter_adr <= x"76543210"; + blitter_sig <= '0'; + blitter_wr <= '0'; blitter_ta <= '0'; - -END rtl; + fb_ad_out <= (others => 'Z'); +end rtl; diff --git a/FPGA_Quartus_13.1/Video/DDR_CTR.vhd b/FPGA_Quartus_13.1/Video/DDR_CTR.vhd index 907266f..321e14c 100755 --- a/FPGA_Quartus_13.1/Video/DDR_CTR.vhd +++ b/FPGA_Quartus_13.1/Video/DDR_CTR.vhd @@ -1384,17 +1384,25 @@ begin "00000" & video_act_adr(26 downto 24) when video_cnt_h and not nfb_oe else (others => 'Z'); - u0_data <= (sizeIt(VIDEO_BASE_L,8) and VIDEO_BASE_L_D_q) or - (sizeIt(VIDEO_BASE_M,8) and VIDEO_BASE_M_D_q) or - (sizeIt(VIDEO_BASE_H,8) and VIDEO_BASE_H_D_q) or - (sizeIt(VIDEO_CNT_L,8) and VIDEO_ACT_ADR(7 downto 0)) or - (sizeIt(VIDEO_CNT_M,8) and VIDEO_ACT_ADR(15 downto 8)) or - (sizeIt(VIDEO_CNT_H,8) and VIDEO_ACT_ADR(23 downto 16)); - u0_enabledt <= (VIDEO_BASE_L or VIDEO_BASE_M or VIDEO_BASE_H or VIDEO_CNT_L - or VIDEO_CNT_M or VIDEO_CNT_H) and (not nFB_OE); - fb_ad_out(23 downto 16) <= u0_tridata when u0_enabledt; - - +-- u0_data <= (sizeIt(VIDEO_BASE_L,8) and VIDEO_BASE_L_D_q) or +-- (sizeIt(VIDEO_BASE_M,8) and VIDEO_BASE_M_D_q) or +-- (sizeIt(VIDEO_BASE_H,8) and VIDEO_BASE_H_D_q) or +-- (sizeIt(VIDEO_CNT_L,8) and VIDEO_ACT_ADR(7 downto 0)) or +-- (sizeIt(VIDEO_CNT_M,8) and VIDEO_ACT_ADR(15 downto 8)) or +-- (sizeIt(VIDEO_CNT_H,8) and VIDEO_ACT_ADR(23 downto 16)); +-- u0_enabledt <= (VIDEO_BASE_L or VIDEO_BASE_M or VIDEO_BASE_H or VIDEO_CNT_L +-- or VIDEO_CNT_M or VIDEO_CNT_H) and (not nFB_OE); +-- fb_ad_out(23 downto 16) <= u0_tridata when u0_enabledt else (others => 'Z'); + + fb_ad_out(23 downto 16) <= video_base_l_d_q when video_base_l and not nfb_oe else + video_base_m_d_q when video_base_m and not nfb_oe else + video_base_h_d_q when video_base_h and not nfb_oe else + video_act_adr(7 downto 0) when video_cnt_l and not nfb_oe else + video_act_adr(15 downto 8) when video_cnt_m and not nfb_oe else + video_act_adr(23 downto 16) when video_cnt_h and not nfb_oe else + (others => 'Z'); + fb_ad_out(15 downto 0) <= (others => 'Z'); + -- Assignments added to explicitly combine the -- effects of multiple drivers in the source FIFO_BANK_OK_d <= FIFO_BANK_OK_d_1 or FIFO_BANK_OK_d_2; diff --git a/FPGA_Quartus_13.1/Video/video.vhd b/FPGA_Quartus_13.1/Video/video.vhd index 17e6fcd..0ab7374 100644 --- a/FPGA_Quartus_13.1/Video/video.vhd +++ b/FPGA_Quartus_13.1/Video/video.vhd @@ -1,229 +1,248 @@ --- Copyright (C) 1991-2014 Altera Corporation --- Your use of Altera Corporation's design tools, logic functions --- and other software and tools, and its AMPP partner logic --- functions, and any output files from any of the foregoing --- (including device programming or simulation files), and any --- associated documentation or information are expressly subject --- to the terms and conditions of the Altera Program License --- Subscription Agreement, Altera MegaCore Function License --- Agreement, or other applicable license agreement, including, --- without limitation, that your use is for the sole purpose of --- programming logic devices manufactured by Altera and sold by --- Altera or its authorized distributors. Please refer to the --- applicable agreement for further details. +---------------------------------------------------------------------- +---- ---- +---- This file is part of the 'Firebee' project. ---- +---- http://firebee.org ---- +---- ---- +---- Description: ---- +---- This package contains utility functions, procedures and constants +---- for the Firebee project. +---- +---- Author(s): ---- +---- Fredi Aschwanden +---- Markus Fröschle, mfro@mubf.de +---- ---- +---------------------------------------------------------------------- +---- ---- +---- Copyright (C) 2015 Markus Fröschle & the FireBee project +---- ---- +---- This source file is free software; you can redistribute it ---- +---- and/or modify it under the terms of the GNU General Public ---- +---- License as published by the Free Software Foundation; either ---- +---- version 2 of the License, or (at your option) any later ---- +---- version. ---- +---- ---- +---- This program is distributed in the hope that it will be ---- +---- useful, but WITHOUT ANY WARRANTY; without even the implied ---- +---- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- +---- PURPOSE. See the GNU General Public License for more ---- +---- details. ---- +---- ---- +---- You should have received a copy of the GNU General Public ---- +---- License along with this program; if not, write to the Free ---- +---- Software Foundation, Inc., 51 Franklin Street, Fifth Floor, ---- +---- Boston, MA 02110-1301, USA. ---- +---- ---- +---------------------------------------------------------------------- +-- --- PROGRAM "Quartus II 64-Bit" --- VERSION "Version 13.1.4 Build 182 03/12/2014 SJ Web Edition" --- CREATED "Mon Jan 11 09:20:56 2016" +library ieee; +use ieee.std_logic_1164.all; -LIBRARY ieee; - USE ieee.std_logic_1164.all; +library work; -LIBRARY work; - -ENTITY video IS - PORT +entity video is + port ( - MAIN_CLK : IN std_logic; - nFB_CS1 : IN std_logic; - nFB_CS2 : IN std_logic; - nFB_CS3 : IN std_logic; - nFB_WR : IN std_logic; - FB_SIZE0 : IN std_logic; - FB_SIZE1 : IN std_logic; - nRSTO : IN std_logic; - nFB_OE : IN std_logic; - FB_ALE : IN std_logic; - DDR_SYNC_66M : IN std_logic; - CLK33M : IN std_logic; - CLK25M : IN std_logic; - CLK_VIDEO : IN std_logic; - VR_BUSY : IN std_logic; - DDRCLK : IN std_logic_vector(3 DOWNTO 0); - fb_ad_in : in std_logic_vector(31 DOWNTO 0); + MAIN_CLK : in std_logic; + nFB_CS1 : in std_logic; + nFB_CS2 : in std_logic; + nFB_CS3 : in std_logic; + nFB_WR : in std_logic; + FB_SIZE0 : in std_logic; + FB_SIZE1 : in std_logic; + nRSTO : in std_logic; + nFB_OE : in std_logic; + FB_ALE : in std_logic; + DDR_SYNC_66M : in std_logic; + CLK33M : in std_logic; + CLK25M : in std_logic; + CLK_VIDEO : in std_logic; + VR_BUSY : in std_logic; + ddrclk : in std_logic_vector(3 downto 0); + fb_ad_in : in std_logic_vector(31 downto 0); fb_ad_out : out std_logic_vector(31 downto 0); - FB_ADR : IN std_logic_vector(31 DOWNTO 0); - VD : INOUT std_logic_vector(31 DOWNTO 0); - VDQS : INOUT std_logic_vector(3 DOWNTO 0); - VR_D : IN std_logic_vector(8 DOWNTO 0); - nBLANK : OUT std_logic; - nVWE : OUT std_logic; - nVCAS : OUT std_logic; - nVRAS : OUT std_logic; - nVCS : OUT std_logic; - nPD_VGA : OUT std_logic; - VCKE : OUT std_logic; - VSYNC : OUT std_logic; - HSYNC : OUT std_logic; - nSYNC : OUT std_logic; - VIDEO_TA : OUT std_logic; - PIXEL_CLK : OUT std_logic; - VIDEO_RECONFIG : OUT std_logic; - VR_WR : OUT std_logic; - VR_RD : OUT std_logic; - BA : OUT std_logic_vector(1 DOWNTO 0); - VA : OUT std_logic_vector(12 DOWNTO 0); - VB : OUT std_logic_vector(7 DOWNTO 0); - VDM : OUT std_logic_vector(3 DOWNTO 0); - VG : OUT std_logic_vector(7 DOWNTO 0); - VR : OUT std_logic_vector(7 DOWNTO 0) + FB_ADR : in std_logic_vector(31 downto 0); + VD : inout std_logic_vector(31 downto 0); + vdqs : inout std_logic_vector(3 downto 0); + VR_D : in std_logic_vector(8 downto 0); + nBLANK : out std_logic; + nVWE : out std_logic; + nVCAS : out std_logic; + nVRAS : out std_logic; + nVCS : out std_logic; + nPD_VGA : out std_logic; + VCKE : out std_logic; + VSYNC : out std_logic; + HSYNC : out std_logic; + nSYNC : out std_logic; + VIDEO_TA : out std_logic; + pixel_clk : out std_logic; + VIDEO_RECONFIG : out std_logic; + VR_WR : out std_logic; + VR_RD : out std_logic; + BA : out std_logic_vector(1 downto 0); + VA : out std_logic_vector(12 downto 0); + VB : out std_logic_vector(7 downto 0); + VDM : out std_logic_vector(3 downto 0); + VG : out std_logic_vector(7 downto 0); + VR : out std_logic_vector(7 downto 0) ); -END video; +end video; ARCHITECTURE rtl OF video IS - ATTRIBUTE black_box : BOOLEAN; - ATTRIBUTE noopt : BOOLEAN; - SIGNAL ACP_CLUT_RD : std_logic; - SIGNAL ACP_CLUT_WR : std_logic_vector(3 DOWNTO 0); - SIGNAL BLITTER_ADR : std_logic_vector(31 DOWNTO 0); - SIGNAL BLITTER_DACK : std_logic_vector(4 DOWNTO 0); - SIGNAL BLITTER_DIN : std_logic_vector(127 DOWNTO 0); - SIGNAL BLITTER_DOUT : std_logic_vector(127 DOWNTO 0); - SIGNAL BLITTER_ON : std_logic; - SIGNAL BLITTER_RUN : std_logic; - SIGNAL BLITTER_SIG : std_logic; - SIGNAL BLITTER_TA : std_logic; - SIGNAL BLITTER_WR : std_logic; - SIGNAL BORDER_COLOR : std_logic_vector(23 DOWNTO 0); - SIGNAL CC16 : std_logic_vector(23 DOWNTO 0); - SIGNAL CC24 : std_logic_vector(31 DOWNTO 0); - SIGNAL CCA : std_logic_vector(23 DOWNTO 0); - SIGNAL CCF : std_logic_vector(23 DOWNTO 0); - SIGNAL CCS : std_logic_vector(23 DOWNTO 0); - SIGNAL CCSEL : std_logic_vector(2 DOWNTO 0); - SIGNAL CLR_FIFO : std_logic; - SIGNAL CLUT_ADR : std_logic_vector(7 DOWNTO 0); - SIGNAL CLUT_ADR1A : std_logic; - SIGNAL CLUT_ADR2A : std_logic; - SIGNAL CLUT_ADR3A : std_logic; - SIGNAL CLUT_ADR4A : std_logic; - SIGNAL CLUT_ADR5A : std_logic; - SIGNAL CLUT_ADR6A : std_logic; - SIGNAL CLUT_ADR7A : std_logic; - SIGNAL CLUT_MUX_ADR : std_logic_vector(3 DOWNTO 0); - SIGNAL CLUT_OFF : std_logic_vector(3 DOWNTO 0); - SIGNAL COLOR1 : std_logic; - SIGNAL COLOR2 : std_logic; - SIGNAL COLOR4 : std_logic; - SIGNAL COLOR8 : std_logic; - SIGNAL DDR_FB : std_logic_vector(4 DOWNTO 0); - SIGNAL DDR_WR : std_logic; - SIGNAL DDRWR_D_SEL : std_logic_vector(1 DOWNTO 0); - SIGNAL DOP_FIFO_CLR : std_logic; - SIGNAL FALCON_CLUT_RDH : std_logic; - SIGNAL FALCON_CLUT_RDL : std_logic; - SIGNAL FALCON_CLUT_WR : std_logic_vector(3 DOWNTO 0); - SIGNAL FB_DDR : std_logic_vector(127 DOWNTO 0); - SIGNAL FB_LE : std_logic_vector(3 DOWNTO 0); - SIGNAL FB_VDOE : std_logic_vector(3 DOWNTO 0); - SIGNAL FIFO_D : std_logic_vector(127 DOWNTO 0); - SIGNAL FIFO_MW : std_logic_vector(8 DOWNTO 0); - SIGNAL FIFO_RDE : std_logic; - SIGNAL FIFO_WRE : std_logic; - SIGNAL INTER_ZEI : std_logic; - SIGNAL nFB_BURST : std_logic := '0'; - SIGNAL pixel_clk_i : std_logic; - SIGNAL SR_BLITTER_DACK : std_logic; - SIGNAL SR_DDR_FB : std_logic; - SIGNAL SR_DDR_WR : std_logic; - SIGNAL SR_DDRWR_D_SEL : std_logic; - SIGNAL SR_FIFO_WRE : std_logic; - SIGNAL SR_VDMP : std_logic_vector(7 DOWNTO 0); - SIGNAL ST_CLUT_RD : std_logic; - SIGNAL ST_CLUT_WR : std_logic_vector(1 DOWNTO 0); - SIGNAL VDM_SEL : std_logic_vector(3 DOWNTO 0); - SIGNAL VDMA : std_logic_vector(127 DOWNTO 0); - SIGNAL VDMB : std_logic_vector(127 DOWNTO 0); - SIGNAL VDMC : std_logic_vector(127 DOWNTO 0); - SIGNAL VDMP : std_logic_vector(7 DOWNTO 0); - SIGNAL VDOUT_OE : std_logic; - SIGNAL VDP_IN : std_logic_vector(63 DOWNTO 0); - SIGNAL VDP_OUT : std_logic_vector(63 DOWNTO 0); - SIGNAL VDR : std_logic_vector(31 DOWNTO 0); - SIGNAL VDVZ : std_logic_vector(127 DOWNTO 0); - SIGNAL VIDEO_DDR_TA : std_logic; - SIGNAL VIDEO_MOD_TA : std_logic; - SIGNAL VIDEO_RAM_CTR : std_logic_vector(15 DOWNTO 0); - SIGNAL ZR_C8 : std_logic_vector(7 DOWNTO 0); - SIGNAL ZR_C8B : std_logic_vector(7 DOWNTO 0); - SIGNAL SYNTHESIZED_WIRE_0 : std_logic; - SIGNAL SYNTHESIZED_WIRE_1 : std_logic; - SIGNAL SYNTHESIZED_WIRE_2 : std_logic; - SIGNAL SYNTHESIZED_WIRE_3 : std_logic; - SIGNAL SYNTHESIZED_WIRE_4 : std_logic; - SIGNAL SYNTHESIZED_WIRE_5 : std_logic; - SIGNAL SYNTHESIZED_WIRE_60 : std_logic; - SIGNAL SYNTHESIZED_WIRE_7 : std_logic_vector(15 DOWNTO 0); - SIGNAL DFF_inst93 : std_logic; - SIGNAL SYNTHESIZED_WIRE_8 : std_logic; - SIGNAL SYNTHESIZED_WIRE_9 : std_logic; - SIGNAL SYNTHESIZED_WIRE_61 : std_logic; - SIGNAL SYNTHESIZED_WIRE_11 : std_logic_vector(31 DOWNTO 0); - SIGNAL SYNTHESIZED_WIRE_12 : std_logic_vector(7 DOWNTO 0); - SIGNAL SYNTHESIZED_WIRE_13 : std_logic_vector(31 DOWNTO 0); - SIGNAL SYNTHESIZED_WIRE_14 : std_logic_vector(31 DOWNTO 0); - SIGNAL SYNTHESIZED_WIRE_15 : std_logic_vector(31 DOWNTO 0); - SIGNAL SYNTHESIZED_WIRE_16 : std_logic; - SIGNAL SYNTHESIZED_WIRE_18 : std_logic; - SIGNAL SYNTHESIZED_WIRE_19 : std_logic; - SIGNAL SYNTHESIZED_WIRE_20 : std_logic; - SIGNAL SYNTHESIZED_WIRE_21 : std_logic; - SIGNAL SYNTHESIZED_WIRE_22 : std_logic; - SIGNAL SYNTHESIZED_WIRE_23 : std_logic; - SIGNAL SYNTHESIZED_WIRE_24 : std_logic; - SIGNAL SYNTHESIZED_WIRE_25 : std_logic_vector(23 DOWNTO 0); - SIGNAL SYNTHESIZED_WIRE_26 : std_logic_vector(23 DOWNTO 0); - SIGNAL SYNTHESIZED_WIRE_62 : std_logic_vector(23 DOWNTO 0); - SIGNAL SYNTHESIZED_WIRE_29 : std_logic_vector(2 DOWNTO 0); - SIGNAL SYNTHESIZED_WIRE_30 : std_logic_vector(7 DOWNTO 0); - SIGNAL SYNTHESIZED_WIRE_31 : std_logic_vector(2 DOWNTO 0); - SIGNAL SYNTHESIZED_WIRE_32 : std_logic_vector(7 DOWNTO 0); - SIGNAL SYNTHESIZED_WIRE_33 : std_logic_vector(7 DOWNTO 0); - SIGNAL SYNTHESIZED_WIRE_34 : std_logic_vector(2 DOWNTO 0); - SIGNAL SYNTHESIZED_WIRE_63 : std_logic_vector(127 DOWNTO 0); - SIGNAL SYNTHESIZED_WIRE_36 : std_logic_vector(127 DOWNTO 0); - SIGNAL SYNTHESIZED_WIRE_38 : std_logic; - SIGNAL SYNTHESIZED_WIRE_40 : std_logic; - SIGNAL SYNTHESIZED_WIRE_41 : std_logic_vector(5 DOWNTO 0); - SIGNAL SYNTHESIZED_WIRE_42 : std_logic_vector(23 DOWNTO 0); - SIGNAL SYNTHESIZED_WIRE_43 : std_logic_vector(23 DOWNTO 0); - SIGNAL SYNTHESIZED_WIRE_44 : std_logic_vector(5 DOWNTO 0); - SIGNAL SYNTHESIZED_WIRE_45 : std_logic_vector(5 DOWNTO 0); - SIGNAL SYNTHESIZED_WIRE_46 : std_logic; - SIGNAL SYNTHESIZED_WIRE_47 : std_logic_vector(6 DOWNTO 0); - SIGNAL SYNTHESIZED_WIRE_48 : std_logic_vector(31 DOWNTO 0); - SIGNAL DFF_inst91 : std_logic; - SIGNAL SYNTHESIZED_WIRE_64 : std_logic; - SIGNAL SYNTHESIZED_WIRE_49 : std_logic; - SIGNAL SYNTHESIZED_WIRE_50 : std_logic; - SIGNAL SYNTHESIZED_WIRE_51 : std_logic; - SIGNAL SYNTHESIZED_WIRE_52 : std_logic; - SIGNAL SYNTHESIZED_WIRE_53 : std_logic; - SIGNAL SYNTHESIZED_WIRE_54 : std_logic; - SIGNAL SYNTHESIZED_WIRE_65 : std_logic_vector(23 DOWNTO 0); + attribute black_box : BOOLEAN; + attribute noopt : BOOLEAN; + signal ACP_CLUT_RD : std_logic; + signal ACP_CLUT_WR : std_logic_vector(3 downto 0); + signal BLITTER_ADR : std_logic_vector(31 downto 0); + signal blitter_dack : std_logic_vector(4 downto 0); + signal blitter_din : std_logic_vector(127 downto 0); + signal BLITTER_DOUT : std_logic_vector(127 downto 0); + signal BLITTER_ON : std_logic; + signal BLITTER_RUN : std_logic; + signal BLITTER_SIG : std_logic; + signal BLITTER_TA : std_logic; + signal BLITTER_WR : std_logic; + signal BORDER_COLOR : std_logic_vector(23 downto 0); + signal CC16 : std_logic_vector(23 downto 0); + signal CC24 : std_logic_vector(31 downto 0); + signal CCA : std_logic_vector(23 downto 0); + signal ccf : std_logic_vector(23 downto 0); + signal CCS : std_logic_vector(23 downto 0); + signal CCSEL : std_logic_vector(2 downto 0); + signal CLR_FIFO : std_logic; + signal clut_adr : std_logic_vector(7 downto 0); + signal CLUT_ADR1A : std_logic; + signal CLUT_ADR2A : std_logic; + signal CLUT_ADR3A : std_logic; + signal CLUT_ADR4A : std_logic; + signal CLUT_ADR5A : std_logic; + signal CLUT_ADR6A : std_logic; + signal CLUT_ADR7A : std_logic; + signal CLUT_MUX_ADR : std_logic_vector(3 downto 0); + signal CLUT_OFF : std_logic_vector(3 downto 0); + signal color1 : std_logic; + signal color2 : std_logic; + signal color4 : std_logic; + signal color8 : std_logic; + signal DDR_FB : std_logic_vector(4 downto 0); + signal ddr_wr : std_logic; + signal ddrwr_d_sel : std_logic_vector(1 downto 0); + signal DOP_FIFO_CLR : std_logic; + signal FALCON_CLUT_RDH : std_logic; + signal FALCON_CLUT_RDL : std_logic; + signal FALCON_CLUT_WR : std_logic_vector(3 downto 0); + signal FB_DDR : std_logic_vector(127 downto 0); + signal FB_LE : std_logic_vector(3 downto 0); + signal FB_VDOE : std_logic_vector(3 downto 0); + signal FIFO_D : std_logic_vector(127 downto 0); + signal FIFO_MW : std_logic_vector(8 downto 0); + signal FIFO_RDE : std_logic; + signal FIFO_WRE : std_logic; + signal INTER_ZEI : std_logic; + signal nFB_BURST : std_logic := '0'; + signal pixel_clk_i : std_logic; + signal SR_BLITTER_DACK : std_logic; + signal SR_DDR_FB : std_logic; + signal sr_ddr_wr : std_logic; + signal SR_DDRWR_D_SEL : std_logic; + signal SR_FIFO_WRE : std_logic; + signal SR_VDMP : std_logic_vector(7 downto 0); + signal ST_CLUT_RD : std_logic; + signal ST_CLUT_WR : std_logic_vector(1 downto 0); + signal VDM_SEL : std_logic_vector(3 downto 0); + signal VDMA : std_logic_vector(127 downto 0); + signal VDMB : std_logic_vector(127 downto 0); + signal VDMC : std_logic_vector(127 downto 0); + signal VDMP : std_logic_vector(7 downto 0); + signal vdout_oe : std_logic; + signal VDP_IN : std_logic_vector(63 downto 0); + signal VDP_OUT : std_logic_vector(63 downto 0); + signal VDR : std_logic_vector(31 downto 0); + signal vdvz : std_logic_vector(127 downto 0); + signal VIDEO_DDR_TA : std_logic; + signal VIDEO_MOD_TA : std_logic; + signal VIDEO_RAM_CTR : std_logic_vector(15 downto 0); + signal ZR_C8 : std_logic_vector(7 downto 0); + signal ZR_C8B : std_logic_vector(7 downto 0); + signal SYNTHESIZED_WIRE_0 : std_logic; + signal SYNTHESIZED_WIRE_1 : std_logic; + signal SYNTHESIZED_WIRE_2 : std_logic; + signal SYNTHESIZED_WIRE_3 : std_logic; + signal SYNTHESIZED_WIRE_4 : std_logic; + signal SYNTHESIZED_WIRE_5 : std_logic; + signal SYNTHESIZED_WIRE_60 : std_logic; + signal SYNTHESIZED_WIRE_7 : std_logic_vector(15 downto 0); + signal DFF_inst93 : std_logic; + signal SYNTHESIZED_WIRE_8 : std_logic; + signal SYNTHESIZED_WIRE_9 : std_logic; + signal SYNTHESIZED_WIRE_61 : std_logic; + signal SYNTHESIZED_WIRE_11 : std_logic_vector(31 downto 0); + signal SYNTHESIZED_WIRE_12 : std_logic_vector(7 downto 0); + signal SYNTHESIZED_WIRE_13 : std_logic_vector(31 downto 0); + signal SYNTHESIZED_WIRE_14 : std_logic_vector(31 downto 0); + signal SYNTHESIZED_WIRE_15 : std_logic_vector(31 downto 0); + signal SYNTHESIZED_WIRE_16 : std_logic; + signal SYNTHESIZED_WIRE_18 : std_logic; + signal SYNTHESIZED_WIRE_19 : std_logic; + signal SYNTHESIZED_WIRE_20 : std_logic; + signal SYNTHESIZED_WIRE_21 : std_logic; + signal SYNTHESIZED_WIRE_22 : std_logic; + signal SYNTHESIZED_WIRE_23 : std_logic; + signal SYNTHESIZED_WIRE_24 : std_logic; + signal SYNTHESIZED_WIRE_25 : std_logic_vector(23 downto 0); + signal SYNTHESIZED_WIRE_26 : std_logic_vector(23 downto 0); + signal SYNTHESIZED_WIRE_62 : std_logic_vector(23 downto 0); + signal SYNTHESIZED_WIRE_29 : std_logic_vector(2 downto 0); + signal SYNTHESIZED_WIRE_30 : std_logic_vector(7 downto 0); + signal SYNTHESIZED_WIRE_31 : std_logic_vector(2 downto 0); + signal SYNTHESIZED_WIRE_32 : std_logic_vector(7 downto 0); + signal SYNTHESIZED_WIRE_33 : std_logic_vector(7 downto 0); + signal SYNTHESIZED_WIRE_34 : std_logic_vector(2 downto 0); + signal SYNTHESIZED_WIRE_63 : std_logic_vector(127 downto 0); + signal SYNTHESIZED_WIRE_36 : std_logic_vector(127 downto 0); + signal SYNTHESIZED_WIRE_38 : std_logic; + signal SYNTHESIZED_WIRE_40 : std_logic; + signal SYNTHESIZED_WIRE_41 : std_logic_vector(5 downto 0); + signal SYNTHESIZED_WIRE_42 : std_logic_vector(23 downto 0); + signal SYNTHESIZED_WIRE_43 : std_logic_vector(23 downto 0); + signal SYNTHESIZED_WIRE_44 : std_logic_vector(5 downto 0); + signal SYNTHESIZED_WIRE_45 : std_logic_vector(5 downto 0); + signal SYNTHESIZED_WIRE_46 : std_logic; + signal SYNTHESIZED_WIRE_47 : std_logic_vector(6 downto 0); + signal SYNTHESIZED_WIRE_48 : std_logic_vector(31 downto 0); + signal DFF_inst91 : std_logic; + signal SYNTHESIZED_WIRE_64 : std_logic; + signal SYNTHESIZED_WIRE_49 : std_logic; + signal SYNTHESIZED_WIRE_50 : std_logic; + signal SYNTHESIZED_WIRE_51 : std_logic; + signal SYNTHESIZED_WIRE_52 : std_logic; + signal SYNTHESIZED_WIRE_53 : std_logic; + signal SYNTHESIZED_WIRE_54 : std_logic; + signal SYNTHESIZED_WIRE_65 : std_logic_vector(23 downto 0); - SIGNAL GDFX_TEMP_SIGNAL_16 : std_logic_vector(7 DOWNTO 0); - SIGNAL GDFX_TEMP_SIGNAL_0 : std_logic_vector(15 DOWNTO 0); - SIGNAL GDFX_TEMP_SIGNAL_6 : std_logic_vector(127 DOWNTO 0); - SIGNAL GDFX_TEMP_SIGNAL_5 : std_logic_vector(127 DOWNTO 0); - SIGNAL GDFX_TEMP_SIGNAL_4 : std_logic_vector(127 DOWNTO 0); - SIGNAL GDFX_TEMP_SIGNAL_3 : std_logic_vector(127 DOWNTO 0); - SIGNAL GDFX_TEMP_SIGNAL_2 : std_logic_vector(127 DOWNTO 0); - SIGNAL GDFX_TEMP_SIGNAL_1 : std_logic_vector(127 DOWNTO 0); - SIGNAL GDFX_TEMP_SIGNAL_15 : std_logic_vector(127 DOWNTO 0); - SIGNAL GDFX_TEMP_SIGNAL_14 : std_logic_vector(127 DOWNTO 0); - SIGNAL GDFX_TEMP_SIGNAL_13 : std_logic_vector(127 DOWNTO 0); - SIGNAL GDFX_TEMP_SIGNAL_12 : std_logic_vector(127 DOWNTO 0); - SIGNAL GDFX_TEMP_SIGNAL_11 : std_logic_vector(127 DOWNTO 0); - SIGNAL GDFX_TEMP_SIGNAL_10 : std_logic_vector(127 DOWNTO 0); - SIGNAL GDFX_TEMP_SIGNAL_9 : std_logic_vector(127 DOWNTO 0); - SIGNAL GDFX_TEMP_SIGNAL_8 : std_logic_vector(127 DOWNTO 0); - SIGNAL GDFX_TEMP_SIGNAL_7 : std_logic_vector(127 DOWNTO 0); + signal GDFX_TEMP_SIGNAL_16 : std_logic_vector(7 downto 0); + signal GDFX_TEMP_SIGNAL_0 : std_logic_vector(15 downto 0); + signal GDFX_TEMP_SIGNAL_6 : std_logic_vector(127 downto 0); + signal GDFX_TEMP_SIGNAL_5 : std_logic_vector(127 downto 0); + signal GDFX_TEMP_SIGNAL_4 : std_logic_vector(127 downto 0); + signal GDFX_TEMP_SIGNAL_3 : std_logic_vector(127 downto 0); + signal GDFX_TEMP_SIGNAL_2 : std_logic_vector(127 downto 0); + signal GDFX_TEMP_SIGNAL_1 : std_logic_vector(127 downto 0); + signal GDFX_TEMP_SIGNAL_15 : std_logic_vector(127 downto 0); + signal GDFX_TEMP_SIGNAL_14 : std_logic_vector(127 downto 0); + signal GDFX_TEMP_SIGNAL_13 : std_logic_vector(127 downto 0); + signal GDFX_TEMP_SIGNAL_12 : std_logic_vector(127 downto 0); + signal GDFX_TEMP_SIGNAL_11 : std_logic_vector(127 downto 0); + signal GDFX_TEMP_SIGNAL_10 : std_logic_vector(127 downto 0); + signal GDFX_TEMP_SIGNAL_9 : std_logic_vector(127 downto 0); + signal GDFX_TEMP_SIGNAL_8 : std_logic_vector(127 downto 0); + signal GDFX_TEMP_SIGNAL_7 : std_logic_vector(127 downto 0); -BEGIN - VB(7 DOWNTO 0) <= SYNTHESIZED_WIRE_65(7 DOWNTO 0); - VG(7 DOWNTO 0) <= SYNTHESIZED_WIRE_65(15 DOWNTO 8); - VR(7 DOWNTO 0) <= SYNTHESIZED_WIRE_65(23 DOWNTO 16); +begin + VB(7 downto 0) <= SYNTHESIZED_WIRE_65(7 downto 0); + VG(7 downto 0) <= SYNTHESIZED_WIRE_65(15 downto 8); + VR(7 downto 0) <= SYNTHESIZED_WIRE_65(23 downto 16); SYNTHESIZED_WIRE_0 <= '0'; SYNTHESIZED_WIRE_1 <= '0'; @@ -264,21 +283,21 @@ BEGIN CC16(0) <= GDFX_TEMP_SIGNAL_16(0); - GDFX_TEMP_SIGNAL_15 <= (VDMB(55 DOWNTO 0) & VDMA(127 DOWNTO 56)); - GDFX_TEMP_SIGNAL_14 <= (VDMB(63 DOWNTO 0) & VDMA(127 DOWNTO 64)); - GDFX_TEMP_SIGNAL_13 <= (VDMB(71 DOWNTO 0) & VDMA(127 DOWNTO 72)); - GDFX_TEMP_SIGNAL_12 <= (VDMB(79 DOWNTO 0) & VDMA(127 DOWNTO 80)); - GDFX_TEMP_SIGNAL_11 <= (VDMB(87 DOWNTO 0) & VDMA(127 DOWNTO 88)); - GDFX_TEMP_SIGNAL_10 <= (VDMB(95 DOWNTO 0) & VDMA(127 DOWNTO 96)); - GDFX_TEMP_SIGNAL_9 <= (VDMB(103 DOWNTO 0) & VDMA(127 DOWNTO 104)); - GDFX_TEMP_SIGNAL_8 <= (VDMB(111 DOWNTO 0) & VDMA(127 DOWNTO 112)); - GDFX_TEMP_SIGNAL_7 <= (VDMB(119 DOWNTO 0) & VDMA(127 DOWNTO 120)); - GDFX_TEMP_SIGNAL_6 <= (VDMB(7 DOWNTO 0) & VDMA(127 DOWNTO 8)); - GDFX_TEMP_SIGNAL_5 <= (VDMB(15 DOWNTO 0) & VDMA(127 DOWNTO 16)); - GDFX_TEMP_SIGNAL_4 <= (VDMB(23 DOWNTO 0) & VDMA(127 DOWNTO 24)); - GDFX_TEMP_SIGNAL_3 <= (VDMB(31 DOWNTO 0) & VDMA(127 DOWNTO 32)); - GDFX_TEMP_SIGNAL_2 <= (VDMB(39 DOWNTO 0) & VDMA(127 DOWNTO 40)); - GDFX_TEMP_SIGNAL_1 <= (VDMB(47 DOWNTO 0) & VDMA(127 DOWNTO 48)); + GDFX_TEMP_SIGNAL_15 <= (VDMB(55 downto 0) & VDMA(127 downto 56)); + GDFX_TEMP_SIGNAL_14 <= (VDMB(63 downto 0) & VDMA(127 downto 64)); + GDFX_TEMP_SIGNAL_13 <= (VDMB(71 downto 0) & VDMA(127 downto 72)); + GDFX_TEMP_SIGNAL_12 <= (VDMB(79 downto 0) & VDMA(127 downto 80)); + GDFX_TEMP_SIGNAL_11 <= (VDMB(87 downto 0) & VDMA(127 downto 88)); + GDFX_TEMP_SIGNAL_10 <= (VDMB(95 downto 0) & VDMA(127 downto 96)); + GDFX_TEMP_SIGNAL_9 <= (VDMB(103 downto 0) & VDMA(127 downto 104)); + GDFX_TEMP_SIGNAL_8 <= (VDMB(111 downto 0) & VDMA(127 downto 112)); + GDFX_TEMP_SIGNAL_7 <= (VDMB(119 downto 0) & VDMA(127 downto 120)); + GDFX_TEMP_SIGNAL_6 <= (VDMB(7 downto 0) & VDMA(127 downto 8)); + GDFX_TEMP_SIGNAL_5 <= (VDMB(15 downto 0) & VDMA(127 downto 16)); + GDFX_TEMP_SIGNAL_4 <= (VDMB(23 downto 0) & VDMA(127 downto 24)); + GDFX_TEMP_SIGNAL_3 <= (VDMB(31 downto 0) & VDMA(127 downto 32)); + GDFX_TEMP_SIGNAL_2 <= (VDMB(39 downto 0) & VDMA(127 downto 40)); + GDFX_TEMP_SIGNAL_1 <= (VDMB(47 downto 0) & VDMA(127 downto 48)); acp_clut_ram : entity work.altdpram2 @@ -288,12 +307,12 @@ BEGIN wren_b => SYNTHESIZED_WIRE_0, clock_a => MAIN_CLK, clock_b => pixel_clk_i, - address_a => FB_ADR(9 DOWNTO 2), + address_a => FB_ADR(9 downto 2), address_b => ZR_C8B, - data_a => fb_ad_in(7 DOWNTO 0), - data_b => (OTHERS => '0'), + data_a => fb_ad_in(7 downto 0), + data_b => (others => '0'), q_a => SYNTHESIZED_WIRE_30, - q_b => CCA(7 DOWNTO 0) + q_b => CCA(7 downto 0) ); @@ -304,12 +323,12 @@ BEGIN wren_b => SYNTHESIZED_WIRE_1, clock_a => MAIN_CLK, clock_b => pixel_clk_i, - address_a => FB_ADR(9 DOWNTO 2), + address_a => FB_ADR(9 downto 2), address_b => ZR_C8B, - data_a => fb_ad_in(15 DOWNTO 8), - data_b => (OTHERS => '0'), + data_a => fb_ad_in(15 downto 8), + data_b => (others => '0'), q_a => SYNTHESIZED_WIRE_32, - q_b => CCA(15 DOWNTO 8) + q_b => CCA(15 downto 8) ); @@ -320,15 +339,14 @@ BEGIN wren_b => SYNTHESIZED_WIRE_2, clock_a => MAIN_CLK, clock_b => pixel_clk_i, - address_a => FB_ADR(9 DOWNTO 2), + address_a => FB_ADR(9 downto 2), address_b => ZR_C8B, - data_a => fb_ad_in(23 DOWNTO 16), - data_b => (OTHERS => '0'), + data_a => fb_ad_in(23 downto 16), + data_b => (others => '0'), q_a => SYNTHESIZED_WIRE_33, - q_b => CCA(23 DOWNTO 16) + q_b => CCA(23 downto 16) ); - i_blitter : entity work.blitter port map ( @@ -343,10 +361,10 @@ BEGIN nFB_CS1 => nFB_CS1, nFB_CS2 => nFB_CS2, nFB_CS3 => nFB_CS3, - DDRCLK0 => DDRCLK(0), + DDRCLK0 => ddrclk(0), SR_BLITTER_DACK => SR_BLITTER_DACK, - BLITTER_DACK => BLITTER_DACK, - BLITTER_DIN => BLITTER_DIN, + blitter_dack => blitter_dack, + blitter_din => blitter_din, fb_ad_in => fb_ad_in, fb_ad_out => fb_ad_out, FB_ADR => FB_ADR, @@ -357,9 +375,8 @@ BEGIN blitter_ta => blitter_ta, BLITTER_ADR => BLITTER_ADR, BLITTER_DOUT => BLITTER_DOUT - ); - - + ); + i_ddr_ctr : entity work.ddr_ctr port map ( @@ -376,7 +393,7 @@ BEGIN DDR_SYNC_66M => DDR_SYNC_66M, BLITTER_SIG => BLITTER_SIG, BLITTER_WR => BLITTER_WR, - DDRCLK0 => DDRCLK(0), + DDRCLK0 => ddrclk(0), CLK33M => CLK33M, CLR_FIFO => CLR_FIFO, BLITTER_ADR => BLITTER_ADR, @@ -392,19 +409,19 @@ BEGIN nVCAS => nVCAS, SR_FIFO_WRE => SR_FIFO_WRE, SR_DDR_FB => SR_DDR_FB, - SR_DDR_WR => SR_DDR_WR, + sr_ddr_wr => sr_ddr_wr, SR_DDRWR_D_SEL => SR_DDRWR_D_SEL, VIDEO_DDR_TA => VIDEO_DDR_TA, SR_BLITTER_DACK => SR_BLITTER_DACK, - DDRWR_D_SEL1 => DDRWR_D_SEL(1), + DDRWR_D_SEL1 => ddrwr_d_sel(1), BA => BA, FB_LE => FB_LE, FB_VDOE => FB_VDOE, SR_VDMP => SR_VDMP, VA => VA, VDM_SEL => VDM_SEL - ); - + ); + falcon_clut_blue : entity work.altdpram1 port map @@ -413,12 +430,12 @@ BEGIN wren_b => SYNTHESIZED_WIRE_3, clock_a => MAIN_CLK, clock_b => pixel_clk_i, - address_a => FB_ADR(9 DOWNTO 2), - address_b => CLUT_ADR, - data_a => fb_ad_in(23 DOWNTO 18), - data_b => (OTHERS => '0'), + address_a => FB_ADR(9 downto 2), + address_b => clut_adr, + data_a => fb_ad_in(23 downto 18), + data_b => (others => '0'), q_a => SYNTHESIZED_WIRE_45, - q_b => CCF(7 DOWNTO 2) + q_b => ccf(7 downto 2) ); @@ -429,12 +446,12 @@ BEGIN wren_b => SYNTHESIZED_WIRE_4, clock_a => MAIN_CLK, clock_b => pixel_clk_i, - address_a => FB_ADR(9 DOWNTO 2), - address_b => CLUT_ADR, - data_a => fb_ad_in(23 DOWNTO 18), - data_b => (OTHERS => '0'), + address_a => FB_ADR(9 downto 2), + address_b => clut_adr, + data_a => fb_ad_in(23 downto 18), + data_b => (others => '0'), q_a => SYNTHESIZED_WIRE_44, - q_b => CCF(15 DOWNTO 10) + q_b => ccf(15 downto 10) ); @@ -445,12 +462,12 @@ BEGIN wren_b => SYNTHESIZED_WIRE_5, clock_a => MAIN_CLK, clock_b => pixel_clk_i, - address_a => FB_ADR(9 DOWNTO 2), - address_b => CLUT_ADR, - data_a => fb_ad_in(31 DOWNTO 26), - data_b => (OTHERS => '0'), + address_a => FB_ADR(9 downto 2), + address_b => clut_adr, + data_a => fb_ad_in(31 downto 26), + data_b => (others => '0'), q_a => SYNTHESIZED_WIRE_41, - q_b => CCF(23 DOWNTO 18) + q_b => ccf(23 downto 18) ); @@ -458,7 +475,7 @@ BEGIN port map ( wrreq => FIFO_WRE, - wrclk => DDRCLK(0), + wrclk => ddrclk(0), rdreq => SYNTHESIZED_WIRE_60, rdclk => pixel_clk_i, aclr => CLR_FIFO, @@ -471,15 +488,15 @@ BEGIN inst1 : entity work.altddio_bidir0 port map ( - oe => VDOUT_OE, - inclock => DDRCLK(1), - outclock => DDRCLK(3), - datain_h => VDP_OUT(63 DOWNTO 32), - datain_l => VDP_OUT(31 DOWNTO 0), + oe => vdout_oe, + inclock => ddrclk(1), + outclock => ddrclk(3), + datain_h => VDP_OUT(63 downto 32), + datain_l => VDP_OUT(31 downto 0), padio => VD, combout => SYNTHESIZED_WIRE_15, - dataout_h => VDP_IN(31 DOWNTO 0), - dataout_l => VDP_IN(63 DOWNTO 32) + dataout_h => VDP_IN(31 downto 0), + dataout_l => VDP_IN(63 downto 32) ); @@ -521,18 +538,18 @@ BEGIN ( data1 => DFF_inst93, data0 => ZR_C8(0), - sel => COLOR1, + sel => color1, result => ZR_C8B(0) ); - CLUT_ADR(2) <= CLUT_ADR2A AND SYNTHESIZED_WIRE_61; - CLUT_ADR(4) <= CLUT_OFF(0) OR SYNTHESIZED_WIRE_8; - CLUT_ADR(6) <= CLUT_OFF(2) OR SYNTHESIZED_WIRE_9; + clut_adr(2) <= CLUT_ADR2A AND SYNTHESIZED_WIRE_61; + clut_adr(4) <= CLUT_OFF(0) OR SYNTHESIZED_WIRE_8; + clut_adr(6) <= CLUT_OFF(2) OR SYNTHESIZED_WIRE_9; - SYNTHESIZED_WIRE_61 <= COLOR8 OR COLOR4; - SYNTHESIZED_WIRE_16 <= COLOR4 OR COLOR8 OR COLOR2; + SYNTHESIZED_WIRE_61 <= color8 OR color4; + SYNTHESIZED_WIRE_16 <= color4 OR color8 OR color2; fb_ad_out <= vdr when fb_vdoe(0) else (others => 'Z'); @@ -554,9 +571,9 @@ BEGIN inst12 : entity work.lpm_ff1 port map ( - clock => DDRCLK(0), - data => VDP_IN(31 DOWNTO 0), - q => VDVZ(31 DOWNTO 0) + clock => ddrclk(0), + data => VDP_IN(31 downto 0), + q => vdvz(31 downto 0) ); @@ -566,7 +583,7 @@ BEGIN clock => DDR_SYNC_66M, enable => FB_LE(0), data => fb_ad_in, - q => FB_DDR(127 DOWNTO 96) + q => FB_DDR(127 downto 96) ); @@ -576,7 +593,7 @@ BEGIN clock => DDR_SYNC_66M, enable => FB_LE(1), data => fb_ad_in, - q => FB_DDR(95 DOWNTO 64) + q => FB_DDR(95 downto 64) ); @@ -586,7 +603,7 @@ BEGIN clock => DDR_SYNC_66M, enable => FB_LE(2), data => fb_ad_in, - q => FB_DDR(63 DOWNTO 32) + q => FB_DDR(63 downto 32) ); @@ -596,16 +613,16 @@ BEGIN clock => DDR_SYNC_66M, enable => FB_LE(3), data => fb_ad_in, - q => FB_DDR(31 DOWNTO 0) + q => FB_DDR(31 downto 0) ); inst17 : entity work.lpm_ff0 port map ( - clock => DDRCLK(0), + clock => ddrclk(0), enable => DDR_FB(1), - data => VDP_IN(31 DOWNTO 0), + data => VDP_IN(31 downto 0), q => SYNTHESIZED_WIRE_11 ); @@ -613,9 +630,9 @@ BEGIN inst18 : entity work.lpm_ff0 port map ( - clock => DDRCLK(0), + clock => ddrclk(0), enable => DDR_FB(0), - data => VDP_IN(63 DOWNTO 32), + data => VDP_IN(63 downto 32), q => SYNTHESIZED_WIRE_13 ); @@ -623,9 +640,9 @@ BEGIN inst19 : entity work.lpm_ff0 port map ( - clock => DDRCLK(0), + clock => ddrclk(0), enable => DDR_FB(0), - data => VDP_IN(31 DOWNTO 0), + data => VDP_IN(31 downto 0), q => SYNTHESIZED_WIRE_14 ); @@ -633,9 +650,9 @@ BEGIN inst2 : entity work.altddio_out0 port map ( - outclock => DDRCLK(3), - datain_h => VDMP(7 DOWNTO 4), - datain_l => VDMP(3 DOWNTO 0), + outclock => ddrclk(3), + datain_h => VDMP(7 downto 4), + datain_l => VDMP(3 downto 0), dataout => VDM ); @@ -643,9 +660,9 @@ BEGIN inst20 : entity work.lpm_ff1 port map ( - clock => DDRCLK(0), - data => VDVZ(31 DOWNTO 0), - q => VDVZ(95 DOWNTO 64) + clock => ddrclk(0), + data => vdvz(31 downto 0), + q => vdvz(95 downto 64) ); @@ -653,11 +670,11 @@ BEGIN port map ( clock => pixel_clk_i, - data0x => FIFO_D(127 DOWNTO 96), - data1x => FIFO_D(95 DOWNTO 64), - data2x => FIFO_D(63 DOWNTO 32), - data3x => FIFO_D(31 DOWNTO 0), - sel => CLUT_MUX_ADR(1 DOWNTO 0), + data0x => FIFO_D(127 downto 96), + data1x => FIFO_D(95 downto 64), + data2x => FIFO_D(63 downto 32), + data3x => FIFO_D(31 downto 0), + sel => CLUT_MUX_ADR(1 downto 0), result => SYNTHESIZED_WIRE_48 ); @@ -665,11 +682,11 @@ BEGIN inst22 : entity work.lpm_mux5 port map ( - data0x => FB_DDR(127 DOWNTO 64), - data1x => FB_DDR(63 DOWNTO 0), - data2x => BLITTER_DOUT(127 DOWNTO 64), - data3x => BLITTER_DOUT(63 DOWNTO 0), - sel => DDRWR_D_SEL, + data0x => FB_DDR(127 downto 64), + data1x => FB_DDR(63 downto 0), + data2x => BLITTER_DOUT(127 downto 64), + data3x => BLITTER_DOUT(63 downto 0), + sel => ddrwr_d_sel, result => VDP_OUT ); @@ -685,15 +702,15 @@ BEGIN port map ( clock => pixel_clk_i, - data0x => FIFO_D(127 DOWNTO 112), - data1x => FIFO_D(111 DOWNTO 96), - data2x => FIFO_D(95 DOWNTO 80), - data3x => FIFO_D(79 DOWNTO 64), - data4x => FIFO_D(63 DOWNTO 48), - data5x => FIFO_D(47 DOWNTO 32), - data6x => FIFO_D(31 DOWNTO 16), - data7x => FIFO_D(15 DOWNTO 0), - sel => CLUT_MUX_ADR(2 DOWNTO 0), + data0x => FIFO_D(127 downto 112), + data1x => FIFO_D(111 downto 96), + data2x => FIFO_D(95 downto 80), + data3x => FIFO_D(79 downto 64), + data4x => FIFO_D(63 downto 48), + data5x => FIFO_D(47 downto 32), + data6x => FIFO_D(31 downto 16), + data7x => FIFO_D(15 downto 0), + sel => CLUT_MUX_ADR(2 downto 0), result => SYNTHESIZED_WIRE_7 ); @@ -702,22 +719,22 @@ BEGIN port map ( clock => pixel_clk_i, - data0x => FIFO_D(127 DOWNTO 120), - data10x => FIFO_D(47 DOWNTO 40), - data11x => FIFO_D(39 DOWNTO 32), - data12x => FIFO_D(31 DOWNTO 24), - data13x => FIFO_D(23 DOWNTO 16), - data14x => FIFO_D(15 DOWNTO 8), - data15x => FIFO_D(7 DOWNTO 0), - data1x => FIFO_D(119 DOWNTO 112), - data2x => FIFO_D(111 DOWNTO 104), - data3x => FIFO_D(103 DOWNTO 96), - data4x => FIFO_D(95 DOWNTO 88), - data5x => FIFO_D(87 DOWNTO 80), - data6x => FIFO_D(79 DOWNTO 72), - data7x => FIFO_D(71 DOWNTO 64), - data8x => FIFO_D(63 DOWNTO 56), - data9x => FIFO_D(55 DOWNTO 48), + data0x => FIFO_D(127 downto 120), + data10x => FIFO_D(47 downto 40), + data11x => FIFO_D(39 downto 32), + data12x => FIFO_D(31 downto 24), + data13x => FIFO_D(23 downto 16), + data14x => FIFO_D(15 downto 8), + data15x => FIFO_D(7 downto 0), + data1x => FIFO_D(119 downto 112), + data2x => FIFO_D(111 downto 104), + data3x => FIFO_D(103 downto 96), + data4x => FIFO_D(95 downto 88), + data5x => FIFO_D(87 downto 80), + data6x => FIFO_D(79 downto 72), + data7x => FIFO_D(71 downto 64), + data8x => FIFO_D(63 downto 56), + data9x => FIFO_D(55 downto 48), sel => CLUT_MUX_ADR, result => SYNTHESIZED_WIRE_12 ); @@ -726,7 +743,7 @@ BEGIN inst26 : entity work.lpm_shiftreg4 port map ( - clock => DDRCLK(0), + clock => ddrclk(0), shiftin => SR_FIFO_WRE, shiftout => FIFO_WRE ); @@ -740,50 +757,50 @@ BEGIN q => VDR ); - CLUT_ADR(1) <= CLUT_ADR1A AND SYNTHESIZED_WIRE_16; + clut_adr(1) <= CLUT_ADR1A AND SYNTHESIZED_WIRE_16; inst3 : entity work.lpm_ff1 port map ( - clock => DDRCLK(0), - data => VDP_IN(63 DOWNTO 32), - q => VDVZ(63 DOWNTO 32) + clock => ddrclk(0), + data => VDP_IN(63 downto 32), + q => vdvz(63 downto 32) ); - CLUT_ADR(3) <= SYNTHESIZED_WIRE_61 AND CLUT_ADR3A; - CLUT_ADR(5) <= CLUT_OFF(1) OR SYNTHESIZED_WIRE_18; - SYNTHESIZED_WIRE_8 <= CLUT_ADR4A AND COLOR8; - SYNTHESIZED_WIRE_18 <= CLUT_ADR5A AND COLOR8; - SYNTHESIZED_WIRE_9 <= CLUT_ADR6A AND COLOR8; - SYNTHESIZED_WIRE_46 <= CLUT_ADR7A AND COLOR8; + clut_adr(3) <= SYNTHESIZED_WIRE_61 AND CLUT_ADR3A; + clut_adr(5) <= CLUT_OFF(1) OR SYNTHESIZED_WIRE_18; + SYNTHESIZED_WIRE_8 <= CLUT_ADR4A AND color8; + SYNTHESIZED_WIRE_18 <= CLUT_ADR5A AND color8; + SYNTHESIZED_WIRE_9 <= CLUT_ADR6A AND color8; + SYNTHESIZED_WIRE_46 <= CLUT_ADR7A AND color8; inst36 : entity work.lpm_ff6 port map ( - clock => DDRCLK(0), - enable => BLITTER_DACK(0), - data => VDVZ, - q => BLITTER_DIN + clock => ddrclk(0), + enable => blitter_dack(0), + data => vdvz, + q => blitter_din ); - VDOUT_OE <= DDR_WR OR SR_DDR_WR; - video_ta <= blitter_ta /* or video_mod_ta */ or video_ddr_ta; + vdout_oe <= ddr_wr OR sr_ddr_wr; + video_ta <= blitter_ta or video_mod_ta or video_ddr_ta; inst4 : entity work.lpm_ff1 port map ( - clock => DDRCLK(0), - data => VDVZ(63 DOWNTO 32), - q => VDVZ(127 DOWNTO 96) + clock => ddrclk(0), + data => vdvz(63 downto 32), + q => vdvz(127 downto 96) ); inst40 : entity work.mux41_0 port map ( - S0 => COLOR2, - S1 => COLOR4, + S0 => color2, + S1 => color4, D0 => CLUT_ADR6A, INH => SYNTHESIZED_WIRE_19, D1 => CLUT_ADR7A, @@ -794,8 +811,8 @@ BEGIN inst41 : entity work.mux41_1 port map ( - S0 => COLOR2, - S1 => COLOR4, + S0 => color2, + S1 => color4, D0 => CLUT_ADR5A, INH => SYNTHESIZED_WIRE_20, D1 => CLUT_ADR6A, @@ -806,9 +823,9 @@ BEGIN inst42 : entity work.mux41_2 port map ( - S0 => COLOR2, + S0 => color2, D2 => CLUT_ADR7A, - S1 => COLOR4, + S1 => color4, D0 => CLUT_ADR4A, INH => SYNTHESIZED_WIRE_21, D1 => CLUT_ADR5A, @@ -819,9 +836,9 @@ BEGIN inst43 : entity work.mux41_3 port map ( - S0 => COLOR2, + S0 => color2, D2 => CLUT_ADR6A, - S1 => COLOR4, + S1 => color4, D0 => CLUT_ADR3A, INH => SYNTHESIZED_WIRE_22, D1 => CLUT_ADR4A, @@ -832,9 +849,9 @@ BEGIN inst44 : entity work.mux41_4 port map ( - S0 => COLOR2, + S0 => color2, D2 => CLUT_ADR5A, - S1 => COLOR4, + S1 => color4, D0 => CLUT_ADR2A, INH => SYNTHESIZED_WIRE_23, D1 => CLUT_ADR3A, @@ -845,9 +862,9 @@ BEGIN inst45 : entity work.mux41_5 port map ( - S0 => COLOR2, + S0 => color2, D2 => CLUT_ADR4A, - S1 => COLOR4, + S1 => color4, D0 => CLUT_ADR1A, INH => SYNTHESIZED_WIRE_24, D1 => CLUT_ADR2A, @@ -868,7 +885,7 @@ BEGIN port map ( clock => pixel_clk_i, - data => CCF, + data => ccf, q => SYNTHESIZED_WIRE_25 ); @@ -909,7 +926,7 @@ BEGIN inst54 : entity work.lpm_constant0 port map ( - result => CCS(20 DOWNTO 16) + result => CCS(20 downto 16) ); @@ -922,7 +939,7 @@ BEGIN inst59 : entity work.lpm_constant0 port map ( - result => CCS(12 DOWNTO 8) + result => CCS(12 downto 8) ); fb_ad_out(18 downto 16) <= synthesized_wire_34 when st_clut_rd else (others => 'Z'); @@ -955,15 +972,14 @@ BEGIN inst64 : entity work.lpm_constant0 port map ( - result => CCS(4 DOWNTO 0) + result => CCS(4 downto 0) ); SYNTHESIZED_WIRE_60 <= FIFO_RDE AND SYNTHESIZED_WIRE_40; fb_ad_out(31 downto 26) <= synthesized_wire_41 when falcon_clut_rdh else (others => 'Z'); - -- the following line results in a syntax error. No idea what's wrong with it: - -- fb_ad_out(23 downto 18) <= synthesized_wire_44 when falcon_clut_rdh else (others <= 'Z'); + fb_ad_out(23 downto 18) <= synthesized_wire_44 when falcon_clut_rdh else (others => 'Z'); SYNTHESIZED_WIRE_38 <= FIFO_RDE AND INTER_ZEI; SYNTHESIZED_WIRE_40 <= NOT(INTER_ZEI); @@ -974,11 +990,11 @@ BEGIN clock => pixel_clk_i, data0x => SYNTHESIZED_WIRE_42, data1x => SYNTHESIZED_WIRE_43, - data2x => (OTHERS => '0'), - data3x => (OTHERS => '0'), + data2x => (others => '0'), + data3x => (others => '0'), data4x => CCA, data5x => CC16, - data6x => CC24(23 DOWNTO 0), + data6x => CC24(23 downto 0), data7x => BORDER_COLOR, sel => CCSEL, result => SYNTHESIZED_WIRE_62 @@ -988,9 +1004,9 @@ BEGIN inst71 : entity work.lpm_ff6 port map ( - clock => DDRCLK(0), + clock => ddrclk(0), enable => FIFO_WRE, - data => VDVZ, + data => vdvz, q => VDMA ); @@ -1001,29 +1017,29 @@ BEGIN inst77 : entity work.lpm_constant1 port map ( - result => CCF(1 DOWNTO 0) + result => ccf(1 downto 0) ); - CLUT_ADR(7) <= CLUT_OFF(3) OR SYNTHESIZED_WIRE_46; + clut_adr(7) <= CLUT_OFF(3) OR SYNTHESIZED_WIRE_46; inst80 : entity work.lpm_constant1 port map ( - result => CCF(9 DOWNTO 8) + result => ccf(9 downto 8) ); inst81 : entity work.lpm_mux4 port map ( - sel => COLOR1, - data0x => ZR_C8(7 DOWNTO 1), + sel => color1, + data0x => ZR_C8(7 downto 1), data1x => SYNTHESIZED_WIRE_47, - result => ZR_C8B(7 DOWNTO 1) + result => ZR_C8B(7 downto 1) ); @@ -1037,35 +1053,35 @@ BEGIN inst83 : entity work.lpm_constant1 port map ( - result => CCF(17 DOWNTO 16) + result => ccf(17 downto 16) ); - PROCESS(DDRCLK(0), DDR_WR) - BEGIN - IF (DDR_WR = '1') THEN - VDQS <= (OTHERS => DDRCLK(0)); + process(ddrclk(0), ddr_wr) + begin + if (ddr_wr = '1') then + vdqs <= (others => ddrclk(0)); ELSE - VDQS <= (OTHERS => 'Z'); - END IF; - END PROCESS; + vdqs <= (others => 'Z'); + end if; + end process; - PROCESS(DDRCLK(3)) - BEGIN - IF (rising_edge(DDRCLK(3))) THEN - DDRWR_D_SEL(0) <= SR_DDRWR_D_SEL; - DDR_WR <= SR_DDR_WR; - END IF; - END PROCESS; + process(ddrclk(3)) + begin + if (rising_edge(ddrclk(3))) then + ddrwr_d_sel(0) <= SR_DDRWR_D_SEL; + ddr_wr <= sr_ddr_wr; + end if; + end process; inst89 : entity work.lpm_shiftreg6 port map ( - clock => DDRCLK(0), + clock => ddrclk(0), shiftin => SR_BLITTER_DACK, - q => BLITTER_DACK + q => blitter_dack ); @@ -1078,54 +1094,54 @@ BEGIN ); - PROCESS(pixel_clk_i) - BEGIN - IF (rising_edge(pixel_clk_i)) THEN - DFF_inst91 <= CLUT_ADR(0); - END IF; - END PROCESS; + process(pixel_clk_i) + begin + if (rising_edge(pixel_clk_i)) then + DFF_inst91 <= clut_adr(0); + end if; + end process; inst92 : entity work.lpm_shiftreg6 port map ( - clock => DDRCLK(0), + clock => ddrclk(0), shiftin => SR_DDR_FB, q => DDR_FB ); - PROCESS(pixel_clk_i) - BEGIN - IF (rising_edge(pixel_clk_i)) THEN + process(pixel_clk_i) + begin + if (rising_edge(pixel_clk_i)) then DFF_inst93 <= DFF_inst91; - END IF; - END PROCESS; + end if; + end process; inst94 : entity work.lpm_ff6 port map ( - clock => DDRCLK(0), + clock => ddrclk(0), enable => FIFO_WRE, data => VDMA, q => VDMB ); - PROCESS(pixel_clk_i) - BEGIN - IF (rising_edge(pixel_clk_i)) THEN + process(pixel_clk_i) + begin + if (rising_edge(pixel_clk_i)) then SYNTHESIZED_WIRE_64 <= FIFO_RDE; - END IF; - END PROCESS; + end if; + end process; inst97 : entity work.lpm_ff5 port map ( - clock => DDRCLK(2), + clock => ddrclk(2), data => SR_VDMP, q => VDMP ); @@ -1137,8 +1153,8 @@ BEGIN load => SYNTHESIZED_WIRE_64, clock => pixel_clk_i, shiftin => SYNTHESIZED_WIRE_49, - data => FIFO_D(127 DOWNTO 112), - shiftout => CLUT_ADR(0) + data => FIFO_D(127 downto 112), + shiftout => clut_adr(0) ); @@ -1148,7 +1164,7 @@ BEGIN load => SYNTHESIZED_WIRE_64, clock => pixel_clk_i, shiftin => SYNTHESIZED_WIRE_50, - data => FIFO_D(111 DOWNTO 96), + data => FIFO_D(111 downto 96), shiftout => CLUT_ADR1A ); @@ -1159,7 +1175,7 @@ BEGIN load => SYNTHESIZED_WIRE_64, clock => pixel_clk_i, shiftin => SYNTHESIZED_WIRE_51, - data => FIFO_D(95 DOWNTO 80), + data => FIFO_D(95 downto 80), shiftout => CLUT_ADR2A ); @@ -1170,7 +1186,7 @@ BEGIN load => SYNTHESIZED_WIRE_64, clock => pixel_clk_i, shiftin => SYNTHESIZED_WIRE_52, - data => FIFO_D(79 DOWNTO 64), + data => FIFO_D(79 downto 64), shiftout => CLUT_ADR3A ); @@ -1181,7 +1197,7 @@ BEGIN load => SYNTHESIZED_WIRE_64, clock => pixel_clk_i, shiftin => SYNTHESIZED_WIRE_53, - data => FIFO_D(63 DOWNTO 48), + data => FIFO_D(63 downto 48), shiftout => CLUT_ADR4A ); @@ -1192,7 +1208,7 @@ BEGIN load => SYNTHESIZED_WIRE_64, clock => pixel_clk_i, shiftin => SYNTHESIZED_WIRE_54, - data => FIFO_D(47 DOWNTO 32), + data => FIFO_D(47 downto 32), shiftout => CLUT_ADR5A ); @@ -1203,7 +1219,7 @@ BEGIN load => SYNTHESIZED_WIRE_64, clock => pixel_clk_i, shiftin => CLUT_ADR7A, - data => FIFO_D(31 DOWNTO 16), + data => FIFO_D(31 downto 16), shiftout => CLUT_ADR6A ); @@ -1213,8 +1229,8 @@ BEGIN ( load => SYNTHESIZED_WIRE_64, clock => pixel_clk_i, - shiftin => CLUT_ADR(0), - data => FIFO_D(15 DOWNTO 0), + shiftin => clut_adr(0), + data => FIFO_D(15 downto 0), shiftout => CLUT_ADR7A ); @@ -1226,12 +1242,12 @@ BEGIN wren_b => '0', clock_a => MAIN_CLK, clock_b => pixel_clk_i, - address_a => FB_ADR(4 DOWNTO 1), - address_b => CLUT_ADR(3 DOWNTO 0), - data_a => fb_ad_in(18 DOWNTO 16), - data_b => (OTHERS => '0'), + address_a => FB_ADR(4 downto 1), + address_b => clut_adr(3 downto 0), + data_a => fb_ad_in(18 downto 16), + data_b => (others => '0'), q_a => SYNTHESIZED_WIRE_34, - q_b => CCS(7 DOWNTO 5) + q_b => CCS(7 downto 5) ); @@ -1242,12 +1258,12 @@ BEGIN wren_b => '0', clock_a => MAIN_CLK, clock_b => pixel_clk_i, - address_a => FB_ADR(4 DOWNTO 1), - address_b => CLUT_ADR(3 DOWNTO 0), - data_a => fb_ad_in(22 DOWNTO 20), - data_b => (OTHERS => '0'), + address_a => FB_ADR(4 downto 1), + address_b => clut_adr(3 downto 0), + data_a => fb_ad_in(22 downto 20), + data_b => (others => '0'), q_a => SYNTHESIZED_WIRE_31, - q_b => CCS(15 DOWNTO 13) + q_b => CCS(15 downto 13) ); @@ -1258,12 +1274,12 @@ BEGIN wren_b => '0', clock_a => MAIN_CLK, clock_b => pixel_clk_i, - address_a => FB_ADR(4 DOWNTO 1), - address_b => CLUT_ADR(3 DOWNTO 0), - data_a => fb_ad_in(26 DOWNTO 24), - data_b => (OTHERS => '0'), + address_a => FB_ADR(4 downto 1), + address_b => clut_adr(3 downto 0), + data_a => fb_ad_in(26 downto 24), + data_b => (others => '0'), q_a => SYNTHESIZED_WIRE_29, - q_b => CCS(23 DOWNTO 21) + q_b => CCS(23 downto 21) ); @@ -1289,9 +1305,9 @@ BEGIN fb_ad_out => fb_ad_out, FB_ADR => FB_ADR, VR_D => VR_D, - COLOR8 => COLOR8, + color8 => color8, ACP_CLUT_RD => ACP_CLUT_RD, - COLOR1 => COLOR1, + color1 => color1, FALCON_CLUT_RDH => FALCON_CLUT_RDH, FALCON_CLUT_RDL => FALCON_CLUT_RDL, ST_CLUT_RD => ST_CLUT_RD, @@ -1301,9 +1317,9 @@ BEGIN nSYNC => nSYNC, nPD_VGA => nPD_VGA, FIFO_RDE => FIFO_RDE, - COLOR2 => COLOR2, - COLOR4 => COLOR4, - PIXEL_CLK => pixel_clk_i, + color2 => color2, + color4 => color4, + pixel_clk => pixel_clk_i, BLITTER_ON => BLITTER_ON, VIDEO_MOD_TA => VIDEO_MOD_TA, INTER_ZEI => INTER_ZEI, @@ -1322,5 +1338,5 @@ BEGIN VIDEO_RAM_CTR => VIDEO_RAM_CTR ); - PIXEL_CLK <= pixel_clk_i; -END rtl; \ No newline at end of file + pixel_clk <= pixel_clk_i; +end rtl; \ No newline at end of file diff --git a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd index a44b48e..7eac92f 100755 --- a/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd +++ b/FPGA_Quartus_13.1/Video/video_mod_mux_clutctr.vhd @@ -1131,7 +1131,7 @@ begin -- 10 VGA -- 11 TV -- $8006/2 - sys_ctr_cs <= '1' when nFB_CS1 = '0' and f_addr_cmp_w(fb_adR, 20x"f8006") = '1'; + sys_ctr_cs <= '1' when nFB_CS1 = '0' and f_addr_cmp_w(fb_adR, 20x"f8006") = '1' else '0'; -- fb_adR(19 downto 1) = std_logic_vector'(20x"f8006")(19 downto 1) else '0'; -- sys_ctr_CS <= to_std_logic(((not nFB_CS1) = '1') and fb_adR(19 downto 1) = "1111100000000000011"); @@ -1284,32 +1284,32 @@ begin -- (sizeIt(VIDEO_PLL_RECONFIG_CS,16) and std_logic_vector'(vr_busy & "0000" & vr_wr_q & vr_rd & video_reconfig_q & "11111010")); fb_ad_out(31 downto 16) <= "000000" & st_shift_mode_q & "00000000" when st_shift_mode_cs = '1' else - "100000000" & sys_ctr_q(6 downto 4) & (not blitter_run) & sys_ctr_q(2 downto 0) when sys_ctr_cs = '1' else - lwd_q when lof_cs = '1' and lwd_cs = '1' else - "0000" & hbe_q when hbe_cs = '1' else - "0000" & hdb_q when hdb_cs = '1' else - "0000" & hde_q when hde_cs = '1' else - "0000" & hbb_q when hbb_cs = '1' else - "0000" & hss_q when hss_cs = '1' else - "0000" & hht_q when hht_cs = '1' else - "00000" & vbe_q when vbe_cs = '1' else - "00000" & vdb_q when vdb_cs = '1' else - "00000" & vde_q when vde_cs = '1' else - "00000" & vbb_q when vbb_cs = '1' else - "00000" & vss_q when vss_cs = '1' else - "00000" & vft_q when vft_cs = '1' else - "0000000" & vco_q when vco_cs = '1' else - "000000000000" & vcntrl_q when vcntrl_cs = '1' else - acp_vctr_q(31 downto 16) when acp_vctr_cs = '1' else - atari_hh_q(31 downto 16) when atari_hh_cs = '1' else - atari_vh_q(31 downto 16) when atari_vh_cs = '1' else - atari_hl_q(31 downto 16) when atari_hl_cs = '1' else - atari_vl_q(31 downto 16) when atari_vl_cs = '1' else - "00000000" & border_color_q(23 downto 16) when border_color_cs = '1' else - "0000000" & vr_dout_q when video_pll_config_cs = '1' else - vr_busy & "0000" & vr_wr_q & vr_rd & video_reconfig_q & "11111010" when video_pll_reconfig_cs = '1' else - (others => 'Z'); - + "100000000" & sys_ctr_q(6 downto 4) & (not blitter_run) & sys_ctr_q(2 downto 0) when sys_ctr_cs = '1' else + lwd_q when lof_cs = '1' and lwd_cs = '1' else + "0000" & hbe_q when hbe_cs = '1' else + "0000" & hdb_q when hdb_cs = '1' else + "0000" & hde_q when hde_cs = '1' else + "0000" & hbb_q when hbb_cs = '1' else + "0000" & hss_q when hss_cs = '1' else + "0000" & hht_q when hht_cs = '1' else + "00000" & vbe_q when vbe_cs = '1' else + "00000" & vdb_q when vdb_cs = '1' else + "00000" & vde_q when vde_cs = '1' else + "00000" & vbb_q when vbb_cs = '1' else + "00000" & vss_q when vss_cs = '1' else + "00000" & vft_q when vft_cs = '1' else + "0000000" & vco_q when vco_cs = '1' else + "000000000000" & vcntrl_q when vcntrl_cs = '1' else + acp_vctr_q(31 downto 16) when acp_vctr_cs = '1' else + atari_hh_q(31 downto 16) when atari_hh_cs = '1' else + atari_vh_q(31 downto 16) when atari_vh_cs = '1' else + atari_hl_q(31 downto 16) when atari_hl_cs = '1' else + atari_vl_q(31 downto 16) when atari_vl_cs = '1' else + "00000000" & border_color_q(23 downto 16) when border_color_cs = '1' else + "0000000" & vr_dout_q when video_pll_config_cs = '1' else + vr_busy & "0000" & vr_wr_q & vr_rd & video_reconfig_q & "11111010" when video_pll_reconfig_cs = '1' else + (others => 'Z'); + -- u0_enabledt <= (st_shift_mode_CS or falcon_shift_mode_CS or acp_vctr_CS or border_color_CS or sys_ctr_CS or lof_CS or lwd_CS or HBE_CS or HDB_CS or -- hde_CS or HBB_CS or HSS_CS or HHT_CS or atari_hh_CS or atari_vh_CS or atari_hl_CS or ATARI_VL_CS or VIDEO_PLL_CONFIG_CS or -- VIDEO_PLL_RECONFIG_CS or VBE_CS or VDB_CS or VDE_CS or VBB_CS or VSS_CS or VFT_CS or VCO_CS or vcntrl_cs) and (not nFB_OE); @@ -1326,16 +1326,38 @@ begin -- fb_ad(15 downto 0) <= u1_tridata; fb_ad_out(15 downto 0) <= acp_vctr_q(15 downto 0) when acp_vctr_cs = '1' else - atari_hh_q(15 downto 0) when atari_hh_cs = '1' else - atari_vh_q(15 downto 0) when atari_vh_cs = '1' else - atari_hl_q(15 downto 0) when atari_hl_cs = '1' else - atari_vl_q(15 downto 0) when atari_vl_cs = '1' else - border_color_q(15 downto 0) when border_color_cs = '1' else - (others => 'Z'); + atari_hh_q(15 downto 0) when atari_hh_cs = '1' else + atari_vh_q(15 downto 0) when atari_vh_cs = '1' else + atari_hl_q(15 downto 0) when atari_hl_cs = '1' else + atari_vl_q(15 downto 0) when atari_vl_cs = '1' else + border_color_q(15 downto 0) when border_color_cs = '1' else + (others => 'Z'); - video_mod_ta <= clut_ta_q or st_shift_mode_CS or falcon_shift_mode_CS or acp_vctr_CS or sys_ctr_CS or lof_CS or lwd_CS or HBE_CS or HDB_CS or - hde_CS or HBB_CS or HSS_CS or HHT_CS or atari_hh_CS or atari_vh_CS or atari_hl_CS or ATARI_VL_CS or VBE_CS or VDB_CS or VDE_CS or VBB_CS or - VSS_CS or VFT_CS or VCO_CS or vcntrl_cs; + video_mod_ta <= clut_ta_q or + st_shift_mode_cs or + falcon_shift_mode_cs or + acp_vctr_cs or + sys_ctr_cs or + lof_cs or + lwd_cs or + hbe_cs or + hdb_cs or + hde_cs or + hbb_cs or + hss_cs or + hht_cs or + atari_hh_cs or + atari_vh_cs or + atari_hl_cs or + atari_vl_cs or + vbe_cs or + vdb_cs or + vde_cs or + vbb_cs or + vss_cs or + vft_cs or + vco_cs or + vcntrl_cs; -- VIDEO AUSGABE SETZEN CLK17M_d <= not CLK17M_q; diff --git a/FPGA_Quartus_13.1/firebee1.vhd b/FPGA_Quartus_13.1/firebee1.vhd index 39d550e..8883449 100644 --- a/FPGA_Quartus_13.1/firebee1.vhd +++ b/FPGA_Quartus_13.1/firebee1.vhd @@ -1,12 +1,12 @@ -LIBRARY ieee; - USE ieee.std_logic_1164.all; +library ieee; +use ieee.std_logic_1164.all; -LIBRARY altera; - USE altera.altera_primitives_components.all; +library altera; +use altera.altera_primitives_components.all; -LIBRARY work; +library work; -ENTITY firebee1 IS +entity firebee1 is port ( FB_ALE : in std_logic; @@ -147,7 +147,7 @@ ENTITY firebee1 IS ); end firebee1; -architecture rtl OF firebee1 IS +architecture rtl of firebee1 is signal ACP_CONF : std_logic_vector(31 downto 0); signal clk25m_i : std_logic; signal CLK2M : std_logic; @@ -269,8 +269,7 @@ begin c3 => DDRCLK(3), c4 => DDR_SYNC_66M ); - - + i_dsp : work.dsp port map ( @@ -284,8 +283,9 @@ begin FB_SIZE1 => FB_SIZE1, nFB_BURST => nFB_BURST, nRSTO => nRSTO, - nFB_CS3 => nFB_CS3, - FB_AD => FB_AD, + nFB_CS3 => nFB_CS3, + fb_ad_in => fb_ad_in, + fb_ad_out => fb_ad_out, FB_ADR => FB_ADR, IO => IO, SRD => SRD, @@ -297,8 +297,7 @@ begin DSP_INT => DSP_INT, DSP_TA => DSP_TA ); - - + i_falconio_sdcard_ide_cf : work.falconio_sdcard_ide_cf port map ( @@ -358,8 +357,9 @@ begin SD_CD_DATA3 => SD_CD_DATA3, SD_CDM_D1 => SD_CDM_D1, ACP_CONF => ACP_CONF(31 downto 24), - ACSI_D => ACSI_D, - FB_AD => FB_AD, + ACSI_D => ACSI_D, + fb_ad_in => fb_ad_in, + fb_ad_out => fb_ad_out, FB_ADR => FB_ADR, LP_D => LP_D, SCSI_D => SCSI_D, @@ -405,7 +405,7 @@ begin DMA_DRQ => DMA_DRQ, MIDI_TLR => MIDI_TLR ); - + i_interrupt_handler : work.interrupt_handler port map @@ -429,16 +429,16 @@ begin VSYNC => VSYNC, HSYNC => HSYNC, DMA_DRQ => DMA_DRQ, - nRSTO => nRSTO, - FB_AD => FB_AD, + nRSTO => nRSTO, + fb_ad_in => fb_ad_in, + fb_ad_out => fb_ad_out, FB_ADR => FB_ADR, INT_HANDLER_TA => INT_HANDLER_TA, TIN0 => TIN0, ACP_CONF => ACP_CONF, nIRQ => nIRQ - ); - - + ); + i_mfp_acia_clk_pll : work.altpll1 port map ( @@ -473,7 +473,6 @@ begin data_out => VR_D ); - i_video : entity work.video port map ( @@ -522,7 +521,6 @@ begin VR => VR ); - i_video_clk_pll : altpll4 port map ( @@ -563,6 +561,8 @@ begin nWR_GATE <= not(WR_GATE); nFB_TA <= not(video_ta or int_handler_ta or dsp_ta or falcon_io_ta); + fb_ad_in <= fb_ad; + fb_ad <= fb_ad_out when (video_ta or int_handler_ta or dsp_ta or falcon_io_ta) else (others => 'Z'); CLK33M <= MAIN_CLK; diff --git a/FPGA_Quartus_13.1/firebee_utils_pkg.vhd b/FPGA_Quartus_13.1/firebee_utils_pkg.vhd deleted file mode 100644 index 5f31318..0000000 --- a/FPGA_Quartus_13.1/firebee_utils_pkg.vhd +++ /dev/null @@ -1,171 +0,0 @@ ----------------------------------------------------------------------- ----- ---- ----- This file is part of the 'Firebee' project. ---- ----- http://acp.atari.org ---- ----- ---- ----- Description: ---- ----- This package contains utility functions, procedures and constants ----- for the Firebee project. ----- ----- Author(s): ---- ----- - Markus Fröschle, mfro@mubf.de ----- ---- ----------------------------------------------------------------------- ----- ---- ----- Copyright (C) 2015 Markus Fröschle ----- ---- ----- This source file is free software; you can redistribute it ---- ----- and/or modify it under the terms of the GNU General Public ---- ----- License as published by the Free Software Foundation; either ---- ----- version 2 of the License, or (at your option) any later ---- ----- version. ---- ----- ---- ----- This program is distributed in the hope that it will be ---- ----- useful, but WITHOUT ANY WARRANTY; without even the implied ---- ----- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR ---- ----- PURPOSE. See the GNU General Public License for more ---- ----- details. ---- ----- ---- ----- You should have received a copy of the GNU General Public ---- ----- License along with this program; if not, write to the Free ---- ----- Software Foundation, Inc., 51 Franklin Street, Fifth Floor, ---- ----- Boston, MA 02110-1301, USA. ---- ----- ---- ----------------------------------------------------------------------- --- - -LIBRARY ieee; - USE ieee.std_logic_1164.ALL; - USE ieee.numeric_std.ALL; - -PACKAGE firebee_utils_pkg IS - FUNCTION f_addr_cmp_l(SIGNAL addr : std_logic_vector; CONSTANT addr_const : std_logic_vector) RETURN std_logic; - FUNCTION f_addr_cmp_w(SIGNAL addr : std_logic_vector; CONSTANT addr_const : std_logic_vector) RETURN std_logic; - FUNCTION f_addr_cmp_b(SIGNAL addr : std_logic_vector; CONSTANT addr_const : std_logic_vector) RETURN std_logic; - FUNCTION f_addr_cmp_mask(SIGNAL addr : std_logic_vector; CONSTANT addr_const : std_logic_vector; CONSTANT num_ignore : integer) RETURN std_logic; - - COMPONENT synchronizer IS - PORT - ( - -- Input ports - source_signal : IN std_logic; - - target_clock : IN std_logic; - target_signal : OUT std_logic - ); - END COMPONENT synchronizer; - -END firebee_utils_pkg; - -PACKAGE BODY firebee_utils_pkg IS - - FUNCTION f_addr_cmp_l(SIGNAL addr : std_logic_vector; CONSTANT addr_const : std_logic_vector) RETURN std_logic IS - VARIABLE ret : std_logic := '1'; - VARIABLE c_low : integer; - VARIABLE c_hi : integer; - BEGIN - c_hi := addr_const'HIGH; - c_low := addr_const'LOW; - - -- synthesis translate_off - REPORT("addr_const'HIGH = " & integer'IMAGE(c_hi) & " addr_const'LOW = " & integer'IMAGE(c_low)) SEVERITY WARNING; - REPORT("addr'HIGH = " & integer'IMAGE(addr'HIGH) & " addr'LOW = " & integer'IMAGE(addr'LOW)) SEVERITY WARNING; - -- synthesis translate_on - - FOR i IN c_hi DOWNTO c_low + 2 LOOP - IF addr(i) /= addr_const(c_hi - i) THEN - - -- synthesis translate_off - REPORT("f_addr_cmp_l(): addr = " & to_hstring(unsigned(addr)) & " differs from addr_const = " & to_hstring(unsigned(addr_const)) & - " at bit = " & integer'IMAGE(i)) SEVERITY WARNING; - REPORT("addr(" & integer'IMAGE(i) & ") (" & to_string(addr) & ") = " & to_string(addr(i)) & - " addr_const(" & integer'IMAGE(i) & ") ( " & to_string(addr_const) & ") = " & to_string(addr_const(i))); - -- synthesis translate_on - - ret := '0'; - EXIT; - END IF; - END LOOP; - RETURN ret; - END FUNCTION f_addr_cmp_l; - - FUNCTION f_addr_cmp_w(SIGNAL addr : std_logic_vector; CONSTANT addr_const : std_logic_vector) RETURN std_logic IS - VARIABLE ret : std_logic := '1'; - VARIABLE c_hi : integer; - VARIABLE c_low : integer; - BEGIN - REPORT("f_addr_cmp_w(): addr_const'HIGH = " & integer'IMAGE(addr_const'HIGH) & " addr_const'LOW = " & integer'IMAGE(addr_const'LOW)) SEVERITY WARNING; - REPORT("f_addr_cmp_w(): addr'HIGH = " & integer'IMAGE(addr'HIGH) & " addr'LOW = " & integer'IMAGE(addr'LOW)) SEVERITY WARNING; - - c_hi := addr_const'HIGH; - c_low := addr_const'LOW; - FOR i IN c_hi DOWNTO c_low + 1 LOOP - IF addr(i) /= addr_const(c_hi - i) THEN - - -- synthesis translate_off - REPORT("f_addr_cmp_w(): addr = " & to_hstring(unsigned(addr)) & " differs from addr_const = " & to_hstring(unsigned(addr_const)) & - " at bit = " & integer'IMAGE(i)) SEVERITY WARNING; - REPORT("f_addr_cmp_w(): addr(" & integer'IMAGE(i) & ") (" & to_string(addr) & ") = " & to_string(addr(i)) & - " addr_const(" & integer'IMAGE(i) & ") ( " & to_string(addr_const) & ") = " & to_string(addr_const(i))); - -- synthesis translate_on - - ret := '0'; - EXIT; - END IF; - END LOOP; - RETURN ret; - END FUNCTION f_addr_cmp_w; - - -- this is just for completeness - FUNCTION f_addr_cmp_b(SIGNAL addr : std_logic_vector; CONSTANT addr_const : std_logic_vector) RETURN std_logic IS - VARIABLE ret : std_logic := '1'; - VARIABLE c_hi : integer; - VARIABLE c_low : integer; - BEGIN - c_hi := addr_const'HIGH; - c_low := addr_const'LOW; - - FOR i IN c_hi DOWNTO c_low LOOP - IF addr(i) /= addr_const(c_hi - i) THEN - - -- synthesis translate_off - REPORT("f_addr_cmp_l(): addr = " & to_hstring(unsigned(addr)) & " differs from addr_const = " & to_hstring(unsigned(addr_const)) & - " at bit = " & integer'IMAGE(i)) SEVERITY WARNING; - REPORT("addr(" & integer'IMAGE(i) & ") (" & to_string(addr) & ") = " & to_string(addr(i)) & - " addr_const(" & integer'IMAGE(i) & ") ( " & to_string(addr_const) & ") = " & to_string(addr_const(i))); - -- synthesis translate_on - - ret := '0'; - EXIT; - END IF; - END LOOP; - RETURN ret; - END FUNCTION f_addr_cmp_b; - - -- this is for arbitrary sized address compares. It compares from the highest bit of addr_const to the lowest - num_ignore - -- bit, thus allowing any size of comparision. - FUNCTION f_addr_cmp_mask(SIGNAL addr : std_logic_vector; CONSTANT addr_const : std_logic_vector; CONSTANT num_ignore : integer) RETURN std_logic IS - VARIABLE ret : std_logic := '1'; - VARIABLE c_hi : integer; - VARIABLE c_low : integer; - BEGIN - c_hi := addr_const'HIGH; - c_low := addr_const'LOW; - - FOR i IN addr_const'HIGH DOWNTO addr_const'LOW + num_ignore LOOP - IF addr(i) /= addr_const(c_hi - i) THEN - - -- synthesis translate_off - REPORT("f_addr_cmp_l(): addr = " & to_hstring(unsigned(addr)) & " differs from addr_const = " & to_hstring(unsigned(addr_const)) & - " at bit = " & integer'IMAGE(i)) SEVERITY WARNING; - REPORT("addr(" & integer'IMAGE(i) & ") (" & to_string(addr) & ") = " & to_string(addr(i)) & - " addr_const(" & integer'IMAGE(i) & ") ( " & to_string(addr_const) & ") = " & to_string(addr_const(i))); - -- synthesis translate_on - - ret := '0'; - EXIT; - END IF; - END LOOP; - RETURN ret; - END FUNCTION f_addr_cmp_mask; -END PACKAGE BODY firebee_utils_pkg; \ No newline at end of file