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IP migration and cleanup - again

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torlus
2014-03-07 21:03:00 +00:00
committed by David Gálvez
parent 923b18b2d3
commit d2a3f1f4ff
441 changed files with 163358 additions and 0 deletions
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75
FPGA_by_Gregory_Estrade/Video/BLITTER/BLITTER.vhd Normal file
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-- WARNING: Do NOT edit the input and output ports in this file in a text
-- editor if you plan to continue editing the block that represents it in
-- the Block Editor! File corruption is VERY likely to occur.
-- Copyright (C) 1991-2008 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
-- Generated by Quartus II Version 8.1 (Build Build 163 10/28/2008)
-- Created on Fri Oct 16 15:40:59 2009
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- Entity Declaration
ENTITY BLITTER IS
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
PORT
(
nRSTO : IN STD_LOGIC;
MAIN_CLK : IN STD_LOGIC;
FB_ALE : IN STD_LOGIC;
nFB_WR : IN STD_LOGIC;
nFB_OE : IN STD_LOGIC;
FB_SIZE0 : IN STD_LOGIC;
FB_SIZE1 : IN STD_LOGIC;
VIDEO_RAM_CTR : IN STD_LOGIC_VECTOR(15 downto 0);
BLITTER_ON : IN STD_LOGIC;
FB_ADR : IN STD_LOGIC_VECTOR(31 downto 0);
nFB_CS1 : IN STD_LOGIC;
nFB_CS2 : IN STD_LOGIC;
nFB_CS3 : IN STD_LOGIC;
DDRCLK0 : IN STD_LOGIC;
BLITTER_DIN : IN STD_LOGIC_VECTOR(127 downto 0);
BLITTER_DACK : IN STD_LOGIC_VECTOR(4 downto 0);
BLITTER_RUN : OUT STD_LOGIC;
BLITTER_DOUT : OUT STD_LOGIC_VECTOR(127 downto 0);
BLITTER_ADR : OUT STD_LOGIC_VECTOR(31 downto 0);
BLITTER_SIG : OUT STD_LOGIC;
BLITTER_WR : OUT STD_LOGIC;
BLITTER_TA : OUT STD_LOGIC;
FB_AD : INOUT STD_LOGIC_VECTOR(31 downto 0)
);
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
END BLITTER;
-- Architecture Body
ARCHITECTURE BLITTER_architecture OF BLITTER IS
BEGIN
BLITTER_RUN <= '0';
BLITTER_DOUT <= x"FEDCBA9876543210F0F0F0F0F0F0F0F0";
BLITTER_ADR <= x"76543210";
BLITTER_SIG <= '0';
BLITTER_WR <= '0';
BLITTER_TA <= '0';
END BLITTER_architecture;

659
FPGA_by_Gregory_Estrade/Video/DDR_CTR.tdf Normal file
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TITLE "DDR_CTR";
-- CREATED BY FREDI ASCHWANDEN
INCLUDE "lpm_bustri_BYT.inc";
-- FIFO WATER MARK
CONSTANT FIFO_LWM = 0;
CONSTANT FIFO_MWM = 200;
CONSTANT FIFO_HWM = 500;
-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
SUBDESIGN DDR_CTR
(
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
FB_ADR[31..0] : INPUT;
nFB_CS1 : INPUT;
nFB_CS2 : INPUT;
nFB_CS3 : INPUT;
nFB_OE : INPUT;
FB_SIZE0 : INPUT;
FB_SIZE1 : INPUT;
nRSTO : INPUT;
MAIN_CLK : INPUT;
FB_ALE : INPUT;
nFB_WR : INPUT;
DDR_SYNC_66M : INPUT;
CLR_FIFO : INPUT;
VIDEO_RAM_CTR[15..0] : INPUT;
BLITTER_ADR[31..0] : INPUT;
BLITTER_SIG : INPUT;
BLITTER_WR : INPUT;
DDRCLK0 : INPUT;
CLK33M : INPUT;
FIFO_MW[8..0] : INPUT;
VA[12..0] : OUTPUT;
nVWE : OUTPUT;
nVRAS : OUTPUT;
nVCS : OUTPUT;
VCKE : OUTPUT;
nVCAS : OUTPUT;
FB_LE[3..0] : OUTPUT;
FB_VDOE[3..0] : OUTPUT;
SR_FIFO_WRE : OUTPUT;
SR_DDR_FB : OUTPUT;
SR_DDR_WR : OUTPUT;
SR_DDRWR_D_SEL : OUTPUT;
SR_VDMP[7..0] : OUTPUT;
VIDEO_DDR_TA : OUTPUT;
SR_BLITTER_DACK : OUTPUT;
BA[1..0] : OUTPUT;
DDRWR_D_SEL1 : OUTPUT;
VDM_SEL[3..0] : OUTPUT;
FB_AD[31..0] : BIDIR;
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
)
VARIABLE
FB_REGDDR :MACHINE WITH STATES(FR_WAIT,FR_S0,FR_S1,FR_S2,FR_S3);
DDR_SM :MACHINE WITH STATES(DS_T1,DS_T2A,DS_T2B,DS_T3,DS_N5,DS_N6, DS_N7, DS_N8, -- START (NORMAL 8 CYCLES TOTAL = 60ns)
DS_C2,DS_C3,DS_C4, DS_C5, DS_C6, DS_C7, -- CONFIG
DS_T4R,DS_T5R, -- READ CPU UND BLITTER,
DS_T4W,DS_T5W,DS_T6W,DS_T7W,DS_T8W,DS_T9W, -- WRITE CPU UND BLITTER
DS_T4F,DS_T5F,DS_T6F,DS_T7F,DS_T8F,DS_T9F,DS_T10F, -- READ FIFO
DS_CB6, DS_CB8, -- CLOSE FIFO BANK
DS_R2,DS_R3,DS_R4, DS_R5, DS_R6); -- REFRESH 10X7.5NS=75NS
LINE :NODE;
FB_B[3..0] :NODE;
VCAS :NODE;
VRAS :NODE;
VWE :NODE;
VA_P[12..0] :DFF;
BA_P[1..0] :DFF;
VA_S[12..0] :DFF;
BA_S[1..0] :DFF;
MCS[1..0] :DFF;
CPU_DDR_SYNC :DFF;
DDR_SEL :NODE;
DDR_CS :DFFE;
DDR_CONFIG :NODE;
SR_DDR_WR :DFF;
SR_DDRWR_D_SEL :DFF;
SR_VDMP[7..0] :DFF;
CPU_ROW_ADR[12..0] :NODE;
CPU_BA[1..0] :NODE;
CPU_COL_ADR[9..0] :NODE;
CPU_SIG :NODE;
CPU_REQ :DFF;
CPU_AC :DFF;
BUS_CYC :DFF;
BUS_CYC_END :NODE;
BLITTER_REQ :DFF;
BLITTER_AC :DFF;
BLITTER_ROW_ADR[12..0] :NODE;
BLITTER_BA[1..0] :NODE;
BLITTER_COL_ADR[9..0] :NODE;
FIFO_REQ :DFF;
FIFO_AC :DFF;
FIFO_ROW_ADR[12..0] :NODE;
FIFO_BA[1..0] :NODE;
FIFO_COL_ADR[9..0] :NODE;
FIFO_ACTIVE :NODE;
CLR_FIFO_SYNC :DFF;
CLEAR_FIFO_CNT :DFF;
STOP :DFF;
SR_FIFO_WRE :DFF;
FIFO_BANK_OK :DFF;
FIFO_BANK_NOT_OK :NODE;
DDR_REFRESH_ON :NODE;
DDR_REFRESH_CNT[10..0] :DFF;
DDR_REFRESH_REQ :DFF;
DDR_REFRESH_SIG[3..0] :DFFE;
REFRESH_TIME :DFF;
VIDEO_BASE_L_D[7..0] :DFFE;
VIDEO_BASE_L :NODE;
VIDEO_BASE_M_D[7..0] :DFFE;
VIDEO_BASE_M :NODE;
VIDEO_BASE_H_D[7..0] :DFFE;
VIDEO_BASE_H :NODE;
VIDEO_BASE_X_D[2..0] :DFFE;
VIDEO_ADR_CNT[22..0] :DFFE;
VIDEO_CNT_L :NODE;
VIDEO_CNT_M :NODE;
VIDEO_CNT_H :NODE;
VIDEO_BASE_ADR[22..0] :NODE;
VIDEO_ACT_ADR[26..0] :NODE;
BEGIN
LINE = FB_SIZE0 & FB_SIZE1;
-- BYT SELECT
FB_B0 = FB_ADR[1..0]==0 -- ADR==0
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
FB_B1 = FB_ADR[1..0]==1 -- ADR==1
# FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HIGH WORD
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
FB_B2 = FB_ADR[1..0]==2 -- ADR==2
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
FB_B3 = FB_ADR[1..0]==3 -- ADR==3
# FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LOW WORD
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
-- CPU READ (REG DDR => CPU) AND WRITE (CPU => REG DDR) --------------------------------------------------
FB_REGDDR.CLK = MAIN_CLK;
CASE FB_REGDDR IS
WHEN FR_WAIT =>
FB_LE0 = !nFB_WR;
IF BUS_CYC # DDR_SEL & LINE & !nFB_WR THEN -- LOS WENN BEREIT ODER IMMER BEI LINE WRITE
FB_REGDDR = FR_S0;
ELSE
FB_REGDDR = FR_WAIT;
END IF;
WHEN FR_S0 =>
IF DDR_CS THEN
FB_LE0 = !nFB_WR;
VIDEO_DDR_TA = VCC;
IF LINE THEN
FB_VDOE0 = !nFB_OE & !DDR_CONFIG;
FB_REGDDR = FR_S1;
ELSE
BUS_CYC_END = VCC;
FB_VDOE0 = !nFB_OE & !MAIN_CLK & !DDR_CONFIG;
FB_REGDDR = FR_WAIT;
END IF;
ELSE
FB_REGDDR = FR_WAIT;
END IF;
WHEN FR_S1 =>
IF DDR_CS THEN
FB_VDOE1 = !nFB_OE & !DDR_CONFIG;
FB_LE1 = !nFB_WR;
VIDEO_DDR_TA = VCC;
FB_REGDDR = FR_S2;
ELSE
FB_REGDDR = FR_WAIT;
END IF;
WHEN FR_S2 =>
IF DDR_CS THEN
FB_VDOE2 = !nFB_OE & !DDR_CONFIG;
FB_LE2 = !nFB_WR;
IF !BUS_CYC & LINE & !nFB_WR THEN -- BEI LINE WRITE EVT. WARTEN
FB_REGDDR = FR_S2;
ELSE
VIDEO_DDR_TA = VCC;
FB_REGDDR = FR_S3;
END IF;
ELSE
FB_REGDDR = FR_WAIT;
END IF;
WHEN FR_S3 =>
IF DDR_CS THEN
FB_VDOE3 = !nFB_OE & !MAIN_CLK & !DDR_CONFIG;
FB_LE3 = !nFB_WR;
VIDEO_DDR_TA = VCC;
BUS_CYC_END = VCC;
FB_REGDDR = FR_WAIT;
ELSE
FB_REGDDR = FR_WAIT;
END IF;
END CASE;
-- DDR STEUERUNG -----------------------------------------------------
-- VIDEO RAM CONTROL REGISTER (IST IN VIDEO_MUX_CTR) $F0000400: BIT 0: VCKE; 1: !nVCS ;2:REFRESH ON , (0=FIFO UND CNT CLEAR); 3: CONFIG; 8: FIFO_ACTIVE;
VCKE = VIDEO_RAM_CTR0;
nVCS = !VIDEO_RAM_CTR1;
DDR_REFRESH_ON = VIDEO_RAM_CTR2;
DDR_CONFIG = VIDEO_RAM_CTR3;
FIFO_ACTIVE = VIDEO_RAM_CTR8;
--------------------------------
CPU_ROW_ADR[] = FB_ADR[26..14];
CPU_BA[] = FB_ADR[13..12];
CPU_COL_ADR[] = FB_ADR[11..2];
nVRAS = !VRAS;
nVCAS = !VCAS;
nVWE = !VWE;
SR_DDR_WR.CLK = DDRCLK0;
SR_DDRWR_D_SEL.CLK = DDRCLK0;
SR_VDMP[7..0].CLK = DDRCLK0;
SR_FIFO_WRE.CLK = DDRCLK0;
CPU_AC.CLK = DDRCLK0;
FIFO_AC.CLK = DDRCLK0;
BLITTER_AC.CLK = DDRCLK0;
DDRWR_D_SEL1 = BLITTER_AC;
-- SELECT LOGIC
DDR_SEL = FB_ALE & FB_AD[31..30]==B"01";
DDR_CS.CLK = MAIN_CLK;
DDR_CS.ENA = FB_ALE;
DDR_CS = DDR_SEL;
-- WENN READ ODER WRITE B,W,L DDR SOFORT ANFORDERN, BEI WRITE LINE SP<53>TER
CPU_SIG = DDR_SEL & (nFB_WR # !LINE) & !DDR_CONFIG -- NICHT LINE ODER READ SOFORT LOS WENN NICHT CONFIG
# DDR_SEL & DDR_CONFIG -- CONFIG SOFORT LOS
# FB_REGDDR==FR_S1 & !nFB_WR; -- LINE WRITE SP<53>TER
CPU_REQ.CLK = DDR_SYNC_66M;
CPU_REQ = CPU_SIG
# CPU_REQ & FB_REGDDR!=FR_S1 & FB_REGDDR!=FR_S3 & !BUS_CYC_END & !BUS_CYC; -- HALTEN BUS CYC BEGONNEN ODER FERTIG
BUS_CYC.CLK = DDRCLK0;
BUS_CYC = BUS_CYC & !BUS_CYC_END;
-- STATE MACHINE SYNCHRONISIEREN -----------------
MCS[].CLK = DDRCLK0;
MCS0 = MAIN_CLK;
MCS1 = MCS0;
CPU_DDR_SYNC.CLK = DDRCLK0;
CPU_DDR_SYNC = MCS[]==2 & VCKE & !nVCS; -- NUR 1 WENN EIN
---------------------------------------------------
VA_S[].CLK = DDRCLK0;
BA_S[].CLK = DDRCLK0;
VA[] = VA_S[];
BA[] = BA_S[];
VA_P[].CLK = DDRCLK0;
BA_P[].CLK = DDRCLK0;
-- DDR STATE MACHINE -----------------------------------------------
DDR_SM.CLK = DDRCLK0;
CASE DDR_SM IS
WHEN DS_T1 =>
IF DDR_REFRESH_REQ THEN
DDR_SM = DS_R2;
ELSE
IF CPU_DDR_SYNC THEN -- SYNCHRON UND EIN?
IF DDR_CONFIG THEN -- JA
DDR_SM = DS_C2;
ELSE
IF CPU_REQ THEN -- BEI WAIT UND LINE WRITE
VA_S[] = CPU_ROW_ADR[];
BA_S[] = CPU_BA[];
CPU_AC = VCC;
BUS_CYC = VCC;
DDR_SM = DS_T2B;
ELSE
IF FIFO_REQ # !BLITTER_REQ THEN -- FIFO IST DEFAULT
VA_P[] = FIFO_ROW_ADR[];
BA_P[] = FIFO_BA[];
FIFO_AC = VCC; -- VORBESETZEN
ELSE
VA_P[] = BLITTER_ROW_ADR[];
BA_P[] = BLITTER_BA[];
BLITTER_AC = VCC; -- VORBESETZEN
END IF;
DDR_SM = DS_T2A;
END IF;
END IF;
ELSE
DDR_SM = DS_T1; -- NEIN ->SYNCHRONISIEREN
END IF;
END IF;
WHEN DS_T2A => -- SCHNELLZUGRIFF *** HIER IST PAGE IMMER NOT OK ***
IF DDR_SEL & (nFB_WR # !LINE) THEN
VRAS = VCC;
VA[] = FB_AD[26..14];
BA[] = FB_AD[13..12];
VA_S[10] = VCC; -- AUTO PRECHARGE DA NICHT FIFO PAGE
CPU_AC = VCC;
BUS_CYC = VCC; -- BUS CYCLUS LOSTRETEN
ELSE
VRAS = FIFO_AC & FIFO_REQ # BLITTER_AC & BLITTER_REQ;
VA[] = VA_P[];
BA[] = BA_P[];
VA_S[10] = !(FIFO_AC & FIFO_REQ);
FIFO_BANK_OK = FIFO_AC & FIFO_REQ;
FIFO_AC = FIFO_AC & FIFO_REQ;
BLITTER_AC = BLITTER_AC & BLITTER_REQ;
END IF;
DDR_SM = DS_T3;
WHEN DS_T2B =>
VRAS = VCC;
FIFO_BANK_NOT_OK = VCC;
CPU_AC = VCC;
BUS_CYC = VCC; -- BUS CYCLUS LOSTRETEN
DDR_SM = DS_T3;
WHEN DS_T3 =>
CPU_AC = CPU_AC;
FIFO_AC = FIFO_AC;
BLITTER_AC = BLITTER_AC;
VA_S[10] = VA_S[10]; -- AUTO PRECHARGE WENN NICHT FIFO PAGE
IF !nFB_WR & CPU_AC # BLITTER_WR & BLITTER_AC THEN
DDR_SM = DS_T4W;
ELSE
IF CPU_AC THEN -- CPU?
VA_S[9..0] = CPU_COL_ADR[];
BA_S[] = CPU_BA[];
DDR_SM = DS_T4R;
ELSE
IF FIFO_AC THEN -- FIFO?
VA_S[9..0] = FIFO_COL_ADR[];
BA_S[] = FIFO_BA[];
DDR_SM = DS_T4F;
ELSE
IF BLITTER_AC THEN
VA_S[9..0] = BLITTER_COL_ADR[];
BA_S[] = BLITTER_BA[];
DDR_SM = DS_T4R;
ELSE
DDR_SM = DS_N8;
END IF;
END IF;
END IF;
END IF;
-- READ
WHEN DS_T4R =>
CPU_AC = CPU_AC;
BLITTER_AC = BLITTER_AC;
VCAS = VCC;
SR_DDR_FB = CPU_AC; -- READ DATEN F<>R CPU
SR_BLITTER_DACK = BLITTER_AC; -- BLITTER DACK AND BLITTER LATCH DATEN
DDR_SM = DS_T5R;
WHEN DS_T5R =>
CPU_AC = CPU_AC;
BLITTER_AC = BLITTER_AC;
IF FIFO_REQ & FIFO_BANK_OK THEN -- FIFO READ EINSCHIEBEN WENN BANK OK
VA_S[9..0] = FIFO_COL_ADR[];
VA_S[10] = GND; -- MANUEL PRECHARGE
BA_S[] = FIFO_BA[];
DDR_SM = DS_T6F;
ELSE
VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN
DDR_SM = DS_CB6;
END IF;
-- WRITE
WHEN DS_T4W =>
CPU_AC = CPU_AC;
BLITTER_AC = BLITTER_AC;
SR_BLITTER_DACK = BLITTER_AC; -- BLITTER ACK AND BLITTER LATCH DATEN
VA_S[10] = VA_S[10]; -- AUTO PRECHARGE WENN NICHT FIFO PAGE
DDR_SM = DS_T5W;
WHEN DS_T5W =>
CPU_AC = CPU_AC;
BLITTER_AC = BLITTER_AC;
VA_S[9..0] = CPU_AC & CPU_COL_ADR[]
# BLITTER_AC & BLITTER_COL_ADR[];
VA_S[10] = VA_S[10]; -- AUTO PRECHARGE WENN NICHT FIFO PAGE
BA_S[] = CPU_AC & CPU_BA[]
# BLITTER_AC & BLITTER_BA[];
SR_VDMP[7..4] = FB_B[]; -- BYTE ENABLE WRITE
SR_VDMP[3..0] = LINE & B"1111"; -- LINE ENABLE WRITE
DDR_SM = DS_T6W;
WHEN DS_T6W =>
CPU_AC = CPU_AC;
BLITTER_AC = BLITTER_AC;
VCAS = VCC;
VWE = VCC;
SR_DDR_WR = VCC; -- WRITE COMMAND CPU UND BLITTER IF WRITER
SR_DDRWR_D_SEL = VCC; -- 2. H<>LFTE WRITE DATEN SELEKTIEREN
SR_VDMP[] = LINE & B"11111111"; -- WENN LINE DANN ACTIV
DDR_SM = DS_T7W;
WHEN DS_T7W =>
CPU_AC = CPU_AC;
BLITTER_AC = BLITTER_AC;
SR_DDR_WR = VCC; -- WRITE COMMAND CPU UND BLITTER IF WRITE
SR_DDRWR_D_SEL = VCC; -- 2. H<>LFTE WRITE DATEN SELEKTIEREN
DDR_SM = DS_T8W;
WHEN DS_T8W =>
DDR_SM = DS_T9W;
WHEN DS_T9W =>
IF FIFO_REQ & FIFO_BANK_OK THEN
VA_S[9..0] = FIFO_COL_ADR[];
VA_S[10] = GND; -- NON AUTO PRECHARGE
BA_S[] = FIFO_BA[];
DDR_SM = DS_T6F;
ELSE
VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN
DDR_SM = DS_CB6;
END IF;
-- FIFO READ
WHEN DS_T4F =>
VCAS = VCC;
SR_FIFO_WRE = VCC; -- DATEN WRITE FIFO
DDR_SM = DS_T5F;
WHEN DS_T5F =>
IF FIFO_REQ THEN
IF VIDEO_ADR_CNT[7..0]==H"FF" THEN -- NEUE PAGE?
VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN
DDR_SM = DS_CB6; -- BANK SCHLIESSEN
ELSE
VA_S[9..0] = FIFO_COL_ADR[]+4;
VA_S[10] = GND; -- NON AUTO PRECHARGE
BA_S[] = FIFO_BA[];
DDR_SM = DS_T6F;
END IF;
ELSE
VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN
DDR_SM = DS_CB6; -- NOCH OFFEN LASSEN
END IF;
WHEN DS_T6F =>
VCAS = VCC;
SR_FIFO_WRE = VCC; -- DATEN WRITE FIFO
DDR_SM = DS_T7F;
WHEN DS_T7F =>
IF CPU_REQ & FIFO_MW[]>FIFO_LWM THEN
VA_S[10] = VCC; -- ALLE PAGES SCHLIESEN
DDR_SM = DS_CB8; -- BANK SCHLIESSEN
ELSE
IF FIFO_REQ THEN
IF VIDEO_ADR_CNT[7..0]==H"FF" THEN -- NEUE PAGE?
VA_S[10] = VCC; -- ALLE PAGES SCHLIESSEN
DDR_SM = DS_CB8; -- BANK SCHLIESSEN
ELSE
VA_S[9..0] = FIFO_COL_ADR[]+4;
VA_S[10] = GND; -- NON AUTO PRECHARGE
BA_S[] = FIFO_BA[];
DDR_SM = DS_T8F;
END IF;
ELSE
VA_S[10] = VCC; -- ALLE PAGES SCHLIESEN
DDR_SM = DS_CB8; -- BANK SCHLIESSEN
END IF;
END IF;
WHEN DS_T8F =>
VCAS = VCC;
SR_FIFO_WRE = VCC; -- DATEN WRITE FIFO
IF FIFO_MW[]<FIFO_LWM THEN -- NOTFALL?
DDR_SM = DS_T5F; -- JA->
ELSE
DDR_SM = DS_T9F;
END IF;
WHEN DS_T9F =>
IF FIFO_REQ THEN
IF VIDEO_ADR_CNT[7..0]==H"FF" THEN -- NEUE PAGE?
VA_S[10] = VCC; -- ALLE BANKS SCHLIESEN
DDR_SM = DS_CB6; -- BANK SCHLIESSEN
ELSE
VA_P[9..0] = FIFO_COL_ADR[]+4;
VA_P[10] = GND; -- NON AUTO PRECHARGE
BA_P[] = FIFO_BA[];
DDR_SM = DS_T10F;
END IF;
ELSE
VA_S[10] = VCC; -- ALLE BANKS SCHLIESEN
DDR_SM = DS_CB6; -- BANK SCHLIESSEN
END IF;
WHEN DS_T10F =>
IF DDR_SEL & (nFB_WR # !LINE) & FB_AD[13..12]!=FIFO_BA[] THEN
VRAS = VCC;
VA[] = FB_AD[26..14];
BA[] = FB_AD[13..12];
CPU_AC = VCC;
BUS_CYC = VCC; -- BUS CYCLUS LOSTRETEN
VA_S[10] = VCC; -- AUTO PRECHARGE DA NICHT FIFO BANK
DDR_SM = DS_T3;
ELSE
VCAS = VCC;
VA[] = VA_P[];
BA[] = BA_P[];
SR_FIFO_WRE = VCC; -- DATEN WRITE FIFO
DDR_SM = DS_T7F;
END IF;
-- CONFIG CYCLUS
WHEN DS_C2 =>
DDR_SM = DS_C3;
WHEN DS_C3 =>
BUS_CYC = CPU_REQ;
DDR_SM = DS_C4;
WHEN DS_C4 =>
IF CPU_REQ THEN
DDR_SM = DS_C5;
ELSE
DDR_SM = DS_T1;
END IF;
WHEN DS_C5 =>
DDR_SM = DS_C6;
WHEN DS_C6 =>
VA_S[] = FB_AD[12..0];
BA_S[] = FB_AD[14..13];
DDR_SM = DS_C7;
WHEN DS_C7 =>
VRAS = FB_AD18 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1; -- NUR BEI LONG WRITE
VCAS = FB_AD17 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1; -- NUR BEI LONG WRITE
VWE = FB_AD16 & !nFB_WR & !FB_SIZE0 & !FB_SIZE1; -- NUR BEI LONG WRITE
DDR_SM = DS_N8;
-- CLOSE FIFO BANK
WHEN DS_CB6 =>
FIFO_BANK_NOT_OK = VCC; -- AUF NOT OK
VRAS = VCC; -- B<>NKE SCHLIESSEN
VWE = VCC;
DDR_SM = DS_N7;
WHEN DS_CB8 =>
FIFO_BANK_NOT_OK = VCC; -- AUF NOT OK
VRAS = VCC; -- B<>NKE SCHLIESSEN
VWE = VCC;
DDR_SM = DS_T1;
-- REFRESH 70NS = 10 ZYCLEN
WHEN DS_R2 =>
IF DDR_REFRESH_SIG[]==9 THEN -- EIN CYCLUS VORLAUF UM BANKS ZU SCHLIESSEN
VRAS = VCC; -- ALLE BANKS SCHLIESSEN
VWE = VCC;
VA[10] = VCC;
FIFO_BANK_NOT_OK = VCC;
DDR_SM = DS_R4;
ELSE
VCAS = VCC;
VRAS = VCC;
DDR_SM = DS_R3;
END IF;
WHEN DS_R3 =>
DDR_SM = DS_R4;
WHEN DS_R4 =>
DDR_SM = DS_R5;
WHEN DS_R5 =>
DDR_SM = DS_R6;
WHEN DS_R6 =>
DDR_SM = DS_N5;
-- LEERSCHLAUFE
WHEN DS_N5 =>
DDR_SM = DS_N6;
WHEN DS_N6 =>
DDR_SM = DS_N7;
WHEN DS_N7 =>
DDR_SM = DS_N8;
WHEN DS_N8 =>
DDR_SM = DS_T1;
END CASE;
---------------------------------------------------------------
-- BLITTER ----------------------
-----------------------------------------
BLITTER_REQ.CLK = DDRCLK0;
BLITTER_REQ = BLITTER_SIG & !DDR_CONFIG & VCKE & !nVCS;
BLITTER_ROW_ADR[] = BLITTER_ADR[26..14];
BLITTER_BA1 = BLITTER_ADR13;
BLITTER_BA0 = BLITTER_ADR12;
BLITTER_COL_ADR[] = BLITTER_ADR[11..2];
------------------------------------------------------------------------------
-- FIFO ---------------------------------
--------------------------------------------------------
FIFO_REQ.CLK = DDRCLK0;
FIFO_REQ = (FIFO_MW[]<FIFO_MWM
# FIFO_MW[]<FIFO_HWM & FIFO_REQ) & FIFO_ACTIVE & !CLEAR_FIFO_CNT & !STOP & !DDR_CONFIG & VCKE & !nVCS;
FIFO_ROW_ADR[] = VIDEO_ADR_CNT[22..10];
FIFO_BA1 = VIDEO_ADR_CNT9;
FIFO_BA0 = VIDEO_ADR_CNT8;
FIFO_COL_ADR[] = (VIDEO_ADR_CNT[7..0],B"00");
FIFO_BANK_OK.CLK = DDRCLK0;
FIFO_BANK_OK = FIFO_BANK_OK & !FIFO_BANK_NOT_OK;
-- Z<>HLER R<>CKSETZEN WENN CLR FIFO ----------------
CLR_FIFO_SYNC.CLK =DDRCLK0;
CLR_FIFO_SYNC = CLR_FIFO; -- SYNCHRONISIEREN
CLEAR_FIFO_CNT.CLK = DDRCLK0;
CLEAR_FIFO_CNT = CLR_FIFO_SYNC # !FIFO_ACTIVE;
STOP.CLK = DDRCLK0;
STOP = CLR_FIFO_SYNC # CLEAR_FIFO_CNT;
-- Z<>HLEN -----------------------------------------------
VIDEO_ADR_CNT[].CLK = DDRCLK0;
VIDEO_ADR_CNT[].ENA = SR_FIFO_WRE # CLEAR_FIFO_CNT;
VIDEO_ADR_CNT[] = CLEAR_FIFO_CNT & VIDEO_BASE_ADR[]
# !CLEAR_FIFO_CNT & VIDEO_ADR_CNT[]+1;
VIDEO_BASE_ADR[22..20] = VIDEO_BASE_X_D[];
VIDEO_BASE_ADR[19..12] = VIDEO_BASE_H_D[];
VIDEO_BASE_ADR[11..4] = VIDEO_BASE_M_D[];
VIDEO_BASE_ADR[3..0] = VIDEO_BASE_L_D[7..4];
VDM_SEL[] = VIDEO_BASE_L_D[3..0];
-- AKTUELLE VIDEO ADRESSE
VIDEO_ACT_ADR[26..4] = VIDEO_ADR_CNT[] - (0,FIFO_MW[]);
VIDEO_ACT_ADR[3..0] = VDM_SEL[];
-----------------------------------------------------------------------------------------
-- REFRESH: IMMER 8 AUFS MAL, ANFORDERUNG ALLE 7.8us X 8 STCK. = 62.4us = 2059->2048 33MHz CLOCKS
-----------------------------------------------------------------------------------------
DDR_REFRESH_CNT[].CLK = CLK33M;
DDR_REFRESH_CNT[] = DDR_REFRESH_CNT[]+1; -- Z<>HLEN 0-2047
REFRESH_TIME.CLK = DDRCLK0;
REFRESH_TIME = DDR_REFRESH_CNT[]==0 & !MAIN_CLK; -- SYNC
DDR_REFRESH_SIG[].CLK = DDRCLK0;
DDR_REFRESH_SIG[].ENA = REFRESH_TIME # DDR_SM==DS_R6;
DDR_REFRESH_SIG[] = REFRESH_TIME & 9 & DDR_REFRESH_ON & !DDR_CONFIG -- 9 ST<53>CK (8 REFRESH UND 1 ALS VORLAUF)
# !REFRESH_TIME & (DDR_REFRESH_SIG[]-1) & DDR_REFRESH_ON & !DDR_CONFIG; -- MINUS 1 WENN GEMACHT
DDR_REFRESH_REQ.CLK = DDRCLK0;
DDR_REFRESH_REQ = DDR_REFRESH_SIG[]!=0 & DDR_REFRESH_ON & !REFRESH_TIME & !DDR_CONFIG;
-----------------------------------------------------------
-- VIDEO REGISTER -----------------------
---------------------------------------------------------------------------------------------------------------------
VIDEO_BASE_L_D[].CLK = MAIN_CLK;
VIDEO_BASE_L = !nFB_CS1 & FB_ADR[19..1]==H"7C106"; -- 820D/2
VIDEO_BASE_L_D[] = FB_AD[23..16]; -- SORRY, NUR 16 BYT GRENZEN
VIDEO_BASE_L_D[].ENA = !nFB_WR & VIDEO_BASE_L & FB_B1;
VIDEO_BASE_M_D[].CLK = MAIN_CLK;
VIDEO_BASE_M = !nFB_CS1 & FB_ADR[19..1]==H"7C101"; -- 8203/2
VIDEO_BASE_M_D[] = FB_AD[23..16];
VIDEO_BASE_M_D[].ENA = !nFB_WR & VIDEO_BASE_M & FB_B3;
VIDEO_BASE_H_D[].CLK = MAIN_CLK;
VIDEO_BASE_H = !nFB_CS1 & FB_ADR[19..1]==H"7C100"; -- 8200-1/2
VIDEO_BASE_H_D[] = FB_AD[23..16];
VIDEO_BASE_H_D[].ENA = !nFB_WR & VIDEO_BASE_H & FB_B1;
VIDEO_BASE_X_D[].CLK = MAIN_CLK;
VIDEO_BASE_X_D[] = FB_AD[26..24];
VIDEO_BASE_X_D[].ENA = !nFB_WR & VIDEO_BASE_H & FB_B0;
VIDEO_CNT_L = !nFB_CS1 & FB_ADR[19..1]==H"7C104"; -- 8209/2
VIDEO_CNT_M = !nFB_CS1 & FB_ADR[19..1]==H"7C103"; -- 8207/2
VIDEO_CNT_H = !nFB_CS1 & FB_ADR[19..1]==H"7C102"; -- 8204,5/2
FB_AD[31..24] = lpm_bustri_BYT(
VIDEO_BASE_H & (0,VIDEO_BASE_X_D[])
# VIDEO_CNT_H & (0,VIDEO_ACT_ADR[26..24])
,(VIDEO_BASE_H # VIDEO_CNT_H) & !nFB_OE);
FB_AD[23..16] = lpm_bustri_BYT(
VIDEO_BASE_L & VIDEO_BASE_L_D[]
# VIDEO_BASE_M & VIDEO_BASE_M_D[]
# VIDEO_BASE_H & VIDEO_BASE_H_D[]
# VIDEO_CNT_L & VIDEO_ACT_ADR[7..0]
# VIDEO_CNT_M & VIDEO_ACT_ADR[15..8]
# VIDEO_CNT_H & VIDEO_ACT_ADR[23..16]
,(VIDEO_BASE_L # VIDEO_BASE_M # VIDEO_BASE_H # VIDEO_CNT_L # VIDEO_CNT_M # VIDEO_CNT_H) & !nFB_OE);
END;

1097
FPGA_by_Gregory_Estrade/Video/DDR_CTR.v Normal file
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FPGA_by_Gregory_Estrade/Video/VIDEO_MOD_MUX_CLUTCTR.tdf Normal file
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TITLE "VIDEO MODUSE UND CLUT CONTROL";
-- CREATED BY FREDI ASCHWANDEN
INCLUDE "lpm_bustri_WORD.inc";
INCLUDE "lpm_bustri_BYT.inc";
-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
SUBDESIGN VIDEO_MOD_MUX_CLUTCTR
(
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
nRSTO : INPUT;
MAIN_CLK : INPUT;
nFB_CS1 : INPUT;
nFB_CS2 : INPUT;
nFB_CS3 : INPUT;
nFB_WR : INPUT;
nFB_OE : INPUT;
FB_SIZE0 : INPUT;
FB_SIZE1 : INPUT;
nFB_BURST : INPUT;
FB_ADR[31..0] : INPUT;
CLK33M : INPUT;
CLK25M : INPUT;
BLITTER_RUN : INPUT;
CLK_VIDEO : INPUT;
VR_D[8..0] : INPUT;
VR_BUSY : INPUT;
COLOR8 : OUTPUT;
ACP_CLUT_RD : OUTPUT;
COLOR1 : OUTPUT;
FALCON_CLUT_RDH : OUTPUT;
FALCON_CLUT_RDL : OUTPUT;
FALCON_CLUT_WR[3..0] : OUTPUT;
ST_CLUT_RD : OUTPUT;
ST_CLUT_WR[1..0] : OUTPUT;
CLUT_MUX_ADR[3..0] : OUTPUT;
HSYNC : OUTPUT;
VSYNC : OUTPUT;
nBLANK : OUTPUT;
nSYNC : OUTPUT;
nPD_VGA : OUTPUT;
FIFO_RDE : OUTPUT;
COLOR2 : OUTPUT;
COLOR4 : OUTPUT;
PIXEL_CLK : OUTPUT;
CLUT_OFF[3..0] : OUTPUT;
BLITTER_ON : OUTPUT;
VIDEO_RAM_CTR[15..0] : OUTPUT;
VIDEO_MOD_TA : OUTPUT;
CCR[23..0] : OUTPUT;
CCSEL[2..0] : OUTPUT;
ACP_CLUT_WR[3..0] : OUTPUT;
INTER_ZEI : OUTPUT;
DOP_FIFO_CLR : OUTPUT;
VIDEO_RECONFIG : OUTPUT;
VR_WR : OUTPUT;
VR_RD : OUTPUT;
CLR_FIFO : OUTPUT;
FB_AD[31..0] : BIDIR;
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
)
VARIABLE
CLK17M :DFF;
CLK13M :DFF;
ACP_CLUT_CS :NODE;
ACP_CLUT :NODE;
VIDEO_PLL_CONFIG_CS :NODE;
VR_WR :DFF;
VR_DOUT[8..0] :DFFE;
VR_FRQ[7..0] :DFFE;
VIDEO_PLL_RECONFIG_CS :NODE;
VIDEO_RECONFIG :DFF;
FALCON_CLUT_CS :NODE;
FALCON_CLUT :NODE;
ST_CLUT_CS :NODE;
ST_CLUT :NODE;
FB_B[3..0] :NODE;
FB_16B[1..0] :NODE;
ST_SHIFT_MODE[1..0] :DFFE;
ST_SHIFT_MODE_CS :NODE;
FALCON_SHIFT_MODE[10..0] :DFFE;
FALCON_SHIFT_MODE_CS :NODE;
CLUT_MUX_ADR[3..0] :DFF;
CLUT_MUX_AV[1..0][3..0] :DFF;
ACP_VCTR_CS :NODE;
ACP_VCTR[31..0] :DFFE;
CCR_CS :NODE;
CCR[23..0] :DFFE;
ACP_VIDEO_ON :NODE;
SYS_CTR[6..0] :DFFE;
SYS_CTR_CS :NODE;
VDL_LOF[15..0] :DFFE;
VDL_LOF_CS :NODE;
VDL_LWD[15..0] :DFFE;
VDL_LWD_CS :NODE;
-- DIV. CONTROL REGISTER
CLUT_TA :DFF; -- BRAUCHT EIN WAITSTAT
HSYNC :DFF;
HSYNC_I[7..0] :DFF;
HSY_LEN[7..0] :DFF; -- L<>NGE HSYNC PULS IN PIXEL_CLK
HSYNC_START :DFF;
LAST :DFF; -- LETZTES PIXEL EINER ZEILE ERREICHT
VSYNC :DFF;
VSYNC_START :DFFE;
VSYNC_I[2..0] :DFFE;
nBLANK :DFF;
DISP_ON :DFF;
DPO_ZL :DFFE;
DPO_ON :DFF;
DPO_OFF :DFF;
VDTRON :DFF;
VDO_ZL :DFFE;
VDO_ON :DFF;
VDO_OFF :DFF;
VHCNT[11..0] :DFF;
SUB_PIXEL_CNT[6..0] :DFFE;
VVCNT[10..0] :DFFE;
VERZ[2..0][9..0] :DFF;
RAND[6..0] :DFF;
RAND_ON :NODE;
FIFO_RDE :DFF;
CLR_FIFO :DFFE;
START_ZEILE :DFFE;
SYNC_PIX :DFF;
SYNC_PIX1 :DFF;
SYNC_PIX2 :DFF;
CCSEL[2..0] :DFF;
COLOR16 :NODE;
COLOR24 :NODE;
-- ATARI RESOLUTION
ATARI_SYNC :NODE;
ATARI_HH[31..0] :DFFE; -- HORIZONTAL TIMING 640x480
ATARI_HH_CS :NODE;
ATARI_VH[31..0] :DFFE; -- VERTIKAL TIMING 640x480
ATARI_VH_CS :NODE;
ATARI_HL[31..0] :DFFE; -- HORIZONTAL TIMING 320x240
ATARI_HL_CS :NODE;
ATARI_VL[31..0] :DFFE; -- VERTIKAL TIMING 320x240
ATARI_VL_CS :NODE;
-- HORIZONTAL
RAND_LINKS[11..0] :NODE;
HDIS_START[11..0] :NODE;
HDIS_END[11..0] :NODE;
RAND_RECHTS[11..0] :NODE;
HS_START[11..0] :NODE;
H_TOTAL[11..0] :NODE;
HDIS_LEN[11..0] :NODE;
MULF[5..0] :NODE;
VDL_HHT[11..0] :DFFE;
VDL_HHT_CS :NODE;
VDL_HBE[11..0] :DFFE;
VDL_HBE_CS :NODE;
VDL_HDB[11..0] :DFFE;
VDL_HDB_CS :NODE;
VDL_HDE[11..0] :DFFE;
VDL_HDE_CS :NODE;
VDL_HBB[11..0] :DFFE;
VDL_HBB_CS :NODE;
VDL_HSS[11..0] :DFFE;
VDL_HSS_CS :NODE;
-- VERTIKAL
RAND_OBEN[10..0] :NODE;
VDIS_START[10..0] :NODE;
VDIS_END[10..0] :NODE;
RAND_UNTEN[10..0] :NODE;
VS_START[10..0] :NODE;
V_TOTAL[10..0] :NODE;
FALCON_VIDEO :NODE;
ST_VIDEO :NODE;
INTER_ZEI :DFF;
DOP_ZEI :DFF;
DOP_FIFO_CLR :DFF;
VDL_VBE[10..0] :DFFE;
VDL_VBE_CS :NODE;
VDL_VDB[10..0] :DFFE;
VDL_VDB_CS :NODE;
VDL_VDE[10..0] :DFFE;
VDL_VDE_CS :NODE;
VDL_VBB[10..0] :DFFE;
VDL_VBB_CS :NODE;
VDL_VSS[10..0] :DFFE;
VDL_VSS_CS :NODE;
VDL_VFT[10..0] :DFFE;
VDL_VFT_CS :NODE;
VDL_VCT[8..0] :DFFE;
VDL_VCT_CS :NODE;
VDL_VMD[3..0] :DFFE;
VDL_VMD_CS :NODE;
BEGIN
-- BYT SELECT 32 BIT
FB_B0 = FB_ADR[1..0]==0; -- ADR==0
FB_B1 = FB_ADR[1..0]==1 -- ADR==1
# FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HIGH WORD
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
FB_B2 = FB_ADR[1..0]==2 -- ADR==2
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
FB_B3 = FB_ADR[1..0]==3 -- ADR==3
# FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LOW WORD
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
-- BYT SELECT 16 BIT
FB_16B0 = FB_ADR[0]==0; -- ADR==0
FB_16B1 = FB_ADR[0]==1 -- ADR==1
# !(!FB_SIZE1 & FB_SIZE0); -- NOT BYT
-- ACP CLUT --
ACP_CLUT_CS = !nFB_CS2 & FB_ADR[27..10]==H"0"; -- 0-3FF/1024
ACP_CLUT_RD = ACP_CLUT_CS & !nFB_OE;
ACP_CLUT_WR[] = FB_B[] & ACP_CLUT_CS & !nFB_WR;
CLUT_TA.CLK = MAIN_CLK;
CLUT_TA = (ACP_CLUT_CS # FALCON_CLUT_CS # ST_CLUT_CS) & !VIDEO_MOD_TA;
--FALCON CLUT --
FALCON_CLUT_CS = !nFB_CS1 & FB_ADR[19..10]==H"3E6"; -- $F9800/$400
FALCON_CLUT_RDH = FALCON_CLUT_CS & !nFB_OE & !FB_ADR1; -- HIGH WORD
FALCON_CLUT_RDL = FALCON_CLUT_CS & !nFB_OE & FB_ADR1; -- LOW WORD
FALCON_CLUT_WR[1..0] = FB_16B[] & !FB_ADR1 & FALCON_CLUT_CS & !nFB_WR;
FALCON_CLUT_WR[3..2] = FB_16B[] & FB_ADR1 & FALCON_CLUT_CS & !nFB_WR;
-- ST CLUT --
ST_CLUT_CS = !nFB_CS1 & FB_ADR[19..5]==H"7C12"; -- $F8240/$20
ST_CLUT_RD = ST_CLUT_CS & !nFB_OE;
ST_CLUT_WR[] = FB_16B[] & ST_CLUT_CS & !nFB_WR;
-- ST SHIFT MODE
ST_SHIFT_MODE[].CLK = MAIN_CLK;
ST_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C130"; -- $F8260/2
ST_SHIFT_MODE[] = FB_AD[25..24];
ST_SHIFT_MODE[].ENA = ST_SHIFT_MODE_CS & !nFB_WR & FB_B0;
COLOR1 = ST_SHIFT_MODE[]==B"10" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- MONO
COLOR2 = ST_SHIFT_MODE[]==B"01" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- 4 FARBEN
COLOR4 = ST_SHIFT_MODE[]==B"00" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- 16 FARBEN
-- FALCON SHIFT MODE
FALCON_SHIFT_MODE[].CLK = MAIN_CLK;
FALCON_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C133"; -- $F8266/2
FALCON_SHIFT_MODE[] = FB_AD[26..16];
FALCON_SHIFT_MODE[10..8].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B2;
FALCON_SHIFT_MODE[7..0].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR & FB_B3;
CLUT_OFF[3..0] = FALCON_SHIFT_MODE[3..0] & COLOR4;
COLOR1 = FALCON_SHIFT_MODE10 & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON;
COLOR8 = FALCON_SHIFT_MODE4 & !COLOR16 & FALCON_VIDEO & !ACP_VIDEO_ON;
COLOR16 = FALCON_SHIFT_MODE8 & FALCON_VIDEO & !ACP_VIDEO_ON;
COLOR4 = !COLOR1 & !COLOR16 & !COLOR8 & FALCON_VIDEO & !ACP_VIDEO_ON;
-- ACP VIDEO CONTROL BIT 0=ACP VIDEO ON, 1=POWER ON VIDEO DAC, 2=ACP 24BIT,3=ACP 16BIT,4=ACP 8BIT,5=ACP 1BIT, 6=FALCON SHIFT MODE;7=ST SHIFT MODE;9..8= VCLK FREQUENZ;15=-SYNC ALLOWED; 31..16=VIDEO_RAM_CTR,25=RANDFARBE EINSCHALTEN, 26=STANDARD ATARI SYNCS
ACP_VCTR[].CLK = MAIN_CLK;
ACP_VCTR_CS = !nFB_CS2 & FB_ADR[27..2]==H"100"; -- $400/4
ACP_VCTR[31..8] = FB_AD[31..8];
ACP_VCTR[5..0] = FB_AD[5..0];
ACP_VCTR[31..24].ENA = ACP_VCTR_CS & FB_B0 & !nFB_WR;
ACP_VCTR[23..16].ENA = ACP_VCTR_CS & FB_B1 & !nFB_WR;
ACP_VCTR[15..8].ENA = ACP_VCTR_CS & FB_B2 & !nFB_WR;
ACP_VCTR[5..0].ENA = ACP_VCTR_CS & FB_B3 & !nFB_WR;
ACP_VIDEO_ON = ACP_VCTR0;
nPD_VGA = ACP_VCTR1;
-- ATARI MODUS
ATARI_SYNC = ACP_VCTR26; -- WENN 1 AUTOMATISCHE AUFL<46>SUNG
-- HORIZONTAL TIMING 640x480
ATARI_HH[].CLK = MAIN_CLK;
ATARI_HH_CS = !nFB_CS2 & FB_ADR[27..2]==H"104"; -- $410/4
ATARI_HH[] = FB_AD[];
ATARI_HH[31..24].ENA = ATARI_HH_CS & FB_B0 & !nFB_WR;
ATARI_HH[23..16].ENA = ATARI_HH_CS & FB_B1 & !nFB_WR;
ATARI_HH[15..8].ENA = ATARI_HH_CS & FB_B2 & !nFB_WR;
ATARI_HH[7..0].ENA = ATARI_HH_CS & FB_B3 & !nFB_WR;
-- VERTIKAL TIMING 640x480
ATARI_VH[].CLK = MAIN_CLK;
ATARI_VH_CS = !nFB_CS2 & FB_ADR[27..2]==H"105"; -- $414/4
ATARI_VH[] = FB_AD[];
ATARI_VH[31..24].ENA = ATARI_VH_CS & FB_B0 & !nFB_WR;
ATARI_VH[23..16].ENA = ATARI_VH_CS & FB_B1 & !nFB_WR;
ATARI_VH[15..8].ENA = ATARI_VH_CS & FB_B2 & !nFB_WR;
ATARI_VH[7..0].ENA = ATARI_VH_CS & FB_B3 & !nFB_WR;
-- HORIZONTAL TIMING 320x240
ATARI_HL[].CLK = MAIN_CLK;
ATARI_HL_CS = !nFB_CS2 & FB_ADR[27..2]==H"106"; -- $418/4
ATARI_HL[] = FB_AD[];
ATARI_HL[31..24].ENA = ATARI_HL_CS & FB_B0 & !nFB_WR;
ATARI_HL[23..16].ENA = ATARI_HL_CS & FB_B1 & !nFB_WR;
ATARI_HL[15..8].ENA = ATARI_HL_CS & FB_B2 & !nFB_WR;
ATARI_HL[7..0].ENA = ATARI_HL_CS & FB_B3 & !nFB_WR;
-- VERTIKAL TIMING 320x240
ATARI_VL[].CLK = MAIN_CLK;
ATARI_VL_CS = !nFB_CS2 & FB_ADR[27..2]==H"107"; -- $41C/4
ATARI_VL[] = FB_AD[];
ATARI_VL[31..24].ENA = ATARI_VL_CS & FB_B0 & !nFB_WR;
ATARI_VL[23..16].ENA = ATARI_VL_CS & FB_B1 & !nFB_WR;
ATARI_VL[15..8].ENA = ATARI_VL_CS & FB_B2 & !nFB_WR;
ATARI_VL[7..0].ENA = ATARI_VL_CS & FB_B3 & !nFB_WR;
-- VIDEO PLL CONFIG
VIDEO_PLL_CONFIG_CS = !nFB_CS2 & FB_ADR[27..9]==H"3" & FB_B0 & FB_B1; -- $(F)000'0600-7FF ->6/2 WORD RESP LONG ONLY
VR_WR.CLK = MAIN_CLK;
VR_WR = VIDEO_PLL_CONFIG_CS & !nFB_WR & !VR_BUSY & !VR_WR;
VR_RD = VIDEO_PLL_CONFIG_CS & nFB_WR & !VR_BUSY;
VR_DOUT[].CLK = MAIN_CLK;
VR_DOUT[].ENA = !VR_BUSY;
VR_DOUT[] = VR_D[];
VR_FRQ[].CLK = MAIN_CLK;
VR_FRQ[].ENA = VR_WR & FB_ADR[8..0]==H"04";
VR_FRQ[] = FB_AD[23..16];
-- VIDEO PLL RECONFIG
VIDEO_PLL_RECONFIG_CS = !nFB_CS2 & FB_ADR[27..0]==H"800" & FB_B0; -- $(F)000'0800
VIDEO_RECONFIG.CLK = MAIN_CLK;
VIDEO_RECONFIG = VIDEO_PLL_RECONFIG_CS & !nFB_WR & !VR_BUSY & !VIDEO_RECONFIG;
------------------------------------------------------------------------------------------------------------------------
VIDEO_RAM_CTR[] = ACP_VCTR[31..16];
-------------- COLOR MODE IM ACP SETZEN
COLOR1 = ACP_VCTR5 & !ACP_VCTR4 & !ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON;
COLOR8 = ACP_VCTR4 & !ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON;
COLOR16 = ACP_VCTR3 & !ACP_VCTR2 & ACP_VIDEO_ON;
COLOR24 = ACP_VCTR2 & ACP_VIDEO_ON;
ACP_CLUT = ACP_VIDEO_ON & (COLOR1 # COLOR8) # ST_VIDEO & COLOR1;
-- ST ODER FALCON SHIFT MODE SETZEN WENN WRITE X..SHIFT REGISTER
ACP_VCTR7 = FALCON_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON;
ACP_VCTR6 = ST_SHIFT_MODE_CS & !nFB_WR & !ACP_VIDEO_ON;
ACP_VCTR[7..6].ENA = FALCON_SHIFT_MODE_CS & !nFB_WR # ST_SHIFT_MODE_CS & !nFB_WR # ACP_VCTR_CS & FB_B3 & !nFB_WR & FB_AD0;
FALCON_VIDEO = ACP_VCTR7;
FALCON_CLUT = FALCON_VIDEO & !ACP_VIDEO_ON & !COLOR16;
ST_VIDEO = ACP_VCTR6;
ST_CLUT = ST_VIDEO & !ACP_VIDEO_ON & !FALCON_CLUT & !COLOR1;
CCSEL[].CLK = PIXEL_CLK;
CCSEL[] = B"000" & ST_CLUT -- ONLY FOR INFORMATION
# B"001" & FALCON_CLUT
# B"100" & ACP_CLUT
# B"101" & COLOR16
# B"110" & COLOR24
# B"111" & RAND_ON;
-- DIVERSE (VIDEO)-REGISTER ----------------------------
-- RANDFARBE
CCR[].CLK = MAIN_CLK;
CCR_CS = !nFB_CS2 & FB_ADR[27..2]==H"101"; -- $404/4
CCR[] = FB_AD[23..0];
CCR[23..16].ENA = CCR_CS & FB_B1 & !nFB_WR;
CCR[15..8].ENA = CCR_CS & FB_B2 & !nFB_WR;
CCR[7..0].ENA = CCR_CS & FB_B3 & !nFB_WR;
--SYS CTR
SYS_CTR_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C003"; -- $8006/2
SYS_CTR[].CLK = MAIN_CLK;
SYS_CTR[6..0] = FB_AD[22..16];
SYS_CTR[6..0].ENA = SYS_CTR_CS & !nFB_WR & FB_B3;
BLITTER_ON = !SYS_CTR3;
--VDL_LOF
VDL_LOF_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C107"; -- $820E/2
VDL_LOF[].CLK = MAIN_CLK;
VDL_LOF[] = FB_AD[31..16];
VDL_LOF[15..8].ENA = VDL_LOF_CS & !nFB_WR & FB_B2;
VDL_LOF[7..0].ENA = VDL_LOF_CS & !nFB_WR & FB_B3;
--VDL_LWD
VDL_LWD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C108"; -- $8210/2
VDL_LWD[].CLK = MAIN_CLK;
VDL_LWD[] = FB_AD[31..16];
VDL_LWD[15..8].ENA = VDL_LWD_CS & !nFB_WR & FB_B0;
VDL_LWD[7..0].ENA = VDL_LWD_CS & !nFB_WR & FB_B1;
-- HORIZONTAL
-- VDL_HHT
VDL_HHT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C141"; -- $8282/2
VDL_HHT[].CLK = MAIN_CLK;
VDL_HHT[] = FB_AD[27..16];
VDL_HHT[11..8].ENA = VDL_HHT_CS & !nFB_WR & FB_B2;
VDL_HHT[7..0].ENA = VDL_HHT_CS & !nFB_WR & FB_B3;
-- VDL_HBE
VDL_HBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C143"; -- $8286/2
VDL_HBE[].CLK = MAIN_CLK;
VDL_HBE[] = FB_AD[27..16];
VDL_HBE[11..8].ENA = VDL_HBE_CS & !nFB_WR & FB_B2;
VDL_HBE[7..0].ENA = VDL_HBE_CS & !nFB_WR & FB_B3;
-- VDL_HDB
VDL_HDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C144"; -- $8288/2
VDL_HDB[].CLK = MAIN_CLK;
VDL_HDB[] = FB_AD[27..16];
VDL_HDB[11..8].ENA = VDL_HDB_CS & !nFB_WR & FB_B0;
VDL_HDB[7..0].ENA = VDL_HDB_CS & !nFB_WR & FB_B1;
-- VDL_HDE
VDL_HDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C145"; -- $828A/2
VDL_HDE[].CLK = MAIN_CLK;
VDL_HDE[] = FB_AD[27..16];
VDL_HDE[11..8].ENA = VDL_HDE_CS & !nFB_WR & FB_B2;
VDL_HDE[7..0].ENA = VDL_HDE_CS & !nFB_WR & FB_B3;
-- VDL_HBB
VDL_HBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C142"; -- $8284/2
VDL_HBB[].CLK = MAIN_CLK;
VDL_HBB[] = FB_AD[27..16];
VDL_HBB[11..8].ENA = VDL_HBB_CS & !nFB_WR & FB_B0;
VDL_HBB[7..0].ENA = VDL_HBB_CS & !nFB_WR & FB_B1;
-- VDL_HSS
VDL_HSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C146"; -- $828C/2
VDL_HSS[].CLK = MAIN_CLK;
VDL_HSS[] = FB_AD[27..16];
VDL_HSS[11..8].ENA = VDL_HSS_CS & !nFB_WR & FB_B0;
VDL_HSS[7..0].ENA = VDL_HSS_CS & !nFB_WR & FB_B1;
-- VERTIKAL
-- VDL_VBE
VDL_VBE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C153"; -- $82A6/2
VDL_VBE[].CLK = MAIN_CLK;
VDL_VBE[] = FB_AD[26..16];
VDL_VBE[10..8].ENA = VDL_VBE_CS & !nFB_WR & FB_B2;
VDL_VBE[7..0].ENA = VDL_VBE_CS & !nFB_WR & FB_B3;
-- VDL_VDB
VDL_VDB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C154"; -- $82A8/2
VDL_VDB[].CLK = MAIN_CLK;
VDL_VDB[] = FB_AD[26..16];
VDL_VDB[10..8].ENA = VDL_VDB_CS & !nFB_WR & FB_B0;
VDL_VDB[7..0].ENA = VDL_VDB_CS & !nFB_WR & FB_B1;
-- VDL_VDE
VDL_VDE_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C155"; -- $82AA/2
VDL_VDE[].CLK = MAIN_CLK;
VDL_VDE[] = FB_AD[26..16];
VDL_VDE[10..8].ENA = VDL_VDE_CS & !nFB_WR & FB_B2;
VDL_VDE[7..0].ENA = VDL_VDE_CS & !nFB_WR & FB_B3;
-- VDL_VBB
VDL_VBB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C152"; -- $82A4/2
VDL_VBB[].CLK = MAIN_CLK;
VDL_VBB[] = FB_AD[26..16];
VDL_VBB[10..8].ENA = VDL_VBB_CS & !nFB_WR & FB_B0;
VDL_VBB[7..0].ENA = VDL_VBB_CS & !nFB_WR & FB_B1;
-- VDL_VSS
VDL_VSS_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C156"; -- $82AC/2
VDL_VSS[].CLK = MAIN_CLK;
VDL_VSS[] = FB_AD[26..16];
VDL_VSS[10..8].ENA = VDL_VSS_CS & !nFB_WR & FB_B0;
VDL_VSS[7..0].ENA = VDL_VSS_CS & !nFB_WR & FB_B1;
-- VDL_VFT
VDL_VFT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C151"; -- $82A2/2
VDL_VFT[].CLK = MAIN_CLK;
VDL_VFT[] = FB_AD[26..16];
VDL_VFT[10..8].ENA = VDL_VFT_CS & !nFB_WR & FB_B2;
VDL_VFT[7..0].ENA = VDL_VFT_CS & !nFB_WR & FB_B3;
-- VDL_VCT
VDL_VCT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C160"; -- $82C0/2
VDL_VCT[].CLK = MAIN_CLK;
VDL_VCT[] = FB_AD[24..16];
VDL_VCT[8].ENA = VDL_VCT_CS & !nFB_WR & FB_B0;
VDL_VCT[7..0].ENA = VDL_VCT_CS & !nFB_WR & FB_B1;
-- VDL_VMD
VDL_VMD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C161"; -- $82C2/2
VDL_VMD[].CLK = MAIN_CLK;
VDL_VMD[] = FB_AD[19..16];
VDL_VMD[3..0].ENA = VDL_VMD_CS & !nFB_WR & FB_B3;
--- REGISTER OUT
FB_AD[31..16] = lpm_bustri_WORD(
ST_SHIFT_MODE_CS & (0,ST_SHIFT_MODE[],B"00000000")
# FALCON_SHIFT_MODE_CS & (0,FALCON_SHIFT_MODE[])
# SYS_CTR_CS & (B"100000000",SYS_CTR[6..4],!BLITTER_RUN,SYS_CTR[2..0])
# VDL_LOF_CS & VDL_LOF[]
# VDL_LWD_CS & VDL_LWD[]
# VDL_HBE_CS & (0,VDL_HBE[])
# VDL_HDB_CS & (0,VDL_HDB[])
# VDL_HDE_CS & (0,VDL_HDE[])
# VDL_HBB_CS & (0,VDL_HBB[])
# VDL_HSS_CS & (0,VDL_HSS[])
# VDL_HHT_CS & (0,VDL_HHT[])
# VDL_VBE_CS & (0,VDL_VBE[])
# VDL_VDB_CS & (0,VDL_VDB[])
# VDL_VDE_CS & (0,VDL_VDE[])
# VDL_VBB_CS & (0,VDL_VBB[])
# VDL_VSS_CS & (0,VDL_VSS[])
# VDL_VFT_CS & (0,VDL_VFT[])
# VDL_VCT_CS & (0,VDL_VCT[])
# VDL_VMD_CS & (0,VDL_VMD[])
# ACP_VCTR_CS & ACP_VCTR[31..16]
# ATARI_HH_CS & ATARI_HH[31..16]
# ATARI_VH_CS & ATARI_VH[31..16]
# ATARI_HL_CS & ATARI_HL[31..16]
# ATARI_VL_CS & ATARI_VL[31..16]
# CCR_CS & (0,CCR[23..16])
# VIDEO_PLL_CONFIG_CS & (0,VR_DOUT[])
# VIDEO_PLL_RECONFIG_CS & (VR_BUSY,B"0000",VR_WR,VR_RD,VIDEO_RECONFIG,H"FA")
,(ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # CCR_CS # SYS_CTR_CS # VDL_LOF_CS # VDL_LWD_CS
# VDL_HBE_CS # VDL_HDB_CS # VDL_HDE_CS # VDL_HBB_CS # VDL_HSS_CS # VDL_HHT_CS
# ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS # VIDEO_PLL_CONFIG_CS # VIDEO_PLL_RECONFIG_CS
# VDL_VBE_CS # VDL_VDB_CS # VDL_VDE_CS # VDL_VBB_CS # VDL_VSS_CS # VDL_VFT_CS # VDL_VCT_CS # VDL_VMD_CS) & !nFB_OE);
FB_AD[15..0] = lpm_bustri_WORD(
ACP_VCTR_CS & ACP_VCTR[15..0]
# ATARI_HH_CS & ATARI_HH[15..0]
# ATARI_VH_CS & ATARI_VH[15..0]
# ATARI_HL_CS & ATARI_HL[15..0]
# ATARI_VL_CS & ATARI_VL[15..0]
# CCR_CS & CCR[15..0]
,(ACP_VCTR_CS # CCR_CS # ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS ) & !nFB_OE);
VIDEO_MOD_TA = CLUT_TA # ST_SHIFT_MODE_CS # FALCON_SHIFT_MODE_CS # ACP_VCTR_CS # SYS_CTR_CS # VDL_LOF_CS # VDL_LWD_CS
# VDL_HBE_CS # VDL_HDB_CS # VDL_HDE_CS # VDL_HBB_CS # VDL_HSS_CS # VDL_HHT_CS
# ATARI_HH_CS # ATARI_VH_CS # ATARI_HL_CS # ATARI_VL_CS
# VDL_VBE_CS # VDL_VDB_CS # VDL_VDE_CS # VDL_VBB_CS # VDL_VSS_CS # VDL_VFT_CS # VDL_VCT_CS # VDL_VMD_CS;
-- VIDEO AUSGABE SETZEN
CLK17M.CLK = CLK33M;
CLK17M = !CLK17M;
CLK13M.CLK = CLK25M;
CLK13M = !CLK13M;
PIXEL_CLK = CLK13M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & VDL_VCT2 # VDL_VCT0)
# CLK17M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & !VDL_VCT2 # VDL_VCT0)
# CLK25M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VMD2 & VDL_VCT2 & !VDL_VCT0
# CLK33M & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VMD2 & !VDL_VCT2 & !VDL_VCT0
# CLK25M & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00"
# CLK33M & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01"
# CLK_VIDEO & ACP_VIDEO_ON & ACP_VCTR[9];
--------------------------------------------------------------
-- HORIZONTALE SYNC L<>NGE in PIXEL_CLK
----------------------------------------------------------------
HSY_LEN[].CLK = MAIN_CLK;
HSY_LEN[] = 14 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & VDL_VCT2 # VDL_VCT0)
# 16 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & ( VDL_VMD2 & !VDL_VCT2 # VDL_VCT0)
# 28 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VMD2 & VDL_VCT2 & !VDL_VCT0
# 32 & !ACP_VIDEO_ON & (FALCON_VIDEO # ST_VIDEO) & !VDL_VMD2 & !VDL_VCT2 & !VDL_VCT0
# 28 & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"00"
# 32 & ACP_VIDEO_ON & ACP_VCTR[9..8]==B"01"
# 16 + (0,VR_FRQ[7..1]) & ACP_VIDEO_ON & ACP_VCTR[9]; -- hsync puls length in pixeln=frequenz/ = 500ns
MULF[] = 2 & !ST_VIDEO & VDL_VMD2 -- MULTIPLIKATIONS FAKTOR
# 4 & !ST_VIDEO & !VDL_VMD2
# 16 & ST_VIDEO & VDL_VMD2
# 32 & ST_VIDEO & !VDL_VMD2;
HDIS_LEN[] = 320 & VDL_VMD2 -- BREITE IN PIXELN
# 640 & !VDL_VMD2;
-- DOPPELZEILENMODUS
DOP_ZEI.CLK = MAIN_CLK;
DOP_ZEI = VDL_VMD0 & ST_VIDEO; -- ZEILENVERDOPPELUNG EIN AUS
INTER_ZEI.CLK = PIXEL_CLK;
INTER_ZEI = DOP_ZEI & VVCNT0!=VDIS_START0 & VVCNT[]!=0 & VHCNT[]<(HDIS_END[]-1) -- EINSCHIEBEZEILE AUF "DOPPEL" ZEILEN UND ZEILE NULL WEGEN SYNC
# DOP_ZEI & VVCNT0==VDIS_START0 & VVCNT[]!=0 & VHCNT[]>(HDIS_END[]-2); -- EINSCHIEBEZEILE AUF "NORMAL" ZEILEN UND ZEILE NULL WEGEN SYNC
DOP_FIFO_CLR.CLK = PIXEL_CLK;
DOP_FIFO_CLR = INTER_ZEI & HSYNC_START # SYNC_PIX; -- DOPPELZEILENFIFO L<>SCHEN AM ENDE DER DOPPELZEILE UND BEI MAIN FIFO START
RAND_LINKS[] = VDL_HBE[] & ACP_VIDEO_ON
# 21 & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2
# 42 & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2
# VDL_HBE[] * (0,MULF[5..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; --
HDIS_START[] = VDL_HDB[] & ACP_VIDEO_ON
# RAND_LINKS[]+1 & !ACP_VIDEO_ON; --
HDIS_END[] = VDL_HDE[] & ACP_VIDEO_ON
# RAND_LINKS[]+HDIS_LEN[] & !ACP_VIDEO_ON; --
RAND_RECHTS[] = VDL_HBB[] & ACP_VIDEO_ON
# HDIS_END[]+1 & !ACP_VIDEO_ON; --
HS_START[] = VDL_HSS[] & ACP_VIDEO_ON
# ATARI_HL[11..0] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2
# ATARI_HH[11..0] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2
# (VDL_HHT[]+1+VDL_HSS[]) * (0,MULF[5..1]) & !ACP_VIDEO_ON & !ATARI_SYNC; --
H_TOTAL[] = VDL_HHT[] & ACP_VIDEO_ON
# ATARI_HL[27..16] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2
# ATARI_HH[27..16] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2
# (VDL_HHT[]+2) * (0,MULF[]) & !ACP_VIDEO_ON & !ATARI_SYNC; --
RAND_OBEN[] = VDL_VBE[] & ACP_VIDEO_ON
# 31 & !ACP_VIDEO_ON & ATARI_SYNC
# (0,VDL_VBE[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC;
VDIS_START[] = VDL_VDB[] & ACP_VIDEO_ON
# 32 & !ACP_VIDEO_ON & ATARI_SYNC
# (0,VDL_VDB[10..1])+1 & !ACP_VIDEO_ON & !ATARI_SYNC;
VDIS_END[] = VDL_VDE[] & ACP_VIDEO_ON
# 431 & !ACP_VIDEO_ON & ATARI_SYNC & ST_VIDEO
# 511 & !ACP_VIDEO_ON & ATARI_SYNC & !ST_VIDEO
# (0,VDL_VDE[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC;
RAND_UNTEN[] = VDL_VBB[] & ACP_VIDEO_ON
# VDIS_END[]+1 & !ACP_VIDEO_ON & ATARI_SYNC
# (0,VDL_VBB[10..1])+1 & !ACP_VIDEO_ON & !ATARI_SYNC;
VS_START[] = VDL_VSS[] & ACP_VIDEO_ON
# ATARI_VL[10..0] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2
# ATARI_VH[10..0] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2
# (0,VDL_VSS[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC;
V_TOTAL[] = VDL_VFT[] & ACP_VIDEO_ON
# ATARI_VL[26..16] & !ACP_VIDEO_ON & ATARI_SYNC & VDL_VMD2
# ATARI_VH[26..16] & !ACP_VIDEO_ON & ATARI_SYNC & !VDL_VMD2
# (0,VDL_VFT[10..1]) & !ACP_VIDEO_ON & !ATARI_SYNC;
-- Z<>HLER
LAST.CLK = PIXEL_CLK;
LAST = VHCNT[]==(H_TOTAL[]-2);
VHCNT[].CLK = PIXEL_CLK;
VHCNT[] = (VHCNT[] + 1) & !LAST;
VVCNT[].CLK = PIXEL_CLK;
VVCNT[].ENA = LAST;
VVCNT[] = (VVCNT[] + 1) & (VVCNT[]!=V_TOTAL[]-1);
-- DISPLAY ON OFF
DPO_ZL.CLK = PIXEL_CLK;
DPO_ZL = (VVCNT[]>RAND_OBEN[]-1) & (VVCNT[]<RAND_UNTEN[]-1); -- 1 ZEILE DAVOR ON OFF
DPO_ZL.ENA = LAST; -- AM ZEILENENDE <20>BERNEHMEN
DPO_ON.CLK = PIXEL_CLK;
DPO_ON = VHCNT[]==RAND_LINKS[]; -- BESSER EINZELN WEGEN TIMING
DPO_OFF.CLK = PIXEL_CLK;
DPO_OFF = VHCNT[]==(RAND_RECHTS[]-1);
DISP_ON.CLK = PIXEL_CLK;
DISP_ON = DISP_ON & !DPO_OFF
# DPO_ON & DPO_ZL;
-- DATENTRANSFER ON OFF
VDO_ON.CLK = PIXEL_CLK;
VDO_ON = VHCNT[]==(HDIS_START[]-1); -- BESSER EINZELN WEGEN TIMING
VDO_OFF.CLK = PIXEL_CLK;
VDO_OFF = VHCNT[]==HDIS_END[];
VDO_ZL.CLK = PIXEL_CLK;
VDO_ZL.ENA = LAST; -- AM ZEILENENDE <20>BERNEHMEN
VDO_ZL = (VVCNT[]>=(VDIS_START[]-1)) & (VVCNT[]<VDIS_END[]); -- 1 ZEILE DAVOR ON OFF
VDTRON.CLK = PIXEL_CLK;
VDTRON = VDTRON & !VDO_OFF
# VDO_ON & VDO_ZL;
-- VERZ<52>GERUNG UND SYNC
HSYNC_START.CLK = PIXEL_CLK;
HSYNC_START = VHCNT[]==HS_START[]-3;
HSYNC_I[].CLK = PIXEL_CLK;
HSYNC_I[] = HSY_LEN[] & HSYNC_START
# (HSYNC_I[]-1) & !HSYNC_START & HSYNC_I[]!=0;
VSYNC_START.CLK = PIXEL_CLK;
VSYNC_START.ENA = LAST;
VSYNC_START = VVCNT[]==(VS_START[]-3); -- start am ende der Zeile vor dem vsync
VSYNC_I[].CLK = PIXEL_CLK;
VSYNC_I[].ENA = LAST; -- start am ende der Zeile vor dem vsync
VSYNC_I[] = 3 & VSYNC_START -- 3 zeilen vsync length
# (VSYNC_I[]-1) & !VSYNC_START & VSYNC_I[]!=0; -- runterz<72>hlen bis 0
VERZ[][].CLK = PIXEL_CLK;
VERZ[][1] = VERZ[][0];
VERZ[][2] = VERZ[][1];
VERZ[][3] = VERZ[][2];
VERZ[][4] = VERZ[][3];
VERZ[][5] = VERZ[][4];
VERZ[][6] = VERZ[][5];
VERZ[][7] = VERZ[][6];
VERZ[][8] = VERZ[][7];
VERZ[][9] = VERZ[][8];
VERZ[0][0] = DISP_ON;
VERZ[1][0] = HSYNC_I[]!=0;
VERZ[1][0] = (!ACP_VCTR15 # !VDL_VCT6) & HSYNC_I[]!=0
# ACP_VCTR15 & VDL_VCT6 & HSYNC_I[]==0; -- NUR M<>GLICH WENN BEIDE
VERZ[2][0] = (!ACP_VCTR15 # !VDL_VCT5) & VSYNC_I[]!=0
# ACP_VCTR15 & VDL_VCT5 & VSYNC_I[]==0; -- NUR M<>GLICH WENN BEIDE
nBLANK.CLK = PIXEL_CLK;
nBLANK = VERZ[0][8];
HSYNC.CLK = PIXEL_CLK;
HSYNC = VERZ[1][9];
VSYNC.CLK = PIXEL_CLK;
VSYNC = VERZ[2][9];
nSYNC = GND;
-- RANDFARBE MACHEN ------------------------------------
RAND[].CLK = PIXEL_CLK;
RAND[0] = DISP_ON & !VDTRON & ACP_VCTR25;
RAND[1] = RAND[0];
RAND[2] = RAND[1];
RAND[3] = RAND[2];
RAND[4] = RAND[3];
RAND[5] = RAND[4];
RAND[6] = RAND[5];
RAND_ON = RAND[6];
----------------------------------------------------------
CLR_FIFO.CLK = PIXEL_CLK;
CLR_FIFO.ENA = LAST;
CLR_FIFO = VVCNT[]==V_TOTAL[]-2; -- IN LETZTER ZEILE L<>SCHEN
START_ZEILE.CLK = PIXEL_CLK;
START_ZEILE.ENA = LAST;
START_ZEILE = VVCNT[]==0; -- ZEILE 1
SYNC_PIX.CLK = PIXEL_CLK;
SYNC_PIX = VHCNT[]==3 & START_ZEILE; -- SUB PIXEL Z<>HLER SYNCHRONISIEREN
SYNC_PIX1.CLK = PIXEL_CLK;
SYNC_PIX1 = VHCNT[]==5 & START_ZEILE; -- SUB PIXEL Z<>HLER SYNCHRONISIEREN
SYNC_PIX2.CLK = PIXEL_CLK;
SYNC_PIX2 = VHCNT[]==7 & START_ZEILE; -- SUB PIXEL Z<>HLER SYNCHRONISIEREN
SUB_PIXEL_CNT[].CLK = PIXEL_CLK;
SUB_PIXEL_CNT[].ENA = VDTRON # SYNC_PIX;
SUB_PIXEL_CNT[] = (SUB_PIXEL_CNT[] + 1) & !SYNC_PIX; --count up if display on sonst clear bei sync pix
FIFO_RDE.CLK = PIXEL_CLK;
FIFO_RDE = (SUB_PIXEL_CNT[6..0]==1 & COLOR1
# SUB_PIXEL_CNT[5..0]==1 & COLOR2
# SUB_PIXEL_CNT[4..0]==1 & COLOR4
# SUB_PIXEL_CNT[3..0]==1 & COLOR8
# SUB_PIXEL_CNT[2..0]==1 & COLOR16
# SUB_PIXEL_CNT[1..0]==1 & COLOR24) & VDTRON
# SYNC_PIX # SYNC_PIX1 # SYNC_PIX2; -- 3 CLOCK ZUS<55>TZLICH F<>R FIFO SHIFT DATAOUT UND SHIFT RIGTH POSITION
CLUT_MUX_ADR[].CLK = PIXEL_CLK;
CLUT_MUX_AV[][].CLK = PIXEL_CLK;
CLUT_MUX_AV[0][] = SUB_PIXEL_CNT[3..0];
CLUT_MUX_AV[1][] = CLUT_MUX_AV[0][];
CLUT_MUX_ADR[] = CLUT_MUX_AV[1][];
END;

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