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compiles again, but needs reconnecting the split FlexBus signal at top level

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Markus Fröschle
2016-07-28 07:11:19 +00:00
parent cf0c449258
commit c6f8a7d4e8
3 changed files with 85 additions and 180 deletions
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FPGA_Quartus_13.1/firebee1.vhd
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@@ -201,6 +201,8 @@ architecture rtl OF firebee1 IS
signal nFB_WR_i : std_logic;
signal nIDE_RD_i : std_logic;
signal nIDE_WR_i : std_logic;
signal fb_ad_in : std_logic_vector(31 downto 0);
signal fb_ad_out : std_logic_vector(31 downto 0);
component altpll_reconfig1
port
@@ -491,7 +493,8 @@ begin
CLK_VIDEO => CLK_VIDEO,
VR_BUSY => VR_BUSY,
DDRCLK => DDRCLK,
FB_AD => FB_AD,
fb_ad_in => fb_ad_in,
fb_ad_out => fb_ad_out,
FB_ADR => FB_ADR,
VD => VD,
VDQS => VDQS,