ragnar/FPGA_Config
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reformat

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This commit is contained in:
Markus Fröschle
2016-01-11 07:13:36 +00:00
parent 9cfde26eef
commit b3edfcd457
4 changed files with 92 additions and 74 deletions
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88
FPGA_Quartus_13.1/Interrupt_Handler/interrupt_handler.tdf
View File

@@ -94,7 +94,7 @@ BEGIN
# !FB_SIZE1 & FB_SIZE0 & FB_ADR1 & FB_ADR0 -- LLBYT # !FB_SIZE1 & FB_SIZE0 & FB_ADR1 & FB_ADR0 -- LLBYT
# !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0; -- LONG UND LINE # !FB_SIZE1 & !FB_SIZE0 # FB_SIZE1 & FB_SIZE0; -- LONG UND LINE
-- INTERRUPT CONTROL REGISTER: BIT0=INT5 AUSL<EFBFBD>SEN, 1=INT7 AUSL<EFBFBD>SEN -- INTERRUPT CONTROL REGISTER: BIT0=INT5 AUSLÖSEN, 1=INT7 AUSLÖSEN
INT_CTR[].CLK = MAIN_CLK; INT_CTR[].CLK = MAIN_CLK;
INT_CTR_CS = !nFB_CS2 & FB_ADR[27..2]==H"4000"; -- $10000/4 INT_CTR_CS = !nFB_CS2 & FB_ADR[27..2]==H"4000"; -- $10000/4
INT_CTR[] = FB_AD[]; INT_CTR[] = FB_AD[];
@@ -102,7 +102,8 @@ BEGIN
INT_CTR[23..16].ENA = INT_CTR_CS & FB_B1 & !nFB_WR; INT_CTR[23..16].ENA = INT_CTR_CS & FB_B1 & !nFB_WR;
INT_CTR[15..8].ENA = INT_CTR_CS & FB_B2 & !nFB_WR; INT_CTR[15..8].ENA = INT_CTR_CS & FB_B2 & !nFB_WR;
INT_CTR[7..0].ENA = INT_CTR_CS & FB_B3 & !nFB_WR; INT_CTR[7..0].ENA = INT_CTR_CS & FB_B3 & !nFB_WR;
-- INTERRUPT ENABLE REGISTER BIT31=INT7,30=INT6,29=INT5,28=INT4,27=INT3,26=INT2
-- INTERRUPT ENABLE REGISTER BIT31=INT7,30=INT6,29=INT5,28=INT4,27=INT3,26=INT2
INT_ENA[].CLK = MAIN_CLK; INT_ENA[].CLK = MAIN_CLK;
INT_ENA[].CLRN = nRSTO; INT_ENA[].CLRN = nRSTO;
INT_ENA_CS = !nFB_CS2 & FB_ADR[27..2]==H"4001"; -- $10004/4 INT_ENA_CS = !nFB_CS2 & FB_ADR[27..2]==H"4001"; -- $10004/4
@@ -111,16 +112,19 @@ BEGIN
INT_ENA[23..16].ENA = INT_ENA_CS & FB_B1 & !nFB_WR; INT_ENA[23..16].ENA = INT_ENA_CS & FB_B1 & !nFB_WR;
INT_ENA[15..8].ENA = INT_ENA_CS & FB_B2 & !nFB_WR; INT_ENA[15..8].ENA = INT_ENA_CS & FB_B2 & !nFB_WR;
INT_ENA[7..0].ENA = INT_ENA_CS & FB_B3 & !nFB_WR; INT_ENA[7..0].ENA = INT_ENA_CS & FB_B3 & !nFB_WR;
-- INTERRUPT CLEAR REGISTER WRITE ONLY 1=INTERRUPT CLEAR
-- INTERRUPT CLEAR REGISTER WRITE ONLY 1=INTERRUPT CLEAR
INT_CLEAR[].CLK = MAIN_CLK; INT_CLEAR[].CLK = MAIN_CLK;
INT_CLEAR_CS = !nFB_CS2 & FB_ADR[27..2]==H"4002"; -- $10008/4 INT_CLEAR_CS = !nFB_CS2 & FB_ADR[27..2]==H"4002"; -- $10008/4
INT_CLEAR[31..24] = FB_AD[31..24] & INT_CLEAR_CS & FB_B0 & !nFB_WR; INT_CLEAR[31..24] = FB_AD[31..24] & INT_CLEAR_CS & FB_B0 & !nFB_WR;
INT_CLEAR[23..16] = FB_AD[23..16] & INT_CLEAR_CS & FB_B1 & !nFB_WR; INT_CLEAR[23..16] = FB_AD[23..16] & INT_CLEAR_CS & FB_B1 & !nFB_WR;
INT_CLEAR[15..8] = FB_AD[15..8] & INT_CLEAR_CS & FB_B2 & !nFB_WR; INT_CLEAR[15..8] = FB_AD[15..8] & INT_CLEAR_CS & FB_B2 & !nFB_WR;
INT_CLEAR[7..0] = FB_AD[7..0] & INT_CLEAR_CS & FB_B3 & !nFB_WR; INT_CLEAR[7..0] = FB_AD[7..0] & INT_CLEAR_CS & FB_B3 & !nFB_WR;
-- INTERRUPT LATCH REGISTER READ ONLY
-- INTERRUPT LATCH REGISTER READ ONLY
INT_LATCH_CS = !nFB_CS2 & FB_ADR[27..2]==H"4003"; -- $1000C/4 INT_LATCH_CS = !nFB_CS2 & FB_ADR[27..2]==H"4003"; -- $1000C/4
-- INTERRUPT
-- INTERRUPT
!nIRQ2 = HSYNC & INT_ENA[26]; !nIRQ2 = HSYNC & INT_ENA[26];
!nIRQ3 = INT_CTR0 & INT_ENA[27]; !nIRQ3 = INT_CTR0 & INT_ENA[27];
!nIRQ4 = VSYNC & INT_ENA[28]; !nIRQ4 = VSYNC & INT_ENA[28];
@@ -128,26 +132,27 @@ BEGIN
!nIRQ6 = !nMFP_INT & INT_ENA[30]; !nIRQ6 = !nMFP_INT & INT_ENA[30];
!nIRQ7 = PSEUDO_BUS_ERROR & INT_ENA[31]; !nIRQ7 = PSEUDO_BUS_ERROR & INT_ENA[31];
PSEUDO_BUS_ERROR = !nFB_CS1 & (FB_ADR[19..4]==H"F8C8" -- SCC
# FB_ADR[19..4]==H"F8E0" -- VME
-- # FB_ADR[19..4]==H"F920" -- PADDLE
-- # FB_ADR[19..4]==H"F921" -- PADDLE
-- # FB_ADR[19..4]==H"F922" -- PADDLE
# FB_ADR[19..4]==H"FFA8" -- MFP2
# FB_ADR[19..4]==H"FFA9" -- MFP2
# FB_ADR[19..4]==H"FFAA" -- MFP2
# FB_ADR[19..4]==H"FFA8" -- MFP2
# FB_ADR[19..8]==H"F87" -- TT SCSI
# FB_ADR[19..4]==H"FFC2" -- ST UHR
# FB_ADR[19..4]==H"FFC3" -- ST UHR
-- # FB_ADR[19..4]==H"F890" -- DMA SOUND
-- # FB_ADR[19..4]==H"F891" -- DMA SOUND
-- # FB_ADR[19..4]==H"F892" -- DMA SOUND
);
-- IF VIDEO ADR CHANGE
TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR; -- WRITE VIDEO BASE ADR HIGH 0xFFFF8201/2
-- INTERRUPT LATCH PSEUDO_BUS_ERROR = !nFB_CS1 & (FB_ADR[19..4]==H"F8C8" -- SCC
# FB_ADR[19..4]==H"F8E0" -- VME
-- # FB_ADR[19..4]==H"F920" -- PADDLE
-- # FB_ADR[19..4]==H"F921" -- PADDLE
-- # FB_ADR[19..4]==H"F922" -- PADDLE
# FB_ADR[19..4]==H"FFA8" -- MFP2
# FB_ADR[19..4]==H"FFA9" -- MFP2
# FB_ADR[19..4]==H"FFAA" -- MFP2
# FB_ADR[19..4]==H"FFA8" -- MFP2
# FB_ADR[19..8]==H"F87" -- TT SCSI
# FB_ADR[19..4]==H"FFC2" -- ST UHR
# FB_ADR[19..4]==H"FFC3" -- ST UHR
-- # FB_ADR[19..4]==H"F890" -- DMA SOUND
-- # FB_ADR[19..4]==H"F891" -- DMA SOUND
-- # FB_ADR[19..4]==H"F892" -- DMA SOUND
);
-- IF VIDEO ADR CHANGE
TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR; -- WRITE VIDEO BASE ADR HIGH 0xFFFF8201/2
-- INTERRUPT LATCH
INT_L[].CLK = MAIN_CLK; INT_L[].CLK = MAIN_CLK;
INT_L[].CLRN = nRSTO; INT_L[].CLRN = nRSTO;
INT_L0 = PIC_INT & INT_ENA[0]; INT_L0 = PIC_INT & INT_ENA[0];
@@ -162,9 +167,11 @@ TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR; -- WRITE VIDEO BASE ADR H
INT_L9 = HSYNC & INT_ENA[9]; INT_L9 = HSYNC & INT_ENA[9];
INT_LA[][].CLK = MAIN_CLK; INT_LA[][].CLK = MAIN_CLK;
INT_LATCH[] = H"FFFFFFFF";
INT_LATCH[] = H"FFFFFFFF";
INT_LATCH[].CLRN = !INT_CLEAR[] & nRSTO; INT_LATCH[].CLRN = !INT_CLEAR[] & nRSTO;
FOR I IN 0 TO 9 GENERATE
FOR I IN 0 TO 9 GENERATE
INT_LA[I][].CLRN = INT_ENA[I] & nRSTO; INT_LA[I][].CLRN = INT_ENA[I] & nRSTO;
INT_LA[I][] = INT_LA[I][]+1 & INT_L[I] & INT_LA[I][]<7 INT_LA[I][] = INT_LA[I][]+1 & INT_L[I] & INT_LA[I][]<7
# INT_LA[I][]-1 & !INT_L[I] & INT_LA[I][]>8 # INT_LA[I][]-1 & !INT_L[I] & INT_LA[I][]>8
@@ -191,8 +198,9 @@ TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR; -- WRITE VIDEO BASE ADR H
INT_IN29 = INT_LATCH[]!=H"00000000"; INT_IN29 = INT_LATCH[]!=H"00000000";
INT_IN30 = !nMFP_INT; INT_IN30 = !nMFP_INT;
INT_IN31 = DMA_DRQ; INT_IN31 = DMA_DRQ;
--***************************************************************************************
-- ACP CONFIG REGISTER: BIT 31-> 0=CF 1=IDE --***************************************************************************************
-- ACP CONFIG REGISTER: BIT 31-> 0=CF 1=IDE
ACP_CONF[].CLK = MAIN_CLK; ACP_CONF[].CLK = MAIN_CLK;
ACP_CONF_CS = !nFB_CS2 & FB_ADR[27..2]==H"10000"; -- $4'0000/4 ACP_CONF_CS = !nFB_CS2 & FB_ADR[27..2]==H"10000"; -- $4'0000/4
ACP_CONF[] = FB_AD[]; ACP_CONF[] = FB_AD[];
@@ -200,11 +208,11 @@ TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR; -- WRITE VIDEO BASE ADR H
ACP_CONF[23..16].ENA = ACP_CONF_CS & FB_B1 & !nFB_WR; ACP_CONF[23..16].ENA = ACP_CONF_CS & FB_B1 & !nFB_WR;
ACP_CONF[15..8].ENA = ACP_CONF_CS & FB_B2 & !nFB_WR; ACP_CONF[15..8].ENA = ACP_CONF_CS & FB_B2 & !nFB_WR;
ACP_CONF[7..0].ENA = ACP_CONF_CS & FB_B3 & !nFB_WR; ACP_CONF[7..0].ENA = ACP_CONF_CS & FB_B3 & !nFB_WR;
--*************************************************************************************** --***************************************************************************************
-------------------------------------------------------------- --------------------------------------------------------------
-- C1287 0=SEK 2=MIN 4=STD 6=WOCHENTAG 7=TAG 8=MONAT 9=JAHR -- C1287 0=SEK 2=MIN 4=STD 6=WOCHENTAG 7=TAG 8=MONAT 9=JAHR
---------------------------------------------------------- ----------------------------------------------------------
RTC_ADR[].CLK = MAIN_CLK; RTC_ADR[].CLK = MAIN_CLK;
RTC_ADR[] = FB_AD[21..16]; RTC_ADR[] = FB_AD[21..16];
UHR_AS = !nFB_CS1 & FB_ADR[19..1]==H"7C4B0" & FB_B1; -- FFFF8961 UHR_AS = !nFB_CS1 & FB_ADR[19..1]==H"7C4B0" & FB_B1; -- FFFF8961
@@ -238,7 +246,7 @@ TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR; -- WRITE VIDEO BASE ADR H
WERTE[1][11] = VCC; -- IMMER 24H FORMAT WERTE[1][11] = VCC; -- IMMER 24H FORMAT
WERTE[0][11] = VCC; -- IMMER SOMMERZEITKORREKTUR WERTE[0][11] = VCC; -- IMMER SOMMERZEITKORREKTUR
WERTE[7][13] = VCC; -- IMMER RICHTIG WERTE[7][13] = VCC; -- IMMER RICHTIG
-- SOMMER WINTERZEIT: BIT 0 IM REGISTER D IST DIE INFORMATION OB SOMMERZEIT IST (BRAUCHT MAN F<>R R<>CKSCHALTUNG) -- SOMMER WINTERZEIT: BIT 0 IM REGISTER D IST DIE INFORMATION OB SOMMERZEIT IST (BRAUCHT MAN F<>R R<>CKSCHALTUNG)
SOMMERZEIT = WERTE[][6]==1 & WERTE[][4]==1 & WERTE[][8]==4 & WERTE[][7]>23; --LETZTER SONNTAG IM APRIL SOMMERZEIT = WERTE[][6]==1 & WERTE[][4]==1 & WERTE[][8]==4 & WERTE[][7]>23; --LETZTER SONNTAG IM APRIL
WERTE[0][13] = SOMMERZEIT; WERTE[0][13] = SOMMERZEIT;
WERTE[0][13].ENA = INC_STD & (SOMMERZEIT # WINTERZEIT); WERTE[0][13].ENA = INC_STD & (SOMMERZEIT # WINTERZEIT);
@@ -249,36 +257,36 @@ TIN0 = !nFB_CS1 & FB_ADR[19..1]==H"7C100" & !nFB_WR; -- WRITE VIDEO BASE ADR H
ACHTELSEKUNDEN[].ENA = PIC_INT_SYNC[2] & UPDATE_ON; ACHTELSEKUNDEN[].ENA = PIC_INT_SYNC[2] & UPDATE_ON;
-- SEKUNDEN -- SEKUNDEN
INC_SEC = ACHTELSEKUNDEN[]==7 & PIC_INT_SYNC[2] & UPDATE_ON; INC_SEC = ACHTELSEKUNDEN[]==7 & PIC_INT_SYNC[2] & UPDATE_ON;
WERTE[][0] = (WERTE[][0]+1) & WERTE[][0]!=59 & !(RTC_ADR[]==0 & UHR_DS & !nFB_WR); -- SEKUNDEN Z<>HLEN BIS 59 WERTE[][0] = (WERTE[][0]+1) & WERTE[][0]!=59 & !(RTC_ADR[]==0 & UHR_DS & !nFB_WR); -- SEKUNDEN Z<>HLEN BIS 59
WERTE[][0].ENA = INC_SEC & !(RTC_ADR[]==0 & UHR_DS & !nFB_WR); WERTE[][0].ENA = INC_SEC & !(RTC_ADR[]==0 & UHR_DS & !nFB_WR);
-- MINUTEN -- MINUTEN
INC_MIN = INC_SEC & WERTE[][0]==59; -- INC_MIN = INC_SEC & WERTE[][0]==59; --
WERTE[][2] = (WERTE[][2]+1) & WERTE[][2]!=59 & !(RTC_ADR[]==2 & UHR_DS & !nFB_WR); -- MINUTEN Z<>HLEN BIS 59 WERTE[][2] = (WERTE[][2]+1) & WERTE[][2]!=59 & !(RTC_ADR[]==2 & UHR_DS & !nFB_WR); -- MINUTEN Z<>HLEN BIS 59
WERTE[][2].ENA = INC_MIN & !(RTC_ADR[]==2 & UHR_DS & !nFB_WR); -- WERTE[][2].ENA = INC_MIN & !(RTC_ADR[]==2 & UHR_DS & !nFB_WR); --
-- STUNDEN -- STUNDEN
INC_STD = INC_MIN & WERTE[][2]==59; INC_STD = INC_MIN & WERTE[][2]==59;
WERTE[][4] = (WERTE[][4]+1+(1 & SOMMERZEIT)) & WERTE[][4]!=23 & !(RTC_ADR[]==4 & UHR_DS & !nFB_WR); -- STUNDEN Z<>HLEN BIS 23 WERTE[][4] = (WERTE[][4]+1+(1 & SOMMERZEIT)) & WERTE[][4]!=23 & !(RTC_ADR[]==4 & UHR_DS & !nFB_WR); -- STUNDEN Z<>HLEN BIS 23
WERTE[][4].ENA = INC_STD & !(WINTERZEIT & WERTE[0][12]) & !(RTC_ADR[]==4 & UHR_DS & !nFB_WR); -- EINE STUNDE AUSLASSEN WENN WINTERZEITUMSCHALTUNG UND NOCH SOMMERZEIT WERTE[][4].ENA = INC_STD & !(WINTERZEIT & WERTE[0][12]) & !(RTC_ADR[]==4 & UHR_DS & !nFB_WR); -- EINE STUNDE AUSLASSEN WENN WINTERZEITUMSCHALTUNG UND NOCH SOMMERZEIT
-- WOCHENTAG UND TAG -- WOCHENTAG UND TAG
INC_TAG = INC_STD & WERTE[][2]==23; INC_TAG = INC_STD & WERTE[][2]==23;
WERTE[][6] = (WERTE[][6]+1) & WERTE[][6]!=7 & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR) -- WOCHENTAG Z<>HLEN BIS 7 WERTE[][6] = (WERTE[][6]+1) & WERTE[][6]!=7 & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR) -- WOCHENTAG Z<>HLEN BIS 7
# 1 & WERTE[][6]==7 & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR); -- DANN BEI 1 WEITER # 1 & WERTE[][6]==7 & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR); -- DANN BEI 1 WEITER
WERTE[][6].ENA = INC_TAG & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR); WERTE[][6].ENA = INC_TAG & !(RTC_ADR[]==6 & UHR_DS & !nFB_WR);
ANZAHL_TAGE_DES_MONATS[] = 31 & (WERTE[][8]==1 # WERTE[][8]==3 # WERTE[][8]==5 # WERTE[][8]==7 # WERTE[][8]==8 # WERTE[][8]==10 # WERTE[][8]==12) ANZAHL_TAGE_DES_MONATS[] = 31 & (WERTE[][8]==1 # WERTE[][8]==3 # WERTE[][8]==5 # WERTE[][8]==7 # WERTE[][8]==8 # WERTE[][8]==10 # WERTE[][8]==12)
# 30 & (WERTE[][8]==4 # WERTE[][8]==6 # WERTE[][8]==9 # WERTE[][8]==11) # 30 & (WERTE[][8]==4 # WERTE[][8]==6 # WERTE[][8]==9 # WERTE[][8]==11)
# 29 & WERTE[][8]==2 & WERTE[1..0][9]==0 # 29 & WERTE[][8]==2 & WERTE[1..0][9]==0
# 28 & WERTE[][8]==2 & WERTE[1..0][9]!=0; # 28 & WERTE[][8]==2 & WERTE[1..0][9]!=0;
WERTE[][7] = (WERTE[][7]+1) & WERTE[][7]!=ANZAHL_TAGE_DES_MONATS[] & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR) -- TAG Z<>HLEN BIS MONATSENDE WERTE[][7] = (WERTE[][7]+1) & WERTE[][7]!=ANZAHL_TAGE_DES_MONATS[] & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR) -- TAG Z<>HLEN BIS MONATSENDE
# 1 & WERTE[][7]==ANZAHL_TAGE_DES_MONATS[] & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR); -- DANN BEI 1 WEITER # 1 & WERTE[][7]==ANZAHL_TAGE_DES_MONATS[] & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR); -- DANN BEI 1 WEITER
WERTE[][7].ENA = INC_TAG & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR); -- WERTE[][7].ENA = INC_TAG & !(RTC_ADR[]==7 & UHR_DS & !nFB_WR); --
-- MONATE -- MONATE
INC_MONAT = INC_TAG & WERTE[][7]==ANZAHL_TAGE_DES_MONATS[]; -- INC_MONAT = INC_TAG & WERTE[][7]==ANZAHL_TAGE_DES_MONATS[]; --
WERTE[][8] = (WERTE[][8]+1) & WERTE[][8]!=12 & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR) -- MONATE Z<>HLEN BIS 12 WERTE[][8] = (WERTE[][8]+1) & WERTE[][8]!=12 & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR) -- MONATE Z<>HLEN BIS 12
# 1 & WERTE[][8]==12 & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR); -- DANN BEI 1 WEITER # 1 & WERTE[][8]==12 & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR); -- DANN BEI 1 WEITER
WERTE[][8].ENA = INC_MONAT & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR); WERTE[][8].ENA = INC_MONAT & !(RTC_ADR[]==8 & UHR_DS & !nFB_WR);
-- JAHR -- JAHR
INC_JAHR = INC_MONAT & WERTE[][8]==12; -- INC_JAHR = INC_MONAT & WERTE[][8]==12; --
WERTE[][9] = (WERTE[][9]+1) & WERTE[][9]!=99 & !(RTC_ADR[]==9 & UHR_DS & !nFB_WR); -- JAHRE Z<>HLEN BIS 99 WERTE[][9] = (WERTE[][9]+1) & WERTE[][9]!=99 & !(RTC_ADR[]==9 & UHR_DS & !nFB_WR); -- JAHRE Z<>HLEN BIS 99
WERTE[][9].ENA = INC_JAHR & !(RTC_ADR[]==9 & UHR_DS & !nFB_WR); WERTE[][9].ENA = INC_JAHR & !(RTC_ADR[]==9 & UHR_DS & !nFB_WR);
-- TRISTATE OUTPUT -- TRISTATE OUTPUT

68
FPGA_Quartus_13.1/Video/VIDEO_MOD_MUX_CLUTCTR.tdf
View File

@@ -93,10 +93,10 @@ VARIABLE
ACP_VIDEO_ON :NODE; ACP_VIDEO_ON :NODE;
SYS_CTR[6..0] :DFFE; SYS_CTR[6..0] :DFFE;
SYS_CTR_CS :NODE; SYS_CTR_CS :NODE;
LOF[15..0] :DFFE; LOF[15..0] :DFFE;
LOF_CS :NODE; LOF_CS :NODE;
LWD[15..0] :DFFE; LWD[15..0] :DFFE;
LWD_CS :NODE; LWD_CS :NODE;
-- DIV. CONTROL REGISTER -- DIV. CONTROL REGISTER
CLUT_TA :DFF; -- BRAUCHT EIN WAITSTAT CLUT_TA :DFF; -- BRAUCHT EIN WAITSTAT
HSYNC :DFF; HSYNC :DFF;
@@ -131,6 +131,7 @@ VARIABLE
CCSEL[2..0] :DFF; CCSEL[2..0] :DFF;
COLOR16 :NODE; COLOR16 :NODE;
COLOR24 :NODE; COLOR24 :NODE;
-- ATARI RESOLUTION -- ATARI RESOLUTION
ATARI_SYNC :NODE; ATARI_SYNC :NODE;
ATARI_HH[31..0] :DFFE; -- HORIZONTAL TIMING 640x480 ATARI_HH[31..0] :DFFE; -- HORIZONTAL TIMING 640x480
@@ -150,18 +151,18 @@ VARIABLE
H_TOTAL[11..0] :NODE; H_TOTAL[11..0] :NODE;
HDIS_LEN[11..0] :NODE; HDIS_LEN[11..0] :NODE;
MULF[5..0] :NODE; MULF[5..0] :NODE;
HHT[11..0] :DFFE; HHT[11..0] :DFFE;
HHT_CS :NODE; HHT_CS :NODE;
HBE[11..0] :DFFE; HBE[11..0] :DFFE;
HBE_CS :NODE; HBE_CS :NODE;
HDB[11..0] :DFFE; HDB[11..0] :DFFE;
HDB_CS :NODE; HDB_CS :NODE;
HDE[11..0] :DFFE; HDE[11..0] :DFFE;
HDE_CS :NODE; HDE_CS :NODE;
HBB[11..0] :DFFE; HBB[11..0] :DFFE;
HBB_CS :NODE; HBB_CS :NODE;
HSS[11..0] :DFFE; HSS[11..0] :DFFE;
HSS_CS :NODE; HSS_CS :NODE;
-- VERTIKAL -- VERTIKAL
RAND_OBEN[10..0] :NODE; RAND_OBEN[10..0] :NODE;
VDIS_START[10..0] :NODE; VDIS_START[10..0] :NODE;
@@ -175,20 +176,20 @@ VARIABLE
DOP_ZEI :DFF; DOP_ZEI :DFF;
DOP_FIFO_CLR :DFF; DOP_FIFO_CLR :DFF;
VBE[10..0] :DFFE; VBE[10..0] :DFFE;
VBE_CS :NODE; VBE_CS :NODE;
VDB[10..0] :DFFE; VDB[10..0] :DFFE;
VDB_CS :NODE; VDB_CS :NODE;
VDE[10..0] :DFFE; VDE[10..0] :DFFE;
VDE_CS :NODE; VDE_CS :NODE;
VBB[10..0] :DFFE; VBB[10..0] :DFFE;
VBB_CS :NODE; VBB_CS :NODE;
VSS[10..0] :DFFE; VSS[10..0] :DFFE;
VSS_CS :NODE; VSS_CS :NODE;
VFT[10..0] :DFFE; VFT[10..0] :DFFE;
VFT_CS :NODE; VFT_CS :NODE;
VCO[8..0] :DFFE; VCO[8..0] :DFFE;
VCO_CS :NODE; VCO_CS :NODE;
VCNTRL[3..0] :DFFE; VCNTRL[3..0] :DFFE;
VCNTRL_CS :NODE; VCNTRL_CS :NODE;
@@ -203,26 +204,32 @@ BEGIN
FB_B3 = FB_ADR[1..0] == 3 -- ADR==3 FB_B3 = FB_ADR[1..0] == 3 -- ADR==3
# FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LOW WORD # FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LOW WORD
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE # FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
-- BYT SELECT 16 BIT -- BYT SELECT 16 BIT
FB_16B0 = FB_ADR[0] == 0; -- ADR==0 FB_16B0 = FB_ADR[0] == 0; -- ADR==0
FB_16B1 = FB_ADR[0] == 1 -- ADR==1 FB_16B1 = FB_ADR[0] == 1 -- ADR==1
# !(!FB_SIZE1 & FB_SIZE0); -- NOT BYT # !(!FB_SIZE1 & FB_SIZE0); -- NOT BYT
-- ACP CLUT -- -- ACP CLUT --
ACP_CLUT_CS = !nFB_CS2 & FB_ADR[27..10] == H"0"; -- 0-3FF/1024 ACP_CLUT_CS = !nFB_CS2 & FB_ADR[27..10] == H"0"; -- 0-3FF/1024
ACP_CLUT_RD = ACP_CLUT_CS & !nFB_OE; ACP_CLUT_RD = ACP_CLUT_CS & !nFB_OE;
ACP_CLUT_WR[] = FB_B[] & ACP_CLUT_CS & !nFB_WR; ACP_CLUT_WR[] = FB_B[] & ACP_CLUT_CS & !nFB_WR;
CLUT_TA.CLK = MAIN_CLK; CLUT_TA.CLK = MAIN_CLK;
CLUT_TA = (ACP_CLUT_CS # FALCON_CLUT_CS # ST_CLUT_CS) & !VIDEO_MOD_TA; CLUT_TA = (ACP_CLUT_CS # FALCON_CLUT_CS # ST_CLUT_CS) & !VIDEO_MOD_TA;
--FALCON CLUT -- --FALCON CLUT --
FALCON_CLUT_CS = !nFB_CS1 & FB_ADR[19..10] == H"3E6"; -- $F9800/$400 FALCON_CLUT_CS = !nFB_CS1 & FB_ADR[19..10] == H"3E6"; -- $F9800/$400
FALCON_CLUT_RDH = FALCON_CLUT_CS & !nFB_OE & !FB_ADR1; -- HIGH WORD FALCON_CLUT_RDH = FALCON_CLUT_CS & !nFB_OE & !FB_ADR1; -- HIGH WORD
FALCON_CLUT_RDL = FALCON_CLUT_CS & !nFB_OE & FB_ADR1; -- LOW WORD FALCON_CLUT_RDL = FALCON_CLUT_CS & !nFB_OE & FB_ADR1; -- LOW WORD
FALCON_CLUT_WR[1..0] = FB_16B[] & !FB_ADR1 & FALCON_CLUT_CS & !nFB_WR; FALCON_CLUT_WR[1..0] = FB_16B[] & !FB_ADR1 & FALCON_CLUT_CS & !nFB_WR;
FALCON_CLUT_WR[3..2] = FB_16B[] & FB_ADR1 & FALCON_CLUT_CS & !nFB_WR; FALCON_CLUT_WR[3..2] = FB_16B[] & FB_ADR1 & FALCON_CLUT_CS & !nFB_WR;
-- ST CLUT -- -- ST CLUT --
ST_CLUT_CS = !nFB_CS1 & FB_ADR[19..5] == H"7C12"; -- $F8240/$20 ST_CLUT_CS = !nFB_CS1 & FB_ADR[19..5] == H"7C12"; -- $F8240/$20
ST_CLUT_RD = ST_CLUT_CS & !nFB_OE; ST_CLUT_RD = ST_CLUT_CS & !nFB_OE;
ST_CLUT_WR[] = FB_16B[] & ST_CLUT_CS & !nFB_WR; ST_CLUT_WR[] = FB_16B[] & ST_CLUT_CS & !nFB_WR;
-- ST SHIFT MODE -- ST SHIFT MODE
ST_SHIFT_MODE[].CLK = MAIN_CLK; ST_SHIFT_MODE[].CLK = MAIN_CLK;
ST_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C130"; -- $F8260/2 ST_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C130"; -- $F8260/2
@@ -231,6 +238,7 @@ BEGIN
COLOR1 = ST_SHIFT_MODE[] == B"10" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- MONO COLOR1 = ST_SHIFT_MODE[] == B"10" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- MONO
COLOR2 = ST_SHIFT_MODE[] == B"01" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- 4 FARBEN COLOR2 = ST_SHIFT_MODE[] == B"01" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- 4 FARBEN
COLOR4 = ST_SHIFT_MODE[] == B"00" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- 16 FARBEN COLOR4 = ST_SHIFT_MODE[] == B"00" & !COLOR8 & ST_VIDEO & !ACP_VIDEO_ON; -- 16 FARBEN
-- FALCON SHIFT MODE -- FALCON SHIFT MODE
FALCON_SHIFT_MODE[].CLK = MAIN_CLK; FALCON_SHIFT_MODE[].CLK = MAIN_CLK;
FALCON_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C133"; -- $F8266/2 FALCON_SHIFT_MODE_CS = !nFB_CS1 & FB_ADR[19..1] == H"7C133"; -- $F8266/2

2
FPGA_Quartus_13.1/firebee1.qsf
View File

@@ -368,7 +368,7 @@ set_global_assignment -name FORCE_CONFIGURATION_VCCIO ON
set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL" set_global_assignment -name STRATIX_DEVICE_IO_STANDARD "3.3-V LVTTL"
set_global_assignment -name FITTER_EFFORT "AUTO FIT" set_global_assignment -name FITTER_EFFORT "AUTO FIT"
set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON set_global_assignment -name PHYSICAL_SYNTHESIS_COMBO_LOGIC ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION ON set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_DUPLICATION OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON set_global_assignment -name PHYSICAL_SYNTHESIS_ASYNCHRONOUS_SIGNAL_PIPELINING ON
set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF set_global_assignment -name PHYSICAL_SYNTHESIS_REGISTER_RETIMING OFF
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT NORMAL

8
FPGA_Quartus_13.1/firebee1.sdc
View File

@@ -118,15 +118,17 @@ derive_clock_uncertainty
# Set Input Delay # Set Input Delay
#************************************************************** #**************************************************************
set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 [all_inputs] set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 [get_pins {FB*}]
set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 {nFB_CS1 nFB_CS2 nFB_CS3 nFB_OE}
#************************************************************** #**************************************************************
# Set Output Delay # Set Output Delay
#************************************************************** #**************************************************************
set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 [all_outputs] set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 [get_pins {FB*}]
set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 {nFB_TA}
set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 1.5 [get_pins {VA}]
#************************************************************** #**************************************************************
# Set Clock Groups # Set Clock Groups