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reformat

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This commit is contained in:
Markus Fröschle
2016-01-11 07:13:36 +00:00
parent 9cfde26eef
commit b3edfcd457
4 changed files with 92 additions and 74 deletions
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8
FPGA_Quartus_13.1/firebee1.sdc
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@@ -118,15 +118,17 @@ derive_clock_uncertainty
# Set Input Delay
#**************************************************************
set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 [all_inputs]
set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 [get_pins {FB*}]
set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 {nFB_CS1 nFB_CS2 nFB_CS3 nFB_OE}
#**************************************************************
# Set Output Delay
#**************************************************************
set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 [all_outputs]
set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 [get_pins {FB*}]
set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 {nFB_TA}
set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 1.5 [get_pins {VA}]
#**************************************************************
# Set Clock Groups