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add more DDR clk signals to sdc

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This commit is contained in:
Markus Fröschle
2016-01-11 17:05:39 +00:00
parent 476825a3ba
commit b35e12b329
2 changed files with 1746 additions and 1737 deletions
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1266
FPGA_Quartus_13.1/Video/video.vhd
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11
FPGA_Quartus_13.1/firebee1.sdc
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@@ -131,8 +131,19 @@ set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 1.500 [get_port
set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -min 1.500 {nFB_TA}
set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 [get_ports {FB*}]
set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.500 {nFB_TA}
# the video RAM access
set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 1.500 [get_ports {VA[*]}]
set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 1.500 [get_ports {VA[*]}]
set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 1.500 [get_ports {VD[*]}]
set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 1.500 [get_ports {VD[*]}]
set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 1.500 [get_ports {VDQS[*]}]
set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 1.500 [get_ports {VDQS[*]}]
set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -min 1.500 [get_ports {VDM[*]}]
set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 1.500 [get_ports {VDM[*]}]
set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 1.500 {nVCAS nVRAS nVWE nVCS VCKE DDRCLK nDDRCLK BA[*]}
set_output_delay -add_delay -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -max 1.500 {nVCAS nVRAS nVWE nVCS VCKE DDRCLK nDDRCLK BA[*]}
#**************************************************************
# Set Clock Groups