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Sync with Fredi's source tree 15/04/2017

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IDE and Blitter work.
This commit is contained in:
David Gálvez
2018-04-09 17:21:35 +02:00
parent 68129dbe57
commit b2d17efff1
97 changed files with 9395 additions and 9114 deletions
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FPGA_by_Fredi/Video/lpm_fifo_dc0.cmp
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@@ -1,4 +1,4 @@
--Copyright (C) 1991-2008 Altera Corporation
--Copyright (C) 1991-2010 Altera Corporation
--Your use of Altera Corporation's design tools, logic functions
--and other software and tools, and its AMPP partner logic
--functions, and any output files from any of the foregoing
@@ -23,7 +23,6 @@ component lpm_fifo_dc0
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
q : OUT STD_LOGIC_VECTOR (127 DOWNTO 0);
rdempty : OUT STD_LOGIC ;
wrusedw : OUT STD_LOGIC_VECTOR (8 DOWNTO 0)
wrusedw : OUT STD_LOGIC_VECTOR (10 DOWNTO 0)
);
end component;