forked from Firebee/FPGA_Config
Sync with Fredi's source tree 15/04/2017
IDE and Blitter work.
This commit is contained in:
David Gálvez
@@ -1,110 +0,0 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2010 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.1"))
|
||||
(symbol
|
||||
(rect 0 0 256 128)
|
||||
(text "altsyncram0" (rect 84 2 187 21)(font "Arial" (font_size 10)))
|
||||
(text "inst" (rect 8 109 31 124)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 32)
|
||||
(input)
|
||||
(text "data[15..0]" (rect 0 0 73 16)(font "Arial" (font_size 8)))
|
||||
(text "data[15..0]" (rect 4 16 66 32)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 32)(pt 112 32)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 48)
|
||||
(input)
|
||||
(text "address[3..0]" (rect 0 0 89 16)(font "Arial" (font_size 8)))
|
||||
(text "address[3..0]" (rect 4 32 80 48)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 48)(pt 112 48)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 64)
|
||||
(input)
|
||||
(text "wren" (rect 0 0 31 16)(font "Arial" (font_size 8)))
|
||||
(text "wren" (rect 4 48 31 64)(font "Arial" (font_size 8)))
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||||
(line (pt 0 64)(pt 112 64)(line_width 1))
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||||
)
|
||||
(port
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||||
(pt 0 88)
|
||||
(input)
|
||||
(text "byteena_a[1..0]" (rect 0 0 106 16)(font "Arial" (font_size 8)))
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||||
(text "byteena_a[1..0]" (rect 4 72 94 88)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 88)(pt 112 88)(line_width 3))
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||||
)
|
||||
(port
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||||
(pt 0 104)
|
||||
(input)
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||||
(text "clock" (rect 0 0 36 16)(font "Arial" (font_size 8)))
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||||
(text "clock" (rect 4 88 35 104)(font "Arial" (font_size 8)))
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||||
(line (pt 0 104)(pt 104 104)(line_width 1))
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||||
)
|
||||
(port
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||||
(pt 256 32)
|
||||
(output)
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||||
(text "q[15..0]" (rect 0 0 51 16)(font "Arial" (font_size 8)))
|
||||
(text "q[15..0]" (rect 209 16 253 32)(font "Arial" (font_size 8)))
|
||||
(line (pt 256 32)(pt 168 32)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(text "16 Word(s)" (rect 133 35 147 90)(font "Arial" )(vertical))
|
||||
(text "RAM" (rect 149 49 163 72)(font "Arial" )(vertical))
|
||||
(text "Block Type: AUTO" (rect 41 106 129 120)(font "Arial" ))
|
||||
(line (pt 128 24)(pt 168 24)(line_width 1))
|
||||
(line (pt 168 24)(pt 168 96)(line_width 1))
|
||||
(line (pt 168 96)(pt 128 96)(line_width 1))
|
||||
(line (pt 128 96)(pt 128 24)(line_width 1))
|
||||
(line (pt 112 27)(pt 120 27)(line_width 1))
|
||||
(line (pt 120 27)(pt 120 39)(line_width 1))
|
||||
(line (pt 120 39)(pt 112 39)(line_width 1))
|
||||
(line (pt 112 39)(pt 112 27)(line_width 1))
|
||||
(line (pt 112 34)(pt 114 36)(line_width 1))
|
||||
(line (pt 114 36)(pt 112 38)(line_width 1))
|
||||
(line (pt 104 36)(pt 112 36)(line_width 1))
|
||||
(line (pt 120 32)(pt 128 32)(line_width 3))
|
||||
(line (pt 112 43)(pt 120 43)(line_width 1))
|
||||
(line (pt 120 43)(pt 120 55)(line_width 1))
|
||||
(line (pt 120 55)(pt 112 55)(line_width 1))
|
||||
(line (pt 112 55)(pt 112 43)(line_width 1))
|
||||
(line (pt 112 50)(pt 114 52)(line_width 1))
|
||||
(line (pt 114 52)(pt 112 54)(line_width 1))
|
||||
(line (pt 104 52)(pt 112 52)(line_width 1))
|
||||
(line (pt 120 48)(pt 128 48)(line_width 3))
|
||||
(line (pt 112 59)(pt 120 59)(line_width 1))
|
||||
(line (pt 120 59)(pt 120 71)(line_width 1))
|
||||
(line (pt 120 71)(pt 112 71)(line_width 1))
|
||||
(line (pt 112 71)(pt 112 59)(line_width 1))
|
||||
(line (pt 112 66)(pt 114 68)(line_width 1))
|
||||
(line (pt 114 68)(pt 112 70)(line_width 1))
|
||||
(line (pt 104 68)(pt 112 68)(line_width 1))
|
||||
(line (pt 120 64)(pt 128 64)(line_width 1))
|
||||
(line (pt 112 83)(pt 120 83)(line_width 1))
|
||||
(line (pt 120 83)(pt 120 95)(line_width 1))
|
||||
(line (pt 120 95)(pt 112 95)(line_width 1))
|
||||
(line (pt 112 95)(pt 112 83)(line_width 1))
|
||||
(line (pt 112 90)(pt 114 92)(line_width 1))
|
||||
(line (pt 114 92)(pt 112 94)(line_width 1))
|
||||
(line (pt 104 92)(pt 112 92)(line_width 1))
|
||||
(line (pt 120 88)(pt 128 88)(line_width 3))
|
||||
(line (pt 104 36)(pt 104 105)(line_width 1))
|
||||
)
|
||||
)
|
||||
@@ -1,26 +0,0 @@
|
||||
--Copyright (C) 1991-2010 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
component altsyncram0
|
||||
PORT
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||||
(
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||||
address : IN STD_LOGIC_VECTOR (3 DOWNTO 0);
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byteena_a : IN STD_LOGIC_VECTOR (1 DOWNTO 0) := (OTHERS => '1');
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clock : IN STD_LOGIC := '1';
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||||
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
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wren : IN STD_LOGIC := '0';
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||||
q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0)
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||||
);
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||||
end component;
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||||
@@ -15,13 +15,18 @@
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||||
FUNCTION altsyncram0
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||||
(
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||||
address[3..0],
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||||
address_a[3..0],
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||||
address_b[3..0],
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||||
byteena_a[1..0],
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||||
clock,
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data[15..0],
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||||
wren
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||||
clock_a,
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||||
clock_b,
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||||
data_a[15..0],
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||||
data_b[15..0],
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wren_a,
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wren_b
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||||
)
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RETURNS (
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q[15..0]
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||||
q_a[15..0],
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q_b[15..0]
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);
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||||
|
||||
@@ -1,6 +1,4 @@
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set_global_assignment -name IP_TOOL_NAME "ALTSYNCRAM"
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set_global_assignment -name IP_TOOL_VERSION "9.1"
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||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altsyncram0.tdf"]
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set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altsyncram0.bsf"]
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set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altsyncram0.inc"]
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set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altsyncram0.cmp"]
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||||
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@@ -38,43 +38,63 @@ INCLUDE "altsyncram.inc";
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SUBDESIGN altsyncram0
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(
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address[3..0] : INPUT;
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||||
address_a[3..0] : INPUT;
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||||
address_b[3..0] : INPUT;
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byteena_a[1..0] : INPUT = VCC;
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clock : INPUT = VCC;
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||||
data[15..0] : INPUT;
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||||
wren : INPUT = GND;
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||||
q[15..0] : OUTPUT;
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||||
clock_a : INPUT = VCC;
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||||
clock_b : INPUT;
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||||
data_a[15..0] : INPUT;
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||||
data_b[15..0] : INPUT;
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||||
wren_a : INPUT = GND;
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wren_b : INPUT = GND;
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||||
q_a[15..0] : OUTPUT;
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||||
q_b[15..0] : OUTPUT;
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)
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VARIABLE
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altsyncram_component : altsyncram WITH (
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||||
ADDRESS_REG_B = "CLOCK1",
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||||
BYTE_SIZE = 8,
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CLOCK_ENABLE_INPUT_A = "BYPASS",
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||||
CLOCK_ENABLE_INPUT_B = "BYPASS",
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||||
CLOCK_ENABLE_OUTPUT_A = "BYPASS",
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||||
CLOCK_ENABLE_OUTPUT_B = "BYPASS",
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||||
INDATA_REG_B = "CLOCK1",
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||||
INTENDED_DEVICE_FAMILY = "Cyclone III",
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||||
LPM_HINT = "ENABLE_RUNTIME_MOD=NO",
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||||
LPM_TYPE = "altsyncram",
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||||
NUMWORDS_A = 16,
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||||
OPERATION_MODE = "SINGLE_PORT",
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||||
NUMWORDS_B = 16,
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||||
OPERATION_MODE = "BIDIR_DUAL_PORT",
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||||
OUTDATA_ACLR_A = "NONE",
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||||
OUTDATA_ACLR_B = "NONE",
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||||
OUTDATA_REG_A = "UNREGISTERED",
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||||
OUTDATA_REG_B = "UNREGISTERED",
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||||
POWER_UP_UNINITIALIZED = "FALSE",
|
||||
READ_DURING_WRITE_MODE_PORT_A = "NEW_DATA_WITH_NBE_READ",
|
||||
READ_DURING_WRITE_MODE_PORT_B = "NEW_DATA_WITH_NBE_READ",
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||||
WIDTHAD_A = 4,
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||||
WIDTHAD_B = 4,
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||||
WIDTH_A = 16,
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||||
WIDTH_BYTEENA_A = 2
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||||
WIDTH_B = 16,
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||||
WIDTH_BYTEENA_A = 2,
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||||
WIDTH_BYTEENA_B = 1,
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||||
WRCONTROL_WRADDRESS_REG_B = "CLOCK1"
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||||
);
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||||
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||||
BEGIN
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||||
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||||
q[15..0] = altsyncram_component.q_a[15..0];
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altsyncram_component.wren_a = wren;
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||||
altsyncram_component.clock0 = clock;
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||||
q_a[15..0] = altsyncram_component.q_a[15..0];
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q_b[15..0] = altsyncram_component.q_b[15..0];
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altsyncram_component.wren_a = wren_a;
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altsyncram_component.clock0 = clock_a;
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||||
altsyncram_component.wren_b = wren_b;
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||||
altsyncram_component.clock1 = clock_b;
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||||
altsyncram_component.byteena_a[1..0] = byteena_a[1..0];
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||||
altsyncram_component.address_a[3..0] = address[3..0];
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||||
altsyncram_component.data_a[15..0] = data[15..0];
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||||
altsyncram_component.address_a[3..0] = address_a[3..0];
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||||
altsyncram_component.address_b[3..0] = address_b[3..0];
|
||||
altsyncram_component.data_a[15..0] = data_a[15..0];
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||||
altsyncram_component.data_b[15..0] = data_b[15..0];
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||||
END;
|
||||
|
||||
|
||||
@@ -100,13 +120,13 @@ END;
|
||||
-- Retrieval info: PRIVATE: CLRrren NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: CLRwraddress NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: CLRwren NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: Clock NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: Clock NUMERIC "5"
|
||||
-- Retrieval info: PRIVATE: Clock_A NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: Clock_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: ECC NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: IMPLEMENT_IN_LES NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: INDATA_ACLR_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: INDATA_REG_B NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: INIT_FILE_LAYOUT STRING "PORT_A"
|
||||
-- Retrieval info: PRIVATE: INIT_TO_SIM_X NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
@@ -116,17 +136,17 @@ END;
|
||||
-- Retrieval info: PRIVATE: MEMSIZE NUMERIC "256"
|
||||
-- Retrieval info: PRIVATE: MEM_IN_BITS NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: MIFfilename STRING ""
|
||||
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: OPERATION_MODE NUMERIC "3"
|
||||
-- Retrieval info: PRIVATE: OUTDATA_ACLR_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: OUTDATA_REG_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_MIXED_PORTS NUMERIC "2"
|
||||
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_A NUMERIC "4"
|
||||
-- Retrieval info: PRIVATE: READ_DURING_WRITE_MODE_PORT_B NUMERIC "4"
|
||||
-- Retrieval info: PRIVATE: REGdata NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: REGq NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: REGrren NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: REGrdaddress NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: REGrren NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: REGwraddress NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: REGwren NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
@@ -138,44 +158,64 @@ END;
|
||||
-- Retrieval info: PRIVATE: WIDTH_WRITE_A NUMERIC "16"
|
||||
-- Retrieval info: PRIVATE: WIDTH_WRITE_B NUMERIC "16"
|
||||
-- Retrieval info: PRIVATE: WRADDR_ACLR_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: WRADDR_REG_B NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: WRCTRL_ACLR_B NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: enable NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: rden NUMERIC "0"
|
||||
-- Retrieval info: CONSTANT: ADDRESS_REG_B STRING "CLOCK1"
|
||||
-- Retrieval info: CONSTANT: BYTE_SIZE NUMERIC "8"
|
||||
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_A STRING "BYPASS"
|
||||
-- Retrieval info: CONSTANT: CLOCK_ENABLE_INPUT_B STRING "BYPASS"
|
||||
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_A STRING "BYPASS"
|
||||
-- Retrieval info: CONSTANT: CLOCK_ENABLE_OUTPUT_B STRING "BYPASS"
|
||||
-- Retrieval info: CONSTANT: INDATA_REG_B STRING "CLOCK1"
|
||||
-- Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
-- Retrieval info: CONSTANT: LPM_HINT STRING "ENABLE_RUNTIME_MOD=NO"
|
||||
-- Retrieval info: CONSTANT: LPM_TYPE STRING "altsyncram"
|
||||
-- Retrieval info: CONSTANT: NUMWORDS_A NUMERIC "16"
|
||||
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "SINGLE_PORT"
|
||||
-- Retrieval info: CONSTANT: NUMWORDS_B NUMERIC "16"
|
||||
-- Retrieval info: CONSTANT: OPERATION_MODE STRING "BIDIR_DUAL_PORT"
|
||||
-- Retrieval info: CONSTANT: OUTDATA_ACLR_A STRING "NONE"
|
||||
-- Retrieval info: CONSTANT: OUTDATA_ACLR_B STRING "NONE"
|
||||
-- Retrieval info: CONSTANT: OUTDATA_REG_A STRING "UNREGISTERED"
|
||||
-- Retrieval info: CONSTANT: OUTDATA_REG_B STRING "UNREGISTERED"
|
||||
-- Retrieval info: CONSTANT: POWER_UP_UNINITIALIZED STRING "FALSE"
|
||||
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_A STRING "NEW_DATA_WITH_NBE_READ"
|
||||
-- Retrieval info: CONSTANT: READ_DURING_WRITE_MODE_PORT_B STRING "NEW_DATA_WITH_NBE_READ"
|
||||
-- Retrieval info: CONSTANT: WIDTHAD_A NUMERIC "4"
|
||||
-- Retrieval info: CONSTANT: WIDTHAD_B NUMERIC "4"
|
||||
-- Retrieval info: CONSTANT: WIDTH_A NUMERIC "16"
|
||||
-- Retrieval info: CONSTANT: WIDTH_B NUMERIC "16"
|
||||
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_A NUMERIC "2"
|
||||
-- Retrieval info: USED_PORT: address 0 0 4 0 INPUT NODEFVAL address[3..0]
|
||||
-- Retrieval info: CONSTANT: WIDTH_BYTEENA_B NUMERIC "1"
|
||||
-- Retrieval info: CONSTANT: WRCONTROL_WRADDRESS_REG_B STRING "CLOCK1"
|
||||
-- Retrieval info: USED_PORT: address_a 0 0 4 0 INPUT NODEFVAL address_a[3..0]
|
||||
-- Retrieval info: USED_PORT: address_b 0 0 4 0 INPUT NODEFVAL address_b[3..0]
|
||||
-- Retrieval info: USED_PORT: byteena_a 0 0 2 0 INPUT VCC byteena_a[1..0]
|
||||
-- Retrieval info: USED_PORT: clock 0 0 0 0 INPUT VCC clock
|
||||
-- Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
|
||||
-- Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
|
||||
-- Retrieval info: USED_PORT: wren 0 0 0 0 INPUT GND wren
|
||||
-- Retrieval info: CONNECT: @data_a 0 0 16 0 data 0 0 16 0
|
||||
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren 0 0 0 0
|
||||
-- Retrieval info: CONNECT: q 0 0 16 0 @q_a 0 0 16 0
|
||||
-- Retrieval info: CONNECT: @address_a 0 0 4 0 address 0 0 4 0
|
||||
-- Retrieval info: USED_PORT: clock_a 0 0 0 0 INPUT VCC clock_a
|
||||
-- Retrieval info: USED_PORT: clock_b 0 0 0 0 INPUT NODEFVAL clock_b
|
||||
-- Retrieval info: USED_PORT: data_a 0 0 16 0 INPUT NODEFVAL data_a[15..0]
|
||||
-- Retrieval info: USED_PORT: data_b 0 0 16 0 INPUT NODEFVAL data_b[15..0]
|
||||
-- Retrieval info: USED_PORT: q_a 0 0 16 0 OUTPUT NODEFVAL q_a[15..0]
|
||||
-- Retrieval info: USED_PORT: q_b 0 0 16 0 OUTPUT NODEFVAL q_b[15..0]
|
||||
-- Retrieval info: USED_PORT: wren_a 0 0 0 0 INPUT GND wren_a
|
||||
-- Retrieval info: USED_PORT: wren_b 0 0 0 0 INPUT GND wren_b
|
||||
-- Retrieval info: CONNECT: @data_a 0 0 16 0 data_a 0 0 16 0
|
||||
-- Retrieval info: CONNECT: @wren_a 0 0 0 0 wren_a 0 0 0 0
|
||||
-- Retrieval info: CONNECT: q_a 0 0 16 0 @q_a 0 0 16 0
|
||||
-- Retrieval info: CONNECT: q_b 0 0 16 0 @q_b 0 0 16 0
|
||||
-- Retrieval info: CONNECT: @address_a 0 0 4 0 address_a 0 0 4 0
|
||||
-- Retrieval info: CONNECT: @data_b 0 0 16 0 data_b 0 0 16 0
|
||||
-- Retrieval info: CONNECT: @address_b 0 0 4 0 address_b 0 0 4 0
|
||||
-- Retrieval info: CONNECT: @wren_b 0 0 0 0 wren_b 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @byteena_a 0 0 2 0 byteena_a 0 0 2 0
|
||||
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @clock0 0 0 0 0 clock_a 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @clock1 0 0 0 0 clock_b 0 0 0 0
|
||||
-- Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0.tdf TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0.inc TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0.cmp TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0.bsf TRUE FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0.cmp FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0.bsf FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0_inst.tdf FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0_waveforms.html TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0_waveforms.html FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altsyncram0_wave*.jpg FALSE
|
||||
-- Retrieval info: LIB_FILE: altera_mf
|
||||
|
||||
Binary file not shown.
|
Before Width: | Height: | Size: 88 KiB |
@@ -1,13 +0,0 @@
|
||||
<html>
|
||||
<head>
|
||||
<title>Sample Waveforms for "altsyncram0.tdf" </title>
|
||||
</head>
|
||||
<body>
|
||||
<h2><CENTER>Sample behavioral waveforms for design file "altsyncram0.tdf" </CENTER></h2>
|
||||
<P>The following waveforms show the behavior of altsyncram megafunction for the chosen set of parameters in design "altsyncram0.tdf". For the purpose of this simulation, the contents of the memory at the start of the sample waveforms is assumed to be ( FFF0, FFF1, FFF2, FFF3, ...). The design "altsyncram0.tdf" has </P>
|
||||
<CENTER><img src=altsyncram0_wave0.jpg> </CENTER>
|
||||
<P><CENTER><FONT size=2>Fig. 1 : Wave showing read operation. </CENTER></P>
|
||||
<P><FONT size=3>The above waveform shows the behavior of the design under normal read conditions. The read happens at the rising edge of the enabled clock cycle. The output from the RAM is undefined until after the first rising edge of the read clock. </P>
|
||||
<P></P>
|
||||
</body>
|
||||
</html>
|
||||
@@ -1,427 +0,0 @@
|
||||
-- WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
-- editor if you plan to continue editing the block that represents it in
|
||||
-- the Block Editor! File corruption is VERY likely to occur.
|
||||
|
||||
-- Copyright (C) 1991-2010 Altera Corporation
|
||||
-- Your use of Altera Corporation's design tools, logic functions
|
||||
-- and other software and tools, and its AMPP partner logic
|
||||
-- functions, and any output files from any of the foregoing
|
||||
-- (including device programming or simulation files), and any
|
||||
-- associated documentation or information are expressly subject
|
||||
-- to the terms and conditions of the Altera Program License
|
||||
-- Subscription Agreement, Altera MegaCore Function License
|
||||
-- Agreement, or other applicable license agreement, including,
|
||||
-- without limitation, that your use is for the sole purpose of
|
||||
-- programming logic devices manufactured by Altera and sold by
|
||||
-- Altera or its authorized distributors. Please refer to the
|
||||
-- applicable agreement for further details.
|
||||
|
||||
|
||||
-- Generated by Quartus II Version 9.1 (Build Build 350 03/24/2010)
|
||||
-- Created on Sat Jan 15 11:06:17 2011
|
||||
INCLUDE "lpm_bustri_WORD.inc";
|
||||
INCLUDE "VIDEO/BLITTER/lpm_clshift0.INC";
|
||||
|
||||
CONSTANT BL_SKEW_LF = 255;
|
||||
|
||||
-- Title Statement (optional)
|
||||
TITLE "Blitter";
|
||||
|
||||
|
||||
-- Parameters Statement (optional)
|
||||
|
||||
-- {{ALTERA_PARAMETERS_BEGIN}} DO NOT REMOVE THIS LINE!
|
||||
-- {{ALTERA_PARAMETERS_END}} DO NOT REMOVE THIS LINE!
|
||||
|
||||
|
||||
-- Subdesign Section
|
||||
|
||||
SUBDESIGN BLITTER
|
||||
(
|
||||
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
|
||||
nRSTO : INPUT;
|
||||
MAIN_CLK : INPUT;
|
||||
FB_ALE : INPUT;
|
||||
nFB_WR : INPUT;
|
||||
nFB_OE : INPUT;
|
||||
FB_SIZE0 : INPUT;
|
||||
FB_SIZE1 : INPUT;
|
||||
VIDEO_RAM_CTR[15..0] : INPUT;
|
||||
BLITTER_ON : INPUT;
|
||||
FB_ADR[31..0] : INPUT;
|
||||
nFB_CS1 : INPUT;
|
||||
nFB_CS2 : INPUT;
|
||||
nFB_CS3 : INPUT;
|
||||
DDRCLK0 : INPUT;
|
||||
BLITTER_DIN[127..0] : INPUT;
|
||||
BLITTER_DACK[4..0] : INPUT;
|
||||
SR_BLITTER_DACK : INPUT;
|
||||
BLITTER_RUN : OUTPUT;
|
||||
BLITTER_DOUT[127..0] : OUTPUT;
|
||||
BLITTER_ADR[31..0] : OUTPUT;
|
||||
BLITTER_SIG : OUTPUT;
|
||||
BLITTER_WR : OUTPUT;
|
||||
BLITTER_TA : OUTPUT;
|
||||
FB_AD[31..0] : BIDIR;
|
||||
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
|
||||
)
|
||||
|
||||
VARIABLE
|
||||
FB_B[3..0] :NODE;
|
||||
FB_16B[1..0] :NODE;
|
||||
BLITTER_CS :NODE;
|
||||
BL_HRAM0_CS :NODE;
|
||||
BL_HRAM0[15..0] :DFFE;
|
||||
BL_HRAM1_CS :NODE;
|
||||
BL_HRAM1[15..0] :DFFE;
|
||||
BL_HRAM2_CS :NODE;
|
||||
BL_HRAM2[15..0] :DFFE;
|
||||
BL_HRAM3_CS :NODE;
|
||||
BL_HRAM3[15..0] :DFFE;
|
||||
BL_HRAM4_CS :NODE;
|
||||
BL_HRAM4[15..0] :DFFE;
|
||||
BL_HRAM5_CS :NODE;
|
||||
BL_HRAM5[15..0] :DFFE;
|
||||
BL_HRAM6_CS :NODE;
|
||||
BL_HRAM6[15..0] :DFFE;
|
||||
BL_HRAM7_CS :NODE;
|
||||
BL_HRAM7[15..0] :DFFE;
|
||||
BL_HRAM8_CS :NODE;
|
||||
BL_HRAM8[15..0] :DFFE;
|
||||
BL_HRAM9_CS :NODE;
|
||||
BL_HRAM9[15..0] :DFFE;
|
||||
BL_HRAMA_CS :NODE;
|
||||
BL_HRAMA[15..0] :DFFE;
|
||||
BL_HRAMB_CS :NODE;
|
||||
BL_HRAMB[15..0] :DFFE;
|
||||
BL_HRAMC_CS :NODE;
|
||||
BL_HRAMC[15..0] :DFFE;
|
||||
BL_HRAMD_CS :NODE;
|
||||
BL_HRAMD[15..0] :DFFE;
|
||||
BL_HRAME_CS :NODE;
|
||||
BL_HRAME[15..0] :DFFE;
|
||||
BL_HRAMF_CS :NODE;
|
||||
BL_HRAMF[15..0] :DFFE;
|
||||
BL_SRC_X_INC_CS :NODE;
|
||||
BL_SRC_X_INC[15..0] :DFFE;
|
||||
BL_SRC_Y_INC_CS :NODE;
|
||||
BL_SRC_Y_INC[15..0] :DFFE;
|
||||
BL_ENDMASK1_CS :NODE;
|
||||
BL_ENDMASK1[15..0] :DFFE;
|
||||
BL_ENDMASK2_CS :NODE;
|
||||
BL_ENDMASK2[15..0] :DFFE;
|
||||
BL_ENDMASK3_CS :NODE;
|
||||
BL_ENDMASK3[15..0] :DFFE;
|
||||
BL_SRC_ADRH_CS :NODE;
|
||||
BL_SRC_ADRL_CS :NODE;
|
||||
BL_SRC_ADR[31..0] :DFFE;
|
||||
BL_DST_X_INC_CS :NODE;
|
||||
BL_DST_X_INC[15..0] :DFFE;
|
||||
BL_DST_Y_INC_CS :NODE;
|
||||
BL_DST_Y_INC[15..0] :DFFE;
|
||||
BL_DST_ADRH_CS :NODE;
|
||||
BL_DST_ADRL_CS :NODE;
|
||||
BL_DST_ADR[31..0] :DFFE;
|
||||
BL_X_CNT_CS :NODE;
|
||||
BL_X_CNT[15..0] :DFFE;
|
||||
BL_Y_CNT_CS :NODE;
|
||||
BL_Y_CNT[15..0] :DFFE;
|
||||
BL_HT_OP_CS :NODE;
|
||||
BL_HT_OP[7..0] :DFFE;
|
||||
BL_LC_OP[7..0] :DFFE;
|
||||
BL_LN_CS :NODE;
|
||||
BL_LN[7..0] :DFFE;
|
||||
BL_SKEW[7..0] :DFFE;
|
||||
|
||||
BL_SKEW_EXT[6..0] :NODE;
|
||||
BL_SKEW_IN[255..0] :DFFE;
|
||||
BL_SKEW_OUT[255..0] :DFFE;
|
||||
|
||||
BL_DATA_DDR_READY :DFF; -- 1 WENN DATEN GESCHRIEBEN ODER LESBAR
|
||||
BL_READ_SRC :DFFE;
|
||||
BL_DST_BUFFER[127..0] :DFFE;
|
||||
BL_READ_DST :DFFE;
|
||||
|
||||
COUNT[18..0] :DFF;
|
||||
|
||||
BEGIN
|
||||
-- BYT SELECT 32 BIT
|
||||
FB_B0 = FB_ADR[1..0]==0; -- ADR==0
|
||||
FB_B1 = FB_ADR[1..0]==1 -- ADR==1
|
||||
# FB_SIZE1 & !FB_SIZE0 & !FB_ADR1 -- HIGH WORD
|
||||
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
|
||||
FB_B2 = FB_ADR[1..0]==2 -- ADR==2
|
||||
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
|
||||
FB_B3 = FB_ADR[1..0]==3 -- ADR==3
|
||||
# FB_SIZE1 & !FB_SIZE0 & FB_ADR1 -- LOW WORD
|
||||
# FB_SIZE1 & FB_SIZE0 # !FB_SIZE1 & !FB_SIZE0; -- LONG UND LINE
|
||||
-- BYT SELECT 16 BIT
|
||||
FB_16B0 = FB_ADR[0]==0; -- ADR==0
|
||||
FB_16B1 = FB_ADR[0]==1 -- ADR==1
|
||||
# !(!FB_SIZE1 & FB_SIZE0); -- NOT BYT
|
||||
-- BLITTER CS
|
||||
BLITTER_CS = !nFB_CS1 & FB_ADR[19..6]==H"3E28"; -- FFFF8A00-3F/40
|
||||
BLITTER_TA = BLITTER_CS;
|
||||
-- REGISTER
|
||||
-- HALFTON RAM 0
|
||||
BL_HRAM0[].CLK = MAIN_CLK;
|
||||
BL_HRAM0[15..0] = FB_AD[31..16];
|
||||
BL_HRAM0_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C500"; -- $F8A00/2
|
||||
BL_HRAM0[15..8].ENA = BL_HRAM0_CS & !nFB_WR & FB_16B0;
|
||||
BL_HRAM0[7..0].ENA = BL_HRAM0_CS & !nFB_WR & FB_16B1;
|
||||
-- HALFTON RAM 1
|
||||
BL_HRAM1[].CLK = MAIN_CLK;
|
||||
BL_HRAM1[15..0] = FB_AD[31..16];
|
||||
BL_HRAM1_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C501"; -- $F8A02/2
|
||||
BL_HRAM1[15..8].ENA = BL_HRAM1_CS & !nFB_WR & FB_16B0;
|
||||
BL_HRAM1[7..0].ENA = BL_HRAM1_CS & !nFB_WR & FB_16B1;
|
||||
-- HALFTON RAM 2
|
||||
BL_HRAM2[].CLK = MAIN_CLK;
|
||||
BL_HRAM2[15..0] = FB_AD[31..16];
|
||||
BL_HRAM2_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C502"; -- $F8A04/2
|
||||
BL_HRAM2[15..8].ENA = BL_HRAM2_CS & !nFB_WR & FB_16B0;
|
||||
BL_HRAM2[7..0].ENA = BL_HRAM2_CS & !nFB_WR & FB_16B1;
|
||||
-- HALFTON RAM 3
|
||||
BL_HRAM3[].CLK = MAIN_CLK;
|
||||
BL_HRAM3[15..0] = FB_AD[31..16];
|
||||
BL_HRAM3_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C503"; -- $F8A06/2
|
||||
BL_HRAM3[15..8].ENA = BL_HRAM3_CS & !nFB_WR & FB_16B0;
|
||||
BL_HRAM3[7..0].ENA = BL_HRAM3_CS & !nFB_WR & FB_16B1;
|
||||
-- HALFTON RAM 4
|
||||
BL_HRAM4[].CLK = MAIN_CLK;
|
||||
BL_HRAM4[15..0] = FB_AD[31..16];
|
||||
BL_HRAM4_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C504"; -- $F8A08/2
|
||||
BL_HRAM4[15..8].ENA = BL_HRAM4_CS & !nFB_WR & FB_16B0;
|
||||
BL_HRAM4[7..0].ENA = BL_HRAM4_CS & !nFB_WR & FB_16B1;
|
||||
-- HALFTON RAM 5
|
||||
BL_HRAM5[].CLK = MAIN_CLK;
|
||||
BL_HRAM5[15..0] = FB_AD[31..16];
|
||||
BL_HRAM5_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C505"; -- $F8A08/2
|
||||
BL_HRAM5[15..8].ENA = BL_HRAM5_CS & !nFB_WR & FB_16B0;
|
||||
BL_HRAM5[7..0].ENA = BL_HRAM5_CS & !nFB_WR & FB_16B1;
|
||||
-- HALFTON RAM 6
|
||||
BL_HRAM6[].CLK = MAIN_CLK;
|
||||
BL_HRAM6[15..0] = FB_AD[31..16];
|
||||
BL_HRAM6_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C506"; -- $F8A08/2
|
||||
BL_HRAM6[15..8].ENA = BL_HRAM6_CS & !nFB_WR & FB_16B0;
|
||||
BL_HRAM6[7..0].ENA = BL_HRAM6_CS & !nFB_WR & FB_16B1;
|
||||
-- HALFTON RAM 7
|
||||
BL_HRAM7[].CLK = MAIN_CLK;
|
||||
BL_HRAM7[15..0] = FB_AD[31..16];
|
||||
BL_HRAM7_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C507"; -- $F8A08/2
|
||||
BL_HRAM7[15..8].ENA = BL_HRAM7_CS & !nFB_WR & FB_16B0;
|
||||
BL_HRAM7[7..0].ENA = BL_HRAM7_CS & !nFB_WR & FB_16B1;
|
||||
-- HALFTON RAM 8
|
||||
BL_HRAM8[].CLK = MAIN_CLK;
|
||||
BL_HRAM8[15..0] = FB_AD[31..16];
|
||||
BL_HRAM8_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C508"; -- $F8A10/2
|
||||
BL_HRAM8[15..8].ENA = BL_HRAM8_CS & !nFB_WR & FB_16B0;
|
||||
BL_HRAM8[7..0].ENA = BL_HRAM8_CS & !nFB_WR & FB_16B1;
|
||||
-- HALFTON RAM 9
|
||||
BL_HRAM9[].CLK = MAIN_CLK;
|
||||
BL_HRAM9[15..0] = FB_AD[31..16];
|
||||
BL_HRAM9_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C509"; -- $F8A12/2
|
||||
BL_HRAM9[15..8].ENA = BL_HRAM9_CS & !nFB_WR & FB_16B0;
|
||||
BL_HRAM9[7..0].ENA = BL_HRAM9_CS & !nFB_WR & FB_16B1;
|
||||
-- HALFTON RAM 10
|
||||
BL_HRAMA[].CLK = MAIN_CLK;
|
||||
BL_HRAMA[15..0] = FB_AD[31..16];
|
||||
BL_HRAMA_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C50A"; -- $F8A4/2
|
||||
BL_HRAMA[15..8].ENA = BL_HRAMA_CS & !nFB_WR & FB_16B0;
|
||||
BL_HRAMA[7..0].ENA = BL_HRAMA_CS & !nFB_WR & FB_16B1;
|
||||
-- HALFTON RAM 11
|
||||
BL_HRAMB[].CLK = MAIN_CLK;
|
||||
BL_HRAMB[15..0] = FB_AD[31..16];
|
||||
BL_HRAMB_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C50B"; -- $F8A16/2
|
||||
BL_HRAMB[15..8].ENA = BL_HRAMB_CS & !nFB_WR & FB_16B0;
|
||||
BL_HRAMB[7..0].ENA = BL_HRAMB_CS & !nFB_WR & FB_16B1;
|
||||
-- HALFTON RAM 12
|
||||
BL_HRAMC[].CLK = MAIN_CLK;
|
||||
BL_HRAMC[15..0] = FB_AD[31..16];
|
||||
BL_HRAMC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C50C"; -- $F8A18/2
|
||||
BL_HRAMC[15..8].ENA = BL_HRAMC_CS & !nFB_WR & FB_16B0;
|
||||
BL_HRAMC[7..0].ENA = BL_HRAMC_CS & !nFB_WR & FB_16B1;
|
||||
-- HALFTON RAM 13
|
||||
BL_HRAMD[].CLK = MAIN_CLK;
|
||||
BL_HRAMD[15..0] = FB_AD[31..16];
|
||||
BL_HRAMD_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C50D"; -- $F8A1A/2
|
||||
BL_HRAMD[15..8].ENA = BL_HRAMD_CS & !nFB_WR & FB_16B0;
|
||||
BL_HRAMD[7..0].ENA = BL_HRAMD_CS & !nFB_WR & FB_16B1;
|
||||
-- HALFTON RAM 14
|
||||
BL_HRAME[].CLK = MAIN_CLK;
|
||||
BL_HRAME[15..0] = FB_AD[31..16];
|
||||
BL_HRAME_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C50E"; -- $F8A1C/2
|
||||
BL_HRAME[15..8].ENA = BL_HRAME_CS & !nFB_WR & FB_16B0;
|
||||
BL_HRAME[7..0].ENA = BL_HRAME_CS & !nFB_WR & FB_16B1;
|
||||
-- HALFTON RAM 15
|
||||
BL_HRAMF[].CLK = MAIN_CLK;
|
||||
BL_HRAMF[15..0] = FB_AD[31..16];
|
||||
BL_HRAMF_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C50F"; -- $F8A1E/2
|
||||
BL_HRAMF[15..8].ENA = BL_HRAMF_CS & !nFB_WR & FB_16B0;
|
||||
BL_HRAMF[7..0].ENA = BL_HRAMF_CS & !nFB_WR & FB_16B1;
|
||||
-- SRC X INC
|
||||
BL_SRC_X_INC[].CLK = MAIN_CLK;
|
||||
BL_SRC_X_INC[] = FB_AD[31..16];
|
||||
BL_SRC_X_INC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C510"; -- $F8A20/2
|
||||
BL_SRC_X_INC[15..8].ENA = BL_SRC_X_INC_CS & !nFB_WR & FB_16B0;
|
||||
BL_SRC_X_INC[7..0].ENA = BL_SRC_X_INC_CS & !nFB_WR & FB_16B1;
|
||||
-- SRC Y INC
|
||||
BL_SRC_Y_INC[].CLK = MAIN_CLK;
|
||||
BL_SRC_Y_INC[] = FB_AD[31..16];
|
||||
BL_SRC_Y_INC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C511"; -- $F8A22/2
|
||||
BL_SRC_Y_INC[15..8].ENA = BL_SRC_Y_INC_CS & !nFB_WR & FB_16B0;
|
||||
BL_SRC_Y_INC[7..0].ENA = BL_SRC_Y_INC_CS & !nFB_WR & FB_16B1;
|
||||
-- SRC ADR HIGH
|
||||
BL_SRC_ADR[].CLK = MAIN_CLK;
|
||||
BL_SRC_ADR[31..16] = FB_AD[31..16];
|
||||
BL_SRC_ADRH_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C512"; -- $F8A24/2
|
||||
BL_SRC_ADR[31..24].ENA = BL_SRC_ADRH_CS & !nFB_WR & FB_16B0;
|
||||
BL_SRC_ADR[23..16].ENA = BL_SRC_ADRH_CS & !nFB_WR & FB_16B1;
|
||||
-- SRC ADR LOW
|
||||
BL_SRC_ADR[].CLK = MAIN_CLK;
|
||||
BL_SRC_ADR[15..0] = FB_AD[31..16];
|
||||
BL_SRC_ADRL_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C513"; -- $F8A26/2
|
||||
BL_SRC_ADR[15..8].ENA = BL_SRC_ADRL_CS & !nFB_WR & FB_16B0;
|
||||
BL_SRC_ADR[7..0].ENA = BL_SRC_ADRL_CS & !nFB_WR & FB_16B1;
|
||||
-- ENDMASK 1
|
||||
BL_ENDMASK1[].CLK = MAIN_CLK;
|
||||
BL_ENDMASK1[] = FB_AD[31..16];
|
||||
BL_ENDMASK1_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C514"; -- $F8A28/2
|
||||
BL_ENDMASK1[15..8].ENA = BL_ENDMASK1_CS & !nFB_WR & FB_16B0;
|
||||
BL_ENDMASK1[7..0].ENA = BL_ENDMASK1_CS & !nFB_WR & FB_16B1;
|
||||
-- ENDMASK 2
|
||||
BL_ENDMASK2[].CLK = MAIN_CLK;
|
||||
BL_ENDMASK2[] = FB_AD[31..16];
|
||||
BL_ENDMASK2_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C515"; -- $F8A2A/2
|
||||
BL_ENDMASK2[15..8].ENA = BL_ENDMASK2_CS & !nFB_WR & FB_16B0;
|
||||
BL_ENDMASK2[7..0].ENA = BL_ENDMASK2_CS & !nFB_WR & FB_16B1;
|
||||
-- ENDMASK 3
|
||||
BL_ENDMASK3[].CLK = MAIN_CLK;
|
||||
BL_ENDMASK3[] = FB_AD[31..16];
|
||||
BL_ENDMASK3_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C516"; -- $F8A2C/2
|
||||
BL_ENDMASK3[15..8].ENA = BL_ENDMASK3_CS & !nFB_WR & FB_16B0;
|
||||
BL_ENDMASK3[7..0].ENA = BL_ENDMASK3_CS & !nFB_WR & FB_16B1;
|
||||
-- DST X INC
|
||||
BL_DST_X_INC[].CLK = MAIN_CLK;
|
||||
BL_DST_X_INC[] = FB_AD[31..16];
|
||||
BL_DST_X_INC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C517"; -- $F8A2E/2
|
||||
BL_DST_X_INC[15..8].ENA = BL_DST_X_INC_CS & !nFB_WR & FB_16B0;
|
||||
BL_DST_X_INC[7..0].ENA = BL_DST_X_INC_CS & !nFB_WR & FB_16B1;
|
||||
-- DST Y INC
|
||||
BL_DST_Y_INC[].CLK = MAIN_CLK;
|
||||
BL_DST_Y_INC[] = FB_AD[31..16];
|
||||
BL_DST_Y_INC_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C518"; -- $F8A30/2
|
||||
BL_DST_Y_INC[15..8].ENA = BL_DST_Y_INC_CS & !nFB_WR & FB_16B0;
|
||||
BL_DST_Y_INC[7..0].ENA = BL_DST_Y_INC_CS & !nFB_WR & FB_16B1;
|
||||
-- DST ADR HIGH
|
||||
BL_DST_ADR[].CLK = MAIN_CLK;
|
||||
BL_DST_ADR[31..16] = FB_AD[31..16];
|
||||
BL_DST_ADRH_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C512"; -- $F8A24/2
|
||||
BL_DST_ADR[31..24].ENA = BL_DST_ADRH_CS & !nFB_WR & FB_16B0;
|
||||
BL_DST_ADR[23..16].ENA = BL_DST_ADRH_CS & !nFB_WR & FB_16B1;
|
||||
-- DST ADR LOW
|
||||
BL_DST_ADR[].CLK = MAIN_CLK;
|
||||
BL_DST_ADR[15..0] = FB_AD[31..16];
|
||||
BL_DST_ADRL_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C513"; -- $F8A26/2
|
||||
BL_DST_ADR[15..8].ENA = BL_DST_ADRL_CS & !nFB_WR & FB_16B0;
|
||||
BL_DST_ADR[7..0].ENA = BL_DST_ADRL_CS & !nFB_WR & FB_16B1;
|
||||
-- X COUNT
|
||||
BL_X_CNT[].CLK = MAIN_CLK;
|
||||
BL_X_CNT[] = FB_AD[31..16];
|
||||
BL_X_CNT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51B"; -- $F8A36/2
|
||||
BL_X_CNT[15..8].ENA = BL_X_CNT_CS & !nFB_WR & FB_16B0;
|
||||
BL_X_CNT[7..0].ENA = BL_X_CNT_CS & !nFB_WR & FB_16B1;
|
||||
-- Y COUNT
|
||||
BL_Y_CNT[].CLK = MAIN_CLK;
|
||||
BL_Y_CNT[] = FB_AD[31..16];
|
||||
BL_Y_CNT_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51C"; -- $F8A38/2
|
||||
BL_Y_CNT[15..8].ENA = BL_Y_CNT_CS & !nFB_WR & FB_16B0;
|
||||
BL_Y_CNT[7..0].ENA = BL_Y_CNT_CS & !nFB_WR & FB_16B1;
|
||||
-- HALFTONE OP BYT
|
||||
BL_HT_OP[].CLK = MAIN_CLK;
|
||||
BL_HT_OP[] = FB_AD[31..24];
|
||||
BL_HT_OP_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51D"; -- $F8A3A/2
|
||||
BL_HT_OP[7..0].ENA = BL_HT_OP_CS & !nFB_WR & FB_16B0;
|
||||
-- LOGIC OP BYT
|
||||
BL_LC_OP[].CLK = MAIN_CLK;
|
||||
BL_LC_OP[] = FB_AD[23..16];
|
||||
BL_LC_OP[7..0].ENA = BL_HT_OP_CS & !nFB_WR & FB_16B1; -- $F8A3B
|
||||
-- LINE NUMBER BYT
|
||||
BL_LN[].CLK = MAIN_CLK;
|
||||
BL_LN[] = FB_AD[31..24];
|
||||
BL_LN_CS = !nFB_CS1 & FB_ADR[19..1]==H"7C51E"; -- $F8A3C/2
|
||||
BL_LN[7..0].ENA = BL_LN_CS & !nFB_WR & FB_16B0;
|
||||
-- SKEW BYT
|
||||
BL_SKEW[].CLK = MAIN_CLK;
|
||||
BL_SKEW[] = FB_AD[31..24];
|
||||
BL_SKEW[7..0].ENA = BL_LN_CS & !nFB_WR & FB_16B1; -- $F8A3D
|
||||
--- REGISTER OUT
|
||||
FB_AD[31..16] = lpm_bustri_WORD(
|
||||
BL_HRAM0_CS & BL_HRAM0[15..0]
|
||||
# BL_HRAM1_CS & BL_HRAM1[15..0]
|
||||
# BL_HRAM2_CS & BL_HRAM2[15..0]
|
||||
# BL_HRAM3_CS & BL_HRAM3[15..0]
|
||||
# BL_HRAM4_CS & BL_HRAM4[15..0]
|
||||
# BL_HRAM5_CS & BL_HRAM5[15..0]
|
||||
# BL_HRAM6_CS & BL_HRAM6[15..0]
|
||||
# BL_HRAM7_CS & BL_HRAM7[15..0]
|
||||
# BL_HRAM8_CS & BL_HRAM8[15..0]
|
||||
# BL_HRAM9_CS & BL_HRAM9[15..0]
|
||||
# BL_HRAMA_CS & BL_HRAMA[15..0]
|
||||
# BL_HRAMB_CS & BL_HRAMB[15..0]
|
||||
# BL_HRAMC_CS & BL_HRAMC[15..0]
|
||||
# BL_HRAMD_CS & BL_HRAMD[15..0]
|
||||
# BL_HRAME_CS & BL_HRAME[15..0]
|
||||
# BL_HRAMF_CS & BL_HRAMF[15..0]
|
||||
# BL_SRC_X_INC_CS & BL_SRC_X_INC[]
|
||||
# BL_SRC_Y_INC_CS & BL_SRC_Y_INC[]
|
||||
# BL_SRC_ADRH_CS & BL_SRC_ADR[31..16]
|
||||
# BL_SRC_ADRL_CS & BL_SRC_ADR[15..0]
|
||||
# BL_ENDMASK1_CS & BL_ENDMASK1[]
|
||||
# BL_ENDMASK2_CS & BL_ENDMASK2[]
|
||||
# BL_ENDMASK3_CS & BL_ENDMASK3[]
|
||||
# BL_DST_X_INC_CS & BL_DST_X_INC[]
|
||||
# BL_DST_Y_INC_CS & BL_DST_Y_INC[]
|
||||
# BL_DST_ADRH_CS & BL_DST_ADR[31..16]
|
||||
# BL_DST_ADRL_CS & BL_DST_ADR[15..0]
|
||||
# BL_X_CNT_CS & BL_X_CNT[]
|
||||
# BL_Y_CNT_CS & BL_Y_CNT[]
|
||||
# BL_HT_OP_CS & (BL_HT_OP[],BL_LC_OP[])
|
||||
# BL_LN_CS & (BL_LN[],BL_SKEW[])
|
||||
,!nFB_CS1 & FB_ADR[19..6]==H"3E28" & !nFB_OE); -- FFFF8A00-3F/40
|
||||
-----------------------------------------
|
||||
--
|
||||
BL_READ_SRC.CLK = DDRCLK0;
|
||||
BL_READ_DST.CLK = DDRCLK0;
|
||||
|
||||
|
||||
BLITTER_RUN = VCC;
|
||||
BLITTER_SIG = VCC;
|
||||
BLITTER_WR = VCC;
|
||||
-- READY SIGNAL 1 CLOCK SP<53>TER
|
||||
BL_DATA_DDR_READY.CLK = DDRCLK0;
|
||||
BL_DATA_DDR_READY = BL_DATA_DDR_READY & BLITTER_DACK0;
|
||||
-- SRC BUFFER LADEN
|
||||
BL_SKEW_IN[].CLK = DDRCLK0;
|
||||
BL_SKEW_IN[].ENA = BL_DATA_DDR_READY & BL_READ_SRC;
|
||||
BL_SKEW_IN[255..128] = BLITTER_DIN[];
|
||||
BL_SKEW_IN[127..0] = BL_SKEW_IN[255..128];
|
||||
-- DST BUFFER LADEN
|
||||
BL_DST_BUFFER[].CLK = DDRCLK0;
|
||||
BL_DST_BUFFER[].ENA = BL_DATA_DDR_READY & BL_READ_DST;
|
||||
BL_DST_BUFFER[] = BLITTER_DIN[];
|
||||
-- SKEW EXTENDET
|
||||
BL_SKEW_EXT[6..4] = BL_SRC_ADR[3..1];
|
||||
BL_SKEW_EXT[3..0] = BL_SKEW[3..0];
|
||||
-- SKEW EXT MUX
|
||||
BL_SKEW_OUT[].CLK = DDRCLK0;
|
||||
BL_SKEW_OUT[].ENA = BL_DATA_DDR_READY & BL_READ_DST;
|
||||
BL_SKEW_OUT[] = lpm_clshift0(BL_SKEW_IN[],BL_SKEW_EXT[]); -- BIT 127..0 SIND RELEVANT
|
||||
|
||||
COUNT[] = COUNT[] + 16;
|
||||
COUNT[].CLK = BLITTER_DACK0;
|
||||
BLITTER_DOUT[] = H"112233445566778899AABBCCDDEEFF00";
|
||||
BLITTER_ADR[] = (0, COUNT[]) + 400000;
|
||||
|
||||
END;
|
||||
|
||||
@@ -1,54 +0,0 @@
|
||||
/*
|
||||
WARNING: Do NOT edit the input and output ports in this file in a text
|
||||
editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2010 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
(including device programming or simulation files), and any
|
||||
associated documentation or information are expressly subject
|
||||
to the terms and conditions of the Altera Program License
|
||||
Subscription Agreement, Altera MegaCore Function License
|
||||
Agreement, or other applicable license agreement, including,
|
||||
without limitation, that your use is for the sole purpose of
|
||||
programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.1"))
|
||||
(symbol
|
||||
(rect 0 0 208 80)
|
||||
(text "lpm_clshift0" (rect 62 3 162 22)(font "Arial" (font_size 10)))
|
||||
(text "inst" (rect 8 61 31 76)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 24)
|
||||
(input)
|
||||
(text "data[255..0]" (rect 0 0 81 16)(font "Arial" (font_size 8)))
|
||||
(text "data[255..0]" (rect 20 16 89 32)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 24)(pt 16 24)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 0 40)
|
||||
(input)
|
||||
(text "distance[6..0]" (rect 0 0 93 16)(font "Arial" (font_size 8)))
|
||||
(text "distance[6..0]" (rect 20 32 99 48)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 40)(pt 16 40)(line_width 3))
|
||||
)
|
||||
(port
|
||||
(pt 208 24)
|
||||
(output)
|
||||
(text "result[255..0]" (rect 0 0 89 16)(font "Arial" (font_size 8)))
|
||||
(text "result[255..0]" (rect 113 16 189 32)(font "Arial" (font_size 8)))
|
||||
(line (pt 208 24)(pt 192 24)(line_width 3))
|
||||
)
|
||||
(drawing
|
||||
(text "LOGICAL right shift" (rect 21 50 114 64)(font "Arial" ))
|
||||
(line (pt 16 16)(pt 16 64)(line_width 1))
|
||||
(line (pt 192 16)(pt 192 64)(line_width 1))
|
||||
(line (pt 16 16)(pt 192 16)(line_width 1))
|
||||
(line (pt 16 64)(pt 192 64)(line_width 1))
|
||||
)
|
||||
)
|
||||
@@ -13,12 +13,13 @@
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
FUNCTION lpm_clshift0
|
||||
FUNCTION lpm_clshift144
|
||||
(
|
||||
data[255..0],
|
||||
distance[6..0]
|
||||
data[143..0],
|
||||
direction,
|
||||
distance[7..0]
|
||||
)
|
||||
|
||||
RETURNS (
|
||||
result[255..0]
|
||||
result[143..0]
|
||||
);
|
||||
4
FPGA_by_Fredi/Video/BLITTER/lpm_clshift144.qip
Normal file
4
FPGA_by_Fredi/Video/BLITTER/lpm_clshift144.qip
Normal file
@@ -0,0 +1,4 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "LPM_CLSHIFT"
|
||||
set_global_assignment -name IP_TOOL_VERSION "9.1"
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_clshift144.tdf"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_clshift144.inc"]
|
||||
94
FPGA_by_Fredi/Video/BLITTER/lpm_clshift144.tdf
Normal file
94
FPGA_by_Fredi/Video/BLITTER/lpm_clshift144.tdf
Normal file
@@ -0,0 +1,94 @@
|
||||
-- megafunction wizard: %LPM_CLSHIFT%
|
||||
-- GENERATION: STANDARD
|
||||
-- VERSION: WM1.0
|
||||
-- MODULE: lpm_clshift
|
||||
|
||||
-- ============================================================
|
||||
-- File Name: lpm_clshift144.tdf
|
||||
-- Megafunction Name(s):
|
||||
-- lpm_clshift
|
||||
--
|
||||
-- Simulation Library Files(s):
|
||||
--
|
||||
-- ============================================================
|
||||
-- ************************************************************
|
||||
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
--
|
||||
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
|
||||
-- ************************************************************
|
||||
|
||||
|
||||
--Copyright (C) 1991-2010 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
--(including device programming or simulation files), and any
|
||||
--associated documentation or information are expressly subject
|
||||
--to the terms and conditions of the Altera Program License
|
||||
--Subscription Agreement, Altera MegaCore Function License
|
||||
--Agreement, or other applicable license agreement, including,
|
||||
--without limitation, that your use is for the sole purpose of
|
||||
--programming logic devices manufactured by Altera and sold by
|
||||
--Altera or its authorized distributors. Please refer to the
|
||||
--applicable agreement for further details.
|
||||
|
||||
INCLUDE "lpm_clshift.inc";
|
||||
|
||||
|
||||
|
||||
SUBDESIGN lpm_clshift144
|
||||
(
|
||||
data[143..0] : INPUT;
|
||||
direction : INPUT;
|
||||
distance[7..0] : INPUT;
|
||||
result[143..0] : OUTPUT;
|
||||
)
|
||||
|
||||
VARIABLE
|
||||
|
||||
lpm_clshift_component : lpm_clshift WITH (
|
||||
LPM_SHIFTTYPE = "LOGICAL",
|
||||
LPM_TYPE = "LPM_CLSHIFT",
|
||||
LPM_WIDTH = 144,
|
||||
LPM_WIDTHDIST = 8
|
||||
);
|
||||
|
||||
BEGIN
|
||||
|
||||
result[143..0] = lpm_clshift_component.result[143..0];
|
||||
lpm_clshift_component.distance[7..0] = distance[7..0];
|
||||
lpm_clshift_component.direction = direction;
|
||||
lpm_clshift_component.data[143..0] = data[143..0];
|
||||
END;
|
||||
|
||||
|
||||
|
||||
-- ============================================================
|
||||
-- CNX file retrieval info
|
||||
-- ============================================================
|
||||
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
-- Retrieval info: PRIVATE: LPM_SHIFTTYPE NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: LPM_WIDTH NUMERIC "144"
|
||||
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
-- Retrieval info: PRIVATE: lpm_width_varies NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: lpm_widthdist NUMERIC "8"
|
||||
-- Retrieval info: PRIVATE: lpm_widthdist_style NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: port_direction NUMERIC "2"
|
||||
-- Retrieval info: CONSTANT: LPM_SHIFTTYPE STRING "LOGICAL"
|
||||
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CLSHIFT"
|
||||
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "144"
|
||||
-- Retrieval info: CONSTANT: LPM_WIDTHDIST NUMERIC "8"
|
||||
-- Retrieval info: USED_PORT: data 0 0 144 0 INPUT NODEFVAL data[143..0]
|
||||
-- Retrieval info: USED_PORT: direction 0 0 0 0 INPUT NODEFVAL direction
|
||||
-- Retrieval info: USED_PORT: distance 0 0 8 0 INPUT NODEFVAL distance[7..0]
|
||||
-- Retrieval info: USED_PORT: result 0 0 144 0 OUTPUT NODEFVAL result[143..0]
|
||||
-- Retrieval info: CONNECT: @distance 0 0 8 0 distance 0 0 8 0
|
||||
-- Retrieval info: CONNECT: @data 0 0 144 0 data 0 0 144 0
|
||||
-- Retrieval info: CONNECT: result 0 0 144 0 @result 0 0 144 0
|
||||
-- Retrieval info: CONNECT: @direction 0 0 0 0 direction 0 0 0 0
|
||||
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_clshift144.tdf TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_clshift144.inc TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_clshift144.cmp FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_clshift144.bsf FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_clshift144_inst.tdf FALSE
|
||||
@@ -13,11 +13,13 @@
|
||||
--applicable agreement for further details.
|
||||
|
||||
|
||||
component lpm_clshift0
|
||||
PORT
|
||||
(
|
||||
data : IN STD_LOGIC_VECTOR (255 DOWNTO 0);
|
||||
distance : IN STD_LOGIC_VECTOR (6 DOWNTO 0);
|
||||
result : OUT STD_LOGIC_VECTOR (255 DOWNTO 0)
|
||||
);
|
||||
end component;
|
||||
FUNCTION lpm_clshift384
|
||||
(
|
||||
data[383..0],
|
||||
direction,
|
||||
distance[7..0]
|
||||
)
|
||||
|
||||
RETURNS (
|
||||
result[383..0]
|
||||
);
|
||||
@@ -1,6 +1,5 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "LPM_CLSHIFT"
|
||||
set_global_assignment -name IP_TOOL_VERSION "9.1"
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_clshift0.tdf"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_clshift0.bsf"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_clshift0.inc"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_clshift0.cmp"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_clshift384.tdf"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_clshift384.inc"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "lpm_clshift384.cmp"]
|
||||
@@ -36,11 +36,12 @@ INCLUDE "lpm_clshift.inc";
|
||||
|
||||
|
||||
|
||||
SUBDESIGN lpm_clshift0
|
||||
SUBDESIGN lpm_clshift384
|
||||
(
|
||||
data[255..0] : INPUT;
|
||||
distance[6..0] : INPUT;
|
||||
result[255..0] : OUTPUT;
|
||||
data[383..0] : INPUT;
|
||||
direction : INPUT;
|
||||
distance[7..0] : INPUT;
|
||||
result[383..0] : OUTPUT;
|
||||
)
|
||||
|
||||
VARIABLE
|
||||
@@ -48,16 +49,16 @@ VARIABLE
|
||||
lpm_clshift_component : lpm_clshift WITH (
|
||||
LPM_SHIFTTYPE = "LOGICAL",
|
||||
LPM_TYPE = "LPM_CLSHIFT",
|
||||
LPM_WIDTH = 256,
|
||||
LPM_WIDTHDIST = 7
|
||||
LPM_WIDTH = 384,
|
||||
LPM_WIDTHDIST = 8
|
||||
);
|
||||
|
||||
BEGIN
|
||||
|
||||
result[255..0] = lpm_clshift_component.result[255..0];
|
||||
lpm_clshift_component.distance[6..0] = distance[6..0];
|
||||
lpm_clshift_component.direction = VCC;
|
||||
lpm_clshift_component.data[255..0] = data[255..0];
|
||||
result[383..0] = lpm_clshift_component.result[383..0];
|
||||
lpm_clshift_component.distance[7..0] = distance[7..0];
|
||||
lpm_clshift_component.direction = direction;
|
||||
lpm_clshift_component.data[383..0] = data[383..0];
|
||||
END;
|
||||
|
||||
|
||||
@@ -67,26 +68,27 @@ END;
|
||||
-- ============================================================
|
||||
-- Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone III"
|
||||
-- Retrieval info: PRIVATE: LPM_SHIFTTYPE NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: LPM_WIDTH NUMERIC "256"
|
||||
-- Retrieval info: PRIVATE: LPM_WIDTH NUMERIC "384"
|
||||
-- Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
|
||||
-- Retrieval info: PRIVATE: lpm_width_varies NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: lpm_widthdist NUMERIC "7"
|
||||
-- Retrieval info: PRIVATE: lpm_widthdist_style NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: port_direction NUMERIC "1"
|
||||
-- Retrieval info: PRIVATE: lpm_widthdist NUMERIC "8"
|
||||
-- Retrieval info: PRIVATE: lpm_widthdist_style NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: port_direction NUMERIC "2"
|
||||
-- Retrieval info: CONSTANT: LPM_SHIFTTYPE STRING "LOGICAL"
|
||||
-- Retrieval info: CONSTANT: LPM_TYPE STRING "LPM_CLSHIFT"
|
||||
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "256"
|
||||
-- Retrieval info: CONSTANT: LPM_WIDTHDIST NUMERIC "7"
|
||||
-- Retrieval info: USED_PORT: data 0 0 256 0 INPUT NODEFVAL data[255..0]
|
||||
-- Retrieval info: USED_PORT: distance 0 0 7 0 INPUT NODEFVAL distance[6..0]
|
||||
-- Retrieval info: USED_PORT: result 0 0 256 0 OUTPUT NODEFVAL result[255..0]
|
||||
-- Retrieval info: CONNECT: @distance 0 0 7 0 distance 0 0 7 0
|
||||
-- Retrieval info: CONNECT: @data 0 0 256 0 data 0 0 256 0
|
||||
-- Retrieval info: CONNECT: result 0 0 256 0 @result 0 0 256 0
|
||||
-- Retrieval info: CONNECT: @direction 0 0 0 0 VCC 0 0 0 0
|
||||
-- Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "384"
|
||||
-- Retrieval info: CONSTANT: LPM_WIDTHDIST NUMERIC "8"
|
||||
-- Retrieval info: USED_PORT: data 0 0 384 0 INPUT NODEFVAL data[383..0]
|
||||
-- Retrieval info: USED_PORT: direction 0 0 0 0 INPUT NODEFVAL direction
|
||||
-- Retrieval info: USED_PORT: distance 0 0 8 0 INPUT NODEFVAL distance[7..0]
|
||||
-- Retrieval info: USED_PORT: result 0 0 384 0 OUTPUT NODEFVAL result[383..0]
|
||||
-- Retrieval info: CONNECT: @distance 0 0 8 0 distance 0 0 8 0
|
||||
-- Retrieval info: CONNECT: @data 0 0 384 0 data 0 0 384 0
|
||||
-- Retrieval info: CONNECT: result 0 0 384 0 @result 0 0 384 0
|
||||
-- Retrieval info: CONNECT: @direction 0 0 0 0 direction 0 0 0 0
|
||||
-- Retrieval info: LIBRARY: lpm lpm.lpm_components.all
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_clshift0.tdf TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_clshift0.inc TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_clshift0.cmp TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_clshift0.bsf TRUE FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_clshift0.bsf TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL lpm_clshift0_inst.tdf FALSE
|
||||
Reference in New Issue
Block a user