Sync with Fredi's source tree 15/04/2017

IDE and Blitter work.

FPGA_by_Fredi/FPGA_DATE.bsf

@@ -0,0 +1,42 @@
+/*
+WARNING: Do NOT edit the input and output ports in this file in a text
+editor if you plan to continue editing the block that represents it in
+the Block Editor! File corruption is VERY likely to occur.
+*/
+/*
+Copyright (C) 1991-2010 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions 
+and other software and tools, and its AMPP partner logic 
+functions, and any output files from any of the foregoing 
+(including device programming or simulation files), and any 
+associated documentation or information are expressly subject 
+to the terms and conditions of the Altera Program License 
+Subscription Agreement, Altera MegaCore Function License 
+Agreement, or other applicable license agreement, including, 
+without limitation, that your use is for the sole purpose of 
+programming logic devices manufactured by Altera and sold by 
+Altera or its authorized distributors.  Please refer to the 
+applicable agreement for further details.
+*/
+(header "symbol" (version "1.1"))
+(symbol
+	(rect 0 0 88 48)
+	(text "FPGA_DATE" (rect 6 1 96 17)(font "Arial" (font_size 10)))
+	(text "inst" (rect 8 32 25 44)(font "Arial" ))
+	(port
+		(pt 88 24)
+		(output)
+		(text "result[31..0]" (rect 0 0 67 14)(font "Arial" (font_size 8)))
+		(text "result[31..0]" (rect 85 -31 98 24)(font "Arial" (font_size 8))(invisible))
+		(line (pt 88 24)(pt 72 24)(line_width 3))
+	)
+	(drawing
+		(text "319037463" (rect 27 18 72 30)(font "Arial" ))
+		(text "32" (rect 77 25 87 37)(font "Arial" ))
+		(line (pt 16 16)(pt 72 16)(line_width 1))
+		(line (pt 72 16)(pt 72 32)(line_width 1))
+		(line (pt 72 32)(pt 16 32)(line_width 1))
+		(line (pt 16 32)(pt 16 16)(line_width 1))
+		(line (pt 72 28)(pt 80 20)(line_width 1))
+	)
+)