forked from Firebee/FPGA_Config
basically working config. Resolution changes still scramble the screen, however
This commit is contained in:
Markus Fröschle
@@ -4,7 +4,7 @@ editor if you plan to continue editing the block that represents it in
|
||||
the Block Editor! File corruption is VERY likely to occur.
|
||||
*/
|
||||
/*
|
||||
Copyright (C) 1991-2010 Altera Corporation
|
||||
Copyright (C) 1991-2014 Altera Corporation
|
||||
Your use of Altera Corporation's design tools, logic functions
|
||||
and other software and tools, and its AMPP partner logic
|
||||
functions, and any output files from any of the foregoing
|
||||
@@ -18,100 +18,100 @@ programming logic devices manufactured by Altera and sold by
|
||||
Altera or its authorized distributors. Please refer to the
|
||||
applicable agreement for further details.
|
||||
*/
|
||||
(header "symbol" (version "1.1"))
|
||||
(header "symbol" (version "1.2"))
|
||||
(symbol
|
||||
(rect 0 0 304 248)
|
||||
(text "altpll2" (rect 132 1 179 20)(font "Arial" (font_size 10)))
|
||||
(text "inst" (rect 8 229 31 244)(font "Arial" ))
|
||||
(rect 0 0 256 200)
|
||||
(text "altpll2" (rect 111 0 153 16)(font "Arial" (font_size 10)))
|
||||
(text "inst" (rect 8 185 26 196)(font "Arial" ))
|
||||
(port
|
||||
(pt 0 72)
|
||||
(pt 0 64)
|
||||
(input)
|
||||
(text "inclk0" (rect 0 0 40 16)(font "Arial" (font_size 8)))
|
||||
(text "inclk0" (rect 4 56 38 72)(font "Arial" (font_size 8)))
|
||||
(line (pt 0 72)(pt 48 72)(line_width 1))
|
||||
(text "inclk0" (rect 0 0 34 13)(font "Arial" (font_size 8)))
|
||||
(text "inclk0" (rect 4 51 31 63)(font "Arial" (font_size 8)))
|
||||
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|
||||
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|
||||
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|
||||
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|
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|
||||
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|
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|
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|
||||
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|
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|
||||
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
(output)
|
||||
(text "c2" (rect 0 0 16 16)(font "Arial" (font_size 8)))
|
||||
(text "c2" (rect 287 104 301 120)(font "Arial" (font_size 8)))
|
||||
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|
||||
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|
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|
||||
)
|
||||
(port
|
||||
(pt 304 144)
|
||||
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|
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|
||||
(text "c3" (rect 0 0 16 16)(font "Arial" (font_size 8)))
|
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|
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|
||||
(text "c3" (rect 0 0 15 13)(font "Arial" (font_size 8)))
|
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|
||||
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|
||||
(port
|
||||
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|
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|
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|
||||
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|
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|
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|
||||
)
|
||||
(drawing
|
||||
(text "Cyclone III" (rect 229 230 277 244)(font "Arial" ))
|
||||
(text "inclk0 frequency: 33.000 MHz" (rect 58 67 201 81)(font "Arial" ))
|
||||
(text "Operation Mode: Src Sync Comp" (rect 58 84 215 98)(font "Arial" ))
|
||||
(text "Clk " (rect 59 111 76 125)(font "Arial" ))
|
||||
(text "Ratio" (rect 85 111 109 125)(font "Arial" ))
|
||||
(text "Ph (dg)" (rect 119 111 154 125)(font "Arial" ))
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|
||||
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|
||||
(text "Cyclone III" (rect 198 186 442 382)(font "Arial" ))
|
||||
(text "inclk0 frequency: 33.000 MHz" (rect 50 60 226 130)(font "Arial" ))
|
||||
(text "Operation Mode: Src Sync Comp" (rect 50 72 239 154)(font "Arial" ))
|
||||
(text "Clk " (rect 51 91 117 192)(font "Arial" ))
|
||||
(text "Ratio" (rect 71 91 165 192)(font "Arial" ))
|
||||
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|
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|
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||||
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|
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|
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|
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|
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|
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|
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|
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|
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
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|
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|
||||
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|
||||
)
|
||||
)
|
||||
|
||||
@@ -1,4 +1,4 @@
|
||||
--Copyright (C) 1991-2010 Altera Corporation
|
||||
--Copyright (C) 1991-2014 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
|
||||
@@ -1,4 +1,4 @@
|
||||
--Copyright (C) 1991-2010 Altera Corporation
|
||||
--Copyright (C) 1991-2014 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
set_global_assignment -name IP_TOOL_NAME "ALTPLL"
|
||||
set_global_assignment -name IP_TOOL_VERSION "9.1"
|
||||
set_global_assignment -name IP_TOOL_VERSION "13.1"
|
||||
set_global_assignment -name VHDL_FILE [file join $::quartus(qip_path) "altpll2.vhd"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.bsf"]
|
||||
set_global_assignment -name MISC_FILE [file join $::quartus(qip_path) "altpll2.inc"]
|
||||
|
||||
@@ -14,11 +14,11 @@
|
||||
-- ************************************************************
|
||||
-- THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
|
||||
--
|
||||
-- 9.1 Build 350 03/24/2010 SP 2 SJ Web Edition
|
||||
-- 13.1.4 Build 182 03/12/2014 SJ Web Edition
|
||||
-- ************************************************************
|
||||
|
||||
|
||||
--Copyright (C) 1991-2010 Altera Corporation
|
||||
--Copyright (C) 1991-2014 Altera Corporation
|
||||
--Your use of Altera Corporation's design tools, logic functions
|
||||
--and other software and tools, and its AMPP partner logic
|
||||
--functions, and any output files from any of the foregoing
|
||||
@@ -140,8 +140,8 @@ ARCHITECTURE SYN OF altpll2 IS
|
||||
width_clock : NATURAL
|
||||
);
|
||||
PORT (
|
||||
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0);
|
||||
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0)
|
||||
clk : OUT STD_LOGIC_VECTOR (4 DOWNTO 0);
|
||||
inclk : IN STD_LOGIC_VECTOR (1 DOWNTO 0)
|
||||
);
|
||||
END COMPONENT;
|
||||
|
||||
@@ -149,14 +149,14 @@ BEGIN
|
||||
sub_wire8_bv(0 DOWNTO 0) <= "0";
|
||||
sub_wire8 <= To_stdlogicvector(sub_wire8_bv);
|
||||
sub_wire5 <= sub_wire0(4);
|
||||
sub_wire4 <= sub_wire0(3);
|
||||
sub_wire3 <= sub_wire0(2);
|
||||
sub_wire2 <= sub_wire0(1);
|
||||
sub_wire1 <= sub_wire0(0);
|
||||
c0 <= sub_wire1;
|
||||
c1 <= sub_wire2;
|
||||
c2 <= sub_wire3;
|
||||
c3 <= sub_wire4;
|
||||
sub_wire4 <= sub_wire0(2);
|
||||
sub_wire3 <= sub_wire0(0);
|
||||
sub_wire2 <= sub_wire0(3);
|
||||
sub_wire1 <= sub_wire0(1);
|
||||
c1 <= sub_wire1;
|
||||
c3 <= sub_wire2;
|
||||
c0 <= sub_wire3;
|
||||
c2 <= sub_wire4;
|
||||
c4 <= sub_wire5;
|
||||
sub_wire6 <= inclk0;
|
||||
sub_wire7 <= sub_wire8(0 DOWNTO 0) & sub_wire6;
|
||||
@@ -293,7 +293,7 @@ END SYN;
|
||||
-- Retrieval info: PRIVATE: INT_FEEDBACK__MODE_RADIO STRING "1"
|
||||
-- Retrieval info: PRIVATE: LOCKED_OUTPUT_CHECK STRING "0"
|
||||
-- Retrieval info: PRIVATE: LONG_SCAN_RADIO STRING "1"
|
||||
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "330.000"
|
||||
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE STRING "Not Available"
|
||||
-- Retrieval info: PRIVATE: LVDS_MODE_DATA_RATE_DIRTY NUMERIC "0"
|
||||
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT0 STRING "deg"
|
||||
-- Retrieval info: PRIVATE: LVDS_PHASE_SHIFT_UNIT1 STRING "deg"
|
||||
@@ -459,18 +459,18 @@ END SYN;
|
||||
-- Retrieval info: USED_PORT: c3 0 0 0 0 OUTPUT_CLK_EXT VCC "c3"
|
||||
-- Retrieval info: USED_PORT: c4 0 0 0 0 OUTPUT_CLK_EXT VCC "c4"
|
||||
-- Retrieval info: USED_PORT: inclk0 0 0 0 0 INPUT_CLK_EXT GND "inclk0"
|
||||
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
|
||||
-- Retrieval info: CONNECT: @inclk 0 0 1 0 inclk0 0 0 0 0
|
||||
-- Retrieval info: CONNECT: c0 0 0 0 0 @clk 0 0 1 0
|
||||
-- Retrieval info: CONNECT: c1 0 0 0 0 @clk 0 0 1 1
|
||||
-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
|
||||
-- Retrieval info: CONNECT: c2 0 0 0 0 @clk 0 0 1 2
|
||||
-- Retrieval info: CONNECT: c3 0 0 0 0 @clk 0 0 1 3
|
||||
-- Retrieval info: CONNECT: c4 0 0 0 0 @clk 0 0 1 4
|
||||
-- Retrieval info: CONNECT: @inclk 0 0 1 1 GND 0 0 0 0
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.vhd TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.ppf TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.inc TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.cmp TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.bsf TRUE FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2.bsf TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2_inst.vhd FALSE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2_waveforms.html TRUE
|
||||
-- Retrieval info: GEN_FILE: TYPE_NORMAL altpll2_wave*.jpg FALSE
|
||||
|
||||
@@ -751,4 +751,11 @@ set_global_assignment -name QIP_FILE lpm_bustri_LONG.qip
|
||||
set_global_assignment -name QIP_FILE lpm_bustri_BYT.qip
|
||||
set_global_assignment -name QIP_FILE lpm_bustri_WORD.qip
|
||||
set_global_assignment -name QIP_FILE altddio_out3.qip
|
||||
set_global_assignment -name VHDL_INPUT_VERSION VHDL_2008
|
||||
set_global_assignment -name VHDL_SHOW_LMF_MAPPING_MESSAGES OFF
|
||||
set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (VHDL)"
|
||||
set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VHDL -section_id eda_simulation
|
||||
|
||||
set_global_assignment -name SYNCHRONIZER_IDENTIFICATION AUTO
|
||||
set_global_assignment -name TIMEQUEST_DO_CCPP_REMOVAL ON
|
||||
set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
|
||||
Binary file not shown.
@@ -1,30 +1,47 @@
|
||||
## Generated SDC file "firebee1.sdc"
|
||||
|
||||
## Copyright (C) 1991-2014 Altera Corporation
|
||||
## Your use of Altera Corporation's design tools, logic functions
|
||||
## and other software and tools, and its AMPP partner logic
|
||||
## functions, and any output files from any of the foregoing
|
||||
## (including device programming or simulation files), and any
|
||||
## associated documentation or information are expressly subject
|
||||
## to the terms and conditions of the Altera Program License
|
||||
## Subscription Agreement, Altera MegaCore Function License
|
||||
## Agreement, or other applicable license agreement, including,
|
||||
## without limitation, that your use is for the sole purpose of
|
||||
## programming logic devices manufactured by Altera and sold by
|
||||
## Altera or its authorized distributors. Please refer to the
|
||||
## applicable agreement for further details.
|
||||
|
||||
|
||||
## VENDOR "Altera"
|
||||
## PROGRAM "Quartus II"
|
||||
## VERSION "Version 13.1.4 Build 182 03/12/2014 SJ Web Edition"
|
||||
|
||||
## DATE "Mon Sep 21 20:39:03 2015"
|
||||
|
||||
#--------------------------------------------------------------#
|
||||
# #
|
||||
## DEVICE "EP3C40F484C6"
|
||||
# Synopsis design constraints for the Firebee project #
|
||||
# #
|
||||
|
||||
# This file is part of the Firebee ACP project. #
|
||||
# http://www.experiment-s.de #
|
||||
# #
|
||||
# Description: #
|
||||
# timing constraints for the Firebee VHDL config #
|
||||
# #
|
||||
# #
|
||||
# #
|
||||
# To Do: #
|
||||
# - #
|
||||
# #
|
||||
# Author(s): #
|
||||
# Markus Fröschle, mfro@mubf.de #
|
||||
# #
|
||||
#--------------------------------------------------------------#
|
||||
# #
|
||||
# Copyright (C) 2015 Markus Fröschle & the ACP project #
|
||||
# #
|
||||
# This source file may be used and distributed without #
|
||||
# restriction provided that this copyright statement is not #
|
||||
# removed from the file and that any derivative work contains #
|
||||
# the original copyright notice and the associated disclaimer. #
|
||||
# #
|
||||
# This source file is free software; you can redistribute it #
|
||||
# and/or modify it under the terms of the GNU Lesser General #
|
||||
# Public License as published by the Free Software Foundation; #
|
||||
# either version 2.1 of the License, or (at your option) any #
|
||||
# later version. #
|
||||
# #
|
||||
# This source is distributed in the hope that it will be #
|
||||
# useful, but WITHOUT ANY WARRANTY; without even the implied #
|
||||
# warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR #
|
||||
# PURPOSE. See the GNU Lesser General Public License for more #
|
||||
# details. #
|
||||
# #
|
||||
# You should have received a copy of the GNU Lesser General #
|
||||
# Public License along with this source; if not, download it #
|
||||
# from http://www.gnu.org/licenses/lgpl.html #
|
||||
# #
|
||||
################################################################
|
||||
|
||||
#**************************************************************
|
||||
# Time Information
|
||||
@@ -51,11 +68,11 @@ create_clock -name {MAIN_CLK} -period 30.303 -waveform { 0.000 15.151 } [get_por
|
||||
#
|
||||
# PLL2: i_ddr_clock_pll
|
||||
# input: MAIN_CLK
|
||||
# c0: 132 MHz
|
||||
# c1: 132 MHz
|
||||
# c2: 132 MHz
|
||||
# c3: 132 MHz
|
||||
# c4: 66 MHz
|
||||
# c0: 132 MHz 190°
|
||||
# c1: 132 MHz 0°
|
||||
# c2: 132 MHz 180°
|
||||
# c3: 132 MHz 105°
|
||||
# c4: 66 MHz 270°
|
||||
#
|
||||
# PLL3: i_atari_clk_pll
|
||||
# input: MAIN_CLK
|
||||
@@ -101,14 +118,14 @@ derive_clock_uncertainty
|
||||
# Set Input Delay
|
||||
#**************************************************************
|
||||
|
||||
set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] 1.000 [get_ports {FB_AD[0]}]
|
||||
set_input_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.000 [all_inputs]
|
||||
|
||||
|
||||
#**************************************************************
|
||||
# Set Output Delay
|
||||
#**************************************************************
|
||||
|
||||
set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] 1.000 [get_ports {FB_AD[0]}]
|
||||
set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] -max 1.000 [all_outputs]
|
||||
|
||||
|
||||
#**************************************************************
|
||||
@@ -122,7 +139,7 @@ set_output_delay -add_delay -clock [get_clocks {MAIN_CLK}] 1.000 [get_ports {F
|
||||
#**************************************************************
|
||||
|
||||
#
|
||||
# i_videl_clk is freely programmable
|
||||
# i_video_clk is freely programmable
|
||||
#
|
||||
set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_video_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]
|
||||
|
||||
@@ -133,9 +150,6 @@ set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_atari_clk_pl
|
||||
# MAIN_CLK to DDR clk and v.v.
|
||||
set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]
|
||||
set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] -to [get_clocks {MAIN_CLK}]
|
||||
set_false_path -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}]
|
||||
set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {MAIN_CLK}]
|
||||
|
||||
|
||||
set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {i_atari_clk_pll|altpll_component|auto_generated|pll1|clk[1]}]
|
||||
set_false_path -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}]
|
||||
@@ -174,48 +188,6 @@ set_false_path -from [get_keepers {*rdptr_g*}] -to [get_keepers {*ws_dgrp|dffpip
|
||||
# Set Multicycle Path
|
||||
#**************************************************************
|
||||
|
||||
# Clocks used:
|
||||
# MAIN_CLK 33MHz
|
||||
#
|
||||
# PLL1: i_mfp_acia_clk_pll
|
||||
# input: MAIN_CLK
|
||||
# c0: 500 kHz
|
||||
# c1: 2.4576 MHz
|
||||
# c2: 24.576 MHz
|
||||
#
|
||||
# PLL2: i_ddr_clock_pll
|
||||
# input: MAIN_CLK
|
||||
# c0: 132 MHz
|
||||
# c1: 132 MHz
|
||||
# c2: 132 MHz
|
||||
# c3: 132 MHz
|
||||
# c4: 66 MHz
|
||||
#
|
||||
# PLL3: i_atari_clk_pll
|
||||
# input: MAIN_CLK
|
||||
# c0: 2 MHz
|
||||
# c1: 16 MHz
|
||||
# c2: 25 MHz
|
||||
# c3: 48 MHz
|
||||
#
|
||||
# PLL4_ i_video_clk_pll
|
||||
# input: USB_CLK (48 MHz, PLL3 c3)
|
||||
# c0: 96 MHz, programmable in 1MHz steps
|
||||
|
||||
|
||||
# 66 MHz to 33 MHz
|
||||
set_multicycle_path -setup -start -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {MAIN_CLK}] 2
|
||||
set_multicycle_path -hold -start -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {MAIN_CLK}] 2
|
||||
# 33 MHz to 66 MHz
|
||||
set_multicycle_path -setup -end -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] 2
|
||||
set_multicycle_path -hold -end -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] 2
|
||||
# 132 MHz to 33 MHz
|
||||
set_multicycle_path -setup -end -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {MAIN_CLK}] 4
|
||||
set_multicycle_path -hold -end -from [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] -to [get_clocks {MAIN_CLK}] 4
|
||||
# 33 MHz to 132 MHz
|
||||
set_multicycle_path -setup -start -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] 4
|
||||
set_multicycle_path -hold -start -from [get_clocks {MAIN_CLK}] -to [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[4]}] 4
|
||||
|
||||
#**************************************************************
|
||||
# Set Maximum Delay
|
||||
#**************************************************************
|
||||
@@ -238,3 +210,15 @@ set_multicycle_path -hold -start -from [get_clocks {MAIN_CLK}] -to [get_clocks {
|
||||
#set_output_delay -max -clock [get_clocks {MAIN_CLK}] [get_pins {*}] 25
|
||||
#set_output_delay -min -clock [get_clocks {MAIN_CLK}] [get_pins {*}] .5
|
||||
|
||||
# restrict timing of video controller
|
||||
|
||||
#set_output_delay -min -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] 0.1 [get_ports {VA[*]}]
|
||||
#set_output_delay -max -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] 0.2 [get_ports {VA[*]}]
|
||||
|
||||
#set_output_delay -min -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] 0.1 [get_ports {BA[*]}]
|
||||
#set_output_delay -max -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] 0.2 [get_ports {BA[*]}]
|
||||
|
||||
#set_output_delay -min -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] 0.1 [get_ports {VD[*]}]
|
||||
#set_output_delay -max -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] 0.2 [get_ports {VD[*]}]
|
||||
#set_input_delay -min -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] 0.1 [get_ports {VD[*]}]
|
||||
#set_input_delay -max -clock [get_clocks {i_ddr_clk_pll|altpll_component|auto_generated|pll1|clk[0]}] 0.2 [get_ports {VD[*]}]
|
||||
|
||||
@@ -1,23 +0,0 @@
|
||||
# Copyright (C) 1991-2008 Altera Corporation
|
||||
# Your use of Altera Corporation's design tools, logic functions
|
||||
# and other software and tools, and its AMPP partner logic
|
||||
# functions, and any output files from any of the foregoing
|
||||
# (including device programming or simulation files), and any
|
||||
# associated documentation or information are expressly subject
|
||||
# to the terms and conditions of the Altera Program License
|
||||
# Subscription Agreement, Altera MegaCore Function License
|
||||
# Agreement, or other applicable license agreement, including,
|
||||
# without limitation, that your use is for the sole purpose of
|
||||
# programming logic devices manufactured by Altera and sold by
|
||||
# Altera or its authorized distributors. Please refer to the
|
||||
# applicable agreement for further details.
|
||||
|
||||
|
||||
|
||||
QUARTUS_VERSION = "8.1"
|
||||
DATE = "10:07:29 September 03, 2009"
|
||||
|
||||
|
||||
# Revisions
|
||||
|
||||
PROJECT_REVISION = "firebee1"
|
||||
@@ -1,27 +0,0 @@
|
||||
[ProjectWorkspace]
|
||||
ptn_Child1=Frames
|
||||
[ProjectWorkspace.Frames]
|
||||
ptn_Child1=ChildFrames
|
||||
[ProjectWorkspace.Frames.ChildFrames]
|
||||
ptn_Child1=Document-0
|
||||
ptn_Child2=Document-1
|
||||
ptn_Child3=Document-2
|
||||
ptn_Child4=Document-3
|
||||
[ProjectWorkspace.Frames.ChildFrames.Document-0]
|
||||
ptn_Child1=ViewFrame-0
|
||||
[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0]
|
||||
DocPathName=firebee1.bdf
|
||||
DocumentCLSID={7b19e8f2-2bbe-11d1-a082-0020affa5bde}
|
||||
IsChildFrameDetached=False
|
||||
IsActiveChildFrame=False
|
||||
ptn_Child1=StateMap
|
||||
[ProjectWorkspace.Frames.ChildFrames.Document-1]
|
||||
ptn_Child1=ViewFrame-0
|
||||
[ProjectWorkspace.Frames.ChildFrames.Document-1.ViewFrame-0]
|
||||
DocPathName=FalconIO_SDCard_IDE_CF/FalconIO_SDCard_IDE_CF.vhd
|
||||
DocumentCLSID={ca385d57-a4c7-11d1-a098-0020affa43f2}
|
||||
IsChildFrameDetached=False
|
||||
IsActiveChildFrame=False
|
||||
ptn_Child1=StateMap
|
||||
[ProjectWorkspace.Frames.ChildFrames.Document-1.ViewFrame-0.StateMap]
|
||||
AFC_IN_REPORT=False
|
||||
Reference in New Issue
Block a user