fix formatting

FPGA_Quartus_13.1/Video/DDR_CTR.vhd

@@ -242,27 +242,37 @@ ARCHITECTURE rtl OF ddr_ctr IS
 -- Sub Module Interface Section
 
 
-   component lpm_bustri_BYT
+    COMPONENT lpm_bustri_BYT
-      Port (
+        PORT
-	 data: in std_logic_vector(7 DOWNTO 0);
+        (
-	 enabledt: in std_logic;
+            data        : IN std_logic_vector(7 DOWNTO 0);
-	 tridata: buffer std_logic_vector(7 DOWNTO 0)
+            enabledt    : IN std_logic;
+            tridata     : BUFFER std_logic_vector(7 DOWNTO 0)
         );
-   END component;
+    END COMPONENT lpm_bustri_BYT;
 
-   Function to_std_logic(X: in Boolean) return Std_Logic IS
+    FUNCTION to_std_logic(X : IN boolean) RETURN std_logic IS
         VARIABLE ret : std_logic;
     BEGIN
-   IF x THEN ret := '1';  ELSE ret := '0'; END IF;
+        IF x THEN
-   return ret;
+            ret := '1';
+        ELSE
+            ret := '0';
+        END IF;
+        RETURN ret;
     END to_std_logic;
 
 
     -- sizeIt replicates a value to an array of specific length.
-   Function sizeIt(a: std_Logic; len: integer) return std_logic_vector IS
+    FUNCTION sizeit(a: std_logic; len: integer) RETURN std_logic_vector IS
-      VARIABLE rep: std_logic_vector( len-1 DOWNTO 0);
+        VARIABLE rep: std_logic_vector(len - 1 DOWNTO 0);
-   BEGIN for i in rep'range loop rep(i) := a;  END loop; return rep;
+    BEGIN
+        FOR i IN rep'RANGE LOOP
+            rep(i) := a;
+        END LOOP;
+        RETURN rep;
     END sizeIt;
+
 BEGIN
 
 -- Sub Module Section